Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Mitsubishi D10V, for GDB. |
349c5d5f | 2 | |
51603483 | 3 | Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software |
349c5d5f | 4 | Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
c906108c SS |
27 | #include "symtab.h" |
28 | #include "gdbtypes.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdb_string.h" | |
32 | #include "value.h" | |
33 | #include "inferior.h" | |
c5aa993b | 34 | #include "dis-asm.h" |
c906108c SS |
35 | #include "symfile.h" |
36 | #include "objfiles.h" | |
104c1213 | 37 | #include "language.h" |
28d069e6 | 38 | #include "arch-utils.h" |
4e052eda | 39 | #include "regcache.h" |
c906108c | 40 | |
f0d4cc9e | 41 | #include "floatformat.h" |
b91b96f4 | 42 | #include "gdb/sim-d10v.h" |
8238d0bf | 43 | #include "sim-regno.h" |
4ce44c66 | 44 | |
fa1fd571 AC |
45 | #include "gdb_assert.h" |
46 | ||
cce74817 | 47 | struct frame_extra_info |
c5aa993b JM |
48 | { |
49 | CORE_ADDR return_pc; | |
50 | int frameless; | |
51 | int size; | |
52 | }; | |
cce74817 | 53 | |
4ce44c66 JM |
54 | struct gdbarch_tdep |
55 | { | |
56 | int a0_regnum; | |
57 | int nr_dmap_regs; | |
58 | unsigned long (*dmap_register) (int nr); | |
59 | unsigned long (*imap_register) (int nr); | |
4ce44c66 JM |
60 | }; |
61 | ||
62 | /* These are the addresses the D10V-EVA board maps data and | |
63 | instruction memory to. */ | |
cce74817 | 64 | |
78eac43e MS |
65 | enum memspace { |
66 | DMEM_START = 0x2000000, | |
67 | IMEM_START = 0x1000000, | |
68 | STACK_START = 0x200bffe | |
69 | }; | |
cce74817 | 70 | |
4ce44c66 JM |
71 | /* d10v register names. */ |
72 | ||
73 | enum | |
74 | { | |
75 | R0_REGNUM = 0, | |
78eac43e MS |
76 | R3_REGNUM = 3, |
77 | _FP_REGNUM = 11, | |
4ce44c66 | 78 | LR_REGNUM = 13, |
78eac43e | 79 | _SP_REGNUM = 15, |
4ce44c66 | 80 | PSW_REGNUM = 16, |
78eac43e | 81 | _PC_REGNUM = 18, |
4ce44c66 | 82 | NR_IMAP_REGS = 2, |
78eac43e MS |
83 | NR_A_REGS = 2, |
84 | TS2_NUM_REGS = 37, | |
85 | TS3_NUM_REGS = 42, | |
86 | /* d10v calling convention. */ | |
87 | ARG1_REGNUM = R0_REGNUM, | |
88 | ARGN_REGNUM = R3_REGNUM, | |
89 | RET1_REGNUM = R0_REGNUM, | |
4ce44c66 | 90 | }; |
78eac43e | 91 | |
4ce44c66 JM |
92 | #define NR_DMAP_REGS (gdbarch_tdep (current_gdbarch)->nr_dmap_regs) |
93 | #define A0_REGNUM (gdbarch_tdep (current_gdbarch)->a0_regnum) | |
94 | ||
392a587b JM |
95 | /* Local functions */ |
96 | ||
a14ed312 | 97 | extern void _initialize_d10v_tdep (void); |
392a587b | 98 | |
095a4c96 EZ |
99 | static CORE_ADDR d10v_read_sp (void); |
100 | ||
101 | static CORE_ADDR d10v_read_fp (void); | |
102 | ||
a14ed312 | 103 | static void d10v_eva_prepare_to_trace (void); |
392a587b | 104 | |
a14ed312 | 105 | static void d10v_eva_get_trace_data (void); |
c906108c | 106 | |
a14ed312 KB |
107 | static int prologue_find_regs (unsigned short op, struct frame_info *fi, |
108 | CORE_ADDR addr); | |
cce74817 | 109 | |
f5e1cf12 | 110 | static void d10v_frame_init_saved_regs (struct frame_info *); |
cce74817 | 111 | |
a14ed312 | 112 | static void do_d10v_pop_frame (struct frame_info *fi); |
cce74817 | 113 | |
f5e1cf12 | 114 | static int |
72623009 | 115 | d10v_frame_chain_valid (CORE_ADDR chain, struct frame_info *frame) |
c906108c | 116 | { |
51603483 | 117 | return (get_frame_pc (frame) > IMEM_START); |
c906108c SS |
118 | } |
119 | ||
23964bcd | 120 | static CORE_ADDR |
489137c0 AC |
121 | d10v_stack_align (CORE_ADDR len) |
122 | { | |
123 | return (len + 1) & ~1; | |
124 | } | |
c906108c SS |
125 | |
126 | /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of | |
127 | EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc | |
128 | and TYPE is the type (which is known to be struct, union or array). | |
129 | ||
130 | The d10v returns anything less than 8 bytes in size in | |
131 | registers. */ | |
132 | ||
f5e1cf12 | 133 | static int |
fba45db2 | 134 | d10v_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 135 | { |
02da6206 JSC |
136 | long alignment; |
137 | int i; | |
138 | /* The d10v only passes a struct in a register when that structure | |
139 | has an alignment that matches the size of a register. */ | |
140 | /* If the structure doesn't fit in 4 registers, put it on the | |
141 | stack. */ | |
142 | if (TYPE_LENGTH (type) > 8) | |
143 | return 1; | |
144 | /* If the struct contains only one field, don't put it on the stack | |
145 | - gcc can fit it in one or more registers. */ | |
146 | if (TYPE_NFIELDS (type) == 1) | |
147 | return 0; | |
148 | alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); | |
149 | for (i = 1; i < TYPE_NFIELDS (type); i++) | |
150 | { | |
151 | /* If the alignment changes, just assume it goes on the | |
152 | stack. */ | |
153 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) | |
154 | return 1; | |
155 | } | |
156 | /* If the alignment is suitable for the d10v's 16 bit registers, | |
157 | don't put it on the stack. */ | |
158 | if (alignment == 2 || alignment == 4) | |
159 | return 0; | |
160 | return 1; | |
c906108c SS |
161 | } |
162 | ||
163 | ||
f4f9705a | 164 | static const unsigned char * |
fba45db2 | 165 | d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
392a587b | 166 | { |
c5aa993b JM |
167 | static unsigned char breakpoint[] = |
168 | {0x2f, 0x90, 0x5e, 0x00}; | |
392a587b JM |
169 | *lenptr = sizeof (breakpoint); |
170 | return breakpoint; | |
171 | } | |
172 | ||
4ce44c66 JM |
173 | /* Map the REG_NR onto an ascii name. Return NULL or an empty string |
174 | when the reg_nr isn't valid. */ | |
175 | ||
176 | enum ts2_regnums | |
177 | { | |
178 | TS2_IMAP0_REGNUM = 32, | |
179 | TS2_DMAP_REGNUM = 34, | |
180 | TS2_NR_DMAP_REGS = 1, | |
181 | TS2_A0_REGNUM = 35 | |
182 | }; | |
183 | ||
fa88f677 | 184 | static const char * |
4ce44c66 | 185 | d10v_ts2_register_name (int reg_nr) |
392a587b | 186 | { |
c5aa993b JM |
187 | static char *register_names[] = |
188 | { | |
189 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
190 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
191 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
192 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
193 | "imap0", "imap1", "dmap", "a0", "a1" | |
392a587b JM |
194 | }; |
195 | if (reg_nr < 0) | |
196 | return NULL; | |
197 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
198 | return NULL; | |
c5aa993b | 199 | return register_names[reg_nr]; |
392a587b JM |
200 | } |
201 | ||
4ce44c66 JM |
202 | enum ts3_regnums |
203 | { | |
204 | TS3_IMAP0_REGNUM = 36, | |
205 | TS3_DMAP0_REGNUM = 38, | |
206 | TS3_NR_DMAP_REGS = 4, | |
207 | TS3_A0_REGNUM = 32 | |
208 | }; | |
209 | ||
fa88f677 | 210 | static const char * |
4ce44c66 JM |
211 | d10v_ts3_register_name (int reg_nr) |
212 | { | |
213 | static char *register_names[] = | |
214 | { | |
215 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
216 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
217 | "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", | |
218 | "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", | |
219 | "a0", "a1", | |
220 | "spi", "spu", | |
221 | "imap0", "imap1", | |
222 | "dmap0", "dmap1", "dmap2", "dmap3" | |
223 | }; | |
224 | if (reg_nr < 0) | |
225 | return NULL; | |
226 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
227 | return NULL; | |
228 | return register_names[reg_nr]; | |
229 | } | |
230 | ||
bf93dfed JB |
231 | /* Access the DMAP/IMAP registers in a target independent way. |
232 | ||
233 | Divide the D10V's 64k data space into four 16k segments: | |
234 | 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and | |
235 | 0xc000 -- 0xffff. | |
236 | ||
237 | On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- | |
238 | 0x7fff) always map to the on-chip data RAM, and the fourth always | |
239 | maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into | |
240 | unified memory or instruction memory, under the control of the | |
241 | single DMAP register. | |
242 | ||
243 | On the TS3, there are four DMAP registers, each of which controls | |
244 | one of the segments. */ | |
4ce44c66 JM |
245 | |
246 | static unsigned long | |
247 | d10v_ts2_dmap_register (int reg_nr) | |
248 | { | |
249 | switch (reg_nr) | |
250 | { | |
251 | case 0: | |
252 | case 1: | |
253 | return 0x2000; | |
254 | case 2: | |
255 | return read_register (TS2_DMAP_REGNUM); | |
256 | default: | |
257 | return 0; | |
258 | } | |
259 | } | |
260 | ||
261 | static unsigned long | |
262 | d10v_ts3_dmap_register (int reg_nr) | |
263 | { | |
264 | return read_register (TS3_DMAP0_REGNUM + reg_nr); | |
265 | } | |
266 | ||
267 | static unsigned long | |
268 | d10v_dmap_register (int reg_nr) | |
269 | { | |
270 | return gdbarch_tdep (current_gdbarch)->dmap_register (reg_nr); | |
271 | } | |
272 | ||
273 | static unsigned long | |
274 | d10v_ts2_imap_register (int reg_nr) | |
275 | { | |
276 | return read_register (TS2_IMAP0_REGNUM + reg_nr); | |
277 | } | |
278 | ||
279 | static unsigned long | |
280 | d10v_ts3_imap_register (int reg_nr) | |
281 | { | |
282 | return read_register (TS3_IMAP0_REGNUM + reg_nr); | |
283 | } | |
284 | ||
285 | static unsigned long | |
286 | d10v_imap_register (int reg_nr) | |
287 | { | |
288 | return gdbarch_tdep (current_gdbarch)->imap_register (reg_nr); | |
289 | } | |
290 | ||
291 | /* MAP GDB's internal register numbering (determined by the layout fo | |
292 | the REGISTER_BYTE array) onto the simulator's register | |
293 | numbering. */ | |
294 | ||
295 | static int | |
296 | d10v_ts2_register_sim_regno (int nr) | |
297 | { | |
8238d0bf AC |
298 | if (legacy_register_sim_regno (nr) < 0) |
299 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
300 | if (nr >= TS2_IMAP0_REGNUM |
301 | && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) | |
302 | return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
303 | if (nr == TS2_DMAP_REGNUM) | |
304 | return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; | |
305 | if (nr >= TS2_A0_REGNUM | |
306 | && nr < TS2_A0_REGNUM + NR_A_REGS) | |
307 | return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
308 | return nr; | |
309 | } | |
310 | ||
311 | static int | |
312 | d10v_ts3_register_sim_regno (int nr) | |
313 | { | |
8238d0bf AC |
314 | if (legacy_register_sim_regno (nr) < 0) |
315 | return legacy_register_sim_regno (nr); | |
4ce44c66 JM |
316 | if (nr >= TS3_IMAP0_REGNUM |
317 | && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) | |
318 | return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; | |
319 | if (nr >= TS3_DMAP0_REGNUM | |
320 | && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) | |
321 | return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; | |
322 | if (nr >= TS3_A0_REGNUM | |
323 | && nr < TS3_A0_REGNUM + NR_A_REGS) | |
324 | return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; | |
325 | return nr; | |
326 | } | |
327 | ||
392a587b JM |
328 | /* Index within `registers' of the first byte of the space for |
329 | register REG_NR. */ | |
330 | ||
f5e1cf12 | 331 | static int |
fba45db2 | 332 | d10v_register_byte (int reg_nr) |
392a587b | 333 | { |
4ce44c66 | 334 | if (reg_nr < A0_REGNUM) |
392a587b | 335 | return (reg_nr * 2); |
4ce44c66 JM |
336 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) |
337 | return (A0_REGNUM * 2 | |
338 | + (reg_nr - A0_REGNUM) * 8); | |
339 | else | |
340 | return (A0_REGNUM * 2 | |
341 | + NR_A_REGS * 8 | |
342 | + (reg_nr - A0_REGNUM - NR_A_REGS) * 2); | |
392a587b JM |
343 | } |
344 | ||
345 | /* Number of bytes of storage in the actual machine representation for | |
346 | register REG_NR. */ | |
347 | ||
f5e1cf12 | 348 | static int |
fba45db2 | 349 | d10v_register_raw_size (int reg_nr) |
392a587b | 350 | { |
4ce44c66 JM |
351 | if (reg_nr < A0_REGNUM) |
352 | return 2; | |
353 | else if (reg_nr < (A0_REGNUM + NR_A_REGS)) | |
392a587b JM |
354 | return 8; |
355 | else | |
356 | return 2; | |
357 | } | |
358 | ||
392a587b JM |
359 | /* Return the GDB type object for the "standard" data type |
360 | of data in register N. */ | |
361 | ||
f5e1cf12 | 362 | static struct type * |
fba45db2 | 363 | d10v_register_virtual_type (int reg_nr) |
392a587b | 364 | { |
75af7f68 JB |
365 | if (reg_nr == PC_REGNUM) |
366 | return builtin_type_void_func_ptr; | |
095a4c96 EZ |
367 | if (reg_nr == _SP_REGNUM || reg_nr == _FP_REGNUM) |
368 | return builtin_type_void_data_ptr; | |
75af7f68 | 369 | else if (reg_nr >= A0_REGNUM |
4ce44c66 JM |
370 | && reg_nr < (A0_REGNUM + NR_A_REGS)) |
371 | return builtin_type_int64; | |
392a587b | 372 | else |
4ce44c66 | 373 | return builtin_type_int16; |
392a587b JM |
374 | } |
375 | ||
f5e1cf12 | 376 | static int |
fba45db2 | 377 | d10v_daddr_p (CORE_ADDR x) |
392a587b JM |
378 | { |
379 | return (((x) & 0x3000000) == DMEM_START); | |
380 | } | |
381 | ||
f5e1cf12 | 382 | static int |
fba45db2 | 383 | d10v_iaddr_p (CORE_ADDR x) |
392a587b JM |
384 | { |
385 | return (((x) & 0x3000000) == IMEM_START); | |
386 | } | |
387 | ||
169a7369 MS |
388 | static CORE_ADDR |
389 | d10v_make_daddr (CORE_ADDR x) | |
390 | { | |
391 | return ((x) | DMEM_START); | |
392 | } | |
393 | ||
394 | static CORE_ADDR | |
395 | d10v_make_iaddr (CORE_ADDR x) | |
396 | { | |
397 | if (d10v_iaddr_p (x)) | |
398 | return x; /* Idempotency -- x is already in the IMEM space. */ | |
399 | else | |
400 | return (((x) << 2) | IMEM_START); | |
401 | } | |
392a587b | 402 | |
f5e1cf12 | 403 | static CORE_ADDR |
fba45db2 | 404 | d10v_convert_iaddr_to_raw (CORE_ADDR x) |
392a587b JM |
405 | { |
406 | return (((x) >> 2) & 0xffff); | |
407 | } | |
408 | ||
f5e1cf12 | 409 | static CORE_ADDR |
fba45db2 | 410 | d10v_convert_daddr_to_raw (CORE_ADDR x) |
392a587b JM |
411 | { |
412 | return ((x) & 0xffff); | |
413 | } | |
414 | ||
75af7f68 JB |
415 | static void |
416 | d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) | |
417 | { | |
418 | /* Is it a code address? */ | |
419 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
420 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) | |
421 | { | |
75af7f68 JB |
422 | store_unsigned_integer (buf, TYPE_LENGTH (type), |
423 | d10v_convert_iaddr_to_raw (addr)); | |
424 | } | |
425 | else | |
426 | { | |
427 | /* Strip off any upper segment bits. */ | |
428 | store_unsigned_integer (buf, TYPE_LENGTH (type), | |
429 | d10v_convert_daddr_to_raw (addr)); | |
430 | } | |
431 | } | |
432 | ||
433 | static CORE_ADDR | |
66140c26 | 434 | d10v_pointer_to_address (struct type *type, const void *buf) |
75af7f68 JB |
435 | { |
436 | CORE_ADDR addr = extract_address (buf, TYPE_LENGTH (type)); | |
437 | ||
438 | /* Is it a code address? */ | |
439 | if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC | |
74a9bb82 FF |
440 | || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD |
441 | || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) | |
75af7f68 JB |
442 | return d10v_make_iaddr (addr); |
443 | else | |
444 | return d10v_make_daddr (addr); | |
445 | } | |
446 | ||
095a4c96 EZ |
447 | /* Don't do anything if we have an integer, this way users can type 'x |
448 | <addr>' w/o having gdb outsmart them. The internal gdb conversions | |
449 | to the correct space are taken care of in the pointer_to_address | |
450 | function. If we don't do this, 'x $fp' wouldn't work. */ | |
fc0c74b1 AC |
451 | static CORE_ADDR |
452 | d10v_integer_to_address (struct type *type, void *buf) | |
453 | { | |
454 | LONGEST val; | |
455 | val = unpack_long (type, buf); | |
095a4c96 | 456 | return val; |
fc0c74b1 | 457 | } |
75af7f68 | 458 | |
392a587b JM |
459 | /* Store the address of the place in which to copy the structure the |
460 | subroutine will return. This is called from call_function. | |
461 | ||
462 | We store structs through a pointer passed in the first Argument | |
463 | register. */ | |
464 | ||
f5e1cf12 | 465 | static void |
fba45db2 | 466 | d10v_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
392a587b JM |
467 | { |
468 | write_register (ARG1_REGNUM, (addr)); | |
469 | } | |
470 | ||
471 | /* Write into appropriate registers a function return value | |
472 | of type TYPE, given in virtual format. | |
473 | ||
474 | Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ | |
475 | ||
f5e1cf12 | 476 | static void |
fa1fd571 AC |
477 | d10v_store_return_value (struct type *type, struct regcache *regcache, |
478 | const void *valbuf) | |
392a587b | 479 | { |
fa1fd571 AC |
480 | /* Only char return values need to be shifted right within the first |
481 | regnum. */ | |
3d79a47c MS |
482 | if (TYPE_LENGTH (type) == 1 |
483 | && TYPE_CODE (type) == TYPE_CODE_INT) | |
484 | { | |
fa1fd571 AC |
485 | bfd_byte tmp[2]; |
486 | tmp[1] = *(bfd_byte *)valbuf; | |
487 | regcache_cooked_write (regcache, RET1_REGNUM, tmp); | |
3d79a47c MS |
488 | } |
489 | else | |
fa1fd571 AC |
490 | { |
491 | int reg; | |
492 | /* A structure is never more than 8 bytes long. See | |
493 | use_struct_convention(). */ | |
494 | gdb_assert (TYPE_LENGTH (type) <= 8); | |
495 | /* Write out most registers, stop loop before trying to write | |
496 | out any dangling byte at the end of the buffer. */ | |
497 | for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) | |
498 | { | |
499 | regcache_cooked_write (regcache, RET1_REGNUM + reg, | |
500 | (bfd_byte *) valbuf + reg * 2); | |
501 | } | |
502 | /* Write out any dangling byte at the end of the buffer. */ | |
503 | if ((reg * 2) + 1 == TYPE_LENGTH (type)) | |
504 | regcache_cooked_write_part (regcache, reg, 0, 1, | |
505 | (bfd_byte *) valbuf + reg * 2); | |
506 | } | |
392a587b JM |
507 | } |
508 | ||
509 | /* Extract from an array REGBUF containing the (raw) register state | |
510 | the address in which a function should return its structure value, | |
511 | as a CORE_ADDR (or an expression that can be used as one). */ | |
512 | ||
f5e1cf12 | 513 | static CORE_ADDR |
fa1fd571 | 514 | d10v_extract_struct_value_address (struct regcache *regcache) |
392a587b | 515 | { |
fa1fd571 AC |
516 | ULONGEST addr; |
517 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); | |
518 | return (addr | DMEM_START); | |
392a587b JM |
519 | } |
520 | ||
f5e1cf12 | 521 | static CORE_ADDR |
fba45db2 | 522 | d10v_frame_saved_pc (struct frame_info *frame) |
392a587b | 523 | { |
1e2330ba AC |
524 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
525 | get_frame_base (frame), | |
526 | get_frame_base (frame))) | |
50abf9e5 | 527 | return d10v_make_iaddr (deprecated_read_register_dummy (get_frame_pc (frame), |
1e2330ba | 528 | get_frame_base (frame), |
135c175f | 529 | PC_REGNUM)); |
78eac43e | 530 | else |
da50a4b7 | 531 | return (get_frame_extra_info (frame)->return_pc); |
392a587b JM |
532 | } |
533 | ||
392a587b JM |
534 | /* Immediately after a function call, return the saved pc. We can't |
535 | use frame->return_pc beause that is determined by reading R13 off | |
536 | the stack and that may not be written yet. */ | |
537 | ||
f5e1cf12 | 538 | static CORE_ADDR |
fba45db2 | 539 | d10v_saved_pc_after_call (struct frame_info *frame) |
392a587b | 540 | { |
c5aa993b | 541 | return ((read_register (LR_REGNUM) << 2) |
392a587b JM |
542 | | IMEM_START); |
543 | } | |
544 | ||
c906108c SS |
545 | /* Discard from the stack the innermost frame, restoring all saved |
546 | registers. */ | |
547 | ||
f5e1cf12 | 548 | static void |
fba45db2 | 549 | d10v_pop_frame (void) |
cce74817 JM |
550 | { |
551 | generic_pop_current_frame (do_d10v_pop_frame); | |
552 | } | |
553 | ||
554 | static void | |
fba45db2 | 555 | do_d10v_pop_frame (struct frame_info *fi) |
c906108c SS |
556 | { |
557 | CORE_ADDR fp; | |
558 | int regnum; | |
c906108c SS |
559 | char raw_buffer[8]; |
560 | ||
c193f6ac | 561 | fp = get_frame_base (fi); |
c906108c SS |
562 | /* fill out fsr with the address of where each */ |
563 | /* register was stored in the frame */ | |
cce74817 | 564 | d10v_frame_init_saved_regs (fi); |
c5aa993b | 565 | |
c906108c | 566 | /* now update the current registers with the old values */ |
4ce44c66 | 567 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + NR_A_REGS; regnum++) |
c906108c | 568 | { |
b2fb4676 | 569 | if (get_frame_saved_regs (fi)[regnum]) |
c906108c | 570 | { |
b2fb4676 | 571 | read_memory (get_frame_saved_regs (fi)[regnum], raw_buffer, REGISTER_RAW_SIZE (regnum)); |
73937e03 AC |
572 | deprecated_write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, |
573 | REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
574 | } |
575 | } | |
576 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
577 | { | |
b2fb4676 | 578 | if (get_frame_saved_regs (fi)[regnum]) |
c906108c | 579 | { |
b2fb4676 | 580 | write_register (regnum, read_memory_unsigned_integer (get_frame_saved_regs (fi)[regnum], REGISTER_RAW_SIZE (regnum))); |
c906108c SS |
581 | } |
582 | } | |
b2fb4676 | 583 | if (get_frame_saved_regs (fi)[PSW_REGNUM]) |
c906108c | 584 | { |
b2fb4676 | 585 | write_register (PSW_REGNUM, read_memory_unsigned_integer (get_frame_saved_regs (fi)[PSW_REGNUM], REGISTER_RAW_SIZE (PSW_REGNUM))); |
c906108c SS |
586 | } |
587 | ||
588 | write_register (PC_REGNUM, read_register (LR_REGNUM)); | |
da50a4b7 | 589 | write_register (SP_REGNUM, fp + get_frame_extra_info (fi)->size); |
c906108c SS |
590 | target_store_registers (-1); |
591 | flush_cached_frames (); | |
592 | } | |
593 | ||
c5aa993b | 594 | static int |
fba45db2 | 595 | check_prologue (unsigned short op) |
c906108c SS |
596 | { |
597 | /* st rn, @-sp */ | |
598 | if ((op & 0x7E1F) == 0x6C1F) | |
599 | return 1; | |
600 | ||
601 | /* st2w rn, @-sp */ | |
602 | if ((op & 0x7E3F) == 0x6E1F) | |
603 | return 1; | |
604 | ||
605 | /* subi sp, n */ | |
606 | if ((op & 0x7FE1) == 0x01E1) | |
607 | return 1; | |
608 | ||
609 | /* mv r11, sp */ | |
610 | if (op == 0x417E) | |
611 | return 1; | |
612 | ||
613 | /* nop */ | |
614 | if (op == 0x5E00) | |
615 | return 1; | |
616 | ||
617 | /* st rn, @sp */ | |
618 | if ((op & 0x7E1F) == 0x681E) | |
619 | return 1; | |
620 | ||
621 | /* st2w rn, @sp */ | |
c5aa993b JM |
622 | if ((op & 0x7E3F) == 0x3A1E) |
623 | return 1; | |
c906108c SS |
624 | |
625 | return 0; | |
626 | } | |
627 | ||
f5e1cf12 | 628 | static CORE_ADDR |
fba45db2 | 629 | d10v_skip_prologue (CORE_ADDR pc) |
c906108c SS |
630 | { |
631 | unsigned long op; | |
632 | unsigned short op1, op2; | |
633 | CORE_ADDR func_addr, func_end; | |
634 | struct symtab_and_line sal; | |
635 | ||
636 | /* If we have line debugging information, then the end of the */ | |
637 | /* prologue should the first assembly instruction of the first source line */ | |
638 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
639 | { | |
640 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 641 | if (sal.end && sal.end < func_end) |
c906108c SS |
642 | return sal.end; |
643 | } | |
c5aa993b JM |
644 | |
645 | if (target_read_memory (pc, (char *) &op, 4)) | |
c906108c SS |
646 | return pc; /* Can't access it -- assume no prologue. */ |
647 | ||
648 | while (1) | |
649 | { | |
c5aa993b | 650 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
651 | if ((op & 0xC0000000) == 0xC0000000) |
652 | { | |
653 | /* long instruction */ | |
c5aa993b JM |
654 | if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ |
655 | ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ | |
656 | ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ | |
c906108c SS |
657 | break; |
658 | } | |
659 | else | |
660 | { | |
661 | /* short instructions */ | |
662 | if ((op & 0xC0000000) == 0x80000000) | |
663 | { | |
664 | op2 = (op & 0x3FFF8000) >> 15; | |
665 | op1 = op & 0x7FFF; | |
c5aa993b JM |
666 | } |
667 | else | |
c906108c SS |
668 | { |
669 | op1 = (op & 0x3FFF8000) >> 15; | |
670 | op2 = op & 0x7FFF; | |
671 | } | |
c5aa993b | 672 | if (check_prologue (op1)) |
c906108c | 673 | { |
c5aa993b | 674 | if (!check_prologue (op2)) |
c906108c SS |
675 | { |
676 | /* if the previous opcode was really part of the prologue */ | |
677 | /* and not just a NOP, then we want to break after both instructions */ | |
678 | if (op1 != 0x5E00) | |
679 | pc += 4; | |
680 | break; | |
681 | } | |
682 | } | |
683 | else | |
684 | break; | |
685 | } | |
686 | pc += 4; | |
687 | } | |
688 | return pc; | |
689 | } | |
690 | ||
a5afb99f AC |
691 | /* Given a GDB frame, determine the address of the calling function's |
692 | frame. This will be used to create a new GDB frame struct, and | |
693 | then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be | |
694 | called for the new frame. */ | |
c906108c | 695 | |
f5e1cf12 | 696 | static CORE_ADDR |
fba45db2 | 697 | d10v_frame_chain (struct frame_info *fi) |
c906108c | 698 | { |
78eac43e MS |
699 | CORE_ADDR addr; |
700 | ||
701 | /* A generic call dummy's frame is the same as caller's. */ | |
1e2330ba AC |
702 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
703 | get_frame_base (fi))) | |
704 | return get_frame_base (fi); | |
78eac43e | 705 | |
cce74817 | 706 | d10v_frame_init_saved_regs (fi); |
c906108c | 707 | |
78eac43e | 708 | |
da50a4b7 AC |
709 | if (get_frame_extra_info (fi)->return_pc == IMEM_START |
710 | || inside_entry_file (get_frame_extra_info (fi)->return_pc)) | |
78eac43e MS |
711 | { |
712 | /* This is meant to halt the backtrace at "_start". | |
713 | Make sure we don't halt it at a generic dummy frame. */ | |
da50a4b7 | 714 | if (!DEPRECATED_PC_IN_CALL_DUMMY (get_frame_extra_info (fi)->return_pc, 0, 0)) |
78eac43e MS |
715 | return (CORE_ADDR) 0; |
716 | } | |
c906108c | 717 | |
b2fb4676 | 718 | if (!get_frame_saved_regs (fi)[FP_REGNUM]) |
c906108c | 719 | { |
b2fb4676 AC |
720 | if (!get_frame_saved_regs (fi)[SP_REGNUM] |
721 | || get_frame_saved_regs (fi)[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
722 | return (CORE_ADDR) 0; |
723 | ||
b2fb4676 | 724 | return get_frame_saved_regs (fi)[SP_REGNUM]; |
c906108c SS |
725 | } |
726 | ||
b2fb4676 | 727 | addr = read_memory_unsigned_integer (get_frame_saved_regs (fi)[FP_REGNUM], |
78eac43e MS |
728 | REGISTER_RAW_SIZE (FP_REGNUM)); |
729 | if (addr == 0) | |
c5aa993b | 730 | return (CORE_ADDR) 0; |
c906108c | 731 | |
78eac43e | 732 | return d10v_make_daddr (addr); |
c5aa993b | 733 | } |
c906108c SS |
734 | |
735 | static int next_addr, uses_frame; | |
736 | ||
c5aa993b | 737 | static int |
fba45db2 | 738 | prologue_find_regs (unsigned short op, struct frame_info *fi, CORE_ADDR addr) |
c906108c SS |
739 | { |
740 | int n; | |
741 | ||
742 | /* st rn, @-sp */ | |
743 | if ((op & 0x7E1F) == 0x6C1F) | |
744 | { | |
745 | n = (op & 0x1E0) >> 5; | |
746 | next_addr -= 2; | |
b2fb4676 | 747 | get_frame_saved_regs (fi)[n] = next_addr; |
c906108c SS |
748 | return 1; |
749 | } | |
750 | ||
751 | /* st2w rn, @-sp */ | |
752 | else if ((op & 0x7E3F) == 0x6E1F) | |
753 | { | |
754 | n = (op & 0x1E0) >> 5; | |
755 | next_addr -= 4; | |
b2fb4676 AC |
756 | get_frame_saved_regs (fi)[n] = next_addr; |
757 | get_frame_saved_regs (fi)[n + 1] = next_addr + 2; | |
c906108c SS |
758 | return 1; |
759 | } | |
760 | ||
761 | /* subi sp, n */ | |
762 | if ((op & 0x7FE1) == 0x01E1) | |
763 | { | |
764 | n = (op & 0x1E) >> 1; | |
765 | if (n == 0) | |
766 | n = 16; | |
767 | next_addr -= n; | |
768 | return 1; | |
769 | } | |
770 | ||
771 | /* mv r11, sp */ | |
772 | if (op == 0x417E) | |
773 | { | |
774 | uses_frame = 1; | |
775 | return 1; | |
776 | } | |
777 | ||
778 | /* nop */ | |
779 | if (op == 0x5E00) | |
780 | return 1; | |
781 | ||
782 | /* st rn, @sp */ | |
783 | if ((op & 0x7E1F) == 0x681E) | |
784 | { | |
785 | n = (op & 0x1E0) >> 5; | |
b2fb4676 | 786 | get_frame_saved_regs (fi)[n] = next_addr; |
c906108c SS |
787 | return 1; |
788 | } | |
789 | ||
790 | /* st2w rn, @sp */ | |
791 | if ((op & 0x7E3F) == 0x3A1E) | |
792 | { | |
793 | n = (op & 0x1E0) >> 5; | |
b2fb4676 AC |
794 | get_frame_saved_regs (fi)[n] = next_addr; |
795 | get_frame_saved_regs (fi)[n + 1] = next_addr + 2; | |
c906108c SS |
796 | return 1; |
797 | } | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
cce74817 JM |
802 | /* Put here the code to store, into fi->saved_regs, the addresses of |
803 | the saved registers of frame described by FRAME_INFO. This | |
804 | includes special registers such as pc and fp saved in special ways | |
805 | in the stack frame. sp is even more special: the address we return | |
806 | for it IS the sp for the next frame. */ | |
807 | ||
f5e1cf12 | 808 | static void |
fba45db2 | 809 | d10v_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
810 | { |
811 | CORE_ADDR fp, pc; | |
812 | unsigned long op; | |
813 | unsigned short op1, op2; | |
814 | int i; | |
815 | ||
1e2330ba | 816 | fp = get_frame_base (fi); |
b2fb4676 | 817 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
818 | next_addr = 0; |
819 | ||
50abf9e5 | 820 | pc = get_pc_function_start (get_frame_pc (fi)); |
c906108c SS |
821 | |
822 | uses_frame = 0; | |
823 | while (1) | |
824 | { | |
c5aa993b | 825 | op = (unsigned long) read_memory_integer (pc, 4); |
c906108c SS |
826 | if ((op & 0xC0000000) == 0xC0000000) |
827 | { | |
828 | /* long instruction */ | |
829 | if ((op & 0x3FFF0000) == 0x01FF0000) | |
830 | { | |
831 | /* add3 sp,sp,n */ | |
832 | short n = op & 0xFFFF; | |
833 | next_addr += n; | |
834 | } | |
835 | else if ((op & 0x3F0F0000) == 0x340F0000) | |
836 | { | |
837 | /* st rn, @(offset,sp) */ | |
838 | short offset = op & 0xFFFF; | |
839 | short n = (op >> 20) & 0xF; | |
b2fb4676 | 840 | get_frame_saved_regs (fi)[n] = next_addr + offset; |
c906108c SS |
841 | } |
842 | else if ((op & 0x3F1F0000) == 0x350F0000) | |
843 | { | |
844 | /* st2w rn, @(offset,sp) */ | |
845 | short offset = op & 0xFFFF; | |
846 | short n = (op >> 20) & 0xF; | |
b2fb4676 AC |
847 | get_frame_saved_regs (fi)[n] = next_addr + offset; |
848 | get_frame_saved_regs (fi)[n + 1] = next_addr + offset + 2; | |
c906108c SS |
849 | } |
850 | else | |
851 | break; | |
852 | } | |
853 | else | |
854 | { | |
855 | /* short instructions */ | |
856 | if ((op & 0xC0000000) == 0x80000000) | |
857 | { | |
858 | op2 = (op & 0x3FFF8000) >> 15; | |
859 | op1 = op & 0x7FFF; | |
c5aa993b JM |
860 | } |
861 | else | |
c906108c SS |
862 | { |
863 | op1 = (op & 0x3FFF8000) >> 15; | |
864 | op2 = op & 0x7FFF; | |
865 | } | |
78eac43e MS |
866 | if (!prologue_find_regs (op1, fi, pc) |
867 | || !prologue_find_regs (op2, fi, pc)) | |
c906108c SS |
868 | break; |
869 | } | |
870 | pc += 4; | |
871 | } | |
c5aa993b | 872 | |
da50a4b7 | 873 | get_frame_extra_info (fi)->size = -next_addr; |
c906108c SS |
874 | |
875 | if (!(fp & 0xffff)) | |
095a4c96 | 876 | fp = d10v_read_sp (); |
c906108c | 877 | |
c5aa993b | 878 | for (i = 0; i < NUM_REGS - 1; i++) |
b2fb4676 | 879 | if (get_frame_saved_regs (fi)[i]) |
c906108c | 880 | { |
b2fb4676 | 881 | get_frame_saved_regs (fi)[i] = fp - (next_addr - get_frame_saved_regs (fi)[i]); |
c906108c SS |
882 | } |
883 | ||
b2fb4676 | 884 | if (get_frame_saved_regs (fi)[LR_REGNUM]) |
c906108c | 885 | { |
78eac43e | 886 | CORE_ADDR return_pc |
b2fb4676 | 887 | = read_memory_unsigned_integer (get_frame_saved_regs (fi)[LR_REGNUM], |
78eac43e | 888 | REGISTER_RAW_SIZE (LR_REGNUM)); |
da50a4b7 | 889 | get_frame_extra_info (fi)->return_pc = d10v_make_iaddr (return_pc); |
c906108c SS |
890 | } |
891 | else | |
892 | { | |
da50a4b7 | 893 | get_frame_extra_info (fi)->return_pc = d10v_make_iaddr (read_register (LR_REGNUM)); |
c906108c | 894 | } |
c5aa993b | 895 | |
78eac43e | 896 | /* The SP is not normally (ever?) saved, but check anyway */ |
b2fb4676 | 897 | if (!get_frame_saved_regs (fi)[SP_REGNUM]) |
c906108c SS |
898 | { |
899 | /* if the FP was saved, that means the current FP is valid, */ | |
900 | /* otherwise, it isn't being used, so we use the SP instead */ | |
901 | if (uses_frame) | |
b2fb4676 | 902 | get_frame_saved_regs (fi)[SP_REGNUM] |
da50a4b7 | 903 | = d10v_read_fp () + get_frame_extra_info (fi)->size; |
c906108c SS |
904 | else |
905 | { | |
da50a4b7 AC |
906 | get_frame_saved_regs (fi)[SP_REGNUM] = fp + get_frame_extra_info (fi)->size; |
907 | get_frame_extra_info (fi)->frameless = 1; | |
b2fb4676 | 908 | get_frame_saved_regs (fi)[FP_REGNUM] = 0; |
c906108c SS |
909 | } |
910 | } | |
911 | } | |
912 | ||
f5e1cf12 | 913 | static void |
fba45db2 | 914 | d10v_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 915 | { |
a00a19e9 | 916 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
cce74817 JM |
917 | frame_saved_regs_zalloc (fi); |
918 | ||
da50a4b7 AC |
919 | get_frame_extra_info (fi)->frameless = 0; |
920 | get_frame_extra_info (fi)->size = 0; | |
921 | get_frame_extra_info (fi)->return_pc = 0; | |
c906108c | 922 | |
50abf9e5 | 923 | /* If get_frame_pc (fi) is zero, but this is not the outermost frame, |
78eac43e | 924 | then let's snatch the return_pc from the callee, so that |
ae45cd16 | 925 | DEPRECATED_PC_IN_CALL_DUMMY will work. */ |
aab3ea25 AC |
926 | if (get_frame_pc (fi) == 0 |
927 | && frame_relative_level (fi) != 0 && get_next_frame (fi) != NULL) | |
11c02a10 | 928 | deprecated_update_frame_pc_hack (fi, d10v_frame_saved_pc (get_next_frame (fi))); |
78eac43e | 929 | |
c906108c SS |
930 | /* The call dummy doesn't save any registers on the stack, so we can |
931 | return now. */ | |
1e2330ba AC |
932 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
933 | get_frame_base (fi))) | |
c906108c SS |
934 | { |
935 | return; | |
936 | } | |
937 | else | |
938 | { | |
cce74817 | 939 | d10v_frame_init_saved_regs (fi); |
c906108c SS |
940 | } |
941 | } | |
942 | ||
943 | static void | |
fba45db2 | 944 | show_regs (char *args, int from_tty) |
c906108c SS |
945 | { |
946 | int a; | |
d4f3574e SS |
947 | printf_filtered ("PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", |
948 | (long) read_register (PC_REGNUM), | |
7b570125 | 949 | (long) d10v_make_iaddr (read_register (PC_REGNUM)), |
d4f3574e SS |
950 | (long) read_register (PSW_REGNUM), |
951 | (long) read_register (24), | |
952 | (long) read_register (25), | |
953 | (long) read_register (23)); | |
954 | printf_filtered ("R0-R7 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
955 | (long) read_register (0), | |
956 | (long) read_register (1), | |
957 | (long) read_register (2), | |
958 | (long) read_register (3), | |
959 | (long) read_register (4), | |
960 | (long) read_register (5), | |
961 | (long) read_register (6), | |
962 | (long) read_register (7)); | |
963 | printf_filtered ("R8-R15 %04lx %04lx %04lx %04lx %04lx %04lx %04lx %04lx\n", | |
964 | (long) read_register (8), | |
965 | (long) read_register (9), | |
966 | (long) read_register (10), | |
967 | (long) read_register (11), | |
968 | (long) read_register (12), | |
969 | (long) read_register (13), | |
970 | (long) read_register (14), | |
971 | (long) read_register (15)); | |
4ce44c66 JM |
972 | for (a = 0; a < NR_IMAP_REGS; a++) |
973 | { | |
974 | if (a > 0) | |
975 | printf_filtered (" "); | |
976 | printf_filtered ("IMAP%d %04lx", a, d10v_imap_register (a)); | |
977 | } | |
978 | if (NR_DMAP_REGS == 1) | |
979 | printf_filtered (" DMAP %04lx\n", d10v_dmap_register (2)); | |
980 | else | |
981 | { | |
982 | for (a = 0; a < NR_DMAP_REGS; a++) | |
983 | { | |
984 | printf_filtered (" DMAP%d %04lx", a, d10v_dmap_register (a)); | |
985 | } | |
986 | printf_filtered ("\n"); | |
987 | } | |
988 | printf_filtered ("A0-A%d", NR_A_REGS - 1); | |
989 | for (a = A0_REGNUM; a < A0_REGNUM + NR_A_REGS; a++) | |
c906108c SS |
990 | { |
991 | char num[MAX_REGISTER_RAW_SIZE]; | |
992 | int i; | |
993 | printf_filtered (" "); | |
4caf0990 | 994 | deprecated_read_register_gen (a, (char *) &num); |
c906108c SS |
995 | for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) |
996 | { | |
997 | printf_filtered ("%02x", (num[i] & 0xff)); | |
998 | } | |
999 | } | |
1000 | printf_filtered ("\n"); | |
1001 | } | |
1002 | ||
f5e1cf12 | 1003 | static CORE_ADDR |
39f77062 | 1004 | d10v_read_pc (ptid_t ptid) |
c906108c | 1005 | { |
39f77062 | 1006 | ptid_t save_ptid; |
c906108c SS |
1007 | CORE_ADDR pc; |
1008 | CORE_ADDR retval; | |
1009 | ||
39f77062 KB |
1010 | save_ptid = inferior_ptid; |
1011 | inferior_ptid = ptid; | |
c906108c | 1012 | pc = (int) read_register (PC_REGNUM); |
39f77062 | 1013 | inferior_ptid = save_ptid; |
7b570125 | 1014 | retval = d10v_make_iaddr (pc); |
c906108c SS |
1015 | return retval; |
1016 | } | |
1017 | ||
f5e1cf12 | 1018 | static void |
39f77062 | 1019 | d10v_write_pc (CORE_ADDR val, ptid_t ptid) |
c906108c | 1020 | { |
39f77062 | 1021 | ptid_t save_ptid; |
c906108c | 1022 | |
39f77062 KB |
1023 | save_ptid = inferior_ptid; |
1024 | inferior_ptid = ptid; | |
7b570125 | 1025 | write_register (PC_REGNUM, d10v_convert_iaddr_to_raw (val)); |
39f77062 | 1026 | inferior_ptid = save_ptid; |
c906108c SS |
1027 | } |
1028 | ||
f5e1cf12 | 1029 | static CORE_ADDR |
fba45db2 | 1030 | d10v_read_sp (void) |
c906108c | 1031 | { |
7b570125 | 1032 | return (d10v_make_daddr (read_register (SP_REGNUM))); |
c906108c SS |
1033 | } |
1034 | ||
f5e1cf12 | 1035 | static void |
fba45db2 | 1036 | d10v_write_sp (CORE_ADDR val) |
c906108c | 1037 | { |
7b570125 | 1038 | write_register (SP_REGNUM, d10v_convert_daddr_to_raw (val)); |
c906108c SS |
1039 | } |
1040 | ||
f5e1cf12 | 1041 | static CORE_ADDR |
fba45db2 | 1042 | d10v_read_fp (void) |
c906108c | 1043 | { |
7b570125 | 1044 | return (d10v_make_daddr (read_register (FP_REGNUM))); |
c906108c SS |
1045 | } |
1046 | ||
1047 | /* Function: push_return_address (pc) | |
1048 | Set up the return address for the inferior function call. | |
1049 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
c5aa993b | 1050 | |
f5e1cf12 | 1051 | static CORE_ADDR |
fba45db2 | 1052 | d10v_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 1053 | { |
7b570125 | 1054 | write_register (LR_REGNUM, d10v_convert_iaddr_to_raw (CALL_DUMMY_ADDRESS ())); |
c906108c SS |
1055 | return sp; |
1056 | } | |
c5aa993b | 1057 | |
c906108c | 1058 | |
7a292a7a SS |
1059 | /* When arguments must be pushed onto the stack, they go on in reverse |
1060 | order. The below implements a FILO (stack) to do this. */ | |
1061 | ||
1062 | struct stack_item | |
1063 | { | |
1064 | int len; | |
1065 | struct stack_item *prev; | |
1066 | void *data; | |
1067 | }; | |
1068 | ||
a14ed312 KB |
1069 | static struct stack_item *push_stack_item (struct stack_item *prev, |
1070 | void *contents, int len); | |
7a292a7a | 1071 | static struct stack_item * |
fba45db2 | 1072 | push_stack_item (struct stack_item *prev, void *contents, int len) |
7a292a7a SS |
1073 | { |
1074 | struct stack_item *si; | |
1075 | si = xmalloc (sizeof (struct stack_item)); | |
1076 | si->data = xmalloc (len); | |
1077 | si->len = len; | |
1078 | si->prev = prev; | |
1079 | memcpy (si->data, contents, len); | |
1080 | return si; | |
1081 | } | |
1082 | ||
a14ed312 | 1083 | static struct stack_item *pop_stack_item (struct stack_item *si); |
7a292a7a | 1084 | static struct stack_item * |
fba45db2 | 1085 | pop_stack_item (struct stack_item *si) |
7a292a7a SS |
1086 | { |
1087 | struct stack_item *dead = si; | |
1088 | si = si->prev; | |
b8c9b27d KB |
1089 | xfree (dead->data); |
1090 | xfree (dead); | |
7a292a7a SS |
1091 | return si; |
1092 | } | |
1093 | ||
1094 | ||
f5e1cf12 | 1095 | static CORE_ADDR |
ea7c478f | 1096 | d10v_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
fba45db2 | 1097 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1098 | { |
1099 | int i; | |
1100 | int regnum = ARG1_REGNUM; | |
7a292a7a | 1101 | struct stack_item *si = NULL; |
7bd91a28 MS |
1102 | long val; |
1103 | ||
1104 | /* If struct_return is true, then the struct return address will | |
1105 | consume one argument-passing register. No need to actually | |
1106 | write the value to the register -- that's done by | |
1107 | d10v_store_struct_return(). */ | |
1108 | ||
1109 | if (struct_return) | |
1110 | regnum++; | |
c5aa993b | 1111 | |
c906108c SS |
1112 | /* Fill in registers and arg lists */ |
1113 | for (i = 0; i < nargs; i++) | |
1114 | { | |
ea7c478f | 1115 | struct value *arg = args[i]; |
c906108c SS |
1116 | struct type *type = check_typedef (VALUE_TYPE (arg)); |
1117 | char *contents = VALUE_CONTENTS (arg); | |
1118 | int len = TYPE_LENGTH (type); | |
7bd91a28 MS |
1119 | int aligned_regnum = (regnum + 1) & ~1; |
1120 | ||
8b279e7a | 1121 | /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ |
7bd91a28 MS |
1122 | if (len <= 2 && regnum <= ARGN_REGNUM) |
1123 | /* fits in a single register, do not align */ | |
1124 | { | |
1125 | val = extract_unsigned_integer (contents, len); | |
1126 | write_register (regnum++, val); | |
1127 | } | |
1128 | else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) | |
1129 | /* value fits in remaining registers, store keeping left | |
1130 | aligned */ | |
c906108c | 1131 | { |
7bd91a28 MS |
1132 | int b; |
1133 | regnum = aligned_regnum; | |
1134 | for (b = 0; b < (len & ~1); b += 2) | |
c906108c | 1135 | { |
7bd91a28 | 1136 | val = extract_unsigned_integer (&contents[b], 2); |
c906108c SS |
1137 | write_register (regnum++, val); |
1138 | } | |
7bd91a28 | 1139 | if (b < len) |
c906108c | 1140 | { |
7bd91a28 MS |
1141 | val = extract_unsigned_integer (&contents[b], 1); |
1142 | write_register (regnum++, (val << 8)); | |
c906108c SS |
1143 | } |
1144 | } | |
7bd91a28 MS |
1145 | else |
1146 | { | |
1147 | /* arg will go onto stack */ | |
1148 | regnum = ARGN_REGNUM + 1; | |
1149 | si = push_stack_item (si, contents, len); | |
1150 | } | |
c906108c | 1151 | } |
7a292a7a SS |
1152 | |
1153 | while (si) | |
1154 | { | |
1155 | sp = (sp - si->len) & ~1; | |
1156 | write_memory (sp, si->data, si->len); | |
1157 | si = pop_stack_item (si); | |
1158 | } | |
c5aa993b | 1159 | |
c906108c SS |
1160 | return sp; |
1161 | } | |
1162 | ||
1163 | ||
1164 | /* Given a return value in `regbuf' with a type `valtype', | |
1165 | extract and copy its value into `valbuf'. */ | |
1166 | ||
f5e1cf12 | 1167 | static void |
fa1fd571 AC |
1168 | d10v_extract_return_value (struct type *type, struct regcache *regcache, |
1169 | void *valbuf) | |
c906108c SS |
1170 | { |
1171 | int len; | |
3d79a47c MS |
1172 | #if 0 |
1173 | printf("RET: TYPE=%d len=%d r%d=0x%x\n", TYPE_CODE (type), | |
1174 | TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, | |
1175 | (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), | |
1176 | REGISTER_RAW_SIZE (RET1_REGNUM))); | |
1177 | #endif | |
fa1fd571 | 1178 | if (TYPE_LENGTH (type) == 1) |
c906108c | 1179 | { |
fa1fd571 AC |
1180 | ULONGEST c; |
1181 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); | |
3d79a47c MS |
1182 | store_unsigned_integer (valbuf, 1, c); |
1183 | } | |
3d79a47c MS |
1184 | else |
1185 | { | |
1186 | /* For return values of odd size, the first byte is in the | |
1187 | least significant part of the first register. The | |
fa1fd571 AC |
1188 | remaining bytes in remaining registers. Interestingly, when |
1189 | such values are passed in, the last byte is in the most | |
1190 | significant byte of that same register - wierd. */ | |
1191 | int reg = RET1_REGNUM; | |
1192 | int off = 0; | |
1193 | if (TYPE_LENGTH (type) & 1) | |
1194 | { | |
1195 | regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, | |
1196 | (bfd_byte *)valbuf + off); | |
1197 | off++; | |
1198 | reg++; | |
1199 | } | |
1200 | /* Transfer the remaining registers. */ | |
1201 | for (; off < TYPE_LENGTH (type); reg++, off += 2) | |
1202 | { | |
1203 | regcache_cooked_read (regcache, RET1_REGNUM + reg, | |
1204 | (bfd_byte *) valbuf + off); | |
1205 | } | |
c906108c SS |
1206 | } |
1207 | } | |
1208 | ||
c2c6d25f JM |
1209 | /* Translate a GDB virtual ADDR/LEN into a format the remote target |
1210 | understands. Returns number of bytes that can be transfered | |
4ce44c66 JM |
1211 | starting at TARG_ADDR. Return ZERO if no bytes can be transfered |
1212 | (segmentation fault). Since the simulator knows all about how the | |
1213 | VM system works, we just call that to do the translation. */ | |
c2c6d25f | 1214 | |
4ce44c66 | 1215 | static void |
c2c6d25f JM |
1216 | remote_d10v_translate_xfer_address (CORE_ADDR memaddr, int nr_bytes, |
1217 | CORE_ADDR *targ_addr, int *targ_len) | |
1218 | { | |
4ce44c66 JM |
1219 | long out_addr; |
1220 | long out_len; | |
1221 | out_len = sim_d10v_translate_addr (memaddr, nr_bytes, | |
1222 | &out_addr, | |
1223 | d10v_dmap_register, | |
1224 | d10v_imap_register); | |
1225 | *targ_addr = out_addr; | |
1226 | *targ_len = out_len; | |
c2c6d25f JM |
1227 | } |
1228 | ||
4ce44c66 | 1229 | |
c906108c SS |
1230 | /* The following code implements access to, and display of, the D10V's |
1231 | instruction trace buffer. The buffer consists of 64K or more | |
1232 | 4-byte words of data, of which each words includes an 8-bit count, | |
1233 | an 8-bit segment number, and a 16-bit instruction address. | |
1234 | ||
1235 | In theory, the trace buffer is continuously capturing instruction | |
1236 | data that the CPU presents on its "debug bus", but in practice, the | |
1237 | ROMified GDB stub only enables tracing when it continues or steps | |
1238 | the program, and stops tracing when the program stops; so it | |
1239 | actually works for GDB to read the buffer counter out of memory and | |
1240 | then read each trace word. The counter records where the tracing | |
1241 | stops, but there is no record of where it started, so we remember | |
1242 | the PC when we resumed and then search backwards in the trace | |
1243 | buffer for a word that includes that address. This is not perfect, | |
1244 | because you will miss trace data if the resumption PC is the target | |
1245 | of a branch. (The value of the buffer counter is semi-random, any | |
1246 | trace data from a previous program stop is gone.) */ | |
1247 | ||
1248 | /* The address of the last word recorded in the trace buffer. */ | |
1249 | ||
1250 | #define DBBC_ADDR (0xd80000) | |
1251 | ||
1252 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1253 | ||
1254 | #define TRACE_BUFFER_BASE (0xf40000) | |
1255 | ||
a14ed312 | 1256 | static void trace_command (char *, int); |
c906108c | 1257 | |
a14ed312 | 1258 | static void untrace_command (char *, int); |
c906108c | 1259 | |
a14ed312 | 1260 | static void trace_info (char *, int); |
c906108c | 1261 | |
a14ed312 | 1262 | static void tdisassemble_command (char *, int); |
c906108c | 1263 | |
a14ed312 | 1264 | static void display_trace (int, int); |
c906108c SS |
1265 | |
1266 | /* True when instruction traces are being collected. */ | |
1267 | ||
1268 | static int tracing; | |
1269 | ||
1270 | /* Remembered PC. */ | |
1271 | ||
1272 | static CORE_ADDR last_pc; | |
1273 | ||
1274 | /* True when trace output should be displayed whenever program stops. */ | |
1275 | ||
1276 | static int trace_display; | |
1277 | ||
1278 | /* True when trace listing should include source lines. */ | |
1279 | ||
1280 | static int default_trace_show_source = 1; | |
1281 | ||
c5aa993b JM |
1282 | struct trace_buffer |
1283 | { | |
1284 | int size; | |
1285 | short *counts; | |
1286 | CORE_ADDR *addrs; | |
1287 | } | |
1288 | trace_data; | |
c906108c SS |
1289 | |
1290 | static void | |
fba45db2 | 1291 | trace_command (char *args, int from_tty) |
c906108c SS |
1292 | { |
1293 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1294 | trace_data.size = 0; | |
1295 | if (trace_data.counts == NULL) | |
c5aa993b | 1296 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1297 | if (trace_data.addrs == NULL) |
c5aa993b | 1298 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1299 | |
1300 | tracing = 1; | |
1301 | ||
1302 | printf_filtered ("Tracing is now on.\n"); | |
1303 | } | |
1304 | ||
1305 | static void | |
fba45db2 | 1306 | untrace_command (char *args, int from_tty) |
c906108c SS |
1307 | { |
1308 | tracing = 0; | |
1309 | ||
1310 | printf_filtered ("Tracing is now off.\n"); | |
1311 | } | |
1312 | ||
1313 | static void | |
fba45db2 | 1314 | trace_info (char *args, int from_tty) |
c906108c SS |
1315 | { |
1316 | int i; | |
1317 | ||
1318 | if (trace_data.size) | |
1319 | { | |
1320 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1321 | ||
1322 | for (i = 0; i < trace_data.size; ++i) | |
1323 | { | |
d4f3574e SS |
1324 | printf_filtered ("%d: %d instruction%s at 0x%s\n", |
1325 | i, | |
1326 | trace_data.counts[i], | |
c906108c | 1327 | (trace_data.counts[i] == 1 ? "" : "s"), |
d4f3574e | 1328 | paddr_nz (trace_data.addrs[i])); |
c906108c SS |
1329 | } |
1330 | } | |
1331 | else | |
1332 | printf_filtered ("No entries in trace buffer.\n"); | |
1333 | ||
1334 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1335 | } | |
1336 | ||
1337 | /* Print the instruction at address MEMADDR in debugged memory, | |
1338 | on STREAM. Returns length of the instruction, in bytes. */ | |
1339 | ||
1340 | static int | |
fba45db2 | 1341 | print_insn (CORE_ADDR memaddr, struct ui_file *stream) |
c906108c SS |
1342 | { |
1343 | /* If there's no disassembler, something is very wrong. */ | |
1344 | if (tm_print_insn == NULL) | |
8e65ff28 AC |
1345 | internal_error (__FILE__, __LINE__, |
1346 | "print_insn: no disassembler"); | |
c906108c | 1347 | |
d7449b42 | 1348 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
1349 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; |
1350 | else | |
1351 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
2bf0cb65 | 1352 | return TARGET_PRINT_INSN (memaddr, &tm_print_insn_info); |
c906108c SS |
1353 | } |
1354 | ||
392a587b | 1355 | static void |
fba45db2 | 1356 | d10v_eva_prepare_to_trace (void) |
c906108c SS |
1357 | { |
1358 | if (!tracing) | |
1359 | return; | |
1360 | ||
1361 | last_pc = read_register (PC_REGNUM); | |
1362 | } | |
1363 | ||
1364 | /* Collect trace data from the target board and format it into a form | |
1365 | more useful for display. */ | |
1366 | ||
392a587b | 1367 | static void |
fba45db2 | 1368 | d10v_eva_get_trace_data (void) |
c906108c SS |
1369 | { |
1370 | int count, i, j, oldsize; | |
1371 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1372 | unsigned int last_trace, trace_word, next_word; | |
1373 | unsigned int *tmpspace; | |
1374 | ||
1375 | if (!tracing) | |
1376 | return; | |
1377 | ||
c5aa993b | 1378 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1379 | |
1380 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1381 | ||
1382 | /* Collect buffer contents from the target, stopping when we reach | |
1383 | the word recorded when execution resumed. */ | |
1384 | ||
1385 | count = 0; | |
1386 | while (last_trace > 0) | |
1387 | { | |
1388 | QUIT; | |
1389 | trace_word = | |
1390 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1391 | trace_addr = trace_word & 0xffff; | |
1392 | last_trace -= 4; | |
1393 | /* Ignore an apparently nonsensical entry. */ | |
1394 | if (trace_addr == 0xffd5) | |
1395 | continue; | |
1396 | tmpspace[count++] = trace_word; | |
1397 | if (trace_addr == last_pc) | |
1398 | break; | |
1399 | if (count > 65535) | |
1400 | break; | |
1401 | } | |
1402 | ||
1403 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1404 | include the last instruction executed and transforming the address | |
1405 | into something that GDB likes. */ | |
1406 | ||
1407 | for (i = 0; i < count; ++i) | |
1408 | { | |
1409 | trace_word = tmpspace[i]; | |
1410 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1411 | trace_addr = trace_word & 0xffff; | |
1412 | next_cnt = (next_word >> 24) & 0xff; | |
1413 | j = trace_data.size + count - i - 1; | |
1414 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1415 | trace_data.counts[j] = next_cnt + 1; | |
1416 | } | |
1417 | ||
1418 | oldsize = trace_data.size; | |
1419 | trace_data.size += count; | |
1420 | ||
b8c9b27d | 1421 | xfree (tmpspace); |
c906108c SS |
1422 | |
1423 | if (trace_display) | |
1424 | display_trace (oldsize, trace_data.size); | |
1425 | } | |
1426 | ||
1427 | static void | |
fba45db2 | 1428 | tdisassemble_command (char *arg, int from_tty) |
c906108c SS |
1429 | { |
1430 | int i, count; | |
1431 | CORE_ADDR low, high; | |
1432 | char *space_index; | |
1433 | ||
1434 | if (!arg) | |
1435 | { | |
1436 | low = 0; | |
1437 | high = trace_data.size; | |
1438 | } | |
1439 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1440 | { | |
1441 | low = parse_and_eval_address (arg); | |
1442 | high = low + 5; | |
1443 | } | |
1444 | else | |
1445 | { | |
1446 | /* Two arguments. */ | |
1447 | *space_index = '\0'; | |
1448 | low = parse_and_eval_address (arg); | |
1449 | high = parse_and_eval_address (space_index + 1); | |
1450 | if (high < low) | |
1451 | high = low; | |
1452 | } | |
1453 | ||
d4f3574e | 1454 | printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); |
c906108c SS |
1455 | |
1456 | display_trace (low, high); | |
1457 | ||
1458 | printf_filtered ("End of trace dump.\n"); | |
1459 | gdb_flush (gdb_stdout); | |
1460 | } | |
1461 | ||
1462 | static void | |
fba45db2 | 1463 | display_trace (int low, int high) |
c906108c SS |
1464 | { |
1465 | int i, count, trace_show_source, first, suppress; | |
1466 | CORE_ADDR next_address; | |
1467 | ||
1468 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1469 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1470 | { |
1471 | trace_show_source = 0; | |
1472 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1473 | printf_filtered ("Trace will not display any source.\n"); | |
1474 | } | |
1475 | ||
1476 | first = 1; | |
1477 | suppress = 0; | |
1478 | for (i = low; i < high; ++i) | |
1479 | { | |
1480 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1481 | count = trace_data.counts[i]; |
c906108c SS |
1482 | while (count-- > 0) |
1483 | { | |
1484 | QUIT; | |
1485 | if (trace_show_source) | |
1486 | { | |
1487 | struct symtab_and_line sal, sal_prev; | |
1488 | ||
1489 | sal_prev = find_pc_line (next_address - 4, 0); | |
1490 | sal = find_pc_line (next_address, 0); | |
1491 | ||
1492 | if (sal.symtab) | |
1493 | { | |
1494 | if (first || sal.line != sal_prev.line) | |
1495 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1496 | suppress = 0; | |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | if (!suppress) | |
1501 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1502 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1503 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1504 | suppress = 1; |
1505 | } | |
1506 | } | |
1507 | first = 0; | |
1508 | print_address (next_address, gdb_stdout); | |
1509 | printf_filtered (":"); | |
1510 | printf_filtered ("\t"); | |
1511 | wrap_here (" "); | |
1512 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1513 | printf_filtered ("\n"); | |
1514 | gdb_flush (gdb_stdout); | |
1515 | } | |
1516 | } | |
1517 | } | |
1518 | ||
ac9a91a7 | 1519 | |
0f71a2f6 | 1520 | static gdbarch_init_ftype d10v_gdbarch_init; |
4ce44c66 | 1521 | |
0f71a2f6 | 1522 | static struct gdbarch * |
fba45db2 | 1523 | d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
0f71a2f6 | 1524 | { |
c5aa993b JM |
1525 | static LONGEST d10v_call_dummy_words[] = |
1526 | {0}; | |
0f71a2f6 | 1527 | struct gdbarch *gdbarch; |
4ce44c66 JM |
1528 | int d10v_num_regs; |
1529 | struct gdbarch_tdep *tdep; | |
1530 | gdbarch_register_name_ftype *d10v_register_name; | |
7c7651b2 | 1531 | gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; |
0f71a2f6 | 1532 | |
4ce44c66 JM |
1533 | /* Find a candidate among the list of pre-declared architectures. */ |
1534 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
0f71a2f6 JM |
1535 | if (arches != NULL) |
1536 | return arches->gdbarch; | |
4ce44c66 JM |
1537 | |
1538 | /* None found, create a new architecture from the information | |
1539 | provided. */ | |
1540 | tdep = XMALLOC (struct gdbarch_tdep); | |
1541 | gdbarch = gdbarch_alloc (&info, tdep); | |
1542 | ||
a5afb99f AC |
1543 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
1544 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
1545 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
1546 | ||
4ce44c66 JM |
1547 | switch (info.bfd_arch_info->mach) |
1548 | { | |
1549 | case bfd_mach_d10v_ts2: | |
1550 | d10v_num_regs = 37; | |
1551 | d10v_register_name = d10v_ts2_register_name; | |
7c7651b2 | 1552 | d10v_register_sim_regno = d10v_ts2_register_sim_regno; |
4ce44c66 JM |
1553 | tdep->a0_regnum = TS2_A0_REGNUM; |
1554 | tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; | |
4ce44c66 JM |
1555 | tdep->dmap_register = d10v_ts2_dmap_register; |
1556 | tdep->imap_register = d10v_ts2_imap_register; | |
1557 | break; | |
1558 | default: | |
1559 | case bfd_mach_d10v_ts3: | |
1560 | d10v_num_regs = 42; | |
1561 | d10v_register_name = d10v_ts3_register_name; | |
7c7651b2 | 1562 | d10v_register_sim_regno = d10v_ts3_register_sim_regno; |
4ce44c66 JM |
1563 | tdep->a0_regnum = TS3_A0_REGNUM; |
1564 | tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; | |
4ce44c66 JM |
1565 | tdep->dmap_register = d10v_ts3_dmap_register; |
1566 | tdep->imap_register = d10v_ts3_imap_register; | |
1567 | break; | |
1568 | } | |
0f71a2f6 JM |
1569 | |
1570 | set_gdbarch_read_pc (gdbarch, d10v_read_pc); | |
1571 | set_gdbarch_write_pc (gdbarch, d10v_write_pc); | |
1572 | set_gdbarch_read_fp (gdbarch, d10v_read_fp); | |
0f71a2f6 JM |
1573 | set_gdbarch_read_sp (gdbarch, d10v_read_sp); |
1574 | set_gdbarch_write_sp (gdbarch, d10v_write_sp); | |
1575 | ||
1576 | set_gdbarch_num_regs (gdbarch, d10v_num_regs); | |
1577 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1578 | set_gdbarch_fp_regnum (gdbarch, 11); | |
1579 | set_gdbarch_pc_regnum (gdbarch, 18); | |
1580 | set_gdbarch_register_name (gdbarch, d10v_register_name); | |
1581 | set_gdbarch_register_size (gdbarch, 2); | |
1582 | set_gdbarch_register_bytes (gdbarch, (d10v_num_regs - 2) * 2 + 16); | |
1583 | set_gdbarch_register_byte (gdbarch, d10v_register_byte); | |
1584 | set_gdbarch_register_raw_size (gdbarch, d10v_register_raw_size); | |
1585 | set_gdbarch_max_register_raw_size (gdbarch, 8); | |
8b279e7a | 1586 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
0f71a2f6 JM |
1587 | set_gdbarch_max_register_virtual_size (gdbarch, 8); |
1588 | set_gdbarch_register_virtual_type (gdbarch, d10v_register_virtual_type); | |
1589 | ||
75af7f68 JB |
1590 | set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1591 | set_gdbarch_addr_bit (gdbarch, 32); | |
1592 | set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); | |
1593 | set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); | |
fc0c74b1 | 1594 | set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); |
0f71a2f6 JM |
1595 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
1596 | set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
1597 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
02da6206 | 1598 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
f0d4cc9e AC |
1599 | /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long |
1600 | double'' is 64 bits. */ | |
0f71a2f6 JM |
1601 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1602 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
1603 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
f0d4cc9e AC |
1604 | switch (info.byte_order) |
1605 | { | |
d7449b42 | 1606 | case BFD_ENDIAN_BIG: |
f0d4cc9e AC |
1607 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); |
1608 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); | |
1609 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); | |
1610 | break; | |
778eb05e | 1611 | case BFD_ENDIAN_LITTLE: |
f0d4cc9e AC |
1612 | set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); |
1613 | set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); | |
1614 | set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); | |
1615 | break; | |
1616 | default: | |
8e65ff28 AC |
1617 | internal_error (__FILE__, __LINE__, |
1618 | "d10v_gdbarch_init: bad byte order for float format"); | |
f0d4cc9e | 1619 | } |
0f71a2f6 | 1620 | |
0f71a2f6 | 1621 | set_gdbarch_call_dummy_length (gdbarch, 0); |
0f71a2f6 JM |
1622 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
1623 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
1624 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
1625 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
0f71a2f6 JM |
1626 | set_gdbarch_call_dummy_words (gdbarch, d10v_call_dummy_words); |
1627 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (d10v_call_dummy_words)); | |
1628 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
1629 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
0f71a2f6 JM |
1630 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
1631 | ||
fa1fd571 | 1632 | set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); |
0f71a2f6 JM |
1633 | set_gdbarch_push_arguments (gdbarch, d10v_push_arguments); |
1634 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); | |
1635 | set_gdbarch_push_return_address (gdbarch, d10v_push_return_address); | |
1636 | ||
0f71a2f6 | 1637 | set_gdbarch_store_struct_return (gdbarch, d10v_store_struct_return); |
fa1fd571 AC |
1638 | set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); |
1639 | set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); | |
0f71a2f6 JM |
1640 | set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); |
1641 | ||
1642 | set_gdbarch_frame_init_saved_regs (gdbarch, d10v_frame_init_saved_regs); | |
1643 | set_gdbarch_init_extra_frame_info (gdbarch, d10v_init_extra_frame_info); | |
1644 | ||
1645 | set_gdbarch_pop_frame (gdbarch, d10v_pop_frame); | |
1646 | ||
1647 | set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); | |
1648 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1649 | set_gdbarch_decr_pc_after_break (gdbarch, 4); | |
1650 | set_gdbarch_function_start_offset (gdbarch, 0); | |
1651 | set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); | |
1652 | ||
1653 | set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); | |
1654 | ||
1655 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
1656 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
1657 | set_gdbarch_frame_chain (gdbarch, d10v_frame_chain); | |
1658 | set_gdbarch_frame_chain_valid (gdbarch, d10v_frame_chain_valid); | |
1659 | set_gdbarch_frame_saved_pc (gdbarch, d10v_frame_saved_pc); | |
f4ded5b1 | 1660 | |
0f71a2f6 JM |
1661 | set_gdbarch_saved_pc_after_call (gdbarch, d10v_saved_pc_after_call); |
1662 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
23964bcd | 1663 | set_gdbarch_stack_align (gdbarch, d10v_stack_align); |
0f71a2f6 | 1664 | |
7c7651b2 | 1665 | set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); |
0a49d05e | 1666 | set_gdbarch_extra_stack_alignment_needed (gdbarch, 0); |
7c7651b2 | 1667 | |
0f71a2f6 JM |
1668 | return gdbarch; |
1669 | } | |
1670 | ||
1671 | ||
507f3c78 KB |
1672 | extern void (*target_resume_hook) (void); |
1673 | extern void (*target_wait_loop_hook) (void); | |
c906108c SS |
1674 | |
1675 | void | |
fba45db2 | 1676 | _initialize_d10v_tdep (void) |
c906108c | 1677 | { |
0f71a2f6 JM |
1678 | register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); |
1679 | ||
c906108c SS |
1680 | tm_print_insn = print_insn_d10v; |
1681 | ||
1682 | target_resume_hook = d10v_eva_prepare_to_trace; | |
1683 | target_wait_loop_hook = d10v_eva_get_trace_data; | |
1684 | ||
1685 | add_com ("regs", class_vars, show_regs, "Print all registers"); | |
1686 | ||
cff3e48b | 1687 | add_com ("itrace", class_support, trace_command, |
c906108c SS |
1688 | "Enable tracing of instruction execution."); |
1689 | ||
cff3e48b | 1690 | add_com ("iuntrace", class_support, untrace_command, |
c906108c SS |
1691 | "Disable tracing of instruction execution."); |
1692 | ||
cff3e48b | 1693 | add_com ("itdisassemble", class_vars, tdisassemble_command, |
c906108c SS |
1694 | "Disassemble the trace buffer.\n\ |
1695 | Two optional arguments specify a range of trace buffer entries\n\ | |
1696 | as reported by info trace (NOT addresses!)."); | |
1697 | ||
cff3e48b | 1698 | add_info ("itrace", trace_info, |
c906108c SS |
1699 | "Display info about the trace data buffer."); |
1700 | ||
cff3e48b | 1701 | add_show_from_set (add_set_cmd ("itracedisplay", no_class, |
c5aa993b JM |
1702 | var_integer, (char *) &trace_display, |
1703 | "Set automatic display of trace.\n", &setlist), | |
c906108c | 1704 | &showlist); |
cff3e48b | 1705 | add_show_from_set (add_set_cmd ("itracesource", no_class, |
c5aa993b JM |
1706 | var_integer, (char *) &default_trace_show_source, |
1707 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1708 | &showlist); |
1709 | ||
c5aa993b | 1710 | } |