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From change made to branch by Bob Manson <manson@cygnus.com>:
[deliverable/binutils-gdb.git] / gdb / d30v-tdep.c
CommitLineData
45a70ed6
SG		 1/* Target-dependent code for Mitsubishi D30V, for GDB.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4This file is part of GDB.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20/* Contributed by Martin Hunt, hunt@cygnus.com */
21
22#include "defs.h"
23#include "frame.h"
24#include "obstack.h"
25#include "symtab.h"
26#include "gdbtypes.h"
27#include "gdbcmd.h"
28#include "gdbcore.h"
29#include "gdb_string.h"
30#include "value.h"
31#include "inferior.h"
32#include "dis-asm.h"
33#include "symfile.h"
34#include "objfiles.h"
35
36void d30v_frame_find_saved_regs PARAMS ((struct frame_info *fi,
37 struct frame_saved_regs *fsr));
38static void d30v_pop_dummy_frame PARAMS ((struct frame_info *fi));
5d62f957
MM		 39static void d30v_print_flags PARAMS ((void));
40static void print_flags_command PARAMS ((char *, int));
45a70ed6 41
7359fb1d
DT		 42/* the following defines assume:
43 fp is r61, lr is r62, sp is r63, and ?? is r22
44 if that changes, they will need to be updated */
45
46#define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */
47
48#define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */
49#define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */
50#define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */
51#define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */
52
53#define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */
54#define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */
55#define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */
56#define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */
57
58#define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */
59#define OP_NOP 0x00f00000 /* nop */
60
61#define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */
62#define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */
63#define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */
64#define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */
65#define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */
66
67/* no mask */
68#define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */
69#define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */
70#define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */
71#define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */
72#define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */
73
74#define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */
75#define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */
76#define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */
77#define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */
78#define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */
79
80#define OP_MASK_FM_BIT 0x80000000
81#define OP_MASK_CC_BITS 0x70000000
82#define OP_MASK_SUB_INST 0x0fffffff
83
84#define EXTRACT_RA(op) (((op) >> 12) & 0x3f)
85#define EXTRACT_RB(op) (((op) >> 6) & 0x3f)
86#define EXTRACT_RC(op) (((op) & 0x3f)
87#define EXTRACT_UIMM6(op) ((op) & 0x3f)
88#define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26)
89#define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff))
90#define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr))
91
45a70ed6
SG		 92/* Discard from the stack the innermost frame, restoring all saved
93 registers. */
94
95void
96d30v_pop_frame ()
97{
98 struct frame_info *frame = get_current_frame ();
99 CORE_ADDR fp;
100 int regnum;
101 struct frame_saved_regs fsr;
102 char raw_buffer[8];
103
104 fp = FRAME_FP (frame);
105 if (frame->dummy)
106 {
107 d30v_pop_dummy_frame(frame);
108 return;
109 }
110
111 /* fill out fsr with the address of where each */
112 /* register was stored in the frame */
113 get_frame_saved_regs (frame, &fsr);
114
115 /* now update the current registers with the old values */
116 for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++)
117 {
118 if (fsr.regs[regnum])
119 {
120 read_memory (fsr.regs[regnum], raw_buffer, 8);
121 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8);
122 }
123 }
124 for (regnum = 0; regnum < SP_REGNUM; regnum++)
125 {
126 if (fsr.regs[regnum])
127 {
7359fb1d 128 write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4));
45a70ed6
SG		 129 }
130 }
131 if (fsr.regs[PSW_REGNUM])
132 {
7359fb1d 133 write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4));
45a70ed6
SG		 134 }
135
7359fb1d 136 write_register (PC_REGNUM, read_register(LR_REGNUM));
45a70ed6
SG		 137 write_register (SP_REGNUM, fp + frame->size);
138 target_store_registers (-1);
139 flush_cached_frames ();
140}
141
142static int
143check_prologue (op)
7359fb1d 144 unsigned long op;
45a70ed6 145{
7359fb1d
DT		 146 /* add sp,sp,imm -- observed */
147 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
45a70ed6
SG		 148 return 1;
149
7359fb1d
DT		 150 /* add r22,sp,imm -- observed */
151 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6
SG		 152 return 1;
153
7359fb1d
DT		 154 /* or fp,r0,sp -- observed */
155 if (op == OP_OR_FP_R0_SP)
45a70ed6
SG		 156 return 1;
157
7359fb1d
DT		 158 /* nop */
159 if ((op & OP_MASK_OPCODE) == OP_NOP)
45a70ed6
SG		 160 return 1;
161
7359fb1d
DT		 162 /* stw Ra,@(sp,r0) */
163 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0)
45a70ed6
SG		 164 return 1;
165
7359fb1d
DT		 166 /* stw Ra,@(sp,0x0) */
167 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)
45a70ed6
SG		 168 return 1;
169
7359fb1d
DT		 170 /* st2w Ra,@(sp,r0) */
171 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0)
172 return 1;
173
174 /* st2w Ra,@(sp,0x0) */
175 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)
176 return 1;
177
178 /* stw fp, @(r22+,r0) -- observed */
179 if (op == OP_STW_FP_R22P_R0)
180 return 1;
181
182 /* stw r62, @(r22+,r0) -- observed */
183 if (op == OP_STW_LR_R22P_R0)
184 return 1;
185
186 /* stw Ra, @(fp,r0) -- observed */
187 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
188 return 1; /* first arg */
189
190 /* stw Ra, @(fp,imm) -- observed */
191 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
192 return 1; /* second and subsequent args */
193
194 /* stw fp,@(sp,imm) -- observed */
195 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
196 return 1;
197
198 /* st2w Ra,@(r22+,r0) */
199 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
45a70ed6
SG		 200 return 1;
201
7359fb1d
DT		 202 /* stw Ra, @(sp-) */
203 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
204 return 1;
205
206 /* st2w Ra, @(sp-) */
207 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
208 return 1;
209
210 /* sub.? sp,sp,imm */
211 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
212 return 1;
213
45a70ed6
SG		 214 return 0;
215}
216
217CORE_ADDR
218d30v_skip_prologue (pc)
219 CORE_ADDR pc;
220{
7359fb1d
DT		 221 unsigned long op[2];
222 unsigned long opl, opr; /* left / right sub operations */
223 unsigned long fm0, fm1; /* left / right mode bits */
224 unsigned long cc0, cc1;
225 unsigned long op1, op2;
45a70ed6
SG		 226 CORE_ADDR func_addr, func_end;
227 struct symtab_and_line sal;
228
229 /* If we have line debugging information, then the end of the */
230 /* prologue should the first assembly instruction of the first source line */
231 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
232 {
233 sal = find_pc_line (func_addr, 0);
234 if ( sal.end && sal.end < func_end)
235 return sal.end;
236 }
237
7359fb1d 238 if (target_read_memory (pc, (char *)&op[0], 8))
45a70ed6
SG		 239 return pc; /* Can't access it -- assume no prologue. */
240
241 while (1)
242 {
7359fb1d
DT		 243 opl = (unsigned long)read_memory_integer (pc, 4);
244 opr = (unsigned long)read_memory_integer (pc+4, 4);
245
246 fm0 = (opl & OP_MASK_FM_BIT);
247 fm1 = (opr & OP_MASK_FM_BIT);
248
249 cc0 = (opl & OP_MASK_CC_BITS);
250 cc1 = (opr & OP_MASK_CC_BITS);
251
252 opl = (opl & OP_MASK_SUB_INST);
253 opr = (opr & OP_MASK_SUB_INST);
254
255 if (fm0 && fm1)
45a70ed6 256 {
7359fb1d
DT		 257 /* long instruction (opl contains the opcode) */
258 if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */
259 ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */
260 ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */
261 ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */
45a70ed6
SG		 262 break;
263 }
264 else
265 {
266 /* short instructions */
7359fb1d 267 if (fm0 && !fm1)
45a70ed6 268 {
7359fb1d
DT		 269 op1 = opr;
270 op2 = opl;
45a70ed6
SG		 271 }
272 else
273 {
7359fb1d
DT		 274 op1 = opl;
275 op2 = opr;
45a70ed6
SG		 276 }
277 if (check_prologue(op1))
278 {
279 if (!check_prologue(op2))
280 {
281 /* if the previous opcode was really part of the prologue */
282 /* and not just a NOP, then we want to break after both instructions */
7359fb1d
DT		 283 if ((op1 & OP_MASK_OPCODE) != OP_NOP)
284 pc += 8;
45a70ed6
SG		 285 break;
286 }
287 }
288 else
289 break;
290 }
7359fb1d 291 pc += 8;
45a70ed6
SG		 292 }
293 return pc;
294}
295
296/* Given a GDB frame, determine the address of the calling function's frame.
297 This will be used to create a new GDB frame struct, and then
298 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
299*/
300
301CORE_ADDR
302d30v_frame_chain (frame)
303 struct frame_info *frame;
304{
305 struct frame_saved_regs fsr;
306
307 d30v_frame_find_saved_regs (frame, &fsr);
308
309 if (frame->return_pc == IMEM_START)
310 return (CORE_ADDR)0;
311
312 if (!fsr.regs[FP_REGNUM])
313 {
314 if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START)
315 return (CORE_ADDR)0;
316
317 return fsr.regs[SP_REGNUM];
318 }
319
7359fb1d 320 if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM],4))
45a70ed6
SG		 321 return (CORE_ADDR)0;
322
7359fb1d 323 return read_memory_unsigned_integer(fsr.regs[FP_REGNUM],4)| DMEM_START;
45a70ed6
SG		 324}
325
326static int next_addr, uses_frame;
7359fb1d 327static int frame_size;
45a70ed6
SG		 328
329static int
330prologue_find_regs (op, fsr, addr)
7359fb1d 331 unsigned long op;
45a70ed6
SG		 332 struct frame_saved_regs *fsr;
333 CORE_ADDR addr;
334{
335 int n;
7359fb1d 336 int offset;
45a70ed6 337
7359fb1d
DT		 338 /* add sp,sp,imm -- observed */
339 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
45a70ed6 340 {
7359fb1d
DT		 341 offset = EXTRACT_IMM6(op);
342 /*next_addr += offset;*/
343 frame_size += -offset;
45a70ed6
SG		 344 return 1;
345 }
346
7359fb1d
DT		 347 /* add r22,sp,imm -- observed */
348 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6 349 {
7359fb1d
DT		 350 offset = EXTRACT_IMM6(op);
351 next_addr = (offset - frame_size);
352 return 1;
353 }
354
355 /* stw Ra, @(fp, offset) -- observed */
356 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
357 {
358 n = EXTRACT_RA(op);
359 offset = EXTRACT_IMM6(op);
360 fsr->regs[n] = (offset - frame_size);
45a70ed6
SG		 361 return 1;
362 }
363
7359fb1d
DT		 364 /* stw Ra, @(fp, r0) -- observed */
365 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
45a70ed6 366 {
7359fb1d
DT		 367 n = EXTRACT_RA(op);
368 fsr->regs[n] = (- frame_size);
45a70ed6
SG		 369 return 1;
370 }
371
7359fb1d
DT		 372 /* or fp,0,sp -- observed */
373 if ((op == OP_OR_FP_R0_SP) ||
374 (op == OP_OR_FP_SP_R0) ||
375 (op == OP_OR_FP_IMM0_SP))
45a70ed6
SG		 376 {
377 uses_frame = 1;
378 return 1;
379 }
380
381 /* nop */
7359fb1d 382 if ((op & OP_MASK_OPCODE) == OP_NOP)
45a70ed6
SG		 383 return 1;
384
7359fb1d
DT		 385 /* stw Ra,@(r22+,r0) -- observed */
386 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0)
387 {
388 n = EXTRACT_RA(op);
389 fsr->regs[n] = next_addr;
390 next_addr += 4;
391 return 1;
392 }
393#if 0 /* subsumed in pattern above */
394 /* stw fp,@(r22+,r0) -- observed */
395 if (op == OP_STW_FP_R22P_R0)
396 {
397 fsr->regs[FP_REGNUM] = next_addr; /* XXX */
398 next_addr += 4;
399 return 1;
400 }
401
402 /* stw r62,@(r22+,r0) -- observed */
403 if (op == OP_STW_LR_R22P_R0)
404 {
405 fsr->regs[LR_REGNUM] = next_addr;
406 next_addr += 4;
407 return 1;
408 }
409#endif
410 /* st2w Ra,@(r22+,r0) -- observed */
411 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
412 {
413 n = EXTRACT_RA(op);
414 fsr->regs[n] = next_addr;
415 fsr->regs[n+1] = next_addr + 4;
416 next_addr += 8;
417 return 1;
418 }
419
420 /* stw rn, @(sp-) */
421 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
422 {
423 n = EXTRACT_RA(op);
424 fsr->regs[n] = next_addr;
425 next_addr -= 4;
426 return 1;
427 }
428
429 /* st2w Ra, @(sp-) */
430 else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
45a70ed6 431 {
7359fb1d 432 n = EXTRACT_RA(op);
45a70ed6 433 fsr->regs[n] = next_addr;
7359fb1d
DT		 434 fsr->regs[n+1] = next_addr+4;
435 next_addr -= 8;
436 return 1;
437 }
438
439 /* sub sp,sp,imm */
440 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
441 {
442 offset = EXTRACT_IMM6(op);
443 next_addr -= offset;
45a70ed6
SG		 444 return 1;
445 }
446
7359fb1d
DT		 447 /* st rn, @(sp,0) */
448 if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) ||
449 ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0))
45a70ed6 450 {
7359fb1d 451 n = EXTRACT_RA(op);
45a70ed6 452 fsr->regs[n] = next_addr;
7359fb1d
DT		 453 return 1;
454 }
455
456 /* st2w rn, @(sp,0) */
457 if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) ||
458 ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0))
459 {
460 n = EXTRACT_RA(op);
461 fsr->regs[n] = next_addr;
462 fsr->regs[n+1] = next_addr+4;
45a70ed6
SG		 463 return 1;
464 }
465
466 return 0;
467}
468
469/* Put here the code to store, into a struct frame_saved_regs, the
470 addresses of the saved registers of frame described by FRAME_INFO.
471 This includes special registers such as pc and fp saved in special
472 ways in the stack frame. sp is even more special: the address we
473 return for it IS the sp for the next frame. */
474void
475d30v_frame_find_saved_regs (fi, fsr)
476 struct frame_info *fi;
477 struct frame_saved_regs *fsr;
478{
479 CORE_ADDR fp, pc;
7359fb1d
DT		 480 unsigned long opl, opr;
481 unsigned long op1, op2;
482 unsigned long fm0, fm1;
45a70ed6
SG		 483 int i;
484
485 fp = fi->frame;
486 memset (fsr, 0, sizeof (*fsr));
487 next_addr = 0;
7359fb1d 488 frame_size = 0;
45a70ed6
SG		 489
490 pc = get_pc_function_start (fi->pc);
491
492 uses_frame = 0;
493 while (1)
494 {
7359fb1d
DT		 495 opl = (unsigned long)read_memory_integer (pc, 4);
496 opr = (unsigned long)read_memory_integer (pc+4, 4);
497
498 fm0 = (opl & OP_MASK_FM_BIT);
499 fm1 = (opr & OP_MASK_FM_BIT);
500
501 opl = (opl & OP_MASK_SUB_INST);
502 opr = (opr & OP_MASK_SUB_INST);
503
504 if (fm0 && fm1)
45a70ed6
SG		 505 {
506 /* long instruction */
7359fb1d
DT		 507 if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
508 {
509 /* add sp,sp,n */
510 long offset = EXTRACT_IMM32(opl, opr);
511 frame_size += -offset;
512 }
513 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6 514 {
7359fb1d
DT		 515 /* add r22,sp,offset */
516 long offset = EXTRACT_IMM32(opl,opr);
517 next_addr = (offset - frame_size);
45a70ed6 518 }
7359fb1d 519 else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM)
45a70ed6 520 {
7359fb1d
DT		 521 /* st Ra, @(sp,imm) */
522 long offset = EXTRACT_IMM32(opl, opr);
523 short n = EXTRACT_RA(opl);
524 fsr->regs[n] = (offset - frame_size);
45a70ed6 525 }
7359fb1d 526 else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM)
45a70ed6 527 {
7359fb1d
DT		 528 /* st2w Ra, @(sp,offset) */
529 long offset = EXTRACT_IMM32(opl, opr);
530 short n = EXTRACT_RA(opl);
531 fsr->regs[n] = (offset - frame_size);
532 fsr->regs[n+1] = (offset - frame_size) + 4;
45a70ed6
SG		 533 }
534 else
535 break;
536 }
537 else
538 {
539 /* short instructions */
7359fb1d 540 if (fm0 && !fm1)
45a70ed6 541 {
7359fb1d
DT		 542 op2 = opl;
543 op1 = opr;
45a70ed6
SG		 544 }
545 else
546 {
7359fb1d
DT		 547 op1 = opl;
548 op2 = opr;
45a70ed6
SG		 549 }
550 if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc))
551 break;
552 }
7359fb1d 553 pc += 8;
45a70ed6
SG		 554 }
555
7359fb1d
DT		 556 fi->size = frame_size;
557 if (!fp)
558#if 0
45a70ed6 559 fp = read_register(SP_REGNUM) | DMEM_START;
7359fb1d
DT		 560#else
561 fp = read_register(SP_REGNUM);
562#endif
45a70ed6
SG		 563 for (i=0; i<NUM_REGS-1; i++)
564 if (fsr->regs[i])
565 {
7359fb1d 566 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
45a70ed6
SG		 567 }
568
569 if (fsr->regs[LR_REGNUM])
7359fb1d 570 fi->return_pc = read_memory_unsigned_integer(fsr->regs[LR_REGNUM],4);
45a70ed6 571 else
7359fb1d 572 fi->return_pc = read_register(LR_REGNUM);
45a70ed6
SG		 573
574 /* th SP is not normally (ever?) saved, but check anyway */
575 if (!fsr->regs[SP_REGNUM])
576 {
577 /* if the FP was saved, that means the current FP is valid, */
578 /* otherwise, it isn't being used, so we use the SP instead */
579 if (uses_frame)
580 fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size;
581 else
582 {
583 fsr->regs[SP_REGNUM] = fp + fi->size;
584 fi->frameless = 1;
585 fsr->regs[FP_REGNUM] = 0;
586 }
587 }
588}
589
590void
591d30v_init_extra_frame_info (fromleaf, fi)
592 int fromleaf;
593 struct frame_info *fi;
594{
595 struct frame_saved_regs dummy;
596
7359fb1d 597 if (fi->next && (fi->pc == 0))
45a70ed6
SG		 598 fi->pc = fi->next->return_pc;
599
600 d30v_frame_find_saved_regs (fi, &dummy);
601}
602
7359fb1d
DT		 603void
604d30v_init_frame_pc (fromleaf, prev)
605 int fromleaf;
606 struct frame_info *prev;
607{
608 /* default value, put here so we can breakpoint on it and
609 see if the default value is really the right thing to use */
610 prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
611 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
612}
613
45a70ed6
SG		 614static void d30v_print_register PARAMS ((int regnum, int tabular));
615
616static void
617d30v_print_register (regnum, tabular)
618 int regnum;
619 int tabular;
620{
621 if (regnum < A0_REGNUM)
622 {
623 if (tabular)
624 printf_filtered ("%08x", read_register (regnum));
625 else
626 printf_filtered ("0x%x %d", read_register (regnum),
627 read_register (regnum));
628 }
629 else
630 {
631 char regbuf[MAX_REGISTER_RAW_SIZE];
632
633 read_relative_register_raw_bytes (regnum, regbuf);
634
635 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0,
636 gdb_stdout, 'x', 1, 0, Val_pretty_default);
637
638 if (!tabular)
639 {
640 printf_filtered (" ");
641 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0,
642 gdb_stdout, 'd', 1, 0, Val_pretty_default);
643 }
644 }
645}
646
5d62f957
MM		 647static void
648d30v_print_flags ()
649{
650 long psw = read_register (PSW_REGNUM);
651 printf_filtered ("flags #1");
652 printf_filtered (" (sm) %d", (psw & PSW_SM) != 0);
653 printf_filtered (" (ea) %d", (psw & PSW_EA) != 0);
654 printf_filtered (" (db) %d", (psw & PSW_DB) != 0);
655 printf_filtered (" (ds) %d", (psw & PSW_DS) != 0);
656 printf_filtered (" (ie) %d", (psw & PSW_IE) != 0);
657 printf_filtered (" (rp) %d", (psw & PSW_RP) != 0);
658 printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0);
659
660 printf_filtered ("flags #2");
661 printf_filtered (" (f0) %d", (psw & PSW_F0) != 0);
662 printf_filtered (" (f1) %d", (psw & PSW_F1) != 0);
663 printf_filtered (" (f2) %d", (psw & PSW_F2) != 0);
664 printf_filtered (" (f3) %d", (psw & PSW_F3) != 0);
665 printf_filtered (" (s) %d", (psw & PSW_S) != 0);
666 printf_filtered (" (v) %d", (psw & PSW_V) != 0);
667 printf_filtered (" (va) %d", (psw & PSW_VA) != 0);
668 printf_filtered (" (c) %d\n", (psw & PSW_C) != 0);
669}
670
671static void
672print_flags_command (args, from_tty)
673 char *args;
674 int from_tty;
675{
676 d30v_print_flags ();
677}
678
45a70ed6
SG		 679void
680d30v_do_registers_info (regnum, fpregs)
681 int regnum;
682 int fpregs;
683{
684 long long num1, num2;
5d62f957 685 long psw;
45a70ed6
SG		 686
687 if (regnum != -1)
688 {
689 if (reg_names[0] == NULL || reg_names[0][0] == '\000')
690 return;
691
692 printf_filtered ("%s ", reg_names[regnum]);
693 d30v_print_register (regnum, 0);
694
695 printf_filtered ("\n");
696 return;
697 }
698
699 /* Have to print all the registers. Format them nicely. */
700
701 printf_filtered ("PC=");
702 print_address (read_pc (), gdb_stdout);
703
704 printf_filtered (" PSW=");
705 d30v_print_register (PSW_REGNUM, 1);
706
707 printf_filtered (" BPC=");
708 print_address (read_register (BPC_REGNUM), gdb_stdout);
709
710 printf_filtered (" BPSW=");
711 d30v_print_register (BPSW_REGNUM, 1);
712 printf_filtered ("\n");
713
714 printf_filtered ("DPC=");
715 print_address (read_register (DPC_REGNUM), gdb_stdout);
716
717 printf_filtered (" DPSW=");
718 d30v_print_register (DPSW_REGNUM, 1);
719
720 printf_filtered (" IBA=");
721 print_address (read_register (IBA_REGNUM), gdb_stdout);
722 printf_filtered ("\n");
723
724 printf_filtered ("RPT_C=");
725 d30v_print_register (RPT_C_REGNUM, 1);
726
727 printf_filtered (" RPT_S=");
728 print_address (read_register (RPT_S_REGNUM), gdb_stdout);
729
730 printf_filtered (" RPT_E=");
731 print_address (read_register (RPT_E_REGNUM), gdb_stdout);
732 printf_filtered ("\n");
733
734 printf_filtered ("MOD_S=");
735 print_address (read_register (MOD_S_REGNUM), gdb_stdout);
736
737 printf_filtered (" MOD_E=");
738 print_address (read_register (MOD_E_REGNUM), gdb_stdout);
739 printf_filtered ("\n");
740
741 printf_filtered ("EIT_VB=");
742 print_address (read_register (EIT_VB_REGNUM), gdb_stdout);
743
744 printf_filtered (" INT_S=");
745 d30v_print_register (INT_S_REGNUM, 1);
746
747 printf_filtered (" INT_M=");
748 d30v_print_register (INT_M_REGNUM, 1);
749 printf_filtered ("\n");
750
5d62f957 751 d30v_print_flags ();
45a70ed6
SG		 752 for (regnum = 0; regnum <= 63;)
753 {
754 int i;
755
756 printf_filtered ("R%d-R%d ", regnum, regnum + 7);
757 if (regnum < 10)
758 printf_filtered (" ");
759 if (regnum + 7 < 10)
760 printf_filtered (" ");
761
762 for (i = 0; i < 8; i++)
763 {
764 printf_filtered (" ");
765 d30v_print_register (regnum++, 1);
766 }
767
768 printf_filtered ("\n");
769 }
770
771 printf_filtered ("A0-A1 ");
772
773 d30v_print_register (A0_REGNUM, 1);
774 printf_filtered (" ");
775 d30v_print_register (A1_REGNUM, 1);
776 printf_filtered ("\n");
777}
778
779CORE_ADDR
780d30v_fix_call_dummy (dummyname, start_sp, fun, nargs, args, type, gcc_p)
781 char *dummyname;
782 CORE_ADDR start_sp;
783 CORE_ADDR fun;
784 int nargs;
785 value_ptr *args;
786 struct type *type;
787 int gcc_p;
788{
789 int regnum;
790 CORE_ADDR sp;
791 char buffer[MAX_REGISTER_RAW_SIZE];
792 struct frame_info *frame = get_current_frame ();
793 frame->dummy = start_sp;
7359fb1d 794 /*start_sp |= DMEM_START;*/
45a70ed6
SG		 795
796 sp = start_sp;
797 for (regnum = 0; regnum < NUM_REGS; regnum++)
798 {
799 sp -= REGISTER_RAW_SIZE(regnum);
800 store_address (buffer, REGISTER_RAW_SIZE(regnum), read_register(regnum));
801 write_memory (sp, buffer, REGISTER_RAW_SIZE(regnum));
802 }
7359fb1d 803 write_register (SP_REGNUM, (LONGEST)sp);
45a70ed6 804 /* now we need to load LR with the return address */
7359fb1d 805 write_register (LR_REGNUM, (LONGEST)d30v_call_dummy_address());
45a70ed6
SG		 806 return sp;
807}
808
809static void
810d30v_pop_dummy_frame (fi)
811 struct frame_info *fi;
812{
813 CORE_ADDR sp = fi->dummy;
814 int regnum;
815
816 for (regnum = 0; regnum < NUM_REGS; regnum++)
817 {
818 sp -= REGISTER_RAW_SIZE(regnum);
819 write_register(regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE(regnum)));
820 }
821 flush_cached_frames (); /* needed? */
822}
823
824
825CORE_ADDR
826d30v_push_arguments (nargs, args, sp, struct_return, struct_addr)
827 int nargs;
828 value_ptr *args;
829 CORE_ADDR sp;
830 int struct_return;
831 CORE_ADDR struct_addr;
832{
833 int i, len, index=0, regnum=2;
834 char buffer[4], *contents;
835 LONGEST val;
836 CORE_ADDR ptrs[10];
837
7359fb1d 838#if 0
45a70ed6
SG		 839 /* Pass 1. Put all large args on stack */
840 for (i = 0; i < nargs; i++)
841 {
842 value_ptr arg = args[i];
843 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
844 len = TYPE_LENGTH (arg_type);
845 contents = VALUE_CONTENTS(arg);
846 val = extract_signed_integer (contents, len);
847 if (len > 4)
848 {
849 /* put on stack and pass pointers */
850 sp -= len;
851 write_memory (sp, contents, len);
852 ptrs[index++] = sp;
853 }
854 }
7359fb1d 855#endif
45a70ed6
SG		 856 index = 0;
857
858 for (i = 0; i < nargs; i++)
859 {
860 value_ptr arg = args[i];
861 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
862 len = TYPE_LENGTH (arg_type);
863 contents = VALUE_CONTENTS(arg);
864 val = extract_signed_integer (contents, len);
865 if (len > 4)
866 {
7359fb1d
DT		 867 /* we need multiple registers */
868 int ndx;
869
870 for (ndx = 0; ndx < len; ndx += 4, len -= 4)
45a70ed6 871 {
7359fb1d
DT		 872 if (regnum < 18)
873 {
874 if (len > 4)
875 val = extract_signed_integer (&contents[ndx], 4);
876 else
877 val = extract_signed_integer (&contents[ndx], len);
878
879 write_register (regnum++, val);
880 }
881 else
882 {
883 /* no more registers available. put it on the stack */
884 sp -= len;
885 write_memory (sp, &contents[ndx], len);
886 break;
887 }
45a70ed6
SG		 888 }
889 }
890 else
891 {
7359fb1d 892 if (regnum < 18 )
45a70ed6 893 {
7359fb1d 894 write_register (regnum++, val);
45a70ed6
SG		 895 }
896 else
897 {
898 sp -= len;
899 store_address (buffer, len, val);
900 write_memory (sp, buffer, len);
901 }
902 }
903 }
904 return sp;
905}
906
907
908/* pick an out-of-the-way place to set the return value */
909/* for an inferior function call. The link register is set to this */
910/* value and a momentary breakpoint is set there. When the breakpoint */
911/* is hit, the dummy frame is popped and the previous environment is */
912/* restored. */
913
914CORE_ADDR
915d30v_call_dummy_address ()
916{
917 CORE_ADDR entry;
918 struct minimal_symbol *sym;
919
920 entry = entry_point_address ();
921
922 if (entry != 0)
923 return entry;
924
925 sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile);
926
927 if (!sym || MSYMBOL_TYPE (sym) != mst_text)
928 return 0;
929 else
930 return SYMBOL_VALUE_ADDRESS (sym);
931}
932
933/* Given a return value in `regbuf' with a type `valtype',
934 extract and copy its value into `valbuf'. */
935
936void
937d30v_extract_return_value (valtype, regbuf, valbuf)
938 struct type *valtype;
939 char regbuf[REGISTER_BYTES];
940 char *valbuf;
941{
942 memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype));
943}
944
945/* The following code implements access to, and display of, the D30V's
946 instruction trace buffer. The buffer consists of 64K or more
947 4-byte words of data, of which each words includes an 8-bit count,
948 an 8-bit segment number, and a 16-bit instruction address.
949
950 In theory, the trace buffer is continuously capturing instruction
951 data that the CPU presents on its "debug bus", but in practice, the
952 ROMified GDB stub only enables tracing when it continues or steps
953 the program, and stops tracing when the program stops; so it
954 actually works for GDB to read the buffer counter out of memory and
955 then read each trace word. The counter records where the tracing
956 stops, but there is no record of where it started, so we remember
957 the PC when we resumed and then search backwards in the trace
958 buffer for a word that includes that address. This is not perfect,
959 because you will miss trace data if the resumption PC is the target
960 of a branch. (The value of the buffer counter is semi-random, any
961 trace data from a previous program stop is gone.) */
962
963/* The address of the last word recorded in the trace buffer. */
964
965#define DBBC_ADDR (0xd80000)
966
967/* The base of the trace buffer, at least for the "Board_0". */
968
969#define TRACE_BUFFER_BASE (0xf40000)
970
971static void trace_command PARAMS ((char *, int));
972
973static void untrace_command PARAMS ((char *, int));
974
975static void trace_info PARAMS ((char *, int));
976
977static void tdisassemble_command PARAMS ((char *, int));
978
979static void display_trace PARAMS ((int, int));
980
981/* True when instruction traces are being collected. */
982
983static int tracing;
984
985/* Remembered PC. */
986
987static CORE_ADDR last_pc;
988
989/* True when trace output should be displayed whenever program stops. */
990
991static int trace_display;
992
993/* True when trace listing should include source lines. */
994
995static int default_trace_show_source = 1;
996
997struct trace_buffer {
998 int size;
999 short *counts;
1000 CORE_ADDR *addrs;
1001} trace_data;
1002
1003static void
1004trace_command (args, from_tty)
1005 char *args;
1006 int from_tty;
1007{
1008 /* Clear the host-side trace buffer, allocating space if needed. */
1009 trace_data.size = 0;
1010 if (trace_data.counts == NULL)
1011 trace_data.counts = (short *) xmalloc (65536 * sizeof(short));
1012 if (trace_data.addrs == NULL)
1013 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR));
1014
1015 tracing = 1;
1016
1017 printf_filtered ("Tracing is now on.\n");
1018}
1019
1020static void
1021untrace_command (args, from_tty)
1022 char *args;
1023 int from_tty;
1024{
1025 tracing = 0;
1026
1027 printf_filtered ("Tracing is now off.\n");
1028}
1029
1030static void
1031trace_info (args, from_tty)
1032 char *args;
1033 int from_tty;
1034{
1035 int i;
1036
1037 if (trace_data.size)
1038 {
1039 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1040
1041 for (i = 0; i < trace_data.size; ++i)
1042 {
1043 printf_filtered ("%d: %d instruction%s at 0x%x\n",
1044 i, trace_data.counts[i],
1045 (trace_data.counts[i] == 1 ? "" : "s"),
1046 trace_data.addrs[i]);
1047 }
1048 }
1049 else
1050 printf_filtered ("No entries in trace buffer.\n");
1051
1052 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1053}
1054
1055/* Print the instruction at address MEMADDR in debugged memory,
1056 on STREAM. Returns length of the instruction, in bytes. */
1057
1058static int
1059print_insn (memaddr, stream)
1060 CORE_ADDR memaddr;
1061 GDB_FILE *stream;
1062{
1063 /* If there's no disassembler, something is very wrong. */
1064 if (tm_print_insn == NULL)
1065 abort ();
1066
1067 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1068 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1069 else
1070 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1071 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1072}
1073
1074void
1075d30v_eva_prepare_to_trace ()
1076{
1077 if (!tracing)
1078 return;
1079
1080 last_pc = read_register (PC_REGNUM);
1081}
1082
1083/* Collect trace data from the target board and format it into a form
1084 more useful for display. */
1085
1086void
1087d30v_eva_get_trace_data ()
1088{
1089 int count, i, j, oldsize;
1090 int trace_addr, trace_seg, trace_cnt, next_cnt;
1091 unsigned int last_trace, trace_word, next_word;
1092 unsigned int *tmpspace;
1093
1094 if (!tracing)
1095 return;
1096
1097 tmpspace = xmalloc (65536 * sizeof(unsigned int));
1098
1099 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1100
1101 /* Collect buffer contents from the target, stopping when we reach
1102 the word recorded when execution resumed. */
1103
1104 count = 0;
1105 while (last_trace > 0)
1106 {
1107 QUIT;
1108 trace_word =
1109 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1110 trace_addr = trace_word & 0xffff;
1111 last_trace -= 4;
1112 /* Ignore an apparently nonsensical entry. */
1113 if (trace_addr == 0xffd5)
1114 continue;
1115 tmpspace[count++] = trace_word;
1116 if (trace_addr == last_pc)
1117 break;
1118 if (count > 65535)
1119 break;
1120 }
1121
1122 /* Move the data to the host-side trace buffer, adjusting counts to
1123 include the last instruction executed and transforming the address
1124 into something that GDB likes. */
1125
1126 for (i = 0; i < count; ++i)
1127 {
1128 trace_word = tmpspace[i];
1129 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1130 trace_addr = trace_word & 0xffff;
1131 next_cnt = (next_word >> 24) & 0xff;
1132 j = trace_data.size + count - i - 1;
1133 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1134 trace_data.counts[j] = next_cnt + 1;
1135 }
1136
1137 oldsize = trace_data.size;
1138 trace_data.size += count;
1139
1140 free (tmpspace);
1141
1142 if (trace_display)
1143 display_trace (oldsize, trace_data.size);
1144}
1145
1146static void
1147tdisassemble_command (arg, from_tty)
1148 char *arg;
1149 int from_tty;
1150{
1151 int i, count;
1152 CORE_ADDR low, high;
1153 char *space_index;
1154
1155 if (!arg)
1156 {
1157 low = 0;
1158 high = trace_data.size;
1159 }
1160 else if (!(space_index = (char *) strchr (arg, ' ')))
1161 {
1162 low = parse_and_eval_address (arg);
1163 high = low + 5;
1164 }
1165 else
1166 {
1167 /* Two arguments. */
1168 *space_index = '\0';
1169 low = parse_and_eval_address (arg);
1170 high = parse_and_eval_address (space_index + 1);
1171 if (high < low)
1172 high = low;
1173 }
1174
1175 printf_filtered ("Dump of trace from %d to %d:\n", low, high);
1176
1177 display_trace (low, high);
1178
1179 printf_filtered ("End of trace dump.\n");
1180 gdb_flush (gdb_stdout);
1181}
1182
1183static void
1184display_trace (low, high)
1185 int low, high;
1186{
1187 int i, count, trace_show_source, first, suppress;
1188 CORE_ADDR next_address;
1189
1190 trace_show_source = default_trace_show_source;
1191 if (!have_full_symbols () && !have_partial_symbols())
1192 {
1193 trace_show_source = 0;
1194 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1195 printf_filtered ("Trace will not display any source.\n");
1196 }
1197
1198 first = 1;
1199 suppress = 0;
1200 for (i = low; i < high; ++i)
1201 {
1202 next_address = trace_data.addrs[i];
1203 count = trace_data.counts[i];
1204 while (count-- > 0)
1205 {
1206 QUIT;
1207 if (trace_show_source)
1208 {
1209 struct symtab_and_line sal, sal_prev;
1210
1211 sal_prev = find_pc_line (next_address - 4, 0);
1212 sal = find_pc_line (next_address, 0);
1213
1214 if (sal.symtab)
1215 {
1216 if (first || sal.line != sal_prev.line)
1217 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1218 suppress = 0;
1219 }
1220 else
1221 {
1222 if (!suppress)
1223 /* FIXME-32x64--assumes sal.pc fits in long. */
1224 printf_filtered ("No source file for address %s.\n",
1225 local_hex_string((unsigned long) sal.pc));
1226 suppress = 1;
1227 }
1228 }
1229 first = 0;
1230 print_address (next_address, gdb_stdout);
1231 printf_filtered (":");
1232 printf_filtered ("\t");
1233 wrap_here (" ");
1234 next_address = next_address + print_insn (next_address, gdb_stdout);
1235 printf_filtered ("\n");
1236 gdb_flush (gdb_stdout);
1237 }
1238 }
1239}
1240
1241extern void (*target_resume_hook) PARAMS ((void));
1242extern void (*target_wait_loop_hook) PARAMS ((void));
1243
1244void
1245_initialize_d30v_tdep ()
1246{
1247 tm_print_insn = print_insn_d30v;
1248
1249 target_resume_hook = d30v_eva_prepare_to_trace;
1250 target_wait_loop_hook = d30v_eva_get_trace_data;
1251
5d62f957
MM		 1252 add_info ("flags", print_flags_command, "Print d30v flags.");
1253
45a70ed6
SG		 1254 add_com ("trace", class_support, trace_command,
1255 "Enable tracing of instruction execution.");
1256
1257 add_com ("untrace", class_support, untrace_command,
7359fb1d 1258 "Disable tracing of instruction execution.");
45a70ed6
SG		 1259
1260 add_com ("tdisassemble", class_vars, tdisassemble_command,
1261 "Disassemble the trace buffer.\n\
1262Two optional arguments specify a range of trace buffer entries\n\
1263as reported by info trace (NOT addresses!).");
1264
1265 add_info ("trace", trace_info,
1266 "Display info about the trace data buffer.");
1267
1268 add_show_from_set (add_set_cmd ("tracedisplay", no_class,
1269 var_integer, (char *)&trace_display,
1270 "Set automatic display of trace.\n", &setlist),
1271 &showlist);
1272 add_show_from_set (add_set_cmd ("tracesource", no_class,
1273 var_integer, (char *)&default_trace_show_source,
1274 "Set display of source code with trace.\n", &setlist),
1275 &showlist);
1276
1277}
GDB Binutils - Deliverables
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