Commit | Line | Data |
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c906108c SS |
1 | /* Target-dependent code for Mitsubishi D30V, for GDB. |
2 | Copyright (C) 1996, 1997 Free Software Foundation, Inc. | |
3 | ||
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
20 | |
21 | /* Contributed by Martin Hunt, hunt@cygnus.com */ | |
22 | ||
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "obstack.h" | |
26 | #include "symtab.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdb_string.h" | |
31 | #include "value.h" | |
32 | #include "inferior.h" | |
c5aa993b | 33 | #include "dis-asm.h" |
c906108c SS |
34 | #include "symfile.h" |
35 | #include "objfiles.h" | |
36 | ||
c5aa993b JM |
37 | void d30v_frame_find_saved_regs PARAMS ((struct frame_info * fi, |
38 | struct frame_saved_regs * fsr)); | |
39 | void d30v_frame_find_saved_regs_offsets PARAMS ((struct frame_info * fi, | |
40 | struct frame_saved_regs * fsr)); | |
41 | static void d30v_pop_dummy_frame PARAMS ((struct frame_info * fi)); | |
c906108c SS |
42 | static void d30v_print_flags PARAMS ((void)); |
43 | static void print_flags_command PARAMS ((char *, int)); | |
44 | ||
45 | /* the following defines assume: | |
46 | fp is r61, lr is r62, sp is r63, and ?? is r22 | |
47 | if that changes, they will need to be updated */ | |
48 | ||
c5aa993b | 49 | #define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */ |
c906108c | 50 | |
c5aa993b JM |
51 | #define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */ |
52 | #define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */ | |
53 | #define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */ | |
54 | #define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */ | |
c906108c | 55 | |
c5aa993b JM |
56 | #define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */ |
57 | #define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */ | |
58 | #define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */ | |
59 | #define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */ | |
c906108c | 60 | |
c5aa993b JM |
61 | #define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */ |
62 | #define OP_NOP 0x00f00000 /* nop */ | |
c906108c | 63 | |
c5aa993b JM |
64 | #define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */ |
65 | #define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */ | |
66 | #define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */ | |
67 | #define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */ | |
68 | #define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */ | |
69 | #define OP_OR_SP_R0_IMM 0x03abf000 /* or sp,r0,imm */ | |
c906108c SS |
70 | |
71 | /* no mask */ | |
c5aa993b JM |
72 | #define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */ |
73 | #define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */ | |
74 | #define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */ | |
75 | #define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */ | |
76 | #define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */ | |
77 | ||
78 | #define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */ | |
79 | #define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */ | |
80 | #define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */ | |
81 | #define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */ | |
82 | #define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */ | |
c906108c SS |
83 | |
84 | #define OP_MASK_FM_BIT 0x80000000 | |
85 | #define OP_MASK_CC_BITS 0x70000000 | |
86 | #define OP_MASK_SUB_INST 0x0fffffff | |
87 | ||
88 | #define EXTRACT_RA(op) (((op) >> 12) & 0x3f) | |
89 | #define EXTRACT_RB(op) (((op) >> 6) & 0x3f) | |
90 | #define EXTRACT_RC(op) (((op) & 0x3f) | |
91 | #define EXTRACT_UIMM6(op) ((op) & 0x3f) | |
92 | #define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26) | |
93 | #define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff)) | |
94 | #define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr)) | |
95 | ||
96 | ||
97 | int | |
98 | d30v_frame_chain_valid (chain, fi) | |
99 | CORE_ADDR chain; | |
c5aa993b | 100 | struct frame_info *fi; /* not used here */ |
c906108c SS |
101 | { |
102 | #if 0 | |
103 | return ((chain) != 0 && (fi) != 0 && (fi)->return_pc != 0); | |
104 | #else | |
105 | return ((chain) != 0 && (fi) != 0 && (fi)->frame <= chain); | |
106 | #endif | |
107 | } | |
108 | ||
109 | /* Discard from the stack the innermost frame, restoring all saved | |
110 | registers. */ | |
111 | ||
112 | void | |
113 | d30v_pop_frame () | |
114 | { | |
115 | struct frame_info *frame = get_current_frame (); | |
116 | CORE_ADDR fp; | |
117 | int regnum; | |
118 | struct frame_saved_regs fsr; | |
119 | char raw_buffer[8]; | |
120 | ||
121 | fp = FRAME_FP (frame); | |
122 | if (frame->dummy) | |
123 | { | |
c5aa993b | 124 | d30v_pop_dummy_frame (frame); |
c906108c SS |
125 | return; |
126 | } | |
127 | ||
128 | /* fill out fsr with the address of where each */ | |
129 | /* register was stored in the frame */ | |
130 | get_frame_saved_regs (frame, &fsr); | |
c5aa993b | 131 | |
c906108c | 132 | /* now update the current registers with the old values */ |
c5aa993b | 133 | for (regnum = A0_REGNUM; regnum < A0_REGNUM + 2; regnum++) |
c906108c SS |
134 | { |
135 | if (fsr.regs[regnum]) | |
136 | { | |
137 | read_memory (fsr.regs[regnum], raw_buffer, 8); | |
138 | write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8); | |
139 | } | |
140 | } | |
141 | for (regnum = 0; regnum < SP_REGNUM; regnum++) | |
142 | { | |
143 | if (fsr.regs[regnum]) | |
144 | { | |
145 | write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4)); | |
146 | } | |
147 | } | |
148 | if (fsr.regs[PSW_REGNUM]) | |
149 | { | |
150 | write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4)); | |
151 | } | |
152 | ||
c5aa993b | 153 | write_register (PC_REGNUM, read_register (LR_REGNUM)); |
c906108c SS |
154 | write_register (SP_REGNUM, fp + frame->size); |
155 | target_store_registers (-1); | |
156 | flush_cached_frames (); | |
157 | } | |
158 | ||
c5aa993b | 159 | static int |
c906108c SS |
160 | check_prologue (op) |
161 | unsigned long op; | |
162 | { | |
163 | /* add sp,sp,imm -- observed */ | |
164 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM) | |
165 | return 1; | |
166 | ||
167 | /* add r22,sp,imm -- observed */ | |
168 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM) | |
169 | return 1; | |
170 | ||
171 | /* or fp,r0,sp -- observed */ | |
172 | if (op == OP_OR_FP_R0_SP) | |
173 | return 1; | |
174 | ||
175 | /* nop */ | |
176 | if ((op & OP_MASK_OPCODE) == OP_NOP) | |
177 | return 1; | |
178 | ||
179 | /* stw Ra,@(sp,r0) */ | |
180 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) | |
181 | return 1; | |
182 | ||
183 | /* stw Ra,@(sp,0x0) */ | |
184 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0) | |
185 | return 1; | |
186 | ||
187 | /* st2w Ra,@(sp,r0) */ | |
c5aa993b JM |
188 | if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) |
189 | return 1; | |
c906108c SS |
190 | |
191 | /* st2w Ra,@(sp,0x0) */ | |
c5aa993b JM |
192 | if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0) |
193 | return 1; | |
c906108c | 194 | |
c5aa993b JM |
195 | /* stw fp, @(r22+,r0) -- observed */ |
196 | if (op == OP_STW_FP_R22P_R0) | |
197 | return 1; | |
c906108c | 198 | |
c5aa993b JM |
199 | /* stw r62, @(r22+,r0) -- observed */ |
200 | if (op == OP_STW_LR_R22P_R0) | |
201 | return 1; | |
c906108c | 202 | |
c5aa993b JM |
203 | /* stw Ra, @(fp,r0) -- observed */ |
204 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0) | |
205 | return 1; /* first arg */ | |
c906108c | 206 | |
c5aa993b JM |
207 | /* stw Ra, @(fp,imm) -- observed */ |
208 | if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM) | |
209 | return 1; /* second and subsequent args */ | |
c906108c | 210 | |
c5aa993b JM |
211 | /* stw fp,@(sp,imm) -- observed */ |
212 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM) | |
213 | return 1; | |
c906108c | 214 | |
c5aa993b JM |
215 | /* st2w Ra,@(r22+,r0) */ |
216 | if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0) | |
217 | return 1; | |
c906108c SS |
218 | |
219 | /* stw Ra, @(sp-) */ | |
220 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM) | |
221 | return 1; | |
222 | ||
223 | /* st2w Ra, @(sp-) */ | |
224 | if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM) | |
225 | return 1; | |
226 | ||
227 | /* sub.? sp,sp,imm */ | |
228 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM) | |
229 | return 1; | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | CORE_ADDR | |
235 | d30v_skip_prologue (pc) | |
236 | CORE_ADDR pc; | |
237 | { | |
238 | unsigned long op[2]; | |
239 | unsigned long opl, opr; /* left / right sub operations */ | |
240 | unsigned long fm0, fm1; /* left / right mode bits */ | |
241 | unsigned long cc0, cc1; | |
242 | unsigned long op1, op2; | |
243 | CORE_ADDR func_addr, func_end; | |
244 | struct symtab_and_line sal; | |
245 | ||
246 | /* If we have line debugging information, then the end of the */ | |
247 | /* prologue should the first assembly instruction of the first source line */ | |
248 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
249 | { | |
250 | sal = find_pc_line (func_addr, 0); | |
c5aa993b | 251 | if (sal.end && sal.end < func_end) |
c906108c SS |
252 | return sal.end; |
253 | } | |
c5aa993b JM |
254 | |
255 | if (target_read_memory (pc, (char *) &op[0], 8)) | |
c906108c SS |
256 | return pc; /* Can't access it -- assume no prologue. */ |
257 | ||
258 | while (1) | |
259 | { | |
c5aa993b JM |
260 | opl = (unsigned long) read_memory_integer (pc, 4); |
261 | opr = (unsigned long) read_memory_integer (pc + 4, 4); | |
c906108c SS |
262 | |
263 | fm0 = (opl & OP_MASK_FM_BIT); | |
264 | fm1 = (opr & OP_MASK_FM_BIT); | |
265 | ||
266 | cc0 = (opl & OP_MASK_CC_BITS); | |
267 | cc1 = (opr & OP_MASK_CC_BITS); | |
268 | ||
269 | opl = (opl & OP_MASK_SUB_INST); | |
270 | opr = (opr & OP_MASK_SUB_INST); | |
271 | ||
272 | if (fm0 && fm1) | |
273 | { | |
274 | /* long instruction (opl contains the opcode) */ | |
c5aa993b JM |
275 | if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */ |
276 | ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */ | |
277 | ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */ | |
278 | ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */ | |
c906108c SS |
279 | break; |
280 | } | |
281 | else | |
282 | { | |
283 | /* short instructions */ | |
284 | if (fm0 && !fm1) | |
285 | { | |
286 | op1 = opr; | |
287 | op2 = opl; | |
c5aa993b JM |
288 | } |
289 | else | |
c906108c SS |
290 | { |
291 | op1 = opl; | |
292 | op2 = opr; | |
293 | } | |
c5aa993b | 294 | if (check_prologue (op1)) |
c906108c | 295 | { |
c5aa993b | 296 | if (!check_prologue (op2)) |
c906108c SS |
297 | { |
298 | /* if the previous opcode was really part of the prologue */ | |
299 | /* and not just a NOP, then we want to break after both instructions */ | |
300 | if ((op1 & OP_MASK_OPCODE) != OP_NOP) | |
301 | pc += 8; | |
302 | break; | |
303 | } | |
304 | } | |
305 | else | |
306 | break; | |
307 | } | |
308 | pc += 8; | |
309 | } | |
310 | return pc; | |
311 | } | |
312 | ||
313 | static int end_of_stack; | |
314 | ||
315 | /* Given a GDB frame, determine the address of the calling function's frame. | |
316 | This will be used to create a new GDB frame struct, and then | |
317 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
c5aa993b | 318 | */ |
c906108c SS |
319 | |
320 | CORE_ADDR | |
321 | d30v_frame_chain (frame) | |
322 | struct frame_info *frame; | |
323 | { | |
324 | struct frame_saved_regs fsr; | |
325 | ||
326 | d30v_frame_find_saved_regs (frame, &fsr); | |
327 | ||
328 | if (end_of_stack) | |
c5aa993b | 329 | return (CORE_ADDR) 0; |
c906108c SS |
330 | |
331 | if (frame->return_pc == IMEM_START) | |
c5aa993b | 332 | return (CORE_ADDR) 0; |
c906108c SS |
333 | |
334 | if (!fsr.regs[FP_REGNUM]) | |
335 | { | |
336 | if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START) | |
c5aa993b JM |
337 | return (CORE_ADDR) 0; |
338 | ||
c906108c SS |
339 | return fsr.regs[SP_REGNUM]; |
340 | } | |
341 | ||
c5aa993b JM |
342 | if (!read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4)) |
343 | return (CORE_ADDR) 0; | |
c906108c | 344 | |
c5aa993b JM |
345 | return read_memory_unsigned_integer (fsr.regs[FP_REGNUM], 4); |
346 | } | |
c906108c SS |
347 | |
348 | static int next_addr, uses_frame; | |
349 | static int frame_size; | |
350 | ||
c5aa993b | 351 | static int |
c906108c SS |
352 | prologue_find_regs (op, fsr, addr) |
353 | unsigned long op; | |
354 | struct frame_saved_regs *fsr; | |
355 | CORE_ADDR addr; | |
356 | { | |
357 | int n; | |
358 | int offset; | |
359 | ||
360 | /* add sp,sp,imm -- observed */ | |
361 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM) | |
362 | { | |
c5aa993b JM |
363 | offset = EXTRACT_IMM6 (op); |
364 | /*next_addr += offset; */ | |
c906108c SS |
365 | frame_size += -offset; |
366 | return 1; | |
367 | } | |
368 | ||
369 | /* add r22,sp,imm -- observed */ | |
370 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM) | |
371 | { | |
c5aa993b | 372 | offset = EXTRACT_IMM6 (op); |
c906108c SS |
373 | next_addr = (offset - frame_size); |
374 | return 1; | |
375 | } | |
376 | ||
377 | /* stw Ra, @(fp, offset) -- observed */ | |
378 | if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM) | |
379 | { | |
c5aa993b JM |
380 | n = EXTRACT_RA (op); |
381 | offset = EXTRACT_IMM6 (op); | |
c906108c SS |
382 | fsr->regs[n] = (offset - frame_size); |
383 | return 1; | |
384 | } | |
385 | ||
386 | /* stw Ra, @(fp, r0) -- observed */ | |
387 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0) | |
388 | { | |
c5aa993b JM |
389 | n = EXTRACT_RA (op); |
390 | fsr->regs[n] = (-frame_size); | |
c906108c SS |
391 | return 1; |
392 | } | |
393 | ||
394 | /* or fp,0,sp -- observed */ | |
395 | if ((op == OP_OR_FP_R0_SP) || | |
396 | (op == OP_OR_FP_SP_R0) || | |
397 | (op == OP_OR_FP_IMM0_SP)) | |
398 | { | |
399 | uses_frame = 1; | |
400 | return 1; | |
401 | } | |
402 | ||
403 | /* nop */ | |
404 | if ((op & OP_MASK_OPCODE) == OP_NOP) | |
405 | return 1; | |
406 | ||
407 | /* stw Ra,@(r22+,r0) -- observed */ | |
408 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0) | |
409 | { | |
c5aa993b | 410 | n = EXTRACT_RA (op); |
c906108c SS |
411 | fsr->regs[n] = next_addr; |
412 | next_addr += 4; | |
413 | return 1; | |
414 | } | |
415 | #if 0 /* subsumed in pattern above */ | |
416 | /* stw fp,@(r22+,r0) -- observed */ | |
417 | if (op == OP_STW_FP_R22P_R0) | |
418 | { | |
c5aa993b | 419 | fsr->regs[FP_REGNUM] = next_addr; /* XXX */ |
c906108c SS |
420 | next_addr += 4; |
421 | return 1; | |
422 | } | |
423 | ||
424 | /* stw r62,@(r22+,r0) -- observed */ | |
425 | if (op == OP_STW_LR_R22P_R0) | |
426 | { | |
427 | fsr->regs[LR_REGNUM] = next_addr; | |
428 | next_addr += 4; | |
429 | return 1; | |
430 | } | |
431 | #endif | |
432 | /* st2w Ra,@(r22+,r0) -- observed */ | |
433 | if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0) | |
434 | { | |
c5aa993b | 435 | n = EXTRACT_RA (op); |
c906108c | 436 | fsr->regs[n] = next_addr; |
c5aa993b | 437 | fsr->regs[n + 1] = next_addr + 4; |
c906108c SS |
438 | next_addr += 8; |
439 | return 1; | |
440 | } | |
441 | ||
442 | /* stw rn, @(sp-) */ | |
443 | if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM) | |
444 | { | |
c5aa993b | 445 | n = EXTRACT_RA (op); |
c906108c SS |
446 | fsr->regs[n] = next_addr; |
447 | next_addr -= 4; | |
448 | return 1; | |
449 | } | |
450 | ||
451 | /* st2w Ra, @(sp-) */ | |
452 | else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM) | |
453 | { | |
c5aa993b | 454 | n = EXTRACT_RA (op); |
c906108c | 455 | fsr->regs[n] = next_addr; |
c5aa993b | 456 | fsr->regs[n + 1] = next_addr + 4; |
c906108c SS |
457 | next_addr -= 8; |
458 | return 1; | |
459 | } | |
460 | ||
461 | /* sub sp,sp,imm */ | |
462 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM) | |
463 | { | |
c5aa993b | 464 | offset = EXTRACT_IMM6 (op); |
c906108c SS |
465 | frame_size += -offset; |
466 | return 1; | |
467 | } | |
468 | ||
469 | /* st rn, @(sp,0) -- observed */ | |
470 | if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) || | |
471 | ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)) | |
472 | { | |
c5aa993b JM |
473 | n = EXTRACT_RA (op); |
474 | fsr->regs[n] = (-frame_size); | |
c906108c SS |
475 | return 1; |
476 | } | |
477 | ||
478 | /* st2w rn, @(sp,0) */ | |
479 | if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) || | |
480 | ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)) | |
481 | { | |
c5aa993b JM |
482 | n = EXTRACT_RA (op); |
483 | fsr->regs[n] = (-frame_size); | |
484 | fsr->regs[n + 1] = (-frame_size) + 4; | |
c906108c SS |
485 | return 1; |
486 | } | |
487 | ||
488 | /* stw fp,@(sp,imm) -- observed */ | |
489 | if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM) | |
490 | { | |
c5aa993b | 491 | offset = EXTRACT_IMM6 (op); |
c906108c SS |
492 | fsr->regs[FP_REGNUM] = (offset - frame_size); |
493 | return 1; | |
494 | } | |
495 | return 0; | |
496 | } | |
497 | ||
498 | /* Put here the code to store, into a struct frame_saved_regs, the | |
499 | addresses of the saved registers of frame described by FRAME_INFO. | |
500 | This includes special registers such as pc and fp saved in special | |
501 | ways in the stack frame. sp is even more special: the address we | |
502 | return for it IS the sp for the next frame. */ | |
503 | void | |
504 | d30v_frame_find_saved_regs (fi, fsr) | |
505 | struct frame_info *fi; | |
506 | struct frame_saved_regs *fsr; | |
507 | { | |
508 | CORE_ADDR fp, pc; | |
509 | unsigned long opl, opr; | |
510 | unsigned long op1, op2; | |
511 | unsigned long fm0, fm1; | |
512 | int i; | |
513 | ||
514 | fp = fi->frame; | |
515 | memset (fsr, 0, sizeof (*fsr)); | |
516 | next_addr = 0; | |
517 | frame_size = 0; | |
518 | end_of_stack = 0; | |
519 | ||
520 | uses_frame = 0; | |
521 | ||
522 | d30v_frame_find_saved_regs_offsets (fi, fsr); | |
c5aa993b | 523 | |
c906108c SS |
524 | fi->size = frame_size; |
525 | ||
526 | if (!fp) | |
c5aa993b | 527 | fp = read_register (SP_REGNUM); |
c906108c | 528 | |
c5aa993b | 529 | for (i = 0; i < NUM_REGS - 1; i++) |
c906108c SS |
530 | if (fsr->regs[i]) |
531 | { | |
532 | fsr->regs[i] = fsr->regs[i] + fp + frame_size; | |
533 | } | |
534 | ||
535 | if (fsr->regs[LR_REGNUM]) | |
c5aa993b | 536 | fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4); |
c906108c | 537 | else |
c5aa993b JM |
538 | fi->return_pc = read_register (LR_REGNUM); |
539 | ||
c906108c SS |
540 | /* the SP is not normally (ever?) saved, but check anyway */ |
541 | if (!fsr->regs[SP_REGNUM]) | |
542 | { | |
543 | /* if the FP was saved, that means the current FP is valid, */ | |
544 | /* otherwise, it isn't being used, so we use the SP instead */ | |
545 | if (uses_frame) | |
c5aa993b | 546 | fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size; |
c906108c SS |
547 | else |
548 | { | |
549 | fsr->regs[SP_REGNUM] = fp + fi->size; | |
550 | fi->frameless = 1; | |
551 | fsr->regs[FP_REGNUM] = 0; | |
552 | } | |
553 | } | |
554 | } | |
555 | ||
556 | void | |
557 | d30v_frame_find_saved_regs_offsets (fi, fsr) | |
558 | struct frame_info *fi; | |
559 | struct frame_saved_regs *fsr; | |
560 | { | |
561 | CORE_ADDR fp, pc; | |
562 | unsigned long opl, opr; | |
563 | unsigned long op1, op2; | |
564 | unsigned long fm0, fm1; | |
565 | int i; | |
566 | ||
567 | fp = fi->frame; | |
568 | memset (fsr, 0, sizeof (*fsr)); | |
569 | next_addr = 0; | |
570 | frame_size = 0; | |
571 | end_of_stack = 0; | |
572 | ||
573 | pc = get_pc_function_start (fi->pc); | |
574 | ||
575 | uses_frame = 0; | |
576 | while (pc < fi->pc) | |
577 | { | |
c5aa993b JM |
578 | opl = (unsigned long) read_memory_integer (pc, 4); |
579 | opr = (unsigned long) read_memory_integer (pc + 4, 4); | |
c906108c SS |
580 | |
581 | fm0 = (opl & OP_MASK_FM_BIT); | |
582 | fm1 = (opr & OP_MASK_FM_BIT); | |
583 | ||
584 | opl = (opl & OP_MASK_SUB_INST); | |
585 | opr = (opr & OP_MASK_SUB_INST); | |
586 | ||
587 | if (fm0 && fm1) | |
588 | { | |
589 | /* long instruction */ | |
590 | if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM) | |
591 | { | |
592 | /* add sp,sp,n */ | |
c5aa993b | 593 | long offset = EXTRACT_IMM32 (opl, opr); |
c906108c SS |
594 | frame_size += -offset; |
595 | } | |
596 | else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM) | |
597 | { | |
598 | /* add r22,sp,offset */ | |
c5aa993b | 599 | long offset = EXTRACT_IMM32 (opl, opr); |
c906108c SS |
600 | next_addr = (offset - frame_size); |
601 | } | |
602 | else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM) | |
603 | { | |
604 | /* st Ra, @(sp,imm) */ | |
c5aa993b JM |
605 | long offset = EXTRACT_IMM32 (opl, opr); |
606 | short n = EXTRACT_RA (opl); | |
c906108c SS |
607 | fsr->regs[n] = (offset - frame_size); |
608 | } | |
609 | else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM) | |
610 | { | |
611 | /* st2w Ra, @(sp,offset) */ | |
c5aa993b JM |
612 | long offset = EXTRACT_IMM32 (opl, opr); |
613 | short n = EXTRACT_RA (opl); | |
c906108c | 614 | fsr->regs[n] = (offset - frame_size); |
c5aa993b | 615 | fsr->regs[n + 1] = (offset - frame_size) + 4; |
c906108c SS |
616 | } |
617 | else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_OR_SP_R0_IMM) | |
618 | { | |
619 | end_of_stack = 1; | |
620 | } | |
621 | else | |
622 | break; | |
623 | } | |
624 | else | |
625 | { | |
626 | /* short instructions */ | |
627 | if (fm0 && !fm1) | |
628 | { | |
629 | op2 = opl; | |
630 | op1 = opr; | |
c5aa993b JM |
631 | } |
632 | else | |
c906108c SS |
633 | { |
634 | op1 = opl; | |
635 | op2 = opr; | |
636 | } | |
c5aa993b | 637 | if (!prologue_find_regs (op1, fsr, pc) || !prologue_find_regs (op2, fsr, pc)) |
c906108c SS |
638 | break; |
639 | } | |
640 | pc += 8; | |
641 | } | |
c5aa993b | 642 | |
c906108c SS |
643 | #if 0 |
644 | fi->size = frame_size; | |
645 | ||
646 | if (!fp) | |
c5aa993b | 647 | fp = read_register (SP_REGNUM); |
c906108c | 648 | |
c5aa993b | 649 | for (i = 0; i < NUM_REGS - 1; i++) |
c906108c SS |
650 | if (fsr->regs[i]) |
651 | { | |
652 | fsr->regs[i] = fsr->regs[i] + fp + frame_size; | |
653 | } | |
654 | ||
655 | if (fsr->regs[LR_REGNUM]) | |
c5aa993b | 656 | fi->return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], 4); |
c906108c | 657 | else |
c5aa993b JM |
658 | fi->return_pc = read_register (LR_REGNUM); |
659 | ||
c906108c SS |
660 | /* the SP is not normally (ever?) saved, but check anyway */ |
661 | if (!fsr->regs[SP_REGNUM]) | |
662 | { | |
663 | /* if the FP was saved, that means the current FP is valid, */ | |
664 | /* otherwise, it isn't being used, so we use the SP instead */ | |
665 | if (uses_frame) | |
c5aa993b | 666 | fsr->regs[SP_REGNUM] = read_register (FP_REGNUM) + fi->size; |
c906108c SS |
667 | else |
668 | { | |
669 | fsr->regs[SP_REGNUM] = fp + fi->size; | |
670 | fi->frameless = 1; | |
671 | fsr->regs[FP_REGNUM] = 0; | |
672 | } | |
673 | } | |
674 | #endif | |
675 | } | |
676 | ||
677 | void | |
678 | d30v_init_extra_frame_info (fromleaf, fi) | |
679 | int fromleaf; | |
680 | struct frame_info *fi; | |
681 | { | |
682 | struct frame_saved_regs dummy; | |
683 | ||
684 | if (fi->next && (fi->pc == 0)) | |
c5aa993b | 685 | fi->pc = fi->next->return_pc; |
c906108c SS |
686 | |
687 | d30v_frame_find_saved_regs_offsets (fi, &dummy); | |
688 | ||
689 | if (uses_frame == 0) | |
690 | fi->frameless = 1; | |
691 | else | |
692 | fi->frameless = 0; | |
693 | ||
694 | if ((fi->next == 0) && (uses_frame == 0)) | |
695 | /* innermost frame and it's "frameless", | |
696 | so the fi->frame field is wrong, fix it! */ | |
697 | fi->frame = read_sp (); | |
698 | ||
699 | if (dummy.regs[LR_REGNUM]) | |
700 | { | |
701 | /* it was saved, grab it! */ | |
702 | dummy.regs[LR_REGNUM] += (fi->frame + frame_size); | |
c5aa993b | 703 | fi->return_pc = read_memory_unsigned_integer (dummy.regs[LR_REGNUM], 4); |
c906108c SS |
704 | } |
705 | else | |
c5aa993b | 706 | fi->return_pc = read_register (LR_REGNUM); |
c906108c SS |
707 | } |
708 | ||
709 | void | |
710 | d30v_init_frame_pc (fromleaf, prev) | |
711 | int fromleaf; | |
712 | struct frame_info *prev; | |
713 | { | |
714 | /* default value, put here so we can breakpoint on it and | |
715 | see if the default value is really the right thing to use */ | |
716 | prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \ | |
717 | prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ()); | |
718 | } | |
719 | ||
720 | static void d30v_print_register PARAMS ((int regnum, int tabular)); | |
721 | ||
722 | static void | |
723 | d30v_print_register (regnum, tabular) | |
724 | int regnum; | |
725 | int tabular; | |
726 | { | |
727 | if (regnum < A0_REGNUM) | |
728 | { | |
729 | if (tabular) | |
730 | printf_filtered ("%08x", read_register (regnum)); | |
731 | else | |
732 | printf_filtered ("0x%x %d", read_register (regnum), | |
733 | read_register (regnum)); | |
734 | } | |
735 | else | |
736 | { | |
737 | char regbuf[MAX_REGISTER_RAW_SIZE]; | |
738 | ||
739 | read_relative_register_raw_bytes (regnum, regbuf); | |
740 | ||
741 | val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0, | |
742 | gdb_stdout, 'x', 1, 0, Val_pretty_default); | |
743 | ||
744 | if (!tabular) | |
745 | { | |
746 | printf_filtered (" "); | |
747 | val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0, 0, | |
c5aa993b | 748 | gdb_stdout, 'd', 1, 0, Val_pretty_default); |
c906108c SS |
749 | } |
750 | } | |
751 | } | |
752 | ||
753 | static void | |
754 | d30v_print_flags () | |
755 | { | |
756 | long psw = read_register (PSW_REGNUM); | |
757 | printf_filtered ("flags #1"); | |
758 | printf_filtered (" (sm) %d", (psw & PSW_SM) != 0); | |
759 | printf_filtered (" (ea) %d", (psw & PSW_EA) != 0); | |
760 | printf_filtered (" (db) %d", (psw & PSW_DB) != 0); | |
761 | printf_filtered (" (ds) %d", (psw & PSW_DS) != 0); | |
762 | printf_filtered (" (ie) %d", (psw & PSW_IE) != 0); | |
763 | printf_filtered (" (rp) %d", (psw & PSW_RP) != 0); | |
764 | printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0); | |
765 | ||
766 | printf_filtered ("flags #2"); | |
767 | printf_filtered (" (f0) %d", (psw & PSW_F0) != 0); | |
768 | printf_filtered (" (f1) %d", (psw & PSW_F1) != 0); | |
769 | printf_filtered (" (f2) %d", (psw & PSW_F2) != 0); | |
770 | printf_filtered (" (f3) %d", (psw & PSW_F3) != 0); | |
771 | printf_filtered (" (s) %d", (psw & PSW_S) != 0); | |
772 | printf_filtered (" (v) %d", (psw & PSW_V) != 0); | |
773 | printf_filtered (" (va) %d", (psw & PSW_VA) != 0); | |
774 | printf_filtered (" (c) %d\n", (psw & PSW_C) != 0); | |
775 | } | |
776 | ||
777 | static void | |
778 | print_flags_command (args, from_tty) | |
779 | char *args; | |
780 | int from_tty; | |
781 | { | |
782 | d30v_print_flags (); | |
783 | } | |
784 | ||
785 | void | |
786 | d30v_do_registers_info (regnum, fpregs) | |
787 | int regnum; | |
788 | int fpregs; | |
789 | { | |
790 | long long num1, num2; | |
791 | long psw; | |
792 | ||
793 | if (regnum != -1) | |
794 | { | |
795 | if (REGISTER_NAME (0) == NULL || REGISTER_NAME (0)[0] == '\000') | |
796 | return; | |
797 | ||
798 | printf_filtered ("%s ", REGISTER_NAME (regnum)); | |
799 | d30v_print_register (regnum, 0); | |
800 | ||
801 | printf_filtered ("\n"); | |
802 | return; | |
803 | } | |
804 | ||
805 | /* Have to print all the registers. Format them nicely. */ | |
806 | ||
807 | printf_filtered ("PC="); | |
808 | print_address (read_pc (), gdb_stdout); | |
809 | ||
810 | printf_filtered (" PSW="); | |
811 | d30v_print_register (PSW_REGNUM, 1); | |
812 | ||
813 | printf_filtered (" BPC="); | |
814 | print_address (read_register (BPC_REGNUM), gdb_stdout); | |
815 | ||
816 | printf_filtered (" BPSW="); | |
817 | d30v_print_register (BPSW_REGNUM, 1); | |
818 | printf_filtered ("\n"); | |
819 | ||
820 | printf_filtered ("DPC="); | |
821 | print_address (read_register (DPC_REGNUM), gdb_stdout); | |
822 | ||
823 | printf_filtered (" DPSW="); | |
824 | d30v_print_register (DPSW_REGNUM, 1); | |
825 | ||
826 | printf_filtered (" IBA="); | |
827 | print_address (read_register (IBA_REGNUM), gdb_stdout); | |
828 | printf_filtered ("\n"); | |
829 | ||
830 | printf_filtered ("RPT_C="); | |
831 | d30v_print_register (RPT_C_REGNUM, 1); | |
832 | ||
833 | printf_filtered (" RPT_S="); | |
834 | print_address (read_register (RPT_S_REGNUM), gdb_stdout); | |
835 | ||
836 | printf_filtered (" RPT_E="); | |
837 | print_address (read_register (RPT_E_REGNUM), gdb_stdout); | |
838 | printf_filtered ("\n"); | |
839 | ||
840 | printf_filtered ("MOD_S="); | |
841 | print_address (read_register (MOD_S_REGNUM), gdb_stdout); | |
842 | ||
843 | printf_filtered (" MOD_E="); | |
844 | print_address (read_register (MOD_E_REGNUM), gdb_stdout); | |
845 | printf_filtered ("\n"); | |
846 | ||
847 | printf_filtered ("EIT_VB="); | |
848 | print_address (read_register (EIT_VB_REGNUM), gdb_stdout); | |
849 | ||
850 | printf_filtered (" INT_S="); | |
851 | d30v_print_register (INT_S_REGNUM, 1); | |
852 | ||
853 | printf_filtered (" INT_M="); | |
854 | d30v_print_register (INT_M_REGNUM, 1); | |
855 | printf_filtered ("\n"); | |
856 | ||
857 | d30v_print_flags (); | |
858 | for (regnum = 0; regnum <= 63;) | |
859 | { | |
860 | int i; | |
861 | ||
862 | printf_filtered ("R%d-R%d ", regnum, regnum + 7); | |
863 | if (regnum < 10) | |
864 | printf_filtered (" "); | |
865 | if (regnum + 7 < 10) | |
866 | printf_filtered (" "); | |
867 | ||
868 | for (i = 0; i < 8; i++) | |
869 | { | |
870 | printf_filtered (" "); | |
871 | d30v_print_register (regnum++, 1); | |
872 | } | |
873 | ||
874 | printf_filtered ("\n"); | |
875 | } | |
876 | ||
877 | printf_filtered ("A0-A1 "); | |
878 | ||
879 | d30v_print_register (A0_REGNUM, 1); | |
880 | printf_filtered (" "); | |
881 | d30v_print_register (A1_REGNUM, 1); | |
882 | printf_filtered ("\n"); | |
883 | } | |
884 | ||
885 | CORE_ADDR | |
886 | d30v_fix_call_dummy (dummyname, start_sp, fun, nargs, args, type, gcc_p) | |
887 | char *dummyname; | |
888 | CORE_ADDR start_sp; | |
889 | CORE_ADDR fun; | |
890 | int nargs; | |
891 | value_ptr *args; | |
892 | struct type *type; | |
893 | int gcc_p; | |
894 | { | |
895 | int regnum; | |
896 | CORE_ADDR sp; | |
897 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
898 | struct frame_info *frame = get_current_frame (); | |
899 | frame->dummy = start_sp; | |
c5aa993b | 900 | /*start_sp |= DMEM_START; */ |
c906108c SS |
901 | |
902 | sp = start_sp; | |
903 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
904 | { | |
c5aa993b JM |
905 | sp -= REGISTER_RAW_SIZE (regnum); |
906 | store_address (buffer, REGISTER_RAW_SIZE (regnum), read_register (regnum)); | |
907 | write_memory (sp, buffer, REGISTER_RAW_SIZE (regnum)); | |
c906108c | 908 | } |
c5aa993b | 909 | write_register (SP_REGNUM, (LONGEST) sp); |
c906108c | 910 | /* now we need to load LR with the return address */ |
c5aa993b | 911 | write_register (LR_REGNUM, (LONGEST) d30v_call_dummy_address ()); |
c906108c SS |
912 | return sp; |
913 | } | |
914 | ||
915 | static void | |
916 | d30v_pop_dummy_frame (fi) | |
917 | struct frame_info *fi; | |
918 | { | |
919 | CORE_ADDR sp = fi->dummy; | |
920 | int regnum; | |
921 | ||
922 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
923 | { | |
c5aa993b JM |
924 | sp -= REGISTER_RAW_SIZE (regnum); |
925 | write_register (regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE (regnum))); | |
c906108c | 926 | } |
c5aa993b | 927 | flush_cached_frames (); /* needed? */ |
c906108c SS |
928 | } |
929 | ||
930 | ||
931 | CORE_ADDR | |
932 | d30v_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
933 | int nargs; | |
934 | value_ptr *args; | |
935 | CORE_ADDR sp; | |
936 | int struct_return; | |
937 | CORE_ADDR struct_addr; | |
938 | { | |
c5aa993b | 939 | int i, len, index = 0, regnum = 2; |
c906108c SS |
940 | char buffer[4], *contents; |
941 | LONGEST val; | |
942 | CORE_ADDR ptrs[10]; | |
943 | ||
944 | #if 0 | |
945 | /* Pass 1. Put all large args on stack */ | |
946 | for (i = 0; i < nargs; i++) | |
947 | { | |
948 | value_ptr arg = args[i]; | |
949 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
950 | len = TYPE_LENGTH (arg_type); | |
c5aa993b | 951 | contents = VALUE_CONTENTS (arg); |
c906108c SS |
952 | val = extract_signed_integer (contents, len); |
953 | if (len > 4) | |
954 | { | |
955 | /* put on stack and pass pointers */ | |
956 | sp -= len; | |
957 | write_memory (sp, contents, len); | |
958 | ptrs[index++] = sp; | |
959 | } | |
960 | } | |
961 | #endif | |
962 | index = 0; | |
963 | ||
964 | for (i = 0; i < nargs; i++) | |
965 | { | |
966 | value_ptr arg = args[i]; | |
967 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
968 | len = TYPE_LENGTH (arg_type); | |
c5aa993b | 969 | contents = VALUE_CONTENTS (arg); |
c906108c SS |
970 | if (len > 4) |
971 | { | |
972 | /* we need multiple registers */ | |
973 | int ndx; | |
974 | ||
975 | for (ndx = 0; len > 0; ndx += 8, len -= 8) | |
976 | { | |
977 | if (regnum & 1) | |
978 | regnum++; /* all args > 4 bytes start in even register */ | |
979 | ||
980 | if (regnum < 18) | |
981 | { | |
982 | val = extract_signed_integer (&contents[ndx], 4); | |
983 | write_register (regnum++, val); | |
984 | ||
985 | if (len >= 8) | |
c5aa993b | 986 | val = extract_signed_integer (&contents[ndx + 4], 4); |
c906108c | 987 | else |
c5aa993b | 988 | val = extract_signed_integer (&contents[ndx + 4], len - 4); |
c906108c SS |
989 | write_register (regnum++, val); |
990 | } | |
991 | else | |
992 | { | |
993 | /* no more registers available. put it on the stack */ | |
994 | ||
995 | /* all args > 4 bytes are padded to a multiple of 8 bytes | |
c5aa993b | 996 | and start on an 8 byte boundary */ |
c906108c | 997 | if (sp & 7) |
c5aa993b | 998 | sp -= (sp & 7); /* align it */ |
c906108c | 999 | |
c5aa993b | 1000 | sp -= ((len + 7) & ~7); /* allocate space */ |
c906108c SS |
1001 | write_memory (sp, &contents[ndx], len); |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | } | |
1006 | else | |
1007 | { | |
c5aa993b | 1008 | if (regnum < 18) |
c906108c SS |
1009 | { |
1010 | val = extract_signed_integer (contents, len); | |
1011 | write_register (regnum++, val); | |
1012 | } | |
1013 | else | |
1014 | { | |
1015 | /* all args are padded to a multiple of 4 bytes (at least) */ | |
1016 | sp -= ((len + 3) & ~3); | |
1017 | write_memory (sp, contents, len); | |
1018 | } | |
1019 | } | |
1020 | } | |
1021 | if (sp & 7) | |
1022 | /* stack pointer is not on an 8 byte boundary -- align it */ | |
1023 | sp -= (sp & 7); | |
1024 | return sp; | |
1025 | } | |
1026 | ||
1027 | ||
1028 | /* pick an out-of-the-way place to set the return value */ | |
1029 | /* for an inferior function call. The link register is set to this */ | |
1030 | /* value and a momentary breakpoint is set there. When the breakpoint */ | |
1031 | /* is hit, the dummy frame is popped and the previous environment is */ | |
1032 | /* restored. */ | |
1033 | ||
1034 | CORE_ADDR | |
1035 | d30v_call_dummy_address () | |
1036 | { | |
1037 | CORE_ADDR entry; | |
1038 | struct minimal_symbol *sym; | |
1039 | ||
1040 | entry = entry_point_address (); | |
1041 | ||
1042 | if (entry != 0) | |
1043 | return entry; | |
1044 | ||
1045 | sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile); | |
1046 | ||
1047 | if (!sym || MSYMBOL_TYPE (sym) != mst_text) | |
1048 | return 0; | |
1049 | else | |
1050 | return SYMBOL_VALUE_ADDRESS (sym); | |
1051 | } | |
1052 | ||
1053 | /* Given a return value in `regbuf' with a type `valtype', | |
1054 | extract and copy its value into `valbuf'. */ | |
1055 | ||
1056 | void | |
1057 | d30v_extract_return_value (valtype, regbuf, valbuf) | |
1058 | struct type *valtype; | |
1059 | char regbuf[REGISTER_BYTES]; | |
1060 | char *valbuf; | |
1061 | { | |
1062 | memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype)); | |
1063 | } | |
1064 | ||
1065 | /* The following code implements access to, and display of, the D30V's | |
1066 | instruction trace buffer. The buffer consists of 64K or more | |
1067 | 4-byte words of data, of which each words includes an 8-bit count, | |
1068 | an 8-bit segment number, and a 16-bit instruction address. | |
1069 | ||
1070 | In theory, the trace buffer is continuously capturing instruction | |
1071 | data that the CPU presents on its "debug bus", but in practice, the | |
1072 | ROMified GDB stub only enables tracing when it continues or steps | |
1073 | the program, and stops tracing when the program stops; so it | |
1074 | actually works for GDB to read the buffer counter out of memory and | |
1075 | then read each trace word. The counter records where the tracing | |
1076 | stops, but there is no record of where it started, so we remember | |
1077 | the PC when we resumed and then search backwards in the trace | |
1078 | buffer for a word that includes that address. This is not perfect, | |
1079 | because you will miss trace data if the resumption PC is the target | |
1080 | of a branch. (The value of the buffer counter is semi-random, any | |
1081 | trace data from a previous program stop is gone.) */ | |
1082 | ||
1083 | /* The address of the last word recorded in the trace buffer. */ | |
1084 | ||
1085 | #define DBBC_ADDR (0xd80000) | |
1086 | ||
1087 | /* The base of the trace buffer, at least for the "Board_0". */ | |
1088 | ||
1089 | #define TRACE_BUFFER_BASE (0xf40000) | |
1090 | ||
1091 | static void trace_command PARAMS ((char *, int)); | |
1092 | ||
1093 | static void untrace_command PARAMS ((char *, int)); | |
1094 | ||
1095 | static void trace_info PARAMS ((char *, int)); | |
1096 | ||
1097 | static void tdisassemble_command PARAMS ((char *, int)); | |
1098 | ||
1099 | static void display_trace PARAMS ((int, int)); | |
1100 | ||
1101 | /* True when instruction traces are being collected. */ | |
1102 | ||
1103 | static int tracing; | |
1104 | ||
1105 | /* Remembered PC. */ | |
1106 | ||
1107 | static CORE_ADDR last_pc; | |
1108 | ||
1109 | /* True when trace output should be displayed whenever program stops. */ | |
1110 | ||
1111 | static int trace_display; | |
1112 | ||
1113 | /* True when trace listing should include source lines. */ | |
1114 | ||
1115 | static int default_trace_show_source = 1; | |
1116 | ||
c5aa993b JM |
1117 | struct trace_buffer |
1118 | { | |
1119 | int size; | |
1120 | short *counts; | |
1121 | CORE_ADDR *addrs; | |
1122 | } | |
1123 | trace_data; | |
c906108c SS |
1124 | |
1125 | static void | |
1126 | trace_command (args, from_tty) | |
1127 | char *args; | |
1128 | int from_tty; | |
1129 | { | |
1130 | /* Clear the host-side trace buffer, allocating space if needed. */ | |
1131 | trace_data.size = 0; | |
1132 | if (trace_data.counts == NULL) | |
c5aa993b | 1133 | trace_data.counts = (short *) xmalloc (65536 * sizeof (short)); |
c906108c | 1134 | if (trace_data.addrs == NULL) |
c5aa993b | 1135 | trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof (CORE_ADDR)); |
c906108c SS |
1136 | |
1137 | tracing = 1; | |
1138 | ||
1139 | printf_filtered ("Tracing is now on.\n"); | |
1140 | } | |
1141 | ||
1142 | static void | |
1143 | untrace_command (args, from_tty) | |
1144 | char *args; | |
1145 | int from_tty; | |
1146 | { | |
1147 | tracing = 0; | |
1148 | ||
1149 | printf_filtered ("Tracing is now off.\n"); | |
1150 | } | |
1151 | ||
1152 | static void | |
1153 | trace_info (args, from_tty) | |
1154 | char *args; | |
1155 | int from_tty; | |
1156 | { | |
1157 | int i; | |
1158 | ||
1159 | if (trace_data.size) | |
1160 | { | |
1161 | printf_filtered ("%d entries in trace buffer:\n", trace_data.size); | |
1162 | ||
1163 | for (i = 0; i < trace_data.size; ++i) | |
1164 | { | |
1165 | printf_filtered ("%d: %d instruction%s at 0x%x\n", | |
1166 | i, trace_data.counts[i], | |
1167 | (trace_data.counts[i] == 1 ? "" : "s"), | |
1168 | trace_data.addrs[i]); | |
1169 | } | |
1170 | } | |
1171 | else | |
1172 | printf_filtered ("No entries in trace buffer.\n"); | |
1173 | ||
1174 | printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); | |
1175 | } | |
1176 | ||
1177 | /* Print the instruction at address MEMADDR in debugged memory, | |
1178 | on STREAM. Returns length of the instruction, in bytes. */ | |
1179 | ||
1180 | static int | |
1181 | print_insn (memaddr, stream) | |
1182 | CORE_ADDR memaddr; | |
1183 | GDB_FILE *stream; | |
1184 | { | |
1185 | /* If there's no disassembler, something is very wrong. */ | |
1186 | if (tm_print_insn == NULL) | |
1187 | abort (); | |
1188 | ||
1189 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1190 | tm_print_insn_info.endian = BFD_ENDIAN_BIG; | |
1191 | else | |
1192 | tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; | |
1193 | return (*tm_print_insn) (memaddr, &tm_print_insn_info); | |
1194 | } | |
1195 | ||
1196 | void | |
1197 | d30v_eva_prepare_to_trace () | |
1198 | { | |
1199 | if (!tracing) | |
1200 | return; | |
1201 | ||
1202 | last_pc = read_register (PC_REGNUM); | |
1203 | } | |
1204 | ||
1205 | /* Collect trace data from the target board and format it into a form | |
1206 | more useful for display. */ | |
1207 | ||
1208 | void | |
1209 | d30v_eva_get_trace_data () | |
1210 | { | |
1211 | int count, i, j, oldsize; | |
1212 | int trace_addr, trace_seg, trace_cnt, next_cnt; | |
1213 | unsigned int last_trace, trace_word, next_word; | |
1214 | unsigned int *tmpspace; | |
1215 | ||
1216 | if (!tracing) | |
1217 | return; | |
1218 | ||
c5aa993b | 1219 | tmpspace = xmalloc (65536 * sizeof (unsigned int)); |
c906108c SS |
1220 | |
1221 | last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; | |
1222 | ||
1223 | /* Collect buffer contents from the target, stopping when we reach | |
1224 | the word recorded when execution resumed. */ | |
1225 | ||
1226 | count = 0; | |
1227 | while (last_trace > 0) | |
1228 | { | |
1229 | QUIT; | |
1230 | trace_word = | |
1231 | read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4); | |
1232 | trace_addr = trace_word & 0xffff; | |
1233 | last_trace -= 4; | |
1234 | /* Ignore an apparently nonsensical entry. */ | |
1235 | if (trace_addr == 0xffd5) | |
1236 | continue; | |
1237 | tmpspace[count++] = trace_word; | |
1238 | if (trace_addr == last_pc) | |
1239 | break; | |
1240 | if (count > 65535) | |
1241 | break; | |
1242 | } | |
1243 | ||
1244 | /* Move the data to the host-side trace buffer, adjusting counts to | |
1245 | include the last instruction executed and transforming the address | |
1246 | into something that GDB likes. */ | |
1247 | ||
1248 | for (i = 0; i < count; ++i) | |
1249 | { | |
1250 | trace_word = tmpspace[i]; | |
1251 | next_word = ((i == 0) ? 0 : tmpspace[i - 1]); | |
1252 | trace_addr = trace_word & 0xffff; | |
1253 | next_cnt = (next_word >> 24) & 0xff; | |
1254 | j = trace_data.size + count - i - 1; | |
1255 | trace_data.addrs[j] = (trace_addr << 2) + 0x1000000; | |
1256 | trace_data.counts[j] = next_cnt + 1; | |
1257 | } | |
1258 | ||
1259 | oldsize = trace_data.size; | |
1260 | trace_data.size += count; | |
1261 | ||
1262 | free (tmpspace); | |
1263 | ||
1264 | if (trace_display) | |
1265 | display_trace (oldsize, trace_data.size); | |
1266 | } | |
1267 | ||
1268 | static void | |
1269 | tdisassemble_command (arg, from_tty) | |
1270 | char *arg; | |
1271 | int from_tty; | |
1272 | { | |
1273 | int i, count; | |
1274 | CORE_ADDR low, high; | |
1275 | char *space_index; | |
1276 | ||
1277 | if (!arg) | |
1278 | { | |
1279 | low = 0; | |
1280 | high = trace_data.size; | |
1281 | } | |
1282 | else if (!(space_index = (char *) strchr (arg, ' '))) | |
1283 | { | |
1284 | low = parse_and_eval_address (arg); | |
1285 | high = low + 5; | |
1286 | } | |
1287 | else | |
1288 | { | |
1289 | /* Two arguments. */ | |
1290 | *space_index = '\0'; | |
1291 | low = parse_and_eval_address (arg); | |
1292 | high = parse_and_eval_address (space_index + 1); | |
1293 | if (high < low) | |
1294 | high = low; | |
1295 | } | |
1296 | ||
1297 | printf_filtered ("Dump of trace from %d to %d:\n", low, high); | |
1298 | ||
1299 | display_trace (low, high); | |
1300 | ||
1301 | printf_filtered ("End of trace dump.\n"); | |
1302 | gdb_flush (gdb_stdout); | |
1303 | } | |
1304 | ||
1305 | static void | |
1306 | display_trace (low, high) | |
1307 | int low, high; | |
1308 | { | |
1309 | int i, count, trace_show_source, first, suppress; | |
1310 | CORE_ADDR next_address; | |
1311 | ||
1312 | trace_show_source = default_trace_show_source; | |
c5aa993b | 1313 | if (!have_full_symbols () && !have_partial_symbols ()) |
c906108c SS |
1314 | { |
1315 | trace_show_source = 0; | |
1316 | printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); | |
1317 | printf_filtered ("Trace will not display any source.\n"); | |
1318 | } | |
1319 | ||
1320 | first = 1; | |
1321 | suppress = 0; | |
1322 | for (i = low; i < high; ++i) | |
1323 | { | |
1324 | next_address = trace_data.addrs[i]; | |
c5aa993b | 1325 | count = trace_data.counts[i]; |
c906108c SS |
1326 | while (count-- > 0) |
1327 | { | |
1328 | QUIT; | |
1329 | if (trace_show_source) | |
1330 | { | |
1331 | struct symtab_and_line sal, sal_prev; | |
1332 | ||
1333 | sal_prev = find_pc_line (next_address - 4, 0); | |
1334 | sal = find_pc_line (next_address, 0); | |
1335 | ||
1336 | if (sal.symtab) | |
1337 | { | |
1338 | if (first || sal.line != sal_prev.line) | |
1339 | print_source_lines (sal.symtab, sal.line, sal.line + 1, 0); | |
1340 | suppress = 0; | |
1341 | } | |
1342 | else | |
1343 | { | |
1344 | if (!suppress) | |
1345 | /* FIXME-32x64--assumes sal.pc fits in long. */ | |
1346 | printf_filtered ("No source file for address %s.\n", | |
c5aa993b | 1347 | local_hex_string ((unsigned long) sal.pc)); |
c906108c SS |
1348 | suppress = 1; |
1349 | } | |
1350 | } | |
1351 | first = 0; | |
1352 | print_address (next_address, gdb_stdout); | |
1353 | printf_filtered (":"); | |
1354 | printf_filtered ("\t"); | |
1355 | wrap_here (" "); | |
1356 | next_address = next_address + print_insn (next_address, gdb_stdout); | |
1357 | printf_filtered ("\n"); | |
1358 | gdb_flush (gdb_stdout); | |
1359 | } | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | extern void (*target_resume_hook) PARAMS ((void)); | |
1364 | extern void (*target_wait_loop_hook) PARAMS ((void)); | |
1365 | ||
1366 | void | |
1367 | _initialize_d30v_tdep () | |
1368 | { | |
1369 | tm_print_insn = print_insn_d30v; | |
1370 | ||
1371 | target_resume_hook = d30v_eva_prepare_to_trace; | |
1372 | target_wait_loop_hook = d30v_eva_get_trace_data; | |
1373 | ||
1374 | add_info ("flags", print_flags_command, "Print d30v flags."); | |
1375 | ||
1376 | add_com ("trace", class_support, trace_command, | |
1377 | "Enable tracing of instruction execution."); | |
1378 | ||
1379 | add_com ("untrace", class_support, untrace_command, | |
c5aa993b | 1380 | "Disable tracing of instruction execution."); |
c906108c SS |
1381 | |
1382 | add_com ("tdisassemble", class_vars, tdisassemble_command, | |
1383 | "Disassemble the trace buffer.\n\ | |
1384 | Two optional arguments specify a range of trace buffer entries\n\ | |
1385 | as reported by info trace (NOT addresses!)."); | |
1386 | ||
1387 | add_info ("trace", trace_info, | |
1388 | "Display info about the trace data buffer."); | |
1389 | ||
1390 | add_show_from_set (add_set_cmd ("tracedisplay", no_class, | |
c5aa993b JM |
1391 | var_integer, (char *) &trace_display, |
1392 | "Set automatic display of trace.\n", &setlist), | |
c906108c SS |
1393 | &showlist); |
1394 | add_show_from_set (add_set_cmd ("tracesource", no_class, | |
c5aa993b JM |
1395 | var_integer, (char *) &default_trace_show_source, |
1396 | "Set display of source code with trace.\n", &setlist), | |
c906108c SS |
1397 | &showlist); |
1398 | ||
c5aa993b | 1399 | } |