projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* config-ml.in (multi-do): LDFLAGS must include multilib
[deliverable/binutils-gdb.git] / gdb / d30v-tdep.c
CommitLineData
45a70ed6
SG		 1/* Target-dependent code for Mitsubishi D30V, for GDB.
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4This file is part of GDB.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20/* Contributed by Martin Hunt, hunt@cygnus.com */
21
22#include "defs.h"
23#include "frame.h"
24#include "obstack.h"
25#include "symtab.h"
26#include "gdbtypes.h"
27#include "gdbcmd.h"
28#include "gdbcore.h"
29#include "gdb_string.h"
30#include "value.h"
31#include "inferior.h"
32#include "dis-asm.h"
33#include "symfile.h"
34#include "objfiles.h"
35
36void d30v_frame_find_saved_regs PARAMS ((struct frame_info *fi,
37 struct frame_saved_regs *fsr));
38static void d30v_pop_dummy_frame PARAMS ((struct frame_info *fi));
5d62f957
MM		 39static void d30v_print_flags PARAMS ((void));
40static void print_flags_command PARAMS ((char *, int));
45a70ed6 41
7359fb1d
DT		 42/* the following defines assume:
43 fp is r61, lr is r62, sp is r63, and ?? is r22
44 if that changes, they will need to be updated */
45
46#define OP_MASK_ALL_BUT_RA 0x0ffc0fff /* throw away Ra, keep the rest */
47
48#define OP_STW_SPM 0x054c0fc0 /* stw Ra, @(sp-) */
49#define OP_STW_SP_R0 0x05400fc0 /* stw Ra, @(sp,r0) */
50#define OP_STW_SP_IMM0 0x05480fc0 /* st Ra, @(sp, 0x0) */
51#define OP_STW_R22P_R0 0x05440580 /* stw Ra, @(r22+,r0) */
52
53#define OP_ST2W_SPM 0x056c0fc0 /* st2w Ra, @(sp-) */
54#define OP_ST2W_SP_R0 0x05600fc0 /* st2w Ra, @(sp, r0) */
55#define OP_ST2W_SP_IMM0 0x05680fc0 /* st2w Ra, @(sp, 0x0) */
56#define OP_ST2W_R22P_R0 0x05640580 /* st2w Ra, @(r22+, r0) */
57
58#define OP_MASK_OPCODE 0x0ffc0000 /* just the opcode, ign operands */
59#define OP_NOP 0x00f00000 /* nop */
60
61#define OP_MASK_ALL_BUT_IMM 0x0fffffc0 /* throw away imm, keep the rest */
62#define OP_SUB_SP_IMM 0x082bffc0 /* sub sp,sp,imm */
63#define OP_ADD_SP_IMM 0x080bffc0 /* add sp,sp,imm */
64#define OP_ADD_R22_SP_IMM 0x08096fc0 /* add r22,sp,imm */
65#define OP_STW_FP_SP_IMM 0x054bdfc0 /* stw fp,@(sp,imm) */
36985eca 66#define OP_OR_SP_R0_IMM 0x03abf000 /* or sp,r0,imm */
7359fb1d
DT		 67
68/* no mask */
69#define OP_OR_FP_R0_SP 0x03a3d03f /* or fp,r0,sp */
70#define OP_OR_FP_SP_R0 0x03a3dfc0 /* or fp,sp,r0 */
71#define OP_OR_FP_IMM0_SP 0x03abd03f /* or fp,0x0,sp */
72#define OP_STW_FP_R22P_R0 0x0547d580 /* stw fp,@(r22+,r0) */
73#define OP_STW_LR_R22P_R0 0x0547e580 /* stw lr,@(r22+,r0) */
74
75#define OP_MASK_OP_AND_RB 0x0ff80fc0 /* keep op and rb,throw away rest */
76#define OP_STW_SP_IMM 0x05480fc0 /* stw Ra,@(sp,imm) */
77#define OP_ST2W_SP_IMM 0x05680fc0 /* st2w Ra,@(sp,imm) */
78#define OP_STW_FP_IMM 0x05480f40 /* stw Ra,@(fp,imm) */
79#define OP_STW_FP_R0 0x05400f40 /* stw Ra,@(fp,r0) */
80
81#define OP_MASK_FM_BIT 0x80000000
82#define OP_MASK_CC_BITS 0x70000000
83#define OP_MASK_SUB_INST 0x0fffffff
84
85#define EXTRACT_RA(op) (((op) >> 12) & 0x3f)
86#define EXTRACT_RB(op) (((op) >> 6) & 0x3f)
87#define EXTRACT_RC(op) (((op) & 0x3f)
88#define EXTRACT_UIMM6(op) ((op) & 0x3f)
89#define EXTRACT_IMM6(op) ((((int)EXTRACT_UIMM6(op)) << 26) >> 26)
90#define EXTRACT_IMM26(op) ((((op)&0x0ff00000) >> 2) | ((op)&0x0003ffff))
91#define EXTRACT_IMM32(opl, opr) ((EXTRACT_UIMM6(opl) << 26)|EXTRACT_IMM26(opr))
92
45a70ed6
SG		 93/* Discard from the stack the innermost frame, restoring all saved
94 registers. */
95
96void
97d30v_pop_frame ()
98{
99 struct frame_info *frame = get_current_frame ();
100 CORE_ADDR fp;
101 int regnum;
102 struct frame_saved_regs fsr;
103 char raw_buffer[8];
104
105 fp = FRAME_FP (frame);
106 if (frame->dummy)
107 {
108 d30v_pop_dummy_frame(frame);
109 return;
110 }
111
112 /* fill out fsr with the address of where each */
113 /* register was stored in the frame */
114 get_frame_saved_regs (frame, &fsr);
115
116 /* now update the current registers with the old values */
117 for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++)
118 {
119 if (fsr.regs[regnum])
120 {
121 read_memory (fsr.regs[regnum], raw_buffer, 8);
122 write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 8);
123 }
124 }
125 for (regnum = 0; regnum < SP_REGNUM; regnum++)
126 {
127 if (fsr.regs[regnum])
128 {
7359fb1d 129 write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], 4));
45a70ed6
SG		 130 }
131 }
132 if (fsr.regs[PSW_REGNUM])
133 {
7359fb1d 134 write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], 4));
45a70ed6
SG		 135 }
136
7359fb1d 137 write_register (PC_REGNUM, read_register(LR_REGNUM));
45a70ed6
SG		 138 write_register (SP_REGNUM, fp + frame->size);
139 target_store_registers (-1);
140 flush_cached_frames ();
141}
142
143static int
144check_prologue (op)
7359fb1d 145 unsigned long op;
45a70ed6 146{
7359fb1d
DT		 147 /* add sp,sp,imm -- observed */
148 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
45a70ed6
SG		 149 return 1;
150
7359fb1d
DT		 151 /* add r22,sp,imm -- observed */
152 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6
SG		 153 return 1;
154
7359fb1d
DT		 155 /* or fp,r0,sp -- observed */
156 if (op == OP_OR_FP_R0_SP)
45a70ed6
SG		 157 return 1;
158
7359fb1d
DT		 159 /* nop */
160 if ((op & OP_MASK_OPCODE) == OP_NOP)
45a70ed6
SG		 161 return 1;
162
7359fb1d
DT		 163 /* stw Ra,@(sp,r0) */
164 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0)
45a70ed6
SG		 165 return 1;
166
7359fb1d
DT		 167 /* stw Ra,@(sp,0x0) */
168 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0)
45a70ed6
SG		 169 return 1;
170
7359fb1d
DT		 171 /* st2w Ra,@(sp,r0) */
172 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0)
173 return 1;
174
175 /* st2w Ra,@(sp,0x0) */
176 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0)
177 return 1;
178
179 /* stw fp, @(r22+,r0) -- observed */
180 if (op == OP_STW_FP_R22P_R0)
181 return 1;
182
183 /* stw r62, @(r22+,r0) -- observed */
184 if (op == OP_STW_LR_R22P_R0)
185 return 1;
186
187 /* stw Ra, @(fp,r0) -- observed */
188 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
189 return 1; /* first arg */
190
191 /* stw Ra, @(fp,imm) -- observed */
192 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
193 return 1; /* second and subsequent args */
194
195 /* stw fp,@(sp,imm) -- observed */
196 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
197 return 1;
198
199 /* st2w Ra,@(r22+,r0) */
200 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
45a70ed6
SG		 201 return 1;
202
7359fb1d
DT		 203 /* stw Ra, @(sp-) */
204 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
205 return 1;
206
207 /* st2w Ra, @(sp-) */
208 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
209 return 1;
210
211 /* sub.? sp,sp,imm */
212 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
213 return 1;
214
45a70ed6
SG		 215 return 0;
216}
217
218CORE_ADDR
219d30v_skip_prologue (pc)
220 CORE_ADDR pc;
221{
7359fb1d
DT		 222 unsigned long op[2];
223 unsigned long opl, opr; /* left / right sub operations */
224 unsigned long fm0, fm1; /* left / right mode bits */
225 unsigned long cc0, cc1;
226 unsigned long op1, op2;
45a70ed6
SG		 227 CORE_ADDR func_addr, func_end;
228 struct symtab_and_line sal;
229
230 /* If we have line debugging information, then the end of the */
231 /* prologue should the first assembly instruction of the first source line */
232 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
233 {
234 sal = find_pc_line (func_addr, 0);
235 if ( sal.end && sal.end < func_end)
236 return sal.end;
237 }
238
7359fb1d 239 if (target_read_memory (pc, (char *)&op[0], 8))
45a70ed6
SG		 240 return pc; /* Can't access it -- assume no prologue. */
241
242 while (1)
243 {
7359fb1d
DT		 244 opl = (unsigned long)read_memory_integer (pc, 4);
245 opr = (unsigned long)read_memory_integer (pc+4, 4);
246
247 fm0 = (opl & OP_MASK_FM_BIT);
248 fm1 = (opr & OP_MASK_FM_BIT);
249
250 cc0 = (opl & OP_MASK_CC_BITS);
251 cc1 = (opr & OP_MASK_CC_BITS);
252
253 opl = (opl & OP_MASK_SUB_INST);
254 opr = (opr & OP_MASK_SUB_INST);
255
256 if (fm0 && fm1)
45a70ed6 257 {
7359fb1d
DT		 258 /* long instruction (opl contains the opcode) */
259 if (((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_SP_IMM) && /* add sp,sp,imm */
260 ((opl & OP_MASK_ALL_BUT_IMM) != OP_ADD_R22_SP_IMM) && /* add r22,sp,imm */
261 ((opl & OP_MASK_OP_AND_RB) != OP_STW_SP_IMM) && /* stw Ra, @(sp,imm) */
262 ((opl & OP_MASK_OP_AND_RB) != OP_ST2W_SP_IMM)) /* st2w Ra, @(sp,imm) */
45a70ed6
SG		 263 break;
264 }
265 else
266 {
267 /* short instructions */
7359fb1d 268 if (fm0 && !fm1)
45a70ed6 269 {
7359fb1d
DT		 270 op1 = opr;
271 op2 = opl;
45a70ed6
SG		 272 }
273 else
274 {
7359fb1d
DT		 275 op1 = opl;
276 op2 = opr;
45a70ed6
SG		 277 }
278 if (check_prologue(op1))
279 {
280 if (!check_prologue(op2))
281 {
282 /* if the previous opcode was really part of the prologue */
283 /* and not just a NOP, then we want to break after both instructions */
7359fb1d
DT		 284 if ((op1 & OP_MASK_OPCODE) != OP_NOP)
285 pc += 8;
45a70ed6
SG		 286 break;
287 }
288 }
289 else
290 break;
291 }
7359fb1d 292 pc += 8;
45a70ed6
SG		 293 }
294 return pc;
295}
296
36985eca
DT		 297static int end_of_stack;
298
45a70ed6
SG		 299/* Given a GDB frame, determine the address of the calling function's frame.
300 This will be used to create a new GDB frame struct, and then
301 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
302*/
303
304CORE_ADDR
305d30v_frame_chain (frame)
306 struct frame_info *frame;
307{
308 struct frame_saved_regs fsr;
309
310 d30v_frame_find_saved_regs (frame, &fsr);
311
36985eca
DT		 312 if (end_of_stack)
313 return (CORE_ADDR)0;
314
45a70ed6
SG		 315 if (frame->return_pc == IMEM_START)
316 return (CORE_ADDR)0;
317
318 if (!fsr.regs[FP_REGNUM])
319 {
320 if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START)
321 return (CORE_ADDR)0;
322
323 return fsr.regs[SP_REGNUM];
324 }
325
7359fb1d 326 if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM],4))
45a70ed6
SG		 327 return (CORE_ADDR)0;
328
7ae2b433 329 return read_memory_unsigned_integer(fsr.regs[FP_REGNUM],4);
45a70ed6
SG		 330}
331
332static int next_addr, uses_frame;
7359fb1d 333static int frame_size;
45a70ed6
SG		 334
335static int
336prologue_find_regs (op, fsr, addr)
7359fb1d 337 unsigned long op;
45a70ed6
SG		 338 struct frame_saved_regs *fsr;
339 CORE_ADDR addr;
340{
341 int n;
7359fb1d 342 int offset;
45a70ed6 343
7359fb1d
DT		 344 /* add sp,sp,imm -- observed */
345 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
45a70ed6 346 {
7359fb1d
DT		 347 offset = EXTRACT_IMM6(op);
348 /*next_addr += offset;*/
349 frame_size += -offset;
45a70ed6
SG		 350 return 1;
351 }
352
7359fb1d
DT		 353 /* add r22,sp,imm -- observed */
354 if ((op & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6 355 {
7359fb1d
DT		 356 offset = EXTRACT_IMM6(op);
357 next_addr = (offset - frame_size);
358 return 1;
359 }
360
361 /* stw Ra, @(fp, offset) -- observed */
362 if ((op & OP_MASK_OP_AND_RB) == OP_STW_FP_IMM)
363 {
364 n = EXTRACT_RA(op);
365 offset = EXTRACT_IMM6(op);
366 fsr->regs[n] = (offset - frame_size);
45a70ed6
SG		 367 return 1;
368 }
369
7359fb1d
DT		 370 /* stw Ra, @(fp, r0) -- observed */
371 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_FP_R0)
45a70ed6 372 {
7359fb1d
DT		 373 n = EXTRACT_RA(op);
374 fsr->regs[n] = (- frame_size);
45a70ed6
SG		 375 return 1;
376 }
377
7359fb1d
DT		 378 /* or fp,0,sp -- observed */
379 if ((op == OP_OR_FP_R0_SP) ||
380 (op == OP_OR_FP_SP_R0) ||
381 (op == OP_OR_FP_IMM0_SP))
45a70ed6
SG		 382 {
383 uses_frame = 1;
384 return 1;
385 }
386
387 /* nop */
7359fb1d 388 if ((op & OP_MASK_OPCODE) == OP_NOP)
45a70ed6
SG		 389 return 1;
390
7359fb1d
DT		 391 /* stw Ra,@(r22+,r0) -- observed */
392 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_R22P_R0)
393 {
394 n = EXTRACT_RA(op);
395 fsr->regs[n] = next_addr;
396 next_addr += 4;
397 return 1;
398 }
399#if 0 /* subsumed in pattern above */
400 /* stw fp,@(r22+,r0) -- observed */
401 if (op == OP_STW_FP_R22P_R0)
402 {
403 fsr->regs[FP_REGNUM] = next_addr; /* XXX */
404 next_addr += 4;
405 return 1;
406 }
407
408 /* stw r62,@(r22+,r0) -- observed */
409 if (op == OP_STW_LR_R22P_R0)
410 {
411 fsr->regs[LR_REGNUM] = next_addr;
412 next_addr += 4;
413 return 1;
414 }
415#endif
416 /* st2w Ra,@(r22+,r0) -- observed */
417 if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_R22P_R0)
418 {
419 n = EXTRACT_RA(op);
420 fsr->regs[n] = next_addr;
421 fsr->regs[n+1] = next_addr + 4;
422 next_addr += 8;
423 return 1;
424 }
425
426 /* stw rn, @(sp-) */
427 if ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SPM)
428 {
429 n = EXTRACT_RA(op);
430 fsr->regs[n] = next_addr;
431 next_addr -= 4;
432 return 1;
433 }
434
435 /* st2w Ra, @(sp-) */
436 else if ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SPM)
45a70ed6 437 {
7359fb1d 438 n = EXTRACT_RA(op);
45a70ed6 439 fsr->regs[n] = next_addr;
7359fb1d
DT		 440 fsr->regs[n+1] = next_addr+4;
441 next_addr -= 8;
442 return 1;
443 }
444
445 /* sub sp,sp,imm */
446 if ((op & OP_MASK_ALL_BUT_IMM) == OP_SUB_SP_IMM)
447 {
448 offset = EXTRACT_IMM6(op);
7ae2b433 449 frame_size += -offset;
45a70ed6
SG		 450 return 1;
451 }
452
7ae2b433 453 /* st rn, @(sp,0) -- observed */
7359fb1d
DT		 454 if (((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_R0) ||
455 ((op & OP_MASK_ALL_BUT_RA) == OP_STW_SP_IMM0))
45a70ed6 456 {
7359fb1d 457 n = EXTRACT_RA(op);
7ae2b433 458 fsr->regs[n] = (- frame_size);
7359fb1d
DT		 459 return 1;
460 }
461
462 /* st2w rn, @(sp,0) */
463 if (((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_R0) ||
464 ((op & OP_MASK_ALL_BUT_RA) == OP_ST2W_SP_IMM0))
465 {
466 n = EXTRACT_RA(op);
7ae2b433
DT		 467 fsr->regs[n] = (- frame_size);
468 fsr->regs[n+1] = (- frame_size) + 4;
45a70ed6
SG		 469 return 1;
470 }
471
36985eca
DT		 472 /* stw fp,@(sp,imm) -- observed */
473 if ((op & OP_MASK_ALL_BUT_IMM) == OP_STW_FP_SP_IMM)
474 {
475 offset = EXTRACT_IMM6(op);
476 fsr->regs[FP_REGNUM] = (offset - frame_size);
477 return 1;
478 }
45a70ed6
SG		 479 return 0;
480}
481
482/* Put here the code to store, into a struct frame_saved_regs, the
483 addresses of the saved registers of frame described by FRAME_INFO.
484 This includes special registers such as pc and fp saved in special
485 ways in the stack frame. sp is even more special: the address we
486 return for it IS the sp for the next frame. */
487void
488d30v_frame_find_saved_regs (fi, fsr)
489 struct frame_info *fi;
490 struct frame_saved_regs *fsr;
491{
492 CORE_ADDR fp, pc;
7359fb1d
DT		 493 unsigned long opl, opr;
494 unsigned long op1, op2;
495 unsigned long fm0, fm1;
45a70ed6
SG		 496 int i;
497
498 fp = fi->frame;
499 memset (fsr, 0, sizeof (*fsr));
500 next_addr = 0;
7359fb1d 501 frame_size = 0;
36985eca 502 end_of_stack = 0;
45a70ed6 503
cd44191e
DT		 504 uses_frame = 0;
505
506 d30v_frame_find_saved_regs_offsets (fi, fsr);
507
508 fi->size = frame_size;
509
510 if (!fp)
511 fp = read_register(SP_REGNUM);
512
513 for (i=0; i<NUM_REGS-1; i++)
514 if (fsr->regs[i])
515 {
516 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
517 }
518
519 if (fsr->regs[LR_REGNUM])
520 fi->return_pc = read_memory_unsigned_integer(fsr->regs[LR_REGNUM],4);
521 else
522 fi->return_pc = read_register(LR_REGNUM);
523
524 /* the SP is not normally (ever?) saved, but check anyway */
525 if (!fsr->regs[SP_REGNUM])
526 {
527 /* if the FP was saved, that means the current FP is valid, */
528 /* otherwise, it isn't being used, so we use the SP instead */
529 if (uses_frame)
530 fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size;
531 else
532 {
533 fsr->regs[SP_REGNUM] = fp + fi->size;
534 fi->frameless = 1;
535 fsr->regs[FP_REGNUM] = 0;
536 }
537 }
538}
539
540void
541d30v_frame_find_saved_regs_offsets (fi, fsr)
542 struct frame_info *fi;
543 struct frame_saved_regs *fsr;
544{
545 CORE_ADDR fp, pc;
546 unsigned long opl, opr;
547 unsigned long op1, op2;
548 unsigned long fm0, fm1;
549 int i;
550
551 fp = fi->frame;
552 memset (fsr, 0, sizeof (*fsr));
553 next_addr = 0;
554 frame_size = 0;
555 end_of_stack = 0;
556
45a70ed6
SG		 557 pc = get_pc_function_start (fi->pc);
558
559 uses_frame = 0;
7ae2b433 560 while (pc < fi->pc)
45a70ed6 561 {
7359fb1d
DT		 562 opl = (unsigned long)read_memory_integer (pc, 4);
563 opr = (unsigned long)read_memory_integer (pc+4, 4);
564
565 fm0 = (opl & OP_MASK_FM_BIT);
566 fm1 = (opr & OP_MASK_FM_BIT);
567
568 opl = (opl & OP_MASK_SUB_INST);
569 opr = (opr & OP_MASK_SUB_INST);
570
571 if (fm0 && fm1)
45a70ed6
SG		 572 {
573 /* long instruction */
7359fb1d
DT		 574 if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_SP_IMM)
575 {
576 /* add sp,sp,n */
577 long offset = EXTRACT_IMM32(opl, opr);
578 frame_size += -offset;
579 }
580 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_ADD_R22_SP_IMM)
45a70ed6 581 {
7359fb1d
DT		 582 /* add r22,sp,offset */
583 long offset = EXTRACT_IMM32(opl,opr);
584 next_addr = (offset - frame_size);
45a70ed6 585 }
7359fb1d 586 else if ((opl & OP_MASK_OP_AND_RB) == OP_STW_SP_IMM)
45a70ed6 587 {
7359fb1d
DT		 588 /* st Ra, @(sp,imm) */
589 long offset = EXTRACT_IMM32(opl, opr);
590 short n = EXTRACT_RA(opl);
591 fsr->regs[n] = (offset - frame_size);
45a70ed6 592 }
7359fb1d 593 else if ((opl & OP_MASK_OP_AND_RB) == OP_ST2W_SP_IMM)
45a70ed6 594 {
7359fb1d
DT		 595 /* st2w Ra, @(sp,offset) */
596 long offset = EXTRACT_IMM32(opl, opr);
597 short n = EXTRACT_RA(opl);
598 fsr->regs[n] = (offset - frame_size);
599 fsr->regs[n+1] = (offset - frame_size) + 4;
45a70ed6 600 }
36985eca
DT		 601 else if ((opl & OP_MASK_ALL_BUT_IMM) == OP_OR_SP_R0_IMM)
602 {
603 end_of_stack = 1;
604 }
45a70ed6
SG		 605 else
606 break;
607 }
608 else
609 {
610 /* short instructions */
7359fb1d 611 if (fm0 && !fm1)
45a70ed6 612 {
7359fb1d
DT		 613 op2 = opl;
614 op1 = opr;
45a70ed6
SG		 615 }
616 else
617 {
7359fb1d
DT		 618 op1 = opl;
619 op2 = opr;
45a70ed6
SG		 620 }
621 if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc))
622 break;
623 }
7359fb1d 624 pc += 8;
45a70ed6
SG		 625 }
626
7359fb1d 627#if 0
cd44191e
DT		 628 fi->size = frame_size;
629
36985eca 630 if (!fp)
7359fb1d 631 fp = read_register(SP_REGNUM);
cd44191e 632
45a70ed6
SG		 633 for (i=0; i<NUM_REGS-1; i++)
634 if (fsr->regs[i])
635 {
7359fb1d 636 fsr->regs[i] = fsr->regs[i] + fp + frame_size;
45a70ed6
SG		 637 }
638
639 if (fsr->regs[LR_REGNUM])
7359fb1d 640 fi->return_pc = read_memory_unsigned_integer(fsr->regs[LR_REGNUM],4);
45a70ed6 641 else
7359fb1d 642 fi->return_pc = read_register(LR_REGNUM);
45a70ed6 643
7ae2b433 644 /* the SP is not normally (ever?) saved, but check anyway */
45a70ed6
SG		 645 if (!fsr->regs[SP_REGNUM])
646 {
647 /* if the FP was saved, that means the current FP is valid, */
648 /* otherwise, it isn't being used, so we use the SP instead */
649 if (uses_frame)
650 fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size;
651 else
652 {
653 fsr->regs[SP_REGNUM] = fp + fi->size;
654 fi->frameless = 1;
655 fsr->regs[FP_REGNUM] = 0;
656 }
657 }
cd44191e 658#endif
45a70ed6
SG		 659}
660
661void
662d30v_init_extra_frame_info (fromleaf, fi)
663 int fromleaf;
664 struct frame_info *fi;
665{
666 struct frame_saved_regs dummy;
667
7359fb1d 668 if (fi->next && (fi->pc == 0))
45a70ed6
SG		 669 fi->pc = fi->next->return_pc;
670
cd44191e
DT		 671 d30v_frame_find_saved_regs_offsets (fi, &dummy);
672
673 if (uses_frame == 0)
674 fi->frameless = 1;
675 else
676 fi->frameless = 0;
677
678 if ((fi->next == 0) && (uses_frame == 0))
679 /* innermost frame and it's "frameless",
680 so the fi->frame field is wrong, fix it! */
681 fi->frame = read_sp ();
682
683 if (dummy.regs[LR_REGNUM])
684 {
685 /* it was saved, grab it! */
686 dummy.regs[LR_REGNUM] += (fi->frame + frame_size);
687 fi->return_pc = read_memory_unsigned_integer(dummy.regs[LR_REGNUM],4);
688 }
689 else
690 fi->return_pc = read_register(LR_REGNUM);
45a70ed6
SG		 691}
692
7359fb1d
DT		 693void
694d30v_init_frame_pc (fromleaf, prev)
695 int fromleaf;
696 struct frame_info *prev;
697{
698 /* default value, put here so we can breakpoint on it and
699 see if the default value is really the right thing to use */
700 prev->pc = (fromleaf ? SAVED_PC_AFTER_CALL (prev->next) : \
701 prev->next ? FRAME_SAVED_PC (prev->next) : read_pc ());
702}
703
45a70ed6
SG		 704static void d30v_print_register PARAMS ((int regnum, int tabular));
705
706static void
707d30v_print_register (regnum, tabular)
708 int regnum;
709 int tabular;
710{
711 if (regnum < A0_REGNUM)
712 {
713 if (tabular)
714 printf_filtered ("%08x", read_register (regnum));
715 else
716 printf_filtered ("0x%x %d", read_register (regnum),
717 read_register (regnum));
718 }
719 else
720 {
721 char regbuf[MAX_REGISTER_RAW_SIZE];
722
723 read_relative_register_raw_bytes (regnum, regbuf);
724
725 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0,
726 gdb_stdout, 'x', 1, 0, Val_pretty_default);
727
728 if (!tabular)
729 {
730 printf_filtered (" ");
731 val_print (REGISTER_VIRTUAL_TYPE (regnum), regbuf, 0,
732 gdb_stdout, 'd', 1, 0, Val_pretty_default);
733 }
734 }
735}
736
5d62f957
MM		 737static void
738d30v_print_flags ()
739{
740 long psw = read_register (PSW_REGNUM);
741 printf_filtered ("flags #1");
742 printf_filtered (" (sm) %d", (psw & PSW_SM) != 0);
743 printf_filtered (" (ea) %d", (psw & PSW_EA) != 0);
744 printf_filtered (" (db) %d", (psw & PSW_DB) != 0);
745 printf_filtered (" (ds) %d", (psw & PSW_DS) != 0);
746 printf_filtered (" (ie) %d", (psw & PSW_IE) != 0);
747 printf_filtered (" (rp) %d", (psw & PSW_RP) != 0);
748 printf_filtered (" (md) %d\n", (psw & PSW_MD) != 0);
749
750 printf_filtered ("flags #2");
751 printf_filtered (" (f0) %d", (psw & PSW_F0) != 0);
752 printf_filtered (" (f1) %d", (psw & PSW_F1) != 0);
753 printf_filtered (" (f2) %d", (psw & PSW_F2) != 0);
754 printf_filtered (" (f3) %d", (psw & PSW_F3) != 0);
755 printf_filtered (" (s) %d", (psw & PSW_S) != 0);
756 printf_filtered (" (v) %d", (psw & PSW_V) != 0);
757 printf_filtered (" (va) %d", (psw & PSW_VA) != 0);
758 printf_filtered (" (c) %d\n", (psw & PSW_C) != 0);
759}
760
761static void
762print_flags_command (args, from_tty)
763 char *args;
764 int from_tty;
765{
766 d30v_print_flags ();
767}
768
45a70ed6
SG		 769void
770d30v_do_registers_info (regnum, fpregs)
771 int regnum;
772 int fpregs;
773{
774 long long num1, num2;
5d62f957 775 long psw;
45a70ed6
SG		 776
777 if (regnum != -1)
778 {
779 if (reg_names[0] == NULL || reg_names[0][0] == '\000')
780 return;
781
782 printf_filtered ("%s ", reg_names[regnum]);
783 d30v_print_register (regnum, 0);
784
785 printf_filtered ("\n");
786 return;
787 }
788
789 /* Have to print all the registers. Format them nicely. */
790
791 printf_filtered ("PC=");
792 print_address (read_pc (), gdb_stdout);
793
794 printf_filtered (" PSW=");
795 d30v_print_register (PSW_REGNUM, 1);
796
797 printf_filtered (" BPC=");
798 print_address (read_register (BPC_REGNUM), gdb_stdout);
799
800 printf_filtered (" BPSW=");
801 d30v_print_register (BPSW_REGNUM, 1);
802 printf_filtered ("\n");
803
804 printf_filtered ("DPC=");
805 print_address (read_register (DPC_REGNUM), gdb_stdout);
806
807 printf_filtered (" DPSW=");
808 d30v_print_register (DPSW_REGNUM, 1);
809
810 printf_filtered (" IBA=");
811 print_address (read_register (IBA_REGNUM), gdb_stdout);
812 printf_filtered ("\n");
813
814 printf_filtered ("RPT_C=");
815 d30v_print_register (RPT_C_REGNUM, 1);
816
817 printf_filtered (" RPT_S=");
818 print_address (read_register (RPT_S_REGNUM), gdb_stdout);
819
820 printf_filtered (" RPT_E=");
821 print_address (read_register (RPT_E_REGNUM), gdb_stdout);
822 printf_filtered ("\n");
823
824 printf_filtered ("MOD_S=");
825 print_address (read_register (MOD_S_REGNUM), gdb_stdout);
826
827 printf_filtered (" MOD_E=");
828 print_address (read_register (MOD_E_REGNUM), gdb_stdout);
829 printf_filtered ("\n");
830
831 printf_filtered ("EIT_VB=");
832 print_address (read_register (EIT_VB_REGNUM), gdb_stdout);
833
834 printf_filtered (" INT_S=");
835 d30v_print_register (INT_S_REGNUM, 1);
836
837 printf_filtered (" INT_M=");
838 d30v_print_register (INT_M_REGNUM, 1);
839 printf_filtered ("\n");
840
5d62f957 841 d30v_print_flags ();
45a70ed6
SG		 842 for (regnum = 0; regnum <= 63;)
843 {
844 int i;
845
846 printf_filtered ("R%d-R%d ", regnum, regnum + 7);
847 if (regnum < 10)
848 printf_filtered (" ");
849 if (regnum + 7 < 10)
850 printf_filtered (" ");
851
852 for (i = 0; i < 8; i++)
853 {
854 printf_filtered (" ");
855 d30v_print_register (regnum++, 1);
856 }
857
858 printf_filtered ("\n");
859 }
860
861 printf_filtered ("A0-A1 ");
862
863 d30v_print_register (A0_REGNUM, 1);
864 printf_filtered (" ");
865 d30v_print_register (A1_REGNUM, 1);
866 printf_filtered ("\n");
867}
868
869CORE_ADDR
870d30v_fix_call_dummy (dummyname, start_sp, fun, nargs, args, type, gcc_p)
871 char *dummyname;
872 CORE_ADDR start_sp;
873 CORE_ADDR fun;
874 int nargs;
875 value_ptr *args;
876 struct type *type;
877 int gcc_p;
878{
879 int regnum;
880 CORE_ADDR sp;
881 char buffer[MAX_REGISTER_RAW_SIZE];
882 struct frame_info *frame = get_current_frame ();
883 frame->dummy = start_sp;
7359fb1d 884 /*start_sp |= DMEM_START;*/
45a70ed6
SG		 885
886 sp = start_sp;
887 for (regnum = 0; regnum < NUM_REGS; regnum++)
888 {
889 sp -= REGISTER_RAW_SIZE(regnum);
890 store_address (buffer, REGISTER_RAW_SIZE(regnum), read_register(regnum));
891 write_memory (sp, buffer, REGISTER_RAW_SIZE(regnum));
892 }
7359fb1d 893 write_register (SP_REGNUM, (LONGEST)sp);
45a70ed6 894 /* now we need to load LR with the return address */
7359fb1d 895 write_register (LR_REGNUM, (LONGEST)d30v_call_dummy_address());
45a70ed6
SG		 896 return sp;
897}
898
899static void
900d30v_pop_dummy_frame (fi)
901 struct frame_info *fi;
902{
903 CORE_ADDR sp = fi->dummy;
904 int regnum;
905
906 for (regnum = 0; regnum < NUM_REGS; regnum++)
907 {
908 sp -= REGISTER_RAW_SIZE(regnum);
909 write_register(regnum, read_memory_unsigned_integer (sp, REGISTER_RAW_SIZE(regnum)));
910 }
911 flush_cached_frames (); /* needed? */
912}
913
914
915CORE_ADDR
916d30v_push_arguments (nargs, args, sp, struct_return, struct_addr)
917 int nargs;
918 value_ptr *args;
919 CORE_ADDR sp;
920 int struct_return;
921 CORE_ADDR struct_addr;
922{
923 int i, len, index=0, regnum=2;
924 char buffer[4], *contents;
925 LONGEST val;
926 CORE_ADDR ptrs[10];
927
7359fb1d 928#if 0
45a70ed6
SG		 929 /* Pass 1. Put all large args on stack */
930 for (i = 0; i < nargs; i++)
931 {
932 value_ptr arg = args[i];
933 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
934 len = TYPE_LENGTH (arg_type);
935 contents = VALUE_CONTENTS(arg);
936 val = extract_signed_integer (contents, len);
937 if (len > 4)
938 {
939 /* put on stack and pass pointers */
940 sp -= len;
941 write_memory (sp, contents, len);
942 ptrs[index++] = sp;
943 }
944 }
7359fb1d 945#endif
45a70ed6
SG		 946 index = 0;
947
948 for (i = 0; i < nargs; i++)
949 {
950 value_ptr arg = args[i];
951 struct type *arg_type = check_typedef (VALUE_TYPE (arg));
952 len = TYPE_LENGTH (arg_type);
953 contents = VALUE_CONTENTS(arg);
45a70ed6
SG		 954 if (len > 4)
955 {
7359fb1d
DT		 956 /* we need multiple registers */
957 int ndx;
958
7ae2b433 959 for (ndx = 0; len > 0; ndx += 8, len -= 8)
45a70ed6 960 {
7ae2b433
DT		 961 if (regnum & 1)
962 regnum++; /* all args > 4 bytes start in even register */
963
7359fb1d
DT		 964 if (regnum < 18)
965 {
7ae2b433
DT		 966 val = extract_signed_integer (&contents[ndx], 4);
967 write_register (regnum++, val);
7359fb1d 968
7ae2b433
DT		 969 if (len >= 8)
970 val = extract_signed_integer (&contents[ndx+4], 4);
971 else
972 val = extract_signed_integer (&contents[ndx+4], len-4);
7359fb1d
DT		 973 write_register (regnum++, val);
974 }
975 else
976 {
977 /* no more registers available. put it on the stack */
7ae2b433
DT		 978
979 /* all args > 4 bytes are padded to a multiple of 8 bytes
980 and start on an 8 byte boundary */
981 if (sp & 7)
982 sp -= (sp & 7); /* align it */
983
984 sp -= ((len + 7) & ~7); /* allocate space */
7359fb1d
DT		 985 write_memory (sp, &contents[ndx], len);
986 break;
987 }
45a70ed6
SG		 988 }
989 }
990 else
991 {
7359fb1d 992 if (regnum < 18 )
45a70ed6 993 {
7ae2b433 994 val = extract_signed_integer (contents, len);
7359fb1d 995 write_register (regnum++, val);
45a70ed6
SG		 996 }
997 else
998 {
7ae2b433
DT		 999 /* all args are padded to a multiple of 4 bytes (at least) */
1000 sp -= ((len + 3) & ~3);
1001 write_memory (sp, contents, len);
45a70ed6
SG		 1002 }
1003 }
1004 }
7ae2b433
DT		 1005 if (sp & 7)
1006 /* stack pointer is not on an 8 byte boundary -- align it */
1007 sp -= (sp & 7);
45a70ed6
SG		 1008 return sp;
1009}
1010
1011
1012/* pick an out-of-the-way place to set the return value */
1013/* for an inferior function call. The link register is set to this */
1014/* value and a momentary breakpoint is set there. When the breakpoint */
1015/* is hit, the dummy frame is popped and the previous environment is */
1016/* restored. */
1017
1018CORE_ADDR
1019d30v_call_dummy_address ()
1020{
1021 CORE_ADDR entry;
1022 struct minimal_symbol *sym;
1023
1024 entry = entry_point_address ();
1025
1026 if (entry != 0)
1027 return entry;
1028
1029 sym = lookup_minimal_symbol ("_start", NULL, symfile_objfile);
1030
1031 if (!sym || MSYMBOL_TYPE (sym) != mst_text)
1032 return 0;
1033 else
1034 return SYMBOL_VALUE_ADDRESS (sym);
1035}
1036
1037/* Given a return value in `regbuf' with a type `valtype',
1038 extract and copy its value into `valbuf'. */
1039
1040void
1041d30v_extract_return_value (valtype, regbuf, valbuf)
1042 struct type *valtype;
1043 char regbuf[REGISTER_BYTES];
1044 char *valbuf;
1045{
1046 memcpy (valbuf, regbuf + REGISTER_BYTE (2), TYPE_LENGTH (valtype));
1047}
1048
1049/* The following code implements access to, and display of, the D30V's
1050 instruction trace buffer. The buffer consists of 64K or more
1051 4-byte words of data, of which each words includes an 8-bit count,
1052 an 8-bit segment number, and a 16-bit instruction address.
1053
1054 In theory, the trace buffer is continuously capturing instruction
1055 data that the CPU presents on its "debug bus", but in practice, the
1056 ROMified GDB stub only enables tracing when it continues or steps
1057 the program, and stops tracing when the program stops; so it
1058 actually works for GDB to read the buffer counter out of memory and
1059 then read each trace word. The counter records where the tracing
1060 stops, but there is no record of where it started, so we remember
1061 the PC when we resumed and then search backwards in the trace
1062 buffer for a word that includes that address. This is not perfect,
1063 because you will miss trace data if the resumption PC is the target
1064 of a branch. (The value of the buffer counter is semi-random, any
1065 trace data from a previous program stop is gone.) */
1066
1067/* The address of the last word recorded in the trace buffer. */
1068
1069#define DBBC_ADDR (0xd80000)
1070
1071/* The base of the trace buffer, at least for the "Board_0". */
1072
1073#define TRACE_BUFFER_BASE (0xf40000)
1074
1075static void trace_command PARAMS ((char *, int));
1076
1077static void untrace_command PARAMS ((char *, int));
1078
1079static void trace_info PARAMS ((char *, int));
1080
1081static void tdisassemble_command PARAMS ((char *, int));
1082
1083static void display_trace PARAMS ((int, int));
1084
1085/* True when instruction traces are being collected. */
1086
1087static int tracing;
1088
1089/* Remembered PC. */
1090
1091static CORE_ADDR last_pc;
1092
1093/* True when trace output should be displayed whenever program stops. */
1094
1095static int trace_display;
1096
1097/* True when trace listing should include source lines. */
1098
1099static int default_trace_show_source = 1;
1100
1101struct trace_buffer {
1102 int size;
1103 short *counts;
1104 CORE_ADDR *addrs;
1105} trace_data;
1106
1107static void
1108trace_command (args, from_tty)
1109 char *args;
1110 int from_tty;
1111{
1112 /* Clear the host-side trace buffer, allocating space if needed. */
1113 trace_data.size = 0;
1114 if (trace_data.counts == NULL)
1115 trace_data.counts = (short *) xmalloc (65536 * sizeof(short));
1116 if (trace_data.addrs == NULL)
1117 trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR));
1118
1119 tracing = 1;
1120
1121 printf_filtered ("Tracing is now on.\n");
1122}
1123
1124static void
1125untrace_command (args, from_tty)
1126 char *args;
1127 int from_tty;
1128{
1129 tracing = 0;
1130
1131 printf_filtered ("Tracing is now off.\n");
1132}
1133
1134static void
1135trace_info (args, from_tty)
1136 char *args;
1137 int from_tty;
1138{
1139 int i;
1140
1141 if (trace_data.size)
1142 {
1143 printf_filtered ("%d entries in trace buffer:\n", trace_data.size);
1144
1145 for (i = 0; i < trace_data.size; ++i)
1146 {
1147 printf_filtered ("%d: %d instruction%s at 0x%x\n",
1148 i, trace_data.counts[i],
1149 (trace_data.counts[i] == 1 ? "" : "s"),
1150 trace_data.addrs[i]);
1151 }
1152 }
1153 else
1154 printf_filtered ("No entries in trace buffer.\n");
1155
1156 printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off"));
1157}
1158
1159/* Print the instruction at address MEMADDR in debugged memory,
1160 on STREAM. Returns length of the instruction, in bytes. */
1161
1162static int
1163print_insn (memaddr, stream)
1164 CORE_ADDR memaddr;
1165 GDB_FILE *stream;
1166{
1167 /* If there's no disassembler, something is very wrong. */
1168 if (tm_print_insn == NULL)
1169 abort ();
1170
1171 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
1172 tm_print_insn_info.endian = BFD_ENDIAN_BIG;
1173 else
1174 tm_print_insn_info.endian = BFD_ENDIAN_LITTLE;
1175 return (*tm_print_insn) (memaddr, &tm_print_insn_info);
1176}
1177
1178void
1179d30v_eva_prepare_to_trace ()
1180{
1181 if (!tracing)
1182 return;
1183
1184 last_pc = read_register (PC_REGNUM);
1185}
1186
1187/* Collect trace data from the target board and format it into a form
1188 more useful for display. */
1189
1190void
1191d30v_eva_get_trace_data ()
1192{
1193 int count, i, j, oldsize;
1194 int trace_addr, trace_seg, trace_cnt, next_cnt;
1195 unsigned int last_trace, trace_word, next_word;
1196 unsigned int *tmpspace;
1197
1198 if (!tracing)
1199 return;
1200
1201 tmpspace = xmalloc (65536 * sizeof(unsigned int));
1202
1203 last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2;
1204
1205 /* Collect buffer contents from the target, stopping when we reach
1206 the word recorded when execution resumed. */
1207
1208 count = 0;
1209 while (last_trace > 0)
1210 {
1211 QUIT;
1212 trace_word =
1213 read_memory_unsigned_integer (TRACE_BUFFER_BASE + last_trace, 4);
1214 trace_addr = trace_word & 0xffff;
1215 last_trace -= 4;
1216 /* Ignore an apparently nonsensical entry. */
1217 if (trace_addr == 0xffd5)
1218 continue;
1219 tmpspace[count++] = trace_word;
1220 if (trace_addr == last_pc)
1221 break;
1222 if (count > 65535)
1223 break;
1224 }
1225
1226 /* Move the data to the host-side trace buffer, adjusting counts to
1227 include the last instruction executed and transforming the address
1228 into something that GDB likes. */
1229
1230 for (i = 0; i < count; ++i)
1231 {
1232 trace_word = tmpspace[i];
1233 next_word = ((i == 0) ? 0 : tmpspace[i - 1]);
1234 trace_addr = trace_word & 0xffff;
1235 next_cnt = (next_word >> 24) & 0xff;
1236 j = trace_data.size + count - i - 1;
1237 trace_data.addrs[j] = (trace_addr << 2) + 0x1000000;
1238 trace_data.counts[j] = next_cnt + 1;
1239 }
1240
1241 oldsize = trace_data.size;
1242 trace_data.size += count;
1243
1244 free (tmpspace);
1245
1246 if (trace_display)
1247 display_trace (oldsize, trace_data.size);
1248}
1249
1250static void
1251tdisassemble_command (arg, from_tty)
1252 char *arg;
1253 int from_tty;
1254{
1255 int i, count;
1256 CORE_ADDR low, high;
1257 char *space_index;
1258
1259 if (!arg)
1260 {
1261 low = 0;
1262 high = trace_data.size;
1263 }
1264 else if (!(space_index = (char *) strchr (arg, ' ')))
1265 {
1266 low = parse_and_eval_address (arg);
1267 high = low + 5;
1268 }
1269 else
1270 {
1271 /* Two arguments. */
1272 *space_index = '\0';
1273 low = parse_and_eval_address (arg);
1274 high = parse_and_eval_address (space_index + 1);
1275 if (high < low)
1276 high = low;
1277 }
1278
1279 printf_filtered ("Dump of trace from %d to %d:\n", low, high);
1280
1281 display_trace (low, high);
1282
1283 printf_filtered ("End of trace dump.\n");
1284 gdb_flush (gdb_stdout);
1285}
1286
1287static void
1288display_trace (low, high)
1289 int low, high;
1290{
1291 int i, count, trace_show_source, first, suppress;
1292 CORE_ADDR next_address;
1293
1294 trace_show_source = default_trace_show_source;
1295 if (!have_full_symbols () && !have_partial_symbols())
1296 {
1297 trace_show_source = 0;
1298 printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n");
1299 printf_filtered ("Trace will not display any source.\n");
1300 }
1301
1302 first = 1;
1303 suppress = 0;
1304 for (i = low; i < high; ++i)
1305 {
1306 next_address = trace_data.addrs[i];
1307 count = trace_data.counts[i];
1308 while (count-- > 0)
1309 {
1310 QUIT;
1311 if (trace_show_source)
1312 {
1313 struct symtab_and_line sal, sal_prev;
1314
1315 sal_prev = find_pc_line (next_address - 4, 0);
1316 sal = find_pc_line (next_address, 0);
1317
1318 if (sal.symtab)
1319 {
1320 if (first || sal.line != sal_prev.line)
1321 print_source_lines (sal.symtab, sal.line, sal.line + 1, 0);
1322 suppress = 0;
1323 }
1324 else
1325 {
1326 if (!suppress)
1327 /* FIXME-32x64--assumes sal.pc fits in long. */
1328 printf_filtered ("No source file for address %s.\n",
1329 local_hex_string((unsigned long) sal.pc));
1330 suppress = 1;
1331 }
1332 }
1333 first = 0;
1334 print_address (next_address, gdb_stdout);
1335 printf_filtered (":");
1336 printf_filtered ("\t");
1337 wrap_here (" ");
1338 next_address = next_address + print_insn (next_address, gdb_stdout);
1339 printf_filtered ("\n");
1340 gdb_flush (gdb_stdout);
1341 }
1342 }
1343}
1344
1345extern void (*target_resume_hook) PARAMS ((void));
1346extern void (*target_wait_loop_hook) PARAMS ((void));
1347
1348void
1349_initialize_d30v_tdep ()
1350{
1351 tm_print_insn = print_insn_d30v;
1352
1353 target_resume_hook = d30v_eva_prepare_to_trace;
1354 target_wait_loop_hook = d30v_eva_get_trace_data;
1355
5d62f957
MM		 1356 add_info ("flags", print_flags_command, "Print d30v flags.");
1357
45a70ed6
SG		 1358 add_com ("trace", class_support, trace_command,
1359 "Enable tracing of instruction execution.");
1360
1361 add_com ("untrace", class_support, untrace_command,
7359fb1d 1362 "Disable tracing of instruction execution.");
45a70ed6
SG		 1363
1364 add_com ("tdisassemble", class_vars, tdisassemble_command,
1365 "Disassemble the trace buffer.\n\
1366Two optional arguments specify a range of trace buffer entries\n\
1367as reported by info trace (NOT addresses!).");
1368
1369 add_info ("trace", trace_info,
1370 "Display info about the trace data buffer.");
1371
1372 add_show_from_set (add_set_cmd ("tracedisplay", no_class,
1373 var_integer, (char *)&trace_display,
1374 "Set automatic display of trace.\n", &setlist),
1375 &showlist);
1376 add_show_from_set (add_set_cmd ("tracesource", no_class,
1377 var_integer, (char *)&default_trace_show_source,
1378 "Set display of source code with trace.\n", &setlist),
1379 &showlist);
1380
1381}
GDB Binutils - Deliverables
This page took 0.086152 seconds and 4 git commands to generate.