Commit | Line | Data |
---|---|---|
69517000 AC |
1 | /* Caching code for GDB, the GNU debugger. |
2 | ||
197e01b6 | 3 | Copyright (C) 1992, 1993, 1995, 1996, 1998, 1999, 2000, 2001, 2003 Free |
69517000 | 4 | Software Foundation, Inc. |
c906108c SS |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "dcache.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdb_string.h" | |
27 | #include "gdbcore.h" | |
4930751a | 28 | #include "target.h" |
c906108c | 29 | |
29e57380 C |
30 | /* The data cache could lead to incorrect results because it doesn't |
31 | know about volatile variables, thus making it impossible to debug | |
32 | functions which use memory mapped I/O devices. Set the nocache | |
33 | memory region attribute in those cases. | |
c906108c SS |
34 | |
35 | In general the dcache speeds up performance, some speed improvement | |
36 | comes from the actual caching mechanism, but the major gain is in | |
37 | the reduction of the remote protocol overhead; instead of reading | |
38 | or writing a large area of memory in 4 byte requests, the cache | |
39 | bundles up the requests into 32 byte (actually LINE_SIZE) chunks. | |
40 | Reducing the overhead to an eighth of what it was. This is very | |
41 | obvious when displaying a large amount of data, | |
42 | ||
43 | eg, x/200x 0 | |
44 | ||
45 | caching | no yes | |
46 | ---------------------------- | |
47 | first time | 4 sec 2 sec improvement due to chunking | |
48 | second time | 4 sec 0 sec improvement due to caching | |
49 | ||
50 | The cache structure is unusual, we keep a number of cache blocks | |
51 | (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory. | |
52 | Within each line we remember the address of the line (always a | |
53 | multiple of the LINE_SIZE) and a vector of bytes over the range. | |
54 | There's another vector which contains the state of the bytes. | |
55 | ||
56 | ENTRY_BAD means that the byte is just plain wrong, and has no | |
57 | correspondence with anything else (as it would when the cache is | |
58 | turned on, but nothing has been done to it. | |
59 | ||
60 | ENTRY_DIRTY means that the byte has some data in it which should be | |
61 | written out to the remote target one day, but contains correct | |
29e57380 C |
62 | data. |
63 | ||
64 | ENTRY_OK means that the data is the same in the cache as it is in | |
65 | remote memory. | |
c906108c SS |
66 | |
67 | ||
68 | The ENTRY_DIRTY state is necessary because GDB likes to write large | |
69 | lumps of memory in small bits. If the caching mechanism didn't | |
70 | maintain the DIRTY information, then something like a two byte | |
71 | write would mean that the entire cache line would have to be read, | |
72 | the two bytes modified and then written out again. The alternative | |
73 | would be to not read in the cache line in the first place, and just | |
74 | write the two bytes directly into target memory. The trouble with | |
75 | that is that it really nails performance, because of the remote | |
76 | protocol overhead. This way, all those little writes are bundled | |
77 | up into an entire cache line write in one go, without having to | |
78 | read the cache line in the first place. | |
29e57380 | 79 | */ |
c906108c | 80 | |
29e57380 | 81 | /* NOTE: Interaction of dcache and memory region attributes |
c906108c | 82 | |
29e57380 C |
83 | As there is no requirement that memory region attributes be aligned |
84 | to or be a multiple of the dcache page size, dcache_read_line() and | |
85 | dcache_write_line() must break up the page by memory region. If a | |
86 | chunk does not have the cache attribute set, an invalid memory type | |
87 | is set, etc., then the chunk is skipped. Those chunks are handled | |
88 | in target_xfer_memory() (or target_xfer_memory_partial()). | |
c906108c | 89 | |
29e57380 C |
90 | This doesn't occur very often. The most common occurance is when |
91 | the last bit of the .text segment and the first bit of the .data | |
92 | segment fall within the same dcache page with a ro/cacheable memory | |
93 | region defined for the .text segment and a rw/non-cacheable memory | |
94 | region defined for the .data segment. */ | |
c906108c SS |
95 | |
96 | /* This value regulates the number of cache blocks stored. | |
97 | Smaller values reduce the time spent searching for a cache | |
98 | line, and reduce memory requirements, but increase the risk | |
99 | of a line not being in memory */ | |
100 | ||
c5aa993b | 101 | #define DCACHE_SIZE 64 |
c906108c SS |
102 | |
103 | /* This value regulates the size of a cache line. Smaller values | |
104 | reduce the time taken to read a single byte, but reduce overall | |
105 | throughput. */ | |
106 | ||
c5aa993b | 107 | #define LINE_SIZE_POWER (5) |
c906108c SS |
108 | #define LINE_SIZE (1 << LINE_SIZE_POWER) |
109 | ||
110 | /* Each cache block holds LINE_SIZE bytes of data | |
111 | starting at a multiple-of-LINE_SIZE address. */ | |
112 | ||
c5aa993b | 113 | #define LINE_SIZE_MASK ((LINE_SIZE - 1)) |
c906108c SS |
114 | #define XFORM(x) ((x) & LINE_SIZE_MASK) |
115 | #define MASK(x) ((x) & ~LINE_SIZE_MASK) | |
116 | ||
117 | ||
c5aa993b JM |
118 | #define ENTRY_BAD 0 /* data at this byte is wrong */ |
119 | #define ENTRY_DIRTY 1 /* data at this byte needs to be written back */ | |
120 | #define ENTRY_OK 2 /* data at this byte is same as in memory */ | |
c906108c SS |
121 | |
122 | ||
123 | struct dcache_block | |
c5aa993b JM |
124 | { |
125 | struct dcache_block *p; /* next in list */ | |
126 | CORE_ADDR addr; /* Address for which data is recorded. */ | |
6c932e54 | 127 | gdb_byte data[LINE_SIZE]; /* bytes at given address */ |
c5aa993b | 128 | unsigned char state[LINE_SIZE]; /* what state the data is in */ |
c906108c | 129 | |
c5aa993b JM |
130 | /* whether anything in state is dirty - used to speed up the |
131 | dirty scan. */ | |
132 | int anydirty; | |
c906108c | 133 | |
c5aa993b JM |
134 | int refs; |
135 | }; | |
c906108c SS |
136 | |
137 | ||
29e57380 C |
138 | /* FIXME: dcache_struct used to have a cache_has_stuff field that was |
139 | used to record whether the cache had been accessed. This was used | |
140 | to invalidate the cache whenever caching was (re-)enabled (if the | |
141 | cache was disabled and later re-enabled, it could contain stale | |
142 | data). This was not needed because the cache is write through and | |
143 | the code that enables, disables, and deletes memory region all | |
144 | invalidate the cache. | |
145 | ||
146 | This is overkill, since it also invalidates cache lines from | |
147 | unrelated regions. One way this could be addressed by adding a | |
148 | new function that takes an address and a length and invalidates | |
149 | only those cache lines that match. */ | |
150 | ||
c5aa993b JM |
151 | struct dcache_struct |
152 | { | |
c5aa993b JM |
153 | /* free list */ |
154 | struct dcache_block *free_head; | |
155 | struct dcache_block *free_tail; | |
c906108c | 156 | |
c5aa993b JM |
157 | /* in use list */ |
158 | struct dcache_block *valid_head; | |
159 | struct dcache_block *valid_tail; | |
c906108c | 160 | |
c5aa993b JM |
161 | /* The cache itself. */ |
162 | struct dcache_block *the_cache; | |
c5aa993b | 163 | }; |
c906108c | 164 | |
8edbea78 | 165 | static struct dcache_block *dcache_hit (DCACHE *dcache, CORE_ADDR addr); |
c906108c | 166 | |
8edbea78 | 167 | static int dcache_write_line (DCACHE *dcache, struct dcache_block *db); |
c906108c | 168 | |
8edbea78 | 169 | static int dcache_read_line (DCACHE *dcache, struct dcache_block *db); |
c906108c | 170 | |
8edbea78 C |
171 | static struct dcache_block *dcache_alloc (DCACHE *dcache, CORE_ADDR addr); |
172 | ||
173 | static int dcache_writeback (DCACHE *dcache); | |
c906108c | 174 | |
a14ed312 | 175 | static void dcache_info (char *exp, int tty); |
c906108c | 176 | |
a14ed312 | 177 | void _initialize_dcache (void); |
c906108c | 178 | |
917317f4 | 179 | static int dcache_enabled_p = 0; |
920d2a44 AC |
180 | static void |
181 | show_dcache_enabled_p (struct ui_file *file, int from_tty, | |
182 | struct cmd_list_element *c, const char *value) | |
183 | { | |
184 | fprintf_filtered (file, _("Cache use for remote targets is %s.\n"), value); | |
185 | } | |
186 | ||
c906108c | 187 | |
c5aa993b | 188 | DCACHE *last_cache; /* Used by info dcache */ |
c906108c SS |
189 | |
190 | ||
191 | /* Free all the data cache blocks, thus discarding all cached data. */ | |
192 | ||
193 | void | |
4930751a | 194 | dcache_invalidate (DCACHE *dcache) |
c906108c SS |
195 | { |
196 | int i; | |
197 | dcache->valid_head = 0; | |
198 | dcache->valid_tail = 0; | |
199 | ||
200 | dcache->free_head = 0; | |
201 | dcache->free_tail = 0; | |
202 | ||
203 | for (i = 0; i < DCACHE_SIZE; i++) | |
204 | { | |
205 | struct dcache_block *db = dcache->the_cache + i; | |
206 | ||
207 | if (!dcache->free_head) | |
208 | dcache->free_head = db; | |
209 | else | |
210 | dcache->free_tail->p = db; | |
211 | dcache->free_tail = db; | |
212 | db->p = 0; | |
213 | } | |
214 | ||
c906108c SS |
215 | return; |
216 | } | |
217 | ||
218 | /* If addr is present in the dcache, return the address of the block | |
219 | containing it. */ | |
220 | ||
221 | static struct dcache_block * | |
fba45db2 | 222 | dcache_hit (DCACHE *dcache, CORE_ADDR addr) |
c906108c | 223 | { |
52f0bd74 | 224 | struct dcache_block *db; |
c906108c SS |
225 | |
226 | /* Search all cache blocks for one that is at this address. */ | |
227 | db = dcache->valid_head; | |
228 | ||
229 | while (db) | |
230 | { | |
c5aa993b | 231 | if (MASK (addr) == db->addr) |
c906108c SS |
232 | { |
233 | db->refs++; | |
234 | return db; | |
235 | } | |
236 | db = db->p; | |
237 | } | |
238 | ||
239 | return NULL; | |
240 | } | |
241 | ||
242 | /* Make sure that anything in this line which needs to | |
243 | be written is. */ | |
244 | ||
245 | static int | |
aa1ee363 | 246 | dcache_write_line (DCACHE *dcache, struct dcache_block *db) |
c906108c | 247 | { |
29e57380 | 248 | CORE_ADDR memaddr; |
6c932e54 | 249 | gdb_byte *myaddr; |
29e57380 C |
250 | int len; |
251 | int res; | |
252 | int reg_len; | |
253 | struct mem_region *region; | |
8edbea78 | 254 | |
29e57380 C |
255 | if (!db->anydirty) |
256 | return 1; | |
257 | ||
258 | len = LINE_SIZE; | |
259 | memaddr = db->addr; | |
260 | myaddr = db->data; | |
261 | ||
262 | while (len > 0) | |
c906108c | 263 | { |
29e57380 C |
264 | int s; |
265 | int e; | |
266 | int dirty_len; | |
267 | ||
268 | region = lookup_mem_region(memaddr); | |
269 | if (memaddr + len < region->hi) | |
270 | reg_len = len; | |
271 | else | |
272 | reg_len = region->hi - memaddr; | |
273 | ||
274 | if (!region->attrib.cache || region->attrib.mode == MEM_RO) | |
275 | { | |
276 | memaddr += reg_len; | |
277 | myaddr += reg_len; | |
278 | len -= reg_len; | |
279 | continue; | |
280 | } | |
281 | ||
282 | while (reg_len > 0) | |
c906108c | 283 | { |
29e57380 | 284 | s = XFORM(memaddr); |
c839c4db | 285 | while (reg_len > 0) { |
29e57380 C |
286 | if (db->state[s] == ENTRY_DIRTY) |
287 | break; | |
288 | s++; | |
289 | reg_len--; | |
c839c4db C |
290 | |
291 | memaddr++; | |
292 | myaddr++; | |
293 | len--; | |
294 | } | |
29e57380 C |
295 | |
296 | e = s; | |
c839c4db | 297 | while (reg_len > 0) { |
29e57380 C |
298 | if (db->state[e] != ENTRY_DIRTY) |
299 | break; | |
300 | e++; | |
301 | reg_len--; | |
c839c4db | 302 | } |
29e57380 C |
303 | |
304 | dirty_len = e - s; | |
cf7a04e8 DJ |
305 | res = target_write (¤t_target, TARGET_OBJECT_RAW_MEMORY, |
306 | NULL, myaddr, memaddr, dirty_len); | |
307 | if (res < dirty_len) | |
308 | return 0; | |
309 | ||
310 | memset (&db->state[XFORM(memaddr)], ENTRY_OK, res); | |
311 | memaddr += res; | |
312 | myaddr += res; | |
313 | len -= res; | |
c906108c | 314 | } |
c906108c | 315 | } |
29e57380 C |
316 | |
317 | db->anydirty = 0; | |
c906108c SS |
318 | return 1; |
319 | } | |
320 | ||
8edbea78 C |
321 | /* Read cache line */ |
322 | static int | |
323 | dcache_read_line (DCACHE *dcache, struct dcache_block *db) | |
324 | { | |
325 | CORE_ADDR memaddr; | |
6c932e54 | 326 | gdb_byte *myaddr; |
8edbea78 C |
327 | int len; |
328 | int res; | |
29e57380 C |
329 | int reg_len; |
330 | struct mem_region *region; | |
8edbea78 C |
331 | |
332 | /* If there are any dirty bytes in the line, it must be written | |
333 | before a new line can be read */ | |
334 | if (db->anydirty) | |
335 | { | |
336 | if (!dcache_write_line (dcache, db)) | |
337 | return 0; | |
338 | } | |
339 | ||
340 | len = LINE_SIZE; | |
341 | memaddr = db->addr; | |
342 | myaddr = db->data; | |
343 | ||
344 | while (len > 0) | |
345 | { | |
29e57380 C |
346 | region = lookup_mem_region(memaddr); |
347 | if (memaddr + len < region->hi) | |
348 | reg_len = len; | |
349 | else | |
350 | reg_len = region->hi - memaddr; | |
351 | ||
352 | if (!region->attrib.cache || region->attrib.mode == MEM_WO) | |
353 | { | |
354 | memaddr += reg_len; | |
355 | myaddr += reg_len; | |
356 | len -= reg_len; | |
357 | continue; | |
358 | } | |
359 | ||
cf7a04e8 DJ |
360 | res = target_read (¤t_target, TARGET_OBJECT_RAW_MEMORY, |
361 | NULL, myaddr, memaddr, reg_len); | |
362 | if (res < reg_len) | |
363 | return 0; | |
8edbea78 | 364 | |
cf7a04e8 DJ |
365 | memaddr += res; |
366 | myaddr += res; | |
367 | len -= res; | |
8edbea78 C |
368 | } |
369 | ||
370 | memset (db->state, ENTRY_OK, sizeof (db->data)); | |
371 | db->anydirty = 0; | |
372 | ||
373 | return 1; | |
374 | } | |
375 | ||
c906108c | 376 | /* Get a free cache block, put or keep it on the valid list, |
f1d7622b | 377 | and return its address. */ |
c906108c SS |
378 | |
379 | static struct dcache_block * | |
f1d7622b | 380 | dcache_alloc (DCACHE *dcache, CORE_ADDR addr) |
c906108c | 381 | { |
52f0bd74 | 382 | struct dcache_block *db; |
c906108c | 383 | |
c906108c SS |
384 | /* Take something from the free list */ |
385 | db = dcache->free_head; | |
386 | if (db) | |
387 | { | |
388 | dcache->free_head = db->p; | |
389 | } | |
390 | else | |
391 | { | |
392 | /* Nothing left on free list, so grab one from the valid list */ | |
393 | db = dcache->valid_head; | |
c906108c | 394 | |
8edbea78 C |
395 | if (!dcache_write_line (dcache, db)) |
396 | return NULL; | |
397 | ||
398 | dcache->valid_head = db->p; | |
c906108c SS |
399 | } |
400 | ||
f1d7622b C |
401 | db->addr = MASK(addr); |
402 | db->refs = 0; | |
403 | db->anydirty = 0; | |
404 | memset (db->state, ENTRY_BAD, sizeof (db->data)); | |
405 | ||
c906108c SS |
406 | /* append this line to end of valid list */ |
407 | if (!dcache->valid_head) | |
408 | dcache->valid_head = db; | |
409 | else | |
410 | dcache->valid_tail->p = db; | |
411 | dcache->valid_tail = db; | |
412 | db->p = 0; | |
413 | ||
414 | return db; | |
415 | } | |
416 | ||
29e57380 | 417 | /* Writeback any dirty lines. */ |
c906108c | 418 | static int |
fba45db2 | 419 | dcache_writeback (DCACHE *dcache) |
c906108c SS |
420 | { |
421 | struct dcache_block *db; | |
422 | ||
423 | db = dcache->valid_head; | |
424 | ||
425 | while (db) | |
426 | { | |
427 | if (!dcache_write_line (dcache, db)) | |
428 | return 0; | |
429 | db = db->p; | |
430 | } | |
431 | return 1; | |
432 | } | |
433 | ||
434 | ||
8edbea78 C |
435 | /* Using the data cache DCACHE return the contents of the byte at |
436 | address ADDR in the remote machine. | |
437 | ||
438 | Returns 0 on error. */ | |
439 | ||
440 | static int | |
6c932e54 | 441 | dcache_peek_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr) |
8edbea78 | 442 | { |
52f0bd74 | 443 | struct dcache_block *db = dcache_hit (dcache, addr); |
8edbea78 C |
444 | |
445 | if (!db) | |
446 | { | |
447 | db = dcache_alloc (dcache, addr); | |
448 | if (!db) | |
449 | return 0; | |
450 | } | |
451 | ||
452 | if (db->state[XFORM (addr)] == ENTRY_BAD) | |
453 | { | |
454 | if (!dcache_read_line(dcache, db)) | |
455 | return 0; | |
456 | } | |
457 | ||
458 | *ptr = db->data[XFORM (addr)]; | |
459 | return 1; | |
460 | } | |
461 | ||
462 | ||
c906108c SS |
463 | /* Write the byte at PTR into ADDR in the data cache. |
464 | Return zero on write error. | |
465 | */ | |
466 | ||
467 | static int | |
6c932e54 | 468 | dcache_poke_byte (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr) |
c906108c | 469 | { |
52f0bd74 | 470 | struct dcache_block *db = dcache_hit (dcache, addr); |
c906108c SS |
471 | |
472 | if (!db) | |
473 | { | |
f1d7622b | 474 | db = dcache_alloc (dcache, addr); |
8edbea78 C |
475 | if (!db) |
476 | return 0; | |
c906108c SS |
477 | } |
478 | ||
479 | db->data[XFORM (addr)] = *ptr; | |
480 | db->state[XFORM (addr)] = ENTRY_DIRTY; | |
481 | db->anydirty = 1; | |
482 | return 1; | |
483 | } | |
484 | ||
c906108c SS |
485 | /* Initialize the data cache. */ |
486 | DCACHE * | |
4930751a | 487 | dcache_init (void) |
c906108c SS |
488 | { |
489 | int csize = sizeof (struct dcache_block) * DCACHE_SIZE; | |
490 | DCACHE *dcache; | |
491 | ||
492 | dcache = (DCACHE *) xmalloc (sizeof (*dcache)); | |
c906108c SS |
493 | |
494 | dcache->the_cache = (struct dcache_block *) xmalloc (csize); | |
495 | memset (dcache->the_cache, 0, csize); | |
496 | ||
4930751a | 497 | dcache_invalidate (dcache); |
c906108c SS |
498 | |
499 | last_cache = dcache; | |
500 | return dcache; | |
501 | } | |
502 | ||
e99586d5 C |
503 | /* Free a data cache */ |
504 | void | |
505 | dcache_free (DCACHE *dcache) | |
506 | { | |
507 | if (last_cache == dcache) | |
508 | last_cache = NULL; | |
509 | ||
b8c9b27d KB |
510 | xfree (dcache->the_cache); |
511 | xfree (dcache); | |
e99586d5 C |
512 | } |
513 | ||
c906108c SS |
514 | /* Read or write LEN bytes from inferior memory at MEMADDR, transferring |
515 | to or from debugger address MYADDR. Write to inferior if SHOULD_WRITE is | |
516 | nonzero. | |
517 | ||
518 | Returns length of data written or read; 0 for error. | |
519 | ||
520 | This routine is indended to be called by remote_xfer_ functions. */ | |
521 | ||
522 | int | |
1b0ba102 AC |
523 | dcache_xfer_memory (DCACHE *dcache, CORE_ADDR memaddr, gdb_byte *myaddr, |
524 | int len, int should_write) | |
c906108c SS |
525 | { |
526 | int i; | |
6c932e54 | 527 | int (*xfunc) (DCACHE *dcache, CORE_ADDR addr, gdb_byte *ptr); |
29e57380 | 528 | xfunc = should_write ? dcache_poke_byte : dcache_peek_byte; |
c906108c | 529 | |
29e57380 | 530 | for (i = 0; i < len; i++) |
c906108c | 531 | { |
29e57380 C |
532 | if (!xfunc (dcache, memaddr + i, myaddr + i)) |
533 | return 0; | |
c906108c | 534 | } |
c906108c | 535 | |
29e57380 C |
536 | /* FIXME: There may be some benefit from moving the cache writeback |
537 | to a higher layer, as it could occur after a sequence of smaller | |
538 | writes have been completed (as when a stack frame is constructed | |
539 | for an inferior function call). Note that only moving it up one | |
540 | level to target_xfer_memory() (also target_xfer_memory_partial()) | |
541 | is not sufficent, since we want to coalesce memory transfers that | |
542 | are "logically" connected but not actually a single call to one | |
543 | of the memory transfer functions. */ | |
544 | ||
545 | if (should_write) | |
546 | dcache_writeback (dcache); | |
547 | ||
c906108c SS |
548 | return len; |
549 | } | |
550 | ||
c5aa993b | 551 | static void |
fba45db2 | 552 | dcache_info (char *exp, int tty) |
c906108c SS |
553 | { |
554 | struct dcache_block *p; | |
555 | ||
a3f17187 | 556 | printf_filtered (_("Dcache line width %d, depth %d\n"), |
c906108c SS |
557 | LINE_SIZE, DCACHE_SIZE); |
558 | ||
5e2039ea | 559 | if (last_cache) |
c906108c | 560 | { |
a3f17187 | 561 | printf_filtered (_("Cache state:\n")); |
5e2039ea C |
562 | |
563 | for (p = last_cache->valid_head; p; p = p->p) | |
564 | { | |
565 | int j; | |
a3f17187 | 566 | printf_filtered (_("Line at %s, referenced %d times\n"), |
5e2039ea | 567 | paddr (p->addr), p->refs); |
c906108c | 568 | |
5e2039ea C |
569 | for (j = 0; j < LINE_SIZE; j++) |
570 | printf_filtered ("%02x", p->data[j] & 0xFF); | |
a3f17187 | 571 | printf_filtered (("\n")); |
c906108c | 572 | |
5e2039ea | 573 | for (j = 0; j < LINE_SIZE; j++) |
8edbea78 | 574 | printf_filtered ("%2x", p->state[j]); |
5e2039ea C |
575 | printf_filtered ("\n"); |
576 | } | |
c906108c SS |
577 | } |
578 | } | |
579 | ||
580 | void | |
fba45db2 | 581 | _initialize_dcache (void) |
c906108c | 582 | { |
5bf193a2 AC |
583 | add_setshow_boolean_cmd ("remotecache", class_support, |
584 | &dcache_enabled_p, _("\ | |
585 | Set cache use for remote targets."), _("\ | |
586 | Show cache use for remote targets."), _("\ | |
c906108c SS |
587 | When on, use data caching for remote targets. For many remote targets\n\ |
588 | this option can offer better throughput for reading target memory.\n\ | |
589 | Unfortunately, gdb does not currently know anything about volatile\n\ | |
590 | registers and thus data caching will produce incorrect results with\n\ | |
5bf193a2 AC |
591 | volatile registers are in use. By default, this option is off."), |
592 | NULL, | |
920d2a44 | 593 | show_dcache_enabled_p, |
5bf193a2 | 594 | &setlist, &showlist); |
c906108c SS |
595 | |
596 | add_info ("dcache", dcache_info, | |
1bedd215 | 597 | _("Print information on the dcache performance.")); |
c906108c SS |
598 | |
599 | } |