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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
9ab9195f | 2 | Copyright 2002, 2003, 2004 Free Software Foundation, Inc. |
456f8b9d DB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
8baa6f92 | 22 | #include "gdb_string.h" |
456f8b9d | 23 | #include "inferior.h" |
456f8b9d DB |
24 | #include "gdbcore.h" |
25 | #include "arch-utils.h" | |
26 | #include "regcache.h" | |
8baa6f92 | 27 | #include "frame.h" |
1cb761c7 KB |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
8baa6f92 | 30 | #include "trad-frame.h" |
dcc6aaff | 31 | #include "dis-asm.h" |
526eef89 KB |
32 | #include "gdb_assert.h" |
33 | #include "sim-regno.h" | |
34 | #include "gdb/sim-frv.h" | |
35 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
634aa483 | 36 | #include "symtab.h" |
7e295833 KB |
37 | #include "elf-bfd.h" |
38 | #include "elf/frv.h" | |
39 | #include "osabi.h" | |
40 | #include "frv-tdep.h" | |
456f8b9d DB |
41 | |
42 | extern void _initialize_frv_tdep (void); | |
43 | ||
44 | static gdbarch_init_ftype frv_gdbarch_init; | |
45 | ||
46 | static gdbarch_register_name_ftype frv_register_name; | |
456f8b9d | 47 | static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; |
46a16dba | 48 | static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; |
456f8b9d | 49 | static gdbarch_skip_prologue_ftype frv_skip_prologue; |
456f8b9d | 50 | |
456f8b9d | 51 | |
1cb761c7 | 52 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 53 | { |
1cb761c7 KB |
54 | /* The previous frame's inner-most stack address. Used as this |
55 | frame ID's stack_addr. */ | |
56 | CORE_ADDR prev_sp; | |
456f8b9d | 57 | |
1cb761c7 KB |
58 | /* The frame's base, optionally used by the high-level debug info. */ |
59 | CORE_ADDR base; | |
8baa6f92 KB |
60 | |
61 | /* Table indicating the location of each and every register. */ | |
62 | struct trad_frame_saved_reg *saved_regs; | |
456f8b9d DB |
63 | }; |
64 | ||
456f8b9d DB |
65 | /* A structure describing a particular variant of the FRV. |
66 | We allocate and initialize one of these structures when we create | |
67 | the gdbarch object for a variant. | |
68 | ||
69 | At the moment, all the FR variants we support differ only in which | |
70 | registers are present; the portable code of GDB knows that | |
71 | registers whose names are the empty string don't exist, so the | |
72 | `register_names' array captures all the per-variant information we | |
73 | need. | |
74 | ||
75 | in the future, if we need to have per-variant maps for raw size, | |
76 | virtual type, etc., we should replace register_names with an array | |
77 | of structures, each of which gives all the necessary info for one | |
78 | register. Don't stick parallel arrays in here --- that's so | |
79 | Fortran. */ | |
80 | struct gdbarch_tdep | |
81 | { | |
7e295833 KB |
82 | /* Which ABI is in use? */ |
83 | enum frv_abi frv_abi; | |
84 | ||
456f8b9d DB |
85 | /* How many general-purpose registers does this variant have? */ |
86 | int num_gprs; | |
87 | ||
88 | /* How many floating-point registers does this variant have? */ | |
89 | int num_fprs; | |
90 | ||
91 | /* How many hardware watchpoints can it support? */ | |
92 | int num_hw_watchpoints; | |
93 | ||
94 | /* How many hardware breakpoints can it support? */ | |
95 | int num_hw_breakpoints; | |
96 | ||
97 | /* Register names. */ | |
98 | char **register_names; | |
5ecb7103 KB |
99 | |
100 | /* Given NEXT_FRAME, determine the address of register REGNO saved in | |
101 | the calling sigtramp frame. */ | |
102 | CORE_ADDR (*sigcontext_reg_addr) (struct frame_info *next_frame, int regno, | |
103 | CORE_ADDR *); | |
456f8b9d DB |
104 | }; |
105 | ||
106 | #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) | |
107 | ||
7e295833 KB |
108 | /* Return the FR-V ABI associated with GDBARCH. */ |
109 | enum frv_abi | |
110 | frv_abi (struct gdbarch *gdbarch) | |
111 | { | |
112 | return gdbarch_tdep (gdbarch)->frv_abi; | |
113 | } | |
114 | ||
5ecb7103 KB |
115 | /* Set sigcontext_reg_addr. */ |
116 | void | |
117 | frv_set_sigcontext_reg_addr (struct gdbarch *gdbarch, | |
118 | CORE_ADDR (*sigcontext_reg_addr) | |
119 | (struct frame_info *, int, CORE_ADDR *)) | |
120 | { | |
121 | gdbarch_tdep (gdbarch)->sigcontext_reg_addr = sigcontext_reg_addr; | |
122 | } | |
123 | ||
7e295833 KB |
124 | /* Fetch the interpreter and executable loadmap addresses (for shared |
125 | library support) for the FDPIC ABI. Return 0 if successful, -1 if | |
126 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ | |
127 | int | |
128 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, | |
129 | CORE_ADDR *exec_addr) | |
130 | { | |
131 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) | |
132 | return -1; | |
133 | else | |
134 | { | |
135 | if (interp_addr != NULL) | |
136 | { | |
137 | ULONGEST val; | |
138 | regcache_cooked_read_unsigned (current_regcache, | |
139 | fdpic_loadmap_interp_regnum, &val); | |
140 | *interp_addr = val; | |
141 | } | |
142 | if (exec_addr != NULL) | |
143 | { | |
144 | ULONGEST val; | |
145 | regcache_cooked_read_unsigned (current_regcache, | |
146 | fdpic_loadmap_exec_regnum, &val); | |
147 | *exec_addr = val; | |
148 | } | |
149 | return 0; | |
150 | } | |
151 | } | |
456f8b9d DB |
152 | |
153 | /* Allocate a new variant structure, and set up default values for all | |
154 | the fields. */ | |
155 | static struct gdbarch_tdep * | |
5ae5f592 | 156 | new_variant (void) |
456f8b9d DB |
157 | { |
158 | struct gdbarch_tdep *var; | |
159 | int r; | |
160 | char buf[20]; | |
161 | ||
162 | var = xmalloc (sizeof (*var)); | |
163 | memset (var, 0, sizeof (*var)); | |
164 | ||
7e295833 | 165 | var->frv_abi = FRV_ABI_EABI; |
456f8b9d DB |
166 | var->num_gprs = 64; |
167 | var->num_fprs = 64; | |
168 | var->num_hw_watchpoints = 0; | |
169 | var->num_hw_breakpoints = 0; | |
170 | ||
171 | /* By default, don't supply any general-purpose or floating-point | |
172 | register names. */ | |
6a748db6 KB |
173 | var->register_names |
174 | = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) | |
175 | * sizeof (char *)); | |
176 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) | |
456f8b9d DB |
177 | var->register_names[r] = ""; |
178 | ||
526eef89 | 179 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 180 | registers. */ |
456f8b9d DB |
181 | |
182 | var->register_names[pc_regnum] = "pc"; | |
183 | var->register_names[lr_regnum] = "lr"; | |
184 | var->register_names[lcr_regnum] = "lcr"; | |
185 | ||
186 | var->register_names[psr_regnum] = "psr"; | |
187 | var->register_names[ccr_regnum] = "ccr"; | |
188 | var->register_names[cccr_regnum] = "cccr"; | |
189 | var->register_names[tbr_regnum] = "tbr"; | |
190 | ||
191 | /* Debug registers. */ | |
192 | var->register_names[brr_regnum] = "brr"; | |
193 | var->register_names[dbar0_regnum] = "dbar0"; | |
194 | var->register_names[dbar1_regnum] = "dbar1"; | |
195 | var->register_names[dbar2_regnum] = "dbar2"; | |
196 | var->register_names[dbar3_regnum] = "dbar3"; | |
197 | ||
526eef89 KB |
198 | /* iacc0 (Only found on MB93405.) */ |
199 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
200 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
6a748db6 | 201 | var->register_names[iacc0_regnum] = "iacc0"; |
526eef89 | 202 | |
8b67aa36 KB |
203 | /* fsr0 (Found on FR555 and FR501.) */ |
204 | var->register_names[fsr0_regnum] = "fsr0"; | |
205 | ||
206 | /* acc0 - acc7. The architecture provides for the possibility of many | |
207 | more (up to 64 total), but we don't want to make that big of a hole | |
208 | in the G packet. If we need more in the future, we'll add them | |
209 | elsewhere. */ | |
210 | for (r = acc0_regnum; r <= acc7_regnum; r++) | |
211 | { | |
212 | char *buf; | |
213 | xasprintf (&buf, "acc%d", r - acc0_regnum); | |
214 | var->register_names[r] = buf; | |
215 | } | |
216 | ||
217 | /* accg0 - accg7: These are one byte registers. The remote protocol | |
218 | provides the raw values packed four into a slot. accg0123 and | |
219 | accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. | |
220 | We don't provide names for accg0123 and accg4567 since the user will | |
221 | likely not want to see these raw values. */ | |
222 | ||
223 | for (r = accg0_regnum; r <= accg7_regnum; r++) | |
224 | { | |
225 | char *buf; | |
226 | xasprintf (&buf, "accg%d", r - accg0_regnum); | |
227 | var->register_names[r] = buf; | |
228 | } | |
229 | ||
230 | /* msr0 and msr1. */ | |
231 | ||
232 | var->register_names[msr0_regnum] = "msr0"; | |
233 | var->register_names[msr1_regnum] = "msr1"; | |
234 | ||
235 | /* gner and fner registers. */ | |
236 | var->register_names[gner0_regnum] = "gner0"; | |
237 | var->register_names[gner1_regnum] = "gner1"; | |
238 | var->register_names[fner0_regnum] = "fner0"; | |
239 | var->register_names[fner1_regnum] = "fner1"; | |
240 | ||
456f8b9d DB |
241 | return var; |
242 | } | |
243 | ||
244 | ||
245 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
246 | registers, and fill in the names array appropriately. */ | |
247 | static void | |
248 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
249 | { | |
250 | int r; | |
251 | ||
252 | var->num_gprs = num_gprs; | |
253 | ||
254 | for (r = 0; r < num_gprs; ++r) | |
255 | { | |
256 | char buf[20]; | |
257 | ||
258 | sprintf (buf, "gr%d", r); | |
259 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
260 | } | |
261 | } | |
262 | ||
263 | ||
264 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
265 | registers, and fill in the names array appropriately. */ | |
266 | static void | |
267 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
268 | { | |
269 | int r; | |
270 | ||
271 | var->num_fprs = num_fprs; | |
272 | ||
273 | for (r = 0; r < num_fprs; ++r) | |
274 | { | |
275 | char buf[20]; | |
276 | ||
277 | sprintf (buf, "fr%d", r); | |
278 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
279 | } | |
280 | } | |
281 | ||
7e295833 KB |
282 | static void |
283 | set_variant_abi_fdpic (struct gdbarch_tdep *var) | |
284 | { | |
285 | var->frv_abi = FRV_ABI_FDPIC; | |
286 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); | |
287 | var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp"); | |
288 | } | |
456f8b9d | 289 | |
b2d6d697 KB |
290 | static void |
291 | set_variant_scratch_registers (struct gdbarch_tdep *var) | |
292 | { | |
293 | var->register_names[scr0_regnum] = xstrdup ("scr0"); | |
294 | var->register_names[scr1_regnum] = xstrdup ("scr1"); | |
295 | var->register_names[scr2_regnum] = xstrdup ("scr2"); | |
296 | var->register_names[scr3_regnum] = xstrdup ("scr3"); | |
297 | } | |
298 | ||
456f8b9d DB |
299 | static const char * |
300 | frv_register_name (int reg) | |
301 | { | |
302 | if (reg < 0) | |
303 | return "?toosmall?"; | |
6a748db6 | 304 | if (reg >= frv_num_regs + frv_num_pseudo_regs) |
456f8b9d DB |
305 | return "?toolarge?"; |
306 | ||
307 | return CURRENT_VARIANT->register_names[reg]; | |
308 | } | |
309 | ||
526eef89 | 310 | |
456f8b9d | 311 | static struct type * |
7f398216 | 312 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 313 | { |
526eef89 | 314 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
456f8b9d | 315 | return builtin_type_float; |
6a748db6 KB |
316 | else if (reg == iacc0_regnum) |
317 | return builtin_type_int64; | |
456f8b9d | 318 | else |
526eef89 | 319 | return builtin_type_int32; |
456f8b9d DB |
320 | } |
321 | ||
6a748db6 KB |
322 | static void |
323 | frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
324 | int reg, void *buffer) | |
325 | { | |
326 | if (reg == iacc0_regnum) | |
327 | { | |
328 | regcache_raw_read (regcache, iacc0h_regnum, buffer); | |
329 | regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
330 | } | |
8b67aa36 KB |
331 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
332 | { | |
333 | /* The accg raw registers have four values in each slot with the | |
334 | lowest register number occupying the first byte. */ | |
335 | ||
336 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
337 | int byte_num = (reg - accg0_regnum) % 4; | |
338 | bfd_byte buf[4]; | |
339 | ||
340 | regcache_raw_read (regcache, raw_regnum, buf); | |
341 | memset (buffer, 0, 4); | |
342 | /* FR-V is big endian, so put the requested byte in the first byte | |
343 | of the buffer allocated to hold the pseudo-register. */ | |
344 | ((bfd_byte *) buffer)[0] = buf[byte_num]; | |
345 | } | |
6a748db6 KB |
346 | } |
347 | ||
348 | static void | |
349 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
350 | int reg, const void *buffer) | |
351 | { | |
352 | if (reg == iacc0_regnum) | |
353 | { | |
354 | regcache_raw_write (regcache, iacc0h_regnum, buffer); | |
355 | regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
356 | } | |
8b67aa36 KB |
357 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
358 | { | |
359 | /* The accg raw registers have four values in each slot with the | |
360 | lowest register number occupying the first byte. */ | |
361 | ||
362 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
363 | int byte_num = (reg - accg0_regnum) % 4; | |
364 | char buf[4]; | |
365 | ||
366 | regcache_raw_read (regcache, raw_regnum, buf); | |
367 | buf[byte_num] = ((bfd_byte *) buffer)[0]; | |
368 | regcache_raw_write (regcache, raw_regnum, buf); | |
369 | } | |
6a748db6 KB |
370 | } |
371 | ||
526eef89 KB |
372 | static int |
373 | frv_register_sim_regno (int reg) | |
374 | { | |
375 | static const int spr_map[] = | |
376 | { | |
377 | H_SPR_PSR, /* psr_regnum */ | |
378 | H_SPR_CCR, /* ccr_regnum */ | |
379 | H_SPR_CCCR, /* cccr_regnum */ | |
8b67aa36 KB |
380 | -1, /* fdpic_loadmap_exec_regnum */ |
381 | -1, /* fdpic_loadmap_interp_regnum */ | |
526eef89 KB |
382 | -1, /* 134 */ |
383 | H_SPR_TBR, /* tbr_regnum */ | |
384 | H_SPR_BRR, /* brr_regnum */ | |
385 | H_SPR_DBAR0, /* dbar0_regnum */ | |
386 | H_SPR_DBAR1, /* dbar1_regnum */ | |
387 | H_SPR_DBAR2, /* dbar2_regnum */ | |
388 | H_SPR_DBAR3, /* dbar3_regnum */ | |
8b67aa36 KB |
389 | H_SPR_SCR0, /* scr0_regnum */ |
390 | H_SPR_SCR1, /* scr1_regnum */ | |
391 | H_SPR_SCR2, /* scr2_regnum */ | |
392 | H_SPR_SCR3, /* scr3_regnum */ | |
526eef89 KB |
393 | H_SPR_LR, /* lr_regnum */ |
394 | H_SPR_LCR, /* lcr_regnum */ | |
395 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
8b67aa36 KB |
396 | H_SPR_IACC0L, /* iacc0l_regnum */ |
397 | H_SPR_FSR0, /* fsr0_regnum */ | |
398 | /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ | |
399 | -1, /* acc0_regnum */ | |
400 | -1, /* acc1_regnum */ | |
401 | -1, /* acc2_regnum */ | |
402 | -1, /* acc3_regnum */ | |
403 | -1, /* acc4_regnum */ | |
404 | -1, /* acc5_regnum */ | |
405 | -1, /* acc6_regnum */ | |
406 | -1, /* acc7_regnum */ | |
407 | -1, /* acc0123_regnum */ | |
408 | -1, /* acc4567_regnum */ | |
409 | H_SPR_MSR0, /* msr0_regnum */ | |
410 | H_SPR_MSR1, /* msr1_regnum */ | |
411 | H_SPR_GNER0, /* gner0_regnum */ | |
412 | H_SPR_GNER1, /* gner1_regnum */ | |
413 | H_SPR_FNER0, /* fner0_regnum */ | |
414 | H_SPR_FNER1, /* fner1_regnum */ | |
526eef89 KB |
415 | }; |
416 | ||
417 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
418 | ||
419 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
420 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
421 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
422 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
423 | else if (pc_regnum == reg) | |
424 | return SIM_FRV_PC_REGNUM; | |
425 | else if (reg >= first_spr_regnum | |
426 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
427 | { | |
428 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
429 | ||
430 | if (spr_reg_offset < 0) | |
431 | return SIM_REGNO_DOES_NOT_EXIST; | |
432 | else | |
433 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
434 | } | |
435 | ||
436 | internal_error (__FILE__, __LINE__, "Bad register number %d", reg); | |
437 | } | |
438 | ||
456f8b9d DB |
439 | static const unsigned char * |
440 | frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) | |
441 | { | |
442 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; | |
443 | *lenp = sizeof (breakpoint); | |
444 | return breakpoint; | |
445 | } | |
446 | ||
46a16dba KB |
447 | /* Define the maximum number of instructions which may be packed into a |
448 | bundle (VLIW instruction). */ | |
449 | static const int max_instrs_per_bundle = 8; | |
450 | ||
451 | /* Define the size (in bytes) of an FR-V instruction. */ | |
452 | static const int frv_instr_size = 4; | |
453 | ||
454 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
455 | constraint that a break instruction must not appear as any but the | |
456 | first instruction in the bundle. */ | |
457 | static CORE_ADDR | |
458 | frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
459 | { | |
460 | int count = max_instrs_per_bundle; | |
461 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
462 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
463 | ||
464 | /* Find the end of the previous packing sequence. This will be indicated | |
465 | by either attempting to access some inaccessible memory or by finding | |
466 | an instruction word whose packing bit is set to one. */ | |
467 | while (count-- > 0 && addr >= func_start) | |
468 | { | |
469 | char instr[frv_instr_size]; | |
470 | int status; | |
471 | ||
472 | status = read_memory_nobpt (addr, instr, sizeof instr); | |
473 | ||
474 | if (status != 0) | |
475 | break; | |
476 | ||
477 | /* This is a big endian architecture, so byte zero will have most | |
478 | significant byte. The most significant bit of this byte is the | |
479 | packing bit. */ | |
480 | if (instr[0] & 0x80) | |
481 | break; | |
482 | ||
483 | addr -= frv_instr_size; | |
484 | } | |
485 | ||
486 | if (count > 0) | |
487 | bpaddr = addr + frv_instr_size; | |
488 | ||
489 | return bpaddr; | |
490 | } | |
491 | ||
456f8b9d DB |
492 | |
493 | /* Return true if REG is a caller-saves ("scratch") register, | |
494 | false otherwise. */ | |
495 | static int | |
496 | is_caller_saves_reg (int reg) | |
497 | { | |
498 | return ((4 <= reg && reg <= 7) | |
499 | || (14 <= reg && reg <= 15) | |
500 | || (32 <= reg && reg <= 47)); | |
501 | } | |
502 | ||
503 | ||
504 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
505 | static int | |
506 | is_callee_saves_reg (int reg) | |
507 | { | |
508 | return ((16 <= reg && reg <= 31) | |
509 | || (48 <= reg && reg <= 63)); | |
510 | } | |
511 | ||
512 | ||
513 | /* Return true if REG is an argument register, false otherwise. */ | |
514 | static int | |
515 | is_argument_reg (int reg) | |
516 | { | |
517 | return (8 <= reg && reg <= 13); | |
518 | } | |
519 | ||
456f8b9d DB |
520 | /* Scan an FR-V prologue, starting at PC, until frame->PC. |
521 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
522 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
523 | Return the first PC value after the prologue. | |
524 | ||
525 | Note that, for unoptimized code, we almost don't need this function | |
526 | at all; all arguments and locals live on the stack, so we just need | |
527 | the FP to find everything. The catch: structures passed by value | |
528 | have their addresses living in registers; they're never spilled to | |
529 | the stack. So if you ever want to be able to get to these | |
530 | arguments in any frame but the top, you'll need to do this serious | |
531 | prologue analysis. */ | |
532 | static CORE_ADDR | |
1cb761c7 KB |
533 | frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
534 | struct frv_unwind_cache *info) | |
456f8b9d DB |
535 | { |
536 | /* When writing out instruction bitpatterns, we use the following | |
537 | letters to label instruction fields: | |
538 | P - The parallel bit. We don't use this. | |
539 | J - The register number of GRj in the instruction description. | |
540 | K - The register number of GRk in the instruction description. | |
541 | I - The register number of GRi. | |
542 | S - a signed imediate offset. | |
543 | U - an unsigned immediate offset. | |
544 | ||
545 | The dots below the numbers indicate where hex digit boundaries | |
546 | fall, to make it easier to check the numbers. */ | |
547 | ||
548 | /* Non-zero iff we've seen the instruction that initializes the | |
549 | frame pointer for this function's frame. */ | |
550 | int fp_set = 0; | |
551 | ||
552 | /* If fp_set is non_zero, then this is the distance from | |
553 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
554 | int fp_offset = 0; | |
555 | ||
556 | /* Total size of frame prior to any alloca operations. */ | |
557 | int framesize = 0; | |
558 | ||
1cb761c7 KB |
559 | /* Flag indicating if lr has been saved on the stack. */ |
560 | int lr_saved_on_stack = 0; | |
561 | ||
456f8b9d DB |
562 | /* The number of the general-purpose register we saved the return |
563 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
564 | int lr_save_reg = -1; | |
565 | ||
1cb761c7 KB |
566 | /* Offset (from sp) at which lr has been saved on the stack. */ |
567 | ||
568 | int lr_sp_offset = 0; | |
456f8b9d DB |
569 | |
570 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
571 | register i has been saved at gr_sp_offset[i] from the stack | |
572 | pointer. */ | |
573 | char gr_saved[64]; | |
574 | int gr_sp_offset[64]; | |
575 | ||
d40fcd7b KB |
576 | /* The address of the most recently scanned prologue instruction. */ |
577 | CORE_ADDR last_prologue_pc; | |
578 | ||
579 | /* The address of the next instruction. */ | |
580 | CORE_ADDR next_pc; | |
581 | ||
582 | /* The upper bound to of the pc values to scan. */ | |
583 | CORE_ADDR lim_pc; | |
584 | ||
456f8b9d DB |
585 | memset (gr_saved, 0, sizeof (gr_saved)); |
586 | ||
d40fcd7b KB |
587 | last_prologue_pc = pc; |
588 | ||
589 | /* Try to compute an upper limit (on how far to scan) based on the | |
590 | line number info. */ | |
591 | lim_pc = skip_prologue_using_sal (pc); | |
592 | /* If there's no line number info, lim_pc will be 0. In that case, | |
593 | set the limit to be 100 instructions away from pc. Hopefully, this | |
594 | will be far enough away to account for the entire prologue. Don't | |
595 | worry about overshooting the end of the function. The scan loop | |
596 | below contains some checks to avoid scanning unreasonably far. */ | |
597 | if (lim_pc == 0) | |
598 | lim_pc = pc + 400; | |
599 | ||
600 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
601 | will catch those cases where the pc is in the prologue. */ | |
602 | if (next_frame) | |
603 | { | |
604 | CORE_ADDR frame_pc = frame_pc_unwind (next_frame); | |
605 | if (frame_pc < lim_pc) | |
606 | lim_pc = frame_pc; | |
607 | } | |
608 | ||
609 | /* Scan the prologue. */ | |
610 | while (pc < lim_pc) | |
456f8b9d | 611 | { |
1ccda5e9 KB |
612 | char buf[frv_instr_size]; |
613 | LONGEST op; | |
614 | ||
615 | if (target_read_memory (pc, buf, sizeof buf) != 0) | |
616 | break; | |
617 | op = extract_signed_integer (buf, sizeof buf); | |
618 | ||
d40fcd7b | 619 | next_pc = pc + 4; |
456f8b9d DB |
620 | |
621 | /* The tests in this chain of ifs should be in order of | |
622 | decreasing selectivity, so that more particular patterns get | |
623 | to fire before less particular patterns. */ | |
624 | ||
d40fcd7b KB |
625 | /* Some sort of control transfer instruction: stop scanning prologue. |
626 | Integer Conditional Branch: | |
627 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
628 | Floating-point / media Conditional Branch: | |
629 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
630 | LCR Conditional Branch to LR | |
631 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
632 | Integer conditional Branches to LR | |
633 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
634 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
635 | Floating-point/Media Branches to LR | |
636 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
637 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
638 | Jump and Link | |
639 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
640 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
641 | Call | |
642 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
643 | Return from Trap | |
644 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
645 | Integer Conditional Trap | |
646 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
647 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
648 | Floating-point /media Conditional Trap | |
649 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
650 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
651 | Break | |
652 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
653 | Media Trap | |
654 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
655 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
656 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ | |
657 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ | |
658 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
659 | { | |
660 | /* Stop scanning; not in prologue any longer. */ | |
661 | break; | |
662 | } | |
663 | ||
664 | /* Loading something from memory into fp probably means that | |
665 | we're in the epilogue. Stop scanning the prologue. | |
666 | ld @(GRi, GRk), fp | |
667 | X 000010 0000010 XXXXXX 000100 XXXXXX | |
668 | ldi @(GRi, d12), fp | |
669 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
670 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
671 | || (op & 0x7ffc0000) == 0x04c80000) | |
672 | { | |
673 | break; | |
674 | } | |
675 | ||
456f8b9d DB |
676 | /* Setting the FP from the SP: |
677 | ori sp, 0, fp | |
678 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
679 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
680 | . . . . . . . . | |
681 | We treat this as part of the prologue. */ | |
d40fcd7b | 682 | else if ((op & 0x7fffffff) == 0x04881000) |
456f8b9d DB |
683 | { |
684 | fp_set = 1; | |
685 | fp_offset = 0; | |
d40fcd7b | 686 | last_prologue_pc = next_pc; |
456f8b9d DB |
687 | } |
688 | ||
689 | /* Move the link register to the scratch register grJ, before saving: | |
690 | movsg lr, grJ | |
691 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
692 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
693 | . . . . . . . . | |
694 | We treat this as part of the prologue. */ | |
695 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
696 | { | |
697 | int gr_j = op & 0x3f; | |
698 | ||
699 | /* If we're moving it to a scratch register, that's fine. */ | |
700 | if (is_caller_saves_reg (gr_j)) | |
d40fcd7b KB |
701 | { |
702 | lr_save_reg = gr_j; | |
703 | last_prologue_pc = next_pc; | |
704 | } | |
456f8b9d DB |
705 | } |
706 | ||
707 | /* To save multiple callee-saves registers on the stack, at | |
708 | offset zero: | |
709 | ||
710 | std grK,@(sp,gr0) | |
711 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
712 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
713 | ||
714 | stq grK,@(sp,gr0) | |
715 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
716 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
717 | . . . . . . . . | |
718 | We treat this as part of the prologue, and record the register's | |
719 | saved address in the frame structure. */ | |
720 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
721 | || (op & 0x01ffffff) == 0x000c1100) | |
722 | { | |
723 | int gr_k = ((op >> 25) & 0x3f); | |
724 | int ope = ((op >> 6) & 0x3f); | |
725 | int count; | |
726 | int i; | |
727 | ||
728 | /* Is it an std or an stq? */ | |
729 | if (ope == 0x03) | |
730 | count = 2; | |
731 | else | |
732 | count = 4; | |
733 | ||
734 | /* Is it really a callee-saves register? */ | |
735 | if (is_callee_saves_reg (gr_k)) | |
736 | { | |
737 | for (i = 0; i < count; i++) | |
738 | { | |
739 | gr_saved[gr_k + i] = 1; | |
740 | gr_sp_offset[gr_k + i] = 4 * i; | |
741 | } | |
d40fcd7b | 742 | last_prologue_pc = next_pc; |
456f8b9d | 743 | } |
456f8b9d DB |
744 | } |
745 | ||
746 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
747 | addi sp, S, sp | |
748 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
749 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
750 | . . . . . . . . | |
751 | We treat this as part of the prologue. */ | |
752 | else if ((op & 0x7ffff000) == 0x02401000) | |
753 | { | |
d40fcd7b KB |
754 | if (framesize == 0) |
755 | { | |
756 | /* Sign-extend the twelve-bit field. | |
757 | (Isn't there a better way to do this?) */ | |
758 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
456f8b9d | 759 | |
d40fcd7b KB |
760 | framesize -= s; |
761 | last_prologue_pc = pc; | |
762 | } | |
763 | else | |
764 | { | |
765 | /* If the prologue is being adjusted again, we've | |
766 | likely gone too far; i.e. we're probably in the | |
767 | epilogue. */ | |
768 | break; | |
769 | } | |
456f8b9d DB |
770 | } |
771 | ||
772 | /* Setting the FP to a constant distance from the SP: | |
773 | addi sp, S, fp | |
774 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
775 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
776 | . . . . . . . . | |
777 | We treat this as part of the prologue. */ | |
778 | else if ((op & 0x7ffff000) == 0x04401000) | |
779 | { | |
780 | /* Sign-extend the twelve-bit field. | |
781 | (Isn't there a better way to do this?) */ | |
782 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
783 | fp_set = 1; | |
784 | fp_offset = s; | |
d40fcd7b | 785 | last_prologue_pc = pc; |
456f8b9d DB |
786 | } |
787 | ||
788 | /* To spill an argument register to a scratch register: | |
789 | ori GRi, 0, GRk | |
790 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
791 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
792 | . . . . . . . . | |
793 | For the time being, we treat this as a prologue instruction, | |
794 | assuming that GRi is an argument register. This one's kind | |
795 | of suspicious, because it seems like it could be part of a | |
796 | legitimate body instruction. But we only come here when the | |
797 | source info wasn't helpful, so we have to do the best we can. | |
798 | Hopefully once GCC and GDB agree on how to emit line number | |
799 | info for prologues, then this code will never come into play. */ | |
800 | else if ((op & 0x01fc0fff) == 0x00880000) | |
801 | { | |
802 | int gr_i = ((op >> 12) & 0x3f); | |
803 | ||
d40fcd7b KB |
804 | /* Make sure that the source is an arg register; if it is, we'll |
805 | treat it as a prologue instruction. */ | |
806 | if (is_argument_reg (gr_i)) | |
807 | last_prologue_pc = next_pc; | |
456f8b9d DB |
808 | } |
809 | ||
810 | /* To spill 16-bit values to the stack: | |
811 | sthi GRk, @(fp, s) | |
812 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
813 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
814 | . . . . . . . . | |
815 | And for 8-bit values, we use STB instructions. | |
816 | stbi GRk, @(fp, s) | |
817 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
818 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
819 | . . . . . . . . | |
820 | We check that GRk is really an argument register, and treat | |
821 | all such as part of the prologue. */ | |
822 | else if ( (op & 0x01fff000) == 0x01442000 | |
823 | || (op & 0x01fff000) == 0x01402000) | |
824 | { | |
825 | int gr_k = ((op >> 25) & 0x3f); | |
826 | ||
d40fcd7b KB |
827 | /* Make sure that GRk is really an argument register; treat |
828 | it as a prologue instruction if so. */ | |
829 | if (is_argument_reg (gr_k)) | |
830 | last_prologue_pc = next_pc; | |
456f8b9d DB |
831 | } |
832 | ||
833 | /* To save multiple callee-saves register on the stack, at a | |
834 | non-zero offset: | |
835 | ||
836 | stdi GRk, @(sp, s) | |
837 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
838 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
839 | . . . . . . . . | |
840 | stqi GRk, @(sp, s) | |
841 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
842 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
843 | . . . . . . . . | |
844 | We treat this as part of the prologue, and record the register's | |
845 | saved address in the frame structure. */ | |
846 | else if ((op & 0x01fff000) == 0x014c1000 | |
847 | || (op & 0x01fff000) == 0x01501000) | |
848 | { | |
849 | int gr_k = ((op >> 25) & 0x3f); | |
850 | int count; | |
851 | int i; | |
852 | ||
853 | /* Is it a stdi or a stqi? */ | |
854 | if ((op & 0x01fff000) == 0x014c1000) | |
855 | count = 2; | |
856 | else | |
857 | count = 4; | |
858 | ||
859 | /* Is it really a callee-saves register? */ | |
860 | if (is_callee_saves_reg (gr_k)) | |
861 | { | |
862 | /* Sign-extend the twelve-bit field. | |
863 | (Isn't there a better way to do this?) */ | |
864 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
865 | ||
866 | for (i = 0; i < count; i++) | |
867 | { | |
868 | gr_saved[gr_k + i] = 1; | |
869 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
870 | } | |
d40fcd7b | 871 | last_prologue_pc = next_pc; |
456f8b9d | 872 | } |
456f8b9d DB |
873 | } |
874 | ||
875 | /* Storing any kind of integer register at any constant offset | |
876 | from any other register. | |
877 | ||
878 | st GRk, @(GRi, gr0) | |
879 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
880 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
881 | . . . . . . . . | |
882 | sti GRk, @(GRi, d12) | |
883 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
884 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
885 | . . . . . . . . | |
886 | These could be almost anything, but a lot of prologue | |
887 | instructions fall into this pattern, so let's decode the | |
888 | instruction once, and then work at a higher level. */ | |
889 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
890 | || ((op & 0x01fc0000) == 0x01480000)) | |
891 | { | |
892 | int gr_k = ((op >> 25) & 0x3f); | |
893 | int gr_i = ((op >> 12) & 0x3f); | |
894 | int offset; | |
895 | ||
896 | /* Are we storing with gr0 as an offset, or using an | |
897 | immediate value? */ | |
898 | if ((op & 0x01fc0fff) == 0x000c0080) | |
899 | offset = 0; | |
900 | else | |
901 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
902 | ||
903 | /* If the address isn't relative to the SP or FP, it's not a | |
904 | prologue instruction. */ | |
905 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
d40fcd7b KB |
906 | { |
907 | /* Do nothing; not a prologue instruction. */ | |
908 | } | |
456f8b9d DB |
909 | |
910 | /* Saving the old FP in the new frame (relative to the SP). */ | |
d40fcd7b | 911 | else if (gr_k == fp_regnum && gr_i == sp_regnum) |
1cb761c7 KB |
912 | { |
913 | gr_saved[fp_regnum] = 1; | |
914 | gr_sp_offset[fp_regnum] = offset; | |
d40fcd7b | 915 | last_prologue_pc = next_pc; |
1cb761c7 | 916 | } |
456f8b9d DB |
917 | |
918 | /* Saving callee-saves register(s) on the stack, relative to | |
919 | the SP. */ | |
920 | else if (gr_i == sp_regnum | |
921 | && is_callee_saves_reg (gr_k)) | |
922 | { | |
923 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
924 | if (gr_i == sp_regnum) |
925 | gr_sp_offset[gr_k] = offset; | |
926 | else | |
927 | gr_sp_offset[gr_k] = offset + fp_offset; | |
d40fcd7b | 928 | last_prologue_pc = next_pc; |
456f8b9d DB |
929 | } |
930 | ||
931 | /* Saving the scratch register holding the return address. */ | |
932 | else if (lr_save_reg != -1 | |
933 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
934 | { |
935 | lr_saved_on_stack = 1; | |
936 | if (gr_i == sp_regnum) | |
937 | lr_sp_offset = offset; | |
938 | else | |
939 | lr_sp_offset = offset + fp_offset; | |
d40fcd7b | 940 | last_prologue_pc = next_pc; |
1cb761c7 | 941 | } |
456f8b9d DB |
942 | |
943 | /* Spilling int-sized arguments to the stack. */ | |
944 | else if (is_argument_reg (gr_k)) | |
d40fcd7b | 945 | last_prologue_pc = next_pc; |
456f8b9d | 946 | } |
d40fcd7b | 947 | pc = next_pc; |
456f8b9d DB |
948 | } |
949 | ||
1cb761c7 | 950 | if (next_frame && info) |
456f8b9d | 951 | { |
1cb761c7 KB |
952 | int i; |
953 | ULONGEST this_base; | |
456f8b9d DB |
954 | |
955 | /* If we know the relationship between the stack and frame | |
956 | pointers, record the addresses of the registers we noticed. | |
957 | Note that we have to do this as a separate step at the end, | |
958 | because instructions may save relative to the SP, but we need | |
959 | their addresses relative to the FP. */ | |
960 | if (fp_set) | |
1cb761c7 KB |
961 | frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); |
962 | else | |
963 | frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); | |
456f8b9d | 964 | |
1cb761c7 KB |
965 | for (i = 0; i < 64; i++) |
966 | if (gr_saved[i]) | |
967 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
456f8b9d | 968 | |
1cb761c7 KB |
969 | info->prev_sp = this_base - fp_offset + framesize; |
970 | info->base = this_base; | |
971 | ||
972 | /* If LR was saved on the stack, record its location. */ | |
973 | if (lr_saved_on_stack) | |
974 | info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; | |
975 | ||
976 | /* The call instruction moves the caller's PC in the callee's LR. | |
977 | Since this is an unwind, do the reverse. Copy the location of LR | |
978 | into PC (the address / regnum) so that a request for PC will be | |
979 | converted into a request for the LR. */ | |
980 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
981 | ||
982 | /* Save the previous frame's computed SP value. */ | |
983 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
456f8b9d DB |
984 | } |
985 | ||
d40fcd7b | 986 | return last_prologue_pc; |
456f8b9d DB |
987 | } |
988 | ||
989 | ||
990 | static CORE_ADDR | |
991 | frv_skip_prologue (CORE_ADDR pc) | |
992 | { | |
993 | CORE_ADDR func_addr, func_end, new_pc; | |
994 | ||
995 | new_pc = pc; | |
996 | ||
997 | /* If the line table has entry for a line *within* the function | |
998 | (i.e., not in the prologue, and not past the end), then that's | |
999 | our location. */ | |
1000 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1001 | { | |
1002 | struct symtab_and_line sal; | |
1003 | ||
1004 | sal = find_pc_line (func_addr, 0); | |
1005 | ||
1006 | if (sal.line != 0 && sal.end < func_end) | |
1007 | { | |
1008 | new_pc = sal.end; | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
1013 | If we didn't find a real source location past that, then | |
1014 | do a full analysis of the prologue. */ | |
1015 | if (new_pc < pc + 20) | |
1cb761c7 | 1016 | new_pc = frv_analyze_prologue (pc, 0, 0); |
456f8b9d DB |
1017 | |
1018 | return new_pc; | |
1019 | } | |
1020 | ||
1cb761c7 KB |
1021 | |
1022 | static struct frv_unwind_cache * | |
1023 | frv_frame_unwind_cache (struct frame_info *next_frame, | |
1024 | void **this_prologue_cache) | |
456f8b9d | 1025 | { |
1cb761c7 KB |
1026 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1027 | CORE_ADDR pc; | |
1cb761c7 KB |
1028 | ULONGEST this_base; |
1029 | struct frv_unwind_cache *info; | |
8baa6f92 | 1030 | |
1cb761c7 KB |
1031 | if ((*this_prologue_cache)) |
1032 | return (*this_prologue_cache); | |
456f8b9d | 1033 | |
1cb761c7 KB |
1034 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
1035 | (*this_prologue_cache) = info; | |
1036 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
456f8b9d | 1037 | |
1cb761c7 KB |
1038 | /* Prologue analysis does the rest... */ |
1039 | frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); | |
456f8b9d | 1040 | |
1cb761c7 | 1041 | return info; |
456f8b9d DB |
1042 | } |
1043 | ||
456f8b9d | 1044 | static void |
cd31fb03 KB |
1045 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
1046 | void *valbuf) | |
456f8b9d | 1047 | { |
cd31fb03 KB |
1048 | int len = TYPE_LENGTH (type); |
1049 | ||
1050 | if (len <= 4) | |
1051 | { | |
1052 | ULONGEST gpr8_val; | |
1053 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
1054 | store_unsigned_integer (valbuf, len, gpr8_val); | |
1055 | } | |
1056 | else if (len == 8) | |
1057 | { | |
1058 | ULONGEST regval; | |
1059 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
1060 | store_unsigned_integer (valbuf, 4, regval); | |
1061 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
1062 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); | |
1063 | } | |
1064 | else | |
1065 | internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); | |
456f8b9d DB |
1066 | } |
1067 | ||
1068 | static CORE_ADDR | |
cd31fb03 | 1069 | frv_extract_struct_value_address (struct regcache *regcache) |
456f8b9d | 1070 | { |
cd31fb03 KB |
1071 | ULONGEST addr; |
1072 | regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); | |
1073 | return addr; | |
456f8b9d DB |
1074 | } |
1075 | ||
1076 | static void | |
1077 | frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1078 | { | |
1079 | write_register (struct_return_regnum, addr); | |
1080 | } | |
1081 | ||
1082 | static int | |
1083 | frv_frameless_function_invocation (struct frame_info *frame) | |
1084 | { | |
19772a2c | 1085 | return legacy_frameless_look_for_prologue (frame); |
456f8b9d DB |
1086 | } |
1087 | ||
1cb761c7 KB |
1088 | static CORE_ADDR |
1089 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 1090 | { |
1cb761c7 | 1091 | /* Require dword alignment. */ |
5b03f266 | 1092 | return align_down (sp, 8); |
456f8b9d DB |
1093 | } |
1094 | ||
c4d10515 KB |
1095 | static CORE_ADDR |
1096 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) | |
1097 | { | |
1098 | CORE_ADDR descr; | |
1099 | char valbuf[4]; | |
1100 | ||
1101 | descr = frv_fdpic_find_canonical_descriptor (entry_point); | |
1102 | ||
1103 | if (descr != 0) | |
1104 | return descr; | |
1105 | ||
1106 | /* Construct a non-canonical descriptor from space allocated on | |
1107 | the stack. */ | |
1108 | ||
1109 | descr = value_as_long (value_allocate_space_in_inferior (8)); | |
1110 | store_unsigned_integer (valbuf, 4, entry_point); | |
1111 | write_memory (descr, valbuf, 4); | |
1112 | store_unsigned_integer (valbuf, 4, | |
1113 | frv_fdpic_find_global_pointer (entry_point)); | |
1114 | write_memory (descr + 4, valbuf, 4); | |
1115 | return descr; | |
1116 | } | |
1117 | ||
1118 | static CORE_ADDR | |
1119 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1120 | struct target_ops *targ) | |
1121 | { | |
1122 | CORE_ADDR entry_point; | |
1123 | CORE_ADDR got_address; | |
1124 | ||
1125 | entry_point = get_target_memory_unsigned (targ, addr, 4); | |
1126 | got_address = get_target_memory_unsigned (targ, addr + 4, 4); | |
1127 | ||
1128 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) | |
1129 | return entry_point; | |
1130 | else | |
1131 | return addr; | |
1132 | } | |
1133 | ||
456f8b9d | 1134 | static CORE_ADDR |
1cb761c7 KB |
1135 | frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1136 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1137 | int nargs, struct value **args, CORE_ADDR sp, | |
1138 | int struct_return, CORE_ADDR struct_addr) | |
456f8b9d DB |
1139 | { |
1140 | int argreg; | |
1141 | int argnum; | |
1142 | char *val; | |
1143 | char valbuf[4]; | |
1144 | struct value *arg; | |
1145 | struct type *arg_type; | |
1146 | int len; | |
1147 | enum type_code typecode; | |
1148 | CORE_ADDR regval; | |
1149 | int stack_space; | |
1150 | int stack_offset; | |
c4d10515 | 1151 | enum frv_abi abi = frv_abi (gdbarch); |
456f8b9d DB |
1152 | |
1153 | #if 0 | |
1154 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1155 | nargs, (int) sp, struct_return, struct_addr); | |
1156 | #endif | |
1157 | ||
1158 | stack_space = 0; | |
1159 | for (argnum = 0; argnum < nargs; ++argnum) | |
5b03f266 | 1160 | stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); |
456f8b9d DB |
1161 | |
1162 | stack_space -= (6 * 4); | |
1163 | if (stack_space > 0) | |
1164 | sp -= stack_space; | |
1165 | ||
1166 | /* Make sure stack is dword aligned. */ | |
5b03f266 | 1167 | sp = align_down (sp, 8); |
456f8b9d DB |
1168 | |
1169 | stack_offset = 0; | |
1170 | ||
1171 | argreg = 8; | |
1172 | ||
1173 | if (struct_return) | |
1cb761c7 KB |
1174 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
1175 | struct_addr); | |
456f8b9d DB |
1176 | |
1177 | for (argnum = 0; argnum < nargs; ++argnum) | |
1178 | { | |
1179 | arg = args[argnum]; | |
1180 | arg_type = check_typedef (VALUE_TYPE (arg)); | |
1181 | len = TYPE_LENGTH (arg_type); | |
1182 | typecode = TYPE_CODE (arg_type); | |
1183 | ||
1184 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1185 | { | |
fbd9dcd3 | 1186 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); |
456f8b9d DB |
1187 | typecode = TYPE_CODE_PTR; |
1188 | len = 4; | |
1189 | val = valbuf; | |
1190 | } | |
c4d10515 KB |
1191 | else if (abi == FRV_ABI_FDPIC |
1192 | && len == 4 | |
1193 | && typecode == TYPE_CODE_PTR | |
1194 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
1195 | { | |
1196 | /* The FDPIC ABI requires function descriptors to be passed instead | |
1197 | of entry points. */ | |
1198 | store_unsigned_integer | |
1199 | (valbuf, 4, | |
1200 | find_func_descr (gdbarch, | |
1201 | extract_unsigned_integer (VALUE_CONTENTS (arg), | |
1202 | 4))); | |
1203 | typecode = TYPE_CODE_PTR; | |
1204 | len = 4; | |
1205 | val = valbuf; | |
1206 | } | |
456f8b9d DB |
1207 | else |
1208 | { | |
1209 | val = (char *) VALUE_CONTENTS (arg); | |
1210 | } | |
1211 | ||
1212 | while (len > 0) | |
1213 | { | |
1214 | int partial_len = (len < 4 ? len : 4); | |
1215 | ||
1216 | if (argreg < 14) | |
1217 | { | |
7c0b4a20 | 1218 | regval = extract_unsigned_integer (val, partial_len); |
456f8b9d DB |
1219 | #if 0 |
1220 | printf(" Argnum %d data %x -> reg %d\n", | |
1221 | argnum, (int) regval, argreg); | |
1222 | #endif | |
1cb761c7 | 1223 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
1224 | ++argreg; |
1225 | } | |
1226 | else | |
1227 | { | |
1228 | #if 0 | |
1229 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
1230 | argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); | |
1231 | #endif | |
1232 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 1233 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
1234 | } |
1235 | len -= partial_len; | |
1236 | val += partial_len; | |
1237 | } | |
1238 | } | |
456f8b9d | 1239 | |
1cb761c7 KB |
1240 | /* Set the return address. For the frv, the return breakpoint is |
1241 | always at BP_ADDR. */ | |
1242 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1243 | ||
c4d10515 KB |
1244 | if (abi == FRV_ABI_FDPIC) |
1245 | { | |
1246 | /* Set the GOT register for the FDPIC ABI. */ | |
1247 | regcache_cooked_write_unsigned | |
1248 | (regcache, first_gpr_regnum + 15, | |
1249 | frv_fdpic_find_global_pointer (func_addr)); | |
1250 | } | |
1251 | ||
1cb761c7 KB |
1252 | /* Finally, update the SP register. */ |
1253 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1254 | ||
456f8b9d DB |
1255 | return sp; |
1256 | } | |
1257 | ||
1258 | static void | |
cd31fb03 KB |
1259 | frv_store_return_value (struct type *type, struct regcache *regcache, |
1260 | const void *valbuf) | |
456f8b9d | 1261 | { |
cd31fb03 KB |
1262 | int len = TYPE_LENGTH (type); |
1263 | ||
1264 | if (len <= 4) | |
1265 | { | |
1266 | bfd_byte val[4]; | |
1267 | memset (val, 0, sizeof (val)); | |
1268 | memcpy (val + (4 - len), valbuf, len); | |
1269 | regcache_cooked_write (regcache, 8, val); | |
1270 | } | |
1271 | else if (len == 8) | |
1272 | { | |
1273 | regcache_cooked_write (regcache, 8, valbuf); | |
1274 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); | |
1275 | } | |
456f8b9d DB |
1276 | else |
1277 | internal_error (__FILE__, __LINE__, | |
cd31fb03 | 1278 | "Don't know how to return a %d-byte value.", len); |
456f8b9d DB |
1279 | } |
1280 | ||
456f8b9d | 1281 | |
456f8b9d DB |
1282 | /* Hardware watchpoint / breakpoint support for the FR500 |
1283 | and FR400. */ | |
1284 | ||
1285 | int | |
1286 | frv_check_watch_resources (int type, int cnt, int ot) | |
1287 | { | |
1288 | struct gdbarch_tdep *var = CURRENT_VARIANT; | |
1289 | ||
1290 | /* Watchpoints not supported on simulator. */ | |
1291 | if (strcmp (target_shortname, "sim") == 0) | |
1292 | return 0; | |
1293 | ||
1294 | if (type == bp_hardware_breakpoint) | |
1295 | { | |
1296 | if (var->num_hw_breakpoints == 0) | |
1297 | return 0; | |
1298 | else if (cnt <= var->num_hw_breakpoints) | |
1299 | return 1; | |
1300 | } | |
1301 | else | |
1302 | { | |
1303 | if (var->num_hw_watchpoints == 0) | |
1304 | return 0; | |
1305 | else if (ot) | |
1306 | return -1; | |
1307 | else if (cnt <= var->num_hw_watchpoints) | |
1308 | return 1; | |
1309 | } | |
1310 | return -1; | |
1311 | } | |
1312 | ||
1313 | ||
1314 | CORE_ADDR | |
5ae5f592 | 1315 | frv_stopped_data_address (void) |
456f8b9d DB |
1316 | { |
1317 | CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; | |
1318 | ||
1319 | brr = read_register (brr_regnum); | |
1320 | dbar0 = read_register (dbar0_regnum); | |
1321 | dbar1 = read_register (dbar1_regnum); | |
1322 | dbar2 = read_register (dbar2_regnum); | |
1323 | dbar3 = read_register (dbar3_regnum); | |
1324 | ||
1325 | if (brr & (1<<11)) | |
1326 | return dbar0; | |
1327 | else if (brr & (1<<10)) | |
1328 | return dbar1; | |
1329 | else if (brr & (1<<9)) | |
1330 | return dbar2; | |
1331 | else if (brr & (1<<8)) | |
1332 | return dbar3; | |
1333 | else | |
1334 | return 0; | |
1335 | } | |
1336 | ||
1cb761c7 KB |
1337 | static CORE_ADDR |
1338 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1339 | { | |
1340 | return frame_unwind_register_unsigned (next_frame, pc_regnum); | |
1341 | } | |
1342 | ||
1343 | /* Given a GDB frame, determine the address of the calling function's | |
1344 | frame. This will be used to create a new GDB frame struct. */ | |
1345 | ||
1346 | static void | |
1347 | frv_frame_this_id (struct frame_info *next_frame, | |
1348 | void **this_prologue_cache, struct frame_id *this_id) | |
1349 | { | |
1350 | struct frv_unwind_cache *info | |
1351 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1352 | CORE_ADDR base; | |
1353 | CORE_ADDR func; | |
1354 | struct minimal_symbol *msym_stack; | |
1355 | struct frame_id id; | |
1356 | ||
1357 | /* The FUNC is easy. */ | |
1358 | func = frame_func_unwind (next_frame); | |
1359 | ||
1cb761c7 KB |
1360 | /* Check if the stack is empty. */ |
1361 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1362 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
1363 | return; | |
1364 | ||
1365 | /* Hopefully the prologue analysis either correctly determined the | |
1366 | frame's base (which is the SP from the previous frame), or set | |
1367 | that base to "NULL". */ | |
1368 | base = info->prev_sp; | |
1369 | if (base == 0) | |
1370 | return; | |
1371 | ||
1372 | id = frame_id_build (base, func); | |
1373 | ||
1374 | /* Check that we're not going round in circles with the same frame | |
1375 | ID (but avoid applying the test to sentinel frames which do go | |
1376 | round in circles). Can't use frame_id_eq() as that doesn't yet | |
1377 | compare the frame's PC value. */ | |
1378 | if (frame_relative_level (next_frame) >= 0 | |
1379 | && get_frame_type (next_frame) != DUMMY_FRAME | |
1380 | && frame_id_eq (get_frame_id (next_frame), id)) | |
1381 | return; | |
1382 | ||
1383 | (*this_id) = id; | |
1384 | } | |
1385 | ||
1386 | static void | |
1387 | frv_frame_prev_register (struct frame_info *next_frame, | |
1388 | void **this_prologue_cache, | |
1389 | int regnum, int *optimizedp, | |
1390 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1391 | int *realnump, void *bufferp) | |
1392 | { | |
1393 | struct frv_unwind_cache *info | |
1394 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1395 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1396 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1397 | } | |
1398 | ||
1399 | static const struct frame_unwind frv_frame_unwind = { | |
1400 | NORMAL_FRAME, | |
1401 | frv_frame_this_id, | |
1402 | frv_frame_prev_register | |
1403 | }; | |
1404 | ||
1405 | static const struct frame_unwind * | |
1406 | frv_frame_sniffer (struct frame_info *next_frame) | |
1407 | { | |
1408 | return &frv_frame_unwind; | |
1409 | } | |
1410 | ||
1411 | static CORE_ADDR | |
1412 | frv_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1413 | { | |
1414 | struct frv_unwind_cache *info | |
1415 | = frv_frame_unwind_cache (next_frame, this_cache); | |
1416 | return info->base; | |
1417 | } | |
1418 | ||
1419 | static const struct frame_base frv_frame_base = { | |
1420 | &frv_frame_unwind, | |
1421 | frv_frame_base_address, | |
1422 | frv_frame_base_address, | |
1423 | frv_frame_base_address | |
1424 | }; | |
1425 | ||
1426 | static CORE_ADDR | |
1427 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1428 | { | |
1429 | return frame_unwind_register_unsigned (next_frame, sp_regnum); | |
1430 | } | |
1431 | ||
1432 | ||
1433 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1434 | dummy frame. The frame ID's base needs to match the TOS value | |
1435 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1436 | breakpoint. */ | |
1437 | ||
1438 | static struct frame_id | |
1439 | frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1440 | { | |
1441 | return frame_id_build (frv_unwind_sp (gdbarch, next_frame), | |
1442 | frame_pc_unwind (next_frame)); | |
1443 | } | |
1444 | ||
5ecb7103 KB |
1445 | /* Signal trampolines. */ |
1446 | ||
1447 | static struct frv_unwind_cache * | |
1448 | frv_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1449 | { | |
1450 | struct frv_unwind_cache *cache; | |
1451 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1452 | CORE_ADDR addr; | |
1453 | char buf[4]; | |
1454 | int regno; | |
1455 | CORE_ADDR sc_addr_cache_val = 0; | |
1456 | ||
1457 | if (*this_cache) | |
1458 | return *this_cache; | |
1459 | ||
1460 | cache = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); | |
1461 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
1462 | ||
1463 | frame_unwind_register (next_frame, sp_regnum, buf); | |
1464 | cache->base = extract_unsigned_integer (buf, sizeof buf); | |
1465 | ||
1466 | for (regno = 0; regno < frv_num_regs; regno++) | |
1467 | { | |
1468 | cache->saved_regs[regno].addr | |
1469 | = tdep->sigcontext_reg_addr (next_frame, regno, &sc_addr_cache_val); | |
1470 | } | |
1471 | ||
1472 | ||
1473 | if (cache->saved_regs[sp_regnum].addr != -1 | |
1474 | && target_read_memory (cache->saved_regs[sp_regnum].addr, | |
1475 | buf, sizeof buf) == 0) | |
1476 | { | |
1477 | cache->prev_sp = extract_unsigned_integer (buf, sizeof buf); | |
1478 | ||
1479 | /* Now that we've bothered to read it out of memory, save the | |
1480 | prev frame's SP value in the cache. */ | |
1481 | trad_frame_set_value (cache->saved_regs, sp_regnum, cache->prev_sp); | |
1482 | } | |
1483 | else | |
1484 | { | |
1485 | warning ("Can't read SP value from sigtramp frame"); | |
1486 | } | |
1487 | ||
1488 | *this_cache = cache; | |
1489 | return cache; | |
1490 | } | |
1491 | ||
1492 | static void | |
1493 | frv_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1494 | struct frame_id *this_id) | |
1495 | { | |
1496 | struct frv_unwind_cache *cache = | |
1497 | frv_sigtramp_frame_cache (next_frame, this_cache); | |
1498 | ||
1499 | (*this_id) = frame_id_build (cache->base, frame_pc_unwind (next_frame)); | |
1500 | } | |
1501 | ||
1502 | static void | |
1503 | frv_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
1504 | void **this_cache, | |
1505 | int regnum, int *optimizedp, | |
1506 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1507 | int *realnump, void *valuep) | |
1508 | { | |
1509 | /* Make sure we've initialized the cache. */ | |
1510 | frv_sigtramp_frame_cache (next_frame, this_cache); | |
1511 | ||
1512 | frv_frame_prev_register (next_frame, this_cache, regnum, | |
1513 | optimizedp, lvalp, addrp, realnump, valuep); | |
1514 | } | |
1515 | ||
1516 | static const struct frame_unwind frv_sigtramp_frame_unwind = | |
1517 | { | |
1518 | SIGTRAMP_FRAME, | |
1519 | frv_sigtramp_frame_this_id, | |
1520 | frv_sigtramp_frame_prev_register | |
1521 | }; | |
1522 | ||
1523 | static const struct frame_unwind * | |
1524 | frv_sigtramp_frame_sniffer (struct frame_info *next_frame) | |
1525 | { | |
1526 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1527 | char *name; | |
1528 | ||
1529 | /* We shouldn't even bother to try if the OSABI didn't register | |
1530 | a sigcontext_reg_addr handler. */ | |
1531 | if (!gdbarch_tdep (current_gdbarch)->sigcontext_reg_addr) | |
1532 | return NULL; | |
1533 | ||
1534 | find_pc_partial_function (pc, &name, NULL, NULL); | |
f561f026 | 1535 | if (DEPRECATED_PC_IN_SIGTRAMP (pc, name)) |
5ecb7103 KB |
1536 | return &frv_sigtramp_frame_unwind; |
1537 | ||
1538 | return NULL; | |
1539 | } | |
1cb761c7 | 1540 | |
456f8b9d DB |
1541 | static struct gdbarch * |
1542 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1543 | { | |
1544 | struct gdbarch *gdbarch; | |
1545 | struct gdbarch_tdep *var; | |
7e295833 | 1546 | int elf_flags = 0; |
456f8b9d DB |
1547 | |
1548 | /* Check to see if we've already built an appropriate architecture | |
1549 | object for this executable. */ | |
1550 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1551 | if (arches) | |
1552 | return arches->gdbarch; | |
1553 | ||
1554 | /* Select the right tdep structure for this variant. */ | |
1555 | var = new_variant (); | |
1556 | switch (info.bfd_arch_info->mach) | |
1557 | { | |
1558 | case bfd_mach_frv: | |
1559 | case bfd_mach_frvsimple: | |
1560 | case bfd_mach_fr500: | |
1561 | case bfd_mach_frvtomcat: | |
251a3ae3 | 1562 | case bfd_mach_fr550: |
456f8b9d DB |
1563 | set_variant_num_gprs (var, 64); |
1564 | set_variant_num_fprs (var, 64); | |
1565 | break; | |
1566 | ||
1567 | case bfd_mach_fr400: | |
b2d6d697 | 1568 | case bfd_mach_fr450: |
456f8b9d DB |
1569 | set_variant_num_gprs (var, 32); |
1570 | set_variant_num_fprs (var, 32); | |
1571 | break; | |
1572 | ||
1573 | default: | |
1574 | /* Never heard of this variant. */ | |
1575 | return 0; | |
1576 | } | |
7e295833 KB |
1577 | |
1578 | /* Extract the ELF flags, if available. */ | |
1579 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1580 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1581 | ||
1582 | if (elf_flags & EF_FRV_FDPIC) | |
1583 | set_variant_abi_fdpic (var); | |
1584 | ||
b2d6d697 KB |
1585 | if (elf_flags & EF_FRV_CPU_FR450) |
1586 | set_variant_scratch_registers (var); | |
1587 | ||
456f8b9d DB |
1588 | gdbarch = gdbarch_alloc (&info, var); |
1589 | ||
1590 | set_gdbarch_short_bit (gdbarch, 16); | |
1591 | set_gdbarch_int_bit (gdbarch, 32); | |
1592 | set_gdbarch_long_bit (gdbarch, 32); | |
1593 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1594 | set_gdbarch_float_bit (gdbarch, 32); | |
1595 | set_gdbarch_double_bit (gdbarch, 64); | |
1596 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1597 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1598 | ||
1599 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
6a748db6 KB |
1600 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
1601 | ||
456f8b9d | 1602 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
0ba6dca9 | 1603 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1604 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1605 | ||
1606 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1607 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1608 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d | 1609 | |
6a748db6 KB |
1610 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
1611 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); | |
1612 | ||
456f8b9d DB |
1613 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
1614 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); | |
46a16dba | 1615 | set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); |
456f8b9d | 1616 | |
19772a2c | 1617 | set_gdbarch_deprecated_frameless_function_invocation (gdbarch, frv_frameless_function_invocation); |
456f8b9d | 1618 | |
1fd35568 | 1619 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
cd31fb03 | 1620 | set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); |
456f8b9d | 1621 | |
4183d812 | 1622 | set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); |
cd31fb03 | 1623 | set_gdbarch_store_return_value (gdbarch, frv_store_return_value); |
74055713 | 1624 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); |
456f8b9d | 1625 | |
1cb761c7 KB |
1626 | /* Frame stuff. */ |
1627 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); | |
1628 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); | |
1629 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1cb761c7 | 1630 | frame_base_set_default (gdbarch, &frv_frame_base); |
5ecb7103 KB |
1631 | /* We set the sniffer lower down after the OSABI hooks have been |
1632 | established. */ | |
456f8b9d | 1633 | |
1cb761c7 KB |
1634 | /* Settings for calling functions in the inferior. */ |
1635 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1636 | set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); | |
456f8b9d DB |
1637 | |
1638 | /* Settings that should be unnecessary. */ | |
1639 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1640 | ||
456f8b9d | 1641 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
456f8b9d | 1642 | |
456f8b9d | 1643 | set_gdbarch_remote_translate_xfer_address |
aed7f26a | 1644 | (gdbarch, generic_remote_translate_xfer_address); |
456f8b9d DB |
1645 | |
1646 | /* Hardware watchpoint / breakpoint support. */ | |
1647 | switch (info.bfd_arch_info->mach) | |
1648 | { | |
1649 | case bfd_mach_frv: | |
1650 | case bfd_mach_frvsimple: | |
1651 | case bfd_mach_fr500: | |
1652 | case bfd_mach_frvtomcat: | |
1653 | /* fr500-style hardware debugging support. */ | |
1654 | var->num_hw_watchpoints = 4; | |
1655 | var->num_hw_breakpoints = 4; | |
1656 | break; | |
1657 | ||
1658 | case bfd_mach_fr400: | |
b2d6d697 | 1659 | case bfd_mach_fr450: |
456f8b9d DB |
1660 | /* fr400-style hardware debugging support. */ |
1661 | var->num_hw_watchpoints = 2; | |
1662 | var->num_hw_breakpoints = 4; | |
1663 | break; | |
1664 | ||
1665 | default: | |
1666 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1667 | var->num_hw_watchpoints = 0; | |
1668 | var->num_hw_breakpoints = 0; | |
1669 | break; | |
1670 | } | |
1671 | ||
36482093 | 1672 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
c4d10515 KB |
1673 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) |
1674 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, | |
1675 | frv_convert_from_func_ptr_addr); | |
36482093 | 1676 | |
5ecb7103 KB |
1677 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1678 | gdbarch_init_osabi (info, gdbarch); | |
1679 | ||
1680 | /* Set the sigtramp frame sniffer. */ | |
1681 | frame_unwind_append_sniffer (gdbarch, frv_sigtramp_frame_sniffer); | |
1682 | ||
1683 | /* Set the fallback (prologue based) frame sniffer. */ | |
1684 | frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); | |
1685 | ||
456f8b9d DB |
1686 | return gdbarch; |
1687 | } | |
1688 | ||
1689 | void | |
1690 | _initialize_frv_tdep (void) | |
1691 | { | |
1692 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
456f8b9d | 1693 | } |