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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
9ab9195f | 2 | Copyright 2002, 2003, 2004 Free Software Foundation, Inc. |
456f8b9d DB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #include "defs.h" | |
8baa6f92 | 22 | #include "gdb_string.h" |
456f8b9d | 23 | #include "inferior.h" |
456f8b9d DB |
24 | #include "gdbcore.h" |
25 | #include "arch-utils.h" | |
26 | #include "regcache.h" | |
8baa6f92 | 27 | #include "frame.h" |
1cb761c7 KB |
28 | #include "frame-unwind.h" |
29 | #include "frame-base.h" | |
8baa6f92 | 30 | #include "trad-frame.h" |
dcc6aaff | 31 | #include "dis-asm.h" |
526eef89 KB |
32 | #include "gdb_assert.h" |
33 | #include "sim-regno.h" | |
34 | #include "gdb/sim-frv.h" | |
35 | #include "opcodes/frv-desc.h" /* for the H_SPR_... enums */ | |
634aa483 | 36 | #include "symtab.h" |
7e295833 KB |
37 | #include "elf-bfd.h" |
38 | #include "elf/frv.h" | |
39 | #include "osabi.h" | |
40 | #include "frv-tdep.h" | |
456f8b9d DB |
41 | |
42 | extern void _initialize_frv_tdep (void); | |
43 | ||
44 | static gdbarch_init_ftype frv_gdbarch_init; | |
45 | ||
46 | static gdbarch_register_name_ftype frv_register_name; | |
456f8b9d | 47 | static gdbarch_breakpoint_from_pc_ftype frv_breakpoint_from_pc; |
46a16dba | 48 | static gdbarch_adjust_breakpoint_address_ftype frv_gdbarch_adjust_breakpoint_address; |
456f8b9d | 49 | static gdbarch_skip_prologue_ftype frv_skip_prologue; |
456f8b9d | 50 | |
456f8b9d | 51 | |
1cb761c7 | 52 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 53 | { |
1cb761c7 KB |
54 | /* The previous frame's inner-most stack address. Used as this |
55 | frame ID's stack_addr. */ | |
56 | CORE_ADDR prev_sp; | |
456f8b9d | 57 | |
1cb761c7 KB |
58 | /* The frame's base, optionally used by the high-level debug info. */ |
59 | CORE_ADDR base; | |
8baa6f92 KB |
60 | |
61 | /* Table indicating the location of each and every register. */ | |
62 | struct trad_frame_saved_reg *saved_regs; | |
456f8b9d DB |
63 | }; |
64 | ||
456f8b9d DB |
65 | /* A structure describing a particular variant of the FRV. |
66 | We allocate and initialize one of these structures when we create | |
67 | the gdbarch object for a variant. | |
68 | ||
69 | At the moment, all the FR variants we support differ only in which | |
70 | registers are present; the portable code of GDB knows that | |
71 | registers whose names are the empty string don't exist, so the | |
72 | `register_names' array captures all the per-variant information we | |
73 | need. | |
74 | ||
75 | in the future, if we need to have per-variant maps for raw size, | |
76 | virtual type, etc., we should replace register_names with an array | |
77 | of structures, each of which gives all the necessary info for one | |
78 | register. Don't stick parallel arrays in here --- that's so | |
79 | Fortran. */ | |
80 | struct gdbarch_tdep | |
81 | { | |
7e295833 KB |
82 | /* Which ABI is in use? */ |
83 | enum frv_abi frv_abi; | |
84 | ||
456f8b9d DB |
85 | /* How many general-purpose registers does this variant have? */ |
86 | int num_gprs; | |
87 | ||
88 | /* How many floating-point registers does this variant have? */ | |
89 | int num_fprs; | |
90 | ||
91 | /* How many hardware watchpoints can it support? */ | |
92 | int num_hw_watchpoints; | |
93 | ||
94 | /* How many hardware breakpoints can it support? */ | |
95 | int num_hw_breakpoints; | |
96 | ||
97 | /* Register names. */ | |
98 | char **register_names; | |
99 | }; | |
100 | ||
101 | #define CURRENT_VARIANT (gdbarch_tdep (current_gdbarch)) | |
102 | ||
7e295833 KB |
103 | /* Return the FR-V ABI associated with GDBARCH. */ |
104 | enum frv_abi | |
105 | frv_abi (struct gdbarch *gdbarch) | |
106 | { | |
107 | return gdbarch_tdep (gdbarch)->frv_abi; | |
108 | } | |
109 | ||
110 | /* Fetch the interpreter and executable loadmap addresses (for shared | |
111 | library support) for the FDPIC ABI. Return 0 if successful, -1 if | |
112 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ | |
113 | int | |
114 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, | |
115 | CORE_ADDR *exec_addr) | |
116 | { | |
117 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) | |
118 | return -1; | |
119 | else | |
120 | { | |
121 | if (interp_addr != NULL) | |
122 | { | |
123 | ULONGEST val; | |
124 | regcache_cooked_read_unsigned (current_regcache, | |
125 | fdpic_loadmap_interp_regnum, &val); | |
126 | *interp_addr = val; | |
127 | } | |
128 | if (exec_addr != NULL) | |
129 | { | |
130 | ULONGEST val; | |
131 | regcache_cooked_read_unsigned (current_regcache, | |
132 | fdpic_loadmap_exec_regnum, &val); | |
133 | *exec_addr = val; | |
134 | } | |
135 | return 0; | |
136 | } | |
137 | } | |
456f8b9d DB |
138 | |
139 | /* Allocate a new variant structure, and set up default values for all | |
140 | the fields. */ | |
141 | static struct gdbarch_tdep * | |
5ae5f592 | 142 | new_variant (void) |
456f8b9d DB |
143 | { |
144 | struct gdbarch_tdep *var; | |
145 | int r; | |
146 | char buf[20]; | |
147 | ||
148 | var = xmalloc (sizeof (*var)); | |
149 | memset (var, 0, sizeof (*var)); | |
150 | ||
7e295833 | 151 | var->frv_abi = FRV_ABI_EABI; |
456f8b9d DB |
152 | var->num_gprs = 64; |
153 | var->num_fprs = 64; | |
154 | var->num_hw_watchpoints = 0; | |
155 | var->num_hw_breakpoints = 0; | |
156 | ||
157 | /* By default, don't supply any general-purpose or floating-point | |
158 | register names. */ | |
6a748db6 KB |
159 | var->register_names |
160 | = (char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) | |
161 | * sizeof (char *)); | |
162 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) | |
456f8b9d DB |
163 | var->register_names[r] = ""; |
164 | ||
526eef89 | 165 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 166 | registers. */ |
456f8b9d DB |
167 | |
168 | var->register_names[pc_regnum] = "pc"; | |
169 | var->register_names[lr_regnum] = "lr"; | |
170 | var->register_names[lcr_regnum] = "lcr"; | |
171 | ||
172 | var->register_names[psr_regnum] = "psr"; | |
173 | var->register_names[ccr_regnum] = "ccr"; | |
174 | var->register_names[cccr_regnum] = "cccr"; | |
175 | var->register_names[tbr_regnum] = "tbr"; | |
176 | ||
177 | /* Debug registers. */ | |
178 | var->register_names[brr_regnum] = "brr"; | |
179 | var->register_names[dbar0_regnum] = "dbar0"; | |
180 | var->register_names[dbar1_regnum] = "dbar1"; | |
181 | var->register_names[dbar2_regnum] = "dbar2"; | |
182 | var->register_names[dbar3_regnum] = "dbar3"; | |
183 | ||
526eef89 KB |
184 | /* iacc0 (Only found on MB93405.) */ |
185 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
186 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
6a748db6 | 187 | var->register_names[iacc0_regnum] = "iacc0"; |
526eef89 | 188 | |
8b67aa36 KB |
189 | /* fsr0 (Found on FR555 and FR501.) */ |
190 | var->register_names[fsr0_regnum] = "fsr0"; | |
191 | ||
192 | /* acc0 - acc7. The architecture provides for the possibility of many | |
193 | more (up to 64 total), but we don't want to make that big of a hole | |
194 | in the G packet. If we need more in the future, we'll add them | |
195 | elsewhere. */ | |
196 | for (r = acc0_regnum; r <= acc7_regnum; r++) | |
197 | { | |
198 | char *buf; | |
199 | xasprintf (&buf, "acc%d", r - acc0_regnum); | |
200 | var->register_names[r] = buf; | |
201 | } | |
202 | ||
203 | /* accg0 - accg7: These are one byte registers. The remote protocol | |
204 | provides the raw values packed four into a slot. accg0123 and | |
205 | accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. | |
206 | We don't provide names for accg0123 and accg4567 since the user will | |
207 | likely not want to see these raw values. */ | |
208 | ||
209 | for (r = accg0_regnum; r <= accg7_regnum; r++) | |
210 | { | |
211 | char *buf; | |
212 | xasprintf (&buf, "accg%d", r - accg0_regnum); | |
213 | var->register_names[r] = buf; | |
214 | } | |
215 | ||
216 | /* msr0 and msr1. */ | |
217 | ||
218 | var->register_names[msr0_regnum] = "msr0"; | |
219 | var->register_names[msr1_regnum] = "msr1"; | |
220 | ||
221 | /* gner and fner registers. */ | |
222 | var->register_names[gner0_regnum] = "gner0"; | |
223 | var->register_names[gner1_regnum] = "gner1"; | |
224 | var->register_names[fner0_regnum] = "fner0"; | |
225 | var->register_names[fner1_regnum] = "fner1"; | |
226 | ||
456f8b9d DB |
227 | return var; |
228 | } | |
229 | ||
230 | ||
231 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
232 | registers, and fill in the names array appropriately. */ | |
233 | static void | |
234 | set_variant_num_gprs (struct gdbarch_tdep *var, int num_gprs) | |
235 | { | |
236 | int r; | |
237 | ||
238 | var->num_gprs = num_gprs; | |
239 | ||
240 | for (r = 0; r < num_gprs; ++r) | |
241 | { | |
242 | char buf[20]; | |
243 | ||
244 | sprintf (buf, "gr%d", r); | |
245 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); | |
246 | } | |
247 | } | |
248 | ||
249 | ||
250 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
251 | registers, and fill in the names array appropriately. */ | |
252 | static void | |
253 | set_variant_num_fprs (struct gdbarch_tdep *var, int num_fprs) | |
254 | { | |
255 | int r; | |
256 | ||
257 | var->num_fprs = num_fprs; | |
258 | ||
259 | for (r = 0; r < num_fprs; ++r) | |
260 | { | |
261 | char buf[20]; | |
262 | ||
263 | sprintf (buf, "fr%d", r); | |
264 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); | |
265 | } | |
266 | } | |
267 | ||
7e295833 KB |
268 | static void |
269 | set_variant_abi_fdpic (struct gdbarch_tdep *var) | |
270 | { | |
271 | var->frv_abi = FRV_ABI_FDPIC; | |
272 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); | |
273 | var->register_names[fdpic_loadmap_interp_regnum] = xstrdup ("loadmap_interp"); | |
274 | } | |
456f8b9d | 275 | |
b2d6d697 KB |
276 | static void |
277 | set_variant_scratch_registers (struct gdbarch_tdep *var) | |
278 | { | |
279 | var->register_names[scr0_regnum] = xstrdup ("scr0"); | |
280 | var->register_names[scr1_regnum] = xstrdup ("scr1"); | |
281 | var->register_names[scr2_regnum] = xstrdup ("scr2"); | |
282 | var->register_names[scr3_regnum] = xstrdup ("scr3"); | |
283 | } | |
284 | ||
456f8b9d DB |
285 | static const char * |
286 | frv_register_name (int reg) | |
287 | { | |
288 | if (reg < 0) | |
289 | return "?toosmall?"; | |
6a748db6 | 290 | if (reg >= frv_num_regs + frv_num_pseudo_regs) |
456f8b9d DB |
291 | return "?toolarge?"; |
292 | ||
293 | return CURRENT_VARIANT->register_names[reg]; | |
294 | } | |
295 | ||
526eef89 | 296 | |
456f8b9d | 297 | static struct type * |
7f398216 | 298 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 299 | { |
526eef89 | 300 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
456f8b9d | 301 | return builtin_type_float; |
6a748db6 KB |
302 | else if (reg == iacc0_regnum) |
303 | return builtin_type_int64; | |
456f8b9d | 304 | else |
526eef89 | 305 | return builtin_type_int32; |
456f8b9d DB |
306 | } |
307 | ||
6a748db6 KB |
308 | static void |
309 | frv_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
310 | int reg, void *buffer) | |
311 | { | |
312 | if (reg == iacc0_regnum) | |
313 | { | |
314 | regcache_raw_read (regcache, iacc0h_regnum, buffer); | |
315 | regcache_raw_read (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
316 | } | |
8b67aa36 KB |
317 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
318 | { | |
319 | /* The accg raw registers have four values in each slot with the | |
320 | lowest register number occupying the first byte. */ | |
321 | ||
322 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
323 | int byte_num = (reg - accg0_regnum) % 4; | |
324 | bfd_byte buf[4]; | |
325 | ||
326 | regcache_raw_read (regcache, raw_regnum, buf); | |
327 | memset (buffer, 0, 4); | |
328 | /* FR-V is big endian, so put the requested byte in the first byte | |
329 | of the buffer allocated to hold the pseudo-register. */ | |
330 | ((bfd_byte *) buffer)[0] = buf[byte_num]; | |
331 | } | |
6a748db6 KB |
332 | } |
333 | ||
334 | static void | |
335 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
336 | int reg, const void *buffer) | |
337 | { | |
338 | if (reg == iacc0_regnum) | |
339 | { | |
340 | regcache_raw_write (regcache, iacc0h_regnum, buffer); | |
341 | regcache_raw_write (regcache, iacc0l_regnum, (bfd_byte *) buffer + 4); | |
342 | } | |
8b67aa36 KB |
343 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
344 | { | |
345 | /* The accg raw registers have four values in each slot with the | |
346 | lowest register number occupying the first byte. */ | |
347 | ||
348 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
349 | int byte_num = (reg - accg0_regnum) % 4; | |
350 | char buf[4]; | |
351 | ||
352 | regcache_raw_read (regcache, raw_regnum, buf); | |
353 | buf[byte_num] = ((bfd_byte *) buffer)[0]; | |
354 | regcache_raw_write (regcache, raw_regnum, buf); | |
355 | } | |
6a748db6 KB |
356 | } |
357 | ||
526eef89 KB |
358 | static int |
359 | frv_register_sim_regno (int reg) | |
360 | { | |
361 | static const int spr_map[] = | |
362 | { | |
363 | H_SPR_PSR, /* psr_regnum */ | |
364 | H_SPR_CCR, /* ccr_regnum */ | |
365 | H_SPR_CCCR, /* cccr_regnum */ | |
8b67aa36 KB |
366 | -1, /* fdpic_loadmap_exec_regnum */ |
367 | -1, /* fdpic_loadmap_interp_regnum */ | |
526eef89 KB |
368 | -1, /* 134 */ |
369 | H_SPR_TBR, /* tbr_regnum */ | |
370 | H_SPR_BRR, /* brr_regnum */ | |
371 | H_SPR_DBAR0, /* dbar0_regnum */ | |
372 | H_SPR_DBAR1, /* dbar1_regnum */ | |
373 | H_SPR_DBAR2, /* dbar2_regnum */ | |
374 | H_SPR_DBAR3, /* dbar3_regnum */ | |
8b67aa36 KB |
375 | H_SPR_SCR0, /* scr0_regnum */ |
376 | H_SPR_SCR1, /* scr1_regnum */ | |
377 | H_SPR_SCR2, /* scr2_regnum */ | |
378 | H_SPR_SCR3, /* scr3_regnum */ | |
526eef89 KB |
379 | H_SPR_LR, /* lr_regnum */ |
380 | H_SPR_LCR, /* lcr_regnum */ | |
381 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
8b67aa36 KB |
382 | H_SPR_IACC0L, /* iacc0l_regnum */ |
383 | H_SPR_FSR0, /* fsr0_regnum */ | |
384 | /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ | |
385 | -1, /* acc0_regnum */ | |
386 | -1, /* acc1_regnum */ | |
387 | -1, /* acc2_regnum */ | |
388 | -1, /* acc3_regnum */ | |
389 | -1, /* acc4_regnum */ | |
390 | -1, /* acc5_regnum */ | |
391 | -1, /* acc6_regnum */ | |
392 | -1, /* acc7_regnum */ | |
393 | -1, /* acc0123_regnum */ | |
394 | -1, /* acc4567_regnum */ | |
395 | H_SPR_MSR0, /* msr0_regnum */ | |
396 | H_SPR_MSR1, /* msr1_regnum */ | |
397 | H_SPR_GNER0, /* gner0_regnum */ | |
398 | H_SPR_GNER1, /* gner1_regnum */ | |
399 | H_SPR_FNER0, /* fner0_regnum */ | |
400 | H_SPR_FNER1, /* fner1_regnum */ | |
526eef89 KB |
401 | }; |
402 | ||
403 | gdb_assert (reg >= 0 && reg < NUM_REGS); | |
404 | ||
405 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
406 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
407 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
408 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
409 | else if (pc_regnum == reg) | |
410 | return SIM_FRV_PC_REGNUM; | |
411 | else if (reg >= first_spr_regnum | |
412 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) | |
413 | { | |
414 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
415 | ||
416 | if (spr_reg_offset < 0) | |
417 | return SIM_REGNO_DOES_NOT_EXIST; | |
418 | else | |
419 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
420 | } | |
421 | ||
422 | internal_error (__FILE__, __LINE__, "Bad register number %d", reg); | |
423 | } | |
424 | ||
456f8b9d DB |
425 | static const unsigned char * |
426 | frv_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenp) | |
427 | { | |
428 | static unsigned char breakpoint[] = {0xc0, 0x70, 0x00, 0x01}; | |
429 | *lenp = sizeof (breakpoint); | |
430 | return breakpoint; | |
431 | } | |
432 | ||
46a16dba KB |
433 | /* Define the maximum number of instructions which may be packed into a |
434 | bundle (VLIW instruction). */ | |
435 | static const int max_instrs_per_bundle = 8; | |
436 | ||
437 | /* Define the size (in bytes) of an FR-V instruction. */ | |
438 | static const int frv_instr_size = 4; | |
439 | ||
440 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
441 | constraint that a break instruction must not appear as any but the | |
442 | first instruction in the bundle. */ | |
443 | static CORE_ADDR | |
444 | frv_gdbarch_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
445 | { | |
446 | int count = max_instrs_per_bundle; | |
447 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
448 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
449 | ||
450 | /* Find the end of the previous packing sequence. This will be indicated | |
451 | by either attempting to access some inaccessible memory or by finding | |
452 | an instruction word whose packing bit is set to one. */ | |
453 | while (count-- > 0 && addr >= func_start) | |
454 | { | |
455 | char instr[frv_instr_size]; | |
456 | int status; | |
457 | ||
458 | status = read_memory_nobpt (addr, instr, sizeof instr); | |
459 | ||
460 | if (status != 0) | |
461 | break; | |
462 | ||
463 | /* This is a big endian architecture, so byte zero will have most | |
464 | significant byte. The most significant bit of this byte is the | |
465 | packing bit. */ | |
466 | if (instr[0] & 0x80) | |
467 | break; | |
468 | ||
469 | addr -= frv_instr_size; | |
470 | } | |
471 | ||
472 | if (count > 0) | |
473 | bpaddr = addr + frv_instr_size; | |
474 | ||
475 | return bpaddr; | |
476 | } | |
477 | ||
456f8b9d DB |
478 | |
479 | /* Return true if REG is a caller-saves ("scratch") register, | |
480 | false otherwise. */ | |
481 | static int | |
482 | is_caller_saves_reg (int reg) | |
483 | { | |
484 | return ((4 <= reg && reg <= 7) | |
485 | || (14 <= reg && reg <= 15) | |
486 | || (32 <= reg && reg <= 47)); | |
487 | } | |
488 | ||
489 | ||
490 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
491 | static int | |
492 | is_callee_saves_reg (int reg) | |
493 | { | |
494 | return ((16 <= reg && reg <= 31) | |
495 | || (48 <= reg && reg <= 63)); | |
496 | } | |
497 | ||
498 | ||
499 | /* Return true if REG is an argument register, false otherwise. */ | |
500 | static int | |
501 | is_argument_reg (int reg) | |
502 | { | |
503 | return (8 <= reg && reg <= 13); | |
504 | } | |
505 | ||
456f8b9d DB |
506 | /* Scan an FR-V prologue, starting at PC, until frame->PC. |
507 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
508 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
509 | Return the first PC value after the prologue. | |
510 | ||
511 | Note that, for unoptimized code, we almost don't need this function | |
512 | at all; all arguments and locals live on the stack, so we just need | |
513 | the FP to find everything. The catch: structures passed by value | |
514 | have their addresses living in registers; they're never spilled to | |
515 | the stack. So if you ever want to be able to get to these | |
516 | arguments in any frame but the top, you'll need to do this serious | |
517 | prologue analysis. */ | |
518 | static CORE_ADDR | |
1cb761c7 KB |
519 | frv_analyze_prologue (CORE_ADDR pc, struct frame_info *next_frame, |
520 | struct frv_unwind_cache *info) | |
456f8b9d DB |
521 | { |
522 | /* When writing out instruction bitpatterns, we use the following | |
523 | letters to label instruction fields: | |
524 | P - The parallel bit. We don't use this. | |
525 | J - The register number of GRj in the instruction description. | |
526 | K - The register number of GRk in the instruction description. | |
527 | I - The register number of GRi. | |
528 | S - a signed imediate offset. | |
529 | U - an unsigned immediate offset. | |
530 | ||
531 | The dots below the numbers indicate where hex digit boundaries | |
532 | fall, to make it easier to check the numbers. */ | |
533 | ||
534 | /* Non-zero iff we've seen the instruction that initializes the | |
535 | frame pointer for this function's frame. */ | |
536 | int fp_set = 0; | |
537 | ||
538 | /* If fp_set is non_zero, then this is the distance from | |
539 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
540 | int fp_offset = 0; | |
541 | ||
542 | /* Total size of frame prior to any alloca operations. */ | |
543 | int framesize = 0; | |
544 | ||
1cb761c7 KB |
545 | /* Flag indicating if lr has been saved on the stack. */ |
546 | int lr_saved_on_stack = 0; | |
547 | ||
456f8b9d DB |
548 | /* The number of the general-purpose register we saved the return |
549 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
550 | int lr_save_reg = -1; | |
551 | ||
1cb761c7 KB |
552 | /* Offset (from sp) at which lr has been saved on the stack. */ |
553 | ||
554 | int lr_sp_offset = 0; | |
456f8b9d DB |
555 | |
556 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
557 | register i has been saved at gr_sp_offset[i] from the stack | |
558 | pointer. */ | |
559 | char gr_saved[64]; | |
560 | int gr_sp_offset[64]; | |
561 | ||
d40fcd7b KB |
562 | /* The address of the most recently scanned prologue instruction. */ |
563 | CORE_ADDR last_prologue_pc; | |
564 | ||
565 | /* The address of the next instruction. */ | |
566 | CORE_ADDR next_pc; | |
567 | ||
568 | /* The upper bound to of the pc values to scan. */ | |
569 | CORE_ADDR lim_pc; | |
570 | ||
456f8b9d DB |
571 | memset (gr_saved, 0, sizeof (gr_saved)); |
572 | ||
d40fcd7b KB |
573 | last_prologue_pc = pc; |
574 | ||
575 | /* Try to compute an upper limit (on how far to scan) based on the | |
576 | line number info. */ | |
577 | lim_pc = skip_prologue_using_sal (pc); | |
578 | /* If there's no line number info, lim_pc will be 0. In that case, | |
579 | set the limit to be 100 instructions away from pc. Hopefully, this | |
580 | will be far enough away to account for the entire prologue. Don't | |
581 | worry about overshooting the end of the function. The scan loop | |
582 | below contains some checks to avoid scanning unreasonably far. */ | |
583 | if (lim_pc == 0) | |
584 | lim_pc = pc + 400; | |
585 | ||
586 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
587 | will catch those cases where the pc is in the prologue. */ | |
588 | if (next_frame) | |
589 | { | |
590 | CORE_ADDR frame_pc = frame_pc_unwind (next_frame); | |
591 | if (frame_pc < lim_pc) | |
592 | lim_pc = frame_pc; | |
593 | } | |
594 | ||
595 | /* Scan the prologue. */ | |
596 | while (pc < lim_pc) | |
456f8b9d | 597 | { |
1ccda5e9 KB |
598 | char buf[frv_instr_size]; |
599 | LONGEST op; | |
600 | ||
601 | if (target_read_memory (pc, buf, sizeof buf) != 0) | |
602 | break; | |
603 | op = extract_signed_integer (buf, sizeof buf); | |
604 | ||
d40fcd7b | 605 | next_pc = pc + 4; |
456f8b9d DB |
606 | |
607 | /* The tests in this chain of ifs should be in order of | |
608 | decreasing selectivity, so that more particular patterns get | |
609 | to fire before less particular patterns. */ | |
610 | ||
d40fcd7b KB |
611 | /* Some sort of control transfer instruction: stop scanning prologue. |
612 | Integer Conditional Branch: | |
613 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
614 | Floating-point / media Conditional Branch: | |
615 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
616 | LCR Conditional Branch to LR | |
617 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
618 | Integer conditional Branches to LR | |
619 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
620 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
621 | Floating-point/Media Branches to LR | |
622 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
623 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
624 | Jump and Link | |
625 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
626 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
627 | Call | |
628 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
629 | Return from Trap | |
630 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
631 | Integer Conditional Trap | |
632 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
633 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
634 | Floating-point /media Conditional Trap | |
635 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
636 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
637 | Break | |
638 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
639 | Media Trap | |
640 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
641 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
642 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ | |
643 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ | |
644 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
645 | { | |
646 | /* Stop scanning; not in prologue any longer. */ | |
647 | break; | |
648 | } | |
649 | ||
650 | /* Loading something from memory into fp probably means that | |
651 | we're in the epilogue. Stop scanning the prologue. | |
652 | ld @(GRi, GRk), fp | |
653 | X 000010 0000010 XXXXXX 000100 XXXXXX | |
654 | ldi @(GRi, d12), fp | |
655 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
656 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
657 | || (op & 0x7ffc0000) == 0x04c80000) | |
658 | { | |
659 | break; | |
660 | } | |
661 | ||
456f8b9d DB |
662 | /* Setting the FP from the SP: |
663 | ori sp, 0, fp | |
664 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
665 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
666 | . . . . . . . . | |
667 | We treat this as part of the prologue. */ | |
d40fcd7b | 668 | else if ((op & 0x7fffffff) == 0x04881000) |
456f8b9d DB |
669 | { |
670 | fp_set = 1; | |
671 | fp_offset = 0; | |
d40fcd7b | 672 | last_prologue_pc = next_pc; |
456f8b9d DB |
673 | } |
674 | ||
675 | /* Move the link register to the scratch register grJ, before saving: | |
676 | movsg lr, grJ | |
677 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
678 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
679 | . . . . . . . . | |
680 | We treat this as part of the prologue. */ | |
681 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
682 | { | |
683 | int gr_j = op & 0x3f; | |
684 | ||
685 | /* If we're moving it to a scratch register, that's fine. */ | |
686 | if (is_caller_saves_reg (gr_j)) | |
d40fcd7b KB |
687 | { |
688 | lr_save_reg = gr_j; | |
689 | last_prologue_pc = next_pc; | |
690 | } | |
456f8b9d DB |
691 | } |
692 | ||
693 | /* To save multiple callee-saves registers on the stack, at | |
694 | offset zero: | |
695 | ||
696 | std grK,@(sp,gr0) | |
697 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
698 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
699 | ||
700 | stq grK,@(sp,gr0) | |
701 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
702 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
703 | . . . . . . . . | |
704 | We treat this as part of the prologue, and record the register's | |
705 | saved address in the frame structure. */ | |
706 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
707 | || (op & 0x01ffffff) == 0x000c1100) | |
708 | { | |
709 | int gr_k = ((op >> 25) & 0x3f); | |
710 | int ope = ((op >> 6) & 0x3f); | |
711 | int count; | |
712 | int i; | |
713 | ||
714 | /* Is it an std or an stq? */ | |
715 | if (ope == 0x03) | |
716 | count = 2; | |
717 | else | |
718 | count = 4; | |
719 | ||
720 | /* Is it really a callee-saves register? */ | |
721 | if (is_callee_saves_reg (gr_k)) | |
722 | { | |
723 | for (i = 0; i < count; i++) | |
724 | { | |
725 | gr_saved[gr_k + i] = 1; | |
726 | gr_sp_offset[gr_k + i] = 4 * i; | |
727 | } | |
d40fcd7b | 728 | last_prologue_pc = next_pc; |
456f8b9d | 729 | } |
456f8b9d DB |
730 | } |
731 | ||
732 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
733 | addi sp, S, sp | |
734 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 | |
735 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
736 | . . . . . . . . | |
737 | We treat this as part of the prologue. */ | |
738 | else if ((op & 0x7ffff000) == 0x02401000) | |
739 | { | |
d40fcd7b KB |
740 | if (framesize == 0) |
741 | { | |
742 | /* Sign-extend the twelve-bit field. | |
743 | (Isn't there a better way to do this?) */ | |
744 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
456f8b9d | 745 | |
d40fcd7b KB |
746 | framesize -= s; |
747 | last_prologue_pc = pc; | |
748 | } | |
749 | else | |
750 | { | |
751 | /* If the prologue is being adjusted again, we've | |
752 | likely gone too far; i.e. we're probably in the | |
753 | epilogue. */ | |
754 | break; | |
755 | } | |
456f8b9d DB |
756 | } |
757 | ||
758 | /* Setting the FP to a constant distance from the SP: | |
759 | addi sp, S, fp | |
760 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 | |
761 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
762 | . . . . . . . . | |
763 | We treat this as part of the prologue. */ | |
764 | else if ((op & 0x7ffff000) == 0x04401000) | |
765 | { | |
766 | /* Sign-extend the twelve-bit field. | |
767 | (Isn't there a better way to do this?) */ | |
768 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
769 | fp_set = 1; | |
770 | fp_offset = s; | |
d40fcd7b | 771 | last_prologue_pc = pc; |
456f8b9d DB |
772 | } |
773 | ||
774 | /* To spill an argument register to a scratch register: | |
775 | ori GRi, 0, GRk | |
776 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
777 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
778 | . . . . . . . . | |
779 | For the time being, we treat this as a prologue instruction, | |
780 | assuming that GRi is an argument register. This one's kind | |
781 | of suspicious, because it seems like it could be part of a | |
782 | legitimate body instruction. But we only come here when the | |
783 | source info wasn't helpful, so we have to do the best we can. | |
784 | Hopefully once GCC and GDB agree on how to emit line number | |
785 | info for prologues, then this code will never come into play. */ | |
786 | else if ((op & 0x01fc0fff) == 0x00880000) | |
787 | { | |
788 | int gr_i = ((op >> 12) & 0x3f); | |
789 | ||
d40fcd7b KB |
790 | /* Make sure that the source is an arg register; if it is, we'll |
791 | treat it as a prologue instruction. */ | |
792 | if (is_argument_reg (gr_i)) | |
793 | last_prologue_pc = next_pc; | |
456f8b9d DB |
794 | } |
795 | ||
796 | /* To spill 16-bit values to the stack: | |
797 | sthi GRk, @(fp, s) | |
798 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
799 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
800 | . . . . . . . . | |
801 | And for 8-bit values, we use STB instructions. | |
802 | stbi GRk, @(fp, s) | |
803 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
804 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
805 | . . . . . . . . | |
806 | We check that GRk is really an argument register, and treat | |
807 | all such as part of the prologue. */ | |
808 | else if ( (op & 0x01fff000) == 0x01442000 | |
809 | || (op & 0x01fff000) == 0x01402000) | |
810 | { | |
811 | int gr_k = ((op >> 25) & 0x3f); | |
812 | ||
d40fcd7b KB |
813 | /* Make sure that GRk is really an argument register; treat |
814 | it as a prologue instruction if so. */ | |
815 | if (is_argument_reg (gr_k)) | |
816 | last_prologue_pc = next_pc; | |
456f8b9d DB |
817 | } |
818 | ||
819 | /* To save multiple callee-saves register on the stack, at a | |
820 | non-zero offset: | |
821 | ||
822 | stdi GRk, @(sp, s) | |
823 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
824 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
825 | . . . . . . . . | |
826 | stqi GRk, @(sp, s) | |
827 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
828 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
829 | . . . . . . . . | |
830 | We treat this as part of the prologue, and record the register's | |
831 | saved address in the frame structure. */ | |
832 | else if ((op & 0x01fff000) == 0x014c1000 | |
833 | || (op & 0x01fff000) == 0x01501000) | |
834 | { | |
835 | int gr_k = ((op >> 25) & 0x3f); | |
836 | int count; | |
837 | int i; | |
838 | ||
839 | /* Is it a stdi or a stqi? */ | |
840 | if ((op & 0x01fff000) == 0x014c1000) | |
841 | count = 2; | |
842 | else | |
843 | count = 4; | |
844 | ||
845 | /* Is it really a callee-saves register? */ | |
846 | if (is_callee_saves_reg (gr_k)) | |
847 | { | |
848 | /* Sign-extend the twelve-bit field. | |
849 | (Isn't there a better way to do this?) */ | |
850 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
851 | ||
852 | for (i = 0; i < count; i++) | |
853 | { | |
854 | gr_saved[gr_k + i] = 1; | |
855 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
856 | } | |
d40fcd7b | 857 | last_prologue_pc = next_pc; |
456f8b9d | 858 | } |
456f8b9d DB |
859 | } |
860 | ||
861 | /* Storing any kind of integer register at any constant offset | |
862 | from any other register. | |
863 | ||
864 | st GRk, @(GRi, gr0) | |
865 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 | |
866 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
867 | . . . . . . . . | |
868 | sti GRk, @(GRi, d12) | |
869 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
870 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
871 | . . . . . . . . | |
872 | These could be almost anything, but a lot of prologue | |
873 | instructions fall into this pattern, so let's decode the | |
874 | instruction once, and then work at a higher level. */ | |
875 | else if (((op & 0x01fc0fff) == 0x000c0080) | |
876 | || ((op & 0x01fc0000) == 0x01480000)) | |
877 | { | |
878 | int gr_k = ((op >> 25) & 0x3f); | |
879 | int gr_i = ((op >> 12) & 0x3f); | |
880 | int offset; | |
881 | ||
882 | /* Are we storing with gr0 as an offset, or using an | |
883 | immediate value? */ | |
884 | if ((op & 0x01fc0fff) == 0x000c0080) | |
885 | offset = 0; | |
886 | else | |
887 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
888 | ||
889 | /* If the address isn't relative to the SP or FP, it's not a | |
890 | prologue instruction. */ | |
891 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
d40fcd7b KB |
892 | { |
893 | /* Do nothing; not a prologue instruction. */ | |
894 | } | |
456f8b9d DB |
895 | |
896 | /* Saving the old FP in the new frame (relative to the SP). */ | |
d40fcd7b | 897 | else if (gr_k == fp_regnum && gr_i == sp_regnum) |
1cb761c7 KB |
898 | { |
899 | gr_saved[fp_regnum] = 1; | |
900 | gr_sp_offset[fp_regnum] = offset; | |
d40fcd7b | 901 | last_prologue_pc = next_pc; |
1cb761c7 | 902 | } |
456f8b9d DB |
903 | |
904 | /* Saving callee-saves register(s) on the stack, relative to | |
905 | the SP. */ | |
906 | else if (gr_i == sp_regnum | |
907 | && is_callee_saves_reg (gr_k)) | |
908 | { | |
909 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
910 | if (gr_i == sp_regnum) |
911 | gr_sp_offset[gr_k] = offset; | |
912 | else | |
913 | gr_sp_offset[gr_k] = offset + fp_offset; | |
d40fcd7b | 914 | last_prologue_pc = next_pc; |
456f8b9d DB |
915 | } |
916 | ||
917 | /* Saving the scratch register holding the return address. */ | |
918 | else if (lr_save_reg != -1 | |
919 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
920 | { |
921 | lr_saved_on_stack = 1; | |
922 | if (gr_i == sp_regnum) | |
923 | lr_sp_offset = offset; | |
924 | else | |
925 | lr_sp_offset = offset + fp_offset; | |
d40fcd7b | 926 | last_prologue_pc = next_pc; |
1cb761c7 | 927 | } |
456f8b9d DB |
928 | |
929 | /* Spilling int-sized arguments to the stack. */ | |
930 | else if (is_argument_reg (gr_k)) | |
d40fcd7b | 931 | last_prologue_pc = next_pc; |
456f8b9d | 932 | } |
d40fcd7b | 933 | pc = next_pc; |
456f8b9d DB |
934 | } |
935 | ||
1cb761c7 | 936 | if (next_frame && info) |
456f8b9d | 937 | { |
1cb761c7 KB |
938 | int i; |
939 | ULONGEST this_base; | |
456f8b9d DB |
940 | |
941 | /* If we know the relationship between the stack and frame | |
942 | pointers, record the addresses of the registers we noticed. | |
943 | Note that we have to do this as a separate step at the end, | |
944 | because instructions may save relative to the SP, but we need | |
945 | their addresses relative to the FP. */ | |
946 | if (fp_set) | |
1cb761c7 KB |
947 | frame_unwind_unsigned_register (next_frame, fp_regnum, &this_base); |
948 | else | |
949 | frame_unwind_unsigned_register (next_frame, sp_regnum, &this_base); | |
456f8b9d | 950 | |
1cb761c7 KB |
951 | for (i = 0; i < 64; i++) |
952 | if (gr_saved[i]) | |
953 | info->saved_regs[i].addr = this_base - fp_offset + gr_sp_offset[i]; | |
456f8b9d | 954 | |
1cb761c7 KB |
955 | info->prev_sp = this_base - fp_offset + framesize; |
956 | info->base = this_base; | |
957 | ||
958 | /* If LR was saved on the stack, record its location. */ | |
959 | if (lr_saved_on_stack) | |
960 | info->saved_regs[lr_regnum].addr = this_base - fp_offset + lr_sp_offset; | |
961 | ||
962 | /* The call instruction moves the caller's PC in the callee's LR. | |
963 | Since this is an unwind, do the reverse. Copy the location of LR | |
964 | into PC (the address / regnum) so that a request for PC will be | |
965 | converted into a request for the LR. */ | |
966 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
967 | ||
968 | /* Save the previous frame's computed SP value. */ | |
969 | trad_frame_set_value (info->saved_regs, sp_regnum, info->prev_sp); | |
456f8b9d DB |
970 | } |
971 | ||
d40fcd7b | 972 | return last_prologue_pc; |
456f8b9d DB |
973 | } |
974 | ||
975 | ||
976 | static CORE_ADDR | |
977 | frv_skip_prologue (CORE_ADDR pc) | |
978 | { | |
979 | CORE_ADDR func_addr, func_end, new_pc; | |
980 | ||
981 | new_pc = pc; | |
982 | ||
983 | /* If the line table has entry for a line *within* the function | |
984 | (i.e., not in the prologue, and not past the end), then that's | |
985 | our location. */ | |
986 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
987 | { | |
988 | struct symtab_and_line sal; | |
989 | ||
990 | sal = find_pc_line (func_addr, 0); | |
991 | ||
992 | if (sal.line != 0 && sal.end < func_end) | |
993 | { | |
994 | new_pc = sal.end; | |
995 | } | |
996 | } | |
997 | ||
998 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
999 | If we didn't find a real source location past that, then | |
1000 | do a full analysis of the prologue. */ | |
1001 | if (new_pc < pc + 20) | |
1cb761c7 | 1002 | new_pc = frv_analyze_prologue (pc, 0, 0); |
456f8b9d DB |
1003 | |
1004 | return new_pc; | |
1005 | } | |
1006 | ||
1cb761c7 KB |
1007 | |
1008 | static struct frv_unwind_cache * | |
1009 | frv_frame_unwind_cache (struct frame_info *next_frame, | |
1010 | void **this_prologue_cache) | |
456f8b9d | 1011 | { |
1cb761c7 KB |
1012 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1013 | CORE_ADDR pc; | |
1cb761c7 KB |
1014 | ULONGEST this_base; |
1015 | struct frv_unwind_cache *info; | |
8baa6f92 | 1016 | |
1cb761c7 KB |
1017 | if ((*this_prologue_cache)) |
1018 | return (*this_prologue_cache); | |
456f8b9d | 1019 | |
1cb761c7 KB |
1020 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
1021 | (*this_prologue_cache) = info; | |
1022 | info->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
456f8b9d | 1023 | |
1cb761c7 KB |
1024 | /* Prologue analysis does the rest... */ |
1025 | frv_analyze_prologue (frame_func_unwind (next_frame), next_frame, info); | |
456f8b9d | 1026 | |
1cb761c7 | 1027 | return info; |
456f8b9d DB |
1028 | } |
1029 | ||
456f8b9d | 1030 | static void |
cd31fb03 KB |
1031 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
1032 | void *valbuf) | |
456f8b9d | 1033 | { |
cd31fb03 KB |
1034 | int len = TYPE_LENGTH (type); |
1035 | ||
1036 | if (len <= 4) | |
1037 | { | |
1038 | ULONGEST gpr8_val; | |
1039 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
1040 | store_unsigned_integer (valbuf, len, gpr8_val); | |
1041 | } | |
1042 | else if (len == 8) | |
1043 | { | |
1044 | ULONGEST regval; | |
1045 | regcache_cooked_read_unsigned (regcache, 8, ®val); | |
1046 | store_unsigned_integer (valbuf, 4, regval); | |
1047 | regcache_cooked_read_unsigned (regcache, 9, ®val); | |
1048 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, regval); | |
1049 | } | |
1050 | else | |
1051 | internal_error (__FILE__, __LINE__, "Illegal return value length: %d", len); | |
456f8b9d DB |
1052 | } |
1053 | ||
1054 | static CORE_ADDR | |
cd31fb03 | 1055 | frv_extract_struct_value_address (struct regcache *regcache) |
456f8b9d | 1056 | { |
cd31fb03 KB |
1057 | ULONGEST addr; |
1058 | regcache_cooked_read_unsigned (regcache, struct_return_regnum, &addr); | |
1059 | return addr; | |
456f8b9d DB |
1060 | } |
1061 | ||
1062 | static void | |
1063 | frv_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1064 | { | |
1065 | write_register (struct_return_regnum, addr); | |
1066 | } | |
1067 | ||
1068 | static int | |
1069 | frv_frameless_function_invocation (struct frame_info *frame) | |
1070 | { | |
19772a2c | 1071 | return legacy_frameless_look_for_prologue (frame); |
456f8b9d DB |
1072 | } |
1073 | ||
1cb761c7 KB |
1074 | static CORE_ADDR |
1075 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 1076 | { |
1cb761c7 | 1077 | /* Require dword alignment. */ |
5b03f266 | 1078 | return align_down (sp, 8); |
456f8b9d DB |
1079 | } |
1080 | ||
c4d10515 KB |
1081 | static CORE_ADDR |
1082 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) | |
1083 | { | |
1084 | CORE_ADDR descr; | |
1085 | char valbuf[4]; | |
1086 | ||
1087 | descr = frv_fdpic_find_canonical_descriptor (entry_point); | |
1088 | ||
1089 | if (descr != 0) | |
1090 | return descr; | |
1091 | ||
1092 | /* Construct a non-canonical descriptor from space allocated on | |
1093 | the stack. */ | |
1094 | ||
1095 | descr = value_as_long (value_allocate_space_in_inferior (8)); | |
1096 | store_unsigned_integer (valbuf, 4, entry_point); | |
1097 | write_memory (descr, valbuf, 4); | |
1098 | store_unsigned_integer (valbuf, 4, | |
1099 | frv_fdpic_find_global_pointer (entry_point)); | |
1100 | write_memory (descr + 4, valbuf, 4); | |
1101 | return descr; | |
1102 | } | |
1103 | ||
1104 | static CORE_ADDR | |
1105 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, | |
1106 | struct target_ops *targ) | |
1107 | { | |
1108 | CORE_ADDR entry_point; | |
1109 | CORE_ADDR got_address; | |
1110 | ||
1111 | entry_point = get_target_memory_unsigned (targ, addr, 4); | |
1112 | got_address = get_target_memory_unsigned (targ, addr + 4, 4); | |
1113 | ||
1114 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) | |
1115 | return entry_point; | |
1116 | else | |
1117 | return addr; | |
1118 | } | |
1119 | ||
456f8b9d | 1120 | static CORE_ADDR |
1cb761c7 KB |
1121 | frv_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1122 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1123 | int nargs, struct value **args, CORE_ADDR sp, | |
1124 | int struct_return, CORE_ADDR struct_addr) | |
456f8b9d DB |
1125 | { |
1126 | int argreg; | |
1127 | int argnum; | |
1128 | char *val; | |
1129 | char valbuf[4]; | |
1130 | struct value *arg; | |
1131 | struct type *arg_type; | |
1132 | int len; | |
1133 | enum type_code typecode; | |
1134 | CORE_ADDR regval; | |
1135 | int stack_space; | |
1136 | int stack_offset; | |
c4d10515 | 1137 | enum frv_abi abi = frv_abi (gdbarch); |
456f8b9d DB |
1138 | |
1139 | #if 0 | |
1140 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1141 | nargs, (int) sp, struct_return, struct_addr); | |
1142 | #endif | |
1143 | ||
1144 | stack_space = 0; | |
1145 | for (argnum = 0; argnum < nargs; ++argnum) | |
5b03f266 | 1146 | stack_space += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), 4); |
456f8b9d DB |
1147 | |
1148 | stack_space -= (6 * 4); | |
1149 | if (stack_space > 0) | |
1150 | sp -= stack_space; | |
1151 | ||
1152 | /* Make sure stack is dword aligned. */ | |
5b03f266 | 1153 | sp = align_down (sp, 8); |
456f8b9d DB |
1154 | |
1155 | stack_offset = 0; | |
1156 | ||
1157 | argreg = 8; | |
1158 | ||
1159 | if (struct_return) | |
1cb761c7 KB |
1160 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
1161 | struct_addr); | |
456f8b9d DB |
1162 | |
1163 | for (argnum = 0; argnum < nargs; ++argnum) | |
1164 | { | |
1165 | arg = args[argnum]; | |
1166 | arg_type = check_typedef (VALUE_TYPE (arg)); | |
1167 | len = TYPE_LENGTH (arg_type); | |
1168 | typecode = TYPE_CODE (arg_type); | |
1169 | ||
1170 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1171 | { | |
fbd9dcd3 | 1172 | store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (arg)); |
456f8b9d DB |
1173 | typecode = TYPE_CODE_PTR; |
1174 | len = 4; | |
1175 | val = valbuf; | |
1176 | } | |
c4d10515 KB |
1177 | else if (abi == FRV_ABI_FDPIC |
1178 | && len == 4 | |
1179 | && typecode == TYPE_CODE_PTR | |
1180 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
1181 | { | |
1182 | /* The FDPIC ABI requires function descriptors to be passed instead | |
1183 | of entry points. */ | |
1184 | store_unsigned_integer | |
1185 | (valbuf, 4, | |
1186 | find_func_descr (gdbarch, | |
1187 | extract_unsigned_integer (VALUE_CONTENTS (arg), | |
1188 | 4))); | |
1189 | typecode = TYPE_CODE_PTR; | |
1190 | len = 4; | |
1191 | val = valbuf; | |
1192 | } | |
456f8b9d DB |
1193 | else |
1194 | { | |
1195 | val = (char *) VALUE_CONTENTS (arg); | |
1196 | } | |
1197 | ||
1198 | while (len > 0) | |
1199 | { | |
1200 | int partial_len = (len < 4 ? len : 4); | |
1201 | ||
1202 | if (argreg < 14) | |
1203 | { | |
7c0b4a20 | 1204 | regval = extract_unsigned_integer (val, partial_len); |
456f8b9d DB |
1205 | #if 0 |
1206 | printf(" Argnum %d data %x -> reg %d\n", | |
1207 | argnum, (int) regval, argreg); | |
1208 | #endif | |
1cb761c7 | 1209 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
1210 | ++argreg; |
1211 | } | |
1212 | else | |
1213 | { | |
1214 | #if 0 | |
1215 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
1216 | argnum, *((int *)val), stack_offset, (int) (sp + stack_offset)); | |
1217 | #endif | |
1218 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 1219 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
1220 | } |
1221 | len -= partial_len; | |
1222 | val += partial_len; | |
1223 | } | |
1224 | } | |
456f8b9d | 1225 | |
1cb761c7 KB |
1226 | /* Set the return address. For the frv, the return breakpoint is |
1227 | always at BP_ADDR. */ | |
1228 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1229 | ||
c4d10515 KB |
1230 | if (abi == FRV_ABI_FDPIC) |
1231 | { | |
1232 | /* Set the GOT register for the FDPIC ABI. */ | |
1233 | regcache_cooked_write_unsigned | |
1234 | (regcache, first_gpr_regnum + 15, | |
1235 | frv_fdpic_find_global_pointer (func_addr)); | |
1236 | } | |
1237 | ||
1cb761c7 KB |
1238 | /* Finally, update the SP register. */ |
1239 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1240 | ||
456f8b9d DB |
1241 | return sp; |
1242 | } | |
1243 | ||
1244 | static void | |
cd31fb03 KB |
1245 | frv_store_return_value (struct type *type, struct regcache *regcache, |
1246 | const void *valbuf) | |
456f8b9d | 1247 | { |
cd31fb03 KB |
1248 | int len = TYPE_LENGTH (type); |
1249 | ||
1250 | if (len <= 4) | |
1251 | { | |
1252 | bfd_byte val[4]; | |
1253 | memset (val, 0, sizeof (val)); | |
1254 | memcpy (val + (4 - len), valbuf, len); | |
1255 | regcache_cooked_write (regcache, 8, val); | |
1256 | } | |
1257 | else if (len == 8) | |
1258 | { | |
1259 | regcache_cooked_write (regcache, 8, valbuf); | |
1260 | regcache_cooked_write (regcache, 9, (bfd_byte *) valbuf + 4); | |
1261 | } | |
456f8b9d DB |
1262 | else |
1263 | internal_error (__FILE__, __LINE__, | |
cd31fb03 | 1264 | "Don't know how to return a %d-byte value.", len); |
456f8b9d DB |
1265 | } |
1266 | ||
456f8b9d | 1267 | |
456f8b9d DB |
1268 | /* Hardware watchpoint / breakpoint support for the FR500 |
1269 | and FR400. */ | |
1270 | ||
1271 | int | |
1272 | frv_check_watch_resources (int type, int cnt, int ot) | |
1273 | { | |
1274 | struct gdbarch_tdep *var = CURRENT_VARIANT; | |
1275 | ||
1276 | /* Watchpoints not supported on simulator. */ | |
1277 | if (strcmp (target_shortname, "sim") == 0) | |
1278 | return 0; | |
1279 | ||
1280 | if (type == bp_hardware_breakpoint) | |
1281 | { | |
1282 | if (var->num_hw_breakpoints == 0) | |
1283 | return 0; | |
1284 | else if (cnt <= var->num_hw_breakpoints) | |
1285 | return 1; | |
1286 | } | |
1287 | else | |
1288 | { | |
1289 | if (var->num_hw_watchpoints == 0) | |
1290 | return 0; | |
1291 | else if (ot) | |
1292 | return -1; | |
1293 | else if (cnt <= var->num_hw_watchpoints) | |
1294 | return 1; | |
1295 | } | |
1296 | return -1; | |
1297 | } | |
1298 | ||
1299 | ||
1300 | CORE_ADDR | |
5ae5f592 | 1301 | frv_stopped_data_address (void) |
456f8b9d DB |
1302 | { |
1303 | CORE_ADDR brr, dbar0, dbar1, dbar2, dbar3; | |
1304 | ||
1305 | brr = read_register (brr_regnum); | |
1306 | dbar0 = read_register (dbar0_regnum); | |
1307 | dbar1 = read_register (dbar1_regnum); | |
1308 | dbar2 = read_register (dbar2_regnum); | |
1309 | dbar3 = read_register (dbar3_regnum); | |
1310 | ||
1311 | if (brr & (1<<11)) | |
1312 | return dbar0; | |
1313 | else if (brr & (1<<10)) | |
1314 | return dbar1; | |
1315 | else if (brr & (1<<9)) | |
1316 | return dbar2; | |
1317 | else if (brr & (1<<8)) | |
1318 | return dbar3; | |
1319 | else | |
1320 | return 0; | |
1321 | } | |
1322 | ||
1cb761c7 KB |
1323 | static CORE_ADDR |
1324 | frv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1325 | { | |
1326 | return frame_unwind_register_unsigned (next_frame, pc_regnum); | |
1327 | } | |
1328 | ||
1329 | /* Given a GDB frame, determine the address of the calling function's | |
1330 | frame. This will be used to create a new GDB frame struct. */ | |
1331 | ||
1332 | static void | |
1333 | frv_frame_this_id (struct frame_info *next_frame, | |
1334 | void **this_prologue_cache, struct frame_id *this_id) | |
1335 | { | |
1336 | struct frv_unwind_cache *info | |
1337 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1338 | CORE_ADDR base; | |
1339 | CORE_ADDR func; | |
1340 | struct minimal_symbol *msym_stack; | |
1341 | struct frame_id id; | |
1342 | ||
1343 | /* The FUNC is easy. */ | |
1344 | func = frame_func_unwind (next_frame); | |
1345 | ||
1cb761c7 KB |
1346 | /* Check if the stack is empty. */ |
1347 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
1348 | if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) | |
1349 | return; | |
1350 | ||
1351 | /* Hopefully the prologue analysis either correctly determined the | |
1352 | frame's base (which is the SP from the previous frame), or set | |
1353 | that base to "NULL". */ | |
1354 | base = info->prev_sp; | |
1355 | if (base == 0) | |
1356 | return; | |
1357 | ||
1358 | id = frame_id_build (base, func); | |
1cb761c7 KB |
1359 | (*this_id) = id; |
1360 | } | |
1361 | ||
1362 | static void | |
1363 | frv_frame_prev_register (struct frame_info *next_frame, | |
1364 | void **this_prologue_cache, | |
1365 | int regnum, int *optimizedp, | |
1366 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1367 | int *realnump, void *bufferp) | |
1368 | { | |
1369 | struct frv_unwind_cache *info | |
1370 | = frv_frame_unwind_cache (next_frame, this_prologue_cache); | |
1371 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
1372 | optimizedp, lvalp, addrp, realnump, bufferp); | |
1373 | } | |
1374 | ||
1375 | static const struct frame_unwind frv_frame_unwind = { | |
1376 | NORMAL_FRAME, | |
1377 | frv_frame_this_id, | |
1378 | frv_frame_prev_register | |
1379 | }; | |
1380 | ||
1381 | static const struct frame_unwind * | |
1382 | frv_frame_sniffer (struct frame_info *next_frame) | |
1383 | { | |
1384 | return &frv_frame_unwind; | |
1385 | } | |
1386 | ||
1387 | static CORE_ADDR | |
1388 | frv_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1389 | { | |
1390 | struct frv_unwind_cache *info | |
1391 | = frv_frame_unwind_cache (next_frame, this_cache); | |
1392 | return info->base; | |
1393 | } | |
1394 | ||
1395 | static const struct frame_base frv_frame_base = { | |
1396 | &frv_frame_unwind, | |
1397 | frv_frame_base_address, | |
1398 | frv_frame_base_address, | |
1399 | frv_frame_base_address | |
1400 | }; | |
1401 | ||
1402 | static CORE_ADDR | |
1403 | frv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1404 | { | |
1405 | return frame_unwind_register_unsigned (next_frame, sp_regnum); | |
1406 | } | |
1407 | ||
1408 | ||
1409 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
1410 | dummy frame. The frame ID's base needs to match the TOS value | |
1411 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1412 | breakpoint. */ | |
1413 | ||
1414 | static struct frame_id | |
1415 | frv_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1416 | { | |
1417 | return frame_id_build (frv_unwind_sp (gdbarch, next_frame), | |
1418 | frame_pc_unwind (next_frame)); | |
1419 | } | |
1420 | ||
456f8b9d DB |
1421 | static struct gdbarch * |
1422 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1423 | { | |
1424 | struct gdbarch *gdbarch; | |
1425 | struct gdbarch_tdep *var; | |
7e295833 | 1426 | int elf_flags = 0; |
456f8b9d DB |
1427 | |
1428 | /* Check to see if we've already built an appropriate architecture | |
1429 | object for this executable. */ | |
1430 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1431 | if (arches) | |
1432 | return arches->gdbarch; | |
1433 | ||
1434 | /* Select the right tdep structure for this variant. */ | |
1435 | var = new_variant (); | |
1436 | switch (info.bfd_arch_info->mach) | |
1437 | { | |
1438 | case bfd_mach_frv: | |
1439 | case bfd_mach_frvsimple: | |
1440 | case bfd_mach_fr500: | |
1441 | case bfd_mach_frvtomcat: | |
251a3ae3 | 1442 | case bfd_mach_fr550: |
456f8b9d DB |
1443 | set_variant_num_gprs (var, 64); |
1444 | set_variant_num_fprs (var, 64); | |
1445 | break; | |
1446 | ||
1447 | case bfd_mach_fr400: | |
b2d6d697 | 1448 | case bfd_mach_fr450: |
456f8b9d DB |
1449 | set_variant_num_gprs (var, 32); |
1450 | set_variant_num_fprs (var, 32); | |
1451 | break; | |
1452 | ||
1453 | default: | |
1454 | /* Never heard of this variant. */ | |
1455 | return 0; | |
1456 | } | |
7e295833 KB |
1457 | |
1458 | /* Extract the ELF flags, if available. */ | |
1459 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1460 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1461 | ||
1462 | if (elf_flags & EF_FRV_FDPIC) | |
1463 | set_variant_abi_fdpic (var); | |
1464 | ||
b2d6d697 KB |
1465 | if (elf_flags & EF_FRV_CPU_FR450) |
1466 | set_variant_scratch_registers (var); | |
1467 | ||
456f8b9d DB |
1468 | gdbarch = gdbarch_alloc (&info, var); |
1469 | ||
1470 | set_gdbarch_short_bit (gdbarch, 16); | |
1471 | set_gdbarch_int_bit (gdbarch, 32); | |
1472 | set_gdbarch_long_bit (gdbarch, 32); | |
1473 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1474 | set_gdbarch_float_bit (gdbarch, 32); | |
1475 | set_gdbarch_double_bit (gdbarch, 64); | |
1476 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1477 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1478 | ||
1479 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
6a748db6 KB |
1480 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
1481 | ||
456f8b9d | 1482 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
0ba6dca9 | 1483 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1484 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1485 | ||
1486 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1487 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1488 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d | 1489 | |
6a748db6 KB |
1490 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
1491 | set_gdbarch_pseudo_register_write (gdbarch, frv_pseudo_register_write); | |
1492 | ||
456f8b9d DB |
1493 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
1494 | set_gdbarch_breakpoint_from_pc (gdbarch, frv_breakpoint_from_pc); | |
46a16dba | 1495 | set_gdbarch_adjust_breakpoint_address (gdbarch, frv_gdbarch_adjust_breakpoint_address); |
456f8b9d | 1496 | |
19772a2c | 1497 | set_gdbarch_deprecated_frameless_function_invocation (gdbarch, frv_frameless_function_invocation); |
456f8b9d | 1498 | |
1fd35568 | 1499 | set_gdbarch_use_struct_convention (gdbarch, always_use_struct_convention); |
cd31fb03 | 1500 | set_gdbarch_extract_return_value (gdbarch, frv_extract_return_value); |
456f8b9d | 1501 | |
4183d812 | 1502 | set_gdbarch_deprecated_store_struct_return (gdbarch, frv_store_struct_return); |
cd31fb03 | 1503 | set_gdbarch_store_return_value (gdbarch, frv_store_return_value); |
74055713 | 1504 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, frv_extract_struct_value_address); |
456f8b9d | 1505 | |
1cb761c7 KB |
1506 | /* Frame stuff. */ |
1507 | set_gdbarch_unwind_pc (gdbarch, frv_unwind_pc); | |
1508 | set_gdbarch_unwind_sp (gdbarch, frv_unwind_sp); | |
1509 | set_gdbarch_frame_align (gdbarch, frv_frame_align); | |
1cb761c7 | 1510 | frame_base_set_default (gdbarch, &frv_frame_base); |
5ecb7103 KB |
1511 | /* We set the sniffer lower down after the OSABI hooks have been |
1512 | established. */ | |
456f8b9d | 1513 | |
1cb761c7 KB |
1514 | /* Settings for calling functions in the inferior. */ |
1515 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
1516 | set_gdbarch_unwind_dummy_id (gdbarch, frv_unwind_dummy_id); | |
456f8b9d DB |
1517 | |
1518 | /* Settings that should be unnecessary. */ | |
1519 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1520 | ||
456f8b9d | 1521 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
456f8b9d | 1522 | |
456f8b9d | 1523 | set_gdbarch_remote_translate_xfer_address |
aed7f26a | 1524 | (gdbarch, generic_remote_translate_xfer_address); |
456f8b9d DB |
1525 | |
1526 | /* Hardware watchpoint / breakpoint support. */ | |
1527 | switch (info.bfd_arch_info->mach) | |
1528 | { | |
1529 | case bfd_mach_frv: | |
1530 | case bfd_mach_frvsimple: | |
1531 | case bfd_mach_fr500: | |
1532 | case bfd_mach_frvtomcat: | |
1533 | /* fr500-style hardware debugging support. */ | |
1534 | var->num_hw_watchpoints = 4; | |
1535 | var->num_hw_breakpoints = 4; | |
1536 | break; | |
1537 | ||
1538 | case bfd_mach_fr400: | |
b2d6d697 | 1539 | case bfd_mach_fr450: |
456f8b9d DB |
1540 | /* fr400-style hardware debugging support. */ |
1541 | var->num_hw_watchpoints = 2; | |
1542 | var->num_hw_breakpoints = 4; | |
1543 | break; | |
1544 | ||
1545 | default: | |
1546 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1547 | var->num_hw_watchpoints = 0; | |
1548 | var->num_hw_breakpoints = 0; | |
1549 | break; | |
1550 | } | |
1551 | ||
36482093 | 1552 | set_gdbarch_print_insn (gdbarch, print_insn_frv); |
c4d10515 KB |
1553 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) |
1554 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, | |
1555 | frv_convert_from_func_ptr_addr); | |
36482093 | 1556 | |
5ecb7103 KB |
1557 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1558 | gdbarch_init_osabi (info, gdbarch); | |
1559 | ||
5ecb7103 KB |
1560 | /* Set the fallback (prologue based) frame sniffer. */ |
1561 | frame_unwind_append_sniffer (gdbarch, frv_frame_sniffer); | |
1562 | ||
456f8b9d DB |
1563 | return gdbarch; |
1564 | } | |
1565 | ||
1566 | void | |
1567 | _initialize_frv_tdep (void) | |
1568 | { | |
1569 | register_gdbarch_init (bfd_arch_frv, frv_gdbarch_init); | |
456f8b9d | 1570 | } |