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618f726f | 1 | /* Copyright (C) 1995-2016 Free Software Foundation, Inc. |
bd9e6534 YQ |
2 | |
3 | This file is part of GDB. | |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 3 of the License, or | |
8 | (at your option) any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
17 | ||
18 | #include "server.h" | |
19 | #include "arch/arm.h" | |
6885166d | 20 | #include "arch/arm-linux.h" |
bd9e6534 YQ |
21 | #include "linux-low.h" |
22 | #include "linux-aarch32-low.h" | |
23 | ||
24 | #include <sys/ptrace.h> | |
25 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. | |
26 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
27 | #ifndef ELFMAG0 | |
28 | #include <elf.h> | |
29 | #endif | |
30 | ||
b2ca446f YQ |
31 | /* Correct in either endianness. */ |
32 | #define arm_abi_breakpoint 0xef9f0001UL | |
33 | ||
34 | /* For new EABI binaries. We recognize it regardless of which ABI | |
35 | is used for gdbserver, so single threaded debugging should work | |
36 | OK, but for multi-threaded debugging we only insert the current | |
37 | ABI's breakpoint instruction. For now at least. */ | |
38 | #define arm_eabi_breakpoint 0xe7f001f0UL | |
39 | ||
40 | #if (defined __ARM_EABI__ || defined __aarch64__) | |
41 | static const unsigned long arm_breakpoint = arm_eabi_breakpoint; | |
42 | #else | |
43 | static const unsigned long arm_breakpoint = arm_abi_breakpoint; | |
44 | #endif | |
45 | ||
46 | #define arm_breakpoint_len 4 | |
47 | static const unsigned short thumb_breakpoint = 0xde01; | |
48 | #define thumb_breakpoint_len 2 | |
1b451dda | 49 | static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 }; |
b2ca446f YQ |
50 | #define thumb2_breakpoint_len 4 |
51 | ||
16d5f642 JB |
52 | /* Some older versions of GNU/Linux and Android do not define |
53 | the following macros. */ | |
54 | #ifndef NT_ARM_VFP | |
55 | #define NT_ARM_VFP 0x400 | |
56 | #endif | |
57 | ||
bd9e6534 YQ |
58 | /* Collect GP registers from REGCACHE to buffer BUF. */ |
59 | ||
60 | void | |
61 | arm_fill_gregset (struct regcache *regcache, void *buf) | |
62 | { | |
63 | int i; | |
04248ead | 64 | uint32_t *regs = (uint32_t *) buf; |
bd9e6534 YQ |
65 | |
66 | for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) | |
67 | collect_register (regcache, i, ®s[i]); | |
68 | ||
6885166d | 69 | collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); |
bd9e6534 YQ |
70 | } |
71 | ||
72 | /* Supply GP registers contents, stored in BUF, to REGCACHE. */ | |
73 | ||
74 | void | |
75 | arm_store_gregset (struct regcache *regcache, const void *buf) | |
76 | { | |
77 | int i; | |
78 | char zerobuf[8]; | |
04248ead | 79 | const uint32_t *regs = (const uint32_t *) buf; |
3539aa13 | 80 | uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; |
bd9e6534 YQ |
81 | |
82 | memset (zerobuf, 0, 8); | |
83 | for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) | |
84 | supply_register (regcache, i, ®s[i]); | |
85 | ||
86 | for (; i < ARM_PS_REGNUM; i++) | |
87 | supply_register (regcache, i, zerobuf); | |
88 | ||
3539aa13 YQ |
89 | /* Clear reserved bits bit 20 to bit 23. */ |
90 | cpsr &= 0xff0fffff; | |
91 | supply_register (regcache, ARM_PS_REGNUM, &cpsr); | |
bd9e6534 YQ |
92 | } |
93 | ||
94 | /* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */ | |
95 | ||
96 | void | |
97 | arm_fill_vfpregset_num (struct regcache *regcache, void *buf, int num) | |
98 | { | |
99 | int i, base; | |
100 | ||
101 | gdb_assert (num == 16 || num == 32); | |
102 | ||
103 | base = find_regno (regcache->tdesc, "d0"); | |
104 | for (i = 0; i < num; i++) | |
105 | collect_register (regcache, base + i, (char *) buf + i * 8); | |
106 | ||
107 | collect_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); | |
108 | } | |
109 | ||
110 | /* Supply NUM number of VFP registers contents, stored in BUF, to | |
111 | REGCACHE. */ | |
112 | ||
113 | void | |
114 | arm_store_vfpregset_num (struct regcache *regcache, const void *buf, int num) | |
115 | { | |
116 | int i, base; | |
117 | ||
118 | gdb_assert (num == 16 || num == 32); | |
119 | ||
120 | base = find_regno (regcache->tdesc, "d0"); | |
121 | for (i = 0; i < num; i++) | |
122 | supply_register (regcache, base + i, (char *) buf + i * 8); | |
123 | ||
124 | supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); | |
125 | } | |
126 | ||
127 | static void | |
128 | arm_fill_vfpregset (struct regcache *regcache, void *buf) | |
129 | { | |
130 | arm_fill_vfpregset_num (regcache, buf, 32); | |
131 | } | |
132 | ||
133 | static void | |
134 | arm_store_vfpregset (struct regcache *regcache, const void *buf) | |
135 | { | |
136 | arm_store_vfpregset_num (regcache, buf, 32); | |
137 | } | |
138 | ||
139 | /* Register sets with using PTRACE_GETREGSET. */ | |
140 | ||
141 | static struct regset_info aarch32_regsets[] = { | |
142 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 18 * 4, | |
143 | GENERAL_REGS, | |
144 | arm_fill_gregset, arm_store_gregset }, | |
145 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, 32 * 8 + 4, | |
146 | EXTENDED_REGS, | |
147 | arm_fill_vfpregset, arm_store_vfpregset }, | |
04b3479c | 148 | NULL_REGSET |
bd9e6534 YQ |
149 | }; |
150 | ||
151 | static struct regsets_info aarch32_regsets_info = | |
152 | { | |
153 | aarch32_regsets, /* regsets */ | |
154 | 0, /* num_regsets */ | |
155 | NULL, /* disabled_regsets */ | |
156 | }; | |
157 | ||
158 | struct regs_info regs_info_aarch32 = | |
159 | { | |
160 | NULL, /* regset_bitmap */ | |
161 | NULL, /* usrregs */ | |
162 | &aarch32_regsets_info | |
163 | }; | |
164 | ||
17b1509a YQ |
165 | /* Returns 1 if the current instruction set is thumb, 0 otherwise. */ |
166 | ||
d9311bfa | 167 | int |
17b1509a YQ |
168 | arm_is_thumb_mode (void) |
169 | { | |
170 | struct regcache *regcache = get_thread_regcache (current_thread, 1); | |
171 | unsigned long cpsr; | |
172 | ||
173 | collect_register_by_name (regcache, "cpsr", &cpsr); | |
174 | ||
175 | if (cpsr & 0x20) | |
176 | return 1; | |
177 | else | |
178 | return 0; | |
179 | } | |
180 | ||
181 | /* Returns 1 if there is a software breakpoint at location. */ | |
182 | ||
183 | int | |
184 | arm_breakpoint_at (CORE_ADDR where) | |
185 | { | |
186 | if (arm_is_thumb_mode ()) | |
187 | { | |
188 | /* Thumb mode. */ | |
189 | unsigned short insn; | |
190 | ||
191 | (*the_target->read_memory) (where, (unsigned char *) &insn, 2); | |
192 | if (insn == thumb_breakpoint) | |
193 | return 1; | |
194 | ||
195 | if (insn == thumb2_breakpoint[0]) | |
196 | { | |
197 | (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2); | |
198 | if (insn == thumb2_breakpoint[1]) | |
199 | return 1; | |
200 | } | |
201 | } | |
202 | else | |
203 | { | |
204 | /* ARM mode. */ | |
205 | unsigned long insn; | |
206 | ||
207 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
208 | if (insn == arm_abi_breakpoint) | |
209 | return 1; | |
210 | ||
211 | if (insn == arm_eabi_breakpoint) | |
212 | return 1; | |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | /* Enum describing the different kinds of breakpoints. */ | |
219 | enum arm_breakpoint_kinds | |
220 | { | |
221 | ARM_BP_KIND_THUMB = 2, | |
222 | ARM_BP_KIND_THUMB2 = 3, | |
223 | ARM_BP_KIND_ARM = 4, | |
224 | }; | |
225 | ||
226 | /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". | |
227 | ||
228 | Determine the type and size of breakpoint to insert at PCPTR. Uses the | |
229 | program counter value to determine whether a 16-bit or 32-bit breakpoint | |
230 | should be used. It returns the breakpoint's kind, and adjusts the program | |
231 | counter (if necessary) to point to the actual memory location where the | |
232 | breakpoint should be inserted. */ | |
233 | ||
234 | int | |
235 | arm_breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
236 | { | |
237 | if (IS_THUMB_ADDR (*pcptr)) | |
238 | { | |
239 | gdb_byte buf[2]; | |
240 | ||
241 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
242 | ||
243 | /* Check whether we are replacing a thumb2 32-bit instruction. */ | |
244 | if ((*the_target->read_memory) (*pcptr, buf, 2) == 0) | |
245 | { | |
246 | unsigned short inst1 = 0; | |
247 | ||
248 | (*the_target->read_memory) (*pcptr, (gdb_byte *) &inst1, 2); | |
249 | if (thumb_insn_size (inst1) == 4) | |
250 | return ARM_BP_KIND_THUMB2; | |
251 | } | |
252 | return ARM_BP_KIND_THUMB; | |
253 | } | |
254 | else | |
255 | return ARM_BP_KIND_ARM; | |
256 | } | |
257 | ||
258 | /* Implementation of the linux_target_ops method "sw_breakpoint_from_kind". */ | |
259 | ||
260 | const gdb_byte * | |
261 | arm_sw_breakpoint_from_kind (int kind , int *size) | |
262 | { | |
263 | *size = arm_breakpoint_len; | |
264 | /* Define an ARM-mode breakpoint; we only set breakpoints in the C | |
265 | library, which is most likely to be ARM. If the kernel supports | |
266 | clone events, we will never insert a breakpoint, so even a Thumb | |
267 | C library will work; so will mixing EABI/non-EABI gdbserver and | |
268 | application. */ | |
269 | switch (kind) | |
270 | { | |
271 | case ARM_BP_KIND_THUMB: | |
272 | *size = thumb_breakpoint_len; | |
273 | return (gdb_byte *) &thumb_breakpoint; | |
274 | case ARM_BP_KIND_THUMB2: | |
275 | *size = thumb2_breakpoint_len; | |
276 | return (gdb_byte *) &thumb2_breakpoint; | |
277 | case ARM_BP_KIND_ARM: | |
278 | *size = arm_breakpoint_len; | |
279 | return (const gdb_byte *) &arm_breakpoint; | |
280 | default: | |
281 | return NULL; | |
282 | } | |
283 | return NULL; | |
284 | } | |
285 | ||
286 | /* Implementation of the linux_target_ops method | |
287 | "breakpoint_kind_from_current_state". */ | |
288 | ||
289 | int | |
290 | arm_breakpoint_kind_from_current_state (CORE_ADDR *pcptr) | |
291 | { | |
292 | if (arm_is_thumb_mode ()) | |
293 | { | |
294 | *pcptr = MAKE_THUMB_ADDR (*pcptr); | |
295 | return arm_breakpoint_kind_from_pc (pcptr); | |
296 | } | |
297 | else | |
298 | { | |
299 | return arm_breakpoint_kind_from_pc (pcptr); | |
300 | } | |
301 | } | |
302 | ||
bd9e6534 YQ |
303 | void |
304 | initialize_low_arch_aarch32 (void) | |
305 | { | |
306 | init_registers_arm_with_neon (); | |
307 | ||
308 | initialize_regsets_info (&aarch32_regsets_info); | |
309 | } |