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176eb98c MS |
1 | /* GNU/Linux/AArch64 specific low level interface, for the remote server for |
2 | GDB. | |
3 | ||
32d0add0 | 4 | Copyright (C) 2009-2015 Free Software Foundation, Inc. |
176eb98c MS |
5 | Contributed by ARM Ltd. |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #include "server.h" | |
23 | #include "linux-low.h" | |
24 | #include "elf/common.h" | |
25 | ||
26 | #include <signal.h> | |
27 | #include <sys/user.h> | |
28 | #include <sys/ptrace.h> | |
e9dae05e | 29 | #include <asm/ptrace.h> |
176eb98c MS |
30 | #include <sys/uio.h> |
31 | ||
32 | #include "gdb_proc_service.h" | |
33 | ||
34 | /* Defined in auto-generated files. */ | |
35 | void init_registers_aarch64 (void); | |
3aee8918 | 36 | extern const struct target_desc *tdesc_aarch64; |
176eb98c | 37 | |
176eb98c MS |
38 | #ifdef HAVE_SYS_REG_H |
39 | #include <sys/reg.h> | |
40 | #endif | |
41 | ||
42 | #define AARCH64_X_REGS_NUM 31 | |
43 | #define AARCH64_V_REGS_NUM 32 | |
44 | #define AARCH64_X0_REGNO 0 | |
45 | #define AARCH64_SP_REGNO 31 | |
46 | #define AARCH64_PC_REGNO 32 | |
47 | #define AARCH64_CPSR_REGNO 33 | |
48 | #define AARCH64_V0_REGNO 34 | |
bf330350 CU |
49 | #define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM) |
50 | #define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1) | |
176eb98c | 51 | |
bf330350 | 52 | #define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2) |
176eb98c | 53 | |
176eb98c MS |
54 | /* Here starts the macro definitions, data structures, and code for |
55 | the hardware breakpoint and hardware watchpoint support. The | |
56 | following is the abbreviations that are used frequently in the code | |
57 | and comment: | |
58 | ||
59 | hw - hardware | |
60 | bp - breakpoint | |
61 | wp - watchpoint */ | |
62 | ||
63 | /* Maximum number of hardware breakpoint and watchpoint registers. | |
64 | Neither of these values may exceed the width of dr_changed_t | |
65 | measured in bits. */ | |
66 | ||
67 | #define AARCH64_HBP_MAX_NUM 16 | |
68 | #define AARCH64_HWP_MAX_NUM 16 | |
69 | ||
70 | /* Alignment requirement in bytes of hardware breakpoint and | |
71 | watchpoint address. This is the requirement for the addresses that | |
72 | can be written to the hardware breakpoint/watchpoint value | |
73 | registers. The kernel currently does not do any alignment on | |
74 | addresses when receiving a writing request (via ptrace call) to | |
75 | these debug registers, and it will reject any address that is | |
76 | unaligned. | |
77 | Some limited support has been provided in this gdbserver port for | |
78 | unaligned watchpoints, so that from a gdb user point of view, an | |
79 | unaligned watchpoint can still be set. This is achieved by | |
80 | minimally enlarging the watched area to meet the alignment | |
81 | requirement, and if necessary, splitting the watchpoint over | |
82 | several hardware watchpoint registers. */ | |
83 | ||
84 | #define AARCH64_HBP_ALIGNMENT 4 | |
85 | #define AARCH64_HWP_ALIGNMENT 8 | |
86 | ||
87 | /* The maximum length of a memory region that can be watched by one | |
88 | hardware watchpoint register. */ | |
89 | ||
90 | #define AARCH64_HWP_MAX_LEN_PER_REG 8 | |
91 | ||
92 | /* Each bit of a variable of this type is used to indicate whether a | |
93 | hardware breakpoint or watchpoint setting has been changed since | |
94 | the last updating. Bit N corresponds to the Nth hardware | |
95 | breakpoint or watchpoint setting which is managed in | |
96 | aarch64_debug_reg_state. Where N is valid between 0 and the total | |
97 | number of the hardware breakpoint or watchpoint debug registers | |
98 | minus 1. When the bit N is 1, it indicates the corresponding | |
99 | breakpoint or watchpoint setting is changed, and thus the | |
100 | corresponding hardware debug register needs to be updated via the | |
101 | ptrace interface. | |
102 | ||
103 | In the per-thread arch-specific data area, we define two such | |
104 | variables for per-thread hardware breakpoint and watchpoint | |
105 | settings respectively. | |
106 | ||
107 | This type is part of the mechanism which helps reduce the number of | |
108 | ptrace calls to the kernel, i.e. avoid asking the kernel to write | |
109 | to the debug registers with unchanged values. */ | |
110 | ||
111 | typedef unsigned long long dr_changed_t; | |
112 | ||
113 | /* Set each of the lower M bits of X to 1; assert X is wide enough. */ | |
114 | ||
115 | #define DR_MARK_ALL_CHANGED(x, m) \ | |
116 | do \ | |
117 | { \ | |
118 | gdb_assert (sizeof ((x)) * 8 >= (m)); \ | |
119 | (x) = (((dr_changed_t)1 << (m)) - 1); \ | |
120 | } while (0) | |
121 | ||
122 | #define DR_MARK_N_CHANGED(x, n) \ | |
123 | do \ | |
124 | { \ | |
125 | (x) |= ((dr_changed_t)1 << (n)); \ | |
126 | } while (0) | |
127 | ||
128 | #define DR_CLEAR_CHANGED(x) \ | |
129 | do \ | |
130 | { \ | |
131 | (x) = 0; \ | |
132 | } while (0) | |
133 | ||
134 | #define DR_HAS_CHANGED(x) ((x) != 0) | |
135 | #define DR_N_HAS_CHANGED(x, n) ((x) & ((dr_changed_t)1 << (n))) | |
136 | ||
137 | /* Structure for managing the hardware breakpoint/watchpoint resources. | |
138 | DR_ADDR_* stores the address, DR_CTRL_* stores the control register | |
139 | content, and DR_REF_COUNT_* counts the numbers of references to the | |
140 | corresponding bp/wp, by which way the limited hardware resources | |
141 | are not wasted on duplicated bp/wp settings (though so far gdb has | |
142 | done a good job by not sending duplicated bp/wp requests). */ | |
143 | ||
144 | struct aarch64_debug_reg_state | |
145 | { | |
146 | /* hardware breakpoint */ | |
147 | CORE_ADDR dr_addr_bp[AARCH64_HBP_MAX_NUM]; | |
148 | unsigned int dr_ctrl_bp[AARCH64_HBP_MAX_NUM]; | |
149 | unsigned int dr_ref_count_bp[AARCH64_HBP_MAX_NUM]; | |
150 | ||
151 | /* hardware watchpoint */ | |
152 | CORE_ADDR dr_addr_wp[AARCH64_HWP_MAX_NUM]; | |
153 | unsigned int dr_ctrl_wp[AARCH64_HWP_MAX_NUM]; | |
154 | unsigned int dr_ref_count_wp[AARCH64_HWP_MAX_NUM]; | |
155 | }; | |
156 | ||
157 | /* Per-process arch-specific data we want to keep. */ | |
158 | ||
159 | struct arch_process_info | |
160 | { | |
161 | /* Hardware breakpoint/watchpoint data. | |
162 | The reason for them to be per-process rather than per-thread is | |
163 | due to the lack of information in the gdbserver environment; | |
164 | gdbserver is not told that whether a requested hardware | |
165 | breakpoint/watchpoint is thread specific or not, so it has to set | |
166 | each hw bp/wp for every thread in the current process. The | |
167 | higher level bp/wp management in gdb will resume a thread if a hw | |
168 | bp/wp trap is not expected for it. Since the hw bp/wp setting is | |
169 | same for each thread, it is reasonable for the data to live here. | |
170 | */ | |
171 | struct aarch64_debug_reg_state debug_reg_state; | |
172 | }; | |
173 | ||
174 | /* Per-thread arch-specific data we want to keep. */ | |
175 | ||
176 | struct arch_lwp_info | |
177 | { | |
178 | /* When bit N is 1, it indicates the Nth hardware breakpoint or | |
179 | watchpoint register pair needs to be updated when the thread is | |
180 | resumed; see aarch64_linux_prepare_to_resume. */ | |
181 | dr_changed_t dr_changed_bp; | |
182 | dr_changed_t dr_changed_wp; | |
183 | }; | |
184 | ||
185 | /* Number of hardware breakpoints/watchpoints the target supports. | |
186 | They are initialized with values obtained via the ptrace calls | |
187 | with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively. */ | |
188 | ||
189 | static int aarch64_num_bp_regs; | |
190 | static int aarch64_num_wp_regs; | |
191 | ||
421530db PL |
192 | /* Implementation of linux_target_ops method "cannot_store_register". */ |
193 | ||
176eb98c MS |
194 | static int |
195 | aarch64_cannot_store_register (int regno) | |
196 | { | |
197 | return regno >= AARCH64_NUM_REGS; | |
198 | } | |
199 | ||
421530db PL |
200 | /* Implementation of linux_target_ops method "cannot_fetch_register". */ |
201 | ||
176eb98c MS |
202 | static int |
203 | aarch64_cannot_fetch_register (int regno) | |
204 | { | |
205 | return regno >= AARCH64_NUM_REGS; | |
206 | } | |
207 | ||
208 | static void | |
209 | aarch64_fill_gregset (struct regcache *regcache, void *buf) | |
210 | { | |
211 | struct user_pt_regs *regset = buf; | |
212 | int i; | |
213 | ||
214 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) | |
215 | collect_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); | |
216 | collect_register (regcache, AARCH64_SP_REGNO, ®set->sp); | |
217 | collect_register (regcache, AARCH64_PC_REGNO, ®set->pc); | |
218 | collect_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); | |
219 | } | |
220 | ||
221 | static void | |
222 | aarch64_store_gregset (struct regcache *regcache, const void *buf) | |
223 | { | |
224 | const struct user_pt_regs *regset = buf; | |
225 | int i; | |
226 | ||
227 | for (i = 0; i < AARCH64_X_REGS_NUM; i++) | |
228 | supply_register (regcache, AARCH64_X0_REGNO + i, ®set->regs[i]); | |
229 | supply_register (regcache, AARCH64_SP_REGNO, ®set->sp); | |
230 | supply_register (regcache, AARCH64_PC_REGNO, ®set->pc); | |
231 | supply_register (regcache, AARCH64_CPSR_REGNO, ®set->pstate); | |
232 | } | |
233 | ||
234 | static void | |
235 | aarch64_fill_fpregset (struct regcache *regcache, void *buf) | |
236 | { | |
237 | struct user_fpsimd_state *regset = buf; | |
238 | int i; | |
239 | ||
240 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) | |
241 | collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); | |
bf330350 CU |
242 | collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); |
243 | collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); | |
176eb98c MS |
244 | } |
245 | ||
246 | static void | |
247 | aarch64_store_fpregset (struct regcache *regcache, const void *buf) | |
248 | { | |
249 | const struct user_fpsimd_state *regset = buf; | |
250 | int i; | |
251 | ||
252 | for (i = 0; i < AARCH64_V_REGS_NUM; i++) | |
253 | supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]); | |
bf330350 CU |
254 | supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr); |
255 | supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr); | |
176eb98c MS |
256 | } |
257 | ||
176eb98c MS |
258 | /* Enable miscellaneous debugging output. The name is historical - it |
259 | was originally used to debug LinuxThreads support. */ | |
260 | extern int debug_threads; | |
261 | ||
421530db PL |
262 | /* Implementation of linux_target_ops method "get_pc". */ |
263 | ||
176eb98c MS |
264 | static CORE_ADDR |
265 | aarch64_get_pc (struct regcache *regcache) | |
266 | { | |
267 | unsigned long pc; | |
268 | ||
269 | collect_register_by_name (regcache, "pc", &pc); | |
270 | if (debug_threads) | |
87ce2a04 | 271 | debug_printf ("stop pc is %08lx\n", pc); |
176eb98c MS |
272 | return pc; |
273 | } | |
274 | ||
421530db PL |
275 | /* Implementation of linux_target_ops method "set_pc". */ |
276 | ||
176eb98c MS |
277 | static void |
278 | aarch64_set_pc (struct regcache *regcache, CORE_ADDR pc) | |
279 | { | |
280 | unsigned long newpc = pc; | |
281 | supply_register_by_name (regcache, "pc", &newpc); | |
282 | } | |
283 | ||
176eb98c MS |
284 | #define aarch64_breakpoint_len 4 |
285 | ||
37d66942 PL |
286 | /* AArch64 BRK software debug mode instruction. |
287 | This instruction needs to match gdb/aarch64-tdep.c | |
288 | (aarch64_default_breakpoint). */ | |
289 | static const gdb_byte aarch64_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; | |
176eb98c | 290 | |
421530db PL |
291 | /* Implementation of linux_target_ops method "breakpoint_at". */ |
292 | ||
176eb98c MS |
293 | static int |
294 | aarch64_breakpoint_at (CORE_ADDR where) | |
295 | { | |
37d66942 | 296 | gdb_byte insn[aarch64_breakpoint_len]; |
176eb98c | 297 | |
37d66942 PL |
298 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
299 | aarch64_breakpoint_len); | |
300 | if (memcmp (insn, aarch64_breakpoint, aarch64_breakpoint_len) == 0) | |
176eb98c MS |
301 | return 1; |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | /* Print the values of the cached breakpoint/watchpoint registers. | |
307 | This is enabled via the "set debug-hw-points" monitor command. */ | |
308 | ||
309 | static void | |
310 | aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state, | |
311 | const char *func, CORE_ADDR addr, | |
4ff0d3d8 | 312 | int len, enum target_hw_bp_type type) |
176eb98c MS |
313 | { |
314 | int i; | |
315 | ||
316 | fprintf (stderr, "%s", func); | |
317 | if (addr || len) | |
318 | fprintf (stderr, " (addr=0x%08lx, len=%d, type=%s)", | |
319 | (unsigned long) addr, len, | |
320 | type == hw_write ? "hw-write-watchpoint" | |
321 | : (type == hw_read ? "hw-read-watchpoint" | |
322 | : (type == hw_access ? "hw-access-watchpoint" | |
323 | : (type == hw_execute ? "hw-breakpoint" | |
324 | : "??unknown??")))); | |
325 | fprintf (stderr, ":\n"); | |
326 | ||
327 | fprintf (stderr, "\tBREAKPOINTs:\n"); | |
328 | for (i = 0; i < aarch64_num_bp_regs; i++) | |
329 | fprintf (stderr, "\tBP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", | |
330 | i, paddress (state->dr_addr_bp[i]), | |
331 | state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]); | |
332 | ||
333 | fprintf (stderr, "\tWATCHPOINTs:\n"); | |
334 | for (i = 0; i < aarch64_num_wp_regs; i++) | |
335 | fprintf (stderr, "\tWP%d: addr=0x%s, ctrl=0x%08x, ref.count=%d\n", | |
336 | i, paddress (state->dr_addr_wp[i]), | |
337 | state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]); | |
338 | } | |
339 | ||
340 | static void | |
341 | aarch64_init_debug_reg_state (struct aarch64_debug_reg_state *state) | |
342 | { | |
343 | int i; | |
344 | ||
345 | for (i = 0; i < AARCH64_HBP_MAX_NUM; ++i) | |
346 | { | |
347 | state->dr_addr_bp[i] = 0; | |
348 | state->dr_ctrl_bp[i] = 0; | |
349 | state->dr_ref_count_bp[i] = 0; | |
350 | } | |
351 | ||
352 | for (i = 0; i < AARCH64_HWP_MAX_NUM; ++i) | |
353 | { | |
354 | state->dr_addr_wp[i] = 0; | |
355 | state->dr_ctrl_wp[i] = 0; | |
356 | state->dr_ref_count_wp[i] = 0; | |
357 | } | |
358 | } | |
359 | ||
360 | /* ptrace expects control registers to be formatted as follows: | |
361 | ||
362 | 31 13 5 3 1 0 | |
363 | +--------------------------------+----------+------+------+----+ | |
364 | | RESERVED (SBZ) | LENGTH | TYPE | PRIV | EN | | |
365 | +--------------------------------+----------+------+------+----+ | |
366 | ||
367 | The TYPE field is ignored for breakpoints. */ | |
368 | ||
369 | #define DR_CONTROL_ENABLED(ctrl) (((ctrl) & 0x1) == 1) | |
370 | #define DR_CONTROL_LENGTH(ctrl) (((ctrl) >> 5) & 0xff) | |
371 | ||
372 | /* Utility function that returns the length in bytes of a watchpoint | |
373 | according to the content of a hardware debug control register CTRL. | |
374 | Note that the kernel currently only supports the following Byte | |
375 | Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means | |
376 | that for a hardware watchpoint, its valid length can only be 1 | |
377 | byte, 2 bytes, 4 bytes or 8 bytes. */ | |
378 | ||
379 | static inline unsigned int | |
380 | aarch64_watchpoint_length (unsigned int ctrl) | |
381 | { | |
382 | switch (DR_CONTROL_LENGTH (ctrl)) | |
383 | { | |
384 | case 0x01: | |
385 | return 1; | |
386 | case 0x03: | |
387 | return 2; | |
388 | case 0x0f: | |
389 | return 4; | |
390 | case 0xff: | |
391 | return 8; | |
392 | default: | |
393 | return 0; | |
394 | } | |
395 | } | |
396 | ||
397 | /* Given the hardware breakpoint or watchpoint type TYPE and its | |
398 | length LEN, return the expected encoding for a hardware | |
399 | breakpoint/watchpoint control register. */ | |
400 | ||
401 | static unsigned int | |
4ff0d3d8 | 402 | aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len) |
176eb98c | 403 | { |
4ff0d3d8 | 404 | unsigned int ctrl, ttype; |
176eb98c MS |
405 | |
406 | /* type */ | |
4ff0d3d8 PA |
407 | switch (type) |
408 | { | |
409 | case hw_write: | |
410 | ttype = 2; | |
411 | break; | |
412 | case hw_read: | |
413 | ttype = 1; | |
414 | break; | |
415 | case hw_access: | |
416 | ttype = 3; | |
417 | break; | |
418 | case hw_execute: | |
419 | ttype = 0; | |
420 | break; | |
421 | default: | |
422 | perror_with_name (_("Unrecognized breakpoint/watchpoint type")); | |
423 | } | |
424 | ||
425 | /* type */ | |
426 | ctrl = ttype << 3; | |
176eb98c MS |
427 | /* length bitmask */ |
428 | ctrl |= ((1 << len) - 1) << 5; | |
429 | /* enabled at el0 */ | |
430 | ctrl |= (2 << 1) | 1; | |
431 | ||
432 | return ctrl; | |
433 | } | |
434 | ||
435 | /* Addresses to be written to the hardware breakpoint and watchpoint | |
436 | value registers need to be aligned; the alignment is 4-byte and | |
437 | 8-type respectively. Linux kernel rejects any non-aligned address | |
438 | it receives from the related ptrace call. Furthermore, the kernel | |
439 | currently only supports the following Byte Address Select (BAS) | |
440 | values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware | |
441 | watchpoint to be accepted by the kernel (via ptrace call), its | |
442 | valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes. | |
443 | Despite these limitations, the unaligned watchpoint is supported in | |
444 | this gdbserver port. | |
445 | ||
446 | Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise. */ | |
447 | ||
448 | static int | |
449 | aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len) | |
450 | { | |
451 | unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT | |
452 | : AARCH64_HBP_ALIGNMENT; | |
453 | ||
454 | if (addr & (alignment - 1)) | |
455 | return 0; | |
456 | ||
457 | if (len != 8 && len != 4 && len != 2 && len != 1) | |
458 | return 0; | |
459 | ||
460 | return 1; | |
461 | } | |
462 | ||
463 | /* Given the (potentially unaligned) watchpoint address in ADDR and | |
464 | length in LEN, return the aligned address and aligned length in | |
465 | *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively. The returned | |
466 | aligned address and length will be valid to be written to the | |
467 | hardware watchpoint value and control registers. See the comment | |
468 | above aarch64_point_is_aligned for the information about the | |
469 | alignment requirement. The given watchpoint may get truncated if | |
470 | more than one hardware register is needed to cover the watched | |
471 | region. *NEXT_ADDR_P and *NEXT_LEN_P, if non-NULL, will return the | |
472 | address and length of the remaining part of the watchpoint (which | |
473 | can be processed by calling this routine again to generate another | |
474 | aligned address and length pair. | |
475 | ||
476 | Essentially, unaligned watchpoint is achieved by minimally | |
477 | enlarging the watched area to meet the alignment requirement, and | |
478 | if necessary, splitting the watchpoint over several hardware | |
479 | watchpoint registers. The trade-off is that there will be | |
480 | false-positive hits for the read-type or the access-type hardware | |
481 | watchpoints; for the write type, which is more commonly used, there | |
482 | will be no such issues, as the higher-level breakpoint management | |
483 | in gdb always examines the exact watched region for any content | |
484 | change, and transparently resumes a thread from a watchpoint trap | |
485 | if there is no change to the watched region. | |
486 | ||
487 | Another limitation is that because the watched region is enlarged, | |
488 | the watchpoint fault address returned by | |
489 | aarch64_stopped_data_address may be outside of the original watched | |
490 | region, especially when the triggering instruction is accessing a | |
491 | larger region. When the fault address is not within any known | |
492 | range, watchpoints_triggered in gdb will get confused, as the | |
493 | higher-level watchpoint management is only aware of original | |
494 | watched regions, and will think that some unknown watchpoint has | |
495 | been triggered. In such a case, gdb may stop without displaying | |
496 | any detailed information. | |
497 | ||
498 | Once the kernel provides the full support for Byte Address Select | |
499 | (BAS) in the hardware watchpoint control register, these | |
500 | limitations can be largely relaxed with some further work. */ | |
501 | ||
502 | static void | |
503 | aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p, | |
504 | int *aligned_len_p, CORE_ADDR *next_addr_p, | |
505 | int *next_len_p) | |
506 | { | |
507 | int aligned_len; | |
508 | unsigned int offset; | |
509 | CORE_ADDR aligned_addr; | |
510 | const unsigned int alignment = AARCH64_HWP_ALIGNMENT; | |
511 | const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG; | |
512 | ||
513 | /* As assumed by the algorithm. */ | |
514 | gdb_assert (alignment == max_wp_len); | |
515 | ||
516 | if (len <= 0) | |
517 | return; | |
518 | ||
519 | /* Address to be put into the hardware watchpoint value register | |
520 | must be aligned. */ | |
521 | offset = addr & (alignment - 1); | |
522 | aligned_addr = addr - offset; | |
523 | ||
524 | gdb_assert (offset >= 0 && offset < alignment); | |
525 | gdb_assert (aligned_addr >= 0 && aligned_addr <= addr); | |
526 | gdb_assert ((offset + len) > 0); | |
527 | ||
528 | if (offset + len >= max_wp_len) | |
529 | { | |
530 | /* Need more than one watchpoint registers; truncate it at the | |
531 | alignment boundary. */ | |
532 | aligned_len = max_wp_len; | |
533 | len -= (max_wp_len - offset); | |
534 | addr += (max_wp_len - offset); | |
535 | gdb_assert ((addr & (alignment - 1)) == 0); | |
536 | } | |
537 | else | |
538 | { | |
539 | /* Find the smallest valid length that is large enough to | |
540 | accommodate this watchpoint. */ | |
541 | static const unsigned char | |
542 | aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] = | |
543 | { 1, 2, 4, 4, 8, 8, 8, 8 }; | |
544 | ||
545 | aligned_len = aligned_len_array[offset + len - 1]; | |
546 | addr += len; | |
547 | len = 0; | |
548 | } | |
549 | ||
550 | if (aligned_addr_p != NULL) | |
551 | *aligned_addr_p = aligned_addr; | |
552 | if (aligned_len_p != NULL) | |
553 | *aligned_len_p = aligned_len; | |
554 | if (next_addr_p != NULL) | |
555 | *next_addr_p = addr; | |
556 | if (next_len_p != NULL) | |
557 | *next_len_p = len; | |
558 | } | |
559 | ||
560 | /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint | |
561 | registers with data from *STATE. */ | |
562 | ||
563 | static void | |
564 | aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state, | |
565 | int tid, int watchpoint) | |
566 | { | |
567 | int i, count; | |
568 | struct iovec iov; | |
569 | struct user_hwdebug_state regs; | |
570 | const CORE_ADDR *addr; | |
571 | const unsigned int *ctrl; | |
572 | ||
c623a6ef | 573 | memset (®s, 0, sizeof (regs)); |
176eb98c | 574 | iov.iov_base = ®s; |
176eb98c MS |
575 | count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs; |
576 | addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp; | |
577 | ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp; | |
f45c82da YZ |
578 | if (count == 0) |
579 | return; | |
580 | iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1]) | |
581 | + sizeof (regs.dbg_regs [count - 1])); | |
176eb98c MS |
582 | |
583 | for (i = 0; i < count; i++) | |
584 | { | |
585 | regs.dbg_regs[i].addr = addr[i]; | |
586 | regs.dbg_regs[i].ctrl = ctrl[i]; | |
587 | } | |
588 | ||
589 | if (ptrace (PTRACE_SETREGSET, tid, | |
590 | watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK, | |
591 | (void *) &iov)) | |
592 | error (_("Unexpected error setting hardware debug registers")); | |
593 | } | |
594 | ||
595 | struct aarch64_dr_update_callback_param | |
596 | { | |
597 | int pid; | |
598 | int is_watchpoint; | |
599 | unsigned int idx; | |
600 | }; | |
601 | ||
602 | /* Callback function which records the information about the change of | |
603 | one hardware breakpoint/watchpoint setting for the thread ENTRY. | |
604 | The information is passed in via PTR. | |
605 | N.B. The actual updating of hardware debug registers is not | |
606 | carried out until the moment the thread is resumed. */ | |
607 | ||
608 | static int | |
609 | debug_reg_change_callback (struct inferior_list_entry *entry, void *ptr) | |
610 | { | |
d86d4aaf DE |
611 | struct thread_info *thread = (struct thread_info *) entry; |
612 | struct lwp_info *lwp = get_thread_lwp (thread); | |
176eb98c MS |
613 | struct aarch64_dr_update_callback_param *param_p |
614 | = (struct aarch64_dr_update_callback_param *) ptr; | |
615 | int pid = param_p->pid; | |
616 | int idx = param_p->idx; | |
617 | int is_watchpoint = param_p->is_watchpoint; | |
618 | struct arch_lwp_info *info = lwp->arch_private; | |
619 | dr_changed_t *dr_changed_ptr; | |
620 | dr_changed_t dr_changed; | |
621 | ||
c5e92cca | 622 | if (show_debug_regs) |
176eb98c MS |
623 | { |
624 | fprintf (stderr, "debug_reg_change_callback: \n\tOn entry:\n"); | |
625 | fprintf (stderr, "\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " | |
626 | "dr_changed_wp=0x%llx\n", | |
d86d4aaf | 627 | pid, lwpid_of (thread), info->dr_changed_bp, |
176eb98c MS |
628 | info->dr_changed_wp); |
629 | } | |
630 | ||
631 | dr_changed_ptr = is_watchpoint ? &info->dr_changed_wp | |
632 | : &info->dr_changed_bp; | |
633 | dr_changed = *dr_changed_ptr; | |
634 | ||
635 | /* Only update the threads of this process. */ | |
d86d4aaf | 636 | if (pid_of (thread) == pid) |
176eb98c MS |
637 | { |
638 | gdb_assert (idx >= 0 | |
639 | && (idx <= (is_watchpoint ? aarch64_num_wp_regs | |
640 | : aarch64_num_bp_regs))); | |
641 | ||
642 | /* The following assertion is not right, as there can be changes | |
643 | that have not been made to the hardware debug registers | |
644 | before new changes overwrite the old ones. This can happen, | |
645 | for instance, when the breakpoint/watchpoint hit one of the | |
646 | threads and the user enters continue; then what happens is: | |
647 | 1) all breakpoints/watchpoints are removed for all threads; | |
648 | 2) a single step is carried out for the thread that was hit; | |
649 | 3) all of the points are inserted again for all threads; | |
650 | 4) all threads are resumed. | |
651 | The 2nd step will only affect the one thread in which the | |
652 | bp/wp was hit, which means only that one thread is resumed; | |
653 | remember that the actual updating only happen in | |
654 | aarch64_linux_prepare_to_resume, so other threads remain | |
655 | stopped during the removal and insertion of bp/wp. Therefore | |
656 | for those threads, the change of insertion of the bp/wp | |
657 | overwrites that of the earlier removals. (The situation may | |
658 | be different when bp/wp is steppable, or in the non-stop | |
659 | mode.) */ | |
660 | /* gdb_assert (DR_N_HAS_CHANGED (dr_changed, idx) == 0); */ | |
661 | ||
662 | /* The actual update is done later just before resuming the lwp, | |
663 | we just mark that one register pair needs updating. */ | |
664 | DR_MARK_N_CHANGED (dr_changed, idx); | |
665 | *dr_changed_ptr = dr_changed; | |
666 | ||
667 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
668 | we can update its debug registers. */ | |
669 | if (!lwp->stopped) | |
670 | linux_stop_lwp (lwp); | |
671 | } | |
672 | ||
c5e92cca | 673 | if (show_debug_regs) |
176eb98c MS |
674 | { |
675 | fprintf (stderr, "\tOn exit:\n\tpid%d, tid: %ld, dr_changed_bp=0x%llx, " | |
676 | "dr_changed_wp=0x%llx\n", | |
d86d4aaf DE |
677 | pid, lwpid_of (thread), info->dr_changed_bp, |
678 | info->dr_changed_wp); | |
176eb98c MS |
679 | } |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | /* Notify each thread that their IDXth breakpoint/watchpoint register | |
685 | pair needs to be updated. The message will be recorded in each | |
686 | thread's arch-specific data area, the actual updating will be done | |
687 | when the thread is resumed. */ | |
688 | ||
689 | void | |
690 | aarch64_notify_debug_reg_change (const struct aarch64_debug_reg_state *state, | |
691 | int is_watchpoint, unsigned int idx) | |
692 | { | |
693 | struct aarch64_dr_update_callback_param param; | |
694 | ||
695 | /* Only update the threads of this process. */ | |
0bfdf32f | 696 | param.pid = pid_of (current_thread); |
176eb98c MS |
697 | |
698 | param.is_watchpoint = is_watchpoint; | |
699 | param.idx = idx; | |
700 | ||
d86d4aaf | 701 | find_inferior (&all_threads, debug_reg_change_callback, (void *) ¶m); |
176eb98c MS |
702 | } |
703 | ||
704 | ||
705 | /* Return the pointer to the debug register state structure in the | |
706 | current process' arch-specific data area. */ | |
707 | ||
708 | static struct aarch64_debug_reg_state * | |
709 | aarch64_get_debug_reg_state () | |
710 | { | |
711 | struct process_info *proc; | |
712 | ||
713 | proc = current_process (); | |
fe978cb0 | 714 | return &proc->priv->arch_private->debug_reg_state; |
176eb98c MS |
715 | } |
716 | ||
717 | /* Record the insertion of one breakpoint/watchpoint, as represented | |
718 | by ADDR and CTRL, in the process' arch-specific data area *STATE. */ | |
719 | ||
720 | static int | |
721 | aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state, | |
4ff0d3d8 | 722 | enum target_hw_bp_type type, |
176eb98c MS |
723 | CORE_ADDR addr, int len) |
724 | { | |
725 | int i, idx, num_regs, is_watchpoint; | |
726 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
727 | CORE_ADDR *dr_addr_p; | |
728 | ||
729 | /* Set up state pointers. */ | |
730 | is_watchpoint = (type != hw_execute); | |
731 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
732 | if (is_watchpoint) | |
733 | { | |
734 | num_regs = aarch64_num_wp_regs; | |
735 | dr_addr_p = state->dr_addr_wp; | |
736 | dr_ctrl_p = state->dr_ctrl_wp; | |
737 | dr_ref_count = state->dr_ref_count_wp; | |
738 | } | |
739 | else | |
740 | { | |
741 | num_regs = aarch64_num_bp_regs; | |
742 | dr_addr_p = state->dr_addr_bp; | |
743 | dr_ctrl_p = state->dr_ctrl_bp; | |
744 | dr_ref_count = state->dr_ref_count_bp; | |
745 | } | |
746 | ||
747 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
748 | ||
749 | /* Find an existing or free register in our cache. */ | |
750 | idx = -1; | |
751 | for (i = 0; i < num_regs; ++i) | |
752 | { | |
753 | if ((dr_ctrl_p[i] & 1) == 0) | |
754 | { | |
755 | gdb_assert (dr_ref_count[i] == 0); | |
756 | idx = i; | |
757 | /* no break; continue hunting for an exising one. */ | |
758 | } | |
759 | else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
760 | { | |
761 | gdb_assert (dr_ref_count[i] != 0); | |
762 | idx = i; | |
763 | break; | |
764 | } | |
765 | } | |
766 | ||
767 | /* No space. */ | |
768 | if (idx == -1) | |
769 | return -1; | |
770 | ||
771 | /* Update our cache. */ | |
772 | if ((dr_ctrl_p[idx] & 1) == 0) | |
773 | { | |
774 | /* new entry */ | |
775 | dr_addr_p[idx] = addr; | |
776 | dr_ctrl_p[idx] = ctrl; | |
777 | dr_ref_count[idx] = 1; | |
778 | /* Notify the change. */ | |
779 | aarch64_notify_debug_reg_change (state, is_watchpoint, idx); | |
780 | } | |
781 | else | |
782 | { | |
783 | /* existing entry */ | |
784 | dr_ref_count[idx]++; | |
785 | } | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | /* Record the removal of one breakpoint/watchpoint, as represented by | |
791 | ADDR and CTRL, in the process' arch-specific data area *STATE. */ | |
792 | ||
793 | static int | |
794 | aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state, | |
4ff0d3d8 | 795 | enum target_hw_bp_type type, |
176eb98c MS |
796 | CORE_ADDR addr, int len) |
797 | { | |
798 | int i, num_regs, is_watchpoint; | |
799 | unsigned int ctrl, *dr_ctrl_p, *dr_ref_count; | |
800 | CORE_ADDR *dr_addr_p; | |
801 | ||
802 | /* Set up state pointers. */ | |
803 | is_watchpoint = (type != hw_execute); | |
804 | gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len)); | |
805 | if (is_watchpoint) | |
806 | { | |
807 | num_regs = aarch64_num_wp_regs; | |
808 | dr_addr_p = state->dr_addr_wp; | |
809 | dr_ctrl_p = state->dr_ctrl_wp; | |
810 | dr_ref_count = state->dr_ref_count_wp; | |
811 | } | |
812 | else | |
813 | { | |
814 | num_regs = aarch64_num_bp_regs; | |
815 | dr_addr_p = state->dr_addr_bp; | |
816 | dr_ctrl_p = state->dr_ctrl_bp; | |
817 | dr_ref_count = state->dr_ref_count_bp; | |
818 | } | |
819 | ||
820 | ctrl = aarch64_point_encode_ctrl_reg (type, len); | |
821 | ||
822 | /* Find the entry that matches the ADDR and CTRL. */ | |
823 | for (i = 0; i < num_regs; ++i) | |
824 | if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl) | |
825 | { | |
826 | gdb_assert (dr_ref_count[i] != 0); | |
827 | break; | |
828 | } | |
829 | ||
830 | /* Not found. */ | |
831 | if (i == num_regs) | |
832 | return -1; | |
833 | ||
834 | /* Clear our cache. */ | |
835 | if (--dr_ref_count[i] == 0) | |
836 | { | |
837 | /* Clear the enable bit. */ | |
838 | ctrl &= ~1; | |
839 | dr_addr_p[i] = 0; | |
840 | dr_ctrl_p[i] = ctrl; | |
841 | /* Notify the change. */ | |
842 | aarch64_notify_debug_reg_change (state, is_watchpoint, i); | |
843 | } | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | static int | |
4ff0d3d8 | 849 | aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
176eb98c MS |
850 | int len, int is_insert) |
851 | { | |
852 | struct aarch64_debug_reg_state *state; | |
853 | ||
854 | /* The hardware breakpoint on AArch64 should always be 4-byte | |
855 | aligned. */ | |
856 | if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len)) | |
857 | return -1; | |
858 | ||
859 | state = aarch64_get_debug_reg_state (); | |
860 | ||
861 | if (is_insert) | |
862 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
863 | else | |
864 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
865 | } | |
866 | ||
867 | /* This is essentially the same as aarch64_handle_breakpoint, apart | |
868 | from that it is an aligned watchpoint to be handled. */ | |
869 | ||
870 | static int | |
4ff0d3d8 | 871 | aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type, |
176eb98c MS |
872 | CORE_ADDR addr, int len, int is_insert) |
873 | { | |
874 | struct aarch64_debug_reg_state *state; | |
875 | ||
876 | state = aarch64_get_debug_reg_state (); | |
877 | ||
878 | if (is_insert) | |
879 | return aarch64_dr_state_insert_one_point (state, type, addr, len); | |
880 | else | |
881 | return aarch64_dr_state_remove_one_point (state, type, addr, len); | |
882 | } | |
883 | ||
884 | /* Insert/remove unaligned watchpoint by calling | |
885 | aarch64_align_watchpoint repeatedly until the whole watched region, | |
886 | as represented by ADDR and LEN, has been properly aligned and ready | |
887 | to be written to one or more hardware watchpoint registers. | |
888 | IS_INSERT indicates whether this is an insertion or a deletion. | |
889 | Return 0 if succeed. */ | |
890 | ||
891 | static int | |
4ff0d3d8 | 892 | aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type, |
176eb98c MS |
893 | CORE_ADDR addr, int len, int is_insert) |
894 | { | |
895 | struct aarch64_debug_reg_state *state | |
896 | = aarch64_get_debug_reg_state (); | |
897 | ||
898 | while (len > 0) | |
899 | { | |
900 | CORE_ADDR aligned_addr; | |
901 | int aligned_len, ret; | |
902 | ||
903 | aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len, | |
904 | &addr, &len); | |
905 | ||
906 | if (is_insert) | |
907 | ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr, | |
908 | aligned_len); | |
909 | else | |
910 | ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr, | |
911 | aligned_len); | |
912 | ||
c5e92cca | 913 | if (show_debug_regs) |
176eb98c MS |
914 | fprintf (stderr, |
915 | "handle_unaligned_watchpoint: is_insert: %d\n" | |
916 | " aligned_addr: 0x%s, aligned_len: %d\n" | |
917 | " next_addr: 0x%s, next_len: %d\n", | |
918 | is_insert, paddress (aligned_addr), aligned_len, | |
919 | paddress (addr), len); | |
920 | ||
921 | if (ret != 0) | |
922 | return ret; | |
923 | } | |
924 | ||
925 | return 0; | |
926 | } | |
927 | ||
928 | static int | |
4ff0d3d8 | 929 | aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr, |
176eb98c MS |
930 | int len, int is_insert) |
931 | { | |
932 | if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len)) | |
933 | return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert); | |
934 | else | |
935 | return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert); | |
936 | } | |
937 | ||
421530db PL |
938 | /* Implementation of linux_target_ops method "supports_z_point_type". */ |
939 | ||
4ff0d3d8 PA |
940 | static int |
941 | aarch64_supports_z_point_type (char z_type) | |
942 | { | |
943 | switch (z_type) | |
944 | { | |
96c97461 | 945 | case Z_PACKET_SW_BP: |
4ff0d3d8 PA |
946 | case Z_PACKET_HW_BP: |
947 | case Z_PACKET_WRITE_WP: | |
948 | case Z_PACKET_READ_WP: | |
949 | case Z_PACKET_ACCESS_WP: | |
950 | return 1; | |
951 | default: | |
4ff0d3d8 PA |
952 | return 0; |
953 | } | |
954 | } | |
955 | ||
421530db | 956 | /* Implementation of linux_target_ops method "insert_point". |
176eb98c | 957 | |
421530db PL |
958 | It actually only records the info of the to-be-inserted bp/wp; |
959 | the actual insertion will happen when threads are resumed. */ | |
176eb98c MS |
960 | |
961 | static int | |
802e8e6d PA |
962 | aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
963 | int len, struct raw_breakpoint *bp) | |
176eb98c MS |
964 | { |
965 | int ret; | |
4ff0d3d8 PA |
966 | enum target_hw_bp_type targ_type; |
967 | ||
c5e92cca | 968 | if (show_debug_regs) |
176eb98c MS |
969 | fprintf (stderr, "insert_point on entry (addr=0x%08lx, len=%d)\n", |
970 | (unsigned long) addr, len); | |
971 | ||
802e8e6d PA |
972 | /* Determine the type from the raw breakpoint type. */ |
973 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); | |
176eb98c MS |
974 | |
975 | if (targ_type != hw_execute) | |
976 | ret = | |
977 | aarch64_handle_watchpoint (targ_type, addr, len, 1 /* is_insert */); | |
978 | else | |
979 | ret = | |
980 | aarch64_handle_breakpoint (targ_type, addr, len, 1 /* is_insert */); | |
981 | ||
60a191ed | 982 | if (show_debug_regs) |
176eb98c MS |
983 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
984 | "insert_point", addr, len, targ_type); | |
985 | ||
986 | return ret; | |
987 | } | |
988 | ||
421530db | 989 | /* Implementation of linux_target_ops method "remove_point". |
176eb98c | 990 | |
421530db PL |
991 | It actually only records the info of the to-be-removed bp/wp, |
992 | the actual removal will be done when threads are resumed. */ | |
176eb98c MS |
993 | |
994 | static int | |
802e8e6d PA |
995 | aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
996 | int len, struct raw_breakpoint *bp) | |
176eb98c MS |
997 | { |
998 | int ret; | |
4ff0d3d8 PA |
999 | enum target_hw_bp_type targ_type; |
1000 | ||
c5e92cca | 1001 | if (show_debug_regs) |
176eb98c MS |
1002 | fprintf (stderr, "remove_point on entry (addr=0x%08lx, len=%d)\n", |
1003 | (unsigned long) addr, len); | |
1004 | ||
802e8e6d PA |
1005 | /* Determine the type from the raw breakpoint type. */ |
1006 | targ_type = raw_bkpt_type_to_target_hw_bp_type (type); | |
176eb98c MS |
1007 | |
1008 | /* Set up state pointers. */ | |
1009 | if (targ_type != hw_execute) | |
1010 | ret = | |
1011 | aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */); | |
1012 | else | |
1013 | ret = | |
1014 | aarch64_handle_breakpoint (targ_type, addr, len, 0 /* is_insert */); | |
1015 | ||
60a191ed | 1016 | if (show_debug_regs) |
176eb98c MS |
1017 | aarch64_show_debug_reg_state (aarch64_get_debug_reg_state (), |
1018 | "remove_point", addr, len, targ_type); | |
1019 | ||
1020 | return ret; | |
1021 | } | |
1022 | ||
421530db | 1023 | /* Implementation of linux_target_ops method "stopped_data_address". */ |
176eb98c MS |
1024 | |
1025 | static CORE_ADDR | |
1026 | aarch64_stopped_data_address (void) | |
1027 | { | |
1028 | siginfo_t siginfo; | |
1029 | int pid, i; | |
1030 | struct aarch64_debug_reg_state *state; | |
1031 | ||
0bfdf32f | 1032 | pid = lwpid_of (current_thread); |
176eb98c MS |
1033 | |
1034 | /* Get the siginfo. */ | |
1035 | if (ptrace (PTRACE_GETSIGINFO, pid, NULL, &siginfo) != 0) | |
1036 | return (CORE_ADDR) 0; | |
1037 | ||
1038 | /* Need to be a hardware breakpoint/watchpoint trap. */ | |
1039 | if (siginfo.si_signo != SIGTRAP | |
1040 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
1041 | return (CORE_ADDR) 0; | |
1042 | ||
1043 | /* Check if the address matches any watched address. */ | |
1044 | state = aarch64_get_debug_reg_state (); | |
1045 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) | |
1046 | { | |
1047 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); | |
1048 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
1049 | const CORE_ADDR addr_watch = state->dr_addr_wp[i]; | |
1050 | if (state->dr_ref_count_wp[i] | |
1051 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
1052 | && addr_trap >= addr_watch | |
1053 | && addr_trap < addr_watch + len) | |
1054 | return addr_trap; | |
1055 | } | |
1056 | ||
1057 | return (CORE_ADDR) 0; | |
1058 | } | |
1059 | ||
421530db | 1060 | /* Implementation of linux_target_ops method "stopped_by_watchpoint". */ |
176eb98c MS |
1061 | |
1062 | static int | |
1063 | aarch64_stopped_by_watchpoint (void) | |
1064 | { | |
1065 | if (aarch64_stopped_data_address () != 0) | |
1066 | return 1; | |
1067 | else | |
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | /* Fetch the thread-local storage pointer for libthread_db. */ | |
1072 | ||
1073 | ps_err_e | |
55fac6e0 | 1074 | ps_get_thread_area (const struct ps_prochandle *ph, |
176eb98c MS |
1075 | lwpid_t lwpid, int idx, void **base) |
1076 | { | |
55fac6e0 MS |
1077 | struct iovec iovec; |
1078 | uint64_t reg; | |
1079 | ||
1080 | iovec.iov_base = ® | |
1081 | iovec.iov_len = sizeof (reg); | |
1082 | ||
1083 | if (ptrace (PTRACE_GETREGSET, lwpid, NT_ARM_TLS, &iovec) != 0) | |
176eb98c MS |
1084 | return PS_ERR; |
1085 | ||
1086 | /* IDX is the bias from the thread pointer to the beginning of the | |
1087 | thread descriptor. It has to be subtracted due to implementation | |
1088 | quirks in libthread_db. */ | |
55fac6e0 | 1089 | *base = (void *) (reg - idx); |
176eb98c MS |
1090 | |
1091 | return PS_OK; | |
1092 | } | |
1093 | ||
421530db | 1094 | /* Implementation of linux_target_ops method "linux_new_process". */ |
176eb98c MS |
1095 | |
1096 | static struct arch_process_info * | |
1097 | aarch64_linux_new_process (void) | |
1098 | { | |
1099 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); | |
1100 | ||
1101 | aarch64_init_debug_reg_state (&info->debug_reg_state); | |
1102 | ||
1103 | return info; | |
1104 | } | |
1105 | ||
421530db | 1106 | /* Implementation of linux_target_ops method "linux_new_thread". */ |
176eb98c | 1107 | |
34c703da GB |
1108 | static void |
1109 | aarch64_linux_new_thread (struct lwp_info *lwp) | |
176eb98c MS |
1110 | { |
1111 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); | |
1112 | ||
1113 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1114 | for this thread need to be initialized (with data from | |
1115 | aarch_process_info.debug_reg_state). */ | |
1116 | DR_MARK_ALL_CHANGED (info->dr_changed_bp, aarch64_num_bp_regs); | |
1117 | DR_MARK_ALL_CHANGED (info->dr_changed_wp, aarch64_num_wp_regs); | |
1118 | ||
34c703da | 1119 | lwp->arch_private = info; |
176eb98c MS |
1120 | } |
1121 | ||
421530db PL |
1122 | /* Implementation of linux_target_ops method "linux_new_fork". */ |
1123 | ||
3a8a0396 DB |
1124 | static void |
1125 | aarch64_linux_new_fork (struct process_info *parent, | |
1126 | struct process_info *child) | |
1127 | { | |
1128 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
1129 | gdb_assert (parent->priv != NULL |
1130 | && parent->priv->arch_private != NULL); | |
1131 | gdb_assert (child->priv != NULL | |
1132 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
1133 | |
1134 | /* Linux kernel before 2.6.33 commit | |
1135 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
1136 | will inherit hardware debug registers from parent | |
1137 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
1138 | zeroed debug registers. | |
1139 | ||
1140 | GDB core assumes the child inherits the watchpoints/hw | |
1141 | breakpoints of the parent, and will remove them all from the | |
1142 | forked off process. Copy the debug registers mirrors into the | |
1143 | new process so that all breakpoints and watchpoints can be | |
1144 | removed together. The debug registers mirror will become zeroed | |
1145 | in the end before detaching the forked off process, thus making | |
1146 | this compatible with older Linux kernels too. */ | |
1147 | ||
61a7418c | 1148 | *child->priv->arch_private = *parent->priv->arch_private; |
3a8a0396 DB |
1149 | } |
1150 | ||
421530db PL |
1151 | /* Implementation of linux_target_ops method "linux_prepare_to_resume". |
1152 | ||
176eb98c MS |
1153 | If the debug regs have changed, update the thread's copies. */ |
1154 | ||
1155 | static void | |
1156 | aarch64_linux_prepare_to_resume (struct lwp_info *lwp) | |
1157 | { | |
d86d4aaf DE |
1158 | struct thread_info *thread = get_lwp_thread (lwp); |
1159 | ptid_t ptid = ptid_of (thread); | |
176eb98c MS |
1160 | struct arch_lwp_info *info = lwp->arch_private; |
1161 | ||
1162 | if (DR_HAS_CHANGED (info->dr_changed_bp) | |
1163 | || DR_HAS_CHANGED (info->dr_changed_wp)) | |
1164 | { | |
1165 | int tid = ptid_get_lwp (ptid); | |
1166 | struct process_info *proc = find_process_pid (ptid_get_pid (ptid)); | |
1167 | struct aarch64_debug_reg_state *state | |
fe978cb0 | 1168 | = &proc->priv->arch_private->debug_reg_state; |
176eb98c | 1169 | |
c5e92cca | 1170 | if (show_debug_regs) |
d86d4aaf | 1171 | fprintf (stderr, "prepare_to_resume thread %ld\n", lwpid_of (thread)); |
176eb98c MS |
1172 | |
1173 | /* Watchpoints. */ | |
1174 | if (DR_HAS_CHANGED (info->dr_changed_wp)) | |
1175 | { | |
1176 | aarch64_linux_set_debug_regs (state, tid, 1); | |
1177 | DR_CLEAR_CHANGED (info->dr_changed_wp); | |
1178 | } | |
1179 | ||
1180 | /* Breakpoints. */ | |
1181 | if (DR_HAS_CHANGED (info->dr_changed_bp)) | |
1182 | { | |
1183 | aarch64_linux_set_debug_regs (state, tid, 0); | |
1184 | DR_CLEAR_CHANGED (info->dr_changed_bp); | |
1185 | } | |
1186 | } | |
1187 | } | |
1188 | ||
1189 | /* ptrace hardware breakpoint resource info is formatted as follows: | |
1190 | ||
1191 | 31 24 16 8 0 | |
1192 | +---------------+--------------+---------------+---------------+ | |
1193 | | RESERVED | RESERVED | DEBUG_ARCH | NUM_SLOTS | | |
1194 | +---------------+--------------+---------------+---------------+ */ | |
1195 | ||
1196 | #define AARCH64_DEBUG_NUM_SLOTS(x) ((x) & 0xff) | |
1197 | #define AARCH64_DEBUG_ARCH(x) (((x) >> 8) & 0xff) | |
1198 | #define AARCH64_DEBUG_ARCH_V8 0x6 | |
1199 | ||
421530db PL |
1200 | /* Implementation of linux_target_ops method "arch_setup". */ |
1201 | ||
176eb98c MS |
1202 | static void |
1203 | aarch64_arch_setup (void) | |
1204 | { | |
1205 | int pid; | |
1206 | struct iovec iov; | |
1207 | struct user_hwdebug_state dreg_state; | |
1208 | ||
3aee8918 | 1209 | current_process ()->tdesc = tdesc_aarch64; |
176eb98c | 1210 | |
0bfdf32f | 1211 | pid = lwpid_of (current_thread); |
176eb98c MS |
1212 | iov.iov_base = &dreg_state; |
1213 | iov.iov_len = sizeof (dreg_state); | |
1214 | ||
1215 | /* Get hardware watchpoint register info. */ | |
1216 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_WATCH, &iov) == 0 | |
1217 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
1218 | { | |
1219 | aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
148de6bb MS |
1220 | if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM) |
1221 | { | |
1222 | warning ("Unexpected number of hardware watchpoint registers reported" | |
1223 | " by ptrace, got %d, expected %d.", | |
1224 | aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM); | |
1225 | aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM; | |
1226 | } | |
176eb98c MS |
1227 | } |
1228 | else | |
1229 | { | |
1230 | warning ("Unable to determine the number of hardware watchpoints" | |
1231 | " available."); | |
1232 | aarch64_num_wp_regs = 0; | |
1233 | } | |
1234 | ||
1235 | /* Get hardware breakpoint register info. */ | |
1236 | if (ptrace (PTRACE_GETREGSET, pid, NT_ARM_HW_BREAK, &iov) == 0 | |
1237 | && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8) | |
1238 | { | |
1239 | aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info); | |
1240 | if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM) | |
148de6bb MS |
1241 | { |
1242 | warning ("Unexpected number of hardware breakpoint registers reported" | |
1243 | " by ptrace, got %d, expected %d.", | |
1244 | aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM); | |
1245 | aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM; | |
1246 | } | |
176eb98c MS |
1247 | } |
1248 | else | |
1249 | { | |
1250 | warning ("Unable to determine the number of hardware breakpoints" | |
1251 | " available."); | |
1252 | aarch64_num_bp_regs = 0; | |
1253 | } | |
1254 | } | |
1255 | ||
3aee8918 | 1256 | static struct regset_info aarch64_regsets[] = |
176eb98c MS |
1257 | { |
1258 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, | |
1259 | sizeof (struct user_pt_regs), GENERAL_REGS, | |
1260 | aarch64_fill_gregset, aarch64_store_gregset }, | |
1261 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET, | |
1262 | sizeof (struct user_fpsimd_state), FP_REGS, | |
1263 | aarch64_fill_fpregset, aarch64_store_fpregset | |
1264 | }, | |
1265 | { 0, 0, 0, -1, -1, NULL, NULL } | |
1266 | }; | |
1267 | ||
3aee8918 PA |
1268 | static struct regsets_info aarch64_regsets_info = |
1269 | { | |
1270 | aarch64_regsets, /* regsets */ | |
1271 | 0, /* num_regsets */ | |
1272 | NULL, /* disabled_regsets */ | |
1273 | }; | |
1274 | ||
3aee8918 PA |
1275 | static struct regs_info regs_info = |
1276 | { | |
1277 | NULL, /* regset_bitmap */ | |
c2d65f38 | 1278 | NULL, /* usrregs */ |
3aee8918 PA |
1279 | &aarch64_regsets_info, |
1280 | }; | |
1281 | ||
421530db PL |
1282 | /* Implementation of linux_target_ops method "regs_info". */ |
1283 | ||
3aee8918 PA |
1284 | static const struct regs_info * |
1285 | aarch64_regs_info (void) | |
1286 | { | |
1287 | return ®s_info; | |
1288 | } | |
1289 | ||
7671bf47 PL |
1290 | /* Implementation of linux_target_ops method "supports_tracepoints". */ |
1291 | ||
1292 | static int | |
1293 | aarch64_supports_tracepoints (void) | |
1294 | { | |
1295 | return 1; | |
1296 | } | |
1297 | ||
176eb98c MS |
1298 | struct linux_target_ops the_low_target = |
1299 | { | |
1300 | aarch64_arch_setup, | |
3aee8918 | 1301 | aarch64_regs_info, |
176eb98c MS |
1302 | aarch64_cannot_fetch_register, |
1303 | aarch64_cannot_store_register, | |
421530db | 1304 | NULL, /* fetch_register */ |
176eb98c MS |
1305 | aarch64_get_pc, |
1306 | aarch64_set_pc, | |
1307 | (const unsigned char *) &aarch64_breakpoint, | |
1308 | aarch64_breakpoint_len, | |
421530db PL |
1309 | NULL, /* breakpoint_reinsert_addr */ |
1310 | 0, /* decr_pc_after_break */ | |
176eb98c | 1311 | aarch64_breakpoint_at, |
802e8e6d | 1312 | aarch64_supports_z_point_type, |
176eb98c MS |
1313 | aarch64_insert_point, |
1314 | aarch64_remove_point, | |
1315 | aarch64_stopped_by_watchpoint, | |
1316 | aarch64_stopped_data_address, | |
421530db PL |
1317 | NULL, /* collect_ptrace_register */ |
1318 | NULL, /* supply_ptrace_register */ | |
1319 | NULL, /* siginfo_fixup */ | |
176eb98c MS |
1320 | aarch64_linux_new_process, |
1321 | aarch64_linux_new_thread, | |
3a8a0396 | 1322 | aarch64_linux_new_fork, |
176eb98c | 1323 | aarch64_linux_prepare_to_resume, |
421530db | 1324 | NULL, /* process_qsupported */ |
7671bf47 | 1325 | aarch64_supports_tracepoints, |
176eb98c | 1326 | }; |
3aee8918 PA |
1327 | |
1328 | void | |
1329 | initialize_low_arch (void) | |
1330 | { | |
1331 | init_registers_aarch64 (); | |
1332 | ||
1333 | initialize_regsets_info (&aarch64_regsets_info); | |
1334 | } |