Commit | Line | Data |
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0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
32d0add0 | 2 | Copyright (C) 1995-2015 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
bd9e6534 | 22 | #include "linux-aarch32-low.h" |
0a30fbc4 | 23 | |
bd9e6534 | 24 | #include <sys/uio.h> |
3743bb4f DE |
25 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
26 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
27 | #ifndef ELFMAG0 | |
58d6951d | 28 | #include <elf.h> |
3743bb4f | 29 | #endif |
5826e159 | 30 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 31 | #include <signal.h> |
9308fc88 | 32 | |
58d6951d | 33 | /* Defined in auto-generated files. */ |
d05b4ac3 | 34 | void init_registers_arm (void); |
3aee8918 PA |
35 | extern const struct target_desc *tdesc_arm; |
36 | ||
d05b4ac3 | 37 | void init_registers_arm_with_iwmmxt (void); |
3aee8918 PA |
38 | extern const struct target_desc *tdesc_arm_with_iwmmxt; |
39 | ||
58d6951d | 40 | void init_registers_arm_with_vfpv2 (void); |
3aee8918 PA |
41 | extern const struct target_desc *tdesc_arm_with_vfpv2; |
42 | ||
58d6951d | 43 | void init_registers_arm_with_vfpv3 (void); |
3aee8918 PA |
44 | extern const struct target_desc *tdesc_arm_with_vfpv3; |
45 | ||
9308fc88 DJ |
46 | #ifndef PTRACE_GET_THREAD_AREA |
47 | #define PTRACE_GET_THREAD_AREA 22 | |
48 | #endif | |
49 | ||
fb1e4ffc DJ |
50 | #ifndef PTRACE_GETWMMXREGS |
51 | # define PTRACE_GETWMMXREGS 18 | |
52 | # define PTRACE_SETWMMXREGS 19 | |
53 | #endif | |
54 | ||
58d6951d DJ |
55 | #ifndef PTRACE_GETVFPREGS |
56 | # define PTRACE_GETVFPREGS 27 | |
57 | # define PTRACE_SETVFPREGS 28 | |
58 | #endif | |
59 | ||
09b4ad9f UW |
60 | #ifndef PTRACE_GETHBPREGS |
61 | #define PTRACE_GETHBPREGS 29 | |
62 | #define PTRACE_SETHBPREGS 30 | |
63 | #endif | |
64 | ||
65 | /* Information describing the hardware breakpoint capabilities. */ | |
71487fd7 | 66 | static struct |
09b4ad9f UW |
67 | { |
68 | unsigned char arch; | |
69 | unsigned char max_wp_length; | |
70 | unsigned char wp_count; | |
71 | unsigned char bp_count; | |
71487fd7 | 72 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
73 | |
74 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
75 | typedef enum | |
76 | { | |
77 | arm_hwbp_break = 0, | |
78 | arm_hwbp_load = 1, | |
79 | arm_hwbp_store = 2, | |
80 | arm_hwbp_access = 3 | |
81 | } arm_hwbp_type; | |
82 | ||
83 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
84 | typedef unsigned int arm_hwbp_control_t; | |
85 | ||
86 | /* Structure used to keep track of hardware break-/watch-points. */ | |
87 | struct arm_linux_hw_breakpoint | |
88 | { | |
89 | /* Address to break on, or being watched. */ | |
90 | unsigned int address; | |
91 | /* Control register for break-/watch- point. */ | |
92 | arm_hwbp_control_t control; | |
93 | }; | |
94 | ||
95 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
96 | assume a maximum number of supported break-/watchpoints. */ | |
97 | #define MAX_BPTS 32 | |
98 | #define MAX_WPTS 32 | |
99 | ||
100 | /* Per-process arch-specific data we want to keep. */ | |
101 | struct arch_process_info | |
102 | { | |
103 | /* Hardware breakpoints for this process. */ | |
104 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
105 | /* Hardware watchpoints for this process. */ | |
106 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
107 | }; | |
108 | ||
109 | /* Per-thread arch-specific data we want to keep. */ | |
110 | struct arch_lwp_info | |
111 | { | |
112 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
113 | char bpts_changed[MAX_BPTS]; | |
114 | char wpts_changed[MAX_WPTS]; | |
115 | /* Cached stopped data address. */ | |
116 | CORE_ADDR stopped_data_address; | |
117 | }; | |
118 | ||
58d6951d DJ |
119 | /* These are in <asm/elf.h> in current kernels. */ |
120 | #define HWCAP_VFP 64 | |
121 | #define HWCAP_IWMMXT 512 | |
122 | #define HWCAP_NEON 4096 | |
123 | #define HWCAP_VFPv3 8192 | |
124 | #define HWCAP_VFPv3D16 16384 | |
125 | ||
0a30fbc4 DJ |
126 | #ifdef HAVE_SYS_REG_H |
127 | #include <sys/reg.h> | |
128 | #endif | |
129 | ||
23ce3b1c | 130 | #define arm_num_regs 26 |
0a30fbc4 | 131 | |
2ec06d2e | 132 | static int arm_regmap[] = { |
0a30fbc4 DJ |
133 | 0, 4, 8, 12, 16, 20, 24, 28, |
134 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
135 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
136 | 64 | |
0a30fbc4 DJ |
137 | }; |
138 | ||
2ec06d2e DJ |
139 | static int |
140 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 141 | { |
2ec06d2e | 142 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
143 | } |
144 | ||
2ec06d2e DJ |
145 | static int |
146 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 147 | { |
2ec06d2e | 148 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
149 | } |
150 | ||
fb1e4ffc | 151 | static void |
442ea881 | 152 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc DJ |
153 | { |
154 | int i; | |
155 | ||
89abb039 | 156 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
157 | return; |
158 | ||
fb1e4ffc | 159 | for (i = 0; i < 16; i++) |
442ea881 | 160 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
161 | |
162 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
163 | for (i = 0; i < 6; i++) | |
442ea881 PA |
164 | collect_register (regcache, arm_num_regs + i + 16, |
165 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
166 | } |
167 | ||
168 | static void | |
442ea881 | 169 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc DJ |
170 | { |
171 | int i; | |
172 | ||
89abb039 | 173 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
174 | return; |
175 | ||
fb1e4ffc | 176 | for (i = 0; i < 16; i++) |
442ea881 | 177 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
178 | |
179 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
180 | for (i = 0; i < 6; i++) | |
442ea881 PA |
181 | supply_register (regcache, arm_num_regs + i + 16, |
182 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
183 | } |
184 | ||
58d6951d | 185 | static void |
442ea881 | 186 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 187 | { |
bd9e6534 | 188 | int num; |
58d6951d | 189 | |
89abb039 YQ |
190 | if (regcache->tdesc == tdesc_arm_with_neon |
191 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 192 | num = 32; |
89abb039 | 193 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 194 | num = 16; |
89abb039 YQ |
195 | else |
196 | return; | |
58d6951d | 197 | |
bd9e6534 | 198 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
199 | } |
200 | ||
201 | static void | |
442ea881 | 202 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 203 | { |
bd9e6534 | 204 | int num; |
58d6951d | 205 | |
89abb039 YQ |
206 | if (regcache->tdesc == tdesc_arm_with_neon |
207 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 208 | num = 32; |
89abb039 | 209 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 210 | num = 16; |
89abb039 YQ |
211 | else |
212 | return; | |
58d6951d | 213 | |
bd9e6534 | 214 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 215 | } |
fb1e4ffc | 216 | |
d677d77d DJ |
217 | extern int debug_threads; |
218 | ||
0d62e5e8 | 219 | static CORE_ADDR |
442ea881 | 220 | arm_get_pc (struct regcache *regcache) |
0d62e5e8 DJ |
221 | { |
222 | unsigned long pc; | |
442ea881 | 223 | collect_register_by_name (regcache, "pc", &pc); |
d677d77d | 224 | if (debug_threads) |
87ce2a04 | 225 | debug_printf ("stop pc is %08lx\n", pc); |
0d62e5e8 DJ |
226 | return pc; |
227 | } | |
228 | ||
229 | static void | |
442ea881 | 230 | arm_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 DJ |
231 | { |
232 | unsigned long newpc = pc; | |
442ea881 | 233 | supply_register_by_name (regcache, "pc", &newpc); |
0d62e5e8 DJ |
234 | } |
235 | ||
aeb75bf5 | 236 | /* Correct in either endianness. */ |
0d62e5e8 DJ |
237 | static const unsigned long arm_breakpoint = 0xef9f0001; |
238 | #define arm_breakpoint_len 4 | |
aeb75bf5 | 239 | static const unsigned short thumb_breakpoint = 0xde01; |
177321bd | 240 | static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 }; |
0d62e5e8 | 241 | |
9d1fb177 DJ |
242 | /* For new EABI binaries. We recognize it regardless of which ABI |
243 | is used for gdbserver, so single threaded debugging should work | |
244 | OK, but for multi-threaded debugging we only insert the current | |
245 | ABI's breakpoint instruction. For now at least. */ | |
246 | static const unsigned long arm_eabi_breakpoint = 0xe7f001f0; | |
247 | ||
0d62e5e8 DJ |
248 | static int |
249 | arm_breakpoint_at (CORE_ADDR where) | |
250 | { | |
0bfdf32f | 251 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
aeb75bf5 | 252 | unsigned long cpsr; |
0d62e5e8 | 253 | |
442ea881 | 254 | collect_register_by_name (regcache, "cpsr", &cpsr); |
0d62e5e8 | 255 | |
aeb75bf5 DJ |
256 | if (cpsr & 0x20) |
257 | { | |
258 | /* Thumb mode. */ | |
259 | unsigned short insn; | |
9d1fb177 | 260 | |
aeb75bf5 DJ |
261 | (*the_target->read_memory) (where, (unsigned char *) &insn, 2); |
262 | if (insn == thumb_breakpoint) | |
263 | return 1; | |
177321bd DJ |
264 | |
265 | if (insn == thumb2_breakpoint[0]) | |
266 | { | |
267 | (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2); | |
268 | if (insn == thumb2_breakpoint[1]) | |
269 | return 1; | |
270 | } | |
aeb75bf5 DJ |
271 | } |
272 | else | |
273 | { | |
274 | /* ARM mode. */ | |
275 | unsigned long insn; | |
276 | ||
277 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
278 | if (insn == arm_breakpoint) | |
279 | return 1; | |
280 | ||
281 | if (insn == arm_eabi_breakpoint) | |
282 | return 1; | |
283 | } | |
9d1fb177 | 284 | |
0d62e5e8 DJ |
285 | return 0; |
286 | } | |
287 | ||
3b2fc2ea DJ |
288 | /* We only place breakpoints in empty marker functions, and thread locking |
289 | is outside of the function. So rather than importing software single-step, | |
290 | we can just run until exit. */ | |
291 | static CORE_ADDR | |
442ea881 | 292 | arm_reinsert_addr (void) |
3b2fc2ea | 293 | { |
0bfdf32f | 294 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
3b2fc2ea | 295 | unsigned long pc; |
442ea881 | 296 | collect_register_by_name (regcache, "lr", &pc); |
3b2fc2ea DJ |
297 | return pc; |
298 | } | |
299 | ||
9308fc88 DJ |
300 | /* Fetch the thread-local storage pointer for libthread_db. */ |
301 | ||
302 | ps_err_e | |
303 | ps_get_thread_area (const struct ps_prochandle *ph, | |
1b3f6016 | 304 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
305 | { |
306 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
307 | return PS_ERR; | |
308 | ||
309 | /* IDX is the bias from the thread pointer to the beginning of the | |
310 | thread descriptor. It has to be subtracted due to implementation | |
311 | quirks in libthread_db. */ | |
312 | *base = (void *) ((char *)*base - idx); | |
313 | ||
314 | return PS_OK; | |
315 | } | |
316 | ||
09b4ad9f | 317 | |
71487fd7 UW |
318 | /* Query Hardware Breakpoint information for the target we are attached to |
319 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
320 | static void | |
321 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 322 | { |
71487fd7 | 323 | unsigned int val; |
09b4ad9f | 324 | |
71487fd7 UW |
325 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
326 | return; | |
09b4ad9f | 327 | |
71487fd7 UW |
328 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
329 | if (arm_linux_hwbp_cap.arch == 0) | |
330 | return; | |
09b4ad9f | 331 | |
71487fd7 UW |
332 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
333 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
334 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 335 | |
71487fd7 UW |
336 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
337 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
338 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
339 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
340 | } |
341 | ||
342 | /* How many hardware breakpoints are available? */ | |
343 | static int | |
344 | arm_linux_get_hw_breakpoint_count (void) | |
345 | { | |
71487fd7 | 346 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
347 | } |
348 | ||
349 | /* How many hardware watchpoints are available? */ | |
350 | static int | |
351 | arm_linux_get_hw_watchpoint_count (void) | |
352 | { | |
71487fd7 | 353 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
354 | } |
355 | ||
356 | /* Maximum length of area watched by hardware watchpoint. */ | |
357 | static int | |
358 | arm_linux_get_hw_watchpoint_max_length (void) | |
359 | { | |
71487fd7 | 360 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
361 | } |
362 | ||
363 | /* Initialize an ARM hardware break-/watch-point control register value. | |
364 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
365 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
366 | */ | |
367 | static arm_hwbp_control_t | |
368 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
369 | arm_hwbp_type hwbp_type, | |
370 | int enable) | |
371 | { | |
372 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
373 | gdb_assert (hwbp_type != arm_hwbp_break | |
374 | || ((byte_address_select & 0xfU) != 0)); | |
375 | ||
376 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
377 | } | |
378 | ||
379 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
380 | static int | |
381 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
382 | { | |
383 | return control & 0x1; | |
384 | } | |
385 | ||
386 | /* Is the breakpoint control value CONTROL initialized? */ | |
387 | static int | |
388 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
389 | { | |
390 | return control != 0; | |
391 | } | |
392 | ||
393 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
394 | static arm_hwbp_control_t | |
395 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
396 | { | |
397 | return control & ~0x1; | |
398 | } | |
399 | ||
400 | /* Are two break-/watch-points equal? */ | |
401 | static int | |
402 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
403 | const struct arm_linux_hw_breakpoint *p2) | |
404 | { | |
405 | return p1->address == p2->address && p1->control == p2->control; | |
406 | } | |
407 | ||
802e8e6d PA |
408 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
409 | ||
410 | static int | |
411 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) | |
412 | { | |
413 | switch (raw_type) | |
414 | { | |
415 | case raw_bkpt_type_hw: | |
416 | return arm_hwbp_break; | |
417 | case raw_bkpt_type_write_wp: | |
418 | return arm_hwbp_store; | |
419 | case raw_bkpt_type_read_wp: | |
420 | return arm_hwbp_load; | |
421 | case raw_bkpt_type_access_wp: | |
422 | return arm_hwbp_access; | |
423 | default: | |
424 | gdb_assert_not_reached ("unhandled raw type"); | |
425 | } | |
426 | } | |
427 | ||
09b4ad9f UW |
428 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
429 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
430 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
431 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
432 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 433 | static int |
802e8e6d PA |
434 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
435 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
436 | { |
437 | arm_hwbp_type hwbp_type; | |
438 | unsigned mask; | |
439 | ||
802e8e6d | 440 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
441 | |
442 | if (hwbp_type == arm_hwbp_break) | |
443 | { | |
444 | /* For breakpoints, the length field encodes the mode. */ | |
445 | switch (len) | |
446 | { | |
447 | case 2: /* 16-bit Thumb mode breakpoint */ | |
448 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
449 | mask = 0x3; |
450 | addr &= ~1; | |
09b4ad9f UW |
451 | break; |
452 | case 4: /* 32-bit ARM mode breakpoint */ | |
453 | mask = 0xf; | |
fcf303ab | 454 | addr &= ~3; |
09b4ad9f UW |
455 | break; |
456 | default: | |
457 | /* Unsupported. */ | |
b62e2b27 | 458 | return -2; |
09b4ad9f | 459 | } |
09b4ad9f UW |
460 | } |
461 | else | |
462 | { | |
463 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
464 | CORE_ADDR aligned_addr; | |
465 | ||
466 | /* Can not set watchpoints for zero or negative lengths. */ | |
467 | if (len <= 0) | |
b62e2b27 | 468 | return -2; |
09b4ad9f UW |
469 | /* The current ptrace interface can only handle watchpoints that are a |
470 | power of 2. */ | |
471 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 472 | return -2; |
09b4ad9f UW |
473 | |
474 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
475 | range covered by a watchpoint. */ | |
476 | aligned_addr = addr & ~(max_wp_length - 1); | |
477 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 478 | return -2; |
09b4ad9f UW |
479 | |
480 | mask = (1 << len) - 1; | |
481 | } | |
482 | ||
483 | p->address = (unsigned int) addr; | |
484 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
485 | ||
486 | return hwbp_type != arm_hwbp_break; | |
487 | } | |
488 | ||
489 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
490 | the current process. */ | |
491 | ||
492 | struct update_registers_data | |
493 | { | |
494 | int watch; | |
495 | int i; | |
496 | }; | |
497 | ||
498 | static int | |
499 | update_registers_callback (struct inferior_list_entry *entry, void *arg) | |
500 | { | |
d86d4aaf DE |
501 | struct thread_info *thread = (struct thread_info *) entry; |
502 | struct lwp_info *lwp = get_thread_lwp (thread); | |
09b4ad9f UW |
503 | struct update_registers_data *data = (struct update_registers_data *) arg; |
504 | ||
505 | /* Only update the threads of the current process. */ | |
0bfdf32f | 506 | if (pid_of (thread) == pid_of (current_thread)) |
09b4ad9f UW |
507 | { |
508 | /* The actual update is done later just before resuming the lwp, | |
509 | we just mark that the registers need updating. */ | |
510 | if (data->watch) | |
511 | lwp->arch_private->wpts_changed[data->i] = 1; | |
512 | else | |
513 | lwp->arch_private->bpts_changed[data->i] = 1; | |
514 | ||
515 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
516 | we can update its breakpoint registers. */ | |
517 | if (!lwp->stopped) | |
518 | linux_stop_lwp (lwp); | |
519 | } | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
802e8e6d PA |
524 | static int |
525 | arm_supports_z_point_type (char z_type) | |
526 | { | |
527 | switch (z_type) | |
528 | { | |
529 | case Z_PACKET_HW_BP: | |
530 | case Z_PACKET_WRITE_WP: | |
531 | case Z_PACKET_READ_WP: | |
532 | case Z_PACKET_ACCESS_WP: | |
533 | return 1; | |
534 | default: | |
535 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
536 | return 0; | |
537 | } | |
538 | } | |
539 | ||
09b4ad9f UW |
540 | /* Insert hardware break-/watchpoint. */ |
541 | static int | |
802e8e6d PA |
542 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
543 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
544 | { |
545 | struct process_info *proc = current_process (); | |
546 | struct arm_linux_hw_breakpoint p, *pts; | |
547 | int watch, i, count; | |
548 | ||
549 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
550 | if (watch < 0) | |
551 | { | |
552 | /* Unsupported. */ | |
b62e2b27 | 553 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
554 | } |
555 | ||
556 | if (watch) | |
557 | { | |
558 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 559 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
560 | } |
561 | else | |
562 | { | |
563 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 564 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
565 | } |
566 | ||
567 | for (i = 0; i < count; i++) | |
568 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
569 | { | |
570 | struct update_registers_data data = { watch, i }; | |
571 | pts[i] = p; | |
d86d4aaf | 572 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
573 | return 0; |
574 | } | |
575 | ||
576 | /* We're out of watchpoints. */ | |
577 | return -1; | |
578 | } | |
579 | ||
580 | /* Remove hardware break-/watchpoint. */ | |
581 | static int | |
802e8e6d PA |
582 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
583 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
584 | { |
585 | struct process_info *proc = current_process (); | |
586 | struct arm_linux_hw_breakpoint p, *pts; | |
587 | int watch, i, count; | |
588 | ||
589 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
590 | if (watch < 0) | |
591 | { | |
592 | /* Unsupported. */ | |
593 | return -1; | |
594 | } | |
595 | ||
596 | if (watch) | |
597 | { | |
598 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 599 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
600 | } |
601 | else | |
602 | { | |
603 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 604 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
605 | } |
606 | ||
607 | for (i = 0; i < count; i++) | |
608 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
609 | { | |
610 | struct update_registers_data data = { watch, i }; | |
611 | pts[i].control = arm_hwbp_control_disable (pts[i].control); | |
d86d4aaf | 612 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
613 | return 0; |
614 | } | |
615 | ||
616 | /* No watchpoint matched. */ | |
617 | return -1; | |
618 | } | |
619 | ||
620 | /* Return whether current thread is stopped due to a watchpoint. */ | |
621 | static int | |
622 | arm_stopped_by_watchpoint (void) | |
623 | { | |
0bfdf32f | 624 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 625 | siginfo_t siginfo; |
09b4ad9f UW |
626 | |
627 | /* We must be able to set hardware watchpoints. */ | |
628 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
629 | return 0; | |
630 | ||
631 | /* Retrieve siginfo. */ | |
632 | errno = 0; | |
0bfdf32f | 633 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
634 | if (errno != 0) |
635 | return 0; | |
636 | ||
637 | /* This must be a hardware breakpoint. */ | |
638 | if (siginfo.si_signo != SIGTRAP | |
639 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
640 | return 0; | |
641 | ||
642 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
643 | a watchpoint. */ | |
644 | if (siginfo.si_errno >= 0) | |
645 | return 0; | |
646 | ||
647 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
648 | lwp->arch_private->stopped_data_address | |
649 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
650 | ||
651 | return 1; | |
652 | } | |
653 | ||
654 | /* Return data address that triggered watchpoint. Called only if | |
655 | arm_stopped_by_watchpoint returned true. */ | |
656 | static CORE_ADDR | |
657 | arm_stopped_data_address (void) | |
658 | { | |
0bfdf32f | 659 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
660 | return lwp->arch_private->stopped_data_address; |
661 | } | |
662 | ||
663 | /* Called when a new process is created. */ | |
664 | static struct arch_process_info * | |
665 | arm_new_process (void) | |
666 | { | |
667 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); | |
668 | return info; | |
669 | } | |
670 | ||
671 | /* Called when a new thread is detected. */ | |
34c703da GB |
672 | static void |
673 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f UW |
674 | { |
675 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); | |
676 | int i; | |
677 | ||
678 | for (i = 0; i < MAX_BPTS; i++) | |
679 | info->bpts_changed[i] = 1; | |
680 | for (i = 0; i < MAX_WPTS; i++) | |
681 | info->wpts_changed[i] = 1; | |
682 | ||
34c703da | 683 | lwp->arch_private = info; |
09b4ad9f UW |
684 | } |
685 | ||
3a8a0396 DB |
686 | static void |
687 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
688 | { | |
61a7418c DB |
689 | struct arch_process_info *parent_proc_info = parent->priv->arch_private; |
690 | struct arch_process_info *child_proc_info = child->priv->arch_private; | |
3a8a0396 DB |
691 | struct lwp_info *child_lwp; |
692 | struct arch_lwp_info *child_lwp_info; | |
693 | int i; | |
694 | ||
695 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
696 | gdb_assert (parent->priv != NULL |
697 | && parent->priv->arch_private != NULL); | |
698 | gdb_assert (child->priv != NULL | |
699 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
700 | |
701 | /* Linux kernel before 2.6.33 commit | |
702 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
703 | will inherit hardware debug registers from parent | |
704 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
705 | zeroed debug registers. | |
706 | ||
707 | GDB core assumes the child inherits the watchpoints/hw | |
708 | breakpoints of the parent, and will remove them all from the | |
709 | forked off process. Copy the debug registers mirrors into the | |
710 | new process so that all breakpoints and watchpoints can be | |
711 | removed together. The debug registers mirror will become zeroed | |
712 | in the end before detaching the forked off process, thus making | |
713 | this compatible with older Linux kernels too. */ | |
714 | ||
715 | *child_proc_info = *parent_proc_info; | |
716 | ||
717 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
718 | make sure that the registers will be updated. */ | |
719 | child_lwp = find_lwp_pid (ptid_of (child)); | |
720 | child_lwp_info = child_lwp->arch_private; | |
721 | for (i = 0; i < MAX_BPTS; i++) | |
722 | child_lwp_info->bpts_changed[i] = 1; | |
723 | for (i = 0; i < MAX_WPTS; i++) | |
724 | child_lwp_info->wpts_changed[i] = 1; | |
725 | } | |
726 | ||
09b4ad9f UW |
727 | /* Called when resuming a thread. |
728 | If the debug regs have changed, update the thread's copies. */ | |
729 | static void | |
730 | arm_prepare_to_resume (struct lwp_info *lwp) | |
731 | { | |
d86d4aaf DE |
732 | struct thread_info *thread = get_lwp_thread (lwp); |
733 | int pid = lwpid_of (thread); | |
734 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 735 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
736 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
737 | int i; | |
738 | ||
739 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
740 | if (lwp_info->bpts_changed[i]) | |
741 | { | |
742 | errno = 0; | |
743 | ||
744 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 745 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 746 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 747 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 748 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
749 | |
750 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 751 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 752 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 753 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 754 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
755 | |
756 | lwp_info->bpts_changed[i] = 0; | |
757 | } | |
758 | ||
759 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
760 | if (lwp_info->wpts_changed[i]) | |
761 | { | |
762 | errno = 0; | |
763 | ||
764 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 765 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 766 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 767 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 768 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
769 | |
770 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 771 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 772 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 773 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 774 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
775 | |
776 | lwp_info->wpts_changed[i] = 0; | |
777 | } | |
778 | } | |
779 | ||
780 | ||
58d6951d DJ |
781 | static int |
782 | arm_get_hwcap (unsigned long *valp) | |
783 | { | |
784 | unsigned char *data = alloca (8); | |
785 | int offset = 0; | |
786 | ||
787 | while ((*the_target->read_auxv) (offset, data, 8) == 8) | |
788 | { | |
789 | unsigned int *data_p = (unsigned int *)data; | |
790 | if (data_p[0] == AT_HWCAP) | |
791 | { | |
792 | *valp = data_p[1]; | |
793 | return 1; | |
794 | } | |
795 | ||
796 | offset += 8; | |
797 | } | |
798 | ||
799 | *valp = 0; | |
800 | return 0; | |
801 | } | |
802 | ||
3aee8918 PA |
803 | static const struct target_desc * |
804 | arm_read_description (void) | |
58d6951d | 805 | { |
0bfdf32f | 806 | int pid = lwpid_of (current_thread); |
e8b41681 | 807 | unsigned long arm_hwcap = 0; |
71487fd7 UW |
808 | |
809 | /* Query hardware watchpoint/breakpoint capabilities. */ | |
810 | arm_linux_init_hwbp_cap (pid); | |
811 | ||
58d6951d | 812 | if (arm_get_hwcap (&arm_hwcap) == 0) |
3aee8918 | 813 | return tdesc_arm; |
58d6951d DJ |
814 | |
815 | if (arm_hwcap & HWCAP_IWMMXT) | |
3aee8918 | 816 | return tdesc_arm_with_iwmmxt; |
58d6951d DJ |
817 | |
818 | if (arm_hwcap & HWCAP_VFP) | |
819 | { | |
3aee8918 | 820 | const struct target_desc *result; |
58d6951d DJ |
821 | char *buf; |
822 | ||
823 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
824 | it with VFP. */ | |
825 | if (arm_hwcap & HWCAP_NEON) | |
3aee8918 | 826 | result = tdesc_arm_with_neon; |
58d6951d | 827 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
3aee8918 | 828 | result = tdesc_arm_with_vfpv3; |
58d6951d | 829 | else |
3aee8918 | 830 | result = tdesc_arm_with_vfpv2; |
58d6951d DJ |
831 | |
832 | /* Now make sure that the kernel supports reading these | |
833 | registers. Support was added in 2.6.30. */ | |
58d6951d | 834 | errno = 0; |
c3e8aadd | 835 | buf = xmalloc (32 * 8 + 4); |
58d6951d DJ |
836 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
837 | && errno == EIO) | |
e8b41681 YQ |
838 | result = tdesc_arm; |
839 | ||
58d6951d DJ |
840 | free (buf); |
841 | ||
3aee8918 | 842 | return result; |
58d6951d DJ |
843 | } |
844 | ||
845 | /* The default configuration uses legacy FPA registers, probably | |
846 | simulated. */ | |
3aee8918 | 847 | return tdesc_arm; |
58d6951d DJ |
848 | } |
849 | ||
3aee8918 PA |
850 | static void |
851 | arm_arch_setup (void) | |
852 | { | |
bd9e6534 YQ |
853 | int tid = lwpid_of (current_thread); |
854 | int gpregs[18]; | |
855 | struct iovec iov; | |
856 | ||
3aee8918 | 857 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
858 | |
859 | iov.iov_base = gpregs; | |
860 | iov.iov_len = sizeof (gpregs); | |
861 | ||
862 | /* Check if PTRACE_GETREGSET works. */ | |
863 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
864 | have_ptrace_getregset = 1; | |
865 | else | |
866 | have_ptrace_getregset = 0; | |
3aee8918 PA |
867 | } |
868 | ||
bd9e6534 YQ |
869 | /* Register sets without using PTRACE_GETREGSET. */ |
870 | ||
3aee8918 | 871 | static struct regset_info arm_regsets[] = { |
1570b33e | 872 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4, |
fb1e4ffc DJ |
873 | GENERAL_REGS, |
874 | arm_fill_gregset, arm_store_gregset }, | |
1570b33e | 875 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4, |
fb1e4ffc DJ |
876 | EXTENDED_REGS, |
877 | arm_fill_wmmxregset, arm_store_wmmxregset }, | |
1570b33e | 878 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4, |
58d6951d DJ |
879 | EXTENDED_REGS, |
880 | arm_fill_vfpregset, arm_store_vfpregset }, | |
1570b33e | 881 | { 0, 0, 0, -1, -1, NULL, NULL } |
fb1e4ffc DJ |
882 | }; |
883 | ||
3aee8918 PA |
884 | static struct regsets_info arm_regsets_info = |
885 | { | |
886 | arm_regsets, /* regsets */ | |
887 | 0, /* num_regsets */ | |
888 | NULL, /* disabled_regsets */ | |
889 | }; | |
890 | ||
891 | static struct usrregs_info arm_usrregs_info = | |
892 | { | |
893 | arm_num_regs, | |
894 | arm_regmap, | |
895 | }; | |
896 | ||
bd9e6534 | 897 | static struct regs_info regs_info_arm = |
3aee8918 PA |
898 | { |
899 | NULL, /* regset_bitmap */ | |
900 | &arm_usrregs_info, | |
901 | &arm_regsets_info | |
902 | }; | |
903 | ||
904 | static const struct regs_info * | |
905 | arm_regs_info (void) | |
906 | { | |
bd9e6534 YQ |
907 | const struct target_desc *tdesc = current_process ()->tdesc; |
908 | ||
909 | if (have_ptrace_getregset == 1 | |
910 | && (tdesc == tdesc_arm_with_neon || tdesc == tdesc_arm_with_vfpv3)) | |
911 | return ®s_info_aarch32; | |
912 | else | |
913 | return ®s_info_arm; | |
3aee8918 PA |
914 | } |
915 | ||
2ec06d2e | 916 | struct linux_target_ops the_low_target = { |
58d6951d | 917 | arm_arch_setup, |
3aee8918 | 918 | arm_regs_info, |
2ec06d2e DJ |
919 | arm_cannot_fetch_register, |
920 | arm_cannot_store_register, | |
c14dfd32 | 921 | NULL, /* fetch_register */ |
0d62e5e8 DJ |
922 | arm_get_pc, |
923 | arm_set_pc, | |
aeb75bf5 DJ |
924 | |
925 | /* Define an ARM-mode breakpoint; we only set breakpoints in the C | |
926 | library, which is most likely to be ARM. If the kernel supports | |
927 | clone events, we will never insert a breakpoint, so even a Thumb | |
928 | C library will work; so will mixing EABI/non-EABI gdbserver and | |
929 | application. */ | |
9d1fb177 | 930 | #ifndef __ARM_EABI__ |
f450004a | 931 | (const unsigned char *) &arm_breakpoint, |
9d1fb177 DJ |
932 | #else |
933 | (const unsigned char *) &arm_eabi_breakpoint, | |
934 | #endif | |
0d62e5e8 | 935 | arm_breakpoint_len, |
3b2fc2ea | 936 | arm_reinsert_addr, |
0d62e5e8 DJ |
937 | 0, |
938 | arm_breakpoint_at, | |
802e8e6d | 939 | arm_supports_z_point_type, |
09b4ad9f UW |
940 | arm_insert_point, |
941 | arm_remove_point, | |
942 | arm_stopped_by_watchpoint, | |
943 | arm_stopped_data_address, | |
944 | NULL, /* collect_ptrace_register */ | |
945 | NULL, /* supply_ptrace_register */ | |
946 | NULL, /* siginfo_fixup */ | |
947 | arm_new_process, | |
948 | arm_new_thread, | |
3a8a0396 | 949 | arm_new_fork, |
09b4ad9f | 950 | arm_prepare_to_resume, |
2ec06d2e | 951 | }; |
3aee8918 PA |
952 | |
953 | void | |
954 | initialize_low_arch (void) | |
955 | { | |
956 | /* Initialize the Linux target descriptions. */ | |
957 | init_registers_arm (); | |
958 | init_registers_arm_with_iwmmxt (); | |
959 | init_registers_arm_with_vfpv2 (); | |
960 | init_registers_arm_with_vfpv3 (); | |
bd9e6534 YQ |
961 | |
962 | initialize_low_arch_aarch32 (); | |
3aee8918 PA |
963 | |
964 | initialize_regsets_info (&arm_regsets_info); | |
965 | } |