Commit | Line | Data |
---|---|---|
0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
0b302171 | 2 | Copyright (C) 1995-1996, 1998-2012 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
3743bb4f DE |
22 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
23 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
24 | #ifndef ELFMAG0 | |
58d6951d | 25 | #include <elf.h> |
3743bb4f | 26 | #endif |
9308fc88 | 27 | #include <sys/ptrace.h> |
09b4ad9f | 28 | #include <signal.h> |
9308fc88 | 29 | |
58d6951d | 30 | /* Defined in auto-generated files. */ |
d05b4ac3 | 31 | void init_registers_arm (void); |
d05b4ac3 | 32 | void init_registers_arm_with_iwmmxt (void); |
58d6951d DJ |
33 | void init_registers_arm_with_vfpv2 (void); |
34 | void init_registers_arm_with_vfpv3 (void); | |
35 | void init_registers_arm_with_neon (void); | |
d05b4ac3 | 36 | |
9308fc88 DJ |
37 | #ifndef PTRACE_GET_THREAD_AREA |
38 | #define PTRACE_GET_THREAD_AREA 22 | |
39 | #endif | |
40 | ||
fb1e4ffc DJ |
41 | #ifndef PTRACE_GETWMMXREGS |
42 | # define PTRACE_GETWMMXREGS 18 | |
43 | # define PTRACE_SETWMMXREGS 19 | |
44 | #endif | |
45 | ||
58d6951d DJ |
46 | #ifndef PTRACE_GETVFPREGS |
47 | # define PTRACE_GETVFPREGS 27 | |
48 | # define PTRACE_SETVFPREGS 28 | |
49 | #endif | |
50 | ||
09b4ad9f UW |
51 | #ifndef PTRACE_GETHBPREGS |
52 | #define PTRACE_GETHBPREGS 29 | |
53 | #define PTRACE_SETHBPREGS 30 | |
54 | #endif | |
55 | ||
56 | /* Information describing the hardware breakpoint capabilities. */ | |
71487fd7 | 57 | static struct |
09b4ad9f UW |
58 | { |
59 | unsigned char arch; | |
60 | unsigned char max_wp_length; | |
61 | unsigned char wp_count; | |
62 | unsigned char bp_count; | |
71487fd7 | 63 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
64 | |
65 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
66 | typedef enum | |
67 | { | |
68 | arm_hwbp_break = 0, | |
69 | arm_hwbp_load = 1, | |
70 | arm_hwbp_store = 2, | |
71 | arm_hwbp_access = 3 | |
72 | } arm_hwbp_type; | |
73 | ||
74 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
75 | typedef unsigned int arm_hwbp_control_t; | |
76 | ||
77 | /* Structure used to keep track of hardware break-/watch-points. */ | |
78 | struct arm_linux_hw_breakpoint | |
79 | { | |
80 | /* Address to break on, or being watched. */ | |
81 | unsigned int address; | |
82 | /* Control register for break-/watch- point. */ | |
83 | arm_hwbp_control_t control; | |
84 | }; | |
85 | ||
86 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
87 | assume a maximum number of supported break-/watchpoints. */ | |
88 | #define MAX_BPTS 32 | |
89 | #define MAX_WPTS 32 | |
90 | ||
91 | /* Per-process arch-specific data we want to keep. */ | |
92 | struct arch_process_info | |
93 | { | |
94 | /* Hardware breakpoints for this process. */ | |
95 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
96 | /* Hardware watchpoints for this process. */ | |
97 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
98 | }; | |
99 | ||
100 | /* Per-thread arch-specific data we want to keep. */ | |
101 | struct arch_lwp_info | |
102 | { | |
103 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
104 | char bpts_changed[MAX_BPTS]; | |
105 | char wpts_changed[MAX_WPTS]; | |
106 | /* Cached stopped data address. */ | |
107 | CORE_ADDR stopped_data_address; | |
108 | }; | |
109 | ||
58d6951d DJ |
110 | static unsigned long arm_hwcap; |
111 | ||
112 | /* These are in <asm/elf.h> in current kernels. */ | |
113 | #define HWCAP_VFP 64 | |
114 | #define HWCAP_IWMMXT 512 | |
115 | #define HWCAP_NEON 4096 | |
116 | #define HWCAP_VFPv3 8192 | |
117 | #define HWCAP_VFPv3D16 16384 | |
118 | ||
0a30fbc4 DJ |
119 | #ifdef HAVE_SYS_REG_H |
120 | #include <sys/reg.h> | |
121 | #endif | |
122 | ||
23ce3b1c | 123 | #define arm_num_regs 26 |
0a30fbc4 | 124 | |
2ec06d2e | 125 | static int arm_regmap[] = { |
0a30fbc4 DJ |
126 | 0, 4, 8, 12, 16, 20, 24, 28, |
127 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
128 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
129 | 64 | |
0a30fbc4 DJ |
130 | }; |
131 | ||
2ec06d2e DJ |
132 | static int |
133 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 134 | { |
2ec06d2e | 135 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
136 | } |
137 | ||
2ec06d2e DJ |
138 | static int |
139 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 140 | { |
2ec06d2e | 141 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
142 | } |
143 | ||
fb1e4ffc | 144 | static void |
442ea881 | 145 | arm_fill_gregset (struct regcache *regcache, void *buf) |
fb1e4ffc DJ |
146 | { |
147 | int i; | |
148 | ||
149 | for (i = 0; i < arm_num_regs; i++) | |
150 | if (arm_regmap[i] != -1) | |
442ea881 | 151 | collect_register (regcache, i, ((char *) buf) + arm_regmap[i]); |
fb1e4ffc DJ |
152 | } |
153 | ||
154 | static void | |
442ea881 | 155 | arm_store_gregset (struct regcache *regcache, const void *buf) |
fb1e4ffc DJ |
156 | { |
157 | int i; | |
158 | char zerobuf[8]; | |
159 | ||
160 | memset (zerobuf, 0, 8); | |
161 | for (i = 0; i < arm_num_regs; i++) | |
162 | if (arm_regmap[i] != -1) | |
442ea881 | 163 | supply_register (regcache, i, ((char *) buf) + arm_regmap[i]); |
fb1e4ffc | 164 | else |
442ea881 | 165 | supply_register (regcache, i, zerobuf); |
fb1e4ffc DJ |
166 | } |
167 | ||
fb1e4ffc | 168 | static void |
442ea881 | 169 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc DJ |
170 | { |
171 | int i; | |
172 | ||
58d6951d DJ |
173 | if (!(arm_hwcap & HWCAP_IWMMXT)) |
174 | return; | |
175 | ||
fb1e4ffc | 176 | for (i = 0; i < 16; i++) |
442ea881 | 177 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
178 | |
179 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
180 | for (i = 0; i < 6; i++) | |
442ea881 PA |
181 | collect_register (regcache, arm_num_regs + i + 16, |
182 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
183 | } |
184 | ||
185 | static void | |
442ea881 | 186 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc DJ |
187 | { |
188 | int i; | |
189 | ||
58d6951d DJ |
190 | if (!(arm_hwcap & HWCAP_IWMMXT)) |
191 | return; | |
192 | ||
fb1e4ffc | 193 | for (i = 0; i < 16; i++) |
442ea881 | 194 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
195 | |
196 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
197 | for (i = 0; i < 6; i++) | |
442ea881 PA |
198 | supply_register (regcache, arm_num_regs + i + 16, |
199 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
200 | } |
201 | ||
58d6951d | 202 | static void |
442ea881 | 203 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d DJ |
204 | { |
205 | int i, num, base; | |
206 | ||
207 | if (!(arm_hwcap & HWCAP_VFP)) | |
208 | return; | |
209 | ||
210 | if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) | |
211 | num = 32; | |
212 | else | |
213 | num = 16; | |
214 | ||
215 | base = find_regno ("d0"); | |
216 | for (i = 0; i < num; i++) | |
442ea881 | 217 | collect_register (regcache, base + i, (char *) buf + i * 8); |
58d6951d | 218 | |
442ea881 | 219 | collect_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); |
58d6951d DJ |
220 | } |
221 | ||
222 | static void | |
442ea881 | 223 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d DJ |
224 | { |
225 | int i, num, base; | |
226 | ||
227 | if (!(arm_hwcap & HWCAP_VFP)) | |
228 | return; | |
229 | ||
230 | if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) | |
231 | num = 32; | |
232 | else | |
233 | num = 16; | |
234 | ||
235 | base = find_regno ("d0"); | |
236 | for (i = 0; i < num; i++) | |
442ea881 | 237 | supply_register (regcache, base + i, (char *) buf + i * 8); |
58d6951d | 238 | |
442ea881 | 239 | supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8); |
58d6951d | 240 | } |
fb1e4ffc | 241 | |
d677d77d DJ |
242 | extern int debug_threads; |
243 | ||
0d62e5e8 | 244 | static CORE_ADDR |
442ea881 | 245 | arm_get_pc (struct regcache *regcache) |
0d62e5e8 DJ |
246 | { |
247 | unsigned long pc; | |
442ea881 | 248 | collect_register_by_name (regcache, "pc", &pc); |
d677d77d DJ |
249 | if (debug_threads) |
250 | fprintf (stderr, "stop pc is %08lx\n", pc); | |
0d62e5e8 DJ |
251 | return pc; |
252 | } | |
253 | ||
254 | static void | |
442ea881 | 255 | arm_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 DJ |
256 | { |
257 | unsigned long newpc = pc; | |
442ea881 | 258 | supply_register_by_name (regcache, "pc", &newpc); |
0d62e5e8 DJ |
259 | } |
260 | ||
aeb75bf5 | 261 | /* Correct in either endianness. */ |
0d62e5e8 DJ |
262 | static const unsigned long arm_breakpoint = 0xef9f0001; |
263 | #define arm_breakpoint_len 4 | |
aeb75bf5 | 264 | static const unsigned short thumb_breakpoint = 0xde01; |
177321bd | 265 | static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 }; |
0d62e5e8 | 266 | |
9d1fb177 DJ |
267 | /* For new EABI binaries. We recognize it regardless of which ABI |
268 | is used for gdbserver, so single threaded debugging should work | |
269 | OK, but for multi-threaded debugging we only insert the current | |
270 | ABI's breakpoint instruction. For now at least. */ | |
271 | static const unsigned long arm_eabi_breakpoint = 0xe7f001f0; | |
272 | ||
0d62e5e8 DJ |
273 | static int |
274 | arm_breakpoint_at (CORE_ADDR where) | |
275 | { | |
442ea881 | 276 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
aeb75bf5 | 277 | unsigned long cpsr; |
0d62e5e8 | 278 | |
442ea881 | 279 | collect_register_by_name (regcache, "cpsr", &cpsr); |
0d62e5e8 | 280 | |
aeb75bf5 DJ |
281 | if (cpsr & 0x20) |
282 | { | |
283 | /* Thumb mode. */ | |
284 | unsigned short insn; | |
9d1fb177 | 285 | |
aeb75bf5 DJ |
286 | (*the_target->read_memory) (where, (unsigned char *) &insn, 2); |
287 | if (insn == thumb_breakpoint) | |
288 | return 1; | |
177321bd DJ |
289 | |
290 | if (insn == thumb2_breakpoint[0]) | |
291 | { | |
292 | (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2); | |
293 | if (insn == thumb2_breakpoint[1]) | |
294 | return 1; | |
295 | } | |
aeb75bf5 DJ |
296 | } |
297 | else | |
298 | { | |
299 | /* ARM mode. */ | |
300 | unsigned long insn; | |
301 | ||
302 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
303 | if (insn == arm_breakpoint) | |
304 | return 1; | |
305 | ||
306 | if (insn == arm_eabi_breakpoint) | |
307 | return 1; | |
308 | } | |
9d1fb177 | 309 | |
0d62e5e8 DJ |
310 | return 0; |
311 | } | |
312 | ||
3b2fc2ea DJ |
313 | /* We only place breakpoints in empty marker functions, and thread locking |
314 | is outside of the function. So rather than importing software single-step, | |
315 | we can just run until exit. */ | |
316 | static CORE_ADDR | |
442ea881 | 317 | arm_reinsert_addr (void) |
3b2fc2ea | 318 | { |
442ea881 | 319 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
3b2fc2ea | 320 | unsigned long pc; |
442ea881 | 321 | collect_register_by_name (regcache, "lr", &pc); |
3b2fc2ea DJ |
322 | return pc; |
323 | } | |
324 | ||
9308fc88 DJ |
325 | /* Fetch the thread-local storage pointer for libthread_db. */ |
326 | ||
327 | ps_err_e | |
328 | ps_get_thread_area (const struct ps_prochandle *ph, | |
1b3f6016 | 329 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
330 | { |
331 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
332 | return PS_ERR; | |
333 | ||
334 | /* IDX is the bias from the thread pointer to the beginning of the | |
335 | thread descriptor. It has to be subtracted due to implementation | |
336 | quirks in libthread_db. */ | |
337 | *base = (void *) ((char *)*base - idx); | |
338 | ||
339 | return PS_OK; | |
340 | } | |
341 | ||
09b4ad9f | 342 | |
71487fd7 UW |
343 | /* Query Hardware Breakpoint information for the target we are attached to |
344 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
345 | static void | |
346 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 347 | { |
71487fd7 | 348 | unsigned int val; |
09b4ad9f | 349 | |
71487fd7 UW |
350 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
351 | return; | |
09b4ad9f | 352 | |
71487fd7 UW |
353 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
354 | if (arm_linux_hwbp_cap.arch == 0) | |
355 | return; | |
09b4ad9f | 356 | |
71487fd7 UW |
357 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
358 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
359 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 360 | |
71487fd7 UW |
361 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
362 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
363 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
364 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
365 | } |
366 | ||
367 | /* How many hardware breakpoints are available? */ | |
368 | static int | |
369 | arm_linux_get_hw_breakpoint_count (void) | |
370 | { | |
71487fd7 | 371 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
372 | } |
373 | ||
374 | /* How many hardware watchpoints are available? */ | |
375 | static int | |
376 | arm_linux_get_hw_watchpoint_count (void) | |
377 | { | |
71487fd7 | 378 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
379 | } |
380 | ||
381 | /* Maximum length of area watched by hardware watchpoint. */ | |
382 | static int | |
383 | arm_linux_get_hw_watchpoint_max_length (void) | |
384 | { | |
71487fd7 | 385 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
386 | } |
387 | ||
388 | /* Initialize an ARM hardware break-/watch-point control register value. | |
389 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
390 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
391 | */ | |
392 | static arm_hwbp_control_t | |
393 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
394 | arm_hwbp_type hwbp_type, | |
395 | int enable) | |
396 | { | |
397 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
398 | gdb_assert (hwbp_type != arm_hwbp_break | |
399 | || ((byte_address_select & 0xfU) != 0)); | |
400 | ||
401 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
402 | } | |
403 | ||
404 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
405 | static int | |
406 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
407 | { | |
408 | return control & 0x1; | |
409 | } | |
410 | ||
411 | /* Is the breakpoint control value CONTROL initialized? */ | |
412 | static int | |
413 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
414 | { | |
415 | return control != 0; | |
416 | } | |
417 | ||
418 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
419 | static arm_hwbp_control_t | |
420 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
421 | { | |
422 | return control & ~0x1; | |
423 | } | |
424 | ||
425 | /* Are two break-/watch-points equal? */ | |
426 | static int | |
427 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
428 | const struct arm_linux_hw_breakpoint *p2) | |
429 | { | |
430 | return p1->address == p2->address && p1->control == p2->control; | |
431 | } | |
432 | ||
433 | /* Initialize the hardware breakpoint structure P for a breakpoint or | |
434 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
435 | Returns -1 if TYPE is unsupported, 0 if TYPE represents a breakpoint, | |
436 | and 1 if type represents a watchpoint. */ | |
437 | static int | |
438 | arm_linux_hw_point_initialize (char type, CORE_ADDR addr, int len, | |
439 | struct arm_linux_hw_breakpoint *p) | |
440 | { | |
441 | arm_hwbp_type hwbp_type; | |
442 | unsigned mask; | |
443 | ||
444 | /* Breakpoint/watchpoint types (GDB terminology): | |
445 | 0 = memory breakpoint for instructions | |
446 | (not supported; done via memory write instead) | |
447 | 1 = hardware breakpoint for instructions (supported) | |
448 | 2 = write watchpoint (supported) | |
449 | 3 = read watchpoint (supported) | |
450 | 4 = access watchpoint (supported). */ | |
451 | switch (type) | |
452 | { | |
453 | case '1': | |
454 | hwbp_type = arm_hwbp_break; | |
455 | break; | |
456 | case '2': | |
457 | hwbp_type = arm_hwbp_store; | |
458 | break; | |
459 | case '3': | |
460 | hwbp_type = arm_hwbp_load; | |
461 | break; | |
462 | case '4': | |
463 | hwbp_type = arm_hwbp_access; | |
464 | break; | |
465 | default: | |
466 | /* Unsupported. */ | |
467 | return -1; | |
468 | } | |
469 | ||
470 | if (hwbp_type == arm_hwbp_break) | |
471 | { | |
472 | /* For breakpoints, the length field encodes the mode. */ | |
473 | switch (len) | |
474 | { | |
475 | case 2: /* 16-bit Thumb mode breakpoint */ | |
476 | case 3: /* 32-bit Thumb mode breakpoint */ | |
477 | mask = 0x3 << (addr & 2); | |
478 | break; | |
479 | case 4: /* 32-bit ARM mode breakpoint */ | |
480 | mask = 0xf; | |
481 | break; | |
482 | default: | |
483 | /* Unsupported. */ | |
484 | return -1; | |
485 | } | |
486 | ||
487 | addr &= ~3; | |
488 | } | |
489 | else | |
490 | { | |
491 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
492 | CORE_ADDR aligned_addr; | |
493 | ||
494 | /* Can not set watchpoints for zero or negative lengths. */ | |
495 | if (len <= 0) | |
496 | return -1; | |
497 | /* The current ptrace interface can only handle watchpoints that are a | |
498 | power of 2. */ | |
499 | if ((len & (len - 1)) != 0) | |
500 | return -1; | |
501 | ||
502 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
503 | range covered by a watchpoint. */ | |
504 | aligned_addr = addr & ~(max_wp_length - 1); | |
505 | if (aligned_addr + max_wp_length < addr + len) | |
506 | return -1; | |
507 | ||
508 | mask = (1 << len) - 1; | |
509 | } | |
510 | ||
511 | p->address = (unsigned int) addr; | |
512 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
513 | ||
514 | return hwbp_type != arm_hwbp_break; | |
515 | } | |
516 | ||
517 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
518 | the current process. */ | |
519 | ||
520 | struct update_registers_data | |
521 | { | |
522 | int watch; | |
523 | int i; | |
524 | }; | |
525 | ||
526 | static int | |
527 | update_registers_callback (struct inferior_list_entry *entry, void *arg) | |
528 | { | |
529 | struct lwp_info *lwp = (struct lwp_info *) entry; | |
530 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
531 | ||
532 | /* Only update the threads of the current process. */ | |
533 | if (pid_of (lwp) == pid_of (get_thread_lwp (current_inferior))) | |
534 | { | |
535 | /* The actual update is done later just before resuming the lwp, | |
536 | we just mark that the registers need updating. */ | |
537 | if (data->watch) | |
538 | lwp->arch_private->wpts_changed[data->i] = 1; | |
539 | else | |
540 | lwp->arch_private->bpts_changed[data->i] = 1; | |
541 | ||
542 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
543 | we can update its breakpoint registers. */ | |
544 | if (!lwp->stopped) | |
545 | linux_stop_lwp (lwp); | |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | /* Insert hardware break-/watchpoint. */ | |
552 | static int | |
553 | arm_insert_point (char type, CORE_ADDR addr, int len) | |
554 | { | |
555 | struct process_info *proc = current_process (); | |
556 | struct arm_linux_hw_breakpoint p, *pts; | |
557 | int watch, i, count; | |
558 | ||
559 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
560 | if (watch < 0) | |
561 | { | |
562 | /* Unsupported. */ | |
563 | return 1; | |
564 | } | |
565 | ||
566 | if (watch) | |
567 | { | |
568 | count = arm_linux_get_hw_watchpoint_count (); | |
569 | pts = proc->private->arch_private->wpts; | |
570 | } | |
571 | else | |
572 | { | |
573 | count = arm_linux_get_hw_breakpoint_count (); | |
574 | pts = proc->private->arch_private->bpts; | |
575 | } | |
576 | ||
577 | for (i = 0; i < count; i++) | |
578 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
579 | { | |
580 | struct update_registers_data data = { watch, i }; | |
581 | pts[i] = p; | |
582 | find_inferior (&all_lwps, update_registers_callback, &data); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | /* We're out of watchpoints. */ | |
587 | return -1; | |
588 | } | |
589 | ||
590 | /* Remove hardware break-/watchpoint. */ | |
591 | static int | |
592 | arm_remove_point (char type, CORE_ADDR addr, int len) | |
593 | { | |
594 | struct process_info *proc = current_process (); | |
595 | struct arm_linux_hw_breakpoint p, *pts; | |
596 | int watch, i, count; | |
597 | ||
598 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
599 | if (watch < 0) | |
600 | { | |
601 | /* Unsupported. */ | |
602 | return -1; | |
603 | } | |
604 | ||
605 | if (watch) | |
606 | { | |
607 | count = arm_linux_get_hw_watchpoint_count (); | |
608 | pts = proc->private->arch_private->wpts; | |
609 | } | |
610 | else | |
611 | { | |
612 | count = arm_linux_get_hw_breakpoint_count (); | |
613 | pts = proc->private->arch_private->bpts; | |
614 | } | |
615 | ||
616 | for (i = 0; i < count; i++) | |
617 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
618 | { | |
619 | struct update_registers_data data = { watch, i }; | |
620 | pts[i].control = arm_hwbp_control_disable (pts[i].control); | |
621 | find_inferior (&all_lwps, update_registers_callback, &data); | |
622 | return 0; | |
623 | } | |
624 | ||
625 | /* No watchpoint matched. */ | |
626 | return -1; | |
627 | } | |
628 | ||
629 | /* Return whether current thread is stopped due to a watchpoint. */ | |
630 | static int | |
631 | arm_stopped_by_watchpoint (void) | |
632 | { | |
633 | struct lwp_info *lwp = get_thread_lwp (current_inferior); | |
a5362b9a | 634 | siginfo_t siginfo; |
09b4ad9f UW |
635 | |
636 | /* We must be able to set hardware watchpoints. */ | |
637 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
638 | return 0; | |
639 | ||
640 | /* Retrieve siginfo. */ | |
641 | errno = 0; | |
642 | ptrace (PTRACE_GETSIGINFO, lwpid_of (lwp), 0, &siginfo); | |
643 | if (errno != 0) | |
644 | return 0; | |
645 | ||
646 | /* This must be a hardware breakpoint. */ | |
647 | if (siginfo.si_signo != SIGTRAP | |
648 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
649 | return 0; | |
650 | ||
651 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
652 | a watchpoint. */ | |
653 | if (siginfo.si_errno >= 0) | |
654 | return 0; | |
655 | ||
656 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
657 | lwp->arch_private->stopped_data_address | |
658 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
659 | ||
660 | return 1; | |
661 | } | |
662 | ||
663 | /* Return data address that triggered watchpoint. Called only if | |
664 | arm_stopped_by_watchpoint returned true. */ | |
665 | static CORE_ADDR | |
666 | arm_stopped_data_address (void) | |
667 | { | |
668 | struct lwp_info *lwp = get_thread_lwp (current_inferior); | |
669 | return lwp->arch_private->stopped_data_address; | |
670 | } | |
671 | ||
672 | /* Called when a new process is created. */ | |
673 | static struct arch_process_info * | |
674 | arm_new_process (void) | |
675 | { | |
676 | struct arch_process_info *info = xcalloc (1, sizeof (*info)); | |
677 | return info; | |
678 | } | |
679 | ||
680 | /* Called when a new thread is detected. */ | |
681 | static struct arch_lwp_info * | |
682 | arm_new_thread (void) | |
683 | { | |
684 | struct arch_lwp_info *info = xcalloc (1, sizeof (*info)); | |
685 | int i; | |
686 | ||
687 | for (i = 0; i < MAX_BPTS; i++) | |
688 | info->bpts_changed[i] = 1; | |
689 | for (i = 0; i < MAX_WPTS; i++) | |
690 | info->wpts_changed[i] = 1; | |
691 | ||
692 | return info; | |
693 | } | |
694 | ||
695 | /* Called when resuming a thread. | |
696 | If the debug regs have changed, update the thread's copies. */ | |
697 | static void | |
698 | arm_prepare_to_resume (struct lwp_info *lwp) | |
699 | { | |
700 | int pid = lwpid_of (lwp); | |
701 | struct process_info *proc = find_process_pid (pid_of (lwp)); | |
702 | struct arch_process_info *proc_info = proc->private->arch_private; | |
703 | struct arch_lwp_info *lwp_info = lwp->arch_private; | |
704 | int i; | |
705 | ||
706 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
707 | if (lwp_info->bpts_changed[i]) | |
708 | { | |
709 | errno = 0; | |
710 | ||
711 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
712 | if (ptrace (PTRACE_SETHBPREGS, pid, ((i << 1) + 1), | |
713 | &proc_info->bpts[i].address) < 0) | |
71487fd7 | 714 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
715 | |
716 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
717 | if (ptrace (PTRACE_SETHBPREGS, pid, ((i << 1) + 2), | |
718 | &proc_info->bpts[i].control) < 0) | |
71487fd7 | 719 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
720 | |
721 | lwp_info->bpts_changed[i] = 0; | |
722 | } | |
723 | ||
724 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
725 | if (lwp_info->wpts_changed[i]) | |
726 | { | |
727 | errno = 0; | |
728 | ||
729 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
730 | if (ptrace (PTRACE_SETHBPREGS, pid, -((i << 1) + 1), | |
731 | &proc_info->wpts[i].address) < 0) | |
71487fd7 | 732 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
733 | |
734 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
735 | if (ptrace (PTRACE_SETHBPREGS, pid, -((i << 1) + 2), | |
736 | &proc_info->wpts[i].control) < 0) | |
71487fd7 | 737 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
738 | |
739 | lwp_info->wpts_changed[i] = 0; | |
740 | } | |
741 | } | |
742 | ||
743 | ||
58d6951d DJ |
744 | static int |
745 | arm_get_hwcap (unsigned long *valp) | |
746 | { | |
747 | unsigned char *data = alloca (8); | |
748 | int offset = 0; | |
749 | ||
750 | while ((*the_target->read_auxv) (offset, data, 8) == 8) | |
751 | { | |
752 | unsigned int *data_p = (unsigned int *)data; | |
753 | if (data_p[0] == AT_HWCAP) | |
754 | { | |
755 | *valp = data_p[1]; | |
756 | return 1; | |
757 | } | |
758 | ||
759 | offset += 8; | |
760 | } | |
761 | ||
762 | *valp = 0; | |
763 | return 0; | |
764 | } | |
765 | ||
766 | static void | |
767 | arm_arch_setup (void) | |
768 | { | |
71487fd7 UW |
769 | int pid = lwpid_of (get_thread_lwp (current_inferior)); |
770 | ||
771 | /* Query hardware watchpoint/breakpoint capabilities. */ | |
772 | arm_linux_init_hwbp_cap (pid); | |
773 | ||
58d6951d DJ |
774 | arm_hwcap = 0; |
775 | if (arm_get_hwcap (&arm_hwcap) == 0) | |
776 | { | |
777 | init_registers_arm (); | |
778 | return; | |
779 | } | |
780 | ||
781 | if (arm_hwcap & HWCAP_IWMMXT) | |
782 | { | |
783 | init_registers_arm_with_iwmmxt (); | |
784 | return; | |
785 | } | |
786 | ||
787 | if (arm_hwcap & HWCAP_VFP) | |
788 | { | |
58d6951d DJ |
789 | char *buf; |
790 | ||
791 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
792 | it with VFP. */ | |
793 | if (arm_hwcap & HWCAP_NEON) | |
794 | init_registers_arm_with_neon (); | |
795 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) | |
796 | init_registers_arm_with_vfpv3 (); | |
797 | else | |
798 | init_registers_arm_with_vfpv2 (); | |
799 | ||
800 | /* Now make sure that the kernel supports reading these | |
801 | registers. Support was added in 2.6.30. */ | |
58d6951d | 802 | errno = 0; |
c3e8aadd | 803 | buf = xmalloc (32 * 8 + 4); |
58d6951d DJ |
804 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
805 | && errno == EIO) | |
806 | { | |
807 | arm_hwcap = 0; | |
808 | init_registers_arm (); | |
809 | } | |
810 | free (buf); | |
811 | ||
812 | return; | |
813 | } | |
814 | ||
815 | /* The default configuration uses legacy FPA registers, probably | |
816 | simulated. */ | |
817 | init_registers_arm (); | |
818 | } | |
819 | ||
fb1e4ffc | 820 | struct regset_info target_regsets[] = { |
1570b33e | 821 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4, |
fb1e4ffc DJ |
822 | GENERAL_REGS, |
823 | arm_fill_gregset, arm_store_gregset }, | |
1570b33e | 824 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4, |
fb1e4ffc DJ |
825 | EXTENDED_REGS, |
826 | arm_fill_wmmxregset, arm_store_wmmxregset }, | |
1570b33e | 827 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4, |
58d6951d DJ |
828 | EXTENDED_REGS, |
829 | arm_fill_vfpregset, arm_store_vfpregset }, | |
1570b33e | 830 | { 0, 0, 0, -1, -1, NULL, NULL } |
fb1e4ffc DJ |
831 | }; |
832 | ||
2ec06d2e | 833 | struct linux_target_ops the_low_target = { |
58d6951d | 834 | arm_arch_setup, |
2ec06d2e DJ |
835 | arm_num_regs, |
836 | arm_regmap, | |
1faeff08 | 837 | NULL, |
2ec06d2e DJ |
838 | arm_cannot_fetch_register, |
839 | arm_cannot_store_register, | |
c14dfd32 | 840 | NULL, /* fetch_register */ |
0d62e5e8 DJ |
841 | arm_get_pc, |
842 | arm_set_pc, | |
aeb75bf5 DJ |
843 | |
844 | /* Define an ARM-mode breakpoint; we only set breakpoints in the C | |
845 | library, which is most likely to be ARM. If the kernel supports | |
846 | clone events, we will never insert a breakpoint, so even a Thumb | |
847 | C library will work; so will mixing EABI/non-EABI gdbserver and | |
848 | application. */ | |
9d1fb177 | 849 | #ifndef __ARM_EABI__ |
f450004a | 850 | (const unsigned char *) &arm_breakpoint, |
9d1fb177 DJ |
851 | #else |
852 | (const unsigned char *) &arm_eabi_breakpoint, | |
853 | #endif | |
0d62e5e8 | 854 | arm_breakpoint_len, |
3b2fc2ea | 855 | arm_reinsert_addr, |
0d62e5e8 DJ |
856 | 0, |
857 | arm_breakpoint_at, | |
09b4ad9f UW |
858 | arm_insert_point, |
859 | arm_remove_point, | |
860 | arm_stopped_by_watchpoint, | |
861 | arm_stopped_data_address, | |
862 | NULL, /* collect_ptrace_register */ | |
863 | NULL, /* supply_ptrace_register */ | |
864 | NULL, /* siginfo_fixup */ | |
865 | arm_new_process, | |
866 | arm_new_thread, | |
867 | arm_prepare_to_resume, | |
2ec06d2e | 868 | }; |