Commit | Line | Data |
---|---|---|
0a30fbc4 | 1 | /* GNU/Linux/ARM specific low level interface, for the remote server for GDB. |
32d0add0 | 2 | Copyright (C) 1995-2015 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
deca266c | 21 | #include "arch/arm.h" |
bd9e6534 | 22 | #include "linux-aarch32-low.h" |
0a30fbc4 | 23 | |
bd9e6534 | 24 | #include <sys/uio.h> |
3743bb4f DE |
25 | /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h. |
26 | On Bionic elf.h and linux/elf.h have conflicting definitions. */ | |
27 | #ifndef ELFMAG0 | |
58d6951d | 28 | #include <elf.h> |
3743bb4f | 29 | #endif |
5826e159 | 30 | #include "nat/gdb_ptrace.h" |
09b4ad9f | 31 | #include <signal.h> |
9308fc88 | 32 | |
8689682c AT |
33 | #include "arch/arm.h" |
34 | ||
58d6951d | 35 | /* Defined in auto-generated files. */ |
d05b4ac3 | 36 | void init_registers_arm (void); |
3aee8918 PA |
37 | extern const struct target_desc *tdesc_arm; |
38 | ||
d05b4ac3 | 39 | void init_registers_arm_with_iwmmxt (void); |
3aee8918 PA |
40 | extern const struct target_desc *tdesc_arm_with_iwmmxt; |
41 | ||
58d6951d | 42 | void init_registers_arm_with_vfpv2 (void); |
3aee8918 PA |
43 | extern const struct target_desc *tdesc_arm_with_vfpv2; |
44 | ||
58d6951d | 45 | void init_registers_arm_with_vfpv3 (void); |
3aee8918 PA |
46 | extern const struct target_desc *tdesc_arm_with_vfpv3; |
47 | ||
9308fc88 DJ |
48 | #ifndef PTRACE_GET_THREAD_AREA |
49 | #define PTRACE_GET_THREAD_AREA 22 | |
50 | #endif | |
51 | ||
fb1e4ffc DJ |
52 | #ifndef PTRACE_GETWMMXREGS |
53 | # define PTRACE_GETWMMXREGS 18 | |
54 | # define PTRACE_SETWMMXREGS 19 | |
55 | #endif | |
56 | ||
58d6951d DJ |
57 | #ifndef PTRACE_GETVFPREGS |
58 | # define PTRACE_GETVFPREGS 27 | |
59 | # define PTRACE_SETVFPREGS 28 | |
60 | #endif | |
61 | ||
09b4ad9f UW |
62 | #ifndef PTRACE_GETHBPREGS |
63 | #define PTRACE_GETHBPREGS 29 | |
64 | #define PTRACE_SETHBPREGS 30 | |
65 | #endif | |
66 | ||
67 | /* Information describing the hardware breakpoint capabilities. */ | |
71487fd7 | 68 | static struct |
09b4ad9f UW |
69 | { |
70 | unsigned char arch; | |
71 | unsigned char max_wp_length; | |
72 | unsigned char wp_count; | |
73 | unsigned char bp_count; | |
71487fd7 | 74 | } arm_linux_hwbp_cap; |
09b4ad9f UW |
75 | |
76 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
77 | typedef enum | |
78 | { | |
79 | arm_hwbp_break = 0, | |
80 | arm_hwbp_load = 1, | |
81 | arm_hwbp_store = 2, | |
82 | arm_hwbp_access = 3 | |
83 | } arm_hwbp_type; | |
84 | ||
8689682c AT |
85 | /* Enum describing the different kinds of breakpoints. */ |
86 | enum arm_breakpoint_kinds | |
87 | { | |
88 | ARM_BP_KIND_THUMB = 2, | |
89 | ARM_BP_KIND_THUMB2 = 3, | |
90 | ARM_BP_KIND_ARM = 4, | |
91 | }; | |
92 | ||
09b4ad9f UW |
93 | /* Type describing an ARM Hardware Breakpoint Control register value. */ |
94 | typedef unsigned int arm_hwbp_control_t; | |
95 | ||
96 | /* Structure used to keep track of hardware break-/watch-points. */ | |
97 | struct arm_linux_hw_breakpoint | |
98 | { | |
99 | /* Address to break on, or being watched. */ | |
100 | unsigned int address; | |
101 | /* Control register for break-/watch- point. */ | |
102 | arm_hwbp_control_t control; | |
103 | }; | |
104 | ||
105 | /* Since we cannot dynamically allocate subfields of arch_process_info, | |
106 | assume a maximum number of supported break-/watchpoints. */ | |
107 | #define MAX_BPTS 32 | |
108 | #define MAX_WPTS 32 | |
109 | ||
110 | /* Per-process arch-specific data we want to keep. */ | |
111 | struct arch_process_info | |
112 | { | |
113 | /* Hardware breakpoints for this process. */ | |
114 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
115 | /* Hardware watchpoints for this process. */ | |
116 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
117 | }; | |
118 | ||
119 | /* Per-thread arch-specific data we want to keep. */ | |
120 | struct arch_lwp_info | |
121 | { | |
122 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
123 | char bpts_changed[MAX_BPTS]; | |
124 | char wpts_changed[MAX_WPTS]; | |
125 | /* Cached stopped data address. */ | |
126 | CORE_ADDR stopped_data_address; | |
127 | }; | |
128 | ||
58d6951d DJ |
129 | /* These are in <asm/elf.h> in current kernels. */ |
130 | #define HWCAP_VFP 64 | |
131 | #define HWCAP_IWMMXT 512 | |
132 | #define HWCAP_NEON 4096 | |
133 | #define HWCAP_VFPv3 8192 | |
134 | #define HWCAP_VFPv3D16 16384 | |
135 | ||
0a30fbc4 DJ |
136 | #ifdef HAVE_SYS_REG_H |
137 | #include <sys/reg.h> | |
138 | #endif | |
139 | ||
23ce3b1c | 140 | #define arm_num_regs 26 |
0a30fbc4 | 141 | |
2ec06d2e | 142 | static int arm_regmap[] = { |
0a30fbc4 DJ |
143 | 0, 4, 8, 12, 16, 20, 24, 28, |
144 | 32, 36, 40, 44, 48, 52, 56, 60, | |
23ce3b1c DJ |
145 | -1, -1, -1, -1, -1, -1, -1, -1, -1, |
146 | 64 | |
0a30fbc4 DJ |
147 | }; |
148 | ||
2ec06d2e DJ |
149 | static int |
150 | arm_cannot_store_register (int regno) | |
0a30fbc4 | 151 | { |
2ec06d2e | 152 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
153 | } |
154 | ||
2ec06d2e DJ |
155 | static int |
156 | arm_cannot_fetch_register (int regno) | |
0a30fbc4 | 157 | { |
2ec06d2e | 158 | return (regno >= arm_num_regs); |
0a30fbc4 DJ |
159 | } |
160 | ||
fb1e4ffc | 161 | static void |
442ea881 | 162 | arm_fill_wmmxregset (struct regcache *regcache, void *buf) |
fb1e4ffc DJ |
163 | { |
164 | int i; | |
165 | ||
89abb039 | 166 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
167 | return; |
168 | ||
fb1e4ffc | 169 | for (i = 0; i < 16; i++) |
442ea881 | 170 | collect_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
171 | |
172 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
173 | for (i = 0; i < 6; i++) | |
442ea881 PA |
174 | collect_register (regcache, arm_num_regs + i + 16, |
175 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
176 | } |
177 | ||
178 | static void | |
442ea881 | 179 | arm_store_wmmxregset (struct regcache *regcache, const void *buf) |
fb1e4ffc DJ |
180 | { |
181 | int i; | |
182 | ||
89abb039 | 183 | if (regcache->tdesc != tdesc_arm_with_iwmmxt) |
58d6951d DJ |
184 | return; |
185 | ||
fb1e4ffc | 186 | for (i = 0; i < 16; i++) |
442ea881 | 187 | supply_register (regcache, arm_num_regs + i, (char *) buf + i * 8); |
fb1e4ffc DJ |
188 | |
189 | /* We only have access to wcssf, wcasf, and wcgr0-wcgr3. */ | |
190 | for (i = 0; i < 6; i++) | |
442ea881 PA |
191 | supply_register (regcache, arm_num_regs + i + 16, |
192 | (char *) buf + 16 * 8 + i * 4); | |
fb1e4ffc DJ |
193 | } |
194 | ||
58d6951d | 195 | static void |
442ea881 | 196 | arm_fill_vfpregset (struct regcache *regcache, void *buf) |
58d6951d | 197 | { |
bd9e6534 | 198 | int num; |
58d6951d | 199 | |
89abb039 YQ |
200 | if (regcache->tdesc == tdesc_arm_with_neon |
201 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 202 | num = 32; |
89abb039 | 203 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 204 | num = 16; |
89abb039 YQ |
205 | else |
206 | return; | |
58d6951d | 207 | |
bd9e6534 | 208 | arm_fill_vfpregset_num (regcache, buf, num); |
58d6951d DJ |
209 | } |
210 | ||
211 | static void | |
442ea881 | 212 | arm_store_vfpregset (struct regcache *regcache, const void *buf) |
58d6951d | 213 | { |
bd9e6534 | 214 | int num; |
58d6951d | 215 | |
89abb039 YQ |
216 | if (regcache->tdesc == tdesc_arm_with_neon |
217 | || regcache->tdesc == tdesc_arm_with_vfpv3) | |
58d6951d | 218 | num = 32; |
89abb039 | 219 | else if (regcache->tdesc == tdesc_arm_with_vfpv2) |
58d6951d | 220 | num = 16; |
89abb039 YQ |
221 | else |
222 | return; | |
58d6951d | 223 | |
bd9e6534 | 224 | arm_store_vfpregset_num (regcache, buf, num); |
58d6951d | 225 | } |
fb1e4ffc | 226 | |
d677d77d DJ |
227 | extern int debug_threads; |
228 | ||
0d62e5e8 | 229 | static CORE_ADDR |
442ea881 | 230 | arm_get_pc (struct regcache *regcache) |
0d62e5e8 DJ |
231 | { |
232 | unsigned long pc; | |
442ea881 | 233 | collect_register_by_name (regcache, "pc", &pc); |
d677d77d | 234 | if (debug_threads) |
87ce2a04 | 235 | debug_printf ("stop pc is %08lx\n", pc); |
0d62e5e8 DJ |
236 | return pc; |
237 | } | |
238 | ||
239 | static void | |
442ea881 | 240 | arm_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 DJ |
241 | { |
242 | unsigned long newpc = pc; | |
442ea881 | 243 | supply_register_by_name (regcache, "pc", &newpc); |
0d62e5e8 DJ |
244 | } |
245 | ||
aeb75bf5 | 246 | /* Correct in either endianness. */ |
b0b4b501 | 247 | #define arm_abi_breakpoint 0xef9f0001UL |
0d62e5e8 | 248 | |
9d1fb177 DJ |
249 | /* For new EABI binaries. We recognize it regardless of which ABI |
250 | is used for gdbserver, so single threaded debugging should work | |
251 | OK, but for multi-threaded debugging we only insert the current | |
252 | ABI's breakpoint instruction. For now at least. */ | |
b0b4b501 AT |
253 | #define arm_eabi_breakpoint 0xe7f001f0UL |
254 | ||
255 | #ifndef __ARM_EABI__ | |
256 | static const unsigned long arm_breakpoint = arm_abi_breakpoint; | |
257 | #else | |
258 | static const unsigned long arm_breakpoint = arm_eabi_breakpoint; | |
259 | #endif | |
260 | ||
261 | #define arm_breakpoint_len 4 | |
262 | static const unsigned short thumb_breakpoint = 0xde01; | |
263 | #define thumb_breakpoint_len 2 | |
264 | static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 }; | |
265 | #define thumb2_breakpoint_len 4 | |
9d1fb177 | 266 | |
0d62e5e8 DJ |
267 | static int |
268 | arm_breakpoint_at (CORE_ADDR where) | |
269 | { | |
0bfdf32f | 270 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
aeb75bf5 | 271 | unsigned long cpsr; |
0d62e5e8 | 272 | |
442ea881 | 273 | collect_register_by_name (regcache, "cpsr", &cpsr); |
0d62e5e8 | 274 | |
aeb75bf5 DJ |
275 | if (cpsr & 0x20) |
276 | { | |
277 | /* Thumb mode. */ | |
278 | unsigned short insn; | |
9d1fb177 | 279 | |
aeb75bf5 DJ |
280 | (*the_target->read_memory) (where, (unsigned char *) &insn, 2); |
281 | if (insn == thumb_breakpoint) | |
282 | return 1; | |
177321bd DJ |
283 | |
284 | if (insn == thumb2_breakpoint[0]) | |
285 | { | |
286 | (*the_target->read_memory) (where + 2, (unsigned char *) &insn, 2); | |
287 | if (insn == thumb2_breakpoint[1]) | |
288 | return 1; | |
289 | } | |
aeb75bf5 DJ |
290 | } |
291 | else | |
292 | { | |
293 | /* ARM mode. */ | |
294 | unsigned long insn; | |
295 | ||
296 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); | |
b0b4b501 | 297 | if (insn == arm_abi_breakpoint) |
aeb75bf5 DJ |
298 | return 1; |
299 | ||
300 | if (insn == arm_eabi_breakpoint) | |
301 | return 1; | |
302 | } | |
9d1fb177 | 303 | |
0d62e5e8 DJ |
304 | return 0; |
305 | } | |
306 | ||
3b2fc2ea DJ |
307 | /* We only place breakpoints in empty marker functions, and thread locking |
308 | is outside of the function. So rather than importing software single-step, | |
309 | we can just run until exit. */ | |
310 | static CORE_ADDR | |
442ea881 | 311 | arm_reinsert_addr (void) |
3b2fc2ea | 312 | { |
0bfdf32f | 313 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
3b2fc2ea | 314 | unsigned long pc; |
442ea881 | 315 | collect_register_by_name (regcache, "lr", &pc); |
3b2fc2ea DJ |
316 | return pc; |
317 | } | |
318 | ||
9308fc88 DJ |
319 | /* Fetch the thread-local storage pointer for libthread_db. */ |
320 | ||
321 | ps_err_e | |
322 | ps_get_thread_area (const struct ps_prochandle *ph, | |
1b3f6016 | 323 | lwpid_t lwpid, int idx, void **base) |
9308fc88 DJ |
324 | { |
325 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
326 | return PS_ERR; | |
327 | ||
328 | /* IDX is the bias from the thread pointer to the beginning of the | |
329 | thread descriptor. It has to be subtracted due to implementation | |
330 | quirks in libthread_db. */ | |
331 | *base = (void *) ((char *)*base - idx); | |
332 | ||
333 | return PS_OK; | |
334 | } | |
335 | ||
09b4ad9f | 336 | |
71487fd7 UW |
337 | /* Query Hardware Breakpoint information for the target we are attached to |
338 | (using PID as ptrace argument) and set up arm_linux_hwbp_cap. */ | |
339 | static void | |
340 | arm_linux_init_hwbp_cap (int pid) | |
09b4ad9f | 341 | { |
71487fd7 | 342 | unsigned int val; |
09b4ad9f | 343 | |
71487fd7 UW |
344 | if (ptrace (PTRACE_GETHBPREGS, pid, 0, &val) < 0) |
345 | return; | |
09b4ad9f | 346 | |
71487fd7 UW |
347 | arm_linux_hwbp_cap.arch = (unsigned char)((val >> 24) & 0xff); |
348 | if (arm_linux_hwbp_cap.arch == 0) | |
349 | return; | |
09b4ad9f | 350 | |
71487fd7 UW |
351 | arm_linux_hwbp_cap.max_wp_length = (unsigned char)((val >> 16) & 0xff); |
352 | arm_linux_hwbp_cap.wp_count = (unsigned char)((val >> 8) & 0xff); | |
353 | arm_linux_hwbp_cap.bp_count = (unsigned char)(val & 0xff); | |
09b4ad9f | 354 | |
71487fd7 UW |
355 | if (arm_linux_hwbp_cap.wp_count > MAX_WPTS) |
356 | internal_error (__FILE__, __LINE__, "Unsupported number of watchpoints"); | |
357 | if (arm_linux_hwbp_cap.bp_count > MAX_BPTS) | |
358 | internal_error (__FILE__, __LINE__, "Unsupported number of breakpoints"); | |
09b4ad9f UW |
359 | } |
360 | ||
361 | /* How many hardware breakpoints are available? */ | |
362 | static int | |
363 | arm_linux_get_hw_breakpoint_count (void) | |
364 | { | |
71487fd7 | 365 | return arm_linux_hwbp_cap.bp_count; |
09b4ad9f UW |
366 | } |
367 | ||
368 | /* How many hardware watchpoints are available? */ | |
369 | static int | |
370 | arm_linux_get_hw_watchpoint_count (void) | |
371 | { | |
71487fd7 | 372 | return arm_linux_hwbp_cap.wp_count; |
09b4ad9f UW |
373 | } |
374 | ||
375 | /* Maximum length of area watched by hardware watchpoint. */ | |
376 | static int | |
377 | arm_linux_get_hw_watchpoint_max_length (void) | |
378 | { | |
71487fd7 | 379 | return arm_linux_hwbp_cap.max_wp_length; |
09b4ad9f UW |
380 | } |
381 | ||
382 | /* Initialize an ARM hardware break-/watch-point control register value. | |
383 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
384 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
385 | */ | |
386 | static arm_hwbp_control_t | |
387 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
388 | arm_hwbp_type hwbp_type, | |
389 | int enable) | |
390 | { | |
391 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
392 | gdb_assert (hwbp_type != arm_hwbp_break | |
393 | || ((byte_address_select & 0xfU) != 0)); | |
394 | ||
395 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
396 | } | |
397 | ||
398 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
399 | static int | |
400 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
401 | { | |
402 | return control & 0x1; | |
403 | } | |
404 | ||
405 | /* Is the breakpoint control value CONTROL initialized? */ | |
406 | static int | |
407 | arm_hwbp_control_is_initialized (arm_hwbp_control_t control) | |
408 | { | |
409 | return control != 0; | |
410 | } | |
411 | ||
412 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
413 | static arm_hwbp_control_t | |
414 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
415 | { | |
416 | return control & ~0x1; | |
417 | } | |
418 | ||
419 | /* Are two break-/watch-points equal? */ | |
420 | static int | |
421 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
422 | const struct arm_linux_hw_breakpoint *p2) | |
423 | { | |
424 | return p1->address == p2->address && p1->control == p2->control; | |
425 | } | |
426 | ||
802e8e6d PA |
427 | /* Convert a raw breakpoint type to an enum arm_hwbp_type. */ |
428 | ||
429 | static int | |
430 | raw_bkpt_type_to_arm_hwbp_type (enum raw_bkpt_type raw_type) | |
431 | { | |
432 | switch (raw_type) | |
433 | { | |
434 | case raw_bkpt_type_hw: | |
435 | return arm_hwbp_break; | |
436 | case raw_bkpt_type_write_wp: | |
437 | return arm_hwbp_store; | |
438 | case raw_bkpt_type_read_wp: | |
439 | return arm_hwbp_load; | |
440 | case raw_bkpt_type_access_wp: | |
441 | return arm_hwbp_access; | |
442 | default: | |
443 | gdb_assert_not_reached ("unhandled raw type"); | |
444 | } | |
445 | } | |
446 | ||
09b4ad9f UW |
447 | /* Initialize the hardware breakpoint structure P for a breakpoint or |
448 | watchpoint at ADDR to LEN. The type of watchpoint is given in TYPE. | |
b62e2b27 UW |
449 | Returns -1 if TYPE is unsupported, or -2 if the particular combination |
450 | of ADDR and LEN cannot be implemented. Otherwise, returns 0 if TYPE | |
451 | represents a breakpoint and 1 if type represents a watchpoint. */ | |
09b4ad9f | 452 | static int |
802e8e6d PA |
453 | arm_linux_hw_point_initialize (enum raw_bkpt_type raw_type, CORE_ADDR addr, |
454 | int len, struct arm_linux_hw_breakpoint *p) | |
09b4ad9f UW |
455 | { |
456 | arm_hwbp_type hwbp_type; | |
457 | unsigned mask; | |
458 | ||
802e8e6d | 459 | hwbp_type = raw_bkpt_type_to_arm_hwbp_type (raw_type); |
09b4ad9f UW |
460 | |
461 | if (hwbp_type == arm_hwbp_break) | |
462 | { | |
463 | /* For breakpoints, the length field encodes the mode. */ | |
464 | switch (len) | |
465 | { | |
466 | case 2: /* 16-bit Thumb mode breakpoint */ | |
467 | case 3: /* 32-bit Thumb mode breakpoint */ | |
fcf303ab UW |
468 | mask = 0x3; |
469 | addr &= ~1; | |
09b4ad9f UW |
470 | break; |
471 | case 4: /* 32-bit ARM mode breakpoint */ | |
472 | mask = 0xf; | |
fcf303ab | 473 | addr &= ~3; |
09b4ad9f UW |
474 | break; |
475 | default: | |
476 | /* Unsupported. */ | |
b62e2b27 | 477 | return -2; |
09b4ad9f | 478 | } |
09b4ad9f UW |
479 | } |
480 | else | |
481 | { | |
482 | CORE_ADDR max_wp_length = arm_linux_get_hw_watchpoint_max_length (); | |
483 | CORE_ADDR aligned_addr; | |
484 | ||
485 | /* Can not set watchpoints for zero or negative lengths. */ | |
486 | if (len <= 0) | |
b62e2b27 | 487 | return -2; |
09b4ad9f UW |
488 | /* The current ptrace interface can only handle watchpoints that are a |
489 | power of 2. */ | |
490 | if ((len & (len - 1)) != 0) | |
b62e2b27 | 491 | return -2; |
09b4ad9f UW |
492 | |
493 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
494 | range covered by a watchpoint. */ | |
495 | aligned_addr = addr & ~(max_wp_length - 1); | |
496 | if (aligned_addr + max_wp_length < addr + len) | |
b62e2b27 | 497 | return -2; |
09b4ad9f UW |
498 | |
499 | mask = (1 << len) - 1; | |
500 | } | |
501 | ||
502 | p->address = (unsigned int) addr; | |
503 | p->control = arm_hwbp_control_initialize (mask, hwbp_type, 1); | |
504 | ||
505 | return hwbp_type != arm_hwbp_break; | |
506 | } | |
507 | ||
508 | /* Callback to mark a watch-/breakpoint to be updated in all threads of | |
509 | the current process. */ | |
510 | ||
511 | struct update_registers_data | |
512 | { | |
513 | int watch; | |
514 | int i; | |
515 | }; | |
516 | ||
517 | static int | |
518 | update_registers_callback (struct inferior_list_entry *entry, void *arg) | |
519 | { | |
d86d4aaf DE |
520 | struct thread_info *thread = (struct thread_info *) entry; |
521 | struct lwp_info *lwp = get_thread_lwp (thread); | |
09b4ad9f UW |
522 | struct update_registers_data *data = (struct update_registers_data *) arg; |
523 | ||
524 | /* Only update the threads of the current process. */ | |
0bfdf32f | 525 | if (pid_of (thread) == pid_of (current_thread)) |
09b4ad9f UW |
526 | { |
527 | /* The actual update is done later just before resuming the lwp, | |
528 | we just mark that the registers need updating. */ | |
529 | if (data->watch) | |
530 | lwp->arch_private->wpts_changed[data->i] = 1; | |
531 | else | |
532 | lwp->arch_private->bpts_changed[data->i] = 1; | |
533 | ||
534 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
535 | we can update its breakpoint registers. */ | |
536 | if (!lwp->stopped) | |
537 | linux_stop_lwp (lwp); | |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
802e8e6d PA |
543 | static int |
544 | arm_supports_z_point_type (char z_type) | |
545 | { | |
546 | switch (z_type) | |
547 | { | |
abeead09 | 548 | case Z_PACKET_SW_BP: |
802e8e6d PA |
549 | case Z_PACKET_HW_BP: |
550 | case Z_PACKET_WRITE_WP: | |
551 | case Z_PACKET_READ_WP: | |
552 | case Z_PACKET_ACCESS_WP: | |
553 | return 1; | |
554 | default: | |
555 | /* Leave the handling of sw breakpoints with the gdb client. */ | |
556 | return 0; | |
557 | } | |
558 | } | |
559 | ||
09b4ad9f UW |
560 | /* Insert hardware break-/watchpoint. */ |
561 | static int | |
802e8e6d PA |
562 | arm_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
563 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
564 | { |
565 | struct process_info *proc = current_process (); | |
566 | struct arm_linux_hw_breakpoint p, *pts; | |
567 | int watch, i, count; | |
568 | ||
569 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
570 | if (watch < 0) | |
571 | { | |
572 | /* Unsupported. */ | |
b62e2b27 | 573 | return watch == -1 ? 1 : -1; |
09b4ad9f UW |
574 | } |
575 | ||
576 | if (watch) | |
577 | { | |
578 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 579 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
580 | } |
581 | else | |
582 | { | |
583 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 584 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
585 | } |
586 | ||
587 | for (i = 0; i < count; i++) | |
588 | if (!arm_hwbp_control_is_enabled (pts[i].control)) | |
589 | { | |
590 | struct update_registers_data data = { watch, i }; | |
591 | pts[i] = p; | |
d86d4aaf | 592 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
593 | return 0; |
594 | } | |
595 | ||
596 | /* We're out of watchpoints. */ | |
597 | return -1; | |
598 | } | |
599 | ||
600 | /* Remove hardware break-/watchpoint. */ | |
601 | static int | |
802e8e6d PA |
602 | arm_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
603 | int len, struct raw_breakpoint *bp) | |
09b4ad9f UW |
604 | { |
605 | struct process_info *proc = current_process (); | |
606 | struct arm_linux_hw_breakpoint p, *pts; | |
607 | int watch, i, count; | |
608 | ||
609 | watch = arm_linux_hw_point_initialize (type, addr, len, &p); | |
610 | if (watch < 0) | |
611 | { | |
612 | /* Unsupported. */ | |
613 | return -1; | |
614 | } | |
615 | ||
616 | if (watch) | |
617 | { | |
618 | count = arm_linux_get_hw_watchpoint_count (); | |
fe978cb0 | 619 | pts = proc->priv->arch_private->wpts; |
09b4ad9f UW |
620 | } |
621 | else | |
622 | { | |
623 | count = arm_linux_get_hw_breakpoint_count (); | |
fe978cb0 | 624 | pts = proc->priv->arch_private->bpts; |
09b4ad9f UW |
625 | } |
626 | ||
627 | for (i = 0; i < count; i++) | |
628 | if (arm_linux_hw_breakpoint_equal (&p, pts + i)) | |
629 | { | |
630 | struct update_registers_data data = { watch, i }; | |
631 | pts[i].control = arm_hwbp_control_disable (pts[i].control); | |
d86d4aaf | 632 | find_inferior (&all_threads, update_registers_callback, &data); |
09b4ad9f UW |
633 | return 0; |
634 | } | |
635 | ||
636 | /* No watchpoint matched. */ | |
637 | return -1; | |
638 | } | |
639 | ||
640 | /* Return whether current thread is stopped due to a watchpoint. */ | |
641 | static int | |
642 | arm_stopped_by_watchpoint (void) | |
643 | { | |
0bfdf32f | 644 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
a5362b9a | 645 | siginfo_t siginfo; |
09b4ad9f UW |
646 | |
647 | /* We must be able to set hardware watchpoints. */ | |
648 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
649 | return 0; | |
650 | ||
651 | /* Retrieve siginfo. */ | |
652 | errno = 0; | |
0bfdf32f | 653 | ptrace (PTRACE_GETSIGINFO, lwpid_of (current_thread), 0, &siginfo); |
09b4ad9f UW |
654 | if (errno != 0) |
655 | return 0; | |
656 | ||
657 | /* This must be a hardware breakpoint. */ | |
658 | if (siginfo.si_signo != SIGTRAP | |
659 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
660 | return 0; | |
661 | ||
662 | /* If we are in a positive slot then we're looking at a breakpoint and not | |
663 | a watchpoint. */ | |
664 | if (siginfo.si_errno >= 0) | |
665 | return 0; | |
666 | ||
667 | /* Cache stopped data address for use by arm_stopped_data_address. */ | |
668 | lwp->arch_private->stopped_data_address | |
669 | = (CORE_ADDR) (uintptr_t) siginfo.si_addr; | |
670 | ||
671 | return 1; | |
672 | } | |
673 | ||
674 | /* Return data address that triggered watchpoint. Called only if | |
675 | arm_stopped_by_watchpoint returned true. */ | |
676 | static CORE_ADDR | |
677 | arm_stopped_data_address (void) | |
678 | { | |
0bfdf32f | 679 | struct lwp_info *lwp = get_thread_lwp (current_thread); |
09b4ad9f UW |
680 | return lwp->arch_private->stopped_data_address; |
681 | } | |
682 | ||
683 | /* Called when a new process is created. */ | |
684 | static struct arch_process_info * | |
685 | arm_new_process (void) | |
686 | { | |
8d749320 | 687 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
09b4ad9f UW |
688 | return info; |
689 | } | |
690 | ||
691 | /* Called when a new thread is detected. */ | |
34c703da GB |
692 | static void |
693 | arm_new_thread (struct lwp_info *lwp) | |
09b4ad9f | 694 | { |
8d749320 | 695 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
09b4ad9f UW |
696 | int i; |
697 | ||
698 | for (i = 0; i < MAX_BPTS; i++) | |
699 | info->bpts_changed[i] = 1; | |
700 | for (i = 0; i < MAX_WPTS; i++) | |
701 | info->wpts_changed[i] = 1; | |
702 | ||
34c703da | 703 | lwp->arch_private = info; |
09b4ad9f UW |
704 | } |
705 | ||
3a8a0396 DB |
706 | static void |
707 | arm_new_fork (struct process_info *parent, struct process_info *child) | |
708 | { | |
69291610 HW |
709 | struct arch_process_info *parent_proc_info; |
710 | struct arch_process_info *child_proc_info; | |
3a8a0396 DB |
711 | struct lwp_info *child_lwp; |
712 | struct arch_lwp_info *child_lwp_info; | |
713 | int i; | |
714 | ||
715 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
716 | gdb_assert (parent->priv != NULL |
717 | && parent->priv->arch_private != NULL); | |
718 | gdb_assert (child->priv != NULL | |
719 | && child->priv->arch_private != NULL); | |
3a8a0396 | 720 | |
69291610 HW |
721 | parent_proc_info = parent->priv->arch_private; |
722 | child_proc_info = child->priv->arch_private; | |
723 | ||
3a8a0396 DB |
724 | /* Linux kernel before 2.6.33 commit |
725 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
726 | will inherit hardware debug registers from parent | |
727 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
728 | zeroed debug registers. | |
729 | ||
730 | GDB core assumes the child inherits the watchpoints/hw | |
731 | breakpoints of the parent, and will remove them all from the | |
732 | forked off process. Copy the debug registers mirrors into the | |
733 | new process so that all breakpoints and watchpoints can be | |
734 | removed together. The debug registers mirror will become zeroed | |
735 | in the end before detaching the forked off process, thus making | |
736 | this compatible with older Linux kernels too. */ | |
737 | ||
738 | *child_proc_info = *parent_proc_info; | |
739 | ||
740 | /* Mark all the hardware breakpoints and watchpoints as changed to | |
741 | make sure that the registers will be updated. */ | |
742 | child_lwp = find_lwp_pid (ptid_of (child)); | |
743 | child_lwp_info = child_lwp->arch_private; | |
744 | for (i = 0; i < MAX_BPTS; i++) | |
745 | child_lwp_info->bpts_changed[i] = 1; | |
746 | for (i = 0; i < MAX_WPTS; i++) | |
747 | child_lwp_info->wpts_changed[i] = 1; | |
748 | } | |
749 | ||
09b4ad9f UW |
750 | /* Called when resuming a thread. |
751 | If the debug regs have changed, update the thread's copies. */ | |
752 | static void | |
753 | arm_prepare_to_resume (struct lwp_info *lwp) | |
754 | { | |
d86d4aaf DE |
755 | struct thread_info *thread = get_lwp_thread (lwp); |
756 | int pid = lwpid_of (thread); | |
757 | struct process_info *proc = find_process_pid (pid_of (thread)); | |
fe978cb0 | 758 | struct arch_process_info *proc_info = proc->priv->arch_private; |
09b4ad9f UW |
759 | struct arch_lwp_info *lwp_info = lwp->arch_private; |
760 | int i; | |
761 | ||
762 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) | |
763 | if (lwp_info->bpts_changed[i]) | |
764 | { | |
765 | errno = 0; | |
766 | ||
767 | if (arm_hwbp_control_is_enabled (proc_info->bpts[i].control)) | |
f15f9948 | 768 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 769 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), |
f15f9948 | 770 | &proc_info->bpts[i].address) < 0) |
71487fd7 | 771 | perror_with_name ("Unexpected error setting breakpoint address"); |
09b4ad9f UW |
772 | |
773 | if (arm_hwbp_control_is_initialized (proc_info->bpts[i].control)) | |
f15f9948 | 774 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 775 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), |
f15f9948 | 776 | &proc_info->bpts[i].control) < 0) |
71487fd7 | 777 | perror_with_name ("Unexpected error setting breakpoint"); |
09b4ad9f UW |
778 | |
779 | lwp_info->bpts_changed[i] = 0; | |
780 | } | |
781 | ||
782 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) | |
783 | if (lwp_info->wpts_changed[i]) | |
784 | { | |
785 | errno = 0; | |
786 | ||
787 | if (arm_hwbp_control_is_enabled (proc_info->wpts[i].control)) | |
f15f9948 | 788 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 789 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), |
f15f9948 | 790 | &proc_info->wpts[i].address) < 0) |
71487fd7 | 791 | perror_with_name ("Unexpected error setting watchpoint address"); |
09b4ad9f UW |
792 | |
793 | if (arm_hwbp_control_is_initialized (proc_info->wpts[i].control)) | |
f15f9948 | 794 | if (ptrace (PTRACE_SETHBPREGS, pid, |
b8e1b30e | 795 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), |
f15f9948 | 796 | &proc_info->wpts[i].control) < 0) |
71487fd7 | 797 | perror_with_name ("Unexpected error setting watchpoint"); |
09b4ad9f UW |
798 | |
799 | lwp_info->wpts_changed[i] = 0; | |
800 | } | |
801 | } | |
802 | ||
803 | ||
58d6951d DJ |
804 | static int |
805 | arm_get_hwcap (unsigned long *valp) | |
806 | { | |
807 | unsigned char *data = alloca (8); | |
808 | int offset = 0; | |
809 | ||
810 | while ((*the_target->read_auxv) (offset, data, 8) == 8) | |
811 | { | |
812 | unsigned int *data_p = (unsigned int *)data; | |
813 | if (data_p[0] == AT_HWCAP) | |
814 | { | |
815 | *valp = data_p[1]; | |
816 | return 1; | |
817 | } | |
818 | ||
819 | offset += 8; | |
820 | } | |
821 | ||
822 | *valp = 0; | |
823 | return 0; | |
824 | } | |
825 | ||
3aee8918 PA |
826 | static const struct target_desc * |
827 | arm_read_description (void) | |
58d6951d | 828 | { |
0bfdf32f | 829 | int pid = lwpid_of (current_thread); |
e8b41681 | 830 | unsigned long arm_hwcap = 0; |
71487fd7 UW |
831 | |
832 | /* Query hardware watchpoint/breakpoint capabilities. */ | |
833 | arm_linux_init_hwbp_cap (pid); | |
834 | ||
58d6951d | 835 | if (arm_get_hwcap (&arm_hwcap) == 0) |
3aee8918 | 836 | return tdesc_arm; |
58d6951d DJ |
837 | |
838 | if (arm_hwcap & HWCAP_IWMMXT) | |
3aee8918 | 839 | return tdesc_arm_with_iwmmxt; |
58d6951d DJ |
840 | |
841 | if (arm_hwcap & HWCAP_VFP) | |
842 | { | |
3aee8918 | 843 | const struct target_desc *result; |
58d6951d DJ |
844 | char *buf; |
845 | ||
846 | /* NEON implies either no VFP, or VFPv3-D32. We only support | |
847 | it with VFP. */ | |
848 | if (arm_hwcap & HWCAP_NEON) | |
3aee8918 | 849 | result = tdesc_arm_with_neon; |
58d6951d | 850 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
3aee8918 | 851 | result = tdesc_arm_with_vfpv3; |
58d6951d | 852 | else |
3aee8918 | 853 | result = tdesc_arm_with_vfpv2; |
58d6951d DJ |
854 | |
855 | /* Now make sure that the kernel supports reading these | |
856 | registers. Support was added in 2.6.30. */ | |
58d6951d | 857 | errno = 0; |
c3e8aadd | 858 | buf = xmalloc (32 * 8 + 4); |
58d6951d DJ |
859 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 |
860 | && errno == EIO) | |
e8b41681 YQ |
861 | result = tdesc_arm; |
862 | ||
58d6951d DJ |
863 | free (buf); |
864 | ||
3aee8918 | 865 | return result; |
58d6951d DJ |
866 | } |
867 | ||
868 | /* The default configuration uses legacy FPA registers, probably | |
869 | simulated. */ | |
3aee8918 | 870 | return tdesc_arm; |
58d6951d DJ |
871 | } |
872 | ||
3aee8918 PA |
873 | static void |
874 | arm_arch_setup (void) | |
875 | { | |
bd9e6534 YQ |
876 | int tid = lwpid_of (current_thread); |
877 | int gpregs[18]; | |
878 | struct iovec iov; | |
879 | ||
3aee8918 | 880 | current_process ()->tdesc = arm_read_description (); |
bd9e6534 YQ |
881 | |
882 | iov.iov_base = gpregs; | |
883 | iov.iov_len = sizeof (gpregs); | |
884 | ||
885 | /* Check if PTRACE_GETREGSET works. */ | |
886 | if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iov) == 0) | |
887 | have_ptrace_getregset = 1; | |
888 | else | |
889 | have_ptrace_getregset = 0; | |
3aee8918 PA |
890 | } |
891 | ||
bd9e6534 YQ |
892 | /* Register sets without using PTRACE_GETREGSET. */ |
893 | ||
3aee8918 | 894 | static struct regset_info arm_regsets[] = { |
1570b33e | 895 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4, |
fb1e4ffc DJ |
896 | GENERAL_REGS, |
897 | arm_fill_gregset, arm_store_gregset }, | |
1570b33e | 898 | { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4, |
fb1e4ffc DJ |
899 | EXTENDED_REGS, |
900 | arm_fill_wmmxregset, arm_store_wmmxregset }, | |
1570b33e | 901 | { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4, |
58d6951d DJ |
902 | EXTENDED_REGS, |
903 | arm_fill_vfpregset, arm_store_vfpregset }, | |
50bc912a | 904 | NULL_REGSET |
fb1e4ffc DJ |
905 | }; |
906 | ||
3aee8918 PA |
907 | static struct regsets_info arm_regsets_info = |
908 | { | |
909 | arm_regsets, /* regsets */ | |
910 | 0, /* num_regsets */ | |
911 | NULL, /* disabled_regsets */ | |
912 | }; | |
913 | ||
914 | static struct usrregs_info arm_usrregs_info = | |
915 | { | |
916 | arm_num_regs, | |
917 | arm_regmap, | |
918 | }; | |
919 | ||
bd9e6534 | 920 | static struct regs_info regs_info_arm = |
3aee8918 PA |
921 | { |
922 | NULL, /* regset_bitmap */ | |
923 | &arm_usrregs_info, | |
924 | &arm_regsets_info | |
925 | }; | |
926 | ||
927 | static const struct regs_info * | |
928 | arm_regs_info (void) | |
929 | { | |
bd9e6534 YQ |
930 | const struct target_desc *tdesc = current_process ()->tdesc; |
931 | ||
932 | if (have_ptrace_getregset == 1 | |
933 | && (tdesc == tdesc_arm_with_neon || tdesc == tdesc_arm_with_vfpv3)) | |
934 | return ®s_info_aarch32; | |
935 | else | |
936 | return ®s_info_arm; | |
3aee8918 PA |
937 | } |
938 | ||
8689682c AT |
939 | /* Implementation of linux_target_ops method "breakpoint_kind_from_pc". |
940 | ||
941 | Determine the type and size of breakpoint to insert at PCPTR. Uses the | |
942 | program counter value to determine whether a 16-bit or 32-bit breakpoint | |
943 | should be used. It returns the breakpoint's kind, and adjusts the program | |
944 | counter (if necessary) to point to the actual memory location where the | |
945 | breakpoint should be inserted. */ | |
946 | ||
947 | static int | |
948 | arm_breakpoint_kind_from_pc (CORE_ADDR *pcptr) | |
949 | { | |
950 | if (IS_THUMB_ADDR (*pcptr)) | |
951 | { | |
952 | gdb_byte buf[2]; | |
953 | ||
954 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
955 | ||
956 | /* Check whether we are replacing a thumb2 32-bit instruction. */ | |
957 | if ((*the_target->read_memory) (*pcptr, buf, 2) == 0) | |
958 | { | |
959 | unsigned short inst1 = 0; | |
960 | ||
961 | (*the_target->read_memory) (*pcptr, (gdb_byte *) &inst1, 2); | |
962 | if (thumb_insn_size (inst1) == 4) | |
963 | return ARM_BP_KIND_THUMB2; | |
964 | } | |
965 | return ARM_BP_KIND_THUMB; | |
966 | } | |
967 | else | |
968 | return ARM_BP_KIND_ARM; | |
969 | } | |
970 | ||
971 | /* Implementation of the linux_target_ops method "sw_breakpoint_from_kind". */ | |
aeb75bf5 | 972 | |
dd373349 AT |
973 | static const gdb_byte * |
974 | arm_sw_breakpoint_from_kind (int kind , int *size) | |
975 | { | |
976 | *size = arm_breakpoint_len; | |
aeb75bf5 DJ |
977 | /* Define an ARM-mode breakpoint; we only set breakpoints in the C |
978 | library, which is most likely to be ARM. If the kernel supports | |
979 | clone events, we will never insert a breakpoint, so even a Thumb | |
980 | C library will work; so will mixing EABI/non-EABI gdbserver and | |
981 | application. */ | |
8689682c AT |
982 | switch (kind) |
983 | { | |
984 | case ARM_BP_KIND_THUMB: | |
985 | *size = thumb_breakpoint_len; | |
986 | return (gdb_byte *) &thumb_breakpoint; | |
987 | case ARM_BP_KIND_THUMB2: | |
988 | *size = thumb2_breakpoint_len; | |
989 | return (gdb_byte *) &thumb2_breakpoint; | |
990 | case ARM_BP_KIND_ARM: | |
991 | *size = arm_breakpoint_len; | |
8689682c | 992 | return (const gdb_byte *) &arm_breakpoint; |
8689682c AT |
993 | default: |
994 | return NULL; | |
995 | } | |
996 | return NULL; | |
dd373349 AT |
997 | } |
998 | ||
999 | struct linux_target_ops the_low_target = { | |
1000 | arm_arch_setup, | |
1001 | arm_regs_info, | |
1002 | arm_cannot_fetch_register, | |
1003 | arm_cannot_store_register, | |
1004 | NULL, /* fetch_register */ | |
1005 | arm_get_pc, | |
1006 | arm_set_pc, | |
8689682c | 1007 | arm_breakpoint_kind_from_pc, |
dd373349 | 1008 | arm_sw_breakpoint_from_kind, |
3b2fc2ea | 1009 | arm_reinsert_addr, |
0d62e5e8 DJ |
1010 | 0, |
1011 | arm_breakpoint_at, | |
802e8e6d | 1012 | arm_supports_z_point_type, |
09b4ad9f UW |
1013 | arm_insert_point, |
1014 | arm_remove_point, | |
1015 | arm_stopped_by_watchpoint, | |
1016 | arm_stopped_data_address, | |
1017 | NULL, /* collect_ptrace_register */ | |
1018 | NULL, /* supply_ptrace_register */ | |
1019 | NULL, /* siginfo_fixup */ | |
1020 | arm_new_process, | |
1021 | arm_new_thread, | |
3a8a0396 | 1022 | arm_new_fork, |
09b4ad9f | 1023 | arm_prepare_to_resume, |
2ec06d2e | 1024 | }; |
3aee8918 PA |
1025 | |
1026 | void | |
1027 | initialize_low_arch (void) | |
1028 | { | |
1029 | /* Initialize the Linux target descriptions. */ | |
1030 | init_registers_arm (); | |
1031 | init_registers_arm_with_iwmmxt (); | |
1032 | init_registers_arm_with_vfpv2 (); | |
1033 | init_registers_arm_with_vfpv3 (); | |
bd9e6534 YQ |
1034 | |
1035 | initialize_low_arch_aarch32 (); | |
3aee8918 PA |
1036 | |
1037 | initialize_regsets_info (&arm_regsets_info); | |
1038 | } |