Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
ecd75fc8 | 2 | Copyright (C) 1995-2014 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
21 | #include <sys/ptrace.h> | |
22 | ||
d05b4ac3 UW |
23 | /* Defined in auto-generated file reg-crisv32.c. */ |
24 | void init_registers_crisv32 (void); | |
3aee8918 | 25 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 26 | |
45b134e5 OF |
27 | /* CRISv32 */ |
28 | #define cris_num_regs 49 | |
29 | ||
8eb3d7b6 RW |
30 | #ifndef PTRACE_GET_THREAD_AREA |
31 | #define PTRACE_GET_THREAD_AREA 25 | |
32 | #endif | |
33 | ||
45b134e5 OF |
34 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
35 | without any significant gain). */ | |
36 | ||
37 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
38 | static int cris_regmap[] = { | |
39 | 1*4, 2*4, 3*4, 4*4, | |
40 | 5*4, 6*4, 7*4, 8*4, | |
41 | 9*4, 10*4, 11*4, 12*4, | |
42 | 13*4, 14*4, 24*4, 15*4, | |
43 | ||
44 | -1, -1, -1, 16*4, | |
45 | -1, 22*4, 23*4, 17*4, | |
46 | -1, -1, 21*4, 20*4, | |
47 | -1, 19*4, -1, 18*4, | |
48 | ||
49 | 25*4, | |
50 | ||
1b3f6016 | 51 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
52 | 30*4, 31*4, 32*4, 33*4, |
53 | 34*4, 35*4, 36*4, 37*4, | |
54 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 55 | |
45b134e5 OF |
56 | }; |
57 | ||
58 | extern int debug_threads; | |
59 | ||
60 | static CORE_ADDR | |
442ea881 | 61 | cris_get_pc (struct regcache *regcache) |
45b134e5 OF |
62 | { |
63 | unsigned long pc; | |
442ea881 | 64 | collect_register_by_name (regcache, "pc", &pc); |
45b134e5 OF |
65 | if (debug_threads) |
66 | fprintf (stderr, "stop pc is %08lx\n", pc); | |
67 | return pc; | |
68 | } | |
69 | ||
70 | static void | |
442ea881 | 71 | cris_set_pc (struct regcache *regcache, CORE_ADDR pc) |
45b134e5 OF |
72 | { |
73 | unsigned long newpc = pc; | |
442ea881 | 74 | supply_register_by_name (regcache, "pc", &newpc); |
45b134e5 OF |
75 | } |
76 | ||
77 | static const unsigned short cris_breakpoint = 0xe938; | |
78 | #define cris_breakpoint_len 2 | |
79 | ||
80 | static int | |
81 | cris_breakpoint_at (CORE_ADDR where) | |
82 | { | |
83 | unsigned short insn; | |
84 | ||
f450004a DJ |
85 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
86 | cris_breakpoint_len); | |
45b134e5 OF |
87 | if (insn == cris_breakpoint) |
88 | return 1; | |
89 | ||
90 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
91 | one. */ | |
92 | return 0; | |
93 | } | |
94 | ||
95 | /* We only place breakpoints in empty marker functions, and thread locking | |
96 | is outside of the function. So rather than importing software single-step, | |
97 | we can just run until exit. */ | |
98 | ||
99 | /* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP | |
100 | for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event | |
101 | will fail when debugging multi-threaded applications. */ | |
102 | ||
103 | static CORE_ADDR | |
104 | cris_reinsert_addr (void) | |
105 | { | |
442ea881 | 106 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 107 | unsigned long pc; |
442ea881 | 108 | collect_register_by_name (regcache, "srp", &pc); |
45b134e5 OF |
109 | return pc; |
110 | } | |
111 | ||
112 | static void | |
442ea881 PA |
113 | cris_write_data_breakpoint (struct regcache *regcache, |
114 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
115 | { |
116 | switch (bp) | |
117 | { | |
118 | case 0: | |
442ea881 PA |
119 | supply_register_by_name (regcache, "s3", &start); |
120 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
121 | break; |
122 | case 1: | |
442ea881 PA |
123 | supply_register_by_name (regcache, "s5", &start); |
124 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
125 | break; |
126 | case 2: | |
442ea881 PA |
127 | supply_register_by_name (regcache, "s7", &start); |
128 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
129 | break; |
130 | case 3: | |
442ea881 PA |
131 | supply_register_by_name (regcache, "s9", &start); |
132 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
133 | break; |
134 | case 4: | |
442ea881 PA |
135 | supply_register_by_name (regcache, "s11", &start); |
136 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
137 | break; |
138 | case 5: | |
442ea881 PA |
139 | supply_register_by_name (regcache, "s13", &start); |
140 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
141 | break; |
142 | } | |
143 | } | |
144 | ||
145 | static int | |
d993e290 | 146 | cris_insert_point (char type, CORE_ADDR addr, int len) |
45b134e5 OF |
147 | { |
148 | int bp; | |
149 | unsigned long bp_ctrl; | |
150 | unsigned long start, end; | |
151 | unsigned long ccs; | |
442ea881 | 152 | struct regcache *regcache; |
1b3f6016 | 153 | |
45b134e5 OF |
154 | /* Breakpoint/watchpoint types (GDB terminology): |
155 | 0 = memory breakpoint for instructions | |
156 | (not supported; done via memory write instead) | |
157 | 1 = hardware breakpoint for instructions (not supported) | |
158 | 2 = write watchpoint (supported) | |
159 | 3 = read watchpoint (supported) | |
160 | 4 = access watchpoint (supported). */ | |
1b3f6016 PA |
161 | |
162 | if (type < '2' || type > '4') | |
45b134e5 OF |
163 | { |
164 | /* Unsupported. */ | |
165 | return 1; | |
166 | } | |
167 | ||
442ea881 PA |
168 | regcache = get_thread_regcache (current_inferior, 1); |
169 | ||
45b134e5 OF |
170 | /* Read watchpoints are set as access watchpoints, because of GDB's |
171 | inability to deal with pure read watchpoints. */ | |
172 | if (type == '3') | |
173 | type = '4'; | |
174 | ||
175 | /* Get the configuration register. */ | |
442ea881 | 176 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
177 | |
178 | /* The watchpoint allocation scheme is the simplest possible. | |
179 | For example, if a region is watched for read and | |
180 | a write watch is requested, a new watchpoint will | |
181 | be used. Also, if a watch for a region that is already | |
182 | covered by one or more existing watchpoints, a new | |
183 | watchpoint will be used. */ | |
1b3f6016 | 184 | |
45b134e5 OF |
185 | /* First, find a free data watchpoint. */ |
186 | for (bp = 0; bp < 6; bp++) | |
187 | { | |
188 | /* Each data watchpoint's control registers occupy 2 bits | |
189 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
190 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 191 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
192 | break; |
193 | } | |
1b3f6016 | 194 | |
45b134e5 OF |
195 | if (bp > 5) |
196 | { | |
197 | /* We're out of watchpoints. */ | |
198 | return -1; | |
199 | } | |
200 | ||
201 | /* Configure the control register first. */ | |
202 | if (type == '3' || type == '4') | |
203 | { | |
204 | /* Trigger on read. */ | |
205 | bp_ctrl |= (1 << (2 + bp * 4)); | |
206 | } | |
1b3f6016 | 207 | if (type == '2' || type == '4') |
45b134e5 OF |
208 | { |
209 | /* Trigger on write. */ | |
210 | bp_ctrl |= (2 << (2 + bp * 4)); | |
211 | } | |
1b3f6016 | 212 | |
45b134e5 | 213 | /* Setup the configuration register. */ |
442ea881 | 214 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 215 | |
45b134e5 OF |
216 | /* Setup the range. */ |
217 | start = addr; | |
218 | end = addr + len - 1; | |
219 | ||
220 | /* Configure the watchpoint register. */ | |
442ea881 | 221 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 222 | |
442ea881 | 223 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
224 | /* Set the S1 flag to enable watchpoints. */ |
225 | ccs |= (1 << 19); | |
442ea881 | 226 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
231 | static int | |
d993e290 | 232 | cris_remove_point (char type, CORE_ADDR addr, int len) |
45b134e5 OF |
233 | { |
234 | int bp; | |
235 | unsigned long bp_ctrl; | |
236 | unsigned long start, end; | |
442ea881 | 237 | struct regcache *regcache; |
07c04788 | 238 | unsigned long bp_d_regs[12]; |
1b3f6016 | 239 | |
45b134e5 OF |
240 | /* Breakpoint/watchpoint types: |
241 | 0 = memory breakpoint for instructions | |
242 | (not supported; done via memory write instead) | |
243 | 1 = hardware breakpoint for instructions (not supported) | |
244 | 2 = write watchpoint (supported) | |
245 | 3 = read watchpoint (supported) | |
246 | 4 = access watchpoint (supported). */ | |
247 | if (type < '2' || type > '4') | |
248 | return -1; | |
1b3f6016 | 249 | |
442ea881 PA |
250 | regcache = get_thread_regcache (current_inferior, 1); |
251 | ||
45b134e5 OF |
252 | /* Read watchpoints are set as access watchpoints, because of GDB's |
253 | inability to deal with pure read watchpoints. */ | |
254 | if (type == '3') | |
255 | type = '4'; | |
1b3f6016 | 256 | |
45b134e5 | 257 | /* Get the configuration register. */ |
442ea881 | 258 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
259 | |
260 | /* Try to find a watchpoint that is configured for the | |
261 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 262 | |
45b134e5 OF |
263 | /* Ugly pointer arithmetic, since I cannot rely on a |
264 | single switch (addr) as there may be several watchpoints with | |
265 | the same start address for example. */ | |
266 | ||
45b134e5 | 267 | /* Get all range registers to simplify search. */ |
442ea881 PA |
268 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
269 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
270 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
271 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
272 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
273 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
274 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
275 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
276 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
277 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
278 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
279 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 280 | |
1b3f6016 | 281 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 282 | { |
1b3f6016 | 283 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
284 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
285 | /* Matching range. */ | |
286 | int bitpos = 2 + bp * 4; | |
287 | int rw_bits; | |
1b3f6016 | 288 | |
45b134e5 OF |
289 | /* Read/write bits for this BP. */ |
290 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 291 | |
45b134e5 | 292 | if ((type == '3' && rw_bits == 0x1) |
1b3f6016 | 293 | || (type == '2' && rw_bits == 0x2) |
45b134e5 OF |
294 | || (type == '4' && rw_bits == 0x3)) |
295 | { | |
296 | /* Read/write matched. */ | |
297 | break; | |
298 | } | |
299 | } | |
300 | } | |
1b3f6016 | 301 | |
45b134e5 OF |
302 | if (bp > 5) |
303 | { | |
304 | /* No watchpoint matched. */ | |
305 | return -1; | |
306 | } | |
1b3f6016 | 307 | |
45b134e5 OF |
308 | /* Found a matching watchpoint. Now, deconfigure it by |
309 | both disabling read/write in bp_ctrl and zeroing its | |
310 | start/end addresses. */ | |
311 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
312 | /* Setup the configuration register. */ | |
442ea881 | 313 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
314 | |
315 | start = end = 0; | |
316 | /* Configure the watchpoint register. */ | |
442ea881 | 317 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
318 | |
319 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static int | |
324 | cris_stopped_by_watchpoint (void) | |
325 | { | |
326 | unsigned long exs; | |
07c04788 | 327 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 328 | |
07c04788 | 329 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
330 | |
331 | return (((exs & 0xff00) >> 8) == 0xc); | |
332 | } | |
333 | ||
334 | static CORE_ADDR | |
335 | cris_stopped_data_address (void) | |
336 | { | |
337 | unsigned long eda; | |
07c04788 | 338 | struct regcache *regcache = get_thread_regcache (current_inferior, 1); |
45b134e5 | 339 | |
07c04788 | 340 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
341 | |
342 | /* FIXME: Possibly adjust to match watched range. */ | |
343 | return eda; | |
344 | } | |
345 | ||
8eb3d7b6 RW |
346 | ps_err_e |
347 | ps_get_thread_area (const struct ps_prochandle *ph, | |
348 | lwpid_t lwpid, int idx, void **base) | |
349 | { | |
350 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
351 | return PS_ERR; | |
352 | ||
353 | /* IDX is the bias from the thread pointer to the beginning of the | |
354 | thread descriptor. It has to be subtracted due to implementation | |
355 | quirks in libthread_db. */ | |
356 | *base = (void *) ((char *) *base - idx); | |
357 | return PS_OK; | |
358 | } | |
359 | ||
45b134e5 | 360 | static void |
07c04788 | 361 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
362 | { |
363 | int i; | |
364 | ||
365 | for (i = 0; i < cris_num_regs; i++) | |
366 | { | |
367 | if (cris_regmap[i] != -1) | |
07c04788 | 368 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
369 | } |
370 | } | |
371 | ||
372 | static void | |
07c04788 | 373 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
374 | { |
375 | int i; | |
376 | ||
377 | for (i = 0; i < cris_num_regs; i++) | |
378 | { | |
379 | if (cris_regmap[i] != -1) | |
07c04788 | 380 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
381 | } |
382 | } | |
383 | ||
3aee8918 PA |
384 | static void |
385 | cris_arch_setup (void) | |
386 | { | |
387 | current_process ()->tdesc = tdesc_crisv32; | |
388 | } | |
389 | ||
3aee8918 | 390 | static struct regset_info cris_regsets[] = { |
07c04788 | 391 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 392 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
1570b33e | 393 | { 0, 0, 0, -1, -1, NULL, NULL } |
45b134e5 OF |
394 | }; |
395 | ||
3aee8918 PA |
396 | |
397 | static struct regsets_info cris_regsets_info = | |
398 | { | |
399 | cris_regsets, /* regsets */ | |
400 | 0, /* num_regsets */ | |
401 | NULL, /* disabled_regsets */ | |
402 | }; | |
403 | ||
404 | static struct usrregs_info cris_usrregs_info = | |
405 | { | |
406 | cris_num_regs, | |
407 | cris_regmap, | |
408 | }; | |
409 | ||
410 | static struct regs_info regs_info = | |
411 | { | |
412 | NULL, /* regset_bitmap */ | |
413 | &cris_usrregs_info, | |
414 | &cris_regsets_info | |
415 | }; | |
416 | ||
417 | static const struct regs_info * | |
418 | cris_regs_info (void) | |
419 | { | |
420 | return ®s_info; | |
421 | } | |
422 | ||
45b134e5 | 423 | struct linux_target_ops the_low_target = { |
3aee8918 PA |
424 | cris_arch_setup, |
425 | cris_regs_info, | |
45b134e5 | 426 | NULL, |
1faeff08 | 427 | NULL, |
c14dfd32 | 428 | NULL, /* fetch_register */ |
45b134e5 OF |
429 | cris_get_pc, |
430 | cris_set_pc, | |
f450004a | 431 | (const unsigned char *) &cris_breakpoint, |
45b134e5 OF |
432 | cris_breakpoint_len, |
433 | cris_reinsert_addr, | |
434 | 0, | |
435 | cris_breakpoint_at, | |
d993e290 PA |
436 | cris_insert_point, |
437 | cris_remove_point, | |
45b134e5 OF |
438 | cris_stopped_by_watchpoint, |
439 | cris_stopped_data_address, | |
440 | }; | |
3aee8918 PA |
441 | |
442 | void | |
443 | initialize_low_arch (void) | |
444 | { | |
eddddb9d | 445 | init_registers_crisv32 (); |
3aee8918 PA |
446 | |
447 | initialize_regsets_info (&cris_regsets_info); | |
448 | } |