Commit | Line | Data |
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45b134e5 | 1 | /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. |
618f726f | 2 | Copyright (C) 1995-2016 Free Software Foundation, Inc. |
45b134e5 OF |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
45b134e5 OF |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
45b134e5 OF |
18 | |
19 | #include "server.h" | |
20 | #include "linux-low.h" | |
5826e159 | 21 | #include "nat/gdb_ptrace.h" |
45b134e5 | 22 | |
d05b4ac3 UW |
23 | /* Defined in auto-generated file reg-crisv32.c. */ |
24 | void init_registers_crisv32 (void); | |
3aee8918 | 25 | extern const struct target_desc *tdesc_crisv32; |
d05b4ac3 | 26 | |
45b134e5 OF |
27 | /* CRISv32 */ |
28 | #define cris_num_regs 49 | |
29 | ||
8eb3d7b6 RW |
30 | #ifndef PTRACE_GET_THREAD_AREA |
31 | #define PTRACE_GET_THREAD_AREA 25 | |
32 | #endif | |
33 | ||
45b134e5 OF |
34 | /* Note: Ignoring USP (having the stack pointer in two locations causes trouble |
35 | without any significant gain). */ | |
36 | ||
37 | /* Locations need to match <include/asm/arch/ptrace.h>. */ | |
38 | static int cris_regmap[] = { | |
39 | 1*4, 2*4, 3*4, 4*4, | |
40 | 5*4, 6*4, 7*4, 8*4, | |
41 | 9*4, 10*4, 11*4, 12*4, | |
42 | 13*4, 14*4, 24*4, 15*4, | |
43 | ||
44 | -1, -1, -1, 16*4, | |
45 | -1, 22*4, 23*4, 17*4, | |
46 | -1, -1, 21*4, 20*4, | |
47 | -1, 19*4, -1, 18*4, | |
48 | ||
49 | 25*4, | |
50 | ||
1b3f6016 | 51 | 26*4, -1, -1, 29*4, |
45b134e5 OF |
52 | 30*4, 31*4, 32*4, 33*4, |
53 | 34*4, 35*4, 36*4, 37*4, | |
54 | 38*4, 39*4, 40*4, -1 | |
1b3f6016 | 55 | |
45b134e5 OF |
56 | }; |
57 | ||
58 | extern int debug_threads; | |
59 | ||
60 | static CORE_ADDR | |
442ea881 | 61 | cris_get_pc (struct regcache *regcache) |
45b134e5 OF |
62 | { |
63 | unsigned long pc; | |
442ea881 | 64 | collect_register_by_name (regcache, "pc", &pc); |
45b134e5 | 65 | if (debug_threads) |
87ce2a04 | 66 | debug_printf ("stop pc is %08lx\n", pc); |
45b134e5 OF |
67 | return pc; |
68 | } | |
69 | ||
70 | static void | |
442ea881 | 71 | cris_set_pc (struct regcache *regcache, CORE_ADDR pc) |
45b134e5 OF |
72 | { |
73 | unsigned long newpc = pc; | |
442ea881 | 74 | supply_register_by_name (regcache, "pc", &newpc); |
45b134e5 OF |
75 | } |
76 | ||
77 | static const unsigned short cris_breakpoint = 0xe938; | |
78 | #define cris_breakpoint_len 2 | |
79 | ||
dd373349 AT |
80 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
81 | ||
82 | static const gdb_byte * | |
83 | cris_sw_breakpoint_from_kind (int kind, int *size) | |
84 | { | |
85 | *size = cris_breakpoint_len; | |
86 | return (const gdb_byte *) &cris_breakpoint; | |
87 | } | |
88 | ||
45b134e5 OF |
89 | static int |
90 | cris_breakpoint_at (CORE_ADDR where) | |
91 | { | |
92 | unsigned short insn; | |
93 | ||
f450004a DJ |
94 | (*the_target->read_memory) (where, (unsigned char *) &insn, |
95 | cris_breakpoint_len); | |
45b134e5 OF |
96 | if (insn == cris_breakpoint) |
97 | return 1; | |
98 | ||
99 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
100 | one. */ | |
101 | return 0; | |
102 | } | |
103 | ||
45b134e5 | 104 | static void |
442ea881 PA |
105 | cris_write_data_breakpoint (struct regcache *regcache, |
106 | int bp, unsigned long start, unsigned long end) | |
45b134e5 OF |
107 | { |
108 | switch (bp) | |
109 | { | |
110 | case 0: | |
442ea881 PA |
111 | supply_register_by_name (regcache, "s3", &start); |
112 | supply_register_by_name (regcache, "s4", &end); | |
45b134e5 OF |
113 | break; |
114 | case 1: | |
442ea881 PA |
115 | supply_register_by_name (regcache, "s5", &start); |
116 | supply_register_by_name (regcache, "s6", &end); | |
45b134e5 OF |
117 | break; |
118 | case 2: | |
442ea881 PA |
119 | supply_register_by_name (regcache, "s7", &start); |
120 | supply_register_by_name (regcache, "s8", &end); | |
45b134e5 OF |
121 | break; |
122 | case 3: | |
442ea881 PA |
123 | supply_register_by_name (regcache, "s9", &start); |
124 | supply_register_by_name (regcache, "s10", &end); | |
45b134e5 OF |
125 | break; |
126 | case 4: | |
442ea881 PA |
127 | supply_register_by_name (regcache, "s11", &start); |
128 | supply_register_by_name (regcache, "s12", &end); | |
45b134e5 OF |
129 | break; |
130 | case 5: | |
442ea881 PA |
131 | supply_register_by_name (regcache, "s13", &start); |
132 | supply_register_by_name (regcache, "s14", &end); | |
45b134e5 OF |
133 | break; |
134 | } | |
135 | } | |
136 | ||
137 | static int | |
802e8e6d PA |
138 | cris_supports_z_point_type (char z_type) |
139 | { | |
140 | switch (z_type) | |
141 | { | |
142 | case Z_PACKET_WRITE_WP: | |
143 | case Z_PACKET_READ_WP: | |
144 | case Z_PACKET_ACCESS_WP: | |
145 | return 1; | |
146 | default: | |
147 | return 0; | |
148 | } | |
149 | } | |
150 | ||
151 | static int | |
152 | cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, | |
153 | int len, struct raw_breakpoint *bp) | |
45b134e5 OF |
154 | { |
155 | int bp; | |
156 | unsigned long bp_ctrl; | |
157 | unsigned long start, end; | |
158 | unsigned long ccs; | |
442ea881 | 159 | struct regcache *regcache; |
1b3f6016 | 160 | |
0bfdf32f | 161 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 162 | |
45b134e5 OF |
163 | /* Read watchpoints are set as access watchpoints, because of GDB's |
164 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
165 | if (type == raw_bkpt_type_read_wp) |
166 | type = raw_bkpt_type_access_wp; | |
45b134e5 OF |
167 | |
168 | /* Get the configuration register. */ | |
442ea881 | 169 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
170 | |
171 | /* The watchpoint allocation scheme is the simplest possible. | |
172 | For example, if a region is watched for read and | |
173 | a write watch is requested, a new watchpoint will | |
174 | be used. Also, if a watch for a region that is already | |
175 | covered by one or more existing watchpoints, a new | |
176 | watchpoint will be used. */ | |
1b3f6016 | 177 | |
45b134e5 OF |
178 | /* First, find a free data watchpoint. */ |
179 | for (bp = 0; bp < 6; bp++) | |
180 | { | |
181 | /* Each data watchpoint's control registers occupy 2 bits | |
182 | (hence the 3), starting at bit 2 for D0 (hence the 2) | |
183 | with 4 bits between for each watchpoint (yes, the 4). */ | |
1b3f6016 | 184 | if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) |
45b134e5 OF |
185 | break; |
186 | } | |
1b3f6016 | 187 | |
45b134e5 OF |
188 | if (bp > 5) |
189 | { | |
190 | /* We're out of watchpoints. */ | |
191 | return -1; | |
192 | } | |
193 | ||
194 | /* Configure the control register first. */ | |
802e8e6d | 195 | if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
196 | { |
197 | /* Trigger on read. */ | |
198 | bp_ctrl |= (1 << (2 + bp * 4)); | |
199 | } | |
802e8e6d | 200 | if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp) |
45b134e5 OF |
201 | { |
202 | /* Trigger on write. */ | |
203 | bp_ctrl |= (2 << (2 + bp * 4)); | |
204 | } | |
1b3f6016 | 205 | |
45b134e5 | 206 | /* Setup the configuration register. */ |
442ea881 | 207 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
1b3f6016 | 208 | |
45b134e5 OF |
209 | /* Setup the range. */ |
210 | start = addr; | |
211 | end = addr + len - 1; | |
212 | ||
213 | /* Configure the watchpoint register. */ | |
442ea881 | 214 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 | 215 | |
442ea881 | 216 | collect_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
217 | /* Set the S1 flag to enable watchpoints. */ |
218 | ccs |= (1 << 19); | |
442ea881 | 219 | supply_register_by_name (regcache, "ccs", &ccs); |
45b134e5 OF |
220 | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static int | |
802e8e6d PA |
225 | cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len, |
226 | struct raw_breakpoint *bp) | |
45b134e5 OF |
227 | { |
228 | int bp; | |
229 | unsigned long bp_ctrl; | |
230 | unsigned long start, end; | |
442ea881 | 231 | struct regcache *regcache; |
07c04788 | 232 | unsigned long bp_d_regs[12]; |
1b3f6016 | 233 | |
0bfdf32f | 234 | regcache = get_thread_regcache (current_thread, 1); |
442ea881 | 235 | |
45b134e5 OF |
236 | /* Read watchpoints are set as access watchpoints, because of GDB's |
237 | inability to deal with pure read watchpoints. */ | |
802e8e6d PA |
238 | if (type == raw_bkpt_type_read_wp) |
239 | type = raw_bkpt_type_access_wp; | |
1b3f6016 | 240 | |
45b134e5 | 241 | /* Get the configuration register. */ |
442ea881 | 242 | collect_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
243 | |
244 | /* Try to find a watchpoint that is configured for the | |
245 | specified range, then check that read/write also matches. */ | |
1b3f6016 | 246 | |
45b134e5 OF |
247 | /* Ugly pointer arithmetic, since I cannot rely on a |
248 | single switch (addr) as there may be several watchpoints with | |
249 | the same start address for example. */ | |
250 | ||
45b134e5 | 251 | /* Get all range registers to simplify search. */ |
442ea881 PA |
252 | collect_register_by_name (regcache, "s3", &bp_d_regs[0]); |
253 | collect_register_by_name (regcache, "s4", &bp_d_regs[1]); | |
254 | collect_register_by_name (regcache, "s5", &bp_d_regs[2]); | |
255 | collect_register_by_name (regcache, "s6", &bp_d_regs[3]); | |
256 | collect_register_by_name (regcache, "s7", &bp_d_regs[4]); | |
257 | collect_register_by_name (regcache, "s8", &bp_d_regs[5]); | |
258 | collect_register_by_name (regcache, "s9", &bp_d_regs[6]); | |
259 | collect_register_by_name (regcache, "s10", &bp_d_regs[7]); | |
260 | collect_register_by_name (regcache, "s11", &bp_d_regs[8]); | |
261 | collect_register_by_name (regcache, "s12", &bp_d_regs[9]); | |
262 | collect_register_by_name (regcache, "s13", &bp_d_regs[10]); | |
263 | collect_register_by_name (regcache, "s14", &bp_d_regs[11]); | |
45b134e5 | 264 | |
1b3f6016 | 265 | for (bp = 0; bp < 6; bp++) |
45b134e5 | 266 | { |
1b3f6016 | 267 | if (bp_d_regs[bp * 2] == addr |
45b134e5 OF |
268 | && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { |
269 | /* Matching range. */ | |
270 | int bitpos = 2 + bp * 4; | |
271 | int rw_bits; | |
1b3f6016 | 272 | |
45b134e5 OF |
273 | /* Read/write bits for this BP. */ |
274 | rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; | |
1b3f6016 | 275 | |
802e8e6d PA |
276 | if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1) |
277 | || (type == raw_bkpt_type_write_wp && rw_bits == 0x2) | |
278 | || (type == raw_bkpt_type_access_wp && rw_bits == 0x3)) | |
45b134e5 OF |
279 | { |
280 | /* Read/write matched. */ | |
281 | break; | |
282 | } | |
283 | } | |
284 | } | |
1b3f6016 | 285 | |
45b134e5 OF |
286 | if (bp > 5) |
287 | { | |
288 | /* No watchpoint matched. */ | |
289 | return -1; | |
290 | } | |
1b3f6016 | 291 | |
45b134e5 OF |
292 | /* Found a matching watchpoint. Now, deconfigure it by |
293 | both disabling read/write in bp_ctrl and zeroing its | |
294 | start/end addresses. */ | |
295 | bp_ctrl &= ~(3 << (2 + (bp * 4))); | |
296 | /* Setup the configuration register. */ | |
442ea881 | 297 | supply_register_by_name (regcache, "s0", &bp_ctrl); |
45b134e5 OF |
298 | |
299 | start = end = 0; | |
300 | /* Configure the watchpoint register. */ | |
442ea881 | 301 | cris_write_data_breakpoint (regcache, bp, start, end); |
45b134e5 OF |
302 | |
303 | /* Note that we don't clear the S1 flag here. It's done when continuing. */ | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int | |
308 | cris_stopped_by_watchpoint (void) | |
309 | { | |
310 | unsigned long exs; | |
0bfdf32f | 311 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 312 | |
07c04788 | 313 | collect_register_by_name (regcache, "exs", &exs); |
45b134e5 OF |
314 | |
315 | return (((exs & 0xff00) >> 8) == 0xc); | |
316 | } | |
317 | ||
318 | static CORE_ADDR | |
319 | cris_stopped_data_address (void) | |
320 | { | |
321 | unsigned long eda; | |
0bfdf32f | 322 | struct regcache *regcache = get_thread_regcache (current_thread, 1); |
45b134e5 | 323 | |
07c04788 | 324 | collect_register_by_name (regcache, "eda", &eda); |
45b134e5 OF |
325 | |
326 | /* FIXME: Possibly adjust to match watched range. */ | |
327 | return eda; | |
328 | } | |
329 | ||
8eb3d7b6 RW |
330 | ps_err_e |
331 | ps_get_thread_area (const struct ps_prochandle *ph, | |
332 | lwpid_t lwpid, int idx, void **base) | |
333 | { | |
334 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
335 | return PS_ERR; | |
336 | ||
337 | /* IDX is the bias from the thread pointer to the beginning of the | |
338 | thread descriptor. It has to be subtracted due to implementation | |
339 | quirks in libthread_db. */ | |
340 | *base = (void *) ((char *) *base - idx); | |
341 | return PS_OK; | |
342 | } | |
343 | ||
45b134e5 | 344 | static void |
07c04788 | 345 | cris_fill_gregset (struct regcache *regcache, void *buf) |
45b134e5 OF |
346 | { |
347 | int i; | |
348 | ||
349 | for (i = 0; i < cris_num_regs; i++) | |
350 | { | |
351 | if (cris_regmap[i] != -1) | |
07c04788 | 352 | collect_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
353 | } |
354 | } | |
355 | ||
356 | static void | |
07c04788 | 357 | cris_store_gregset (struct regcache *regcache, const void *buf) |
45b134e5 OF |
358 | { |
359 | int i; | |
360 | ||
361 | for (i = 0; i < cris_num_regs; i++) | |
362 | { | |
363 | if (cris_regmap[i] != -1) | |
07c04788 | 364 | supply_register (regcache, i, ((char *) buf) + cris_regmap[i]); |
45b134e5 OF |
365 | } |
366 | } | |
367 | ||
3aee8918 PA |
368 | static void |
369 | cris_arch_setup (void) | |
370 | { | |
371 | current_process ()->tdesc = tdesc_crisv32; | |
372 | } | |
373 | ||
7d00775e AT |
374 | /* Support for hardware single step. */ |
375 | ||
376 | static int | |
377 | cris_supports_hardware_single_step (void) | |
378 | { | |
379 | return 1; | |
380 | } | |
381 | ||
3aee8918 | 382 | static struct regset_info cris_regsets[] = { |
07c04788 | 383 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4, |
45b134e5 | 384 | GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, |
50bc912a | 385 | NULL_REGSET |
45b134e5 OF |
386 | }; |
387 | ||
3aee8918 PA |
388 | |
389 | static struct regsets_info cris_regsets_info = | |
390 | { | |
391 | cris_regsets, /* regsets */ | |
392 | 0, /* num_regsets */ | |
393 | NULL, /* disabled_regsets */ | |
394 | }; | |
395 | ||
396 | static struct usrregs_info cris_usrregs_info = | |
397 | { | |
398 | cris_num_regs, | |
399 | cris_regmap, | |
400 | }; | |
401 | ||
402 | static struct regs_info regs_info = | |
403 | { | |
404 | NULL, /* regset_bitmap */ | |
405 | &cris_usrregs_info, | |
406 | &cris_regsets_info | |
407 | }; | |
408 | ||
409 | static const struct regs_info * | |
410 | cris_regs_info (void) | |
411 | { | |
412 | return ®s_info; | |
413 | } | |
414 | ||
45b134e5 | 415 | struct linux_target_ops the_low_target = { |
3aee8918 PA |
416 | cris_arch_setup, |
417 | cris_regs_info, | |
45b134e5 | 418 | NULL, |
1faeff08 | 419 | NULL, |
c14dfd32 | 420 | NULL, /* fetch_register */ |
45b134e5 OF |
421 | cris_get_pc, |
422 | cris_set_pc, | |
dd373349 AT |
423 | NULL, /* breakpoint_kind_from_pc */ |
424 | cris_sw_breakpoint_from_kind, | |
fa5308bd | 425 | NULL, /* get_next_pcs */ |
45b134e5 OF |
426 | 0, |
427 | cris_breakpoint_at, | |
802e8e6d | 428 | cris_supports_z_point_type, |
d993e290 PA |
429 | cris_insert_point, |
430 | cris_remove_point, | |
45b134e5 OF |
431 | cris_stopped_by_watchpoint, |
432 | cris_stopped_data_address, | |
7d00775e AT |
433 | NULL, /* collect_ptrace_register */ |
434 | NULL, /* supply_ptrace_register */ | |
435 | NULL, /* siginfo_fixup */ | |
436 | NULL, /* new_process */ | |
437 | NULL, /* new_thread */ | |
438 | NULL, /* new_fork */ | |
439 | NULL, /* prepare_to_resume */ | |
440 | NULL, /* process_qsupported */ | |
441 | NULL, /* supports_tracepoints */ | |
442 | NULL, /* get_thread_area */ | |
443 | NULL, /* install_fast_tracepoint_jump_pad */ | |
444 | NULL, /* emit_ops */ | |
445 | NULL, /* get_min_fast_tracepoint_insn_len */ | |
446 | NULL, /* supports_range_stepping */ | |
447 | NULL, /* breakpoint_kind_from_current_state */ | |
448 | cris_supports_hardware_single_step, | |
45b134e5 | 449 | }; |
3aee8918 PA |
450 | |
451 | void | |
452 | initialize_low_arch (void) | |
453 | { | |
eddddb9d | 454 | init_registers_crisv32 (); |
3aee8918 PA |
455 | |
456 | initialize_regsets_info (&cris_regsets_info); | |
457 | } |