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[PowerPC] Consolidate wordsize getter between native and gdbserver
[deliverable/binutils-gdb.git] / gdb / gdbserver / linux-ppc-low.c
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
e2882c85 3 Copyright (C) 1995-2018 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
b6430ec3 23#include <elf.h>
0a30fbc4
DJ		 24#include <asm/ptrace.h>
25
bd64614e
PFC		 26#include "arch/ppc-linux-common.h"
27#include "arch/ppc-linux-tdesc.h"
514c5338 28#include "nat/ppc-linux.h"
bd64614e 29#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 30#include "ax.h"
31#include "tracepoint.h"
32
33#define PPC_FIELD(value, from, len) \
34 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
35#define PPC_SEXT(v, bs) \
36 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
37 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
38 - ((CORE_ADDR) 1 << ((bs) - 1)))
39#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
40#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
41#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
42#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3
UW		 43
44static unsigned long ppc_hwcap;
45
46
7284e1be
UW		 47#define ppc_num_regs 73
48
5b0a002e
UW		 49#ifdef __powerpc64__
50/* We use a constant for FPSCR instead of PT_FPSCR, because
51 many shipped PPC64 kernels had the wrong value in ptrace.h. */
52static int ppc_regmap[] =
53 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
54 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
55 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
56 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
57 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
58 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
59 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
60 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
61 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
62 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
63 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
64 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
65 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
66 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
67 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
68 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
69 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 70 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
71 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 72#else
0a30fbc4 73/* Currently, don't check/send MQ. */
2ec06d2e 74static int ppc_regmap[] =
0a30fbc4
DJ		 75 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
76 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
77 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
78 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
79 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
80 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
81 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
82 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
83 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
84 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
85 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
86 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
87 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
88 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
89 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
90 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
91 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 92 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
93 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 94 };
95
96static int ppc_regmap_e500[] =
97 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
98 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
99 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
100 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
101 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
102 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
103 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
104 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
105 -1, -1, -1, -1,
106 -1, -1, -1, -1,
107 -1, -1, -1, -1,
108 -1, -1, -1, -1,
109 -1, -1, -1, -1,
110 -1, -1, -1, -1,
111 -1, -1, -1, -1,
112 -1, -1, -1, -1,
113 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 114 PT_CTR * 4, PT_XER * 4, -1,
115 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 116 };
5b0a002e 117#endif
0a30fbc4 118
2ec06d2e
DJ		 119static int
120ppc_cannot_store_register (int regno)
0a30fbc4 121{
3aee8918
PA		 122 const struct target_desc *tdesc = current_process ()->tdesc;
123
b6430ec3 124#ifndef __powerpc64__
bc1e36ca 125 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 126 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
127 && regno == find_regno (tdesc, "fpscr"))
bc1e36ca 128 return 2;
30ed0a8f 129#endif
bc1e36ca 130
7284e1be 131 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 132 if (regno == find_regno (tdesc, "orig_r3")
133 || regno == find_regno (tdesc, "trap"))
7284e1be
UW		 134 return 2;
135
0a30fbc4
DJ		 136 return 0;
137}
138
2ec06d2e
DJ		 139static int
140ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 141{
142 return 0;
143}
144
5b0a002e 145static void
442ea881 146ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 147{
76b233dd
UW		 148 memset (buf, 0, sizeof (long));
149
2e4bb98a
EBM		 150 if (__BYTE_ORDER == __LITTLE_ENDIAN)
151 {
152 /* Little-endian values always sit at the left end of the buffer. */
153 collect_register (regcache, regno, buf);
154 }
155 else if (__BYTE_ORDER == __BIG_ENDIAN)
156 {
157 /* Big-endian values sit at the right end of the buffer. In case of
158 registers whose sizes are smaller than sizeof (long), we must use a
159 padding to access them correctly. */
160 int size = register_size (regcache->tdesc, regno);
161
162 if (size < sizeof (long))
163 collect_register (regcache, regno, buf + sizeof (long) - size);
164 else
165 collect_register (regcache, regno, buf);
166 }
5b0a002e 167 else
2e4bb98a 168 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 169}
170
171static void
442ea881
PA		 172ppc_supply_ptrace_register (struct regcache *regcache,
173 int regno, const char *buf)
5b0a002e 174{
2e4bb98a
EBM		 175 if (__BYTE_ORDER == __LITTLE_ENDIAN)
176 {
177 /* Little-endian values always sit at the left end of the buffer. */
178 supply_register (regcache, regno, buf);
179 }
180 else if (__BYTE_ORDER == __BIG_ENDIAN)
181 {
182 /* Big-endian values sit at the right end of the buffer. In case of
183 registers whose sizes are smaller than sizeof (long), we must use a
184 padding to access them correctly. */
185 int size = register_size (regcache->tdesc, regno);
186
187 if (size < sizeof (long))
188 supply_register (regcache, regno, buf + sizeof (long) - size);
189 else
190 supply_register (regcache, regno, buf);
191 }
5b0a002e 192 else
2e4bb98a 193 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 194}
195
0b9ff2c0
UW		 196
197#define INSTR_SC 0x44000002
198#define NR_spu_run 0x0116
199
200/* If the PPU thread is currently stopped on a spu_run system call,
201 return to FD and ADDR the file handle and NPC parameter address
202 used with the system call. Return non-zero if successful. */
203static int
442ea881 204parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
0b9ff2c0
UW		 205{
206 CORE_ADDR curr_pc;
207 int curr_insn;
208 int curr_r0;
209
3aee8918 210 if (register_size (regcache->tdesc, 0) == 4)
0b9ff2c0
UW		 211 {
212 unsigned int pc, r0, r3, r4;
442ea881
PA		 213 collect_register_by_name (regcache, "pc", &pc);
214 collect_register_by_name (regcache, "r0", &r0);
215 collect_register_by_name (regcache, "orig_r3", &r3);
216 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 217 curr_pc = (CORE_ADDR) pc;
218 curr_r0 = (int) r0;
219 *fd = (int) r3;
220 *addr = (CORE_ADDR) r4;
221 }
222 else
223 {
224 unsigned long pc, r0, r3, r4;
442ea881
PA		 225 collect_register_by_name (regcache, "pc", &pc);
226 collect_register_by_name (regcache, "r0", &r0);
227 collect_register_by_name (regcache, "orig_r3", &r3);
228 collect_register_by_name (regcache, "r4", &r4);
0b9ff2c0
UW		 229 curr_pc = (CORE_ADDR) pc;
230 curr_r0 = (int) r0;
231 *fd = (int) r3;
232 *addr = (CORE_ADDR) r4;
233 }
234
235 /* Fetch instruction preceding current NIP. */
236 if ((*the_target->read_memory) (curr_pc - 4,
237 (unsigned char *) &curr_insn, 4) != 0)
238 return 0;
239 /* It should be a "sc" instruction. */
240 if (curr_insn != INSTR_SC)
241 return 0;
242 /* System call number should be NR_spu_run. */
243 if (curr_r0 != NR_spu_run)
244 return 0;
245
246 return 1;
247}
248
0d62e5e8 249static CORE_ADDR
442ea881 250ppc_get_pc (struct regcache *regcache)
0d62e5e8 251{
0b9ff2c0
UW		 252 CORE_ADDR addr;
253 int fd;
254
442ea881 255 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 256 {
257 unsigned int pc;
258 (*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
493e2a69
MS		 259 return ((CORE_ADDR)1 << 63)
260 | ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
0b9ff2c0 261 }
3aee8918 262 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 263 {
264 unsigned int pc;
442ea881 265 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 266 return (CORE_ADDR) pc;
267 }
268 else
269 {
270 unsigned long pc;
442ea881 271 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 272 return (CORE_ADDR) pc;
273 }
0d62e5e8
DJ		 274}
275
276static void
442ea881 277ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 278{
0b9ff2c0
UW		 279 CORE_ADDR addr;
280 int fd;
281
442ea881 282 if (parse_spufs_run (regcache, &fd, &addr))
0b9ff2c0
UW		 283 {
284 unsigned int newpc = pc;
285 (*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
286 }
3aee8918 287 else if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 288 {
289 unsigned int newpc = pc;
442ea881 290 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 291 }
292 else
293 {
294 unsigned long newpc = pc;
442ea881 295 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 296 }
297}
298
b6430ec3
UW		 299
300static int
a2174ba4 301ppc_get_auxv (unsigned long type, unsigned long *valp)
b6430ec3 302{
3aee8918
PA		 303 const struct target_desc *tdesc = current_process ()->tdesc;
304 int wordsize = register_size (tdesc, 0);
2bc84e8a 305 unsigned char *data = (unsigned char *) alloca (2 * wordsize);
b6430ec3
UW		 306 int offset = 0;
307
308 while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
309 {
310 if (wordsize == 4)
311 {
312 unsigned int *data_p = (unsigned int *)data;
a2174ba4 313 if (data_p[0] == type)
b6430ec3
UW		 314 {
315 *valp = data_p[1];
316 return 1;
317 }
318 }
319 else
320 {
321 unsigned long *data_p = (unsigned long *)data;
a2174ba4 322 if (data_p[0] == type)
b6430ec3
UW		 323 {
324 *valp = data_p[1];
325 return 1;
326 }
327 }
328
329 offset += 2 * wordsize;
330 }
331
332 *valp = 0;
333 return 0;
334}
335
3aee8918
PA		 336#ifndef __powerpc64__
337static int ppc_regmap_adjusted;
338#endif
339
0d62e5e8 340
5b0a002e 341/* Correct in either endianness.
0d62e5e8
DJ		 342 This instruction is "twge r2, r2", which GDB uses as a software
343 breakpoint. */
5b0a002e 344static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 345#define ppc_breakpoint_len 4
346
dd373349
AT		 347/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
348
349static const gdb_byte *
350ppc_sw_breakpoint_from_kind (int kind, int *size)
351{
352 *size = ppc_breakpoint_len;
353 return (const gdb_byte *) &ppc_breakpoint;
354}
355
0d62e5e8
DJ		 356static int
357ppc_breakpoint_at (CORE_ADDR where)
358{
5b0a002e 359 unsigned int insn;
0d62e5e8 360
0b9ff2c0
UW		 361 if (where & ((CORE_ADDR)1 << 63))
362 {
363 char mem_annex[32];
364 sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
365 (*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
366 NULL, where & 0xffffffff, 4);
367 if (insn == 0x3fff)
368 return 1;
369 }
370 else
371 {
372 (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
373 if (insn == ppc_breakpoint)
374 return 1;
375 /* If necessary, recognize more trap instructions here. GDB only uses
376 the one. */
377 }
378
0d62e5e8
DJ		 379 return 0;
380}
381
657f9cde
WW		 382/* Implement supports_z_point_type target-ops.
383 Returns true if type Z_TYPE breakpoint is supported.
384
385 Handling software breakpoint at server side, so tracepoints
386 and breakpoints can be inserted at the same location. */
387
388static int
389ppc_supports_z_point_type (char z_type)
390{
391 switch (z_type)
392 {
393 case Z_PACKET_SW_BP:
394 return 1;
395 case Z_PACKET_HW_BP:
396 case Z_PACKET_WRITE_WP:
397 case Z_PACKET_ACCESS_WP:
398 default:
399 return 0;
400 }
401}
402
403/* Implement insert_point target-ops.
404 Returns 0 on success, -1 on failure and 1 on unsupported. */
405
406static int
407ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
408 int size, struct raw_breakpoint *bp)
409{
410 switch (type)
411 {
412 case raw_bkpt_type_sw:
413 return insert_memory_breakpoint (bp);
414
415 case raw_bkpt_type_hw:
416 case raw_bkpt_type_write_wp:
417 case raw_bkpt_type_access_wp:
418 default:
419 /* Unsupported. */
420 return 1;
421 }
422}
423
424/* Implement remove_point target-ops.
425 Returns 0 on success, -1 on failure and 1 on unsupported. */
426
427static int
428ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
429 int size, struct raw_breakpoint *bp)
430{
431 switch (type)
432 {
433 case raw_bkpt_type_sw:
434 return remove_memory_breakpoint (bp);
435
436 case raw_bkpt_type_hw:
437 case raw_bkpt_type_write_wp:
438 case raw_bkpt_type_access_wp:
439 default:
440 /* Unsupported. */
441 return 1;
442 }
443}
444
e9d25b98
DJ		 445/* Provide only a fill function for the general register set. ps_lgetregs
446 will use this for NPTL support. */
447
442ea881 448static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 449{
450 int i;
451
452 for (i = 0; i < 32; i++)
442ea881 453 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 454
455 for (i = 64; i < 70; i++)
442ea881 456 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 457
458 for (i = 71; i < 73; i++)
442ea881 459 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 460}
461
677c5bb1
LM		 462#define SIZEOF_VSXREGS 32*8
463
464static void
442ea881 465ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 466{
467 int i, base;
2bc84e8a 468 char *regset = (char *) buf;
677c5bb1
LM		 469
470 if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
471 return;
472
3aee8918 473 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 474 for (i = 0; i < 32; i++)
442ea881 475 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 476}
477
478static void
442ea881 479ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 480{
481 int i, base;
2bc84e8a 482 const char *regset = (const char *) buf;
677c5bb1
LM		 483
484 if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
485 return;
486
3aee8918 487 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 488 for (i = 0; i < 32; i++)
442ea881 489 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 490}
491
30ed0a8f
DJ		 492#define SIZEOF_VRREGS 33*16+4
493
494static void
442ea881 495ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 496{
497 int i, base;
2bc84e8a 498 char *regset = (char *) buf;
30ed0a8f 499
b6430ec3
UW		 500 if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
501 return;
502
3aee8918 503 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 504 for (i = 0; i < 32; i++)
442ea881 505 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 506
442ea881
PA		 507 collect_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
508 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 509}
510
511static void
442ea881 512ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 513{
514 int i, base;
2bc84e8a 515 const char *regset = (const char *) buf;
30ed0a8f 516
b6430ec3
UW		 517 if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
518 return;
519
3aee8918 520 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 521 for (i = 0; i < 32; i++)
442ea881 522 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 523
442ea881
PA		 524 supply_register_by_name (regcache, "vscr", &regset[32 * 16 + 12]);
525 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 526}
527
30ed0a8f
DJ		 528struct gdb_evrregset_t
529{
530 unsigned long evr[32];
531 unsigned long long acc;
532 unsigned long spefscr;
533};
534
535static void
442ea881 536ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 537{
538 int i, ev0;
2bc84e8a 539 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 540
b6430ec3
UW		 541 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
542 return;
543
3aee8918 544 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 545 for (i = 0; i < 32; i++)
442ea881 546 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 547
442ea881
PA		 548 collect_register_by_name (regcache, "acc", &regset->acc);
549 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 550}
551
552static void
442ea881 553ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 554{
555 int i, ev0;
2bc84e8a 556 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 557
b6430ec3
UW		 558 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
559 return;
560
3aee8918 561 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 562 for (i = 0; i < 32; i++)
442ea881 563 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 564
442ea881
PA		 565 supply_register_by_name (regcache, "acc", &regset->acc);
566 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 567}
30ed0a8f 568
7d00775e
AT		 569/* Support for hardware single step. */
570
571static int
572ppc_supports_hardware_single_step (void)
573{
574 return 1;
575}
576
3aee8918 577static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 578 /* List the extra register sets before GENERAL_REGS. That way we will
579 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
580 general registers. Some kernels support these, but not the newer
581 PPC_PTRACE_GETREGS. */
1570b33e 582 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS,
677c5bb1 583 ppc_fill_vsxregset, ppc_store_vsxregset },
1570b33e 584 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS,
30ed0a8f 585 ppc_fill_vrregset, ppc_store_vrregset },
1570b33e 586 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS,
30ed0a8f 587 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 588 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 589 NULL_REGSET
e9d25b98
DJ		 590};
591
3aee8918
PA		 592static struct usrregs_info ppc_usrregs_info =
593 {
594 ppc_num_regs,
595 ppc_regmap,
596 };
597
598static struct regsets_info ppc_regsets_info =
599 {
600 ppc_regsets, /* regsets */
601 0, /* num_regsets */
602 NULL, /* disabled_regsets */
603 };
604
605static struct regs_info regs_info =
606 {
607 NULL, /* regset_bitmap */
608 &ppc_usrregs_info,
609 &ppc_regsets_info
610 };
611
612static const struct regs_info *
613ppc_regs_info (void)
614{
615 return &regs_info;
616}
617
e6c5bb05
SM		 618static void
619ppc_arch_setup (void)
620{
621 const struct target_desc *tdesc;
bd64614e 622 struct ppc_linux_features features = ppc_linux_no_features;
2e077f5e 623 int tid = lwpid_of (current_thread);
bd64614e 624
2e077f5e 625 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 626
bd64614e 627 if (features.wordsize == 4)
bd64614e 628 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 629 else
630 tdesc = tdesc_powerpc_64l;
631
632 current_process ()->tdesc = tdesc;
e6c5bb05 633
bd64614e
PFC		 634 /* The value of current_process ()->tdesc needs to be set for this
635 call. */
a2174ba4 636 ppc_get_auxv (AT_HWCAP, &ppc_hwcap);
bd64614e
PFC		 637
638 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
639
640 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
641 features.vsx = true;
642
643 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
644 features.altivec = true;
645
e6c5bb05 646 if (ppc_hwcap & PPC_FEATURE_CELL)
bd64614e
PFC		 647 features.cell = true;
648
649 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 650
651 /* On 32-bit machines, check for SPE registers.
652 Set the low target's regmap field as appropriately. */
653#ifndef __powerpc64__
654 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
655 tdesc = tdesc_powerpc_e500l;
656
657 if (!ppc_regmap_adjusted)
658 {
659 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
660 ppc_usrregs_info.regmap = ppc_regmap_e500;
661
662 /* If the FPSCR is 64-bit wide, we need to fetch the whole
663 64-bit slot and not just its second word. The PT_FPSCR
664 supplied in a 32-bit GDB compilation doesn't reflect
665 this. */
666 if (register_size (tdesc, 70) == 8)
667 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
668
669 ppc_regmap_adjusted = 1;
670 }
671#endif
bd64614e 672
e6c5bb05
SM		 673 current_process ()->tdesc = tdesc;
674}
675
a2174ba4
MK		 676/* Implementation of linux_target_ops method "supports_tracepoints". */
677
b04fd3be
MK		 678static int
679ppc_supports_tracepoints (void)
680{
681 return 1;
682}
683
a2174ba4
MK		 684/* Get the thread area address. This is used to recognize which
685 thread is which when tracing with the in-process agent library. We
686 don't read anything from the address, and treat it as opaque; it's
687 the address itself that we assume is unique per-thread. */
688
689static int
690ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
691{
692 struct lwp_info *lwp = find_lwp_pid (pid_to_ptid (lwpid));
693 struct thread_info *thr = get_lwp_thread (lwp);
694 struct regcache *regcache = get_thread_regcache (thr, 1);
695 ULONGEST tp = 0;
696
697#ifdef __powerpc64__
698 if (register_size (regcache->tdesc, 0) == 8)
699 collect_register_by_name (regcache, "r13", &tp);
700 else
701#endif
702 collect_register_by_name (regcache, "r2", &tp);
703
704 *addr = tp;
705
706 return 0;
707}
708
709#ifdef __powerpc64__
710
711/* Older glibc doesn't provide this. */
712
713#ifndef EF_PPC64_ABI
714#define EF_PPC64_ABI 3
715#endif
716
717/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
718 inferiors. */
719
720static int
721is_elfv2_inferior (void)
722{
723 /* To be used as fallback if we're unable to determine the right result -
724 assume inferior uses the same ABI as gdbserver. */
725#if _CALL_ELF == 2
726 const int def_res = 1;
727#else
728 const int def_res = 0;
729#endif
730 unsigned long phdr;
731 Elf64_Ehdr ehdr;
732
733 if (!ppc_get_auxv (AT_PHDR, &phdr))
734 return def_res;
735
736 /* Assume ELF header is at the beginning of the page where program headers
737 are located. If it doesn't look like one, bail. */
738
739 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
740 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
741 return def_res;
742
743 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
744}
745
746#endif
747
748/* Generate a ds-form instruction in BUF and return the number of bytes written
749
750 0 6 11 16 30 32
751 | OPCD | RST | RA | DS |XO| */
752
753__attribute__((unused)) /* Maybe unused due to conditional compilation. */
754static int
755gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
756{
757 uint32_t insn;
758
759 gdb_assert ((opcd & ~0x3f) == 0);
760 gdb_assert ((rst & ~0x1f) == 0);
761 gdb_assert ((ra & ~0x1f) == 0);
762 gdb_assert ((xo & ~0x3) == 0);
763
764 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
765 *buf = (opcd << 26) | insn;
766 return 1;
767}
768
769/* Followings are frequently used ds-form instructions. */
770
771#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
772#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
773#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
774#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
775
776/* Generate a d-form instruction in BUF.
777
778 0 6 11 16 32
779 | OPCD | RST | RA | D | */
780
781static int
782gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
783{
784 uint32_t insn;
785
786 gdb_assert ((opcd & ~0x3f) == 0);
787 gdb_assert ((rst & ~0x1f) == 0);
788 gdb_assert ((ra & ~0x1f) == 0);
789
790 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
791 *buf = (opcd << 26) | insn;
792 return 1;
793}
794
795/* Followings are frequently used d-form instructions. */
796
797#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
798#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
799#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
800#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
801#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
802#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
803#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
804#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
805#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
806
807/* Generate a xfx-form instruction in BUF and return the number of bytes
808 written.
809
810 0 6 11 21 31 32
811 | OPCD | RST | RI | XO |/| */
812
813static int
814gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
815{
816 uint32_t insn;
817 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
818
819 gdb_assert ((opcd & ~0x3f) == 0);
820 gdb_assert ((rst & ~0x1f) == 0);
821 gdb_assert ((xo & ~0x3ff) == 0);
822
823 insn = (rst << 21) | (n << 11) | (xo << 1);
824 *buf = (opcd << 26) | insn;
825 return 1;
826}
827
828/* Followings are frequently used xfx-form instructions. */
829
830#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
831#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
832#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
833#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
834#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
835 E & 0xf, 598)
836#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
837
838
839/* Generate a x-form instruction in BUF and return the number of bytes written.
840
841 0 6 11 16 21 31 32
842 | OPCD | RST | RA | RB | XO |RC| */
843
844static int
845gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
846{
847 uint32_t insn;
848
849 gdb_assert ((opcd & ~0x3f) == 0);
850 gdb_assert ((rst & ~0x1f) == 0);
851 gdb_assert ((ra & ~0x1f) == 0);
852 gdb_assert ((rb & ~0x1f) == 0);
853 gdb_assert ((xo & ~0x3ff) == 0);
854 gdb_assert ((rc & ~1) == 0);
855
856 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
857 *buf = (opcd << 26) | insn;
858 return 1;
859}
860
861/* Followings are frequently used x-form instructions. */
862
863#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
864#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
865#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
866#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
867/* Assume bf = cr7. */
868#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
869
870
871/* Generate a md-form instruction in BUF and return the number of bytes written.
872
873 0 6 11 16 21 27 30 31 32
874 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
875
876static int
877gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
878 int xo, int rc)
879{
880 uint32_t insn;
881 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
882 unsigned int sh0_4 = sh & 0x1f;
883 unsigned int sh5 = (sh >> 5) & 1;
884
885 gdb_assert ((opcd & ~0x3f) == 0);
886 gdb_assert ((rs & ~0x1f) == 0);
887 gdb_assert ((ra & ~0x1f) == 0);
888 gdb_assert ((sh & ~0x3f) == 0);
889 gdb_assert ((mb & ~0x3f) == 0);
890 gdb_assert ((xo & ~0x7) == 0);
891 gdb_assert ((rc & ~0x1) == 0);
892
893 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
894 | (sh5 << 1) | (xo << 2) | (rc & 1);
895 *buf = (opcd << 26) | insn;
896 return 1;
897}
898
899/* The following are frequently used md-form instructions. */
900
901#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
902 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
903#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
904 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
905
906/* Generate a i-form instruction in BUF and return the number of bytes written.
907
908 0 6 30 31 32
909 | OPCD | LI |AA|LK| */
910
911static int
912gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
913{
914 uint32_t insn;
915
916 gdb_assert ((opcd & ~0x3f) == 0);
917
918 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
919 *buf = (opcd << 26) | insn;
920 return 1;
921}
922
923/* The following are frequently used i-form instructions. */
924
925#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
926#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
927
928/* Generate a b-form instruction in BUF and return the number of bytes written.
929
930 0 6 11 16 30 31 32
931 | OPCD | BO | BI | BD |AA|LK| */
932
933static int
934gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
935 int aa, int lk)
936{
937 uint32_t insn;
938
939 gdb_assert ((opcd & ~0x3f) == 0);
940 gdb_assert ((bo & ~0x1f) == 0);
941 gdb_assert ((bi & ~0x1f) == 0);
942
943 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
944 *buf = (opcd << 26) | insn;
945 return 1;
946}
947
948/* The following are frequently used b-form instructions. */
949/* Assume bi = cr7. */
950#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
951
952/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
953 respectively. They are primary used for save/restore GPRs in jump-pad,
954 not used for bytecode compiling. */
955
956#ifdef __powerpc64__
957#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
958 GEN_LD (buf, rt, ra, si) : \
959 GEN_LWZ (buf, rt, ra, si))
960#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
961 GEN_STD (buf, rt, ra, si) : \
962 GEN_STW (buf, rt, ra, si))
963#else
964#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
965#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
966#endif
967
968/* Generate a sequence of instructions to load IMM in the register REG.
969 Write the instructions in BUF and return the number of bytes written. */
970
971static int
972gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
973{
974 uint32_t *p = buf;
975
976 if ((imm + 32768) < 65536)
977 {
978 /* li reg, imm[15:0] */
979 p += GEN_LI (p, reg, imm);
980 }
981 else if ((imm >> 32) == 0)
982 {
983 /* lis reg, imm[31:16]
984 ori reg, reg, imm[15:0]
985 rldicl reg, reg, 0, 32 */
986 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
987 if ((imm & 0xffff) != 0)
988 p += GEN_ORI (p, reg, reg, imm & 0xffff);
989 /* Clear upper 32-bit if sign-bit is set. */
990 if (imm & (1u << 31) && is_64)
991 p += GEN_RLDICL (p, reg, reg, 0, 32);
992 }
993 else
994 {
995 gdb_assert (is_64);
996 /* lis reg, <imm[63:48]>
997 ori reg, reg, <imm[48:32]>
998 rldicr reg, reg, 32, 31
999 oris reg, reg, <imm[31:16]>
1000 ori reg, reg, <imm[15:0]> */
1001 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1002 if (((imm >> 32) & 0xffff) != 0)
1003 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1004 p += GEN_RLDICR (p, reg, reg, 32, 31);
1005 if (((imm >> 16) & 0xffff) != 0)
1006 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1007 if ((imm & 0xffff) != 0)
1008 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1009 }
1010
1011 return p - buf;
1012}
1013
1014/* Generate a sequence for atomically exchange at location LOCK.
1015 This code sequence clobbers r6, r7, r8. LOCK is the location for
1016 the atomic-xchg, OLD_VALUE is expected old value stored in the
1017 location, and R_NEW is a register for the new value. */
1018
1019static int
1020gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1021 int is_64)
1022{
1023 const int r_lock = 6;
1024 const int r_old = 7;
1025 const int r_tmp = 8;
1026 uint32_t *p = buf;
1027
1028 /*
1029 1: lwarx TMP, 0, LOCK
1030 cmpwi TMP, OLD
1031 bne 1b
1032 stwcx. NEW, 0, LOCK
1033 bne 1b */
1034
1035 p += gen_limm (p, r_lock, lock, is_64);
1036 p += gen_limm (p, r_old, old_value, is_64);
1037
1038 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1039 p += GEN_CMPW (p, r_tmp, r_old);
1040 p += GEN_BNE (p, -8);
1041 p += GEN_STWCX (p, r_new, 0, r_lock);
1042 p += GEN_BNE (p, -16);
1043
1044 return p - buf;
1045}
1046
1047/* Generate a sequence of instructions for calling a function
1048 at address of FN. Return the number of bytes are written in BUF. */
1049
1050static int
1051gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1052{
1053 uint32_t *p = buf;
1054
1055 /* Must be called by r12 for caller to calculate TOC address. */
1056 p += gen_limm (p, 12, fn, is_64);
1057 if (is_opd)
1058 {
1059 p += GEN_LOAD (p, 11, 12, 16, is_64);
1060 p += GEN_LOAD (p, 2, 12, 8, is_64);
1061 p += GEN_LOAD (p, 12, 12, 0, is_64);
1062 }
1063 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1064 *p++ = 0x4e800421; /* bctrl */
1065
1066 return p - buf;
1067}
1068
1069/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1070 of instruction. This function is used to adjust pc-relative instructions
1071 when copying. */
1072
1073static void
1074ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1075{
1076 uint32_t insn, op6;
1077 long rel, newrel;
1078
1079 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1080 op6 = PPC_OP6 (insn);
1081
1082 if (op6 == 18 && (insn & 2) == 0)
1083 {
1084 /* branch && AA = 0 */
1085 rel = PPC_LI (insn);
1086 newrel = (oldloc - *to) + rel;
1087
1088 /* Out of range. Cannot relocate instruction. */
1089 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1090 return;
1091
1092 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1093 }
1094 else if (op6 == 16 && (insn & 2) == 0)
1095 {
1096 /* conditional branch && AA = 0 */
1097
1098 /* If the new relocation is too big for even a 26-bit unconditional
1099 branch, there is nothing we can do. Just abort.
1100
1101 Otherwise, if it can be fit in 16-bit conditional branch, just
1102 copy the instruction and relocate the address.
1103
1104 If the it's big for conditional-branch (16-bit), try to invert the
1105 condition and jump with 26-bit branch. For example,
1106
1107 beq .Lgoto
1108 INSN1
1109
1110 =>
1111
1112 bne 1f (+8)
1113 b .Lgoto
1114 1:INSN1
1115
1116 After this transform, we are actually jump from *TO+4 instead of *TO,
1117 so check the relocation again because it will be 1-insn farther then
1118 before if *TO is after OLDLOC.
1119
1120
1121 For BDNZT (or so) is transformed from
1122
1123 bdnzt eq, .Lgoto
1124 INSN1
1125
1126 =>
1127
1128 bdz 1f (+12)
1129 bf eq, 1f (+8)
1130 b .Lgoto
1131 1:INSN1
1132
1133 See also "BO field encodings". */
1134
1135 rel = PPC_BD (insn);
1136 newrel = (oldloc - *to) + rel;
1137
1138 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1139 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1140 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1141 {
1142 newrel -= 4;
1143
1144 /* Out of range. Cannot relocate instruction. */
1145 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1146 return;
1147
1148 if ((PPC_BO (insn) & 0x14) == 0x4)
1149 insn ^= (1 << 24);
1150 else if ((PPC_BO (insn) & 0x14) == 0x10)
1151 insn ^= (1 << 22);
1152
1153 /* Jump over the unconditional branch. */
1154 insn = (insn & ~0xfffc) | 0x8;
1155 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1156 *to += 4;
1157
1158 /* Build a unconditional branch and copy LK bit. */
1159 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1160 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1161 *to += 4;
1162
1163 return;
1164 }
1165 else if ((PPC_BO (insn) & 0x14) == 0)
1166 {
1167 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1168 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1169
1170 newrel -= 8;
1171
1172 /* Out of range. Cannot relocate instruction. */
1173 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1174 return;
1175
1176 /* Copy BI field. */
1177 bf_insn |= (insn & 0x1f0000);
1178
1179 /* Invert condition. */
1180 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1181 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1182
1183 write_inferior_memory (*to, (unsigned char *) &bdnz_insn, 4);
1184 *to += 4;
1185 write_inferior_memory (*to, (unsigned char *) &bf_insn, 4);
1186 *to += 4;
1187
1188 /* Build a unconditional branch and copy LK bit. */
1189 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1190 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1191 *to += 4;
1192
1193 return;
1194 }
1195 else /* (BO & 0x14) == 0x14, branch always. */
1196 {
1197 /* Out of range. Cannot relocate instruction. */
1198 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1199 return;
1200
1201 /* Build a unconditional branch and copy LK bit. */
1202 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
1203 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1204 *to += 4;
1205
1206 return;
1207 }
1208 }
1209
1210 write_inferior_memory (*to, (unsigned char *) &insn, 4);
1211 *to += 4;
1212}
1213
1214/* Implement install_fast_tracepoint_jump_pad of target_ops.
1215 See target.h for details. */
1216
1217static int
1218ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1219 CORE_ADDR collector,
1220 CORE_ADDR lockaddr,
1221 ULONGEST orig_size,
1222 CORE_ADDR *jump_entry,
1223 CORE_ADDR *trampoline,
1224 ULONGEST *trampoline_size,
1225 unsigned char *jjump_pad_insn,
1226 ULONGEST *jjump_pad_insn_size,
1227 CORE_ADDR *adjusted_insn_addr,
1228 CORE_ADDR *adjusted_insn_addr_end,
1229 char *err)
1230{
1231 uint32_t buf[256];
1232 uint32_t *p = buf;
1233 int j, offset;
1234 CORE_ADDR buildaddr = *jump_entry;
1235 const CORE_ADDR entryaddr = *jump_entry;
1236 int rsz, min_frame, frame_size, tp_reg;
1237#ifdef __powerpc64__
1238 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1239 int is_64 = register_size (regcache->tdesc, 0) == 8;
1240 int is_opd = is_64 && !is_elfv2_inferior ();
1241#else
1242 int is_64 = 0, is_opd = 0;
1243#endif
1244
1245#ifdef __powerpc64__
1246 if (is_64)
1247 {
1248 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1249 rsz = 8;
1250 min_frame = 112;
1251 frame_size = (40 * rsz) + min_frame;
1252 tp_reg = 13;
1253 }
1254 else
1255 {
1256#endif
1257 rsz = 4;
1258 min_frame = 16;
1259 frame_size = (40 * rsz) + min_frame;
1260 tp_reg = 2;
1261#ifdef __powerpc64__
1262 }
1263#endif
1264
1265 /* Stack frame layout for this jump pad,
1266
1267 High thread_area (r13/r2) |
1268 tpoint - collecting_t obj
1269 PC/<tpaddr> | +36
1270 CTR | +35
1271 LR | +34
1272 XER | +33
1273 CR | +32
1274 R31 |
1275 R29 |
1276 ... |
1277 R1 | +1
1278 R0 - collected registers
1279 ... |
1280 ... |
1281 Low Back-chain -
1282
1283
1284 The code flow of this jump pad,
1285
1286 1. Adjust SP
1287 2. Save GPR and SPR
1288 3. Prepare argument
1289 4. Call gdb_collector
1290 5. Restore GPR and SPR
1291 6. Restore SP
1292 7. Build a jump for back to the program
1293 8. Copy/relocate original instruction
1294 9. Build a jump for replacing orignal instruction. */
1295
1296 /* Adjust stack pointer. */
1297 if (is_64)
1298 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1299 else
1300 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1301
1302 /* Store GPRs. Save R1 later, because it had just been modified, but
1303 we want the original value. */
1304 for (j = 2; j < 32; j++)
1305 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1306 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1307 /* Set r0 to the original value of r1 before adjusting stack frame,
1308 and then save it. */
1309 p += GEN_ADDI (p, 0, 1, frame_size);
1310 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1311
1312 /* Save CR, XER, LR, and CTR. */
1313 p += GEN_MFCR (p, 3); /* mfcr r3 */
1314 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1315 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1316 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1317 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1318 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1319 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1320 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1321
1322 /* Save PC<tpaddr> */
1323 p += gen_limm (p, 3, tpaddr, is_64);
1324 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1325
1326
1327 /* Setup arguments to collector. */
1328 /* Set r4 to collected registers. */
1329 p += GEN_ADDI (p, 4, 1, min_frame);
1330 /* Set r3 to TPOINT. */
1331 p += gen_limm (p, 3, tpoint, is_64);
1332
1333 /* Prepare collecting_t object for lock. */
1334 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1335 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1336 /* Set R5 to collecting object. */
1337 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1338
1339 p += GEN_LWSYNC (p);
1340 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1341 p += GEN_LWSYNC (p);
1342
1343 /* Call to collector. */
1344 p += gen_call (p, collector, is_64, is_opd);
1345
1346 /* Simply write 0 to release the lock. */
1347 p += gen_limm (p, 3, lockaddr, is_64);
1348 p += gen_limm (p, 4, 0, is_64);
1349 p += GEN_LWSYNC (p);
1350 p += GEN_STORE (p, 4, 3, 0, is_64);
1351
1352 /* Restore stack and registers. */
1353 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1354 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1355 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1356 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1357 p += GEN_MTCR (p, 3); /* mtcr r3 */
1358 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1359 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1360 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1361
1362 /* Restore GPRs. */
1363 for (j = 2; j < 32; j++)
1364 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1365 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1366 /* Restore SP. */
1367 p += GEN_ADDI (p, 1, 1, frame_size);
1368
1369 /* Flush instructions to inferior memory. */
1370 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1371
1372 /* Now, insert the original instruction to execute in the jump pad. */
1373 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1374 *adjusted_insn_addr_end = *adjusted_insn_addr;
1375 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1376
1377 /* Verify the relocation size. If should be 4 for normal copy,
1378 8 or 12 for some conditional branch. */
1379 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1380 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1381 {
1382 sprintf (err, "E.Unexpected instruction length = %d"
1383 "when relocate instruction.",
1384 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1385 return 1;
1386 }
1387
1388 buildaddr = *adjusted_insn_addr_end;
1389 p = buf;
1390 /* Finally, write a jump back to the program. */
1391 offset = (tpaddr + 4) - buildaddr;
1392 if (offset >= (1 << 25) || offset < -(1 << 25))
1393 {
1394 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1395 "(offset 0x%x > 26-bit).", offset);
1396 return 1;
1397 }
1398 /* b <tpaddr+4> */
1399 p += GEN_B (p, offset);
1400 write_inferior_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
1401 *jump_entry = buildaddr + (p - buf) * 4;
1402
1403 /* The jump pad is now built. Wire in a jump to our jump pad. This
1404 is always done last (by our caller actually), so that we can
1405 install fast tracepoints with threads running. This relies on
1406 the agent's atomic write support. */
1407 offset = entryaddr - tpaddr;
1408 if (offset >= (1 << 25) || offset < -(1 << 25))
1409 {
1410 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1411 "(offset 0x%x > 26-bit).", offset);
1412 return 1;
1413 }
1414 /* b <jentry> */
1415 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1416 *jjump_pad_insn_size = 4;
1417
1418 return 0;
1419}
1420
1421/* Returns the minimum instruction length for installing a tracepoint. */
1422
1423static int
1424ppc_get_min_fast_tracepoint_insn_len (void)
1425{
1426 return 4;
1427}
1428
14e2b6d9
MK		 1429/* Emits a given buffer into the target at current_insn_ptr. Length
1430 is in units of 32-bit words. */
1431
1432static void
1433emit_insns (uint32_t *buf, int n)
1434{
1435 n = n * sizeof (uint32_t);
1436 write_inferior_memory (current_insn_ptr, (unsigned char *) buf, n);
1437 current_insn_ptr += n;
1438}
1439
1440#define __EMIT_ASM(NAME, INSNS) \
1441 do \
1442 { \
1443 extern uint32_t start_bcax_ ## NAME []; \
1444 extern uint32_t end_bcax_ ## NAME []; \
1445 emit_insns (start_bcax_ ## NAME, \
1446 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1447 __asm__ (".section .text.__ppcbcax\n\t" \
1448 "start_bcax_" #NAME ":\n\t" \
1449 INSNS "\n\t" \
1450 "end_bcax_" #NAME ":\n\t" \
1451 ".previous\n\t"); \
1452 } while (0)
1453
1454#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1455#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1456
1457/*
1458
1459 Bytecode execution stack frame - 32-bit
1460
1461 | LR save area (SP + 4)
1462 SP' -> +- Back chain (SP + 0)
1463 | Save r31 for access saved arguments
1464 | Save r30 for bytecode stack pointer
1465 | Save r4 for incoming argument *value
1466 | Save r3 for incoming argument regs
1467 r30 -> +- Bytecode execution stack
1468 |
1469 | 64-byte (8 doublewords) at initial.
1470 | Expand stack as needed.
1471 |
1472 +-
1473 | Some padding for minimum stack frame and 16-byte alignment.
1474 | 16 bytes.
1475 SP +- Back-chain (SP')
1476
1477 initial frame size
1478 = 16 + (4 * 4) + 64
1479 = 96
1480
1481 r30 is the stack-pointer for bytecode machine.
1482 It should point to next-empty, so we can use LDU for pop.
1483 r3 is used for cache of the high part of TOP value.
1484 It was the first argument, pointer to regs.
1485 r4 is used for cache of the low part of TOP value.
1486 It was the second argument, pointer to the result.
1487 We should set *result = TOP after leaving this function.
1488
1489 Note:
1490 * To restore stack at epilogue
1491 => sp = r31
1492 * To check stack is big enough for bytecode execution.
1493 => r30 - 8 > SP + 8
1494 * To return execution result.
1495 => 0(r4) = TOP
1496
1497 */
1498
1499/* Regardless of endian, register 3 is always high part, 4 is low part.
1500 These defines are used when the register pair is stored/loaded.
1501 Likewise, to simplify code, have a similiar define for 5:6. */
1502
1503#if __BYTE_ORDER == __LITTLE_ENDIAN
1504#define TOP_FIRST "4"
1505#define TOP_SECOND "3"
1506#define TMP_FIRST "6"
1507#define TMP_SECOND "5"
1508#else
1509#define TOP_FIRST "3"
1510#define TOP_SECOND "4"
1511#define TMP_FIRST "5"
1512#define TMP_SECOND "6"
1513#endif
1514
1515/* Emit prologue in inferior memory. See above comments. */
1516
1517static void
1518ppc_emit_prologue (void)
1519{
1520 EMIT_ASM (/* Save return address. */
1521 "mflr 0 \n"
1522 "stw 0, 4(1) \n"
1523 /* Adjust SP. 96 is the initial frame size. */
1524 "stwu 1, -96(1) \n"
1525 /* Save r30 and incoming arguments. */
1526 "stw 31, 96-4(1) \n"
1527 "stw 30, 96-8(1) \n"
1528 "stw 4, 96-12(1) \n"
1529 "stw 3, 96-16(1) \n"
1530 /* Point r31 to original r1 for access arguments. */
1531 "addi 31, 1, 96 \n"
1532 /* Set r30 to pointing stack-top. */
1533 "addi 30, 1, 64 \n"
1534 /* Initial r3/TOP to 0. */
1535 "li 3, 0 \n"
1536 "li 4, 0 \n");
1537}
1538
1539/* Emit epilogue in inferior memory. See above comments. */
1540
1541static void
1542ppc_emit_epilogue (void)
1543{
1544 EMIT_ASM (/* *result = TOP */
1545 "lwz 5, -12(31) \n"
1546 "stw " TOP_FIRST ", 0(5) \n"
1547 "stw " TOP_SECOND ", 4(5) \n"
1548 /* Restore registers. */
1549 "lwz 31, -4(31) \n"
1550 "lwz 30, -8(31) \n"
1551 /* Restore SP. */
1552 "lwz 1, 0(1) \n"
1553 /* Restore LR. */
1554 "lwz 0, 4(1) \n"
1555 /* Return 0 for no-error. */
1556 "li 3, 0 \n"
1557 "mtlr 0 \n"
1558 "blr \n");
1559}
1560
1561/* TOP = stack[--sp] + TOP */
1562
1563static void
1564ppc_emit_add (void)
1565{
1566 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1567 "lwz " TMP_SECOND ", 4(30)\n"
1568 "addc 4, 6, 4 \n"
1569 "adde 3, 5, 3 \n");
1570}
1571
1572/* TOP = stack[--sp] - TOP */
1573
1574static void
1575ppc_emit_sub (void)
1576{
1577 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1578 "lwz " TMP_SECOND ", 4(30) \n"
1579 "subfc 4, 4, 6 \n"
1580 "subfe 3, 3, 5 \n");
1581}
1582
1583/* TOP = stack[--sp] * TOP */
1584
1585static void
1586ppc_emit_mul (void)
1587{
1588 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1589 "lwz " TMP_SECOND ", 4(30) \n"
1590 "mulhwu 7, 6, 4 \n"
1591 "mullw 3, 6, 3 \n"
1592 "mullw 5, 4, 5 \n"
1593 "mullw 4, 6, 4 \n"
1594 "add 3, 5, 3 \n"
1595 "add 3, 7, 3 \n");
1596}
1597
1598/* TOP = stack[--sp] << TOP */
1599
1600static void
1601ppc_emit_lsh (void)
1602{
1603 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1604 "lwz " TMP_SECOND ", 4(30) \n"
1605 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1606 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1607 "slw 5, 5, 4\n" /* Shift high part left */
1608 "slw 4, 6, 4\n" /* Shift low part left */
1609 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1610 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1611 "or 3, 5, 3\n"
1612 "or 3, 7, 3\n"); /* Assemble high part */
1613}
1614
1615/* Top = stack[--sp] >> TOP
1616 (Arithmetic shift right) */
1617
1618static void
1619ppc_emit_rsh_signed (void)
1620{
1621 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1622 "lwz " TMP_SECOND ", 4(30) \n"
1623 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1624 "sraw 3, 5, 4\n" /* Shift high part right */
1625 "cmpwi 7, 1\n"
1626 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1627 "sraw 4, 5, 7\n" /* Shift high to low */
1628 "b 2f\n"
1629 "1:\n"
1630 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1631 "srw 4, 6, 4\n" /* Shift low part right */
1632 "slw 5, 5, 7\n" /* Shift high to low */
1633 "or 4, 4, 5\n" /* Assemble low part */
1634 "2:\n");
1635}
1636
1637/* Top = stack[--sp] >> TOP
1638 (Logical shift right) */
1639
1640static void
1641ppc_emit_rsh_unsigned (void)
1642{
1643 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1644 "lwz " TMP_SECOND ", 4(30) \n"
1645 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1646 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1647 "srw 6, 6, 4\n" /* Shift low part right */
1648 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1649 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1650 "or 6, 6, 3\n"
1651 "srw 3, 5, 4\n" /* Shift high part right */
1652 "or 4, 6, 7\n"); /* Assemble low part */
1653}
1654
1655/* Emit code for signed-extension specified by ARG. */
1656
1657static void
1658ppc_emit_ext (int arg)
1659{
1660 switch (arg)
1661 {
1662 case 8:
1663 EMIT_ASM ("extsb 4, 4\n"
1664 "srawi 3, 4, 31");
1665 break;
1666 case 16:
1667 EMIT_ASM ("extsh 4, 4\n"
1668 "srawi 3, 4, 31");
1669 break;
1670 case 32:
1671 EMIT_ASM ("srawi 3, 4, 31");
1672 break;
1673 default:
1674 emit_error = 1;
1675 }
1676}
1677
1678/* Emit code for zero-extension specified by ARG. */
1679
1680static void
1681ppc_emit_zero_ext (int arg)
1682{
1683 switch (arg)
1684 {
1685 case 8:
1686 EMIT_ASM ("clrlwi 4,4,24\n"
1687 "li 3, 0\n");
1688 break;
1689 case 16:
1690 EMIT_ASM ("clrlwi 4,4,16\n"
1691 "li 3, 0\n");
1692 break;
1693 case 32:
1694 EMIT_ASM ("li 3, 0");
1695 break;
1696 default:
1697 emit_error = 1;
1698 }
1699}
1700
1701/* TOP = !TOP
1702 i.e., TOP = (TOP == 0) ? 1 : 0; */
1703
1704static void
1705ppc_emit_log_not (void)
1706{
1707 EMIT_ASM ("or 4, 3, 4 \n"
1708 "cntlzw 4, 4 \n"
1709 "srwi 4, 4, 5 \n"
1710 "li 3, 0 \n");
1711}
1712
1713/* TOP = stack[--sp] & TOP */
1714
1715static void
1716ppc_emit_bit_and (void)
1717{
1718 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1719 "lwz " TMP_SECOND ", 4(30) \n"
1720 "and 4, 6, 4 \n"
1721 "and 3, 5, 3 \n");
1722}
1723
1724/* TOP = stack[--sp] | TOP */
1725
1726static void
1727ppc_emit_bit_or (void)
1728{
1729 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1730 "lwz " TMP_SECOND ", 4(30) \n"
1731 "or 4, 6, 4 \n"
1732 "or 3, 5, 3 \n");
1733}
1734
1735/* TOP = stack[--sp] ^ TOP */
1736
1737static void
1738ppc_emit_bit_xor (void)
1739{
1740 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1741 "lwz " TMP_SECOND ", 4(30) \n"
1742 "xor 4, 6, 4 \n"
1743 "xor 3, 5, 3 \n");
1744}
1745
1746/* TOP = ~TOP
1747 i.e., TOP = ~(TOP | TOP) */
1748
1749static void
1750ppc_emit_bit_not (void)
1751{
1752 EMIT_ASM ("nor 3, 3, 3 \n"
1753 "nor 4, 4, 4 \n");
1754}
1755
1756/* TOP = stack[--sp] == TOP */
1757
1758static void
1759ppc_emit_equal (void)
1760{
1761 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1762 "lwz " TMP_SECOND ", 4(30) \n"
1763 "xor 4, 6, 4 \n"
1764 "xor 3, 5, 3 \n"
1765 "or 4, 3, 4 \n"
1766 "cntlzw 4, 4 \n"
1767 "srwi 4, 4, 5 \n"
1768 "li 3, 0 \n");
1769}
1770
1771/* TOP = stack[--sp] < TOP
1772 (Signed comparison) */
1773
1774static void
1775ppc_emit_less_signed (void)
1776{
1777 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1778 "lwz " TMP_SECOND ", 4(30) \n"
1779 "cmplw 6, 6, 4 \n"
1780 "cmpw 7, 5, 3 \n"
1781 /* CR6 bit 0 = low less and high equal */
1782 "crand 6*4+0, 6*4+0, 7*4+2\n"
1783 /* CR7 bit 0 = (low less and high equal) or high less */
1784 "cror 7*4+0, 7*4+0, 6*4+0\n"
1785 "mfcr 4 \n"
1786 "rlwinm 4, 4, 29, 31, 31 \n"
1787 "li 3, 0 \n");
1788}
1789
1790/* TOP = stack[--sp] < TOP
1791 (Unsigned comparison) */
1792
1793static void
1794ppc_emit_less_unsigned (void)
1795{
1796 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1797 "lwz " TMP_SECOND ", 4(30) \n"
1798 "cmplw 6, 6, 4 \n"
1799 "cmplw 7, 5, 3 \n"
1800 /* CR6 bit 0 = low less and high equal */
1801 "crand 6*4+0, 6*4+0, 7*4+2\n"
1802 /* CR7 bit 0 = (low less and high equal) or high less */
1803 "cror 7*4+0, 7*4+0, 6*4+0\n"
1804 "mfcr 4 \n"
1805 "rlwinm 4, 4, 29, 31, 31 \n"
1806 "li 3, 0 \n");
1807}
1808
1809/* Access the memory address in TOP in size of SIZE.
1810 Zero-extend the read value. */
1811
1812static void
1813ppc_emit_ref (int size)
1814{
1815 switch (size)
1816 {
1817 case 1:
1818 EMIT_ASM ("lbz 4, 0(4)\n"
1819 "li 3, 0");
1820 break;
1821 case 2:
1822 EMIT_ASM ("lhz 4, 0(4)\n"
1823 "li 3, 0");
1824 break;
1825 case 4:
1826 EMIT_ASM ("lwz 4, 0(4)\n"
1827 "li 3, 0");
1828 break;
1829 case 8:
1830 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1831 EMIT_ASM ("lwz 3, 4(4)\n"
1832 "lwz 4, 0(4)");
1833 else
1834 EMIT_ASM ("lwz 3, 0(4)\n"
1835 "lwz 4, 4(4)");
1836 break;
1837 }
1838}
1839
1840/* TOP = NUM */
1841
1842static void
1843ppc_emit_const (LONGEST num)
1844{
1845 uint32_t buf[10];
1846 uint32_t *p = buf;
1847
1848 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
1849 p += gen_limm (p, 4, num & 0xffffffff, 0);
1850
1851 emit_insns (buf, p - buf);
1852 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1853}
1854
1855/* Set TOP to the value of register REG by calling get_raw_reg function
1856 with two argument, collected buffer and register number. */
1857
1858static void
1859ppc_emit_reg (int reg)
1860{
1861 uint32_t buf[13];
1862 uint32_t *p = buf;
1863
1864 /* fctx->regs is passed in r3 and then saved in -16(31). */
1865 p += GEN_LWZ (p, 3, 31, -16);
1866 p += GEN_LI (p, 4, reg); /* li r4, reg */
1867 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
1868
1869 emit_insns (buf, p - buf);
1870 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1871
1872 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1873 {
1874 EMIT_ASM ("mr 5, 4\n"
1875 "mr 4, 3\n"
1876 "mr 3, 5\n");
1877 }
1878}
1879
1880/* TOP = stack[--sp] */
1881
1882static void
1883ppc_emit_pop (void)
1884{
1885 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
1886 "lwz " TOP_SECOND ", 4(30) \n");
1887}
1888
1889/* stack[sp++] = TOP
1890
1891 Because we may use up bytecode stack, expand 8 doublewords more
1892 if needed. */
1893
1894static void
1895ppc_emit_stack_flush (void)
1896{
1897 /* Make sure bytecode stack is big enough before push.
1898 Otherwise, expand 64-byte more. */
1899
1900 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
1901 " stw " TOP_SECOND ", 4(30)\n"
1902 " addi 5, 30, -(8 + 8) \n"
1903 " cmpw 7, 5, 1 \n"
1904 " bgt 7, 1f \n"
1905 " stwu 31, -64(1) \n"
1906 "1:addi 30, 30, -8 \n");
1907}
1908
1909/* Swap TOP and stack[sp-1] */
1910
1911static void
1912ppc_emit_swap (void)
1913{
1914 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
1915 "lwz " TMP_SECOND ", 12(30) \n"
1916 "stw " TOP_FIRST ", 8(30) \n"
1917 "stw " TOP_SECOND ", 12(30) \n"
1918 "mr 3, 5 \n"
1919 "mr 4, 6 \n");
1920}
1921
1922/* Discard N elements in the stack. Also used for ppc64. */
1923
1924static void
1925ppc_emit_stack_adjust (int n)
1926{
1927 uint32_t buf[6];
1928 uint32_t *p = buf;
1929
1930 n = n << 3;
1931 if ((n >> 15) != 0)
1932 {
1933 emit_error = 1;
1934 return;
1935 }
1936
1937 p += GEN_ADDI (p, 30, 30, n);
1938
1939 emit_insns (buf, p - buf);
1940 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1941}
1942
1943/* Call function FN. */
1944
1945static void
1946ppc_emit_call (CORE_ADDR fn)
1947{
1948 uint32_t buf[11];
1949 uint32_t *p = buf;
1950
1951 p += gen_call (p, fn, 0, 0);
1952
1953 emit_insns (buf, p - buf);
1954 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1955}
1956
1957/* FN's prototype is `LONGEST(*fn)(int)'.
1958 TOP = fn (arg1)
1959 */
1960
1961static void
1962ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
1963{
1964 uint32_t buf[15];
1965 uint32_t *p = buf;
1966
1967 /* Setup argument. arg1 is a 16-bit value. */
1968 p += gen_limm (p, 3, (uint32_t) arg1, 0);
1969 p += gen_call (p, fn, 0, 0);
1970
1971 emit_insns (buf, p - buf);
1972 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
1973
1974 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1975 {
1976 EMIT_ASM ("mr 5, 4\n"
1977 "mr 4, 3\n"
1978 "mr 3, 5\n");
1979 }
1980}
1981
1982/* FN's prototype is `void(*fn)(int,LONGEST)'.
1983 fn (arg1, TOP)
1984
1985 TOP should be preserved/restored before/after the call. */
1986
1987static void
1988ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
1989{
1990 uint32_t buf[21];
1991 uint32_t *p = buf;
1992
1993 /* Save TOP. 0(30) is next-empty. */
1994 p += GEN_STW (p, 3, 30, 0);
1995 p += GEN_STW (p, 4, 30, 4);
1996
1997 /* Setup argument. arg1 is a 16-bit value. */
1998 if (__BYTE_ORDER == __LITTLE_ENDIAN)
1999 {
2000 p += GEN_MR (p, 5, 4);
2001 p += GEN_MR (p, 6, 3);
2002 }
2003 else
2004 {
2005 p += GEN_MR (p, 5, 3);
2006 p += GEN_MR (p, 6, 4);
2007 }
2008 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2009 p += gen_call (p, fn, 0, 0);
2010
2011 /* Restore TOP */
2012 p += GEN_LWZ (p, 3, 30, 0);
2013 p += GEN_LWZ (p, 4, 30, 4);
2014
2015 emit_insns (buf, p - buf);
2016 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2017}
2018
2019/* Note in the following goto ops:
2020
2021 When emitting goto, the target address is later relocated by
2022 write_goto_address. OFFSET_P is the offset of the branch instruction
2023 in the code sequence, and SIZE_P is how to relocate the instruction,
2024 recognized by ppc_write_goto_address. In current implementation,
2025 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2026 */
2027
2028/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2029
2030static void
2031ppc_emit_if_goto (int *offset_p, int *size_p)
2032{
2033 EMIT_ASM ("or. 3, 3, 4 \n"
2034 "lwzu " TOP_FIRST ", 8(30) \n"
2035 "lwz " TOP_SECOND ", 4(30) \n"
2036 "1:bne 0, 1b \n");
2037
2038 if (offset_p)
2039 *offset_p = 12;
2040 if (size_p)
2041 *size_p = 14;
2042}
2043
2044/* Unconditional goto. Also used for ppc64. */
2045
2046static void
2047ppc_emit_goto (int *offset_p, int *size_p)
2048{
2049 EMIT_ASM ("1:b 1b");
2050
2051 if (offset_p)
2052 *offset_p = 0;
2053 if (size_p)
2054 *size_p = 24;
2055}
2056
2057/* Goto if stack[--sp] == TOP */
2058
2059static void
2060ppc_emit_eq_goto (int *offset_p, int *size_p)
2061{
2062 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2063 "lwz " TMP_SECOND ", 4(30) \n"
2064 "xor 4, 6, 4 \n"
2065 "xor 3, 5, 3 \n"
2066 "or. 3, 3, 4 \n"
2067 "lwzu " TOP_FIRST ", 8(30) \n"
2068 "lwz " TOP_SECOND ", 4(30) \n"
2069 "1:beq 0, 1b \n");
2070
2071 if (offset_p)
2072 *offset_p = 28;
2073 if (size_p)
2074 *size_p = 14;
2075}
2076
2077/* Goto if stack[--sp] != TOP */
2078
2079static void
2080ppc_emit_ne_goto (int *offset_p, int *size_p)
2081{
2082 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2083 "lwz " TMP_SECOND ", 4(30) \n"
2084 "xor 4, 6, 4 \n"
2085 "xor 3, 5, 3 \n"
2086 "or. 3, 3, 4 \n"
2087 "lwzu " TOP_FIRST ", 8(30) \n"
2088 "lwz " TOP_SECOND ", 4(30) \n"
2089 "1:bne 0, 1b \n");
2090
2091 if (offset_p)
2092 *offset_p = 28;
2093 if (size_p)
2094 *size_p = 14;
2095}
2096
2097/* Goto if stack[--sp] < TOP */
2098
2099static void
2100ppc_emit_lt_goto (int *offset_p, int *size_p)
2101{
2102 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2103 "lwz " TMP_SECOND ", 4(30) \n"
2104 "cmplw 6, 6, 4 \n"
2105 "cmpw 7, 5, 3 \n"
2106 /* CR6 bit 0 = low less and high equal */
2107 "crand 6*4+0, 6*4+0, 7*4+2\n"
2108 /* CR7 bit 0 = (low less and high equal) or high less */
2109 "cror 7*4+0, 7*4+0, 6*4+0\n"
2110 "lwzu " TOP_FIRST ", 8(30) \n"
2111 "lwz " TOP_SECOND ", 4(30)\n"
2112 "1:blt 7, 1b \n");
2113
2114 if (offset_p)
2115 *offset_p = 32;
2116 if (size_p)
2117 *size_p = 14;
2118}
2119
2120/* Goto if stack[--sp] <= TOP */
2121
2122static void
2123ppc_emit_le_goto (int *offset_p, int *size_p)
2124{
2125 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2126 "lwz " TMP_SECOND ", 4(30) \n"
2127 "cmplw 6, 6, 4 \n"
2128 "cmpw 7, 5, 3 \n"
2129 /* CR6 bit 0 = low less/equal and high equal */
2130 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2131 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2132 "cror 7*4+0, 7*4+0, 6*4+0\n"
2133 "lwzu " TOP_FIRST ", 8(30) \n"
2134 "lwz " TOP_SECOND ", 4(30)\n"
2135 "1:blt 7, 1b \n");
2136
2137 if (offset_p)
2138 *offset_p = 32;
2139 if (size_p)
2140 *size_p = 14;
2141}
2142
2143/* Goto if stack[--sp] > TOP */
2144
2145static void
2146ppc_emit_gt_goto (int *offset_p, int *size_p)
2147{
2148 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2149 "lwz " TMP_SECOND ", 4(30) \n"
2150 "cmplw 6, 6, 4 \n"
2151 "cmpw 7, 5, 3 \n"
2152 /* CR6 bit 0 = low greater and high equal */
2153 "crand 6*4+0, 6*4+1, 7*4+2\n"
2154 /* CR7 bit 0 = (low greater and high equal) or high greater */
2155 "cror 7*4+0, 7*4+1, 6*4+0\n"
2156 "lwzu " TOP_FIRST ", 8(30) \n"
2157 "lwz " TOP_SECOND ", 4(30)\n"
2158 "1:blt 7, 1b \n");
2159
2160 if (offset_p)
2161 *offset_p = 32;
2162 if (size_p)
2163 *size_p = 14;
2164}
2165
2166/* Goto if stack[--sp] >= TOP */
2167
2168static void
2169ppc_emit_ge_goto (int *offset_p, int *size_p)
2170{
2171 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2172 "lwz " TMP_SECOND ", 4(30) \n"
2173 "cmplw 6, 6, 4 \n"
2174 "cmpw 7, 5, 3 \n"
2175 /* CR6 bit 0 = low ge and high equal */
2176 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2177 /* CR7 bit 0 = (low ge and high equal) or high greater */
2178 "cror 7*4+0, 7*4+1, 6*4+0\n"
2179 "lwzu " TOP_FIRST ", 8(30)\n"
2180 "lwz " TOP_SECOND ", 4(30)\n"
2181 "1:blt 7, 1b \n");
2182
2183 if (offset_p)
2184 *offset_p = 32;
2185 if (size_p)
2186 *size_p = 14;
2187}
2188
2189/* Relocate previous emitted branch instruction. FROM is the address
2190 of the branch instruction, TO is the goto target address, and SIZE
2191 if the value we set by *SIZE_P before. Currently, it is either
2192 24 or 14 of branch and conditional-branch instruction.
2193 Also used for ppc64. */
2194
2195static void
2196ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2197{
2198 long rel = to - from;
2199 uint32_t insn;
2200 int opcd;
2201
2202 read_inferior_memory (from, (unsigned char *) &insn, 4);
2203 opcd = (insn >> 26) & 0x3f;
2204
2205 switch (size)
2206 {
2207 case 14:
2208 if (opcd != 16
2209 || (rel >= (1 << 15) || rel < -(1 << 15)))
2210 emit_error = 1;
2211 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2212 break;
2213 case 24:
2214 if (opcd != 18
2215 || (rel >= (1 << 25) || rel < -(1 << 25)))
2216 emit_error = 1;
2217 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2218 break;
2219 default:
2220 emit_error = 1;
2221 }
2222
2223 if (!emit_error)
2224 write_inferior_memory (from, (unsigned char *) &insn, 4);
2225}
2226
2227/* Table of emit ops for 32-bit. */
2228
2229static struct emit_ops ppc_emit_ops_impl =
2230{
2231 ppc_emit_prologue,
2232 ppc_emit_epilogue,
2233 ppc_emit_add,
2234 ppc_emit_sub,
2235 ppc_emit_mul,
2236 ppc_emit_lsh,
2237 ppc_emit_rsh_signed,
2238 ppc_emit_rsh_unsigned,
2239 ppc_emit_ext,
2240 ppc_emit_log_not,
2241 ppc_emit_bit_and,
2242 ppc_emit_bit_or,
2243 ppc_emit_bit_xor,
2244 ppc_emit_bit_not,
2245 ppc_emit_equal,
2246 ppc_emit_less_signed,
2247 ppc_emit_less_unsigned,
2248 ppc_emit_ref,
2249 ppc_emit_if_goto,
2250 ppc_emit_goto,
2251 ppc_write_goto_address,
2252 ppc_emit_const,
2253 ppc_emit_call,
2254 ppc_emit_reg,
2255 ppc_emit_pop,
2256 ppc_emit_stack_flush,
2257 ppc_emit_zero_ext,
2258 ppc_emit_swap,
2259 ppc_emit_stack_adjust,
2260 ppc_emit_int_call_1,
2261 ppc_emit_void_call_2,
2262 ppc_emit_eq_goto,
2263 ppc_emit_ne_goto,
2264 ppc_emit_lt_goto,
2265 ppc_emit_le_goto,
2266 ppc_emit_gt_goto,
2267 ppc_emit_ge_goto
2268};
2269
2270#ifdef __powerpc64__
2271
2272/*
2273
2274 Bytecode execution stack frame - 64-bit
2275
2276 | LR save area (SP + 16)
2277 | CR save area (SP + 8)
2278 SP' -> +- Back chain (SP + 0)
2279 | Save r31 for access saved arguments
2280 | Save r30 for bytecode stack pointer
2281 | Save r4 for incoming argument *value
2282 | Save r3 for incoming argument regs
2283 r30 -> +- Bytecode execution stack
2284 |
2285 | 64-byte (8 doublewords) at initial.
2286 | Expand stack as needed.
2287 |
2288 +-
2289 | Some padding for minimum stack frame.
2290 | 112 for ELFv1.
2291 SP +- Back-chain (SP')
2292
2293 initial frame size
2294 = 112 + (4 * 8) + 64
2295 = 208
2296
2297 r30 is the stack-pointer for bytecode machine.
2298 It should point to next-empty, so we can use LDU for pop.
2299 r3 is used for cache of TOP value.
2300 It was the first argument, pointer to regs.
2301 r4 is the second argument, pointer to the result.
2302 We should set *result = TOP after leaving this function.
2303
2304 Note:
2305 * To restore stack at epilogue
2306 => sp = r31
2307 * To check stack is big enough for bytecode execution.
2308 => r30 - 8 > SP + 112
2309 * To return execution result.
2310 => 0(r4) = TOP
2311
2312 */
2313
2314/* Emit prologue in inferior memory. See above comments. */
2315
2316static void
2317ppc64v1_emit_prologue (void)
2318{
2319 /* On ELFv1, function pointers really point to function descriptor,
2320 so emit one here. We don't care about contents of words 1 and 2,
2321 so let them just overlap out code. */
2322 uint64_t opd = current_insn_ptr + 8;
2323 uint32_t buf[2];
2324
2325 /* Mind the strict aliasing rules. */
2326 memcpy (buf, &opd, sizeof buf);
2327 emit_insns(buf, 2);
2328 EMIT_ASM (/* Save return address. */
2329 "mflr 0 \n"
2330 "std 0, 16(1) \n"
2331 /* Save r30 and incoming arguments. */
2332 "std 31, -8(1) \n"
2333 "std 30, -16(1) \n"
2334 "std 4, -24(1) \n"
2335 "std 3, -32(1) \n"
2336 /* Point r31 to current r1 for access arguments. */
2337 "mr 31, 1 \n"
2338 /* Adjust SP. 208 is the initial frame size. */
2339 "stdu 1, -208(1) \n"
2340 /* Set r30 to pointing stack-top. */
2341 "addi 30, 1, 168 \n"
2342 /* Initial r3/TOP to 0. */
2343 "li 3, 0 \n");
2344}
2345
2346/* Emit prologue in inferior memory. See above comments. */
2347
2348static void
2349ppc64v2_emit_prologue (void)
2350{
2351 EMIT_ASM (/* Save return address. */
2352 "mflr 0 \n"
2353 "std 0, 16(1) \n"
2354 /* Save r30 and incoming arguments. */
2355 "std 31, -8(1) \n"
2356 "std 30, -16(1) \n"
2357 "std 4, -24(1) \n"
2358 "std 3, -32(1) \n"
2359 /* Point r31 to current r1 for access arguments. */
2360 "mr 31, 1 \n"
2361 /* Adjust SP. 208 is the initial frame size. */
2362 "stdu 1, -208(1) \n"
2363 /* Set r30 to pointing stack-top. */
2364 "addi 30, 1, 168 \n"
2365 /* Initial r3/TOP to 0. */
2366 "li 3, 0 \n");
2367}
2368
2369/* Emit epilogue in inferior memory. See above comments. */
2370
2371static void
2372ppc64_emit_epilogue (void)
2373{
2374 EMIT_ASM (/* Restore SP. */
2375 "ld 1, 0(1) \n"
2376 /* *result = TOP */
2377 "ld 4, -24(1) \n"
2378 "std 3, 0(4) \n"
2379 /* Restore registers. */
2380 "ld 31, -8(1) \n"
2381 "ld 30, -16(1) \n"
2382 /* Restore LR. */
2383 "ld 0, 16(1) \n"
2384 /* Return 0 for no-error. */
2385 "li 3, 0 \n"
2386 "mtlr 0 \n"
2387 "blr \n");
2388}
2389
2390/* TOP = stack[--sp] + TOP */
2391
2392static void
2393ppc64_emit_add (void)
2394{
2395 EMIT_ASM ("ldu 4, 8(30) \n"
2396 "add 3, 4, 3 \n");
2397}
2398
2399/* TOP = stack[--sp] - TOP */
2400
2401static void
2402ppc64_emit_sub (void)
2403{
2404 EMIT_ASM ("ldu 4, 8(30) \n"
2405 "sub 3, 4, 3 \n");
2406}
2407
2408/* TOP = stack[--sp] * TOP */
2409
2410static void
2411ppc64_emit_mul (void)
2412{
2413 EMIT_ASM ("ldu 4, 8(30) \n"
2414 "mulld 3, 4, 3 \n");
2415}
2416
2417/* TOP = stack[--sp] << TOP */
2418
2419static void
2420ppc64_emit_lsh (void)
2421{
2422 EMIT_ASM ("ldu 4, 8(30) \n"
2423 "sld 3, 4, 3 \n");
2424}
2425
2426/* Top = stack[--sp] >> TOP
2427 (Arithmetic shift right) */
2428
2429static void
2430ppc64_emit_rsh_signed (void)
2431{
2432 EMIT_ASM ("ldu 4, 8(30) \n"
2433 "srad 3, 4, 3 \n");
2434}
2435
2436/* Top = stack[--sp] >> TOP
2437 (Logical shift right) */
2438
2439static void
2440ppc64_emit_rsh_unsigned (void)
2441{
2442 EMIT_ASM ("ldu 4, 8(30) \n"
2443 "srd 3, 4, 3 \n");
2444}
2445
2446/* Emit code for signed-extension specified by ARG. */
2447
2448static void
2449ppc64_emit_ext (int arg)
2450{
2451 switch (arg)
2452 {
2453 case 8:
2454 EMIT_ASM ("extsb 3, 3");
2455 break;
2456 case 16:
2457 EMIT_ASM ("extsh 3, 3");
2458 break;
2459 case 32:
2460 EMIT_ASM ("extsw 3, 3");
2461 break;
2462 default:
2463 emit_error = 1;
2464 }
2465}
2466
2467/* Emit code for zero-extension specified by ARG. */
2468
2469static void
2470ppc64_emit_zero_ext (int arg)
2471{
2472 switch (arg)
2473 {
2474 case 8:
2475 EMIT_ASM ("rldicl 3,3,0,56");
2476 break;
2477 case 16:
2478 EMIT_ASM ("rldicl 3,3,0,48");
2479 break;
2480 case 32:
2481 EMIT_ASM ("rldicl 3,3,0,32");
2482 break;
2483 default:
2484 emit_error = 1;
2485 }
2486}
2487
2488/* TOP = !TOP
2489 i.e., TOP = (TOP == 0) ? 1 : 0; */
2490
2491static void
2492ppc64_emit_log_not (void)
2493{
2494 EMIT_ASM ("cntlzd 3, 3 \n"
2495 "srdi 3, 3, 6 \n");
2496}
2497
2498/* TOP = stack[--sp] & TOP */
2499
2500static void
2501ppc64_emit_bit_and (void)
2502{
2503 EMIT_ASM ("ldu 4, 8(30) \n"
2504 "and 3, 4, 3 \n");
2505}
2506
2507/* TOP = stack[--sp] | TOP */
2508
2509static void
2510ppc64_emit_bit_or (void)
2511{
2512 EMIT_ASM ("ldu 4, 8(30) \n"
2513 "or 3, 4, 3 \n");
2514}
2515
2516/* TOP = stack[--sp] ^ TOP */
2517
2518static void
2519ppc64_emit_bit_xor (void)
2520{
2521 EMIT_ASM ("ldu 4, 8(30) \n"
2522 "xor 3, 4, 3 \n");
2523}
2524
2525/* TOP = ~TOP
2526 i.e., TOP = ~(TOP | TOP) */
2527
2528static void
2529ppc64_emit_bit_not (void)
2530{
2531 EMIT_ASM ("nor 3, 3, 3 \n");
2532}
2533
2534/* TOP = stack[--sp] == TOP */
2535
2536static void
2537ppc64_emit_equal (void)
2538{
2539 EMIT_ASM ("ldu 4, 8(30) \n"
2540 "xor 3, 3, 4 \n"
2541 "cntlzd 3, 3 \n"
2542 "srdi 3, 3, 6 \n");
2543}
2544
2545/* TOP = stack[--sp] < TOP
2546 (Signed comparison) */
2547
2548static void
2549ppc64_emit_less_signed (void)
2550{
2551 EMIT_ASM ("ldu 4, 8(30) \n"
2552 "cmpd 7, 4, 3 \n"
2553 "mfcr 3 \n"
2554 "rlwinm 3, 3, 29, 31, 31 \n");
2555}
2556
2557/* TOP = stack[--sp] < TOP
2558 (Unsigned comparison) */
2559
2560static void
2561ppc64_emit_less_unsigned (void)
2562{
2563 EMIT_ASM ("ldu 4, 8(30) \n"
2564 "cmpld 7, 4, 3 \n"
2565 "mfcr 3 \n"
2566 "rlwinm 3, 3, 29, 31, 31 \n");
2567}
2568
2569/* Access the memory address in TOP in size of SIZE.
2570 Zero-extend the read value. */
2571
2572static void
2573ppc64_emit_ref (int size)
2574{
2575 switch (size)
2576 {
2577 case 1:
2578 EMIT_ASM ("lbz 3, 0(3)");
2579 break;
2580 case 2:
2581 EMIT_ASM ("lhz 3, 0(3)");
2582 break;
2583 case 4:
2584 EMIT_ASM ("lwz 3, 0(3)");
2585 break;
2586 case 8:
2587 EMIT_ASM ("ld 3, 0(3)");
2588 break;
2589 }
2590}
2591
2592/* TOP = NUM */
2593
2594static void
2595ppc64_emit_const (LONGEST num)
2596{
2597 uint32_t buf[5];
2598 uint32_t *p = buf;
2599
2600 p += gen_limm (p, 3, num, 1);
2601
2602 emit_insns (buf, p - buf);
2603 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2604}
2605
2606/* Set TOP to the value of register REG by calling get_raw_reg function
2607 with two argument, collected buffer and register number. */
2608
2609static void
2610ppc64v1_emit_reg (int reg)
2611{
2612 uint32_t buf[15];
2613 uint32_t *p = buf;
2614
2615 /* fctx->regs is passed in r3 and then saved in 176(1). */
2616 p += GEN_LD (p, 3, 31, -32);
2617 p += GEN_LI (p, 4, reg);
2618 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2619 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2620 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2621
2622 emit_insns (buf, p - buf);
2623 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2624}
2625
2626/* Likewise, for ELFv2. */
2627
2628static void
2629ppc64v2_emit_reg (int reg)
2630{
2631 uint32_t buf[12];
2632 uint32_t *p = buf;
2633
2634 /* fctx->regs is passed in r3 and then saved in 176(1). */
2635 p += GEN_LD (p, 3, 31, -32);
2636 p += GEN_LI (p, 4, reg);
2637 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2638 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2639 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2640
2641 emit_insns (buf, p - buf);
2642 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2643}
2644
2645/* TOP = stack[--sp] */
2646
2647static void
2648ppc64_emit_pop (void)
2649{
2650 EMIT_ASM ("ldu 3, 8(30)");
2651}
2652
2653/* stack[sp++] = TOP
2654
2655 Because we may use up bytecode stack, expand 8 doublewords more
2656 if needed. */
2657
2658static void
2659ppc64_emit_stack_flush (void)
2660{
2661 /* Make sure bytecode stack is big enough before push.
2662 Otherwise, expand 64-byte more. */
2663
2664 EMIT_ASM (" std 3, 0(30) \n"
2665 " addi 4, 30, -(112 + 8) \n"
2666 " cmpd 7, 4, 1 \n"
2667 " bgt 7, 1f \n"
2668 " stdu 31, -64(1) \n"
2669 "1:addi 30, 30, -8 \n");
2670}
2671
2672/* Swap TOP and stack[sp-1] */
2673
2674static void
2675ppc64_emit_swap (void)
2676{
2677 EMIT_ASM ("ld 4, 8(30) \n"
2678 "std 3, 8(30) \n"
2679 "mr 3, 4 \n");
2680}
2681
2682/* Call function FN - ELFv1. */
2683
2684static void
2685ppc64v1_emit_call (CORE_ADDR fn)
2686{
2687 uint32_t buf[13];
2688 uint32_t *p = buf;
2689
2690 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2691 p += gen_call (p, fn, 1, 1);
2692 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2693
2694 emit_insns (buf, p - buf);
2695 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2696}
2697
2698/* Call function FN - ELFv2. */
2699
2700static void
2701ppc64v2_emit_call (CORE_ADDR fn)
2702{
2703 uint32_t buf[10];
2704 uint32_t *p = buf;
2705
2706 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2707 p += gen_call (p, fn, 1, 0);
2708 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2709
2710 emit_insns (buf, p - buf);
2711 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2712}
2713
2714/* FN's prototype is `LONGEST(*fn)(int)'.
2715 TOP = fn (arg1)
2716 */
2717
2718static void
2719ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
2720{
2721 uint32_t buf[13];
2722 uint32_t *p = buf;
2723
2724 /* Setup argument. arg1 is a 16-bit value. */
2725 p += gen_limm (p, 3, arg1, 1);
2726 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2727 p += gen_call (p, fn, 1, 1);
2728 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2729
2730 emit_insns (buf, p - buf);
2731 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2732}
2733
2734/* Likewise for ELFv2. */
2735
2736static void
2737ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
2738{
2739 uint32_t buf[10];
2740 uint32_t *p = buf;
2741
2742 /* Setup argument. arg1 is a 16-bit value. */
2743 p += gen_limm (p, 3, arg1, 1);
2744 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2745 p += gen_call (p, fn, 1, 0);
2746 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2747
2748 emit_insns (buf, p - buf);
2749 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2750}
2751
2752/* FN's prototype is `void(*fn)(int,LONGEST)'.
2753 fn (arg1, TOP)
2754
2755 TOP should be preserved/restored before/after the call. */
2756
2757static void
2758ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
2759{
2760 uint32_t buf[17];
2761 uint32_t *p = buf;
2762
2763 /* Save TOP. 0(30) is next-empty. */
2764 p += GEN_STD (p, 3, 30, 0);
2765
2766 /* Setup argument. arg1 is a 16-bit value. */
2767 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2768 p += gen_limm (p, 3, arg1, 1);
2769 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2770 p += gen_call (p, fn, 1, 1);
2771 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2772
2773 /* Restore TOP */
2774 p += GEN_LD (p, 3, 30, 0);
2775
2776 emit_insns (buf, p - buf);
2777 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2778}
2779
2780/* Likewise for ELFv2. */
2781
2782static void
2783ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
2784{
2785 uint32_t buf[14];
2786 uint32_t *p = buf;
2787
2788 /* Save TOP. 0(30) is next-empty. */
2789 p += GEN_STD (p, 3, 30, 0);
2790
2791 /* Setup argument. arg1 is a 16-bit value. */
2792 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
2793 p += gen_limm (p, 3, arg1, 1);
2794 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2795 p += gen_call (p, fn, 1, 0);
2796 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2797
2798 /* Restore TOP */
2799 p += GEN_LD (p, 3, 30, 0);
2800
2801 emit_insns (buf, p - buf);
2802 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2803}
2804
2805/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2806
2807static void
2808ppc64_emit_if_goto (int *offset_p, int *size_p)
2809{
2810 EMIT_ASM ("cmpdi 7, 3, 0 \n"
2811 "ldu 3, 8(30) \n"
2812 "1:bne 7, 1b \n");
2813
2814 if (offset_p)
2815 *offset_p = 8;
2816 if (size_p)
2817 *size_p = 14;
2818}
2819
2820/* Goto if stack[--sp] == TOP */
2821
2822static void
2823ppc64_emit_eq_goto (int *offset_p, int *size_p)
2824{
2825 EMIT_ASM ("ldu 4, 8(30) \n"
2826 "cmpd 7, 4, 3 \n"
2827 "ldu 3, 8(30) \n"
2828 "1:beq 7, 1b \n");
2829
2830 if (offset_p)
2831 *offset_p = 12;
2832 if (size_p)
2833 *size_p = 14;
2834}
2835
2836/* Goto if stack[--sp] != TOP */
2837
2838static void
2839ppc64_emit_ne_goto (int *offset_p, int *size_p)
2840{
2841 EMIT_ASM ("ldu 4, 8(30) \n"
2842 "cmpd 7, 4, 3 \n"
2843 "ldu 3, 8(30) \n"
2844 "1:bne 7, 1b \n");
2845
2846 if (offset_p)
2847 *offset_p = 12;
2848 if (size_p)
2849 *size_p = 14;
2850}
2851
2852/* Goto if stack[--sp] < TOP */
2853
2854static void
2855ppc64_emit_lt_goto (int *offset_p, int *size_p)
2856{
2857 EMIT_ASM ("ldu 4, 8(30) \n"
2858 "cmpd 7, 4, 3 \n"
2859 "ldu 3, 8(30) \n"
2860 "1:blt 7, 1b \n");
2861
2862 if (offset_p)
2863 *offset_p = 12;
2864 if (size_p)
2865 *size_p = 14;
2866}
2867
2868/* Goto if stack[--sp] <= TOP */
2869
2870static void
2871ppc64_emit_le_goto (int *offset_p, int *size_p)
2872{
2873 EMIT_ASM ("ldu 4, 8(30) \n"
2874 "cmpd 7, 4, 3 \n"
2875 "ldu 3, 8(30) \n"
2876 "1:ble 7, 1b \n");
2877
2878 if (offset_p)
2879 *offset_p = 12;
2880 if (size_p)
2881 *size_p = 14;
2882}
2883
2884/* Goto if stack[--sp] > TOP */
2885
2886static void
2887ppc64_emit_gt_goto (int *offset_p, int *size_p)
2888{
2889 EMIT_ASM ("ldu 4, 8(30) \n"
2890 "cmpd 7, 4, 3 \n"
2891 "ldu 3, 8(30) \n"
2892 "1:bgt 7, 1b \n");
2893
2894 if (offset_p)
2895 *offset_p = 12;
2896 if (size_p)
2897 *size_p = 14;
2898}
2899
2900/* Goto if stack[--sp] >= TOP */
2901
2902static void
2903ppc64_emit_ge_goto (int *offset_p, int *size_p)
2904{
2905 EMIT_ASM ("ldu 4, 8(30) \n"
2906 "cmpd 7, 4, 3 \n"
2907 "ldu 3, 8(30) \n"
2908 "1:bge 7, 1b \n");
2909
2910 if (offset_p)
2911 *offset_p = 12;
2912 if (size_p)
2913 *size_p = 14;
2914}
2915
2916/* Table of emit ops for 64-bit ELFv1. */
2917
2918static struct emit_ops ppc64v1_emit_ops_impl =
2919{
2920 ppc64v1_emit_prologue,
2921 ppc64_emit_epilogue,
2922 ppc64_emit_add,
2923 ppc64_emit_sub,
2924 ppc64_emit_mul,
2925 ppc64_emit_lsh,
2926 ppc64_emit_rsh_signed,
2927 ppc64_emit_rsh_unsigned,
2928 ppc64_emit_ext,
2929 ppc64_emit_log_not,
2930 ppc64_emit_bit_and,
2931 ppc64_emit_bit_or,
2932 ppc64_emit_bit_xor,
2933 ppc64_emit_bit_not,
2934 ppc64_emit_equal,
2935 ppc64_emit_less_signed,
2936 ppc64_emit_less_unsigned,
2937 ppc64_emit_ref,
2938 ppc64_emit_if_goto,
2939 ppc_emit_goto,
2940 ppc_write_goto_address,
2941 ppc64_emit_const,
2942 ppc64v1_emit_call,
2943 ppc64v1_emit_reg,
2944 ppc64_emit_pop,
2945 ppc64_emit_stack_flush,
2946 ppc64_emit_zero_ext,
2947 ppc64_emit_swap,
2948 ppc_emit_stack_adjust,
2949 ppc64v1_emit_int_call_1,
2950 ppc64v1_emit_void_call_2,
2951 ppc64_emit_eq_goto,
2952 ppc64_emit_ne_goto,
2953 ppc64_emit_lt_goto,
2954 ppc64_emit_le_goto,
2955 ppc64_emit_gt_goto,
2956 ppc64_emit_ge_goto
2957};
2958
2959/* Table of emit ops for 64-bit ELFv2. */
2960
2961static struct emit_ops ppc64v2_emit_ops_impl =
2962{
2963 ppc64v2_emit_prologue,
2964 ppc64_emit_epilogue,
2965 ppc64_emit_add,
2966 ppc64_emit_sub,
2967 ppc64_emit_mul,
2968 ppc64_emit_lsh,
2969 ppc64_emit_rsh_signed,
2970 ppc64_emit_rsh_unsigned,
2971 ppc64_emit_ext,
2972 ppc64_emit_log_not,
2973 ppc64_emit_bit_and,
2974 ppc64_emit_bit_or,
2975 ppc64_emit_bit_xor,
2976 ppc64_emit_bit_not,
2977 ppc64_emit_equal,
2978 ppc64_emit_less_signed,
2979 ppc64_emit_less_unsigned,
2980 ppc64_emit_ref,
2981 ppc64_emit_if_goto,
2982 ppc_emit_goto,
2983 ppc_write_goto_address,
2984 ppc64_emit_const,
2985 ppc64v2_emit_call,
2986 ppc64v2_emit_reg,
2987 ppc64_emit_pop,
2988 ppc64_emit_stack_flush,
2989 ppc64_emit_zero_ext,
2990 ppc64_emit_swap,
2991 ppc_emit_stack_adjust,
2992 ppc64v2_emit_int_call_1,
2993 ppc64v2_emit_void_call_2,
2994 ppc64_emit_eq_goto,
2995 ppc64_emit_ne_goto,
2996 ppc64_emit_lt_goto,
2997 ppc64_emit_le_goto,
2998 ppc64_emit_gt_goto,
2999 ppc64_emit_ge_goto
3000};
3001
3002#endif
3003
3004/* Implementation of linux_target_ops method "emit_ops". */
3005
3006static struct emit_ops *
3007ppc_emit_ops (void)
3008{
3009#ifdef __powerpc64__
3010 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3011
3012 if (register_size (regcache->tdesc, 0) == 8)
3013 {
3014 if (is_elfv2_inferior ())
3015 return &ppc64v2_emit_ops_impl;
3016 else
3017 return &ppc64v1_emit_ops_impl;
3018 }
3019#endif
3020 return &ppc_emit_ops_impl;
3021}
3022
a2174ba4
MK		 3023/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3024
3025static int
3026ppc_get_ipa_tdesc_idx (void)
3027{
3028 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3029 const struct target_desc *tdesc = regcache->tdesc;
3030
3031#ifdef __powerpc64__
3032 if (tdesc == tdesc_powerpc_64l)
3033 return PPC_TDESC_BASE;
3034 if (tdesc == tdesc_powerpc_altivec64l)
3035 return PPC_TDESC_ALTIVEC;
3036 if (tdesc == tdesc_powerpc_cell64l)
3037 return PPC_TDESC_CELL;
3038 if (tdesc == tdesc_powerpc_vsx64l)
3039 return PPC_TDESC_VSX;
3040 if (tdesc == tdesc_powerpc_isa205_64l)
3041 return PPC_TDESC_ISA205;
3042 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3043 return PPC_TDESC_ISA205_ALTIVEC;
3044 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3045 return PPC_TDESC_ISA205_VSX;
3046#endif
3047
3048 if (tdesc == tdesc_powerpc_32l)
3049 return PPC_TDESC_BASE;
3050 if (tdesc == tdesc_powerpc_altivec32l)
3051 return PPC_TDESC_ALTIVEC;
3052 if (tdesc == tdesc_powerpc_cell32l)
3053 return PPC_TDESC_CELL;
3054 if (tdesc == tdesc_powerpc_vsx32l)
3055 return PPC_TDESC_VSX;
3056 if (tdesc == tdesc_powerpc_isa205_32l)
3057 return PPC_TDESC_ISA205;
3058 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3059 return PPC_TDESC_ISA205_ALTIVEC;
3060 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3061 return PPC_TDESC_ISA205_VSX;
3062 if (tdesc == tdesc_powerpc_e500l)
3063 return PPC_TDESC_E500;
3064
3065 return 0;
3066}
3067
2ec06d2e 3068struct linux_target_ops the_low_target = {
6fe305f7 3069 ppc_arch_setup,
3aee8918 3070 ppc_regs_info,
2ec06d2e
DJ		 3071 ppc_cannot_fetch_register,
3072 ppc_cannot_store_register,
c14dfd32 3073 NULL, /* fetch_register */
0d62e5e8
DJ		 3074 ppc_get_pc,
3075 ppc_set_pc,
dd373349
AT		 3076 NULL, /* breakpoint_kind_from_pc */
3077 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3078 NULL,
3079 0,
3080 ppc_breakpoint_at,
657f9cde
WW		 3081 ppc_supports_z_point_type,
3082 ppc_insert_point,
3083 ppc_remove_point,
5b0a002e
UW		 3084 NULL,
3085 NULL,
3086 ppc_collect_ptrace_register,
3087 ppc_supply_ptrace_register,
7d00775e
AT		 3088 NULL, /* siginfo_fixup */
3089 NULL, /* new_process */
04ec7890 3090 NULL, /* delete_process */
7d00775e 3091 NULL, /* new_thread */
466eecee 3092 NULL, /* delete_thread */
7d00775e
AT		 3093 NULL, /* new_fork */
3094 NULL, /* prepare_to_resume */
3095 NULL, /* process_qsupported */
b04fd3be 3096 ppc_supports_tracepoints,
a2174ba4
MK		 3097 ppc_get_thread_area,
3098 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3099 ppc_emit_ops,
a2174ba4 3100 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3101 NULL, /* supports_range_stepping */
3102 NULL, /* breakpoint_kind_from_current_state */
3103 ppc_supports_hardware_single_step,
a2174ba4
MK		 3104 NULL, /* get_syscall_trapinfo */
3105 ppc_get_ipa_tdesc_idx,
2ec06d2e 3106};
3aee8918
PA		 3107
3108void
3109initialize_low_arch (void)
3110{
3111 /* Initialize the Linux target descriptions. */
3112
3113 init_registers_powerpc_32l ();
3114 init_registers_powerpc_altivec32l ();
3115 init_registers_powerpc_cell32l ();
3116 init_registers_powerpc_vsx32l ();
3117 init_registers_powerpc_isa205_32l ();
3118 init_registers_powerpc_isa205_altivec32l ();
3119 init_registers_powerpc_isa205_vsx32l ();
3120 init_registers_powerpc_e500l ();
a2174ba4 3121#if __powerpc64__
3aee8918
PA		 3122 init_registers_powerpc_64l ();
3123 init_registers_powerpc_altivec64l ();
3124 init_registers_powerpc_cell64l ();
3125 init_registers_powerpc_vsx64l ();
3126 init_registers_powerpc_isa205_64l ();
3127 init_registers_powerpc_isa205_altivec64l ();
3128 init_registers_powerpc_isa205_vsx64l ();
a2174ba4 3129#endif
3aee8918
PA		 3130
3131 initialize_regsets_info (&ppc_regsets_info);
3132}
GDB Binutils - Deliverables
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