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265f716b DJ |
1 | /* GNU/Linux S/390 specific low level interface, for the remote server |
2 | for GDB. | |
618f726f | 3 | Copyright (C) 2001-2016 Free Software Foundation, Inc. |
265f716b DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
265f716b DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
265f716b DJ |
19 | |
20 | /* This file is used for both 31-bit and 64-bit S/390 systems. */ | |
21 | ||
22 | #include "server.h" | |
23 | #include "linux-low.h" | |
c642a434 | 24 | #include "elf/common.h" |
265f716b DJ |
25 | |
26 | #include <asm/ptrace.h> | |
5826e159 | 27 | #include "nat/gdb_ptrace.h" |
c642a434 | 28 | #include <sys/uio.h> |
7803799a | 29 | #include <elf.h> |
abd9baf9 MK |
30 | #include <inttypes.h> |
31 | ||
32 | #include "linux-s390-tdesc.h" | |
265f716b | 33 | |
7803799a UW |
34 | #ifndef HWCAP_S390_HIGH_GPRS |
35 | #define HWCAP_S390_HIGH_GPRS 512 | |
36 | #endif | |
d05b4ac3 | 37 | |
6682d959 AA |
38 | #ifndef HWCAP_S390_TE |
39 | #define HWCAP_S390_TE 1024 | |
40 | #endif | |
41 | ||
bf2d68ab AA |
42 | #ifndef HWCAP_S390_VX |
43 | #define HWCAP_S390_VX 2048 | |
44 | #endif | |
45 | ||
c642a434 | 46 | #define s390_num_regs 52 |
265f716b | 47 | |
2ec06d2e | 48 | static int s390_regmap[] = { |
265f716b DJ |
49 | PT_PSWMASK, PT_PSWADDR, |
50 | ||
51 | PT_GPR0, PT_GPR1, PT_GPR2, PT_GPR3, | |
52 | PT_GPR4, PT_GPR5, PT_GPR6, PT_GPR7, | |
53 | PT_GPR8, PT_GPR9, PT_GPR10, PT_GPR11, | |
54 | PT_GPR12, PT_GPR13, PT_GPR14, PT_GPR15, | |
55 | ||
56 | PT_ACR0, PT_ACR1, PT_ACR2, PT_ACR3, | |
57 | PT_ACR4, PT_ACR5, PT_ACR6, PT_ACR7, | |
58 | PT_ACR8, PT_ACR9, PT_ACR10, PT_ACR11, | |
59 | PT_ACR12, PT_ACR13, PT_ACR14, PT_ACR15, | |
60 | ||
265f716b DJ |
61 | PT_FPC, |
62 | ||
d0f54f9d | 63 | #ifndef __s390x__ |
265f716b DJ |
64 | PT_FPR0_HI, PT_FPR1_HI, PT_FPR2_HI, PT_FPR3_HI, |
65 | PT_FPR4_HI, PT_FPR5_HI, PT_FPR6_HI, PT_FPR7_HI, | |
66 | PT_FPR8_HI, PT_FPR9_HI, PT_FPR10_HI, PT_FPR11_HI, | |
67 | PT_FPR12_HI, PT_FPR13_HI, PT_FPR14_HI, PT_FPR15_HI, | |
68 | #else | |
69 | PT_FPR0, PT_FPR1, PT_FPR2, PT_FPR3, | |
70 | PT_FPR4, PT_FPR5, PT_FPR6, PT_FPR7, | |
71 | PT_FPR8, PT_FPR9, PT_FPR10, PT_FPR11, | |
72 | PT_FPR12, PT_FPR13, PT_FPR14, PT_FPR15, | |
73 | #endif | |
c642a434 UW |
74 | |
75 | PT_ORIGGPR2, | |
265f716b DJ |
76 | }; |
77 | ||
c642a434 | 78 | #define s390_num_regs_3264 68 |
7803799a | 79 | |
ab503087 | 80 | #ifdef __s390x__ |
7803799a UW |
81 | static int s390_regmap_3264[] = { |
82 | PT_PSWMASK, PT_PSWADDR, | |
83 | ||
493e2a69 MS |
84 | PT_GPR0, PT_GPR0, PT_GPR1, PT_GPR1, |
85 | PT_GPR2, PT_GPR2, PT_GPR3, PT_GPR3, | |
86 | PT_GPR4, PT_GPR4, PT_GPR5, PT_GPR5, | |
87 | PT_GPR6, PT_GPR6, PT_GPR7, PT_GPR7, | |
88 | PT_GPR8, PT_GPR8, PT_GPR9, PT_GPR9, | |
89 | PT_GPR10, PT_GPR10, PT_GPR11, PT_GPR11, | |
90 | PT_GPR12, PT_GPR12, PT_GPR13, PT_GPR13, | |
91 | PT_GPR14, PT_GPR14, PT_GPR15, PT_GPR15, | |
7803799a UW |
92 | |
93 | PT_ACR0, PT_ACR1, PT_ACR2, PT_ACR3, | |
94 | PT_ACR4, PT_ACR5, PT_ACR6, PT_ACR7, | |
95 | PT_ACR8, PT_ACR9, PT_ACR10, PT_ACR11, | |
96 | PT_ACR12, PT_ACR13, PT_ACR14, PT_ACR15, | |
97 | ||
98 | PT_FPC, | |
99 | ||
100 | PT_FPR0, PT_FPR1, PT_FPR2, PT_FPR3, | |
101 | PT_FPR4, PT_FPR5, PT_FPR6, PT_FPR7, | |
102 | PT_FPR8, PT_FPR9, PT_FPR10, PT_FPR11, | |
103 | PT_FPR12, PT_FPR13, PT_FPR14, PT_FPR15, | |
c642a434 UW |
104 | |
105 | PT_ORIGGPR2, | |
7803799a | 106 | }; |
ab503087 MK |
107 | #else |
108 | static int s390_regmap_3264[] = { | |
109 | PT_PSWMASK, PT_PSWADDR, | |
110 | ||
111 | -1, PT_GPR0, -1, PT_GPR1, | |
112 | -1, PT_GPR2, -1, PT_GPR3, | |
113 | -1, PT_GPR4, -1, PT_GPR5, | |
114 | -1, PT_GPR6, -1, PT_GPR7, | |
115 | -1, PT_GPR8, -1, PT_GPR9, | |
116 | -1, PT_GPR10, -1, PT_GPR11, | |
117 | -1, PT_GPR12, -1, PT_GPR13, | |
118 | -1, PT_GPR14, -1, PT_GPR15, | |
119 | ||
120 | PT_ACR0, PT_ACR1, PT_ACR2, PT_ACR3, | |
121 | PT_ACR4, PT_ACR5, PT_ACR6, PT_ACR7, | |
122 | PT_ACR8, PT_ACR9, PT_ACR10, PT_ACR11, | |
123 | PT_ACR12, PT_ACR13, PT_ACR14, PT_ACR15, | |
124 | ||
125 | PT_FPC, | |
126 | ||
127 | PT_FPR0_HI, PT_FPR1_HI, PT_FPR2_HI, PT_FPR3_HI, | |
128 | PT_FPR4_HI, PT_FPR5_HI, PT_FPR6_HI, PT_FPR7_HI, | |
129 | PT_FPR8_HI, PT_FPR9_HI, PT_FPR10_HI, PT_FPR11_HI, | |
130 | PT_FPR12_HI, PT_FPR13_HI, PT_FPR14_HI, PT_FPR15_HI, | |
131 | ||
132 | PT_ORIGGPR2, | |
133 | }; | |
7803799a UW |
134 | #endif |
135 | ||
136 | ||
2ec06d2e DJ |
137 | static int |
138 | s390_cannot_fetch_register (int regno) | |
265f716b | 139 | { |
265f716b DJ |
140 | return 0; |
141 | } | |
142 | ||
2ec06d2e DJ |
143 | static int |
144 | s390_cannot_store_register (int regno) | |
265f716b | 145 | { |
265f716b DJ |
146 | return 0; |
147 | } | |
2ec06d2e | 148 | |
ee1a7ae4 | 149 | static void |
442ea881 | 150 | s390_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) |
ee1a7ae4 | 151 | { |
3aee8918 | 152 | int size = register_size (regcache->tdesc, regno); |
ab503087 MK |
153 | const struct regs_info *regs_info = (*the_low_target.regs_info) (); |
154 | struct usrregs_info *usr = regs_info->usrregs; | |
155 | int regaddr = usr->regmap[regno]; | |
156 | ||
ee1a7ae4 UW |
157 | if (size < sizeof (long)) |
158 | { | |
159 | memset (buf, 0, sizeof (long)); | |
160 | ||
3aee8918 PA |
161 | if ((regno ^ 1) < usr->num_regs |
162 | && usr->regmap[regno ^ 1] == regaddr) | |
7803799a | 163 | { |
18f5de3b JK |
164 | collect_register (regcache, regno & ~1, buf); |
165 | collect_register (regcache, (regno & ~1) + 1, | |
166 | buf + sizeof (long) - size); | |
7803799a | 167 | } |
d6db1fab UW |
168 | else if (regaddr == PT_PSWMASK) |
169 | { | |
170 | /* Convert 4-byte PSW mask to 8 bytes by clearing bit 12 and copying | |
171 | the basic addressing mode bit from the PSW address. */ | |
3aee8918 | 172 | char *addr = alloca (register_size (regcache->tdesc, regno ^ 1)); |
d6db1fab UW |
173 | collect_register (regcache, regno, buf); |
174 | collect_register (regcache, regno ^ 1, addr); | |
175 | buf[1] &= ~0x8; | |
176 | buf[size] |= (addr[0] & 0x80); | |
177 | } | |
178 | else if (regaddr == PT_PSWADDR) | |
179 | { | |
180 | /* Convert 4-byte PSW address to 8 bytes by clearing the addressing | |
181 | mode bit (which gets copied to the PSW mask instead). */ | |
182 | collect_register (regcache, regno, buf + sizeof (long) - size); | |
183 | buf[sizeof (long) - size] &= ~0x80; | |
184 | } | |
c642a434 UW |
185 | else if ((regaddr >= PT_GPR0 && regaddr <= PT_GPR15) |
186 | || regaddr == PT_ORIGGPR2) | |
442ea881 | 187 | collect_register (regcache, regno, buf + sizeof (long) - size); |
ee1a7ae4 | 188 | else |
442ea881 | 189 | collect_register (regcache, regno, buf); |
ee1a7ae4 | 190 | } |
ab503087 | 191 | else if (regaddr != -1) |
18f5de3b | 192 | collect_register (regcache, regno, buf); |
ee1a7ae4 UW |
193 | } |
194 | ||
195 | static void | |
493e2a69 MS |
196 | s390_supply_ptrace_register (struct regcache *regcache, |
197 | int regno, const char *buf) | |
ee1a7ae4 | 198 | { |
3aee8918 | 199 | int size = register_size (regcache->tdesc, regno); |
ab503087 MK |
200 | const struct regs_info *regs_info = (*the_low_target.regs_info) (); |
201 | struct usrregs_info *usr = regs_info->usrregs; | |
202 | int regaddr = usr->regmap[regno]; | |
203 | ||
ee1a7ae4 UW |
204 | if (size < sizeof (long)) |
205 | { | |
3aee8918 PA |
206 | if ((regno ^ 1) < usr->num_regs |
207 | && usr->regmap[regno ^ 1] == regaddr) | |
7803799a | 208 | { |
18f5de3b JK |
209 | supply_register (regcache, regno & ~1, buf); |
210 | supply_register (regcache, (regno & ~1) + 1, | |
211 | buf + sizeof (long) - size); | |
7803799a | 212 | } |
d6db1fab UW |
213 | else if (regaddr == PT_PSWMASK) |
214 | { | |
215 | /* Convert 8-byte PSW mask to 4 bytes by setting bit 12 and copying | |
216 | the basic addressing mode into the PSW address. */ | |
217 | char *mask = alloca (size); | |
3aee8918 | 218 | char *addr = alloca (register_size (regcache->tdesc, regno ^ 1)); |
d6db1fab UW |
219 | memcpy (mask, buf, size); |
220 | mask[1] |= 0x8; | |
221 | supply_register (regcache, regno, mask); | |
222 | ||
223 | collect_register (regcache, regno ^ 1, addr); | |
224 | addr[0] &= ~0x80; | |
225 | addr[0] |= (buf[size] & 0x80); | |
226 | supply_register (regcache, regno ^ 1, addr); | |
227 | } | |
228 | else if (regaddr == PT_PSWADDR) | |
229 | { | |
230 | /* Convert 8-byte PSW address to 4 bytes by truncating, but | |
231 | keeping the addressing mode bit (which was set from the mask). */ | |
232 | char *addr = alloca (size); | |
233 | char amode; | |
234 | collect_register (regcache, regno, addr); | |
235 | amode = addr[0] & 0x80; | |
236 | memcpy (addr, buf + sizeof (long) - size, size); | |
237 | addr[0] &= ~0x80; | |
238 | addr[0] |= amode; | |
239 | supply_register (regcache, regno, addr); | |
240 | } | |
c642a434 UW |
241 | else if ((regaddr >= PT_GPR0 && regaddr <= PT_GPR15) |
242 | || regaddr == PT_ORIGGPR2) | |
442ea881 | 243 | supply_register (regcache, regno, buf + sizeof (long) - size); |
ee1a7ae4 | 244 | else |
442ea881 | 245 | supply_register (regcache, regno, buf); |
ee1a7ae4 | 246 | } |
ab503087 | 247 | else if (regaddr != -1) |
442ea881 | 248 | supply_register (regcache, regno, buf); |
ee1a7ae4 UW |
249 | } |
250 | ||
b7149293 UW |
251 | /* Provide only a fill function for the general register set. ps_lgetregs |
252 | will use this for NPTL support. */ | |
253 | ||
3aee8918 PA |
254 | static void |
255 | s390_fill_gregset (struct regcache *regcache, void *buf) | |
b7149293 UW |
256 | { |
257 | int i; | |
3aee8918 PA |
258 | const struct regs_info *regs_info = (*the_low_target.regs_info) (); |
259 | struct usrregs_info *usr = regs_info->usrregs; | |
b7149293 | 260 | |
3aee8918 | 261 | for (i = 0; i < usr->num_regs; i++) |
7803799a | 262 | { |
3aee8918 PA |
263 | if (usr->regmap[i] < PT_PSWMASK |
264 | || usr->regmap[i] > PT_ACR15) | |
7803799a UW |
265 | continue; |
266 | ||
3aee8918 PA |
267 | s390_collect_ptrace_register (regcache, i, |
268 | (char *) buf + usr->regmap[i]); | |
7803799a | 269 | } |
b7149293 UW |
270 | } |
271 | ||
c642a434 UW |
272 | /* Fill and store functions for extended register sets. */ |
273 | ||
ab503087 MK |
274 | #ifndef __s390x__ |
275 | static void | |
276 | s390_fill_gprs_high (struct regcache *regcache, void *buf) | |
277 | { | |
278 | int r0h = find_regno (regcache->tdesc, "r0h"); | |
279 | int i; | |
280 | ||
281 | for (i = 0; i < 16; i++) | |
282 | collect_register (regcache, r0h + 2 * i, (char *) buf + 4 * i); | |
283 | } | |
284 | ||
285 | static void | |
286 | s390_store_gprs_high (struct regcache *regcache, const void *buf) | |
287 | { | |
288 | int r0h = find_regno (regcache->tdesc, "r0h"); | |
289 | int i; | |
290 | ||
291 | for (i = 0; i < 16; i++) | |
292 | supply_register (regcache, r0h + 2 * i, (const char *) buf + 4 * i); | |
293 | } | |
294 | #endif | |
295 | ||
c642a434 UW |
296 | static void |
297 | s390_store_last_break (struct regcache *regcache, const void *buf) | |
298 | { | |
3aee8918 PA |
299 | const char *p; |
300 | ||
301 | p = (const char *) buf + 8 - register_size (regcache->tdesc, 0); | |
302 | supply_register_by_name (regcache, "last_break", p); | |
c642a434 UW |
303 | } |
304 | ||
305 | static void | |
306 | s390_fill_system_call (struct regcache *regcache, void *buf) | |
307 | { | |
308 | collect_register_by_name (regcache, "system_call", buf); | |
309 | } | |
310 | ||
311 | static void | |
312 | s390_store_system_call (struct regcache *regcache, const void *buf) | |
313 | { | |
314 | supply_register_by_name (regcache, "system_call", buf); | |
315 | } | |
316 | ||
e5a9158d AA |
317 | static void |
318 | s390_store_tdb (struct regcache *regcache, const void *buf) | |
319 | { | |
320 | int tdb0 = find_regno (regcache->tdesc, "tdb0"); | |
321 | int tr0 = find_regno (regcache->tdesc, "tr0"); | |
322 | int i; | |
323 | ||
324 | for (i = 0; i < 4; i++) | |
325 | supply_register (regcache, tdb0 + i, (const char *) buf + 8 * i); | |
326 | ||
327 | for (i = 0; i < 16; i++) | |
328 | supply_register (regcache, tr0 + i, (const char *) buf + 8 * (16 + i)); | |
329 | } | |
330 | ||
bf2d68ab AA |
331 | static void |
332 | s390_fill_vxrs_low (struct regcache *regcache, void *buf) | |
333 | { | |
334 | int v0 = find_regno (regcache->tdesc, "v0l"); | |
335 | int i; | |
336 | ||
337 | for (i = 0; i < 16; i++) | |
338 | collect_register (regcache, v0 + i, (char *) buf + 8 * i); | |
339 | } | |
340 | ||
341 | static void | |
342 | s390_store_vxrs_low (struct regcache *regcache, const void *buf) | |
343 | { | |
344 | int v0 = find_regno (regcache->tdesc, "v0l"); | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < 16; i++) | |
348 | supply_register (regcache, v0 + i, (const char *) buf + 8 * i); | |
349 | } | |
350 | ||
351 | static void | |
352 | s390_fill_vxrs_high (struct regcache *regcache, void *buf) | |
353 | { | |
354 | int v16 = find_regno (regcache->tdesc, "v16"); | |
355 | int i; | |
356 | ||
357 | for (i = 0; i < 16; i++) | |
358 | collect_register (regcache, v16 + i, (char *) buf + 16 * i); | |
359 | } | |
360 | ||
361 | static void | |
362 | s390_store_vxrs_high (struct regcache *regcache, const void *buf) | |
363 | { | |
364 | int v16 = find_regno (regcache->tdesc, "v16"); | |
365 | int i; | |
366 | ||
367 | for (i = 0; i < 16; i++) | |
368 | supply_register (regcache, v16 + i, (const char *) buf + 16 * i); | |
369 | } | |
370 | ||
3aee8918 | 371 | static struct regset_info s390_regsets[] = { |
1570b33e | 372 | { 0, 0, 0, 0, GENERAL_REGS, s390_fill_gregset, NULL }, |
ab503087 MK |
373 | #ifndef __s390x__ |
374 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_S390_HIGH_GPRS, 0, | |
375 | EXTENDED_REGS, s390_fill_gprs_high, s390_store_gprs_high }, | |
376 | #endif | |
feea5f36 AA |
377 | /* Last break address is read-only; no fill function. */ |
378 | { PTRACE_GETREGSET, -1, NT_S390_LAST_BREAK, 0, EXTENDED_REGS, | |
379 | NULL, s390_store_last_break }, | |
c642a434 UW |
380 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_S390_SYSTEM_CALL, 0, |
381 | EXTENDED_REGS, s390_fill_system_call, s390_store_system_call }, | |
e5a9158d AA |
382 | /* TDB is read-only. */ |
383 | { PTRACE_GETREGSET, -1, NT_S390_TDB, 0, EXTENDED_REGS, | |
384 | NULL, s390_store_tdb }, | |
bf2d68ab AA |
385 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_S390_VXRS_LOW, 0, |
386 | EXTENDED_REGS, s390_fill_vxrs_low, s390_store_vxrs_low }, | |
387 | { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_S390_VXRS_HIGH, 0, | |
388 | EXTENDED_REGS, s390_fill_vxrs_high, s390_store_vxrs_high }, | |
50bc912a | 389 | NULL_REGSET |
b7149293 UW |
390 | }; |
391 | ||
b0ded00b | 392 | |
dd373349 | 393 | static const gdb_byte s390_breakpoint[] = { 0, 1 }; |
b0ded00b UW |
394 | #define s390_breakpoint_len 2 |
395 | ||
dd373349 AT |
396 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
397 | ||
398 | static const gdb_byte * | |
399 | s390_sw_breakpoint_from_kind (int kind, int *size) | |
400 | { | |
401 | *size = s390_breakpoint_len; | |
402 | return s390_breakpoint; | |
403 | } | |
404 | ||
b0ded00b | 405 | static CORE_ADDR |
442ea881 | 406 | s390_get_pc (struct regcache *regcache) |
b0ded00b | 407 | { |
3aee8918 | 408 | if (register_size (regcache->tdesc, 0) == 4) |
d61ddec4 | 409 | { |
d6db1fab UW |
410 | unsigned int pswa; |
411 | collect_register_by_name (regcache, "pswa", &pswa); | |
412 | return pswa & 0x7fffffff; | |
d61ddec4 UW |
413 | } |
414 | else | |
415 | { | |
416 | unsigned long pc; | |
442ea881 | 417 | collect_register_by_name (regcache, "pswa", &pc); |
d61ddec4 UW |
418 | return pc; |
419 | } | |
b0ded00b UW |
420 | } |
421 | ||
422 | static void | |
442ea881 | 423 | s390_set_pc (struct regcache *regcache, CORE_ADDR newpc) |
b0ded00b | 424 | { |
3aee8918 | 425 | if (register_size (regcache->tdesc, 0) == 4) |
d61ddec4 | 426 | { |
d6db1fab UW |
427 | unsigned int pswa; |
428 | collect_register_by_name (regcache, "pswa", &pswa); | |
429 | pswa = (pswa & 0x80000000) | (newpc & 0x7fffffff); | |
430 | supply_register_by_name (regcache, "pswa", &pswa); | |
d61ddec4 UW |
431 | } |
432 | else | |
433 | { | |
434 | unsigned long pc = newpc; | |
442ea881 | 435 | supply_register_by_name (regcache, "pswa", &pc); |
d61ddec4 | 436 | } |
b0ded00b UW |
437 | } |
438 | ||
7803799a | 439 | static unsigned long |
3aee8918 | 440 | s390_get_hwcap (const struct target_desc *tdesc) |
7803799a | 441 | { |
3aee8918 | 442 | int wordsize = register_size (tdesc, 0); |
7803799a UW |
443 | unsigned char *data = alloca (2 * wordsize); |
444 | int offset = 0; | |
445 | ||
446 | while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize) | |
447 | { | |
448 | if (wordsize == 4) | |
449 | { | |
450 | unsigned int *data_p = (unsigned int *)data; | |
451 | if (data_p[0] == AT_HWCAP) | |
452 | return data_p[1]; | |
453 | } | |
454 | else | |
455 | { | |
456 | unsigned long *data_p = (unsigned long *)data; | |
457 | if (data_p[0] == AT_HWCAP) | |
458 | return data_p[1]; | |
459 | } | |
460 | ||
461 | offset += 2 * wordsize; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
d61ddec4 | 466 | |
c642a434 UW |
467 | static int |
468 | s390_check_regset (int pid, int regset, int regsize) | |
469 | { | |
470 | gdb_byte *buf = alloca (regsize); | |
471 | struct iovec iov; | |
472 | ||
473 | iov.iov_base = buf; | |
474 | iov.iov_len = regsize; | |
475 | ||
4ac33720 UW |
476 | if (ptrace (PTRACE_GETREGSET, pid, (long) regset, (long) &iov) >= 0 |
477 | || errno == ENODATA) | |
c642a434 | 478 | return 1; |
4ac33720 | 479 | return 0; |
c642a434 UW |
480 | } |
481 | ||
3aee8918 PA |
482 | /* For a 31-bit inferior, whether the kernel supports using the full |
483 | 64-bit GPRs. */ | |
484 | static int have_hwcap_s390_high_gprs = 0; | |
abd9baf9 | 485 | static int have_hwcap_s390_vx = 0; |
3aee8918 | 486 | |
d61ddec4 UW |
487 | static void |
488 | s390_arch_setup (void) | |
489 | { | |
3aee8918 | 490 | const struct target_desc *tdesc; |
c642a434 UW |
491 | struct regset_info *regset; |
492 | ||
493 | /* Check whether the kernel supports extra register sets. */ | |
0bfdf32f | 494 | int pid = pid_of (current_thread); |
c642a434 UW |
495 | int have_regset_last_break |
496 | = s390_check_regset (pid, NT_S390_LAST_BREAK, 8); | |
497 | int have_regset_system_call | |
498 | = s390_check_regset (pid, NT_S390_SYSTEM_CALL, 4); | |
4ac33720 | 499 | int have_regset_tdb = s390_check_regset (pid, NT_S390_TDB, 256); |
bf2d68ab AA |
500 | int have_regset_vxrs = s390_check_regset (pid, NT_S390_VXRS_LOW, 128) |
501 | && s390_check_regset (pid, NT_S390_VXRS_HIGH, 256); | |
c642a434 | 502 | |
d61ddec4 | 503 | /* Assume 31-bit inferior process. */ |
c642a434 | 504 | if (have_regset_system_call) |
3aee8918 | 505 | tdesc = tdesc_s390_linux32v2; |
c642a434 | 506 | else if (have_regset_last_break) |
3aee8918 | 507 | tdesc = tdesc_s390_linux32v1; |
c642a434 | 508 | else |
3aee8918 | 509 | tdesc = tdesc_s390_linux32; |
d61ddec4 UW |
510 | |
511 | /* On a 64-bit host, check the low bit of the (31-bit) PSWM | |
512 | -- if this is one, we actually have a 64-bit inferior. */ | |
d61ddec4 | 513 | { |
ab503087 | 514 | #ifdef __s390x__ |
d61ddec4 | 515 | unsigned int pswm; |
3aee8918 | 516 | struct regcache *regcache = new_register_cache (tdesc); |
6682d959 | 517 | |
3aee8918 | 518 | fetch_inferior_registers (regcache, find_regno (tdesc, "pswm")); |
442ea881 | 519 | collect_register_by_name (regcache, "pswm", &pswm); |
92b72907 UW |
520 | free_register_cache (regcache); |
521 | ||
d61ddec4 | 522 | if (pswm & 1) |
c642a434 | 523 | { |
6682d959 AA |
524 | if (have_regset_tdb) |
525 | have_regset_tdb = | |
526 | (s390_get_hwcap (tdesc_s390x_linux64v2) & HWCAP_S390_TE) != 0; | |
bf2d68ab AA |
527 | if (have_regset_vxrs) |
528 | have_regset_vxrs = | |
529 | (s390_get_hwcap (tdesc_s390x_linux64v2) & HWCAP_S390_VX) != 0; | |
530 | ||
531 | if (have_regset_vxrs) | |
532 | tdesc = (have_regset_tdb ? tdesc_s390x_tevx_linux64 : | |
533 | tdesc_s390x_vx_linux64); | |
534 | else if (have_regset_tdb) | |
4ac33720 | 535 | tdesc = tdesc_s390x_te_linux64; |
6682d959 | 536 | else if (have_regset_system_call) |
3aee8918 | 537 | tdesc = tdesc_s390x_linux64v2; |
c642a434 | 538 | else if (have_regset_last_break) |
3aee8918 | 539 | tdesc = tdesc_s390x_linux64v1; |
c642a434 | 540 | else |
3aee8918 | 541 | tdesc = tdesc_s390x_linux64; |
c642a434 | 542 | } |
7803799a UW |
543 | |
544 | /* For a 31-bit inferior, check whether the kernel supports | |
545 | using the full 64-bit GPRs. */ | |
ab503087 MK |
546 | else |
547 | #endif | |
548 | if (s390_get_hwcap (tdesc) & HWCAP_S390_HIGH_GPRS) | |
7803799a | 549 | { |
3aee8918 | 550 | have_hwcap_s390_high_gprs = 1; |
6682d959 AA |
551 | if (have_regset_tdb) |
552 | have_regset_tdb = (s390_get_hwcap (tdesc) & HWCAP_S390_TE) != 0; | |
bf2d68ab AA |
553 | if (have_regset_vxrs) |
554 | have_regset_vxrs = (s390_get_hwcap (tdesc) & HWCAP_S390_VX) != 0; | |
3aee8918 | 555 | |
bf2d68ab AA |
556 | if (have_regset_vxrs) |
557 | tdesc = (have_regset_tdb ? tdesc_s390_tevx_linux64 : | |
558 | tdesc_s390_vx_linux64); | |
559 | else if (have_regset_tdb) | |
4ac33720 UW |
560 | tdesc = tdesc_s390_te_linux64; |
561 | else if (have_regset_system_call) | |
3aee8918 | 562 | tdesc = tdesc_s390_linux64v2; |
c642a434 | 563 | else if (have_regset_last_break) |
3aee8918 | 564 | tdesc = tdesc_s390_linux64v1; |
c642a434 | 565 | else |
3aee8918 | 566 | tdesc = tdesc_s390_linux64; |
7803799a | 567 | } |
abd9baf9 MK |
568 | |
569 | have_hwcap_s390_vx = have_regset_vxrs; | |
d61ddec4 | 570 | } |
6682d959 AA |
571 | |
572 | /* Update target_regsets according to available register sets. */ | |
feea5f36 | 573 | for (regset = s390_regsets; regset->size >= 0; regset++) |
6682d959 AA |
574 | if (regset->get_request == PTRACE_GETREGSET) |
575 | switch (regset->nt_type) | |
576 | { | |
ab503087 MK |
577 | #ifndef __s390x__ |
578 | case NT_S390_HIGH_GPRS: | |
579 | regset->size = have_hwcap_s390_high_gprs ? 64 : 0; | |
580 | break; | |
581 | #endif | |
6682d959 | 582 | case NT_S390_LAST_BREAK: |
ab503087 | 583 | regset->size = have_regset_last_break ? 8 : 0; |
6682d959 AA |
584 | break; |
585 | case NT_S390_SYSTEM_CALL: | |
ab503087 | 586 | regset->size = have_regset_system_call ? 4 : 0; |
6682d959 AA |
587 | break; |
588 | case NT_S390_TDB: | |
589 | regset->size = have_regset_tdb ? 256 : 0; | |
bf2d68ab AA |
590 | break; |
591 | case NT_S390_VXRS_LOW: | |
592 | regset->size = have_regset_vxrs ? 128 : 0; | |
593 | break; | |
594 | case NT_S390_VXRS_HIGH: | |
595 | regset->size = have_regset_vxrs ? 256 : 0; | |
596 | break; | |
6682d959 AA |
597 | default: |
598 | break; | |
599 | } | |
600 | ||
3aee8918 | 601 | current_process ()->tdesc = tdesc; |
d61ddec4 UW |
602 | } |
603 | ||
604 | ||
b0ded00b UW |
605 | static int |
606 | s390_breakpoint_at (CORE_ADDR pc) | |
607 | { | |
608 | unsigned char c[s390_breakpoint_len]; | |
609 | read_inferior_memory (pc, c, s390_breakpoint_len); | |
610 | return memcmp (c, s390_breakpoint, s390_breakpoint_len) == 0; | |
611 | } | |
612 | ||
b00b61e1 MK |
613 | /* Breakpoint/Watchpoint support. */ |
614 | ||
615 | /* The "supports_z_point_type" linux_target_ops method. */ | |
616 | ||
617 | static int | |
618 | s390_supports_z_point_type (char z_type) | |
619 | { | |
620 | switch (z_type) | |
621 | { | |
622 | case Z_PACKET_SW_BP: | |
623 | return 1; | |
624 | default: | |
625 | return 0; | |
626 | } | |
627 | } | |
628 | ||
7d00775e AT |
629 | /* Support for hardware single step. */ |
630 | ||
631 | static int | |
632 | s390_supports_hardware_single_step (void) | |
633 | { | |
634 | return 1; | |
635 | } | |
636 | ||
3aee8918 PA |
637 | static struct usrregs_info s390_usrregs_info = |
638 | { | |
639 | s390_num_regs, | |
640 | s390_regmap, | |
641 | }; | |
642 | ||
643 | static struct regsets_info s390_regsets_info = | |
644 | { | |
645 | s390_regsets, /* regsets */ | |
646 | 0, /* num_regsets */ | |
647 | NULL, /* disabled_regsets */ | |
648 | }; | |
649 | ||
650 | static struct regs_info regs_info = | |
651 | { | |
652 | NULL, /* regset_bitmap */ | |
653 | &s390_usrregs_info, | |
654 | &s390_regsets_info | |
655 | }; | |
656 | ||
3aee8918 PA |
657 | static struct usrregs_info s390_usrregs_info_3264 = |
658 | { | |
659 | s390_num_regs_3264, | |
660 | s390_regmap_3264 | |
661 | }; | |
662 | ||
663 | static struct regsets_info s390_regsets_info_3264 = | |
664 | { | |
665 | s390_regsets, /* regsets */ | |
666 | 0, /* num_regsets */ | |
667 | NULL, /* disabled_regsets */ | |
668 | }; | |
669 | ||
670 | static struct regs_info regs_info_3264 = | |
671 | { | |
672 | NULL, /* regset_bitmap */ | |
673 | &s390_usrregs_info_3264, | |
674 | &s390_regsets_info_3264 | |
675 | }; | |
3aee8918 PA |
676 | |
677 | static const struct regs_info * | |
678 | s390_regs_info (void) | |
679 | { | |
3aee8918 PA |
680 | if (have_hwcap_s390_high_gprs) |
681 | { | |
ab503087 | 682 | #ifdef __s390x__ |
3aee8918 PA |
683 | const struct target_desc *tdesc = current_process ()->tdesc; |
684 | ||
685 | if (register_size (tdesc, 0) == 4) | |
686 | return ®s_info_3264; | |
ab503087 MK |
687 | #else |
688 | return ®s_info_3264; | |
3aee8918 | 689 | #endif |
ab503087 | 690 | } |
3aee8918 PA |
691 | return ®s_info; |
692 | } | |
b0ded00b | 693 | |
a4105d04 MK |
694 | /* The "supports_tracepoints" linux_target_ops method. */ |
695 | ||
696 | static int | |
697 | s390_supports_tracepoints (void) | |
698 | { | |
699 | return 1; | |
700 | } | |
701 | ||
abd9baf9 MK |
702 | /* Implementation of linux_target_ops method "get_thread_area". */ |
703 | ||
704 | static int | |
705 | s390_get_thread_area (int lwpid, CORE_ADDR *addrp) | |
706 | { | |
707 | CORE_ADDR res = ptrace (PTRACE_PEEKUSER, lwpid, (long) PT_ACR0, (long) 0); | |
708 | #ifdef __s390x__ | |
709 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
710 | ||
711 | if (register_size (regcache->tdesc, 0) == 4) | |
712 | res &= 0xffffffffull; | |
713 | #endif | |
714 | *addrp = res; | |
715 | return 0; | |
716 | } | |
717 | ||
718 | ||
719 | /* Fast tracepoint support. | |
720 | ||
721 | The register save area on stack is identical for all targets: | |
722 | ||
723 | 0x000+i*0x10: VR0-VR31 | |
724 | 0x200+i*8: GR0-GR15 | |
725 | 0x280+i*4: AR0-AR15 | |
726 | 0x2c0: PSWM [64-bit] | |
727 | 0x2c8: PSWA [64-bit] | |
728 | 0x2d0: FPC | |
729 | ||
730 | If we're on 31-bit linux, we just don't store the high parts of the GPRs. | |
731 | Likewise, if there's no VX support, we just store the FRs into the slots | |
732 | of low VR halves. The agent code is responsible for rearranging that | |
733 | into regcache. */ | |
734 | ||
735 | /* Code sequence saving GPRs for 31-bit target with no high GPRs. There's | |
736 | one trick used at the very beginning: since there's no way to allocate | |
737 | stack space without destroying CC (lay instruction can do it, but it's | |
738 | only supported on later CPUs), we take 4 different execution paths for | |
739 | every possible value of CC, allocate stack space, save %r0, stuff the | |
740 | CC value in %r0 (shifted to match its position in PSWM high word), | |
741 | then branch to common path. */ | |
742 | ||
743 | static const unsigned char s390_ft_entry_gpr_esa[] = { | |
744 | 0xa7, 0x14, 0x00, 0x1e, /* jo .Lcc3 */ | |
745 | 0xa7, 0x24, 0x00, 0x14, /* jh .Lcc2 */ | |
746 | 0xa7, 0x44, 0x00, 0x0a, /* jl .Lcc1 */ | |
747 | /* CC = 0 */ | |
748 | 0xa7, 0xfa, 0xfd, 0x00, /* ahi %r15, -0x300 */ | |
749 | 0x50, 0x00, 0xf2, 0x04, /* st %r0, 0x204(%r15) */ | |
750 | 0xa7, 0x08, 0x00, 0x00, /* lhi %r0, 0 */ | |
751 | 0xa7, 0xf4, 0x00, 0x18, /* j .Lccdone */ | |
752 | /* .Lcc1: */ | |
753 | 0xa7, 0xfa, 0xfd, 0x00, /* ahi %r15, -0x300 */ | |
754 | 0x50, 0x00, 0xf2, 0x04, /* st %r0, 0x204(%r15) */ | |
755 | 0xa7, 0x08, 0x10, 0x00, /* lhi %r0, 0x1000 */ | |
756 | 0xa7, 0xf4, 0x00, 0x10, /* j .Lccdone */ | |
757 | /* .Lcc2: */ | |
758 | 0xa7, 0xfa, 0xfd, 0x00, /* ahi %r15, -0x300 */ | |
759 | 0x50, 0x00, 0xf2, 0x04, /* st %r0, 0x204(%r15) */ | |
760 | 0xa7, 0x08, 0x20, 0x00, /* lhi %r0, 0x2000 */ | |
761 | 0xa7, 0xf4, 0x00, 0x08, /* j .Lccdone */ | |
762 | /* .Lcc3: */ | |
763 | 0xa7, 0xfa, 0xfd, 0x00, /* ahi %r15, -0x300 */ | |
764 | 0x50, 0x00, 0xf2, 0x04, /* st %r0, 0x204(%r15) */ | |
765 | 0xa7, 0x08, 0x30, 0x00, /* lhi %r0, 0x3000 */ | |
766 | /* .Lccdone: */ | |
767 | 0x50, 0x10, 0xf2, 0x0c, /* st %r1, 0x20c(%r15) */ | |
768 | 0x50, 0x20, 0xf2, 0x14, /* st %r2, 0x214(%r15) */ | |
769 | 0x50, 0x30, 0xf2, 0x1c, /* st %r3, 0x21c(%r15) */ | |
770 | 0x50, 0x40, 0xf2, 0x24, /* st %r4, 0x224(%r15) */ | |
771 | 0x50, 0x50, 0xf2, 0x2c, /* st %r5, 0x22c(%r15) */ | |
772 | 0x50, 0x60, 0xf2, 0x34, /* st %r6, 0x234(%r15) */ | |
773 | 0x50, 0x70, 0xf2, 0x3c, /* st %r7, 0x23c(%r15) */ | |
774 | 0x50, 0x80, 0xf2, 0x44, /* st %r8, 0x244(%r15) */ | |
775 | 0x50, 0x90, 0xf2, 0x4c, /* st %r9, 0x24c(%r15) */ | |
776 | 0x50, 0xa0, 0xf2, 0x54, /* st %r10, 0x254(%r15) */ | |
777 | 0x50, 0xb0, 0xf2, 0x5c, /* st %r11, 0x25c(%r15) */ | |
778 | 0x50, 0xc0, 0xf2, 0x64, /* st %r12, 0x264(%r15) */ | |
779 | 0x50, 0xd0, 0xf2, 0x6c, /* st %r13, 0x26c(%r15) */ | |
780 | 0x50, 0xe0, 0xf2, 0x74, /* st %r14, 0x274(%r15) */ | |
781 | /* Compute original value of %r15 and store it. We use ahi instead | |
782 | of la to preserve the whole value, and not just the low 31 bits. | |
783 | This is not particularly important here, but essential in the | |
784 | zarch case where someone might be using the high word of %r15 | |
785 | as an extra register. */ | |
786 | 0x18, 0x1f, /* lr %r1, %r15 */ | |
787 | 0xa7, 0x1a, 0x03, 0x00, /* ahi %r1, 0x300 */ | |
788 | 0x50, 0x10, 0xf2, 0x7c, /* st %r1, 0x27c(%r15) */ | |
789 | }; | |
790 | ||
791 | /* Code sequence saving GPRs for 31-bit target with high GPRs and for 64-bit | |
792 | target. Same as above, except this time we can use load/store multiple, | |
793 | since the 64-bit regs are tightly packed. */ | |
794 | ||
795 | static const unsigned char s390_ft_entry_gpr_zarch[] = { | |
796 | 0xa7, 0x14, 0x00, 0x21, /* jo .Lcc3 */ | |
797 | 0xa7, 0x24, 0x00, 0x16, /* jh .Lcc2 */ | |
798 | 0xa7, 0x44, 0x00, 0x0b, /* jl .Lcc1 */ | |
799 | /* CC = 0 */ | |
800 | 0xa7, 0xfb, 0xfd, 0x00, /* aghi %r15, -0x300 */ | |
801 | 0xeb, 0x0e, 0xf2, 0x00, 0x00, 0x24, /* stmg %r0, %r14, 0x200(%r15) */ | |
802 | 0xa7, 0x08, 0x00, 0x00, /* lhi %r0, 0 */ | |
803 | 0xa7, 0xf4, 0x00, 0x1b, /* j .Lccdone */ | |
804 | /* .Lcc1: */ | |
805 | 0xa7, 0xfb, 0xfd, 0x00, /* aghi %r15, -0x300 */ | |
806 | 0xeb, 0x0e, 0xf2, 0x00, 0x00, 0x24, /* stmg %r0, %r14, 0x200(%r15) */ | |
807 | 0xa7, 0x08, 0x10, 0x00, /* lhi %r0, 0x1000 */ | |
808 | 0xa7, 0xf4, 0x00, 0x12, /* j .Lccdone */ | |
809 | /* .Lcc2: */ | |
810 | 0xa7, 0xfb, 0xfd, 0x00, /* aghi %r15, -0x300 */ | |
811 | 0xeb, 0x0e, 0xf2, 0x00, 0x00, 0x24, /* stmg %r0, %r14, 0x200(%r15) */ | |
812 | 0xa7, 0x08, 0x20, 0x00, /* lhi %r0, 0x2000 */ | |
813 | 0xa7, 0xf4, 0x00, 0x09, /* j .Lccdone */ | |
814 | /* .Lcc3: */ | |
815 | 0xa7, 0xfb, 0xfd, 0x00, /* aghi %r15, -0x300 */ | |
816 | 0xeb, 0x0e, 0xf2, 0x00, 0x00, 0x24, /* stmg %r0, %r14, 0x200(%r15) */ | |
817 | 0xa7, 0x08, 0x30, 0x00, /* lhi %r0, 0x3000 */ | |
818 | /* .Lccdone: */ | |
819 | 0xb9, 0x04, 0x00, 0x1f, /* lgr %r1, %r15 */ | |
820 | 0xa7, 0x1b, 0x03, 0x00, /* aghi %r1, 0x300 */ | |
821 | 0xe3, 0x10, 0xf2, 0x78, 0x00, 0x24, /* stg %r1, 0x278(%r15) */ | |
822 | }; | |
823 | ||
824 | /* Code sequence saving ARs, PSWM and FPC. PSWM has to be assembled from | |
825 | current PSWM (read by epsw) and CC from entry (in %r0). */ | |
826 | ||
827 | static const unsigned char s390_ft_entry_misc[] = { | |
828 | 0x9b, 0x0f, 0xf2, 0x80, /* stam %a0, %a15, 0x20(%%r15) */ | |
829 | 0xb9, 0x8d, 0x00, 0x23, /* epsw %r2, %r3 */ | |
830 | 0xa7, 0x18, 0xcf, 0xff, /* lhi %r1, ~0x3000 */ | |
831 | 0x14, 0x21, /* nr %r2, %r1 */ | |
832 | 0x16, 0x20, /* or %r2, %r0 */ | |
833 | 0x50, 0x20, 0xf2, 0xc0, /* st %r2, 0x2c0(%r15) */ | |
834 | 0x50, 0x30, 0xf2, 0xc4, /* st %r3, 0x2c4(%r15) */ | |
835 | 0xb2, 0x9c, 0xf2, 0xd0, /* stfpc 0x2d0(%r15) */ | |
836 | }; | |
837 | ||
838 | /* Code sequence saving FRs, used if VX not supported. */ | |
839 | ||
840 | static const unsigned char s390_ft_entry_fr[] = { | |
841 | 0x60, 0x00, 0xf0, 0x00, /* std %f0, 0x000(%r15) */ | |
842 | 0x60, 0x10, 0xf0, 0x10, /* std %f1, 0x010(%r15) */ | |
843 | 0x60, 0x20, 0xf0, 0x20, /* std %f2, 0x020(%r15) */ | |
844 | 0x60, 0x30, 0xf0, 0x30, /* std %f3, 0x030(%r15) */ | |
845 | 0x60, 0x40, 0xf0, 0x40, /* std %f4, 0x040(%r15) */ | |
846 | 0x60, 0x50, 0xf0, 0x50, /* std %f5, 0x050(%r15) */ | |
847 | 0x60, 0x60, 0xf0, 0x60, /* std %f6, 0x060(%r15) */ | |
848 | 0x60, 0x70, 0xf0, 0x70, /* std %f7, 0x070(%r15) */ | |
849 | 0x60, 0x80, 0xf0, 0x80, /* std %f8, 0x080(%r15) */ | |
850 | 0x60, 0x90, 0xf0, 0x90, /* std %f9, 0x090(%r15) */ | |
851 | 0x60, 0xa0, 0xf0, 0xa0, /* std %f10, 0x0a0(%r15) */ | |
852 | 0x60, 0xb0, 0xf0, 0xb0, /* std %f11, 0x0b0(%r15) */ | |
853 | 0x60, 0xc0, 0xf0, 0xc0, /* std %f12, 0x0c0(%r15) */ | |
854 | 0x60, 0xd0, 0xf0, 0xd0, /* std %f13, 0x0d0(%r15) */ | |
855 | 0x60, 0xe0, 0xf0, 0xe0, /* std %f14, 0x0e0(%r15) */ | |
856 | 0x60, 0xf0, 0xf0, 0xf0, /* std %f15, 0x0f0(%r15) */ | |
857 | }; | |
858 | ||
859 | /* Code sequence saving VRs, used if VX not supported. */ | |
860 | ||
861 | static const unsigned char s390_ft_entry_vr[] = { | |
862 | 0xe7, 0x0f, 0xf0, 0x00, 0x00, 0x3e, /* vstm %v0, %v15, 0x000(%r15) */ | |
863 | 0xe7, 0x0f, 0xf1, 0x00, 0x0c, 0x3e, /* vstm %v16, %v31, 0x100(%r15) */ | |
864 | }; | |
865 | ||
866 | /* Code sequence doing the collection call for 31-bit target. %r1 contains | |
867 | the address of the literal pool. */ | |
868 | ||
869 | static const unsigned char s390_ft_main_31[] = { | |
870 | /* Load the literals into registers. */ | |
871 | 0x58, 0x50, 0x10, 0x00, /* l %r5, 0x0(%r1) */ | |
872 | 0x58, 0x20, 0x10, 0x04, /* l %r2, 0x4(%r1) */ | |
873 | 0x58, 0x40, 0x10, 0x08, /* l %r4, 0x8(%r1) */ | |
874 | 0x58, 0x60, 0x10, 0x0c, /* l %r6, 0xc(%r1) */ | |
875 | /* Save original PSWA (tracepoint address | 0x80000000). */ | |
876 | 0x50, 0x50, 0xf2, 0xcc, /* st %r5, 0x2cc(%r15) */ | |
877 | /* Construct a collecting_t object at %r15+0x2e0. */ | |
878 | 0x50, 0x20, 0xf2, 0xe0, /* st %r2, 0x2e0(%r15) */ | |
879 | 0x9b, 0x00, 0xf2, 0xe4, /* stam %a0, %a0, 0x2e4(%r15) */ | |
880 | /* Move its address to %r0. */ | |
881 | 0x41, 0x00, 0xf2, 0xe0, /* la %r0, 0x2e0(%r15) */ | |
882 | /* Take the lock. */ | |
883 | /* .Lloop: */ | |
884 | 0xa7, 0x18, 0x00, 0x00, /* lhi %r1, 0 */ | |
885 | 0xba, 0x10, 0x60, 0x00, /* cs %r1, %r0, 0(%r6) */ | |
886 | 0xa7, 0x74, 0xff, 0xfc, /* jne .Lloop */ | |
887 | /* Address of the register save block to %r3. */ | |
888 | 0x18, 0x3f, /* lr %r3, %r15 */ | |
889 | /* Make a stack frame, so that we can call the collector. */ | |
890 | 0xa7, 0xfa, 0xff, 0xa0, /* ahi %r15, -0x60 */ | |
891 | /* Call it. */ | |
892 | 0x0d, 0xe4, /* basr %r14, %r4 */ | |
893 | /* And get rid of the stack frame again. */ | |
894 | 0x41, 0xf0, 0xf0, 0x60, /* la %r15, 0x60(%r15) */ | |
895 | /* Leave the lock. */ | |
896 | 0x07, 0xf0, /* br %r0 */ | |
897 | 0xa7, 0x18, 0x00, 0x00, /* lhi %r1, 0 */ | |
898 | 0x50, 0x10, 0x60, 0x00, /* st %t1, 0(%r6) */ | |
899 | }; | |
900 | ||
901 | /* Code sequence doing the collection call for 64-bit target. %r1 contains | |
902 | the address of the literal pool. */ | |
903 | ||
904 | static const unsigned char s390_ft_main_64[] = { | |
905 | /* Load the literals into registers. */ | |
906 | 0xe3, 0x50, 0x10, 0x00, 0x00, 0x04, /* lg %r5, 0x00(%r1) */ | |
907 | 0xe3, 0x20, 0x10, 0x08, 0x00, 0x04, /* lg %r2, 0x08(%r1) */ | |
908 | 0xe3, 0x40, 0x10, 0x10, 0x00, 0x04, /* lg %r4, 0x10(%r1) */ | |
909 | 0xe3, 0x60, 0x10, 0x18, 0x00, 0x04, /* lg %r6, 0x18(%r1) */ | |
910 | /* Save original PSWA (tracepoint address). */ | |
911 | 0xe3, 0x50, 0xf2, 0xc8, 0x00, 0x24, /* stg %r5, 0x2c8(%r15) */ | |
912 | /* Construct a collecting_t object at %r15+0x2e0. */ | |
913 | 0xe3, 0x20, 0xf2, 0xe0, 0x00, 0x24, /* stg %r2, 0x2e0(%r15) */ | |
914 | 0x9b, 0x01, 0xf2, 0xe8, /* stam %a0, %a1, 0x2e8(%r15) */ | |
915 | /* Move its address to %r0. */ | |
916 | 0x41, 0x00, 0xf2, 0xe0, /* la %r0, 0x2e0(%r15) */ | |
917 | /* Take the lock. */ | |
918 | /* .Lloop: */ | |
919 | 0xa7, 0x19, 0x00, 0x00, /* lghi %r1, 0 */ | |
920 | 0xeb, 0x10, 0x60, 0x00, 0x00, 0x30, /* csg %r1, %r0, 0(%r6) */ | |
921 | 0xa7, 0x74, 0xff, 0xfb, /* jne .Lloop */ | |
922 | /* Address of the register save block to %r3. */ | |
923 | 0xb9, 0x04, 0x00, 0x3f, /* lgr %r3, %r15 */ | |
924 | /* Make a stack frame, so that we can call the collector. */ | |
925 | 0xa7, 0xfb, 0xff, 0x60, /* aghi %r15, -0xa0 */ | |
926 | /* Call it. */ | |
927 | 0x0d, 0xe4, /* basr %r14, %r4 */ | |
928 | /* And get rid of the stack frame again. */ | |
929 | 0x41, 0xf0, 0xf0, 0xa0, /* la %r15, 0xa0(%r15) */ | |
930 | /* Leave the lock. */ | |
931 | 0x07, 0xf0, /* br %r0 */ | |
932 | 0xa7, 0x19, 0x00, 0x00, /* lghi %r1, 0 */ | |
933 | 0xe3, 0x10, 0x60, 0x00, 0x00, 0x24, /* stg %t1, 0(%r6) */ | |
934 | }; | |
935 | ||
936 | /* Code sequence restoring FRs, for targets with no VX support. */ | |
937 | ||
938 | static const unsigned char s390_ft_exit_fr[] = { | |
939 | 0x68, 0x00, 0xf0, 0x00, /* ld %f0, 0x000(%r15) */ | |
940 | 0x68, 0x10, 0xf0, 0x10, /* ld %f1, 0x010(%r15) */ | |
941 | 0x68, 0x20, 0xf0, 0x20, /* ld %f2, 0x020(%r15) */ | |
942 | 0x68, 0x30, 0xf0, 0x30, /* ld %f3, 0x030(%r15) */ | |
943 | 0x68, 0x40, 0xf0, 0x40, /* ld %f4, 0x040(%r15) */ | |
944 | 0x68, 0x50, 0xf0, 0x50, /* ld %f5, 0x050(%r15) */ | |
945 | 0x68, 0x60, 0xf0, 0x60, /* ld %f6, 0x060(%r15) */ | |
946 | 0x68, 0x70, 0xf0, 0x70, /* ld %f7, 0x070(%r15) */ | |
947 | 0x68, 0x80, 0xf0, 0x80, /* ld %f8, 0x080(%r15) */ | |
948 | 0x68, 0x90, 0xf0, 0x90, /* ld %f9, 0x090(%r15) */ | |
949 | 0x68, 0xa0, 0xf0, 0xa0, /* ld %f10, 0x0a0(%r15) */ | |
950 | 0x68, 0xb0, 0xf0, 0xb0, /* ld %f11, 0x0b0(%r15) */ | |
951 | 0x68, 0xc0, 0xf0, 0xc0, /* ld %f12, 0x0c0(%r15) */ | |
952 | 0x68, 0xd0, 0xf0, 0xd0, /* ld %f13, 0x0d0(%r15) */ | |
953 | 0x68, 0xe0, 0xf0, 0xe0, /* ld %f14, 0x0e0(%r15) */ | |
954 | 0x68, 0xf0, 0xf0, 0xf0, /* ld %f15, 0x0f0(%r15) */ | |
955 | }; | |
956 | ||
957 | /* Code sequence restoring VRs. */ | |
958 | ||
959 | static const unsigned char s390_ft_exit_vr[] = { | |
960 | 0xe7, 0x0f, 0xf0, 0x00, 0x00, 0x36, /* vlm %v0, %v15, 0x000(%r15) */ | |
961 | 0xe7, 0x0f, 0xf1, 0x00, 0x0c, 0x36, /* vlm %v16, %v31, 0x100(%r15) */ | |
962 | }; | |
963 | ||
964 | /* Code sequence restoring misc registers. As for PSWM, only CC should be | |
965 | modified by C code, so we use the alr instruction to restore it by | |
966 | manufacturing an operand that'll result in the original flags. */ | |
967 | ||
968 | static const unsigned char s390_ft_exit_misc[] = { | |
969 | 0xb2, 0x9d, 0xf2, 0xd0, /* lfpc 0x2d0(%r15) */ | |
970 | 0x58, 0x00, 0xf2, 0xc0, /* l %r0, 0x2c0(%r15) */ | |
971 | /* Extract CC to high 2 bits of %r0. */ | |
972 | 0x88, 0x00, 0x00, 0x0c, /* srl %r0, 12 */ | |
973 | 0x89, 0x00, 0x00, 0x1e, /* sll %r0, 30 */ | |
974 | /* Add %r0 to itself. Result will be nonzero iff CC bit 0 is set, and | |
975 | will have carry iff CC bit 1 is set - resulting in the same flags | |
976 | as the original. */ | |
977 | 0x1e, 0x00, /* alr %r0, %r0 */ | |
978 | 0x9a, 0x0f, 0xf2, 0x80, /* lam %a0, %a15, 0x280(%r15) */ | |
979 | }; | |
980 | ||
981 | /* Code sequence restoring GPRs, for 31-bit targets with no high GPRs. */ | |
982 | ||
983 | static const unsigned char s390_ft_exit_gpr_esa[] = { | |
984 | 0x58, 0x00, 0xf2, 0x04, /* l %r0, 0x204(%r15) */ | |
985 | 0x58, 0x10, 0xf2, 0x0c, /* l %r1, 0x20c(%r15) */ | |
986 | 0x58, 0x20, 0xf2, 0x14, /* l %r2, 0x214(%r15) */ | |
987 | 0x58, 0x30, 0xf2, 0x1c, /* l %r3, 0x21c(%r15) */ | |
988 | 0x58, 0x40, 0xf2, 0x24, /* l %r4, 0x224(%r15) */ | |
989 | 0x58, 0x50, 0xf2, 0x2c, /* l %r5, 0x22c(%r15) */ | |
990 | 0x58, 0x60, 0xf2, 0x34, /* l %r6, 0x234(%r15) */ | |
991 | 0x58, 0x70, 0xf2, 0x3c, /* l %r7, 0x23c(%r15) */ | |
992 | 0x58, 0x80, 0xf2, 0x44, /* l %r8, 0x244(%r15) */ | |
993 | 0x58, 0x90, 0xf2, 0x4c, /* l %r9, 0x24c(%r15) */ | |
994 | 0x58, 0xa0, 0xf2, 0x54, /* l %r10, 0x254(%r15) */ | |
995 | 0x58, 0xb0, 0xf2, 0x5c, /* l %r11, 0x25c(%r15) */ | |
996 | 0x58, 0xc0, 0xf2, 0x64, /* l %r12, 0x264(%r15) */ | |
997 | 0x58, 0xd0, 0xf2, 0x6c, /* l %r13, 0x26c(%r15) */ | |
998 | 0x58, 0xe0, 0xf2, 0x74, /* l %r14, 0x274(%r15) */ | |
999 | 0x58, 0xf0, 0xf2, 0x7c, /* l %r15, 0x27c(%r15) */ | |
1000 | }; | |
1001 | ||
1002 | /* Code sequence restoring GPRs, for 64-bit targets and 31-bit targets | |
1003 | with high GPRs. */ | |
1004 | ||
1005 | static const unsigned char s390_ft_exit_gpr_zarch[] = { | |
1006 | 0xeb, 0x0f, 0xf2, 0x00, 0x00, 0x04, /* lmg %r0, %r15, 0x200(%r15) */ | |
1007 | }; | |
1008 | ||
1009 | /* Writes instructions to target, updating the to pointer. */ | |
1010 | ||
1011 | static void | |
1012 | append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf) | |
1013 | { | |
1014 | write_inferior_memory (*to, buf, len); | |
1015 | *to += len; | |
1016 | } | |
1017 | ||
1018 | /* Relocates an instruction from oldloc to *to, updating to. */ | |
1019 | ||
1020 | static int | |
1021 | s390_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc, int is_64) | |
1022 | { | |
1023 | gdb_byte buf[6]; | |
1024 | int ilen; | |
1025 | int op2; | |
1026 | /* 0: no fixup, 1: PC16DBL fixup, 2: PC32DBL fixup. */ | |
1027 | int mode = 0; | |
1028 | int is_bras = 0; | |
1029 | read_inferior_memory (oldloc, buf, sizeof buf); | |
1030 | if (buf[0] < 0x40) | |
1031 | ilen = 2; | |
1032 | else if (buf[0] < 0xc0) | |
1033 | ilen = 4; | |
1034 | else | |
1035 | ilen = 6; | |
1036 | switch (buf[0]) | |
1037 | { | |
1038 | case 0x05: /* BALR */ | |
1039 | case 0x0c: /* BASSM */ | |
1040 | case 0x0d: /* BASR */ | |
1041 | case 0x45: /* BAL */ | |
1042 | case 0x4d: /* BAS */ | |
1043 | /* These save a return address and mess around with registers. | |
1044 | We can't relocate them. */ | |
1045 | return 1; | |
1046 | case 0x84: /* BRXH */ | |
1047 | case 0x85: /* BRXLE */ | |
1048 | mode = 1; | |
1049 | break; | |
1050 | case 0xa7: | |
1051 | op2 = buf[1] & 0xf; | |
1052 | /* BRC, BRAS, BRCT, BRCTG */ | |
1053 | if (op2 >= 4 && op2 <= 7) | |
1054 | mode = 1; | |
1055 | /* BRAS */ | |
1056 | if (op2 == 5) | |
1057 | is_bras = 1; | |
1058 | break; | |
1059 | case 0xc0: | |
1060 | op2 = buf[1] & 0xf; | |
1061 | /* LARL, BRCL, BRASL */ | |
1062 | if (op2 == 0 || op2 == 4 || op2 == 5) | |
1063 | mode = 2; | |
1064 | /* BRASL */ | |
1065 | if (op2 == 5) | |
1066 | is_bras = 1; | |
1067 | break; | |
1068 | case 0xc4: | |
1069 | case 0xc6: | |
1070 | /* PC-relative addressing instructions. */ | |
1071 | mode = 2; | |
1072 | break; | |
1073 | case 0xc5: /* BPRP */ | |
1074 | case 0xc7: /* BPP */ | |
1075 | /* Branch prediction - just skip it. */ | |
1076 | return 0; | |
1077 | case 0xcc: | |
1078 | op2 = buf[1] & 0xf; | |
1079 | /* BRCTH */ | |
1080 | if (op2 == 6) | |
1081 | mode = 2; | |
1082 | break; | |
1083 | case 0xec: | |
1084 | op2 = buf[5]; | |
1085 | switch (op2) | |
1086 | { | |
1087 | case 0x44: /* BRXHG */ | |
1088 | case 0x45: /* BRXLG */ | |
1089 | case 0x64: /* CGRJ */ | |
1090 | case 0x65: /* CLGRJ */ | |
1091 | case 0x76: /* CRJ */ | |
1092 | case 0x77: /* CLRJ */ | |
1093 | mode = 1; | |
1094 | break; | |
1095 | } | |
1096 | break; | |
1097 | } | |
1098 | ||
1099 | if (mode != 0) | |
1100 | { | |
1101 | /* We'll have to relocate an instruction with a PC-relative field. | |
1102 | First, compute the target. */ | |
1103 | int64_t loffset = 0; | |
1104 | CORE_ADDR target; | |
1105 | if (mode == 1) | |
1106 | { | |
1107 | int16_t soffset = 0; | |
1108 | memcpy (&soffset, buf + 2, 2); | |
1109 | loffset = soffset; | |
1110 | } | |
1111 | else if (mode == 2) | |
1112 | { | |
1113 | int32_t soffset = 0; | |
1114 | memcpy (&soffset, buf + 2, 4); | |
1115 | loffset = soffset; | |
1116 | } | |
1117 | target = oldloc + loffset * 2; | |
1118 | if (!is_64) | |
1119 | target &= 0x7fffffff; | |
1120 | ||
1121 | if (is_bras) | |
1122 | { | |
1123 | /* BRAS or BRASL was used. We cannot just relocate those, since | |
1124 | they save the return address in a register. We can, however, | |
1125 | replace them with a LARL+JG sequence. */ | |
1126 | ||
1127 | /* Make the LARL. */ | |
1128 | int32_t soffset; | |
1129 | buf[0] = 0xc0; | |
1130 | buf[1] &= 0xf0; | |
1131 | loffset = oldloc + ilen - *to; | |
1132 | loffset >>= 1; | |
1133 | soffset = loffset; | |
1134 | if (soffset != loffset && is_64) | |
1135 | return 1; | |
1136 | memcpy (buf + 2, &soffset, 4); | |
1137 | append_insns (to, 6, buf); | |
1138 | ||
1139 | /* Note: this is not fully correct. In 31-bit mode, LARL will write | |
1140 | an address with the top bit 0, while BRAS/BRASL will write it | |
1141 | with top bit 1. It should not matter much, since linux compilers | |
1142 | use BR and not BSM to return from functions, but it could confuse | |
1143 | some poor stack unwinder. */ | |
1144 | ||
1145 | /* We'll now be writing a JG. */ | |
1146 | mode = 2; | |
1147 | buf[0] = 0xc0; | |
1148 | buf[1] = 0xf4; | |
1149 | ilen = 6; | |
1150 | } | |
1151 | ||
1152 | /* Compute the new offset and write it to the buffer. */ | |
1153 | loffset = target - *to; | |
1154 | loffset >>= 1; | |
1155 | ||
1156 | if (mode == 1) | |
1157 | { | |
1158 | int16_t soffset = loffset; | |
1159 | if (soffset != loffset) | |
1160 | return 1; | |
1161 | memcpy (buf + 2, &soffset, 2); | |
1162 | } | |
1163 | else if (mode == 2) | |
1164 | { | |
1165 | int32_t soffset = loffset; | |
1166 | if (soffset != loffset && is_64) | |
1167 | return 1; | |
1168 | memcpy (buf + 2, &soffset, 4); | |
1169 | } | |
1170 | } | |
1171 | append_insns (to, ilen, buf); | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | /* Implementation of linux_target_ops method | |
1176 | "install_fast_tracepoint_jump_pad". */ | |
1177 | ||
1178 | static int | |
1179 | s390_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, | |
1180 | CORE_ADDR tpaddr, | |
1181 | CORE_ADDR collector, | |
1182 | CORE_ADDR lockaddr, | |
1183 | ULONGEST orig_size, | |
1184 | CORE_ADDR *jump_entry, | |
1185 | CORE_ADDR *trampoline, | |
1186 | ULONGEST *trampoline_size, | |
1187 | unsigned char *jjump_pad_insn, | |
1188 | ULONGEST *jjump_pad_insn_size, | |
1189 | CORE_ADDR *adjusted_insn_addr, | |
1190 | CORE_ADDR *adjusted_insn_addr_end, | |
1191 | char *err) | |
1192 | { | |
1193 | int i; | |
1194 | int64_t loffset; | |
1195 | int32_t offset; | |
1196 | unsigned char jbuf[6] = { 0xc0, 0xf4, 0, 0, 0, 0 }; /* jg ... */ | |
1197 | CORE_ADDR buildaddr = *jump_entry; | |
1198 | #ifdef __s390x__ | |
1199 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
1200 | int is_64 = register_size (regcache->tdesc, 0) == 8; | |
1201 | int is_zarch = is_64 || have_hwcap_s390_high_gprs; | |
1202 | int has_vx = have_hwcap_s390_vx; | |
1203 | #else | |
1204 | int is_64 = 0, is_zarch = 0, has_vx = 0; | |
1205 | #endif | |
1206 | CORE_ADDR literals[4] = { | |
1207 | tpaddr, | |
1208 | tpoint, | |
1209 | collector, | |
1210 | lockaddr, | |
1211 | }; | |
1212 | ||
1213 | /* First, store the GPRs. */ | |
1214 | if (is_zarch) | |
1215 | append_insns (&buildaddr, sizeof s390_ft_entry_gpr_zarch, | |
1216 | s390_ft_entry_gpr_zarch); | |
1217 | else | |
1218 | append_insns (&buildaddr, sizeof s390_ft_entry_gpr_esa, | |
1219 | s390_ft_entry_gpr_esa); | |
1220 | ||
1221 | /* Second, misc registers (ARs, PSWM, FPC). PSWA will be stored below. */ | |
1222 | append_insns (&buildaddr, sizeof s390_ft_entry_misc, s390_ft_entry_misc); | |
1223 | ||
1224 | /* Third, FRs or VRs. */ | |
1225 | if (has_vx) | |
1226 | append_insns (&buildaddr, sizeof s390_ft_entry_vr, s390_ft_entry_vr); | |
1227 | else | |
1228 | append_insns (&buildaddr, sizeof s390_ft_entry_fr, s390_ft_entry_fr); | |
1229 | ||
1230 | /* Now, the main part of code - store PSWA, take lock, call collector, | |
1231 | leave lock. First, we'll need to fetch 4 literals. */ | |
1232 | if (is_64) { | |
1233 | unsigned char buf[] = { | |
1234 | 0x07, 0x07, /* nopr %r7 */ | |
1235 | 0x07, 0x07, /* nopr %r7 */ | |
1236 | 0x07, 0x07, /* nopr %r7 */ | |
1237 | 0xa7, 0x15, 0x00, 0x12, /* bras %r1, .Lend */ | |
1238 | 0, 0, 0, 0, 0, 0, 0, 0, /* tpaddr */ | |
1239 | 0, 0, 0, 0, 0, 0, 0, 0, /* tpoint */ | |
1240 | 0, 0, 0, 0, 0, 0, 0, 0, /* collector */ | |
1241 | 0, 0, 0, 0, 0, 0, 0, 0, /* lockaddr */ | |
1242 | /* .Lend: */ | |
1243 | }; | |
1244 | /* Find the proper start place in buf, so that literals will be | |
1245 | aligned. */ | |
1246 | int bufpos = (buildaddr + 2) & 7; | |
1247 | /* Stuff the literals into the buffer. */ | |
1248 | for (i = 0; i < 4; i++) { | |
1249 | uint64_t lit = literals[i]; | |
1250 | memcpy (&buf[sizeof buf - 32 + i * 8], &lit, 8); | |
1251 | } | |
1252 | append_insns (&buildaddr, sizeof buf - bufpos, buf + bufpos); | |
1253 | append_insns (&buildaddr, sizeof s390_ft_main_64, s390_ft_main_64); | |
1254 | } else { | |
1255 | unsigned char buf[] = { | |
1256 | 0x07, 0x07, /* nopr %r7 */ | |
1257 | 0xa7, 0x15, 0x00, 0x0a, /* bras %r1, .Lend */ | |
1258 | 0, 0, 0, 0, /* tpaddr */ | |
1259 | 0, 0, 0, 0, /* tpoint */ | |
1260 | 0, 0, 0, 0, /* collector */ | |
1261 | 0, 0, 0, 0, /* lockaddr */ | |
1262 | /* .Lend: */ | |
1263 | }; | |
1264 | /* Find the proper start place in buf, so that literals will be | |
1265 | aligned. */ | |
1266 | int bufpos = (buildaddr + 2) & 3; | |
1267 | /* First literal will be saved as the PSWA, make sure it has the high bit | |
1268 | set. */ | |
1269 | literals[0] |= 0x80000000; | |
1270 | /* Stuff the literals into the buffer. */ | |
1271 | for (i = 0; i < 4; i++) { | |
1272 | uint32_t lit = literals[i]; | |
1273 | memcpy (&buf[sizeof buf - 16 + i * 4], &lit, 4); | |
1274 | } | |
1275 | append_insns (&buildaddr, sizeof buf - bufpos, buf + bufpos); | |
1276 | append_insns (&buildaddr, sizeof s390_ft_main_31, s390_ft_main_31); | |
1277 | } | |
1278 | ||
1279 | /* Restore FRs or VRs. */ | |
1280 | if (has_vx) | |
1281 | append_insns (&buildaddr, sizeof s390_ft_exit_vr, s390_ft_exit_vr); | |
1282 | else | |
1283 | append_insns (&buildaddr, sizeof s390_ft_exit_fr, s390_ft_exit_fr); | |
1284 | ||
1285 | /* Restore misc registers. */ | |
1286 | append_insns (&buildaddr, sizeof s390_ft_exit_misc, s390_ft_exit_misc); | |
1287 | ||
1288 | /* Restore the GPRs. */ | |
1289 | if (is_zarch) | |
1290 | append_insns (&buildaddr, sizeof s390_ft_exit_gpr_zarch, | |
1291 | s390_ft_exit_gpr_zarch); | |
1292 | else | |
1293 | append_insns (&buildaddr, sizeof s390_ft_exit_gpr_esa, | |
1294 | s390_ft_exit_gpr_esa); | |
1295 | ||
1296 | /* Now, adjust the original instruction to execute in the jump | |
1297 | pad. */ | |
1298 | *adjusted_insn_addr = buildaddr; | |
1299 | if (s390_relocate_instruction (&buildaddr, tpaddr, is_64)) | |
1300 | { | |
1301 | sprintf (err, "E.Could not relocate instruction for tracepoint."); | |
1302 | return 1; | |
1303 | } | |
1304 | *adjusted_insn_addr_end = buildaddr; | |
1305 | ||
1306 | /* Finally, write a jump back to the program. */ | |
1307 | ||
1308 | loffset = (tpaddr + orig_size) - buildaddr; | |
1309 | loffset >>= 1; | |
1310 | offset = loffset; | |
1311 | if (is_64 && offset != loffset) | |
1312 | { | |
1313 | sprintf (err, | |
1314 | "E.Jump back from jump pad too far from tracepoint " | |
1315 | "(offset 0x%" PRIx64 " > int33).", loffset); | |
1316 | return 1; | |
1317 | } | |
1318 | memcpy (jbuf + 2, &offset, 4); | |
1319 | append_insns (&buildaddr, sizeof jbuf, jbuf); | |
1320 | ||
1321 | /* The jump pad is now built. Wire in a jump to our jump pad. This | |
1322 | is always done last (by our caller actually), so that we can | |
1323 | install fast tracepoints with threads running. This relies on | |
1324 | the agent's atomic write support. */ | |
1325 | loffset = *jump_entry - tpaddr; | |
1326 | loffset >>= 1; | |
1327 | offset = loffset; | |
1328 | if (is_64 && offset != loffset) | |
1329 | { | |
1330 | sprintf (err, | |
1331 | "E.Jump back from jump pad too far from tracepoint " | |
1332 | "(offset 0x%" PRIx64 " > int33).", loffset); | |
1333 | return 1; | |
1334 | } | |
1335 | memcpy (jbuf + 2, &offset, 4); | |
1336 | memcpy (jjump_pad_insn, jbuf, sizeof jbuf); | |
1337 | *jjump_pad_insn_size = sizeof jbuf; | |
1338 | ||
1339 | /* Return the end address of our pad. */ | |
1340 | *jump_entry = buildaddr; | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | /* Implementation of linux_target_ops method | |
1346 | "get_min_fast_tracepoint_insn_len". */ | |
1347 | ||
1348 | static int | |
1349 | s390_get_min_fast_tracepoint_insn_len (void) | |
1350 | { | |
1351 | /* We only support using 6-byte jumps to reach the tracepoint code. | |
1352 | If the tracepoint buffer were allocated sufficiently close (64kiB) | |
1353 | to the executable code, and the traced instruction itself was close | |
1354 | enough to the beginning, we could use 4-byte jumps, but this doesn't | |
1355 | seem to be worth the effort. */ | |
1356 | return 6; | |
1357 | } | |
1358 | ||
1359 | /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */ | |
1360 | ||
1361 | static int | |
1362 | s390_get_ipa_tdesc_idx (void) | |
1363 | { | |
1364 | struct regcache *regcache = get_thread_regcache (current_thread, 0); | |
1365 | const struct target_desc *tdesc = regcache->tdesc; | |
1366 | ||
1367 | #ifdef __s390x__ | |
1368 | if (tdesc == tdesc_s390x_linux64) | |
1369 | return S390_TDESC_64; | |
1370 | if (tdesc == tdesc_s390x_linux64v1) | |
1371 | return S390_TDESC_64V1; | |
1372 | if (tdesc == tdesc_s390x_linux64v2) | |
1373 | return S390_TDESC_64V2; | |
1374 | if (tdesc == tdesc_s390x_te_linux64) | |
1375 | return S390_TDESC_TE; | |
1376 | if (tdesc == tdesc_s390x_vx_linux64) | |
1377 | return S390_TDESC_VX; | |
1378 | if (tdesc == tdesc_s390x_tevx_linux64) | |
1379 | return S390_TDESC_TEVX; | |
1380 | #endif | |
1381 | ||
1382 | if (tdesc == tdesc_s390_linux32) | |
1383 | return S390_TDESC_32; | |
1384 | if (tdesc == tdesc_s390_linux32v1) | |
1385 | return S390_TDESC_32V1; | |
1386 | if (tdesc == tdesc_s390_linux32v2) | |
1387 | return S390_TDESC_32V2; | |
1388 | if (tdesc == tdesc_s390_linux64) | |
1389 | return S390_TDESC_64; | |
1390 | if (tdesc == tdesc_s390_linux64v1) | |
1391 | return S390_TDESC_64V1; | |
1392 | if (tdesc == tdesc_s390_linux64v2) | |
1393 | return S390_TDESC_64V2; | |
1394 | if (tdesc == tdesc_s390_te_linux64) | |
1395 | return S390_TDESC_TE; | |
1396 | if (tdesc == tdesc_s390_vx_linux64) | |
1397 | return S390_TDESC_VX; | |
1398 | if (tdesc == tdesc_s390_tevx_linux64) | |
1399 | return S390_TDESC_TEVX; | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
2ec06d2e | 1404 | struct linux_target_ops the_low_target = { |
d61ddec4 | 1405 | s390_arch_setup, |
3aee8918 | 1406 | s390_regs_info, |
2ec06d2e DJ |
1407 | s390_cannot_fetch_register, |
1408 | s390_cannot_store_register, | |
c14dfd32 | 1409 | NULL, /* fetch_register */ |
b0ded00b UW |
1410 | s390_get_pc, |
1411 | s390_set_pc, | |
dd373349 AT |
1412 | NULL, /* breakpoint_kind_from_pc */ |
1413 | s390_sw_breakpoint_from_kind, | |
b0ded00b UW |
1414 | NULL, |
1415 | s390_breakpoint_len, | |
1416 | s390_breakpoint_at, | |
b00b61e1 | 1417 | s390_supports_z_point_type, |
ee1a7ae4 UW |
1418 | NULL, |
1419 | NULL, | |
1420 | NULL, | |
1421 | NULL, | |
1422 | s390_collect_ptrace_register, | |
1423 | s390_supply_ptrace_register, | |
7d00775e AT |
1424 | NULL, /* siginfo_fixup */ |
1425 | NULL, /* new_process */ | |
1426 | NULL, /* new_thread */ | |
1427 | NULL, /* new_fork */ | |
1428 | NULL, /* prepare_to_resume */ | |
1429 | NULL, /* process_qsupported */ | |
a4105d04 | 1430 | s390_supports_tracepoints, |
abd9baf9 MK |
1431 | s390_get_thread_area, |
1432 | s390_install_fast_tracepoint_jump_pad, | |
7d00775e | 1433 | NULL, /* emit_ops */ |
abd9baf9 | 1434 | s390_get_min_fast_tracepoint_insn_len, |
7d00775e AT |
1435 | NULL, /* supports_range_stepping */ |
1436 | NULL, /* breakpoint_kind_from_current_state */ | |
1437 | s390_supports_hardware_single_step, | |
abd9baf9 MK |
1438 | NULL, /* get_syscall_trapinfo */ |
1439 | s390_get_ipa_tdesc_idx, | |
2ec06d2e | 1440 | }; |
3aee8918 PA |
1441 | |
1442 | void | |
1443 | initialize_low_arch (void) | |
1444 | { | |
1445 | /* Initialize the Linux target descriptions. */ | |
1446 | ||
1447 | init_registers_s390_linux32 (); | |
1448 | init_registers_s390_linux32v1 (); | |
1449 | init_registers_s390_linux32v2 (); | |
1450 | init_registers_s390_linux64 (); | |
1451 | init_registers_s390_linux64v1 (); | |
1452 | init_registers_s390_linux64v2 (); | |
4ac33720 | 1453 | init_registers_s390_te_linux64 (); |
bf2d68ab AA |
1454 | init_registers_s390_vx_linux64 (); |
1455 | init_registers_s390_tevx_linux64 (); | |
abd9baf9 | 1456 | #ifdef __s390x__ |
3aee8918 PA |
1457 | init_registers_s390x_linux64 (); |
1458 | init_registers_s390x_linux64v1 (); | |
1459 | init_registers_s390x_linux64v2 (); | |
4ac33720 | 1460 | init_registers_s390x_te_linux64 (); |
bf2d68ab AA |
1461 | init_registers_s390x_vx_linux64 (); |
1462 | init_registers_s390x_tevx_linux64 (); | |
abd9baf9 | 1463 | #endif |
3aee8918 PA |
1464 | |
1465 | initialize_regsets_info (&s390_regsets_info); | |
3aee8918 | 1466 | initialize_regsets_info (&s390_regsets_info_3264); |
3aee8918 | 1467 | } |