Fix 17492, ld segfault with --oformat=binary
[deliverable/binutils-gdb.git] / gdb / i386-darwin-nat.c
CommitLineData
a80b95ba 1/* Darwin support for GDB, the GNU debugger.
ecd75fc8 2 Copyright (C) 1997-2014 Free Software Foundation, Inc.
a80b95ba
TG
3
4 Contributed by Apple Computer, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21#include "defs.h"
22#include "frame.h"
23#include "inferior.h"
24#include "target.h"
25#include "symfile.h"
26#include "symtab.h"
27#include "objfiles.h"
28#include "gdbcmd.h"
29#include "regcache.h"
a80b95ba 30#include "i386-tdep.h"
a80b95ba
TG
31#include "i387-tdep.h"
32#include "gdbarch.h"
33#include "arch-utils.h"
acdb24a9 34#include "gdbcore.h"
a80b95ba 35
df7e5265 36#include "x86-nat.h"
a80b95ba
TG
37#include "darwin-nat.h"
38#include "i386-darwin-tdep.h"
39
5cd226f2
TG
40#ifdef BFD64
41#include "amd64-nat.h"
46187dff 42#include "amd64-tdep.h"
5cd226f2
TG
43#include "amd64-darwin-tdep.h"
44#endif
45
a80b95ba
TG
46/* Read register values from the inferior process.
47 If REGNO is -1, do this for all registers.
48 Otherwise, REGNO specifies which register (so we can save time). */
49static void
28439f5e
PA
50i386_darwin_fetch_inferior_registers (struct target_ops *ops,
51 struct regcache *regcache, int regno)
a80b95ba
TG
52{
53 thread_t current_thread = ptid_get_tid (inferior_ptid);
54 int fetched = 0;
55 struct gdbarch *gdbarch = get_regcache_arch (regcache);
56
5cd226f2 57#ifdef BFD64
a80b95ba
TG
58 if (gdbarch_ptr_bit (gdbarch) == 64)
59 {
60 if (regno == -1 || amd64_native_gregset_supplies_p (gdbarch, regno))
61 {
62 x86_thread_state_t gp_regs;
63 unsigned int gp_count = x86_THREAD_STATE_COUNT;
64 kern_return_t ret;
65
66 ret = thread_get_state
67 (current_thread, x86_THREAD_STATE, (thread_state_t) & gp_regs,
68 &gp_count);
69 if (ret != KERN_SUCCESS)
70 {
1777feb0 71 printf_unfiltered (_("Error calling thread_get_state for "
17092398 72 "GP registers for thread 0x%lx\n"),
016b7430 73 (unsigned long) current_thread);
a80b95ba
TG
74 MACH_CHECK_ERROR (ret);
75 }
76 amd64_supply_native_gregset (regcache, &gp_regs.uts, -1);
77 fetched++;
78 }
79
80 if (regno == -1 || !amd64_native_gregset_supplies_p (gdbarch, regno))
81 {
82 x86_float_state_t fp_regs;
83 unsigned int fp_count = x86_FLOAT_STATE_COUNT;
84 kern_return_t ret;
85
86 ret = thread_get_state
87 (current_thread, x86_FLOAT_STATE, (thread_state_t) & fp_regs,
88 &fp_count);
89 if (ret != KERN_SUCCESS)
90 {
1777feb0 91 printf_unfiltered (_("Error calling thread_get_state for "
17092398 92 "float registers for thread 0x%lx\n"),
016b7430 93 (unsigned long) current_thread);
a80b95ba
TG
94 MACH_CHECK_ERROR (ret);
95 }
46187dff 96 amd64_supply_fxsave (regcache, -1, &fp_regs.ufs.fs64.__fpu_fcw);
a80b95ba
TG
97 fetched++;
98 }
99 }
100 else
5cd226f2 101#endif
a80b95ba
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102 {
103 if (regno == -1 || regno < I386_NUM_GREGS)
104 {
cf9bb588
TG
105 x86_thread_state32_t gp_regs;
106 unsigned int gp_count = x86_THREAD_STATE32_COUNT;
a80b95ba
TG
107 kern_return_t ret;
108 int i;
109
110 ret = thread_get_state
cf9bb588 111 (current_thread, x86_THREAD_STATE32, (thread_state_t) &gp_regs,
a80b95ba
TG
112 &gp_count);
113 if (ret != KERN_SUCCESS)
114 {
1777feb0 115 printf_unfiltered (_("Error calling thread_get_state for "
17092398
TG
116 "GP registers for thread 0x%lx\n"),
117 (unsigned long) current_thread);
a80b95ba
TG
118 MACH_CHECK_ERROR (ret);
119 }
120 for (i = 0; i < I386_NUM_GREGS; i++)
121 regcache_raw_supply
122 (regcache, i,
123 (char *)&gp_regs + i386_darwin_thread_state_reg_offset[i]);
124
125 fetched++;
126 }
127
128 if (regno == -1
129 || (regno >= I386_ST0_REGNUM && regno < I386_SSE_NUM_REGS))
130 {
cf9bb588
TG
131 x86_float_state32_t fp_regs;
132 unsigned int fp_count = x86_FLOAT_STATE32_COUNT;
a80b95ba
TG
133 kern_return_t ret;
134
135 ret = thread_get_state
cf9bb588 136 (current_thread, x86_FLOAT_STATE32, (thread_state_t) &fp_regs,
a80b95ba
TG
137 &fp_count);
138 if (ret != KERN_SUCCESS)
139 {
1777feb0 140 printf_unfiltered (_("Error calling thread_get_state for "
17092398
TG
141 "float registers for thread 0x%lx\n"),
142 (unsigned long) current_thread);
a80b95ba
TG
143 MACH_CHECK_ERROR (ret);
144 }
145 i387_supply_fxsave (regcache, -1, &fp_regs.__fpu_fcw);
146 fetched++;
147 }
148 }
149
150 if (! fetched)
151 {
152 warning (_("unknown register %d"), regno);
153 regcache_raw_supply (regcache, regno, NULL);
154 }
155}
156
157/* Store our register values back into the inferior.
158 If REGNO is -1, do this for all registers.
159 Otherwise, REGNO specifies which register (so we can save time). */
160
161static void
28439f5e
PA
162i386_darwin_store_inferior_registers (struct target_ops *ops,
163 struct regcache *regcache, int regno)
a80b95ba
TG
164{
165 thread_t current_thread = ptid_get_tid (inferior_ptid);
166 struct gdbarch *gdbarch = get_regcache_arch (regcache);
167
5cd226f2 168#ifdef BFD64
a80b95ba
TG
169 if (gdbarch_ptr_bit (gdbarch) == 64)
170 {
171 if (regno == -1 || amd64_native_gregset_supplies_p (gdbarch, regno))
172 {
173 x86_thread_state_t gp_regs;
174 kern_return_t ret;
175 unsigned int gp_count = x86_THREAD_STATE_COUNT;
176
177 ret = thread_get_state
178 (current_thread, x86_THREAD_STATE, (thread_state_t) &gp_regs,
179 &gp_count);
180 MACH_CHECK_ERROR (ret);
181 gdb_assert (gp_regs.tsh.flavor == x86_THREAD_STATE64);
182 gdb_assert (gp_regs.tsh.count == x86_THREAD_STATE64_COUNT);
183
184 amd64_collect_native_gregset (regcache, &gp_regs.uts, regno);
185
186 ret = thread_set_state (current_thread, x86_THREAD_STATE,
187 (thread_state_t) &gp_regs,
188 x86_THREAD_STATE_COUNT);
189 MACH_CHECK_ERROR (ret);
190 }
191
192 if (regno == -1 || !amd64_native_gregset_supplies_p (gdbarch, regno))
193 {
194 x86_float_state_t fp_regs;
195 kern_return_t ret;
196 unsigned int fp_count = x86_FLOAT_STATE_COUNT;
197
198 ret = thread_get_state
199 (current_thread, x86_FLOAT_STATE, (thread_state_t) & fp_regs,
200 &fp_count);
201 MACH_CHECK_ERROR (ret);
202 gdb_assert (fp_regs.fsh.flavor == x86_FLOAT_STATE64);
203 gdb_assert (fp_regs.fsh.count == x86_FLOAT_STATE64_COUNT);
204
46187dff 205 amd64_collect_fxsave (regcache, regno, &fp_regs.ufs.fs64.__fpu_fcw);
a80b95ba
TG
206
207 ret = thread_set_state (current_thread, x86_FLOAT_STATE,
208 (thread_state_t) & fp_regs,
209 x86_FLOAT_STATE_COUNT);
210 MACH_CHECK_ERROR (ret);
211 }
212 }
213 else
5cd226f2 214#endif
a80b95ba
TG
215 {
216 if (regno == -1 || regno < I386_NUM_GREGS)
217 {
cf9bb588 218 x86_thread_state32_t gp_regs;
a80b95ba 219 kern_return_t ret;
cf9bb588 220 unsigned int gp_count = x86_THREAD_STATE32_COUNT;
a80b95ba
TG
221 int i;
222
223 ret = thread_get_state
cf9bb588 224 (current_thread, x86_THREAD_STATE32, (thread_state_t) &gp_regs,
a80b95ba
TG
225 &gp_count);
226 MACH_CHECK_ERROR (ret);
227
228 for (i = 0; i < I386_NUM_GREGS; i++)
229 if (regno == -1 || regno == i)
230 regcache_raw_collect
231 (regcache, i,
232 (char *)&gp_regs + i386_darwin_thread_state_reg_offset[i]);
233
cf9bb588
TG
234 ret = thread_set_state (current_thread, x86_THREAD_STATE32,
235 (thread_state_t) &gp_regs,
236 x86_THREAD_STATE32_COUNT);
a80b95ba
TG
237 MACH_CHECK_ERROR (ret);
238 }
239
240 if (regno == -1
241 || (regno >= I386_ST0_REGNUM && regno < I386_SSE_NUM_REGS))
242 {
cf9bb588
TG
243 x86_float_state32_t fp_regs;
244 unsigned int fp_count = x86_FLOAT_STATE32_COUNT;
a80b95ba
TG
245 kern_return_t ret;
246
247 ret = thread_get_state
cf9bb588 248 (current_thread, x86_FLOAT_STATE32, (thread_state_t) & fp_regs,
a80b95ba
TG
249 &fp_count);
250 MACH_CHECK_ERROR (ret);
251
252 i387_collect_fxsave (regcache, regno, &fp_regs.__fpu_fcw);
253
cf9bb588
TG
254 ret = thread_set_state (current_thread, x86_FLOAT_STATE32,
255 (thread_state_t) &fp_regs,
256 x86_FLOAT_STATE32_COUNT);
a80b95ba
TG
257 MACH_CHECK_ERROR (ret);
258 }
259 }
260}
261
a80b95ba
TG
262/* Support for debug registers, boosted mostly from i386-linux-nat.c. */
263
a80b95ba 264static void
b1328b1b 265i386_darwin_dr_set (int regnum, CORE_ADDR value)
a80b95ba
TG
266{
267 int current_pid;
268 thread_t current_thread;
269 x86_debug_state_t dr_regs;
270 kern_return_t ret;
61d82a0d 271 unsigned int dr_count;
a80b95ba
TG
272
273 gdb_assert (regnum >= 0 && regnum <= DR_CONTROL);
274
275 current_thread = ptid_get_tid (inferior_ptid);
276
61d82a0d
TG
277 dr_regs.dsh.flavor = x86_DEBUG_STATE;
278 dr_regs.dsh.count = x86_DEBUG_STATE_COUNT;
a80b95ba 279 dr_count = x86_DEBUG_STATE_COUNT;
61d82a0d 280 ret = thread_get_state (current_thread, x86_DEBUG_STATE,
a80b95ba 281 (thread_state_t) &dr_regs, &dr_count);
b1328b1b 282 MACH_CHECK_ERROR (ret);
a80b95ba 283
61d82a0d 284 switch (dr_regs.dsh.flavor)
a80b95ba 285 {
61d82a0d
TG
286 case x86_DEBUG_STATE32:
287 switch (regnum)
288 {
289 case 0:
290 dr_regs.uds.ds32.__dr0 = value;
291 break;
292 case 1:
293 dr_regs.uds.ds32.__dr1 = value;
294 break;
295 case 2:
296 dr_regs.uds.ds32.__dr2 = value;
297 break;
298 case 3:
299 dr_regs.uds.ds32.__dr3 = value;
300 break;
301 case 4:
302 dr_regs.uds.ds32.__dr4 = value;
303 break;
304 case 5:
305 dr_regs.uds.ds32.__dr5 = value;
306 break;
307 case 6:
308 dr_regs.uds.ds32.__dr6 = value;
309 break;
310 case 7:
311 dr_regs.uds.ds32.__dr7 = value;
312 break;
313 }
314 break;
315#ifdef BFD64
316 case x86_DEBUG_STATE64:
317 switch (regnum)
318 {
319 case 0:
320 dr_regs.uds.ds64.__dr0 = value;
321 break;
322 case 1:
323 dr_regs.uds.ds64.__dr1 = value;
324 break;
325 case 2:
326 dr_regs.uds.ds64.__dr2 = value;
327 break;
328 case 3:
329 dr_regs.uds.ds64.__dr3 = value;
330 break;
331 case 4:
332 dr_regs.uds.ds64.__dr4 = value;
333 break;
334 case 5:
335 dr_regs.uds.ds64.__dr5 = value;
336 break;
337 case 6:
338 dr_regs.uds.ds64.__dr6 = value;
339 break;
340 case 7:
341 dr_regs.uds.ds64.__dr7 = value;
342 break;
343 }
344 break;
345#endif
a80b95ba
TG
346 }
347
b1328b1b
TG
348 ret = thread_set_state (current_thread, dr_regs.dsh.flavor,
349 (thread_state_t) &dr_regs.uds, dr_count);
a80b95ba 350
b1328b1b 351 MACH_CHECK_ERROR (ret);
a80b95ba
TG
352}
353
b1328b1b 354static CORE_ADDR
a80b95ba
TG
355i386_darwin_dr_get (int regnum)
356{
357 thread_t current_thread;
358 x86_debug_state_t dr_regs;
359 kern_return_t ret;
61d82a0d 360 unsigned int dr_count;
a80b95ba
TG
361
362 gdb_assert (regnum >= 0 && regnum <= DR_CONTROL);
363
364 current_thread = ptid_get_tid (inferior_ptid);
365
61d82a0d
TG
366 dr_regs.dsh.flavor = x86_DEBUG_STATE;
367 dr_regs.dsh.count = x86_DEBUG_STATE_COUNT;
a80b95ba 368 dr_count = x86_DEBUG_STATE_COUNT;
61d82a0d 369 ret = thread_get_state (current_thread, x86_DEBUG_STATE,
a80b95ba 370 (thread_state_t) &dr_regs, &dr_count);
b1328b1b 371 MACH_CHECK_ERROR (ret);
a80b95ba 372
61d82a0d 373 switch (dr_regs.dsh.flavor)
a80b95ba 374 {
61d82a0d
TG
375 case x86_DEBUG_STATE32:
376 switch (regnum)
377 {
378 case 0:
379 return dr_regs.uds.ds32.__dr0;
380 case 1:
381 return dr_regs.uds.ds32.__dr1;
382 case 2:
383 return dr_regs.uds.ds32.__dr2;
384 case 3:
385 return dr_regs.uds.ds32.__dr3;
386 case 4:
387 return dr_regs.uds.ds32.__dr4;
388 case 5:
389 return dr_regs.uds.ds32.__dr5;
390 case 6:
391 return dr_regs.uds.ds32.__dr6;
392 case 7:
393 return dr_regs.uds.ds32.__dr7;
394 default:
395 return -1;
396 }
397 break;
398#ifdef BFD64
399 case x86_DEBUG_STATE64:
400 switch (regnum)
401 {
402 case 0:
403 return dr_regs.uds.ds64.__dr0;
404 case 1:
405 return dr_regs.uds.ds64.__dr1;
406 case 2:
407 return dr_regs.uds.ds64.__dr2;
408 case 3:
409 return dr_regs.uds.ds64.__dr3;
410 case 4:
411 return dr_regs.uds.ds64.__dr4;
412 case 5:
413 return dr_regs.uds.ds64.__dr5;
414 case 6:
415 return dr_regs.uds.ds64.__dr6;
416 case 7:
417 return dr_regs.uds.ds64.__dr7;
418 default:
419 return -1;
420 }
421 break;
422#endif
423 default:
424 return -1;
a80b95ba
TG
425 }
426}
427
61d82a0d 428static void
a80b95ba
TG
429i386_darwin_dr_set_control (unsigned long control)
430{
431 i386_darwin_dr_set (DR_CONTROL, control);
432}
433
61d82a0d 434static void
a80b95ba
TG
435i386_darwin_dr_set_addr (int regnum, CORE_ADDR addr)
436{
437 gdb_assert (regnum >= 0 && regnum <= DR_LASTADDR - DR_FIRSTADDR);
438
439 i386_darwin_dr_set (DR_FIRSTADDR + regnum, addr);
440}
441
61d82a0d 442static CORE_ADDR
7b50312a 443i386_darwin_dr_get_addr (int regnum)
a80b95ba 444{
7b50312a 445 return i386_darwin_dr_get (regnum);
a80b95ba
TG
446}
447
61d82a0d 448static unsigned long
a80b95ba
TG
449i386_darwin_dr_get_status (void)
450{
451 return i386_darwin_dr_get (DR_STATUS);
452}
453
61d82a0d 454static unsigned long
7b50312a
PA
455i386_darwin_dr_get_control (void)
456{
457 return i386_darwin_dr_get (DR_CONTROL);
458}
459
a80b95ba
TG
460void
461darwin_check_osabi (darwin_inferior *inf, thread_t thread)
462{
f5656ead 463 if (gdbarch_osabi (target_gdbarch ()) == GDB_OSABI_UNKNOWN)
a80b95ba
TG
464 {
465 /* Attaching to a process. Let's figure out what kind it is. */
466 x86_thread_state_t gp_regs;
467 struct gdbarch_info info;
468 unsigned int gp_count = x86_THREAD_STATE_COUNT;
469 kern_return_t ret;
470
471 ret = thread_get_state (thread, x86_THREAD_STATE,
472 (thread_state_t) &gp_regs, &gp_count);
473 if (ret != KERN_SUCCESS)
474 {
475 MACH_CHECK_ERROR (ret);
476 return;
477 }
478
479 gdbarch_info_init (&info);
480 gdbarch_info_fill (&info);
f5656ead 481 info.byte_order = gdbarch_byte_order (target_gdbarch ());
a80b95ba
TG
482 info.osabi = GDB_OSABI_DARWIN;
483 if (gp_regs.tsh.flavor == x86_THREAD_STATE64)
484 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_i386,
485 bfd_mach_x86_64);
486 else
61d82a0d 487 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_i386,
a80b95ba
TG
488 bfd_mach_i386_i386);
489 gdbarch_update_p (info);
490 }
491}
492
493#define X86_EFLAGS_T 0x100UL
494
acdb24a9
TG
495/* Returning from a signal trampoline is done by calling a
496 special system call (sigreturn). This system call
497 restores the registers that were saved when the signal was
498 raised, including %eflags/%rflags. That means that single-stepping
499 won't work. Instead, we'll have to modify the signal context
500 that's about to be restored, and set the trace flag there. */
501
502static int
503i386_darwin_sstep_at_sigreturn (x86_thread_state_t *regs)
504{
f5656ead 505 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
acdb24a9
TG
506 static const gdb_byte darwin_syscall[] = { 0xcd, 0x80 }; /* int 0x80 */
507 gdb_byte buf[sizeof (darwin_syscall)];
508
509 /* Check if PC is at a sigreturn system call. */
510 if (target_read_memory (regs->uts.ts32.__eip, buf, sizeof (buf)) == 0
511 && memcmp (buf, darwin_syscall, sizeof (darwin_syscall)) == 0
512 && regs->uts.ts32.__eax == 0xb8 /* SYS_sigreturn */)
513 {
514 ULONGEST uctx_addr;
515 ULONGEST mctx_addr;
516 ULONGEST flags_addr;
517 unsigned int eflags;
518
e17a4113
UW
519 uctx_addr = read_memory_unsigned_integer
520 (regs->uts.ts32.__esp + 4, 4, byte_order);
521 mctx_addr = read_memory_unsigned_integer
522 (uctx_addr + 28, 4, byte_order);
acdb24a9
TG
523
524 flags_addr = mctx_addr + 12 + 9 * 4;
525 read_memory (flags_addr, (gdb_byte *) &eflags, 4);
526 eflags |= X86_EFLAGS_T;
527 write_memory (flags_addr, (gdb_byte *) &eflags, 4);
528
529 return 1;
530 }
531 return 0;
532}
533
5cd226f2 534#ifdef BFD64
acdb24a9
TG
535static int
536amd64_darwin_sstep_at_sigreturn (x86_thread_state_t *regs)
537{
f5656ead 538 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
acdb24a9
TG
539 static const gdb_byte darwin_syscall[] = { 0x0f, 0x05 }; /* syscall */
540 gdb_byte buf[sizeof (darwin_syscall)];
541
542 /* Check if PC is at a sigreturn system call. */
543 if (target_read_memory (regs->uts.ts64.__rip, buf, sizeof (buf)) == 0
544 && memcmp (buf, darwin_syscall, sizeof (darwin_syscall)) == 0
545 && (regs->uts.ts64.__rax & 0xffffffff) == 0x20000b8 /* SYS_sigreturn */)
546 {
547 ULONGEST mctx_addr;
548 ULONGEST flags_addr;
549 unsigned int rflags;
550
e17a4113
UW
551 mctx_addr = read_memory_unsigned_integer
552 (regs->uts.ts64.__rdi + 48, 8, byte_order);
acdb24a9
TG
553 flags_addr = mctx_addr + 16 + 17 * 8;
554
555 /* AMD64 is little endian. */
556 read_memory (flags_addr, (gdb_byte *) &rflags, 4);
557 rflags |= X86_EFLAGS_T;
558 write_memory (flags_addr, (gdb_byte *) &rflags, 4);
559
560 return 1;
561 }
562 return 0;
563}
5cd226f2 564#endif
acdb24a9 565
a80b95ba
TG
566void
567darwin_set_sstep (thread_t thread, int enable)
568{
569 x86_thread_state_t regs;
570 unsigned int count = x86_THREAD_STATE_COUNT;
571 kern_return_t kret;
572
573 kret = thread_get_state (thread, x86_THREAD_STATE,
574 (thread_state_t) &regs, &count);
575 if (kret != KERN_SUCCESS)
576 {
577 printf_unfiltered (_("darwin_set_sstep: error %x, thread=%x\n"),
578 kret, thread);
579 return;
580 }
acdb24a9 581
a80b95ba
TG
582 switch (regs.tsh.flavor)
583 {
584 case x86_THREAD_STATE32:
585 {
586 __uint32_t bit = enable ? X86_EFLAGS_T : 0;
b1328b1b 587
acdb24a9
TG
588 if (enable && i386_darwin_sstep_at_sigreturn (&regs))
589 return;
a80b95ba
TG
590 if ((regs.uts.ts32.__eflags & X86_EFLAGS_T) == bit)
591 return;
1777feb0
MS
592 regs.uts.ts32.__eflags
593 = (regs.uts.ts32.__eflags & ~X86_EFLAGS_T) | bit;
b1328b1b 594 kret = thread_set_state (thread, x86_THREAD_STATE,
a80b95ba
TG
595 (thread_state_t) &regs, count);
596 MACH_CHECK_ERROR (kret);
597 }
598 break;
5cd226f2 599#ifdef BFD64
a80b95ba
TG
600 case x86_THREAD_STATE64:
601 {
602 __uint64_t bit = enable ? X86_EFLAGS_T : 0;
603
acdb24a9
TG
604 if (enable && amd64_darwin_sstep_at_sigreturn (&regs))
605 return;
a80b95ba
TG
606 if ((regs.uts.ts64.__rflags & X86_EFLAGS_T) == bit)
607 return;
1777feb0
MS
608 regs.uts.ts64.__rflags
609 = (regs.uts.ts64.__rflags & ~X86_EFLAGS_T) | bit;
b1328b1b 610 kret = thread_set_state (thread, x86_THREAD_STATE,
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611 (thread_state_t) &regs, count);
612 MACH_CHECK_ERROR (kret);
613 }
614 break;
5cd226f2 615#endif
a80b95ba 616 default:
b37520b6 617 error (_("darwin_set_sstep: unknown flavour: %d"), regs.tsh.flavor);
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618 }
619}
620
621void
622darwin_complete_target (struct target_ops *target)
623{
5cd226f2 624#ifdef BFD64
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625 amd64_native_gregset64_reg_offset = amd64_darwin_thread_state_reg_offset;
626 amd64_native_gregset64_num_regs = amd64_darwin_thread_state_num_regs;
627 amd64_native_gregset32_reg_offset = i386_darwin_thread_state_reg_offset;
628 amd64_native_gregset32_num_regs = i386_darwin_thread_state_num_regs;
5cd226f2 629#endif
a80b95ba 630
df7e5265 631 x86_use_watchpoints (target);
61d82a0d 632
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GB
633 x86_dr_low.set_control = i386_darwin_dr_set_control;
634 x86_dr_low.set_addr = i386_darwin_dr_set_addr;
635 x86_dr_low.get_addr = i386_darwin_dr_get_addr;
636 x86_dr_low.get_status = i386_darwin_dr_get_status;
637 x86_dr_low.get_control = i386_darwin_dr_get_control;
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638
639 /* Let's assume that the kernel is 64 bits iff the executable is. */
640#ifdef __x86_64__
df7e5265 641 x86_set_debug_register_length (8);
61d82a0d 642#else
df7e5265 643 x86_set_debug_register_length (4);
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644#endif
645
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646 target->to_fetch_registers = i386_darwin_fetch_inferior_registers;
647 target->to_store_registers = i386_darwin_store_inferior_registers;
648}
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