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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
ecd75fc8 | 3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. |
52b98211 EZ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 EZ |
19 | |
20 | #include "defs.h" | |
0baeab03 | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "breakpoint.h" |
23 | #include "command.h" | |
24 | #include "gdbcmd.h" | |
c03374d5 | 25 | #include "target.h" |
9bb9e8ad | 26 | #include "gdb_assert.h" |
4403d8e9 | 27 | #include "inferior.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
9bb9e8ad PM |
40 | struct i386_dr_low_type i386_dr_low; |
41 | ||
52b98211 | 42 | |
e906b9a3 | 43 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 44 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 45 | |
52b98211 EZ |
46 | /* DR7 Debug Control register fields. */ |
47 | ||
48 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
49 | #define DR_CONTROL_SHIFT 16 | |
50 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
51 | #define DR_CONTROL_SIZE 4 | |
52 | ||
53 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
54 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
55 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
56 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
57 | |
58 | /* This is here for completeness. No platform supports this | |
7fa2737c | 59 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
60 | CR4 register needs to be set to support this. */ |
61 | #ifndef DR_RW_IORW | |
7fa2737c | 62 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
63 | #endif |
64 | ||
65 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
66 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
67 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
68 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
69 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
70 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
71 | |
72 | /* Local and Global Enable flags in DR7. | |
73 | ||
74 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
75 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
76 | clears this flag on every task switch. When the Global Enable flag |
77 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
78 | processor never clears this flag. | |
52b98211 EZ |
79 | |
80 | Currently, all watchpoint are locally enabled. If you need to | |
81 | enable them globally, read the comment which pertains to this in | |
82 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
83 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
84 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
85 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
86 | |
87 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
88 | flags). These are only required on i386, to allow detection of the | |
89 | exact instruction which caused a watchpoint to break; i486 and | |
90 | later processors do that automatically. We set these flags for | |
7fa2737c | 91 | backwards compatibility. */ |
52b98211 | 92 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 93 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
94 | |
95 | /* Fields reserved by Intel. This includes the GD (General Detect | |
96 | Enable) flag, which causes a debug exception to be generated when a | |
97 | MOV instruction accesses one of the debug registers. | |
98 | ||
99 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
100 | #define DR_CONTROL_RESERVED (0xFC00) | |
101 | ||
102 | /* Auxiliary helper macros. */ | |
103 | ||
104 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 105 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
106 | |
107 | /* The I'th debug register is vacant if its Local and Global Enable | |
108 | bits are reset in the Debug Control register. */ | |
1ced966e PA |
109 | #define I386_DR_VACANT(state, i) \ |
110 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
52b98211 EZ |
111 | |
112 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
113 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
114 | do { \ | |
115 | (state)->dr_control_mirror |= \ | |
116 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
117 | } while (0) | |
52b98211 EZ |
118 | |
119 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
120 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
121 | do { \ | |
122 | (state)->dr_control_mirror |= \ | |
123 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
124 | } while (0) | |
52b98211 EZ |
125 | |
126 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
127 | #define I386_DR_DISABLE(state, i) \ |
128 | do { \ | |
129 | (state)->dr_control_mirror &= \ | |
130 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
131 | } while (0) | |
52b98211 EZ |
132 | |
133 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 134 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 135 | do { \ |
1ced966e PA |
136 | (state)->dr_control_mirror &= \ |
137 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
138 | (state)->dr_control_mirror |= \ | |
139 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
140 | } while (0) |
141 | ||
142 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
143 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
144 | (((dr7) \ | |
145 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 | 146 | |
a79d3c27 JK |
147 | /* Mask that this I'th watchpoint has triggered. */ |
148 | #define I386_DR_WATCH_MASK(i) (1 << (i)) | |
149 | ||
52b98211 | 150 | /* Did the watchpoint whose address is in the I'th register break? */ |
1ced966e | 151 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
152 | |
153 | /* A macro to loop over all debug registers. */ | |
154 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
155 | ||
26cb8b7c PA |
156 | /* Per-process data. We don't bind this to a per-inferior registry |
157 | because of targets like x86 GNU/Linux that need to keep track of | |
158 | processes that aren't bound to any inferior (e.g., fork children, | |
159 | checkpoints). */ | |
1ced966e | 160 | |
26cb8b7c | 161 | struct i386_process_info |
1ced966e | 162 | { |
26cb8b7c PA |
163 | /* Linked list. */ |
164 | struct i386_process_info *next; | |
1ced966e | 165 | |
26cb8b7c PA |
166 | /* The process identifier. */ |
167 | pid_t pid; | |
4403d8e9 | 168 | |
26cb8b7c | 169 | /* Copy of i386 hardware debug registers. */ |
4403d8e9 JK |
170 | struct i386_debug_reg_state state; |
171 | }; | |
172 | ||
26cb8b7c | 173 | static struct i386_process_info *i386_process_list = NULL; |
d0d8b0c6 | 174 | |
26cb8b7c PA |
175 | /* Find process data for process PID. */ |
176 | ||
177 | static struct i386_process_info * | |
178 | i386_find_process_pid (pid_t pid) | |
d0d8b0c6 | 179 | { |
26cb8b7c PA |
180 | struct i386_process_info *proc; |
181 | ||
182 | for (proc = i386_process_list; proc; proc = proc->next) | |
183 | if (proc->pid == pid) | |
184 | return proc; | |
d0d8b0c6 | 185 | |
26cb8b7c | 186 | return NULL; |
d0d8b0c6 JK |
187 | } |
188 | ||
26cb8b7c PA |
189 | /* Add process data for process PID. Returns newly allocated info |
190 | object. */ | |
4403d8e9 | 191 | |
26cb8b7c PA |
192 | static struct i386_process_info * |
193 | i386_add_process (pid_t pid) | |
4403d8e9 | 194 | { |
26cb8b7c | 195 | struct i386_process_info *proc; |
d0d8b0c6 | 196 | |
26cb8b7c PA |
197 | proc = xcalloc (1, sizeof (*proc)); |
198 | proc->pid = pid; | |
4403d8e9 | 199 | |
26cb8b7c PA |
200 | proc->next = i386_process_list; |
201 | i386_process_list = proc; | |
4403d8e9 | 202 | |
26cb8b7c PA |
203 | return proc; |
204 | } | |
4403d8e9 | 205 | |
26cb8b7c PA |
206 | /* Get data specific info for process PID, creating it if necessary. |
207 | Never returns NULL. */ | |
4403d8e9 | 208 | |
26cb8b7c PA |
209 | static struct i386_process_info * |
210 | i386_process_info_get (pid_t pid) | |
211 | { | |
212 | struct i386_process_info *proc; | |
213 | ||
214 | proc = i386_find_process_pid (pid); | |
215 | if (proc == NULL) | |
216 | proc = i386_add_process (pid); | |
4403d8e9 | 217 | |
26cb8b7c | 218 | return proc; |
4403d8e9 JK |
219 | } |
220 | ||
26cb8b7c | 221 | /* Get debug registers state for process PID. */ |
52b98211 | 222 | |
7b50312a | 223 | struct i386_debug_reg_state * |
26cb8b7c | 224 | i386_debug_reg_state (pid_t pid) |
7b50312a | 225 | { |
26cb8b7c PA |
226 | return &i386_process_info_get (pid)->state; |
227 | } | |
228 | ||
229 | /* See declaration in i386-nat.h. */ | |
230 | ||
231 | void | |
232 | i386_forget_process (pid_t pid) | |
233 | { | |
234 | struct i386_process_info *proc, **proc_link; | |
235 | ||
236 | proc = i386_process_list; | |
237 | proc_link = &i386_process_list; | |
238 | ||
239 | while (proc != NULL) | |
240 | { | |
241 | if (proc->pid == pid) | |
242 | { | |
243 | *proc_link = proc->next; | |
244 | ||
245 | xfree (proc); | |
246 | return; | |
247 | } | |
248 | ||
249 | proc_link = &proc->next; | |
250 | proc = *proc_link; | |
251 | } | |
7b50312a PA |
252 | } |
253 | ||
52b98211 | 254 | /* Whether or not to print the mirrored debug registers. */ |
7fa2737c | 255 | static int maint_show_dr; |
52b98211 EZ |
256 | |
257 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
258 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
259 | ||
260 | /* Internal functions. */ | |
261 | ||
262 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
263 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
264 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
265 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
266 | ||
267 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
268 | according to the length of the region to watch. LEN_RW_BITS is the | |
269 | value of the bit-field from DR7 which describes the length and | |
270 | access type of the region to be watched by this watchpoint. Return | |
271 | 0 on success, -1 on failure. */ | |
1ced966e PA |
272 | static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
273 | CORE_ADDR addr, | |
52b98211 EZ |
274 | unsigned len_rw_bits); |
275 | ||
276 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
277 | according to the length of the region to watch. LEN_RW_BITS is the | |
278 | value of the bits from DR7 which describes the length and access | |
279 | type of the region watched by this watchpoint. Return 0 on | |
280 | success, -1 on failure. */ | |
1ced966e PA |
281 | static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
282 | CORE_ADDR addr, | |
52b98211 EZ |
283 | unsigned len_rw_bits); |
284 | ||
285 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
286 | number of debug registers required to watch a region at address | |
287 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
288 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
289 | about the number of registers, or -1 on failure. If WHAT is not a |
290 | valid value, bombs through internal_error. */ | |
1ced966e PA |
291 | static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
292 | i386_wp_op_t what, | |
52b98211 EZ |
293 | CORE_ADDR addr, int len, |
294 | enum target_hw_bp_type type); | |
295 | ||
296 | /* Implementation. */ | |
297 | ||
7fa2737c MK |
298 | /* Clear the reference counts and forget everything we knew about the |
299 | debug registers. */ | |
300 | ||
52b98211 EZ |
301 | void |
302 | i386_cleanup_dregs (void) | |
303 | { | |
26cb8b7c PA |
304 | /* Starting from scratch has the same effect. */ |
305 | i386_forget_process (ptid_get_pid (inferior_ptid)); | |
52b98211 EZ |
306 | } |
307 | ||
7fa2737c MK |
308 | /* Print the values of the mirrored debug registers. This is called |
309 | when maint_show_dr is non-zero. To set that up, type "maint | |
310 | show-debug-regs" at GDB's prompt. */ | |
311 | ||
52b98211 | 312 | static void |
1ced966e PA |
313 | i386_show_dr (struct i386_debug_reg_state *state, |
314 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
315 | int len, enum target_hw_bp_type type) |
316 | { | |
f5656ead | 317 | int addr_size = gdbarch_addr_bit (target_gdbarch ()) / 8; |
52b98211 EZ |
318 | int i; |
319 | ||
320 | puts_unfiltered (func); | |
321 | if (addr || len) | |
322 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
323 | /* This code is for ia32, so casting CORE_ADDR | |
324 | to unsigned long should be okay. */ | |
325 | (unsigned long)addr, len, | |
326 | type == hw_write ? "data-write" | |
327 | : (type == hw_read ? "data-read" | |
328 | : (type == hw_access ? "data-read/write" | |
329 | : (type == hw_execute ? "instruction-execute" | |
330 | /* FIXME: if/when I/O read/write | |
331 | watchpoints are supported, add them | |
332 | here. */ | |
333 | : "??unknown??")))); | |
334 | puts_unfiltered (":\n"); | |
9bb9e8ad | 335 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
1ced966e PA |
336 | phex (state->dr_control_mirror, 8), |
337 | phex (state->dr_status_mirror, 8)); | |
52b98211 EZ |
338 | ALL_DEBUG_REGISTERS(i) |
339 | { | |
7fa2737c MK |
340 | printf_unfiltered ("\ |
341 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
1ced966e PA |
342 | i, phex (state->dr_mirror[i], addr_size), |
343 | state->dr_ref_count[i], | |
344 | i + 1, phex (state->dr_mirror[i + 1], addr_size), | |
345 | state->dr_ref_count[i+1]); | |
52b98211 EZ |
346 | i++; |
347 | } | |
348 | } | |
349 | ||
350 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
351 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
352 | have the value of 1, 2, or 4. */ | |
353 | ||
52b98211 EZ |
354 | static unsigned |
355 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
356 | { | |
357 | unsigned rw; | |
358 | ||
359 | switch (type) | |
360 | { | |
361 | case hw_execute: | |
362 | rw = DR_RW_EXECUTE; | |
363 | break; | |
364 | case hw_write: | |
365 | rw = DR_RW_WRITE; | |
366 | break; | |
7fa2737c | 367 | case hw_read: |
85d721b8 | 368 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
369 | _("The i386 doesn't support " |
370 | "data-read watchpoints.\n")); | |
52b98211 EZ |
371 | case hw_access: |
372 | rw = DR_RW_READ; | |
373 | break; | |
374 | #if 0 | |
7fa2737c MK |
375 | /* Not yet supported. */ |
376 | case hw_io_access: | |
52b98211 EZ |
377 | rw = DR_RW_IORW; |
378 | break; | |
379 | #endif | |
380 | default: | |
e2e0b3e5 AC |
381 | internal_error (__FILE__, __LINE__, _("\ |
382 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 383 | (int) type); |
52b98211 EZ |
384 | } |
385 | ||
386 | switch (len) | |
387 | { | |
52b98211 EZ |
388 | case 1: |
389 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
390 | case 2: |
391 | return (DR_LEN_2 | rw); | |
392 | case 4: | |
393 | return (DR_LEN_4 | rw); | |
394 | case 8: | |
395 | if (TARGET_HAS_DR_LEN_8) | |
396 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 397 | /* ELSE FALL THROUGH */ |
52b98211 | 398 | default: |
e2e0b3e5 AC |
399 | internal_error (__FILE__, __LINE__, _("\ |
400 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
401 | } |
402 | } | |
403 | ||
404 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
405 | according to the length of the region to watch. LEN_RW_BITS is the | |
406 | value of the bits from DR7 which describes the length and access | |
407 | type of the region to be watched by this watchpoint. Return 0 on | |
408 | success, -1 on failure. */ | |
7fa2737c | 409 | |
52b98211 | 410 | static int |
1ced966e PA |
411 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
412 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
413 | { |
414 | int i; | |
415 | ||
9bb9e8ad PM |
416 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
417 | return -1; | |
418 | ||
52b98211 EZ |
419 | /* First, look for an occupied debug register with the same address |
420 | and the same RW and LEN definitions. If we find one, we can | |
421 | reuse it for this watchpoint as well (and save a register). */ | |
422 | ALL_DEBUG_REGISTERS(i) | |
423 | { | |
1ced966e PA |
424 | if (!I386_DR_VACANT (state, i) |
425 | && state->dr_mirror[i] == addr | |
426 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 427 | { |
1ced966e | 428 | state->dr_ref_count[i]++; |
52b98211 EZ |
429 | return 0; |
430 | } | |
431 | } | |
432 | ||
433 | /* Next, look for a vacant debug register. */ | |
434 | ALL_DEBUG_REGISTERS(i) | |
435 | { | |
1ced966e | 436 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
437 | break; |
438 | } | |
439 | ||
440 | /* No more debug registers! */ | |
441 | if (i >= DR_NADDR) | |
442 | return -1; | |
443 | ||
444 | /* Now set up the register I to watch our region. */ | |
445 | ||
446 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
447 | state->dr_mirror[i] = addr; |
448 | state->dr_ref_count[i] = 1; | |
449 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 450 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 451 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
452 | watchpoints; however, if any target would want that in the |
453 | future, GDB should probably provide a command to control whether | |
454 | to enable watchpoints globally or locally, and the code below | |
455 | should use global or local enable and slow-down flags as | |
456 | appropriate. */ | |
1ced966e PA |
457 | I386_DR_LOCAL_ENABLE (state, i); |
458 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
459 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 460 | |
52b98211 EZ |
461 | return 0; |
462 | } | |
463 | ||
464 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
465 | according to the length of the region to watch. LEN_RW_BITS is the | |
466 | value of the bits from DR7 which describes the length and access | |
467 | type of the region watched by this watchpoint. Return 0 on | |
468 | success, -1 on failure. */ | |
7fa2737c | 469 | |
52b98211 | 470 | static int |
1ced966e PA |
471 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
472 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
473 | { |
474 | int i, retval = -1; | |
475 | ||
476 | ALL_DEBUG_REGISTERS(i) | |
477 | { | |
1ced966e PA |
478 | if (!I386_DR_VACANT (state, i) |
479 | && state->dr_mirror[i] == addr | |
480 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 481 | { |
1ced966e | 482 | if (--state->dr_ref_count[i] == 0) /* no longer in use? */ |
52b98211 EZ |
483 | { |
484 | /* Reset our mirror. */ | |
1ced966e PA |
485 | state->dr_mirror[i] = 0; |
486 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
487 | } |
488 | retval = 0; | |
489 | } | |
490 | } | |
491 | ||
492 | return retval; | |
493 | } | |
494 | ||
495 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
496 | number of debug registers required to watch a region at address | |
497 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
498 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
499 | about the number of registers, or -1 on failure. If WHAT is not a |
500 | valid value, bombs through internal_error. */ | |
501 | ||
52b98211 | 502 | static int |
1ced966e PA |
503 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
504 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
505 | enum target_hw_bp_type type) |
506 | { | |
1ced966e | 507 | int retval = 0; |
e906b9a3 | 508 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 509 | |
e906b9a3 | 510 | static int size_try_array[8][8] = |
52b98211 | 511 | { |
7fa2737c MK |
512 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
513 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
514 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
515 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
516 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
517 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
518 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
519 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
520 | }; |
521 | ||
522 | while (len > 0) | |
523 | { | |
7fa2737c | 524 | int align = addr % max_wp_len; |
f2e7c15d | 525 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 526 | can watch. */ |
7fa2737c MK |
527 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
528 | int size = size_try_array[try][align]; | |
529 | ||
52b98211 | 530 | if (what == WP_COUNT) |
7fa2737c MK |
531 | { |
532 | /* size_try_array[] is defined such that each iteration | |
533 | through the loop is guaranteed to produce an address and a | |
534 | size that can be watched with a single debug register. | |
535 | Thus, for counting the registers required to watch a | |
536 | region, we simply need to increment the count on each | |
537 | iteration. */ | |
538 | retval++; | |
539 | } | |
52b98211 EZ |
540 | else |
541 | { | |
542 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
543 | ||
544 | if (what == WP_INSERT) | |
1ced966e | 545 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 546 | else if (what == WP_REMOVE) |
1ced966e | 547 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 548 | else |
e2e0b3e5 AC |
549 | internal_error (__FILE__, __LINE__, _("\ |
550 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 | 551 | (int)what); |
1ced966e PA |
552 | if (retval) |
553 | break; | |
52b98211 | 554 | } |
7fa2737c | 555 | |
52b98211 EZ |
556 | addr += size; |
557 | len -= size; | |
558 | } | |
7fa2737c MK |
559 | |
560 | return retval; | |
52b98211 EZ |
561 | } |
562 | ||
1ced966e PA |
563 | /* Update the inferior's debug registers with the new debug registers |
564 | state, in NEW_STATE, and then update our local mirror to match. */ | |
565 | ||
566 | static void | |
567 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
568 | { | |
26cb8b7c PA |
569 | struct i386_debug_reg_state *state |
570 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
1ced966e PA |
571 | int i; |
572 | ||
573 | ALL_DEBUG_REGISTERS (i) | |
574 | { | |
4403d8e9 | 575 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
7b50312a | 576 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); |
1ced966e | 577 | else |
4403d8e9 | 578 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
579 | } |
580 | ||
4403d8e9 | 581 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
1ced966e PA |
582 | i386_dr_low.set_control (new_state->dr_control_mirror); |
583 | ||
4403d8e9 | 584 | *state = *new_state; |
1ced966e PA |
585 | } |
586 | ||
52b98211 EZ |
587 | /* Insert a watchpoint to watch a memory region which starts at |
588 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
589 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 590 | |
9bb9e8ad | 591 | static int |
0cf6dd15 TJB |
592 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type, |
593 | struct expression *cond) | |
52b98211 | 594 | { |
26cb8b7c PA |
595 | struct i386_debug_reg_state *state |
596 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 597 | int retval; |
1ced966e PA |
598 | /* Work on a local copy of the debug registers, and on success, |
599 | commit the change back to the inferior. */ | |
4403d8e9 | 600 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 601 | |
85d721b8 PA |
602 | if (type == hw_read) |
603 | return 1; /* unsupported */ | |
604 | ||
e906b9a3 JS |
605 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
606 | || addr % len != 0) | |
1ced966e PA |
607 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
608 | WP_INSERT, addr, len, type); | |
52b98211 EZ |
609 | else |
610 | { | |
611 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
612 | ||
1ced966e PA |
613 | retval = i386_insert_aligned_watchpoint (&local_state, |
614 | addr, len_rw); | |
52b98211 EZ |
615 | } |
616 | ||
1ced966e PA |
617 | if (retval == 0) |
618 | i386_update_inferior_debug_regs (&local_state); | |
619 | ||
52b98211 | 620 | if (maint_show_dr) |
4403d8e9 | 621 | i386_show_dr (state, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
622 | |
623 | return retval; | |
624 | } | |
625 | ||
626 | /* Remove a watchpoint that watched the memory region which starts at | |
627 | address ADDR, whose length is LEN bytes, and for accesses of the | |
628 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 629 | static int |
0cf6dd15 TJB |
630 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type, |
631 | struct expression *cond) | |
52b98211 | 632 | { |
26cb8b7c PA |
633 | struct i386_debug_reg_state *state |
634 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 635 | int retval; |
1ced966e PA |
636 | /* Work on a local copy of the debug registers, and on success, |
637 | commit the change back to the inferior. */ | |
4403d8e9 | 638 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 639 | |
e906b9a3 JS |
640 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
641 | || addr % len != 0) | |
1ced966e PA |
642 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
643 | WP_REMOVE, addr, len, type); | |
52b98211 EZ |
644 | else |
645 | { | |
646 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
647 | ||
1ced966e PA |
648 | retval = i386_remove_aligned_watchpoint (&local_state, |
649 | addr, len_rw); | |
52b98211 EZ |
650 | } |
651 | ||
1ced966e PA |
652 | if (retval == 0) |
653 | i386_update_inferior_debug_regs (&local_state); | |
654 | ||
52b98211 | 655 | if (maint_show_dr) |
4403d8e9 | 656 | i386_show_dr (state, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
657 | |
658 | return retval; | |
659 | } | |
660 | ||
661 | /* Return non-zero if we can watch a memory region that starts at | |
662 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 663 | |
9bb9e8ad | 664 | static int |
52b98211 EZ |
665 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
666 | { | |
26cb8b7c PA |
667 | struct i386_debug_reg_state *state |
668 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c MK |
669 | int nregs; |
670 | ||
52b98211 EZ |
671 | /* Compute how many aligned watchpoints we would need to cover this |
672 | region. */ | |
4403d8e9 | 673 | nregs = i386_handle_nonaligned_watchpoint (state, |
1ced966e | 674 | WP_COUNT, addr, len, hw_write); |
52b98211 EZ |
675 | return nregs <= DR_NADDR ? 1 : 0; |
676 | } | |
677 | ||
4aa7a7f5 | 678 | /* If the inferior has some watchpoint that triggered, set the |
1777feb0 | 679 | address associated with that watchpoint and return non-zero. |
4aa7a7f5 | 680 | Otherwise, return zero. */ |
7fa2737c | 681 | |
9bb9e8ad | 682 | static int |
c03374d5 | 683 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 684 | { |
26cb8b7c PA |
685 | struct i386_debug_reg_state *state |
686 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
7fa2737c | 687 | CORE_ADDR addr = 0; |
52b98211 | 688 | int i; |
4aa7a7f5 | 689 | int rc = 0; |
7b50312a PA |
690 | /* The current thread's DR_STATUS. We always need to read this to |
691 | check whether some watchpoint caused the trap. */ | |
1ced966e | 692 | unsigned status; |
7b50312a PA |
693 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
694 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
695 | unnecessary extra syscall when no watchpoint triggered. */ | |
696 | int control_p = 0; | |
697 | unsigned control = 0; | |
698 | ||
699 | /* In non-stop/async, threads can be running while we change the | |
4403d8e9 JK |
700 | STATE (and friends). Say, we set a watchpoint, and let threads |
701 | resume. Now, say you delete the watchpoint, or add/remove | |
702 | watchpoints such that STATE changes while threads are running. | |
703 | On targets that support non-stop, inserting/deleting watchpoints | |
704 | updates the STATE only. It does not update the real thread's | |
705 | debug registers; that's only done prior to resume. Instead, if | |
706 | threads are running when the mirror changes, a temporary and | |
707 | transparent stop on all threads is forced so they can get their | |
708 | copy of the debug registers updated on re-resume. Now, say, | |
709 | a thread hit a watchpoint before having been updated with the new | |
710 | STATE contents, and we haven't yet handled the corresponding | |
711 | SIGTRAP. If we trusted STATE below, we'd mistake the real | |
712 | trapped address (from the last time we had updated debug | |
713 | registers in the thread) with whatever was currently in STATE. | |
714 | So to fix this, STATE always represents intention, what we _want_ | |
715 | threads to have in debug registers. To get at the address and | |
716 | cause of the trap, we need to read the state the thread still has | |
717 | in its debug registers. | |
7b50312a PA |
718 | |
719 | In sum, always get the current debug register values the current | |
720 | thread has, instead of trusting the global mirror. If the thread | |
721 | was running when we last changed watchpoints, the mirror no | |
722 | longer represents what was set in this thread's debug | |
723 | registers. */ | |
724 | status = i386_dr_low.get_status (); | |
52b98211 EZ |
725 | |
726 | ALL_DEBUG_REGISTERS(i) | |
727 | { | |
7b50312a PA |
728 | if (!I386_DR_WATCH_HIT (status, i)) |
729 | continue; | |
730 | ||
731 | if (!control_p) | |
732 | { | |
733 | control = i386_dr_low.get_control (); | |
734 | control_p = 1; | |
735 | } | |
736 | ||
737 | /* This second condition makes sure DRi is set up for a data | |
738 | watchpoint, not a hardware breakpoint. The reason is that | |
739 | GDB doesn't call the target_stopped_data_address method | |
740 | except for data watchpoints. In other words, I'm being | |
741 | paranoiac. */ | |
742 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 743 | { |
7b50312a | 744 | addr = i386_dr_low.get_addr (i); |
4aa7a7f5 | 745 | rc = 1; |
52b98211 | 746 | if (maint_show_dr) |
4403d8e9 | 747 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
748 | } |
749 | } | |
7fa2737c | 750 | if (maint_show_dr && addr == 0) |
4403d8e9 | 751 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 752 | |
4aa7a7f5 JJ |
753 | if (rc) |
754 | *addr_p = addr; | |
755 | return rc; | |
756 | } | |
757 | ||
9bb9e8ad | 758 | static int |
4aa7a7f5 JJ |
759 | i386_stopped_by_watchpoint (void) |
760 | { | |
761 | CORE_ADDR addr = 0; | |
c03374d5 | 762 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
763 | } |
764 | ||
8181d85f DJ |
765 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
766 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 767 | static int |
a6d9a66e UW |
768 | i386_insert_hw_breakpoint (struct gdbarch *gdbarch, |
769 | struct bp_target_info *bp_tgt) | |
52b98211 | 770 | { |
26cb8b7c PA |
771 | struct i386_debug_reg_state *state |
772 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 773 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 774 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
775 | /* Work on a local copy of the debug registers, and on success, |
776 | commit the change back to the inferior. */ | |
4403d8e9 | 777 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 778 | int retval = i386_insert_aligned_watchpoint (&local_state, |
1ced966e | 779 | addr, len_rw) ? EBUSY : 0; |
52b98211 | 780 | |
edcc485a MR |
781 | if (retval == 0) |
782 | i386_update_inferior_debug_regs (&local_state); | |
783 | ||
52b98211 | 784 | if (maint_show_dr) |
4403d8e9 | 785 | i386_show_dr (state, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
786 | |
787 | return retval; | |
788 | } | |
789 | ||
8181d85f DJ |
790 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
791 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 792 | |
9bb9e8ad | 793 | static int |
a6d9a66e UW |
794 | i386_remove_hw_breakpoint (struct gdbarch *gdbarch, |
795 | struct bp_target_info *bp_tgt) | |
52b98211 | 796 | { |
26cb8b7c PA |
797 | struct i386_debug_reg_state *state |
798 | = i386_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
52b98211 | 799 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 800 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
801 | /* Work on a local copy of the debug registers, and on success, |
802 | commit the change back to the inferior. */ | |
4403d8e9 | 803 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 804 | int retval = i386_remove_aligned_watchpoint (&local_state, |
1ced966e | 805 | addr, len_rw); |
52b98211 | 806 | |
edcc485a MR |
807 | if (retval == 0) |
808 | i386_update_inferior_debug_regs (&local_state); | |
809 | ||
52b98211 | 810 | if (maint_show_dr) |
4403d8e9 | 811 | i386_show_dr (state, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
812 | |
813 | return retval; | |
814 | } | |
815 | ||
c03374d5 DJ |
816 | /* Returns the number of hardware watchpoints of type TYPE that we can |
817 | set. Value is positive if we can set CNT watchpoints, zero if | |
818 | setting watchpoints of type TYPE is not supported, and negative if | |
819 | CNT is more than the maximum number of watchpoints of type TYPE | |
820 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
821 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
822 | CNT is the number of such watchpoints used so far (including this | |
823 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
824 | currently enabled. | |
825 | ||
826 | We always return 1 here because we don't have enough information | |
827 | about possible overlap of addresses that they want to watch. As an | |
828 | extreme example, consider the case where all the watchpoints watch | |
829 | the same address and the same region length: then we can handle a | |
830 | virtually unlimited number of watchpoints, due to debug register | |
831 | sharing implemented via reference counts in i386-nat.c. */ | |
832 | ||
833 | static int | |
834 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
835 | { | |
836 | return 1; | |
837 | } | |
838 | ||
9bb9e8ad PM |
839 | static void |
840 | add_show_debug_regs_command (void) | |
841 | { | |
842 | /* A maintenance command to enable printing the internal DRi mirror | |
843 | variables. */ | |
844 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
845 | &maint_show_dr, _("\ | |
846 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
847 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
848 | Use \"on\" to enable, \"off\" to disable.\n\ | |
849 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
850 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
851 | triggers a breakpoint or watchpoint."), | |
852 | NULL, | |
853 | NULL, | |
854 | &maintenance_set_cmdlist, | |
855 | &maintenance_show_cmdlist); | |
856 | } | |
857 | ||
858 | /* There are only two global functions left. */ | |
859 | ||
c03374d5 DJ |
860 | void |
861 | i386_use_watchpoints (struct target_ops *t) | |
862 | { | |
863 | /* After a watchpoint trap, the PC points to the instruction after the | |
864 | one that caused the trap. Therefore we don't need to step over it. | |
865 | But we do need to reset the status register to avoid another trap. */ | |
866 | t->to_have_continuable_watchpoint = 1; | |
867 | ||
868 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
869 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
870 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
871 | t->to_stopped_data_address = i386_stopped_data_address; | |
872 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
873 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
874 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
875 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
876 | } | |
877 | ||
52b98211 | 878 | void |
9bb9e8ad | 879 | i386_set_debug_register_length (int len) |
52b98211 | 880 | { |
9bb9e8ad PM |
881 | /* This function should be called only once for each native target. */ |
882 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
883 | gdb_assert (len == 4 || len == 8); | |
884 | i386_dr_low.debug_register_length = len; | |
885 | add_show_debug_regs_command (); | |
52b98211 | 886 | } |