Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
7b6bb8da | 3 | Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009, 2010, 2011 |
0fb0cc75 | 4 | Free Software Foundation, Inc. |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 | 20 | |
9bb9e8ad | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "defs.h" |
23 | #include "breakpoint.h" | |
24 | #include "command.h" | |
25 | #include "gdbcmd.h" | |
c03374d5 | 26 | #include "target.h" |
9bb9e8ad | 27 | #include "gdb_assert.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
9bb9e8ad PM |
40 | struct i386_dr_low_type i386_dr_low; |
41 | ||
52b98211 | 42 | |
e906b9a3 | 43 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 44 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 45 | |
52b98211 | 46 | /* Debug registers' indices. */ |
7fa2737c MK |
47 | #define DR_NADDR 4 /* The number of debug address registers. */ |
48 | #define DR_STATUS 6 /* Index of debug status register (DR6). */ | |
1777feb0 | 49 | #define DR_CONTROL 7 /* Index of debug control register (DR7). */ |
52b98211 EZ |
50 | |
51 | /* DR7 Debug Control register fields. */ | |
52 | ||
53 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
54 | #define DR_CONTROL_SHIFT 16 | |
55 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
56 | #define DR_CONTROL_SIZE 4 | |
57 | ||
58 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
59 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
60 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
61 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
62 | |
63 | /* This is here for completeness. No platform supports this | |
7fa2737c | 64 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
65 | CR4 register needs to be set to support this. */ |
66 | #ifndef DR_RW_IORW | |
7fa2737c | 67 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
68 | #endif |
69 | ||
70 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
71 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
72 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
73 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
74 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
75 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
76 | |
77 | /* Local and Global Enable flags in DR7. | |
78 | ||
79 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
80 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
81 | clears this flag on every task switch. When the Global Enable flag |
82 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
83 | processor never clears this flag. | |
52b98211 EZ |
84 | |
85 | Currently, all watchpoint are locally enabled. If you need to | |
86 | enable them globally, read the comment which pertains to this in | |
87 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
88 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
89 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
90 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
91 | |
92 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
93 | flags). These are only required on i386, to allow detection of the | |
94 | exact instruction which caused a watchpoint to break; i486 and | |
95 | later processors do that automatically. We set these flags for | |
7fa2737c | 96 | backwards compatibility. */ |
52b98211 | 97 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 98 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
99 | |
100 | /* Fields reserved by Intel. This includes the GD (General Detect | |
101 | Enable) flag, which causes a debug exception to be generated when a | |
102 | MOV instruction accesses one of the debug registers. | |
103 | ||
104 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
105 | #define DR_CONTROL_RESERVED (0xFC00) | |
106 | ||
107 | /* Auxiliary helper macros. */ | |
108 | ||
109 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 110 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
111 | |
112 | /* The I'th debug register is vacant if its Local and Global Enable | |
113 | bits are reset in the Debug Control register. */ | |
1ced966e PA |
114 | #define I386_DR_VACANT(state, i) \ |
115 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
52b98211 EZ |
116 | |
117 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
118 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
119 | do { \ | |
120 | (state)->dr_control_mirror |= \ | |
121 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
122 | } while (0) | |
52b98211 EZ |
123 | |
124 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
125 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
126 | do { \ | |
127 | (state)->dr_control_mirror |= \ | |
128 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
129 | } while (0) | |
52b98211 EZ |
130 | |
131 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
132 | #define I386_DR_DISABLE(state, i) \ |
133 | do { \ | |
134 | (state)->dr_control_mirror &= \ | |
135 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
136 | } while (0) | |
52b98211 EZ |
137 | |
138 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 139 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 140 | do { \ |
1ced966e PA |
141 | (state)->dr_control_mirror &= \ |
142 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
143 | (state)->dr_control_mirror |= \ | |
144 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
145 | } while (0) |
146 | ||
147 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
148 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
149 | (((dr7) \ | |
150 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 | 151 | |
a79d3c27 JK |
152 | /* Mask that this I'th watchpoint has triggered. */ |
153 | #define I386_DR_WATCH_MASK(i) (1 << (i)) | |
154 | ||
52b98211 | 155 | /* Did the watchpoint whose address is in the I'th register break? */ |
1ced966e | 156 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
157 | |
158 | /* A macro to loop over all debug registers. */ | |
159 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
160 | ||
1ced966e PA |
161 | |
162 | /* Global state needed to track h/w watchpoints. */ | |
163 | ||
164 | struct i386_debug_reg_state | |
165 | { | |
166 | /* Mirror the inferior's DRi registers. We keep the status and | |
167 | control registers separated because they don't hold addresses. | |
168 | Note that since we can change these mirrors while threads are | |
169 | running, we never trust them to explain a cause of a trap. | |
170 | For that, we need to peek directly in the inferior registers. */ | |
171 | CORE_ADDR dr_mirror[DR_NADDR]; | |
172 | unsigned dr_status_mirror, dr_control_mirror; | |
173 | ||
174 | /* Reference counts for each debug register. */ | |
175 | int dr_ref_count[DR_NADDR]; | |
176 | }; | |
177 | ||
178 | /* Clear the reference counts and forget everything we knew about the | |
179 | debug registers. */ | |
180 | ||
181 | static void | |
182 | i386_init_dregs (struct i386_debug_reg_state *state) | |
183 | { | |
184 | int i; | |
185 | ||
186 | ALL_DEBUG_REGISTERS (i) | |
187 | { | |
188 | state->dr_mirror[i] = 0; | |
189 | state->dr_ref_count[i] = 0; | |
190 | } | |
191 | state->dr_control_mirror = 0; | |
192 | state->dr_status_mirror = 0; | |
193 | } | |
194 | ||
195 | static struct i386_debug_reg_state dr_mirror; | |
52b98211 EZ |
196 | |
197 | /* Reference counts for each debug register. */ | |
7fa2737c | 198 | static int dr_ref_count[DR_NADDR]; |
52b98211 EZ |
199 | |
200 | /* Whether or not to print the mirrored debug registers. */ | |
7fa2737c | 201 | static int maint_show_dr; |
52b98211 EZ |
202 | |
203 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
204 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
205 | ||
206 | /* Internal functions. */ | |
207 | ||
208 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
209 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
210 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
211 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
212 | ||
213 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
214 | according to the length of the region to watch. LEN_RW_BITS is the | |
215 | value of the bit-field from DR7 which describes the length and | |
216 | access type of the region to be watched by this watchpoint. Return | |
217 | 0 on success, -1 on failure. */ | |
1ced966e PA |
218 | static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
219 | CORE_ADDR addr, | |
52b98211 EZ |
220 | unsigned len_rw_bits); |
221 | ||
222 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
223 | according to the length of the region to watch. LEN_RW_BITS is the | |
224 | value of the bits from DR7 which describes the length and access | |
225 | type of the region watched by this watchpoint. Return 0 on | |
226 | success, -1 on failure. */ | |
1ced966e PA |
227 | static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
228 | CORE_ADDR addr, | |
52b98211 EZ |
229 | unsigned len_rw_bits); |
230 | ||
231 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
232 | number of debug registers required to watch a region at address | |
233 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
234 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
235 | about the number of registers, or -1 on failure. If WHAT is not a |
236 | valid value, bombs through internal_error. */ | |
1ced966e PA |
237 | static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
238 | i386_wp_op_t what, | |
52b98211 EZ |
239 | CORE_ADDR addr, int len, |
240 | enum target_hw_bp_type type); | |
241 | ||
242 | /* Implementation. */ | |
243 | ||
7fa2737c MK |
244 | /* Clear the reference counts and forget everything we knew about the |
245 | debug registers. */ | |
246 | ||
52b98211 EZ |
247 | void |
248 | i386_cleanup_dregs (void) | |
249 | { | |
1ced966e | 250 | i386_init_dregs (&dr_mirror); |
52b98211 EZ |
251 | } |
252 | ||
7fa2737c MK |
253 | /* Print the values of the mirrored debug registers. This is called |
254 | when maint_show_dr is non-zero. To set that up, type "maint | |
255 | show-debug-regs" at GDB's prompt. */ | |
256 | ||
52b98211 | 257 | static void |
1ced966e PA |
258 | i386_show_dr (struct i386_debug_reg_state *state, |
259 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
260 | int len, enum target_hw_bp_type type) |
261 | { | |
5af949e3 | 262 | int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; |
52b98211 EZ |
263 | int i; |
264 | ||
265 | puts_unfiltered (func); | |
266 | if (addr || len) | |
267 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
268 | /* This code is for ia32, so casting CORE_ADDR | |
269 | to unsigned long should be okay. */ | |
270 | (unsigned long)addr, len, | |
271 | type == hw_write ? "data-write" | |
272 | : (type == hw_read ? "data-read" | |
273 | : (type == hw_access ? "data-read/write" | |
274 | : (type == hw_execute ? "instruction-execute" | |
275 | /* FIXME: if/when I/O read/write | |
276 | watchpoints are supported, add them | |
277 | here. */ | |
278 | : "??unknown??")))); | |
279 | puts_unfiltered (":\n"); | |
9bb9e8ad | 280 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
1ced966e PA |
281 | phex (state->dr_control_mirror, 8), |
282 | phex (state->dr_status_mirror, 8)); | |
52b98211 EZ |
283 | ALL_DEBUG_REGISTERS(i) |
284 | { | |
7fa2737c MK |
285 | printf_unfiltered ("\ |
286 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
1ced966e PA |
287 | i, phex (state->dr_mirror[i], addr_size), |
288 | state->dr_ref_count[i], | |
289 | i + 1, phex (state->dr_mirror[i + 1], addr_size), | |
290 | state->dr_ref_count[i+1]); | |
52b98211 EZ |
291 | i++; |
292 | } | |
293 | } | |
294 | ||
295 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
296 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
297 | have the value of 1, 2, or 4. */ | |
298 | ||
52b98211 EZ |
299 | static unsigned |
300 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
301 | { | |
302 | unsigned rw; | |
303 | ||
304 | switch (type) | |
305 | { | |
306 | case hw_execute: | |
307 | rw = DR_RW_EXECUTE; | |
308 | break; | |
309 | case hw_write: | |
310 | rw = DR_RW_WRITE; | |
311 | break; | |
7fa2737c | 312 | case hw_read: |
85d721b8 | 313 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
314 | _("The i386 doesn't support " |
315 | "data-read watchpoints.\n")); | |
52b98211 EZ |
316 | case hw_access: |
317 | rw = DR_RW_READ; | |
318 | break; | |
319 | #if 0 | |
7fa2737c MK |
320 | /* Not yet supported. */ |
321 | case hw_io_access: | |
52b98211 EZ |
322 | rw = DR_RW_IORW; |
323 | break; | |
324 | #endif | |
325 | default: | |
e2e0b3e5 AC |
326 | internal_error (__FILE__, __LINE__, _("\ |
327 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 328 | (int) type); |
52b98211 EZ |
329 | } |
330 | ||
331 | switch (len) | |
332 | { | |
52b98211 EZ |
333 | case 1: |
334 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
335 | case 2: |
336 | return (DR_LEN_2 | rw); | |
337 | case 4: | |
338 | return (DR_LEN_4 | rw); | |
339 | case 8: | |
340 | if (TARGET_HAS_DR_LEN_8) | |
341 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 342 | /* ELSE FALL THROUGH */ |
52b98211 | 343 | default: |
e2e0b3e5 AC |
344 | internal_error (__FILE__, __LINE__, _("\ |
345 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
346 | } |
347 | } | |
348 | ||
349 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
350 | according to the length of the region to watch. LEN_RW_BITS is the | |
351 | value of the bits from DR7 which describes the length and access | |
352 | type of the region to be watched by this watchpoint. Return 0 on | |
353 | success, -1 on failure. */ | |
7fa2737c | 354 | |
52b98211 | 355 | static int |
1ced966e PA |
356 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
357 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
358 | { |
359 | int i; | |
360 | ||
9bb9e8ad PM |
361 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
362 | return -1; | |
363 | ||
52b98211 EZ |
364 | /* First, look for an occupied debug register with the same address |
365 | and the same RW and LEN definitions. If we find one, we can | |
366 | reuse it for this watchpoint as well (and save a register). */ | |
367 | ALL_DEBUG_REGISTERS(i) | |
368 | { | |
1ced966e PA |
369 | if (!I386_DR_VACANT (state, i) |
370 | && state->dr_mirror[i] == addr | |
371 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 372 | { |
1ced966e | 373 | state->dr_ref_count[i]++; |
52b98211 EZ |
374 | return 0; |
375 | } | |
376 | } | |
377 | ||
378 | /* Next, look for a vacant debug register. */ | |
379 | ALL_DEBUG_REGISTERS(i) | |
380 | { | |
1ced966e | 381 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
382 | break; |
383 | } | |
384 | ||
385 | /* No more debug registers! */ | |
386 | if (i >= DR_NADDR) | |
387 | return -1; | |
388 | ||
389 | /* Now set up the register I to watch our region. */ | |
390 | ||
391 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
392 | state->dr_mirror[i] = addr; |
393 | state->dr_ref_count[i] = 1; | |
394 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 395 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 396 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
397 | watchpoints; however, if any target would want that in the |
398 | future, GDB should probably provide a command to control whether | |
399 | to enable watchpoints globally or locally, and the code below | |
400 | should use global or local enable and slow-down flags as | |
401 | appropriate. */ | |
1ced966e PA |
402 | I386_DR_LOCAL_ENABLE (state, i); |
403 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
404 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 405 | |
52b98211 EZ |
406 | return 0; |
407 | } | |
408 | ||
409 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
410 | according to the length of the region to watch. LEN_RW_BITS is the | |
411 | value of the bits from DR7 which describes the length and access | |
412 | type of the region watched by this watchpoint. Return 0 on | |
413 | success, -1 on failure. */ | |
7fa2737c | 414 | |
52b98211 | 415 | static int |
1ced966e PA |
416 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
417 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
418 | { |
419 | int i, retval = -1; | |
420 | ||
421 | ALL_DEBUG_REGISTERS(i) | |
422 | { | |
1ced966e PA |
423 | if (!I386_DR_VACANT (state, i) |
424 | && state->dr_mirror[i] == addr | |
425 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 426 | { |
1ced966e | 427 | if (--state->dr_ref_count[i] == 0) /* no longer in use? */ |
52b98211 EZ |
428 | { |
429 | /* Reset our mirror. */ | |
1ced966e PA |
430 | state->dr_mirror[i] = 0; |
431 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
432 | } |
433 | retval = 0; | |
434 | } | |
435 | } | |
436 | ||
437 | return retval; | |
438 | } | |
439 | ||
440 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
441 | number of debug registers required to watch a region at address | |
442 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
443 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
444 | about the number of registers, or -1 on failure. If WHAT is not a |
445 | valid value, bombs through internal_error. */ | |
446 | ||
52b98211 | 447 | static int |
1ced966e PA |
448 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
449 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
450 | enum target_hw_bp_type type) |
451 | { | |
1ced966e | 452 | int retval = 0; |
e906b9a3 | 453 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 454 | |
e906b9a3 | 455 | static int size_try_array[8][8] = |
52b98211 | 456 | { |
7fa2737c MK |
457 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
458 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
459 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
460 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
461 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
462 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
463 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
464 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
465 | }; |
466 | ||
467 | while (len > 0) | |
468 | { | |
7fa2737c | 469 | int align = addr % max_wp_len; |
f2e7c15d | 470 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 471 | can watch. */ |
7fa2737c MK |
472 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
473 | int size = size_try_array[try][align]; | |
474 | ||
52b98211 | 475 | if (what == WP_COUNT) |
7fa2737c MK |
476 | { |
477 | /* size_try_array[] is defined such that each iteration | |
478 | through the loop is guaranteed to produce an address and a | |
479 | size that can be watched with a single debug register. | |
480 | Thus, for counting the registers required to watch a | |
481 | region, we simply need to increment the count on each | |
482 | iteration. */ | |
483 | retval++; | |
484 | } | |
52b98211 EZ |
485 | else |
486 | { | |
487 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
488 | ||
489 | if (what == WP_INSERT) | |
1ced966e | 490 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 491 | else if (what == WP_REMOVE) |
1ced966e | 492 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 493 | else |
e2e0b3e5 AC |
494 | internal_error (__FILE__, __LINE__, _("\ |
495 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 | 496 | (int)what); |
1ced966e PA |
497 | if (retval) |
498 | break; | |
52b98211 | 499 | } |
7fa2737c | 500 | |
52b98211 EZ |
501 | addr += size; |
502 | len -= size; | |
503 | } | |
7fa2737c MK |
504 | |
505 | return retval; | |
52b98211 EZ |
506 | } |
507 | ||
1ced966e PA |
508 | /* Update the inferior's debug registers with the new debug registers |
509 | state, in NEW_STATE, and then update our local mirror to match. */ | |
510 | ||
511 | static void | |
512 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
513 | { | |
514 | int i; | |
515 | ||
516 | ALL_DEBUG_REGISTERS (i) | |
517 | { | |
518 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (&dr_mirror, i)) | |
519 | { | |
520 | if (!I386_DR_VACANT (new_state, i)) | |
521 | { | |
522 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); | |
523 | ||
524 | /* Only a sanity check for leftover bits (set possibly only | |
525 | by inferior). */ | |
526 | if (i386_dr_low.unset_status) | |
527 | i386_dr_low.unset_status (I386_DR_WATCH_MASK (i)); | |
528 | } | |
529 | else | |
530 | { | |
531 | if (i386_dr_low.reset_addr) | |
532 | i386_dr_low.reset_addr (i); | |
533 | } | |
534 | } | |
535 | else | |
536 | gdb_assert (new_state->dr_mirror[i] == dr_mirror.dr_mirror[i]); | |
537 | } | |
538 | ||
539 | if (new_state->dr_control_mirror != dr_mirror.dr_control_mirror) | |
540 | i386_dr_low.set_control (new_state->dr_control_mirror); | |
541 | ||
542 | dr_mirror = *new_state; | |
543 | } | |
544 | ||
52b98211 EZ |
545 | /* Insert a watchpoint to watch a memory region which starts at |
546 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
547 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 548 | |
9bb9e8ad | 549 | static int |
0cf6dd15 TJB |
550 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type, |
551 | struct expression *cond) | |
52b98211 EZ |
552 | { |
553 | int retval; | |
1ced966e PA |
554 | /* Work on a local copy of the debug registers, and on success, |
555 | commit the change back to the inferior. */ | |
556 | struct i386_debug_reg_state local_state = dr_mirror; | |
52b98211 | 557 | |
85d721b8 PA |
558 | if (type == hw_read) |
559 | return 1; /* unsupported */ | |
560 | ||
e906b9a3 JS |
561 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
562 | || addr % len != 0) | |
1ced966e PA |
563 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
564 | WP_INSERT, addr, len, type); | |
52b98211 EZ |
565 | else |
566 | { | |
567 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
568 | ||
1ced966e PA |
569 | retval = i386_insert_aligned_watchpoint (&local_state, |
570 | addr, len_rw); | |
52b98211 EZ |
571 | } |
572 | ||
1ced966e PA |
573 | if (retval == 0) |
574 | i386_update_inferior_debug_regs (&local_state); | |
575 | ||
52b98211 | 576 | if (maint_show_dr) |
1ced966e | 577 | i386_show_dr (&dr_mirror, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
578 | |
579 | return retval; | |
580 | } | |
581 | ||
582 | /* Remove a watchpoint that watched the memory region which starts at | |
583 | address ADDR, whose length is LEN bytes, and for accesses of the | |
584 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 585 | static int |
0cf6dd15 TJB |
586 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type, |
587 | struct expression *cond) | |
52b98211 EZ |
588 | { |
589 | int retval; | |
1ced966e PA |
590 | /* Work on a local copy of the debug registers, and on success, |
591 | commit the change back to the inferior. */ | |
592 | struct i386_debug_reg_state local_state = dr_mirror; | |
52b98211 | 593 | |
e906b9a3 JS |
594 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
595 | || addr % len != 0) | |
1ced966e PA |
596 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
597 | WP_REMOVE, addr, len, type); | |
52b98211 EZ |
598 | else |
599 | { | |
600 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
601 | ||
1ced966e PA |
602 | retval = i386_remove_aligned_watchpoint (&local_state, |
603 | addr, len_rw); | |
52b98211 EZ |
604 | } |
605 | ||
1ced966e PA |
606 | if (retval == 0) |
607 | i386_update_inferior_debug_regs (&local_state); | |
608 | ||
52b98211 | 609 | if (maint_show_dr) |
1ced966e | 610 | i386_show_dr (&dr_mirror, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
611 | |
612 | return retval; | |
613 | } | |
614 | ||
615 | /* Return non-zero if we can watch a memory region that starts at | |
616 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 617 | |
9bb9e8ad | 618 | static int |
52b98211 EZ |
619 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
620 | { | |
7fa2737c MK |
621 | int nregs; |
622 | ||
52b98211 EZ |
623 | /* Compute how many aligned watchpoints we would need to cover this |
624 | region. */ | |
1ced966e PA |
625 | nregs = i386_handle_nonaligned_watchpoint (&dr_mirror, |
626 | WP_COUNT, addr, len, hw_write); | |
52b98211 EZ |
627 | return nregs <= DR_NADDR ? 1 : 0; |
628 | } | |
629 | ||
4aa7a7f5 | 630 | /* If the inferior has some watchpoint that triggered, set the |
1777feb0 | 631 | address associated with that watchpoint and return non-zero. |
4aa7a7f5 | 632 | Otherwise, return zero. */ |
7fa2737c | 633 | |
9bb9e8ad | 634 | static int |
c03374d5 | 635 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 636 | { |
7fa2737c | 637 | CORE_ADDR addr = 0; |
52b98211 | 638 | int i; |
4aa7a7f5 | 639 | int rc = 0; |
1ced966e PA |
640 | unsigned status; |
641 | unsigned control; | |
642 | struct i386_debug_reg_state *state = &dr_mirror; | |
52b98211 | 643 | |
1ced966e PA |
644 | dr_mirror.dr_status_mirror = i386_dr_low.get_status (); |
645 | status = dr_mirror.dr_status_mirror; | |
646 | control = dr_mirror.dr_control_mirror; | |
52b98211 EZ |
647 | |
648 | ALL_DEBUG_REGISTERS(i) | |
649 | { | |
1ced966e | 650 | if (I386_DR_WATCH_HIT (status, i) |
52b98211 EZ |
651 | /* This second condition makes sure DRi is set up for a data |
652 | watchpoint, not a hardware breakpoint. The reason is | |
653 | that GDB doesn't call the target_stopped_data_address | |
654 | method except for data watchpoints. In other words, I'm | |
f2e7c15d | 655 | being paranoiac. */ |
1ced966e | 656 | && I386_DR_GET_RW_LEN (control, i) != 0 |
087b74b2 PM |
657 | /* This third condition makes sure DRi is not vacant, this |
658 | avoids false positives in windows-nat.c. */ | |
1ced966e | 659 | && !I386_DR_VACANT (state, i)) |
52b98211 | 660 | { |
1ced966e | 661 | addr = state->dr_mirror[i]; |
4aa7a7f5 | 662 | rc = 1; |
52b98211 | 663 | if (maint_show_dr) |
1ced966e | 664 | i386_show_dr (&dr_mirror, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
665 | } |
666 | } | |
7fa2737c | 667 | if (maint_show_dr && addr == 0) |
1ced966e | 668 | i386_show_dr (&dr_mirror, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 669 | |
4aa7a7f5 JJ |
670 | if (rc) |
671 | *addr_p = addr; | |
672 | return rc; | |
673 | } | |
674 | ||
9bb9e8ad | 675 | static int |
4aa7a7f5 JJ |
676 | i386_stopped_by_watchpoint (void) |
677 | { | |
678 | CORE_ADDR addr = 0; | |
c03374d5 | 679 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
680 | } |
681 | ||
8181d85f DJ |
682 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
683 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 684 | static int |
a6d9a66e UW |
685 | i386_insert_hw_breakpoint (struct gdbarch *gdbarch, |
686 | struct bp_target_info *bp_tgt) | |
52b98211 EZ |
687 | { |
688 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 689 | CORE_ADDR addr = bp_tgt->placed_address; |
1ced966e PA |
690 | int retval = i386_insert_aligned_watchpoint (&dr_mirror, |
691 | addr, len_rw) ? EBUSY : 0; | |
52b98211 EZ |
692 | |
693 | if (maint_show_dr) | |
1ced966e | 694 | i386_show_dr (&dr_mirror, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
695 | |
696 | return retval; | |
697 | } | |
698 | ||
8181d85f DJ |
699 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
700 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 701 | |
9bb9e8ad | 702 | static int |
a6d9a66e UW |
703 | i386_remove_hw_breakpoint (struct gdbarch *gdbarch, |
704 | struct bp_target_info *bp_tgt) | |
52b98211 EZ |
705 | { |
706 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 707 | CORE_ADDR addr = bp_tgt->placed_address; |
1ced966e PA |
708 | int retval = i386_remove_aligned_watchpoint (&dr_mirror, |
709 | addr, len_rw); | |
52b98211 EZ |
710 | |
711 | if (maint_show_dr) | |
1ced966e | 712 | i386_show_dr (&dr_mirror, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
713 | |
714 | return retval; | |
715 | } | |
716 | ||
c03374d5 DJ |
717 | /* Returns the number of hardware watchpoints of type TYPE that we can |
718 | set. Value is positive if we can set CNT watchpoints, zero if | |
719 | setting watchpoints of type TYPE is not supported, and negative if | |
720 | CNT is more than the maximum number of watchpoints of type TYPE | |
721 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
722 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
723 | CNT is the number of such watchpoints used so far (including this | |
724 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
725 | currently enabled. | |
726 | ||
727 | We always return 1 here because we don't have enough information | |
728 | about possible overlap of addresses that they want to watch. As an | |
729 | extreme example, consider the case where all the watchpoints watch | |
730 | the same address and the same region length: then we can handle a | |
731 | virtually unlimited number of watchpoints, due to debug register | |
732 | sharing implemented via reference counts in i386-nat.c. */ | |
733 | ||
734 | static int | |
735 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
736 | { | |
737 | return 1; | |
738 | } | |
739 | ||
9bb9e8ad PM |
740 | static void |
741 | add_show_debug_regs_command (void) | |
742 | { | |
743 | /* A maintenance command to enable printing the internal DRi mirror | |
744 | variables. */ | |
745 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
746 | &maint_show_dr, _("\ | |
747 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
748 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
749 | Use \"on\" to enable, \"off\" to disable.\n\ | |
750 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
751 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
752 | triggers a breakpoint or watchpoint."), | |
753 | NULL, | |
754 | NULL, | |
755 | &maintenance_set_cmdlist, | |
756 | &maintenance_show_cmdlist); | |
757 | } | |
758 | ||
759 | /* There are only two global functions left. */ | |
760 | ||
c03374d5 DJ |
761 | void |
762 | i386_use_watchpoints (struct target_ops *t) | |
763 | { | |
764 | /* After a watchpoint trap, the PC points to the instruction after the | |
765 | one that caused the trap. Therefore we don't need to step over it. | |
766 | But we do need to reset the status register to avoid another trap. */ | |
767 | t->to_have_continuable_watchpoint = 1; | |
768 | ||
769 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
770 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
771 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
772 | t->to_stopped_data_address = i386_stopped_data_address; | |
773 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
774 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
775 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
776 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
777 | } | |
778 | ||
52b98211 | 779 | void |
9bb9e8ad | 780 | i386_set_debug_register_length (int len) |
52b98211 | 781 | { |
9bb9e8ad PM |
782 | /* This function should be called only once for each native target. */ |
783 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
784 | gdb_assert (len == 4 || len == 8); | |
785 | i386_dr_low.debug_register_length = len; | |
786 | add_show_debug_regs_command (); | |
52b98211 | 787 | } |