Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
0b302171 JB |
3 | Copyright (C) 2001, 2004-2005, 2007-2012 Free Software Foundation, |
4 | Inc. | |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 | 20 | |
9bb9e8ad | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "defs.h" |
23 | #include "breakpoint.h" | |
24 | #include "command.h" | |
25 | #include "gdbcmd.h" | |
c03374d5 | 26 | #include "target.h" |
9bb9e8ad | 27 | #include "gdb_assert.h" |
4403d8e9 | 28 | #include "inferior.h" |
52b98211 | 29 | |
7fa2737c | 30 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
31 | debug registers. |
32 | ||
33 | This provides several functions for inserting and removing | |
7fa2737c MK |
34 | hardware-assisted breakpoints and watchpoints, testing if one or |
35 | more of the watchpoints triggered and at what address, checking | |
36 | whether a given region can be watched, etc. | |
37 | ||
7fa2737c MK |
38 | The functions below implement debug registers sharing by reference |
39 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 40 | |
9bb9e8ad PM |
41 | struct i386_dr_low_type i386_dr_low; |
42 | ||
52b98211 | 43 | |
e906b9a3 | 44 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 45 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 46 | |
52b98211 EZ |
47 | /* DR7 Debug Control register fields. */ |
48 | ||
49 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
50 | #define DR_CONTROL_SHIFT 16 | |
51 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
52 | #define DR_CONTROL_SIZE 4 | |
53 | ||
54 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
55 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
56 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
57 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
58 | |
59 | /* This is here for completeness. No platform supports this | |
7fa2737c | 60 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
61 | CR4 register needs to be set to support this. */ |
62 | #ifndef DR_RW_IORW | |
7fa2737c | 63 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
64 | #endif |
65 | ||
66 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
67 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
68 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
69 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
70 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
71 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
72 | |
73 | /* Local and Global Enable flags in DR7. | |
74 | ||
75 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
76 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
77 | clears this flag on every task switch. When the Global Enable flag |
78 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
79 | processor never clears this flag. | |
52b98211 EZ |
80 | |
81 | Currently, all watchpoint are locally enabled. If you need to | |
82 | enable them globally, read the comment which pertains to this in | |
83 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
84 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
85 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
86 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
87 | |
88 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
89 | flags). These are only required on i386, to allow detection of the | |
90 | exact instruction which caused a watchpoint to break; i486 and | |
91 | later processors do that automatically. We set these flags for | |
7fa2737c | 92 | backwards compatibility. */ |
52b98211 | 93 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 94 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
95 | |
96 | /* Fields reserved by Intel. This includes the GD (General Detect | |
97 | Enable) flag, which causes a debug exception to be generated when a | |
98 | MOV instruction accesses one of the debug registers. | |
99 | ||
100 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
101 | #define DR_CONTROL_RESERVED (0xFC00) | |
102 | ||
103 | /* Auxiliary helper macros. */ | |
104 | ||
105 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 106 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
107 | |
108 | /* The I'th debug register is vacant if its Local and Global Enable | |
109 | bits are reset in the Debug Control register. */ | |
1ced966e PA |
110 | #define I386_DR_VACANT(state, i) \ |
111 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
52b98211 EZ |
112 | |
113 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
114 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
115 | do { \ | |
116 | (state)->dr_control_mirror |= \ | |
117 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
118 | } while (0) | |
52b98211 EZ |
119 | |
120 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
121 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
122 | do { \ | |
123 | (state)->dr_control_mirror |= \ | |
124 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
125 | } while (0) | |
52b98211 EZ |
126 | |
127 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
128 | #define I386_DR_DISABLE(state, i) \ |
129 | do { \ | |
130 | (state)->dr_control_mirror &= \ | |
131 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
132 | } while (0) | |
52b98211 EZ |
133 | |
134 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 135 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 136 | do { \ |
1ced966e PA |
137 | (state)->dr_control_mirror &= \ |
138 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
139 | (state)->dr_control_mirror |= \ | |
140 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
141 | } while (0) |
142 | ||
143 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
144 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
145 | (((dr7) \ | |
146 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 | 147 | |
a79d3c27 JK |
148 | /* Mask that this I'th watchpoint has triggered. */ |
149 | #define I386_DR_WATCH_MASK(i) (1 << (i)) | |
150 | ||
52b98211 | 151 | /* Did the watchpoint whose address is in the I'th register break? */ |
1ced966e | 152 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
153 | |
154 | /* A macro to loop over all debug registers. */ | |
155 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
156 | ||
1ced966e PA |
157 | /* Clear the reference counts and forget everything we knew about the |
158 | debug registers. */ | |
159 | ||
160 | static void | |
161 | i386_init_dregs (struct i386_debug_reg_state *state) | |
162 | { | |
163 | int i; | |
164 | ||
165 | ALL_DEBUG_REGISTERS (i) | |
166 | { | |
167 | state->dr_mirror[i] = 0; | |
168 | state->dr_ref_count[i] = 0; | |
169 | } | |
170 | state->dr_control_mirror = 0; | |
171 | state->dr_status_mirror = 0; | |
172 | } | |
173 | ||
4403d8e9 JK |
174 | /* Per-inferior data key. */ |
175 | static const struct inferior_data *i386_inferior_data; | |
176 | ||
177 | /* Per-inferior data. */ | |
178 | struct i386_inferior_data | |
179 | { | |
180 | /* Copy of i386 hardware debug registers for performance reasons. */ | |
181 | struct i386_debug_reg_state state; | |
182 | }; | |
183 | ||
d0d8b0c6 JK |
184 | /* Per-inferior hook for register_inferior_data_with_cleanup. */ |
185 | ||
186 | static void | |
187 | i386_inferior_data_cleanup (struct inferior *inf, void *arg) | |
188 | { | |
189 | struct i386_inferior_data *inf_data = arg; | |
190 | ||
191 | xfree (inf_data); | |
192 | } | |
193 | ||
4403d8e9 JK |
194 | /* Get data specific for INFERIOR_PTID LWP. Return special data area |
195 | for processes being detached. */ | |
196 | ||
197 | static struct i386_inferior_data * | |
198 | i386_inferior_data_get (void) | |
199 | { | |
4403d8e9 | 200 | struct inferior *inf = current_inferior (); |
d0d8b0c6 JK |
201 | struct i386_inferior_data *inf_data; |
202 | ||
203 | inf_data = inferior_data (inf, i386_inferior_data); | |
204 | if (inf_data == NULL) | |
205 | { | |
206 | inf_data = xzalloc (sizeof (*inf_data)); | |
207 | set_inferior_data (current_inferior (), i386_inferior_data, inf_data); | |
208 | } | |
4403d8e9 JK |
209 | |
210 | if (inf->pid != ptid_get_pid (inferior_ptid)) | |
211 | { | |
212 | /* INFERIOR_PTID is being detached from the inferior INF. | |
213 | Provide local cache specific for the detached LWP. */ | |
214 | ||
215 | static struct i386_inferior_data detached_inf_data_local; | |
216 | static int detached_inf_pid = -1; | |
217 | ||
218 | if (detached_inf_pid != ptid_get_pid (inferior_ptid)) | |
219 | { | |
220 | /* Reinitialize the local cache if INFERIOR_PTID is | |
221 | different from the LWP last detached. | |
222 | ||
223 | Linux kernel before 2.6.33 commit | |
224 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
225 | will inherit hardware debug registers from parent | |
226 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
227 | zeroed debug registers. | |
228 | ||
229 | GDB will remove all breakpoints (and watchpoints) from the forked | |
230 | off process. We also need to reset the debug registers in that | |
231 | process to be compatible with the older Linux kernels. | |
232 | ||
233 | Copy the debug registers mirrors into the new process so that all | |
234 | breakpoints and watchpoints can be removed together. The debug | |
235 | registers mirror will become zeroed in the end before detaching | |
236 | the forked off process. */ | |
237 | ||
238 | detached_inf_pid = ptid_get_pid (inferior_ptid); | |
239 | detached_inf_data_local = *inf_data; | |
240 | } | |
241 | ||
242 | return &detached_inf_data_local; | |
243 | } | |
244 | ||
245 | return inf_data; | |
246 | } | |
247 | ||
248 | /* Get debug registers state for INFERIOR_PTID, see | |
249 | i386_inferior_data_get. */ | |
52b98211 | 250 | |
7b50312a PA |
251 | struct i386_debug_reg_state * |
252 | i386_debug_reg_state (void) | |
253 | { | |
4403d8e9 | 254 | return &i386_inferior_data_get ()->state; |
7b50312a PA |
255 | } |
256 | ||
52b98211 | 257 | /* Whether or not to print the mirrored debug registers. */ |
7fa2737c | 258 | static int maint_show_dr; |
52b98211 EZ |
259 | |
260 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
261 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
262 | ||
263 | /* Internal functions. */ | |
264 | ||
265 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
266 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
267 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
268 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
269 | ||
270 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
271 | according to the length of the region to watch. LEN_RW_BITS is the | |
272 | value of the bit-field from DR7 which describes the length and | |
273 | access type of the region to be watched by this watchpoint. Return | |
274 | 0 on success, -1 on failure. */ | |
1ced966e PA |
275 | static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
276 | CORE_ADDR addr, | |
52b98211 EZ |
277 | unsigned len_rw_bits); |
278 | ||
279 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
280 | according to the length of the region to watch. LEN_RW_BITS is the | |
281 | value of the bits from DR7 which describes the length and access | |
282 | type of the region watched by this watchpoint. Return 0 on | |
283 | success, -1 on failure. */ | |
1ced966e PA |
284 | static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
285 | CORE_ADDR addr, | |
52b98211 EZ |
286 | unsigned len_rw_bits); |
287 | ||
288 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
289 | number of debug registers required to watch a region at address | |
290 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
291 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
292 | about the number of registers, or -1 on failure. If WHAT is not a |
293 | valid value, bombs through internal_error. */ | |
1ced966e PA |
294 | static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
295 | i386_wp_op_t what, | |
52b98211 EZ |
296 | CORE_ADDR addr, int len, |
297 | enum target_hw_bp_type type); | |
298 | ||
299 | /* Implementation. */ | |
300 | ||
7fa2737c MK |
301 | /* Clear the reference counts and forget everything we knew about the |
302 | debug registers. */ | |
303 | ||
52b98211 EZ |
304 | void |
305 | i386_cleanup_dregs (void) | |
306 | { | |
4403d8e9 JK |
307 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
308 | ||
309 | i386_init_dregs (state); | |
52b98211 EZ |
310 | } |
311 | ||
7fa2737c MK |
312 | /* Print the values of the mirrored debug registers. This is called |
313 | when maint_show_dr is non-zero. To set that up, type "maint | |
314 | show-debug-regs" at GDB's prompt. */ | |
315 | ||
52b98211 | 316 | static void |
1ced966e PA |
317 | i386_show_dr (struct i386_debug_reg_state *state, |
318 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
319 | int len, enum target_hw_bp_type type) |
320 | { | |
5af949e3 | 321 | int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; |
52b98211 EZ |
322 | int i; |
323 | ||
324 | puts_unfiltered (func); | |
325 | if (addr || len) | |
326 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
327 | /* This code is for ia32, so casting CORE_ADDR | |
328 | to unsigned long should be okay. */ | |
329 | (unsigned long)addr, len, | |
330 | type == hw_write ? "data-write" | |
331 | : (type == hw_read ? "data-read" | |
332 | : (type == hw_access ? "data-read/write" | |
333 | : (type == hw_execute ? "instruction-execute" | |
334 | /* FIXME: if/when I/O read/write | |
335 | watchpoints are supported, add them | |
336 | here. */ | |
337 | : "??unknown??")))); | |
338 | puts_unfiltered (":\n"); | |
9bb9e8ad | 339 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
1ced966e PA |
340 | phex (state->dr_control_mirror, 8), |
341 | phex (state->dr_status_mirror, 8)); | |
52b98211 EZ |
342 | ALL_DEBUG_REGISTERS(i) |
343 | { | |
7fa2737c MK |
344 | printf_unfiltered ("\ |
345 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
1ced966e PA |
346 | i, phex (state->dr_mirror[i], addr_size), |
347 | state->dr_ref_count[i], | |
348 | i + 1, phex (state->dr_mirror[i + 1], addr_size), | |
349 | state->dr_ref_count[i+1]); | |
52b98211 EZ |
350 | i++; |
351 | } | |
352 | } | |
353 | ||
354 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
355 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
356 | have the value of 1, 2, or 4. */ | |
357 | ||
52b98211 EZ |
358 | static unsigned |
359 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
360 | { | |
361 | unsigned rw; | |
362 | ||
363 | switch (type) | |
364 | { | |
365 | case hw_execute: | |
366 | rw = DR_RW_EXECUTE; | |
367 | break; | |
368 | case hw_write: | |
369 | rw = DR_RW_WRITE; | |
370 | break; | |
7fa2737c | 371 | case hw_read: |
85d721b8 | 372 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
373 | _("The i386 doesn't support " |
374 | "data-read watchpoints.\n")); | |
52b98211 EZ |
375 | case hw_access: |
376 | rw = DR_RW_READ; | |
377 | break; | |
378 | #if 0 | |
7fa2737c MK |
379 | /* Not yet supported. */ |
380 | case hw_io_access: | |
52b98211 EZ |
381 | rw = DR_RW_IORW; |
382 | break; | |
383 | #endif | |
384 | default: | |
e2e0b3e5 AC |
385 | internal_error (__FILE__, __LINE__, _("\ |
386 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 387 | (int) type); |
52b98211 EZ |
388 | } |
389 | ||
390 | switch (len) | |
391 | { | |
52b98211 EZ |
392 | case 1: |
393 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
394 | case 2: |
395 | return (DR_LEN_2 | rw); | |
396 | case 4: | |
397 | return (DR_LEN_4 | rw); | |
398 | case 8: | |
399 | if (TARGET_HAS_DR_LEN_8) | |
400 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 401 | /* ELSE FALL THROUGH */ |
52b98211 | 402 | default: |
e2e0b3e5 AC |
403 | internal_error (__FILE__, __LINE__, _("\ |
404 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
405 | } |
406 | } | |
407 | ||
408 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
409 | according to the length of the region to watch. LEN_RW_BITS is the | |
410 | value of the bits from DR7 which describes the length and access | |
411 | type of the region to be watched by this watchpoint. Return 0 on | |
412 | success, -1 on failure. */ | |
7fa2737c | 413 | |
52b98211 | 414 | static int |
1ced966e PA |
415 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
416 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
417 | { |
418 | int i; | |
419 | ||
9bb9e8ad PM |
420 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
421 | return -1; | |
422 | ||
52b98211 EZ |
423 | /* First, look for an occupied debug register with the same address |
424 | and the same RW and LEN definitions. If we find one, we can | |
425 | reuse it for this watchpoint as well (and save a register). */ | |
426 | ALL_DEBUG_REGISTERS(i) | |
427 | { | |
1ced966e PA |
428 | if (!I386_DR_VACANT (state, i) |
429 | && state->dr_mirror[i] == addr | |
430 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 431 | { |
1ced966e | 432 | state->dr_ref_count[i]++; |
52b98211 EZ |
433 | return 0; |
434 | } | |
435 | } | |
436 | ||
437 | /* Next, look for a vacant debug register. */ | |
438 | ALL_DEBUG_REGISTERS(i) | |
439 | { | |
1ced966e | 440 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
441 | break; |
442 | } | |
443 | ||
444 | /* No more debug registers! */ | |
445 | if (i >= DR_NADDR) | |
446 | return -1; | |
447 | ||
448 | /* Now set up the register I to watch our region. */ | |
449 | ||
450 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
451 | state->dr_mirror[i] = addr; |
452 | state->dr_ref_count[i] = 1; | |
453 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 454 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 455 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
456 | watchpoints; however, if any target would want that in the |
457 | future, GDB should probably provide a command to control whether | |
458 | to enable watchpoints globally or locally, and the code below | |
459 | should use global or local enable and slow-down flags as | |
460 | appropriate. */ | |
1ced966e PA |
461 | I386_DR_LOCAL_ENABLE (state, i); |
462 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
463 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 464 | |
52b98211 EZ |
465 | return 0; |
466 | } | |
467 | ||
468 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
469 | according to the length of the region to watch. LEN_RW_BITS is the | |
470 | value of the bits from DR7 which describes the length and access | |
471 | type of the region watched by this watchpoint. Return 0 on | |
472 | success, -1 on failure. */ | |
7fa2737c | 473 | |
52b98211 | 474 | static int |
1ced966e PA |
475 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
476 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
477 | { |
478 | int i, retval = -1; | |
479 | ||
480 | ALL_DEBUG_REGISTERS(i) | |
481 | { | |
1ced966e PA |
482 | if (!I386_DR_VACANT (state, i) |
483 | && state->dr_mirror[i] == addr | |
484 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 485 | { |
1ced966e | 486 | if (--state->dr_ref_count[i] == 0) /* no longer in use? */ |
52b98211 EZ |
487 | { |
488 | /* Reset our mirror. */ | |
1ced966e PA |
489 | state->dr_mirror[i] = 0; |
490 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
491 | } |
492 | retval = 0; | |
493 | } | |
494 | } | |
495 | ||
496 | return retval; | |
497 | } | |
498 | ||
499 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
500 | number of debug registers required to watch a region at address | |
501 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
502 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
503 | about the number of registers, or -1 on failure. If WHAT is not a |
504 | valid value, bombs through internal_error. */ | |
505 | ||
52b98211 | 506 | static int |
1ced966e PA |
507 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
508 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
509 | enum target_hw_bp_type type) |
510 | { | |
1ced966e | 511 | int retval = 0; |
e906b9a3 | 512 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 513 | |
e906b9a3 | 514 | static int size_try_array[8][8] = |
52b98211 | 515 | { |
7fa2737c MK |
516 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
517 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
518 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
519 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
520 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
521 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
522 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
523 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
524 | }; |
525 | ||
526 | while (len > 0) | |
527 | { | |
7fa2737c | 528 | int align = addr % max_wp_len; |
f2e7c15d | 529 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 530 | can watch. */ |
7fa2737c MK |
531 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
532 | int size = size_try_array[try][align]; | |
533 | ||
52b98211 | 534 | if (what == WP_COUNT) |
7fa2737c MK |
535 | { |
536 | /* size_try_array[] is defined such that each iteration | |
537 | through the loop is guaranteed to produce an address and a | |
538 | size that can be watched with a single debug register. | |
539 | Thus, for counting the registers required to watch a | |
540 | region, we simply need to increment the count on each | |
541 | iteration. */ | |
542 | retval++; | |
543 | } | |
52b98211 EZ |
544 | else |
545 | { | |
546 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
547 | ||
548 | if (what == WP_INSERT) | |
1ced966e | 549 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 550 | else if (what == WP_REMOVE) |
1ced966e | 551 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 552 | else |
e2e0b3e5 AC |
553 | internal_error (__FILE__, __LINE__, _("\ |
554 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 | 555 | (int)what); |
1ced966e PA |
556 | if (retval) |
557 | break; | |
52b98211 | 558 | } |
7fa2737c | 559 | |
52b98211 EZ |
560 | addr += size; |
561 | len -= size; | |
562 | } | |
7fa2737c MK |
563 | |
564 | return retval; | |
52b98211 EZ |
565 | } |
566 | ||
1ced966e PA |
567 | /* Update the inferior's debug registers with the new debug registers |
568 | state, in NEW_STATE, and then update our local mirror to match. */ | |
569 | ||
570 | static void | |
571 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
572 | { | |
4403d8e9 | 573 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
1ced966e PA |
574 | int i; |
575 | ||
576 | ALL_DEBUG_REGISTERS (i) | |
577 | { | |
4403d8e9 | 578 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
7b50312a | 579 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); |
1ced966e | 580 | else |
4403d8e9 | 581 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
582 | } |
583 | ||
4403d8e9 | 584 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
1ced966e PA |
585 | i386_dr_low.set_control (new_state->dr_control_mirror); |
586 | ||
4403d8e9 | 587 | *state = *new_state; |
1ced966e PA |
588 | } |
589 | ||
52b98211 EZ |
590 | /* Insert a watchpoint to watch a memory region which starts at |
591 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
592 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 593 | |
9bb9e8ad | 594 | static int |
0cf6dd15 TJB |
595 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type, |
596 | struct expression *cond) | |
52b98211 | 597 | { |
4403d8e9 | 598 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 599 | int retval; |
1ced966e PA |
600 | /* Work on a local copy of the debug registers, and on success, |
601 | commit the change back to the inferior. */ | |
4403d8e9 | 602 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 603 | |
85d721b8 PA |
604 | if (type == hw_read) |
605 | return 1; /* unsupported */ | |
606 | ||
e906b9a3 JS |
607 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
608 | || addr % len != 0) | |
1ced966e PA |
609 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
610 | WP_INSERT, addr, len, type); | |
52b98211 EZ |
611 | else |
612 | { | |
613 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
614 | ||
1ced966e PA |
615 | retval = i386_insert_aligned_watchpoint (&local_state, |
616 | addr, len_rw); | |
52b98211 EZ |
617 | } |
618 | ||
1ced966e PA |
619 | if (retval == 0) |
620 | i386_update_inferior_debug_regs (&local_state); | |
621 | ||
52b98211 | 622 | if (maint_show_dr) |
4403d8e9 | 623 | i386_show_dr (state, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
624 | |
625 | return retval; | |
626 | } | |
627 | ||
628 | /* Remove a watchpoint that watched the memory region which starts at | |
629 | address ADDR, whose length is LEN bytes, and for accesses of the | |
630 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 631 | static int |
0cf6dd15 TJB |
632 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type, |
633 | struct expression *cond) | |
52b98211 | 634 | { |
4403d8e9 | 635 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 636 | int retval; |
1ced966e PA |
637 | /* Work on a local copy of the debug registers, and on success, |
638 | commit the change back to the inferior. */ | |
4403d8e9 | 639 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 640 | |
e906b9a3 JS |
641 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
642 | || addr % len != 0) | |
1ced966e PA |
643 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
644 | WP_REMOVE, addr, len, type); | |
52b98211 EZ |
645 | else |
646 | { | |
647 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
648 | ||
1ced966e PA |
649 | retval = i386_remove_aligned_watchpoint (&local_state, |
650 | addr, len_rw); | |
52b98211 EZ |
651 | } |
652 | ||
1ced966e PA |
653 | if (retval == 0) |
654 | i386_update_inferior_debug_regs (&local_state); | |
655 | ||
52b98211 | 656 | if (maint_show_dr) |
4403d8e9 | 657 | i386_show_dr (state, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
658 | |
659 | return retval; | |
660 | } | |
661 | ||
662 | /* Return non-zero if we can watch a memory region that starts at | |
663 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 664 | |
9bb9e8ad | 665 | static int |
52b98211 EZ |
666 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
667 | { | |
4403d8e9 | 668 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
7fa2737c MK |
669 | int nregs; |
670 | ||
52b98211 EZ |
671 | /* Compute how many aligned watchpoints we would need to cover this |
672 | region. */ | |
4403d8e9 | 673 | nregs = i386_handle_nonaligned_watchpoint (state, |
1ced966e | 674 | WP_COUNT, addr, len, hw_write); |
52b98211 EZ |
675 | return nregs <= DR_NADDR ? 1 : 0; |
676 | } | |
677 | ||
4aa7a7f5 | 678 | /* If the inferior has some watchpoint that triggered, set the |
1777feb0 | 679 | address associated with that watchpoint and return non-zero. |
4aa7a7f5 | 680 | Otherwise, return zero. */ |
7fa2737c | 681 | |
9bb9e8ad | 682 | static int |
c03374d5 | 683 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 684 | { |
4403d8e9 | 685 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
7fa2737c | 686 | CORE_ADDR addr = 0; |
52b98211 | 687 | int i; |
4aa7a7f5 | 688 | int rc = 0; |
7b50312a PA |
689 | /* The current thread's DR_STATUS. We always need to read this to |
690 | check whether some watchpoint caused the trap. */ | |
1ced966e | 691 | unsigned status; |
7b50312a PA |
692 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
693 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
694 | unnecessary extra syscall when no watchpoint triggered. */ | |
695 | int control_p = 0; | |
696 | unsigned control = 0; | |
697 | ||
698 | /* In non-stop/async, threads can be running while we change the | |
4403d8e9 JK |
699 | STATE (and friends). Say, we set a watchpoint, and let threads |
700 | resume. Now, say you delete the watchpoint, or add/remove | |
701 | watchpoints such that STATE changes while threads are running. | |
702 | On targets that support non-stop, inserting/deleting watchpoints | |
703 | updates the STATE only. It does not update the real thread's | |
704 | debug registers; that's only done prior to resume. Instead, if | |
705 | threads are running when the mirror changes, a temporary and | |
706 | transparent stop on all threads is forced so they can get their | |
707 | copy of the debug registers updated on re-resume. Now, say, | |
708 | a thread hit a watchpoint before having been updated with the new | |
709 | STATE contents, and we haven't yet handled the corresponding | |
710 | SIGTRAP. If we trusted STATE below, we'd mistake the real | |
711 | trapped address (from the last time we had updated debug | |
712 | registers in the thread) with whatever was currently in STATE. | |
713 | So to fix this, STATE always represents intention, what we _want_ | |
714 | threads to have in debug registers. To get at the address and | |
715 | cause of the trap, we need to read the state the thread still has | |
716 | in its debug registers. | |
7b50312a PA |
717 | |
718 | In sum, always get the current debug register values the current | |
719 | thread has, instead of trusting the global mirror. If the thread | |
720 | was running when we last changed watchpoints, the mirror no | |
721 | longer represents what was set in this thread's debug | |
722 | registers. */ | |
723 | status = i386_dr_low.get_status (); | |
52b98211 EZ |
724 | |
725 | ALL_DEBUG_REGISTERS(i) | |
726 | { | |
7b50312a PA |
727 | if (!I386_DR_WATCH_HIT (status, i)) |
728 | continue; | |
729 | ||
730 | if (!control_p) | |
731 | { | |
732 | control = i386_dr_low.get_control (); | |
733 | control_p = 1; | |
734 | } | |
735 | ||
736 | /* This second condition makes sure DRi is set up for a data | |
737 | watchpoint, not a hardware breakpoint. The reason is that | |
738 | GDB doesn't call the target_stopped_data_address method | |
739 | except for data watchpoints. In other words, I'm being | |
740 | paranoiac. */ | |
741 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 742 | { |
7b50312a | 743 | addr = i386_dr_low.get_addr (i); |
4aa7a7f5 | 744 | rc = 1; |
52b98211 | 745 | if (maint_show_dr) |
4403d8e9 | 746 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
747 | } |
748 | } | |
7fa2737c | 749 | if (maint_show_dr && addr == 0) |
4403d8e9 | 750 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 751 | |
4aa7a7f5 JJ |
752 | if (rc) |
753 | *addr_p = addr; | |
754 | return rc; | |
755 | } | |
756 | ||
9bb9e8ad | 757 | static int |
4aa7a7f5 JJ |
758 | i386_stopped_by_watchpoint (void) |
759 | { | |
760 | CORE_ADDR addr = 0; | |
c03374d5 | 761 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
762 | } |
763 | ||
8181d85f DJ |
764 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
765 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 766 | static int |
a6d9a66e UW |
767 | i386_insert_hw_breakpoint (struct gdbarch *gdbarch, |
768 | struct bp_target_info *bp_tgt) | |
52b98211 | 769 | { |
4403d8e9 | 770 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 771 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 772 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
773 | /* Work on a local copy of the debug registers, and on success, |
774 | commit the change back to the inferior. */ | |
4403d8e9 | 775 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 776 | int retval = i386_insert_aligned_watchpoint (&local_state, |
1ced966e | 777 | addr, len_rw) ? EBUSY : 0; |
52b98211 | 778 | |
edcc485a MR |
779 | if (retval == 0) |
780 | i386_update_inferior_debug_regs (&local_state); | |
781 | ||
52b98211 | 782 | if (maint_show_dr) |
4403d8e9 | 783 | i386_show_dr (state, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
784 | |
785 | return retval; | |
786 | } | |
787 | ||
8181d85f DJ |
788 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
789 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 790 | |
9bb9e8ad | 791 | static int |
a6d9a66e UW |
792 | i386_remove_hw_breakpoint (struct gdbarch *gdbarch, |
793 | struct bp_target_info *bp_tgt) | |
52b98211 | 794 | { |
4403d8e9 | 795 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 796 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 797 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
798 | /* Work on a local copy of the debug registers, and on success, |
799 | commit the change back to the inferior. */ | |
4403d8e9 | 800 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 801 | int retval = i386_remove_aligned_watchpoint (&local_state, |
1ced966e | 802 | addr, len_rw); |
52b98211 | 803 | |
edcc485a MR |
804 | if (retval == 0) |
805 | i386_update_inferior_debug_regs (&local_state); | |
806 | ||
52b98211 | 807 | if (maint_show_dr) |
4403d8e9 | 808 | i386_show_dr (state, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
809 | |
810 | return retval; | |
811 | } | |
812 | ||
c03374d5 DJ |
813 | /* Returns the number of hardware watchpoints of type TYPE that we can |
814 | set. Value is positive if we can set CNT watchpoints, zero if | |
815 | setting watchpoints of type TYPE is not supported, and negative if | |
816 | CNT is more than the maximum number of watchpoints of type TYPE | |
817 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
818 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
819 | CNT is the number of such watchpoints used so far (including this | |
820 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
821 | currently enabled. | |
822 | ||
823 | We always return 1 here because we don't have enough information | |
824 | about possible overlap of addresses that they want to watch. As an | |
825 | extreme example, consider the case where all the watchpoints watch | |
826 | the same address and the same region length: then we can handle a | |
827 | virtually unlimited number of watchpoints, due to debug register | |
828 | sharing implemented via reference counts in i386-nat.c. */ | |
829 | ||
830 | static int | |
831 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
832 | { | |
833 | return 1; | |
834 | } | |
835 | ||
9bb9e8ad PM |
836 | static void |
837 | add_show_debug_regs_command (void) | |
838 | { | |
839 | /* A maintenance command to enable printing the internal DRi mirror | |
840 | variables. */ | |
841 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
842 | &maint_show_dr, _("\ | |
843 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
844 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
845 | Use \"on\" to enable, \"off\" to disable.\n\ | |
846 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
847 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
848 | triggers a breakpoint or watchpoint."), | |
849 | NULL, | |
850 | NULL, | |
851 | &maintenance_set_cmdlist, | |
852 | &maintenance_show_cmdlist); | |
853 | } | |
854 | ||
855 | /* There are only two global functions left. */ | |
856 | ||
c03374d5 DJ |
857 | void |
858 | i386_use_watchpoints (struct target_ops *t) | |
859 | { | |
860 | /* After a watchpoint trap, the PC points to the instruction after the | |
861 | one that caused the trap. Therefore we don't need to step over it. | |
862 | But we do need to reset the status register to avoid another trap. */ | |
863 | t->to_have_continuable_watchpoint = 1; | |
864 | ||
865 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
866 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
867 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
868 | t->to_stopped_data_address = i386_stopped_data_address; | |
869 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
870 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
871 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
872 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
d0d8b0c6 JK |
873 | |
874 | if (i386_inferior_data == NULL) | |
875 | i386_inferior_data | |
876 | = register_inferior_data_with_cleanup (i386_inferior_data_cleanup); | |
c03374d5 DJ |
877 | } |
878 | ||
52b98211 | 879 | void |
9bb9e8ad | 880 | i386_set_debug_register_length (int len) |
52b98211 | 881 | { |
9bb9e8ad PM |
882 | /* This function should be called only once for each native target. */ |
883 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
884 | gdb_assert (len == 4 || len == 8); | |
885 | i386_dr_low.debug_register_length = len; | |
886 | add_show_debug_regs_command (); | |
52b98211 | 887 | } |