Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
0b302171 JB |
3 | Copyright (C) 2001, 2004-2005, 2007-2012 Free Software Foundation, |
4 | Inc. | |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 | 20 | |
9bb9e8ad | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "defs.h" |
23 | #include "breakpoint.h" | |
24 | #include "command.h" | |
25 | #include "gdbcmd.h" | |
c03374d5 | 26 | #include "target.h" |
9bb9e8ad | 27 | #include "gdb_assert.h" |
4403d8e9 | 28 | #include "inferior.h" |
52b98211 | 29 | |
7fa2737c | 30 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
31 | debug registers. |
32 | ||
33 | This provides several functions for inserting and removing | |
7fa2737c MK |
34 | hardware-assisted breakpoints and watchpoints, testing if one or |
35 | more of the watchpoints triggered and at what address, checking | |
36 | whether a given region can be watched, etc. | |
37 | ||
7fa2737c MK |
38 | The functions below implement debug registers sharing by reference |
39 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 40 | |
9bb9e8ad PM |
41 | struct i386_dr_low_type i386_dr_low; |
42 | ||
52b98211 | 43 | |
e906b9a3 | 44 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 45 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 46 | |
52b98211 EZ |
47 | /* DR7 Debug Control register fields. */ |
48 | ||
49 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
50 | #define DR_CONTROL_SHIFT 16 | |
51 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
52 | #define DR_CONTROL_SIZE 4 | |
53 | ||
54 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
55 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
56 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
57 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
58 | |
59 | /* This is here for completeness. No platform supports this | |
7fa2737c | 60 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
61 | CR4 register needs to be set to support this. */ |
62 | #ifndef DR_RW_IORW | |
7fa2737c | 63 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
64 | #endif |
65 | ||
66 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
67 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
68 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
69 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
70 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
71 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
72 | |
73 | /* Local and Global Enable flags in DR7. | |
74 | ||
75 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
76 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
77 | clears this flag on every task switch. When the Global Enable flag |
78 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
79 | processor never clears this flag. | |
52b98211 EZ |
80 | |
81 | Currently, all watchpoint are locally enabled. If you need to | |
82 | enable them globally, read the comment which pertains to this in | |
83 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
84 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
85 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
86 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
87 | |
88 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
89 | flags). These are only required on i386, to allow detection of the | |
90 | exact instruction which caused a watchpoint to break; i486 and | |
91 | later processors do that automatically. We set these flags for | |
7fa2737c | 92 | backwards compatibility. */ |
52b98211 | 93 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 94 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
95 | |
96 | /* Fields reserved by Intel. This includes the GD (General Detect | |
97 | Enable) flag, which causes a debug exception to be generated when a | |
98 | MOV instruction accesses one of the debug registers. | |
99 | ||
100 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
101 | #define DR_CONTROL_RESERVED (0xFC00) | |
102 | ||
103 | /* Auxiliary helper macros. */ | |
104 | ||
105 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 106 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
107 | |
108 | /* The I'th debug register is vacant if its Local and Global Enable | |
109 | bits are reset in the Debug Control register. */ | |
1ced966e PA |
110 | #define I386_DR_VACANT(state, i) \ |
111 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
52b98211 EZ |
112 | |
113 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
114 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
115 | do { \ | |
116 | (state)->dr_control_mirror |= \ | |
117 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
118 | } while (0) | |
52b98211 EZ |
119 | |
120 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
121 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
122 | do { \ | |
123 | (state)->dr_control_mirror |= \ | |
124 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
125 | } while (0) | |
52b98211 EZ |
126 | |
127 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
128 | #define I386_DR_DISABLE(state, i) \ |
129 | do { \ | |
130 | (state)->dr_control_mirror &= \ | |
131 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
132 | } while (0) | |
52b98211 EZ |
133 | |
134 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 135 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 136 | do { \ |
1ced966e PA |
137 | (state)->dr_control_mirror &= \ |
138 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
139 | (state)->dr_control_mirror |= \ | |
140 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
141 | } while (0) |
142 | ||
143 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
144 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
145 | (((dr7) \ | |
146 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 | 147 | |
a79d3c27 JK |
148 | /* Mask that this I'th watchpoint has triggered. */ |
149 | #define I386_DR_WATCH_MASK(i) (1 << (i)) | |
150 | ||
52b98211 | 151 | /* Did the watchpoint whose address is in the I'th register break? */ |
1ced966e | 152 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
153 | |
154 | /* A macro to loop over all debug registers. */ | |
155 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
156 | ||
1ced966e PA |
157 | /* Clear the reference counts and forget everything we knew about the |
158 | debug registers. */ | |
159 | ||
160 | static void | |
161 | i386_init_dregs (struct i386_debug_reg_state *state) | |
162 | { | |
163 | int i; | |
164 | ||
165 | ALL_DEBUG_REGISTERS (i) | |
166 | { | |
167 | state->dr_mirror[i] = 0; | |
168 | state->dr_ref_count[i] = 0; | |
169 | } | |
170 | state->dr_control_mirror = 0; | |
171 | state->dr_status_mirror = 0; | |
172 | } | |
173 | ||
4403d8e9 JK |
174 | /* Per-inferior data key. */ |
175 | static const struct inferior_data *i386_inferior_data; | |
176 | ||
177 | /* Per-inferior data. */ | |
178 | struct i386_inferior_data | |
179 | { | |
180 | /* Copy of i386 hardware debug registers for performance reasons. */ | |
181 | struct i386_debug_reg_state state; | |
182 | }; | |
183 | ||
184 | /* Get data specific for INFERIOR_PTID LWP. Return special data area | |
185 | for processes being detached. */ | |
186 | ||
187 | static struct i386_inferior_data * | |
188 | i386_inferior_data_get (void) | |
189 | { | |
190 | /* Intermediate patch stub. */ | |
191 | static struct i386_inferior_data inf_data_local; | |
192 | struct inferior *inf = current_inferior (); | |
193 | struct i386_inferior_data *inf_data = &inf_data_local; | |
194 | ||
195 | if (inf->pid != ptid_get_pid (inferior_ptid)) | |
196 | { | |
197 | /* INFERIOR_PTID is being detached from the inferior INF. | |
198 | Provide local cache specific for the detached LWP. */ | |
199 | ||
200 | static struct i386_inferior_data detached_inf_data_local; | |
201 | static int detached_inf_pid = -1; | |
202 | ||
203 | if (detached_inf_pid != ptid_get_pid (inferior_ptid)) | |
204 | { | |
205 | /* Reinitialize the local cache if INFERIOR_PTID is | |
206 | different from the LWP last detached. | |
207 | ||
208 | Linux kernel before 2.6.33 commit | |
209 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
210 | will inherit hardware debug registers from parent | |
211 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
212 | zeroed debug registers. | |
213 | ||
214 | GDB will remove all breakpoints (and watchpoints) from the forked | |
215 | off process. We also need to reset the debug registers in that | |
216 | process to be compatible with the older Linux kernels. | |
217 | ||
218 | Copy the debug registers mirrors into the new process so that all | |
219 | breakpoints and watchpoints can be removed together. The debug | |
220 | registers mirror will become zeroed in the end before detaching | |
221 | the forked off process. */ | |
222 | ||
223 | detached_inf_pid = ptid_get_pid (inferior_ptid); | |
224 | detached_inf_data_local = *inf_data; | |
225 | } | |
226 | ||
227 | return &detached_inf_data_local; | |
228 | } | |
229 | ||
230 | return inf_data; | |
231 | } | |
232 | ||
233 | /* Get debug registers state for INFERIOR_PTID, see | |
234 | i386_inferior_data_get. */ | |
52b98211 | 235 | |
7b50312a PA |
236 | struct i386_debug_reg_state * |
237 | i386_debug_reg_state (void) | |
238 | { | |
4403d8e9 | 239 | return &i386_inferior_data_get ()->state; |
7b50312a PA |
240 | } |
241 | ||
52b98211 | 242 | /* Whether or not to print the mirrored debug registers. */ |
7fa2737c | 243 | static int maint_show_dr; |
52b98211 EZ |
244 | |
245 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
246 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
247 | ||
248 | /* Internal functions. */ | |
249 | ||
250 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
251 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
252 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
253 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
254 | ||
255 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
256 | according to the length of the region to watch. LEN_RW_BITS is the | |
257 | value of the bit-field from DR7 which describes the length and | |
258 | access type of the region to be watched by this watchpoint. Return | |
259 | 0 on success, -1 on failure. */ | |
1ced966e PA |
260 | static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
261 | CORE_ADDR addr, | |
52b98211 EZ |
262 | unsigned len_rw_bits); |
263 | ||
264 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
265 | according to the length of the region to watch. LEN_RW_BITS is the | |
266 | value of the bits from DR7 which describes the length and access | |
267 | type of the region watched by this watchpoint. Return 0 on | |
268 | success, -1 on failure. */ | |
1ced966e PA |
269 | static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
270 | CORE_ADDR addr, | |
52b98211 EZ |
271 | unsigned len_rw_bits); |
272 | ||
273 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
274 | number of debug registers required to watch a region at address | |
275 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
276 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
277 | about the number of registers, or -1 on failure. If WHAT is not a |
278 | valid value, bombs through internal_error. */ | |
1ced966e PA |
279 | static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
280 | i386_wp_op_t what, | |
52b98211 EZ |
281 | CORE_ADDR addr, int len, |
282 | enum target_hw_bp_type type); | |
283 | ||
284 | /* Implementation. */ | |
285 | ||
7fa2737c MK |
286 | /* Clear the reference counts and forget everything we knew about the |
287 | debug registers. */ | |
288 | ||
52b98211 EZ |
289 | void |
290 | i386_cleanup_dregs (void) | |
291 | { | |
4403d8e9 JK |
292 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
293 | ||
294 | i386_init_dregs (state); | |
52b98211 EZ |
295 | } |
296 | ||
7fa2737c MK |
297 | /* Print the values of the mirrored debug registers. This is called |
298 | when maint_show_dr is non-zero. To set that up, type "maint | |
299 | show-debug-regs" at GDB's prompt. */ | |
300 | ||
52b98211 | 301 | static void |
1ced966e PA |
302 | i386_show_dr (struct i386_debug_reg_state *state, |
303 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
304 | int len, enum target_hw_bp_type type) |
305 | { | |
5af949e3 | 306 | int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; |
52b98211 EZ |
307 | int i; |
308 | ||
309 | puts_unfiltered (func); | |
310 | if (addr || len) | |
311 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
312 | /* This code is for ia32, so casting CORE_ADDR | |
313 | to unsigned long should be okay. */ | |
314 | (unsigned long)addr, len, | |
315 | type == hw_write ? "data-write" | |
316 | : (type == hw_read ? "data-read" | |
317 | : (type == hw_access ? "data-read/write" | |
318 | : (type == hw_execute ? "instruction-execute" | |
319 | /* FIXME: if/when I/O read/write | |
320 | watchpoints are supported, add them | |
321 | here. */ | |
322 | : "??unknown??")))); | |
323 | puts_unfiltered (":\n"); | |
9bb9e8ad | 324 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
1ced966e PA |
325 | phex (state->dr_control_mirror, 8), |
326 | phex (state->dr_status_mirror, 8)); | |
52b98211 EZ |
327 | ALL_DEBUG_REGISTERS(i) |
328 | { | |
7fa2737c MK |
329 | printf_unfiltered ("\ |
330 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
1ced966e PA |
331 | i, phex (state->dr_mirror[i], addr_size), |
332 | state->dr_ref_count[i], | |
333 | i + 1, phex (state->dr_mirror[i + 1], addr_size), | |
334 | state->dr_ref_count[i+1]); | |
52b98211 EZ |
335 | i++; |
336 | } | |
337 | } | |
338 | ||
339 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
340 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
341 | have the value of 1, 2, or 4. */ | |
342 | ||
52b98211 EZ |
343 | static unsigned |
344 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
345 | { | |
346 | unsigned rw; | |
347 | ||
348 | switch (type) | |
349 | { | |
350 | case hw_execute: | |
351 | rw = DR_RW_EXECUTE; | |
352 | break; | |
353 | case hw_write: | |
354 | rw = DR_RW_WRITE; | |
355 | break; | |
7fa2737c | 356 | case hw_read: |
85d721b8 | 357 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
358 | _("The i386 doesn't support " |
359 | "data-read watchpoints.\n")); | |
52b98211 EZ |
360 | case hw_access: |
361 | rw = DR_RW_READ; | |
362 | break; | |
363 | #if 0 | |
7fa2737c MK |
364 | /* Not yet supported. */ |
365 | case hw_io_access: | |
52b98211 EZ |
366 | rw = DR_RW_IORW; |
367 | break; | |
368 | #endif | |
369 | default: | |
e2e0b3e5 AC |
370 | internal_error (__FILE__, __LINE__, _("\ |
371 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 372 | (int) type); |
52b98211 EZ |
373 | } |
374 | ||
375 | switch (len) | |
376 | { | |
52b98211 EZ |
377 | case 1: |
378 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
379 | case 2: |
380 | return (DR_LEN_2 | rw); | |
381 | case 4: | |
382 | return (DR_LEN_4 | rw); | |
383 | case 8: | |
384 | if (TARGET_HAS_DR_LEN_8) | |
385 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 386 | /* ELSE FALL THROUGH */ |
52b98211 | 387 | default: |
e2e0b3e5 AC |
388 | internal_error (__FILE__, __LINE__, _("\ |
389 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
390 | } |
391 | } | |
392 | ||
393 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
394 | according to the length of the region to watch. LEN_RW_BITS is the | |
395 | value of the bits from DR7 which describes the length and access | |
396 | type of the region to be watched by this watchpoint. Return 0 on | |
397 | success, -1 on failure. */ | |
7fa2737c | 398 | |
52b98211 | 399 | static int |
1ced966e PA |
400 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
401 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
402 | { |
403 | int i; | |
404 | ||
9bb9e8ad PM |
405 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
406 | return -1; | |
407 | ||
52b98211 EZ |
408 | /* First, look for an occupied debug register with the same address |
409 | and the same RW and LEN definitions. If we find one, we can | |
410 | reuse it for this watchpoint as well (and save a register). */ | |
411 | ALL_DEBUG_REGISTERS(i) | |
412 | { | |
1ced966e PA |
413 | if (!I386_DR_VACANT (state, i) |
414 | && state->dr_mirror[i] == addr | |
415 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 416 | { |
1ced966e | 417 | state->dr_ref_count[i]++; |
52b98211 EZ |
418 | return 0; |
419 | } | |
420 | } | |
421 | ||
422 | /* Next, look for a vacant debug register. */ | |
423 | ALL_DEBUG_REGISTERS(i) | |
424 | { | |
1ced966e | 425 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
426 | break; |
427 | } | |
428 | ||
429 | /* No more debug registers! */ | |
430 | if (i >= DR_NADDR) | |
431 | return -1; | |
432 | ||
433 | /* Now set up the register I to watch our region. */ | |
434 | ||
435 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
436 | state->dr_mirror[i] = addr; |
437 | state->dr_ref_count[i] = 1; | |
438 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 439 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 440 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
441 | watchpoints; however, if any target would want that in the |
442 | future, GDB should probably provide a command to control whether | |
443 | to enable watchpoints globally or locally, and the code below | |
444 | should use global or local enable and slow-down flags as | |
445 | appropriate. */ | |
1ced966e PA |
446 | I386_DR_LOCAL_ENABLE (state, i); |
447 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
448 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 449 | |
52b98211 EZ |
450 | return 0; |
451 | } | |
452 | ||
453 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
454 | according to the length of the region to watch. LEN_RW_BITS is the | |
455 | value of the bits from DR7 which describes the length and access | |
456 | type of the region watched by this watchpoint. Return 0 on | |
457 | success, -1 on failure. */ | |
7fa2737c | 458 | |
52b98211 | 459 | static int |
1ced966e PA |
460 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
461 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
462 | { |
463 | int i, retval = -1; | |
464 | ||
465 | ALL_DEBUG_REGISTERS(i) | |
466 | { | |
1ced966e PA |
467 | if (!I386_DR_VACANT (state, i) |
468 | && state->dr_mirror[i] == addr | |
469 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 470 | { |
1ced966e | 471 | if (--state->dr_ref_count[i] == 0) /* no longer in use? */ |
52b98211 EZ |
472 | { |
473 | /* Reset our mirror. */ | |
1ced966e PA |
474 | state->dr_mirror[i] = 0; |
475 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
476 | } |
477 | retval = 0; | |
478 | } | |
479 | } | |
480 | ||
481 | return retval; | |
482 | } | |
483 | ||
484 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
485 | number of debug registers required to watch a region at address | |
486 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
487 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
488 | about the number of registers, or -1 on failure. If WHAT is not a |
489 | valid value, bombs through internal_error. */ | |
490 | ||
52b98211 | 491 | static int |
1ced966e PA |
492 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
493 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
494 | enum target_hw_bp_type type) |
495 | { | |
1ced966e | 496 | int retval = 0; |
e906b9a3 | 497 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 498 | |
e906b9a3 | 499 | static int size_try_array[8][8] = |
52b98211 | 500 | { |
7fa2737c MK |
501 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
502 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
503 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
504 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
505 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
506 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
507 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
508 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
509 | }; |
510 | ||
511 | while (len > 0) | |
512 | { | |
7fa2737c | 513 | int align = addr % max_wp_len; |
f2e7c15d | 514 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 515 | can watch. */ |
7fa2737c MK |
516 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
517 | int size = size_try_array[try][align]; | |
518 | ||
52b98211 | 519 | if (what == WP_COUNT) |
7fa2737c MK |
520 | { |
521 | /* size_try_array[] is defined such that each iteration | |
522 | through the loop is guaranteed to produce an address and a | |
523 | size that can be watched with a single debug register. | |
524 | Thus, for counting the registers required to watch a | |
525 | region, we simply need to increment the count on each | |
526 | iteration. */ | |
527 | retval++; | |
528 | } | |
52b98211 EZ |
529 | else |
530 | { | |
531 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
532 | ||
533 | if (what == WP_INSERT) | |
1ced966e | 534 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 535 | else if (what == WP_REMOVE) |
1ced966e | 536 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 537 | else |
e2e0b3e5 AC |
538 | internal_error (__FILE__, __LINE__, _("\ |
539 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 | 540 | (int)what); |
1ced966e PA |
541 | if (retval) |
542 | break; | |
52b98211 | 543 | } |
7fa2737c | 544 | |
52b98211 EZ |
545 | addr += size; |
546 | len -= size; | |
547 | } | |
7fa2737c MK |
548 | |
549 | return retval; | |
52b98211 EZ |
550 | } |
551 | ||
1ced966e PA |
552 | /* Update the inferior's debug registers with the new debug registers |
553 | state, in NEW_STATE, and then update our local mirror to match. */ | |
554 | ||
555 | static void | |
556 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
557 | { | |
4403d8e9 | 558 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
1ced966e PA |
559 | int i; |
560 | ||
561 | ALL_DEBUG_REGISTERS (i) | |
562 | { | |
4403d8e9 | 563 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) |
7b50312a | 564 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); |
1ced966e | 565 | else |
4403d8e9 | 566 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); |
1ced966e PA |
567 | } |
568 | ||
4403d8e9 | 569 | if (new_state->dr_control_mirror != state->dr_control_mirror) |
1ced966e PA |
570 | i386_dr_low.set_control (new_state->dr_control_mirror); |
571 | ||
4403d8e9 | 572 | *state = *new_state; |
1ced966e PA |
573 | } |
574 | ||
52b98211 EZ |
575 | /* Insert a watchpoint to watch a memory region which starts at |
576 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
577 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 578 | |
9bb9e8ad | 579 | static int |
0cf6dd15 TJB |
580 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type, |
581 | struct expression *cond) | |
52b98211 | 582 | { |
4403d8e9 | 583 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 584 | int retval; |
1ced966e PA |
585 | /* Work on a local copy of the debug registers, and on success, |
586 | commit the change back to the inferior. */ | |
4403d8e9 | 587 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 588 | |
85d721b8 PA |
589 | if (type == hw_read) |
590 | return 1; /* unsupported */ | |
591 | ||
e906b9a3 JS |
592 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
593 | || addr % len != 0) | |
1ced966e PA |
594 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
595 | WP_INSERT, addr, len, type); | |
52b98211 EZ |
596 | else |
597 | { | |
598 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
599 | ||
1ced966e PA |
600 | retval = i386_insert_aligned_watchpoint (&local_state, |
601 | addr, len_rw); | |
52b98211 EZ |
602 | } |
603 | ||
1ced966e PA |
604 | if (retval == 0) |
605 | i386_update_inferior_debug_regs (&local_state); | |
606 | ||
52b98211 | 607 | if (maint_show_dr) |
4403d8e9 | 608 | i386_show_dr (state, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
609 | |
610 | return retval; | |
611 | } | |
612 | ||
613 | /* Remove a watchpoint that watched the memory region which starts at | |
614 | address ADDR, whose length is LEN bytes, and for accesses of the | |
615 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 616 | static int |
0cf6dd15 TJB |
617 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type, |
618 | struct expression *cond) | |
52b98211 | 619 | { |
4403d8e9 | 620 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 621 | int retval; |
1ced966e PA |
622 | /* Work on a local copy of the debug registers, and on success, |
623 | commit the change back to the inferior. */ | |
4403d8e9 | 624 | struct i386_debug_reg_state local_state = *state; |
52b98211 | 625 | |
e906b9a3 JS |
626 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
627 | || addr % len != 0) | |
1ced966e PA |
628 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
629 | WP_REMOVE, addr, len, type); | |
52b98211 EZ |
630 | else |
631 | { | |
632 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
633 | ||
1ced966e PA |
634 | retval = i386_remove_aligned_watchpoint (&local_state, |
635 | addr, len_rw); | |
52b98211 EZ |
636 | } |
637 | ||
1ced966e PA |
638 | if (retval == 0) |
639 | i386_update_inferior_debug_regs (&local_state); | |
640 | ||
52b98211 | 641 | if (maint_show_dr) |
4403d8e9 | 642 | i386_show_dr (state, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
643 | |
644 | return retval; | |
645 | } | |
646 | ||
647 | /* Return non-zero if we can watch a memory region that starts at | |
648 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 649 | |
9bb9e8ad | 650 | static int |
52b98211 EZ |
651 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
652 | { | |
4403d8e9 | 653 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
7fa2737c MK |
654 | int nregs; |
655 | ||
52b98211 EZ |
656 | /* Compute how many aligned watchpoints we would need to cover this |
657 | region. */ | |
4403d8e9 | 658 | nregs = i386_handle_nonaligned_watchpoint (state, |
1ced966e | 659 | WP_COUNT, addr, len, hw_write); |
52b98211 EZ |
660 | return nregs <= DR_NADDR ? 1 : 0; |
661 | } | |
662 | ||
4aa7a7f5 | 663 | /* If the inferior has some watchpoint that triggered, set the |
1777feb0 | 664 | address associated with that watchpoint and return non-zero. |
4aa7a7f5 | 665 | Otherwise, return zero. */ |
7fa2737c | 666 | |
9bb9e8ad | 667 | static int |
c03374d5 | 668 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 669 | { |
4403d8e9 | 670 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
7fa2737c | 671 | CORE_ADDR addr = 0; |
52b98211 | 672 | int i; |
4aa7a7f5 | 673 | int rc = 0; |
7b50312a PA |
674 | /* The current thread's DR_STATUS. We always need to read this to |
675 | check whether some watchpoint caused the trap. */ | |
1ced966e | 676 | unsigned status; |
7b50312a PA |
677 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
678 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
679 | unnecessary extra syscall when no watchpoint triggered. */ | |
680 | int control_p = 0; | |
681 | unsigned control = 0; | |
682 | ||
683 | /* In non-stop/async, threads can be running while we change the | |
4403d8e9 JK |
684 | STATE (and friends). Say, we set a watchpoint, and let threads |
685 | resume. Now, say you delete the watchpoint, or add/remove | |
686 | watchpoints such that STATE changes while threads are running. | |
687 | On targets that support non-stop, inserting/deleting watchpoints | |
688 | updates the STATE only. It does not update the real thread's | |
689 | debug registers; that's only done prior to resume. Instead, if | |
690 | threads are running when the mirror changes, a temporary and | |
691 | transparent stop on all threads is forced so they can get their | |
692 | copy of the debug registers updated on re-resume. Now, say, | |
693 | a thread hit a watchpoint before having been updated with the new | |
694 | STATE contents, and we haven't yet handled the corresponding | |
695 | SIGTRAP. If we trusted STATE below, we'd mistake the real | |
696 | trapped address (from the last time we had updated debug | |
697 | registers in the thread) with whatever was currently in STATE. | |
698 | So to fix this, STATE always represents intention, what we _want_ | |
699 | threads to have in debug registers. To get at the address and | |
700 | cause of the trap, we need to read the state the thread still has | |
701 | in its debug registers. | |
7b50312a PA |
702 | |
703 | In sum, always get the current debug register values the current | |
704 | thread has, instead of trusting the global mirror. If the thread | |
705 | was running when we last changed watchpoints, the mirror no | |
706 | longer represents what was set in this thread's debug | |
707 | registers. */ | |
708 | status = i386_dr_low.get_status (); | |
52b98211 EZ |
709 | |
710 | ALL_DEBUG_REGISTERS(i) | |
711 | { | |
7b50312a PA |
712 | if (!I386_DR_WATCH_HIT (status, i)) |
713 | continue; | |
714 | ||
715 | if (!control_p) | |
716 | { | |
717 | control = i386_dr_low.get_control (); | |
718 | control_p = 1; | |
719 | } | |
720 | ||
721 | /* This second condition makes sure DRi is set up for a data | |
722 | watchpoint, not a hardware breakpoint. The reason is that | |
723 | GDB doesn't call the target_stopped_data_address method | |
724 | except for data watchpoints. In other words, I'm being | |
725 | paranoiac. */ | |
726 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 727 | { |
7b50312a | 728 | addr = i386_dr_low.get_addr (i); |
4aa7a7f5 | 729 | rc = 1; |
52b98211 | 730 | if (maint_show_dr) |
4403d8e9 | 731 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
732 | } |
733 | } | |
7fa2737c | 734 | if (maint_show_dr && addr == 0) |
4403d8e9 | 735 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 736 | |
4aa7a7f5 JJ |
737 | if (rc) |
738 | *addr_p = addr; | |
739 | return rc; | |
740 | } | |
741 | ||
9bb9e8ad | 742 | static int |
4aa7a7f5 JJ |
743 | i386_stopped_by_watchpoint (void) |
744 | { | |
745 | CORE_ADDR addr = 0; | |
c03374d5 | 746 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
747 | } |
748 | ||
8181d85f DJ |
749 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
750 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 751 | static int |
a6d9a66e UW |
752 | i386_insert_hw_breakpoint (struct gdbarch *gdbarch, |
753 | struct bp_target_info *bp_tgt) | |
52b98211 | 754 | { |
4403d8e9 | 755 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 756 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 757 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
758 | /* Work on a local copy of the debug registers, and on success, |
759 | commit the change back to the inferior. */ | |
4403d8e9 | 760 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 761 | int retval = i386_insert_aligned_watchpoint (&local_state, |
1ced966e | 762 | addr, len_rw) ? EBUSY : 0; |
52b98211 | 763 | |
edcc485a MR |
764 | if (retval == 0) |
765 | i386_update_inferior_debug_regs (&local_state); | |
766 | ||
52b98211 | 767 | if (maint_show_dr) |
4403d8e9 | 768 | i386_show_dr (state, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
769 | |
770 | return retval; | |
771 | } | |
772 | ||
8181d85f DJ |
773 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
774 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 775 | |
9bb9e8ad | 776 | static int |
a6d9a66e UW |
777 | i386_remove_hw_breakpoint (struct gdbarch *gdbarch, |
778 | struct bp_target_info *bp_tgt) | |
52b98211 | 779 | { |
4403d8e9 | 780 | struct i386_debug_reg_state *state = i386_debug_reg_state (); |
52b98211 | 781 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); |
8181d85f | 782 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
783 | /* Work on a local copy of the debug registers, and on success, |
784 | commit the change back to the inferior. */ | |
4403d8e9 | 785 | struct i386_debug_reg_state local_state = *state; |
edcc485a | 786 | int retval = i386_remove_aligned_watchpoint (&local_state, |
1ced966e | 787 | addr, len_rw); |
52b98211 | 788 | |
edcc485a MR |
789 | if (retval == 0) |
790 | i386_update_inferior_debug_regs (&local_state); | |
791 | ||
52b98211 | 792 | if (maint_show_dr) |
4403d8e9 | 793 | i386_show_dr (state, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
794 | |
795 | return retval; | |
796 | } | |
797 | ||
c03374d5 DJ |
798 | /* Returns the number of hardware watchpoints of type TYPE that we can |
799 | set. Value is positive if we can set CNT watchpoints, zero if | |
800 | setting watchpoints of type TYPE is not supported, and negative if | |
801 | CNT is more than the maximum number of watchpoints of type TYPE | |
802 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
803 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
804 | CNT is the number of such watchpoints used so far (including this | |
805 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
806 | currently enabled. | |
807 | ||
808 | We always return 1 here because we don't have enough information | |
809 | about possible overlap of addresses that they want to watch. As an | |
810 | extreme example, consider the case where all the watchpoints watch | |
811 | the same address and the same region length: then we can handle a | |
812 | virtually unlimited number of watchpoints, due to debug register | |
813 | sharing implemented via reference counts in i386-nat.c. */ | |
814 | ||
815 | static int | |
816 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
817 | { | |
818 | return 1; | |
819 | } | |
820 | ||
9bb9e8ad PM |
821 | static void |
822 | add_show_debug_regs_command (void) | |
823 | { | |
824 | /* A maintenance command to enable printing the internal DRi mirror | |
825 | variables. */ | |
826 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
827 | &maint_show_dr, _("\ | |
828 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
829 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
830 | Use \"on\" to enable, \"off\" to disable.\n\ | |
831 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
832 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
833 | triggers a breakpoint or watchpoint."), | |
834 | NULL, | |
835 | NULL, | |
836 | &maintenance_set_cmdlist, | |
837 | &maintenance_show_cmdlist); | |
838 | } | |
839 | ||
840 | /* There are only two global functions left. */ | |
841 | ||
c03374d5 DJ |
842 | void |
843 | i386_use_watchpoints (struct target_ops *t) | |
844 | { | |
845 | /* After a watchpoint trap, the PC points to the instruction after the | |
846 | one that caused the trap. Therefore we don't need to step over it. | |
847 | But we do need to reset the status register to avoid another trap. */ | |
848 | t->to_have_continuable_watchpoint = 1; | |
849 | ||
850 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
851 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
852 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
853 | t->to_stopped_data_address = i386_stopped_data_address; | |
854 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
855 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
856 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
857 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
858 | } | |
859 | ||
52b98211 | 860 | void |
9bb9e8ad | 861 | i386_set_debug_register_length (int len) |
52b98211 | 862 | { |
9bb9e8ad PM |
863 | /* This function should be called only once for each native target. */ |
864 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
865 | gdb_assert (len == 4 || len == 8); | |
866 | i386_dr_low.debug_register_length = len; | |
867 | add_show_debug_regs_command (); | |
52b98211 | 868 | } |