Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
0fb0cc75 JB |
3 | Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 EZ |
20 | |
21 | #include "defs.h" | |
22 | #include "breakpoint.h" | |
23 | #include "command.h" | |
24 | #include "gdbcmd.h" | |
c03374d5 | 25 | #include "target.h" |
52b98211 | 26 | |
7fa2737c | 27 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
28 | debug registers. |
29 | ||
30 | This provides several functions for inserting and removing | |
7fa2737c MK |
31 | hardware-assisted breakpoints and watchpoints, testing if one or |
32 | more of the watchpoints triggered and at what address, checking | |
33 | whether a given region can be watched, etc. | |
34 | ||
35 | A target which wants to use these functions should define several | |
36 | macros, such as `target_insert_watchpoint' and | |
37 | `target_stopped_data_address', listed in target.h, to call the | |
38 | appropriate functions below. It should also define | |
52b98211 EZ |
39 | I386_USE_GENERIC_WATCHPOINTS in its tm.h file. |
40 | ||
7fa2737c MK |
41 | In addition, each target should provide several low-level macros |
42 | that will be called to insert watchpoints and hardware breakpoints | |
43 | into the inferior, remove them, and check their status. These | |
44 | macros are: | |
52b98211 EZ |
45 | |
46 | I386_DR_LOW_SET_CONTROL -- set the debug control (DR7) | |
47 | register to a given value | |
48 | ||
49 | I386_DR_LOW_SET_ADDR -- put an address into one debug | |
50 | register | |
51 | ||
52 | I386_DR_LOW_RESET_ADDR -- reset the address stored in | |
53 | one debug register | |
54 | ||
55 | I386_DR_LOW_GET_STATUS -- return the value of the debug | |
56 | status (DR6) register. | |
57 | ||
7fa2737c MK |
58 | The functions below implement debug registers sharing by reference |
59 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 EZ |
60 | |
61 | #ifdef I386_USE_GENERIC_WATCHPOINTS | |
62 | ||
e906b9a3 JS |
63 | /* Support for 8-byte wide hw watchpoints. */ |
64 | #ifndef TARGET_HAS_DR_LEN_8 | |
7fa2737c | 65 | #define TARGET_HAS_DR_LEN_8 0 |
e906b9a3 JS |
66 | #endif |
67 | ||
52b98211 | 68 | /* Debug registers' indices. */ |
7fa2737c MK |
69 | #define DR_NADDR 4 /* The number of debug address registers. */ |
70 | #define DR_STATUS 6 /* Index of debug status register (DR6). */ | |
71 | #define DR_CONTROL 7 /* Index of debug control register (DR7). */ | |
52b98211 EZ |
72 | |
73 | /* DR7 Debug Control register fields. */ | |
74 | ||
75 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
76 | #define DR_CONTROL_SHIFT 16 | |
77 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
78 | #define DR_CONTROL_SIZE 4 | |
79 | ||
80 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
81 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
82 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
83 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
84 | |
85 | /* This is here for completeness. No platform supports this | |
7fa2737c | 86 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
87 | CR4 register needs to be set to support this. */ |
88 | #ifndef DR_RW_IORW | |
7fa2737c | 89 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
90 | #endif |
91 | ||
92 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
93 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
94 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
95 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
96 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
97 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
98 | |
99 | /* Local and Global Enable flags in DR7. | |
100 | ||
101 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
102 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
103 | clears this flag on every task switch. When the Global Enable flag |
104 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
105 | processor never clears this flag. | |
52b98211 EZ |
106 | |
107 | Currently, all watchpoint are locally enabled. If you need to | |
108 | enable them globally, read the comment which pertains to this in | |
109 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
110 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
111 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
112 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
113 | |
114 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
115 | flags). These are only required on i386, to allow detection of the | |
116 | exact instruction which caused a watchpoint to break; i486 and | |
117 | later processors do that automatically. We set these flags for | |
7fa2737c | 118 | backwards compatibility. */ |
52b98211 | 119 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 120 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
121 | |
122 | /* Fields reserved by Intel. This includes the GD (General Detect | |
123 | Enable) flag, which causes a debug exception to be generated when a | |
124 | MOV instruction accesses one of the debug registers. | |
125 | ||
126 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
127 | #define DR_CONTROL_RESERVED (0xFC00) | |
128 | ||
129 | /* Auxiliary helper macros. */ | |
130 | ||
131 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 132 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
133 | |
134 | /* The I'th debug register is vacant if its Local and Global Enable | |
135 | bits are reset in the Debug Control register. */ | |
136 | #define I386_DR_VACANT(i) \ | |
137 | ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
138 | ||
139 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
140 | #define I386_DR_LOCAL_ENABLE(i) \ | |
141 | dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) | |
142 | ||
143 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
144 | #define I386_DR_GLOBAL_ENABLE(i) \ | |
145 | dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) | |
146 | ||
147 | /* Disable the break/watchpoint in the I'th debug register. */ | |
148 | #define I386_DR_DISABLE(i) \ | |
149 | dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i))) | |
150 | ||
151 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
152 | #define I386_DR_SET_RW_LEN(i,rwlen) \ | |
153 | do { \ | |
154 | dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ | |
155 | dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ | |
156 | } while (0) | |
157 | ||
158 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
159 | #define I386_DR_GET_RW_LEN(i) \ | |
160 | ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
161 | ||
162 | /* Did the watchpoint whose address is in the I'th register break? */ | |
163 | #define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i))) | |
164 | ||
165 | /* A macro to loop over all debug registers. */ | |
166 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
167 | ||
168 | /* Mirror the inferior's DRi registers. We keep the status and | |
169 | control registers separated because they don't hold addresses. */ | |
170 | static CORE_ADDR dr_mirror[DR_NADDR]; | |
7fa2737c | 171 | static unsigned dr_status_mirror, dr_control_mirror; |
52b98211 EZ |
172 | |
173 | /* Reference counts for each debug register. */ | |
7fa2737c | 174 | static int dr_ref_count[DR_NADDR]; |
52b98211 EZ |
175 | |
176 | /* Whether or not to print the mirrored debug registers. */ | |
7fa2737c | 177 | static int maint_show_dr; |
52b98211 EZ |
178 | |
179 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
180 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
181 | ||
182 | /* Internal functions. */ | |
183 | ||
184 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
185 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
186 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
187 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
188 | ||
189 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
190 | according to the length of the region to watch. LEN_RW_BITS is the | |
191 | value of the bit-field from DR7 which describes the length and | |
192 | access type of the region to be watched by this watchpoint. Return | |
193 | 0 on success, -1 on failure. */ | |
194 | static int i386_insert_aligned_watchpoint (CORE_ADDR addr, | |
195 | unsigned len_rw_bits); | |
196 | ||
197 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
198 | according to the length of the region to watch. LEN_RW_BITS is the | |
199 | value of the bits from DR7 which describes the length and access | |
200 | type of the region watched by this watchpoint. Return 0 on | |
201 | success, -1 on failure. */ | |
202 | static int i386_remove_aligned_watchpoint (CORE_ADDR addr, | |
203 | unsigned len_rw_bits); | |
204 | ||
205 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
206 | number of debug registers required to watch a region at address | |
207 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
208 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
209 | about the number of registers, or -1 on failure. If WHAT is not a |
210 | valid value, bombs through internal_error. */ | |
52b98211 EZ |
211 | static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what, |
212 | CORE_ADDR addr, int len, | |
213 | enum target_hw_bp_type type); | |
214 | ||
215 | /* Implementation. */ | |
216 | ||
7fa2737c MK |
217 | /* Clear the reference counts and forget everything we knew about the |
218 | debug registers. */ | |
219 | ||
52b98211 EZ |
220 | void |
221 | i386_cleanup_dregs (void) | |
222 | { | |
223 | int i; | |
224 | ||
225 | ALL_DEBUG_REGISTERS(i) | |
226 | { | |
227 | dr_mirror[i] = 0; | |
228 | dr_ref_count[i] = 0; | |
229 | } | |
230 | dr_control_mirror = 0; | |
231 | dr_status_mirror = 0; | |
232 | } | |
233 | ||
7fa2737c MK |
234 | /* Print the values of the mirrored debug registers. This is called |
235 | when maint_show_dr is non-zero. To set that up, type "maint | |
236 | show-debug-regs" at GDB's prompt. */ | |
237 | ||
52b98211 EZ |
238 | static void |
239 | i386_show_dr (const char *func, CORE_ADDR addr, | |
240 | int len, enum target_hw_bp_type type) | |
241 | { | |
242 | int i; | |
243 | ||
244 | puts_unfiltered (func); | |
245 | if (addr || len) | |
246 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
247 | /* This code is for ia32, so casting CORE_ADDR | |
248 | to unsigned long should be okay. */ | |
249 | (unsigned long)addr, len, | |
250 | type == hw_write ? "data-write" | |
251 | : (type == hw_read ? "data-read" | |
252 | : (type == hw_access ? "data-read/write" | |
253 | : (type == hw_execute ? "instruction-execute" | |
254 | /* FIXME: if/when I/O read/write | |
255 | watchpoints are supported, add them | |
256 | here. */ | |
257 | : "??unknown??")))); | |
258 | puts_unfiltered (":\n"); | |
259 | printf_unfiltered ("\tCONTROL (DR7): %08x STATUS (DR6): %08x\n", | |
260 | dr_control_mirror, dr_status_mirror); | |
261 | ALL_DEBUG_REGISTERS(i) | |
262 | { | |
7fa2737c MK |
263 | printf_unfiltered ("\ |
264 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
e906b9a3 JS |
265 | i, paddr(dr_mirror[i]), dr_ref_count[i], |
266 | i+1, paddr(dr_mirror[i+1]), dr_ref_count[i+1]); | |
52b98211 EZ |
267 | i++; |
268 | } | |
269 | } | |
270 | ||
271 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
272 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
273 | have the value of 1, 2, or 4. */ | |
274 | ||
52b98211 EZ |
275 | static unsigned |
276 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
277 | { | |
278 | unsigned rw; | |
279 | ||
280 | switch (type) | |
281 | { | |
282 | case hw_execute: | |
283 | rw = DR_RW_EXECUTE; | |
284 | break; | |
285 | case hw_write: | |
286 | rw = DR_RW_WRITE; | |
287 | break; | |
7fa2737c MK |
288 | case hw_read: |
289 | /* The i386 doesn't support data-read watchpoints. */ | |
52b98211 EZ |
290 | case hw_access: |
291 | rw = DR_RW_READ; | |
292 | break; | |
293 | #if 0 | |
7fa2737c MK |
294 | /* Not yet supported. */ |
295 | case hw_io_access: | |
52b98211 EZ |
296 | rw = DR_RW_IORW; |
297 | break; | |
298 | #endif | |
299 | default: | |
e2e0b3e5 AC |
300 | internal_error (__FILE__, __LINE__, _("\ |
301 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 302 | (int) type); |
52b98211 EZ |
303 | } |
304 | ||
305 | switch (len) | |
306 | { | |
52b98211 EZ |
307 | case 1: |
308 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
309 | case 2: |
310 | return (DR_LEN_2 | rw); | |
311 | case 4: | |
312 | return (DR_LEN_4 | rw); | |
313 | case 8: | |
314 | if (TARGET_HAS_DR_LEN_8) | |
315 | return (DR_LEN_8 | rw); | |
52b98211 | 316 | default: |
e2e0b3e5 AC |
317 | internal_error (__FILE__, __LINE__, _("\ |
318 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
319 | } |
320 | } | |
321 | ||
322 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
323 | according to the length of the region to watch. LEN_RW_BITS is the | |
324 | value of the bits from DR7 which describes the length and access | |
325 | type of the region to be watched by this watchpoint. Return 0 on | |
326 | success, -1 on failure. */ | |
7fa2737c | 327 | |
52b98211 EZ |
328 | static int |
329 | i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) | |
330 | { | |
331 | int i; | |
332 | ||
333 | /* First, look for an occupied debug register with the same address | |
334 | and the same RW and LEN definitions. If we find one, we can | |
335 | reuse it for this watchpoint as well (and save a register). */ | |
336 | ALL_DEBUG_REGISTERS(i) | |
337 | { | |
338 | if (!I386_DR_VACANT (i) | |
339 | && dr_mirror[i] == addr | |
340 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) | |
341 | { | |
342 | dr_ref_count[i]++; | |
343 | return 0; | |
344 | } | |
345 | } | |
346 | ||
347 | /* Next, look for a vacant debug register. */ | |
348 | ALL_DEBUG_REGISTERS(i) | |
349 | { | |
350 | if (I386_DR_VACANT (i)) | |
351 | break; | |
352 | } | |
353 | ||
354 | /* No more debug registers! */ | |
355 | if (i >= DR_NADDR) | |
356 | return -1; | |
357 | ||
358 | /* Now set up the register I to watch our region. */ | |
359 | ||
360 | /* Record the info in our local mirrored array. */ | |
361 | dr_mirror[i] = addr; | |
362 | dr_ref_count[i] = 1; | |
363 | I386_DR_SET_RW_LEN (i, len_rw_bits); | |
364 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
7fa2737c | 365 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
366 | watchpoints; however, if any target would want that in the |
367 | future, GDB should probably provide a command to control whether | |
368 | to enable watchpoints globally or locally, and the code below | |
369 | should use global or local enable and slow-down flags as | |
370 | appropriate. */ | |
371 | I386_DR_LOCAL_ENABLE (i); | |
372 | dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
373 | dr_control_mirror &= I386_DR_CONTROL_MASK; | |
374 | ||
375 | /* Finally, actually pass the info to the inferior. */ | |
52b98211 | 376 | I386_DR_LOW_SET_ADDR (i, addr); |
4bcc3944 | 377 | I386_DR_LOW_SET_CONTROL (dr_control_mirror); |
52b98211 EZ |
378 | |
379 | return 0; | |
380 | } | |
381 | ||
382 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
383 | according to the length of the region to watch. LEN_RW_BITS is the | |
384 | value of the bits from DR7 which describes the length and access | |
385 | type of the region watched by this watchpoint. Return 0 on | |
386 | success, -1 on failure. */ | |
7fa2737c | 387 | |
52b98211 EZ |
388 | static int |
389 | i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) | |
390 | { | |
391 | int i, retval = -1; | |
392 | ||
393 | ALL_DEBUG_REGISTERS(i) | |
394 | { | |
395 | if (!I386_DR_VACANT (i) | |
396 | && dr_mirror[i] == addr | |
397 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) | |
398 | { | |
399 | if (--dr_ref_count[i] == 0) /* no longer in use? */ | |
400 | { | |
401 | /* Reset our mirror. */ | |
402 | dr_mirror[i] = 0; | |
403 | I386_DR_DISABLE (i); | |
404 | /* Reset it in the inferior. */ | |
52b98211 | 405 | I386_DR_LOW_SET_CONTROL (dr_control_mirror); |
4bcc3944 | 406 | I386_DR_LOW_RESET_ADDR (i); |
52b98211 EZ |
407 | } |
408 | retval = 0; | |
409 | } | |
410 | } | |
411 | ||
412 | return retval; | |
413 | } | |
414 | ||
415 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
416 | number of debug registers required to watch a region at address | |
417 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
418 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
419 | about the number of registers, or -1 on failure. If WHAT is not a |
420 | valid value, bombs through internal_error. */ | |
421 | ||
52b98211 EZ |
422 | static int |
423 | i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, | |
424 | enum target_hw_bp_type type) | |
425 | { | |
7fa2737c | 426 | int retval = 0, status = 0; |
e906b9a3 | 427 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 428 | |
e906b9a3 | 429 | static int size_try_array[8][8] = |
52b98211 | 430 | { |
7fa2737c MK |
431 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
432 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
433 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
434 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
435 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
436 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
437 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
438 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
439 | }; |
440 | ||
441 | while (len > 0) | |
442 | { | |
7fa2737c | 443 | int align = addr % max_wp_len; |
f2e7c15d | 444 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 445 | can watch. */ |
7fa2737c MK |
446 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
447 | int size = size_try_array[try][align]; | |
448 | ||
52b98211 | 449 | if (what == WP_COUNT) |
7fa2737c MK |
450 | { |
451 | /* size_try_array[] is defined such that each iteration | |
452 | through the loop is guaranteed to produce an address and a | |
453 | size that can be watched with a single debug register. | |
454 | Thus, for counting the registers required to watch a | |
455 | region, we simply need to increment the count on each | |
456 | iteration. */ | |
457 | retval++; | |
458 | } | |
52b98211 EZ |
459 | else |
460 | { | |
461 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
462 | ||
463 | if (what == WP_INSERT) | |
464 | status = i386_insert_aligned_watchpoint (addr, len_rw); | |
465 | else if (what == WP_REMOVE) | |
466 | status = i386_remove_aligned_watchpoint (addr, len_rw); | |
467 | else | |
e2e0b3e5 AC |
468 | internal_error (__FILE__, __LINE__, _("\ |
469 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 EZ |
470 | (int)what); |
471 | /* We keep the loop going even after a failure, because some | |
472 | of the other aligned watchpoints might still succeed | |
473 | (e.g. if they watch addresses that are already watched, | |
474 | in which case we just increment the reference counts of | |
475 | occupied debug registers). If we break out of the loop | |
476 | too early, we could cause those addresses watched by | |
477 | other watchpoints to be disabled when breakpoint.c reacts | |
478 | to our failure to insert this watchpoint and tries to | |
479 | remove it. */ | |
480 | if (status) | |
7fa2737c | 481 | retval = status; |
52b98211 | 482 | } |
7fa2737c | 483 | |
52b98211 EZ |
484 | addr += size; |
485 | len -= size; | |
486 | } | |
7fa2737c MK |
487 | |
488 | return retval; | |
52b98211 EZ |
489 | } |
490 | ||
491 | /* Insert a watchpoint to watch a memory region which starts at | |
492 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
493 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 494 | |
52b98211 EZ |
495 | int |
496 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type) | |
497 | { | |
498 | int retval; | |
499 | ||
e906b9a3 JS |
500 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
501 | || addr % len != 0) | |
52b98211 EZ |
502 | retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type); |
503 | else | |
504 | { | |
505 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
506 | ||
507 | retval = i386_insert_aligned_watchpoint (addr, len_rw); | |
508 | } | |
509 | ||
510 | if (maint_show_dr) | |
511 | i386_show_dr ("insert_watchpoint", addr, len, type); | |
512 | ||
513 | return retval; | |
514 | } | |
515 | ||
516 | /* Remove a watchpoint that watched the memory region which starts at | |
517 | address ADDR, whose length is LEN bytes, and for accesses of the | |
518 | type TYPE. Return 0 on success, -1 on failure. */ | |
519 | int | |
520 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type) | |
521 | { | |
522 | int retval; | |
523 | ||
e906b9a3 JS |
524 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
525 | || addr % len != 0) | |
52b98211 EZ |
526 | retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type); |
527 | else | |
528 | { | |
529 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
530 | ||
531 | retval = i386_remove_aligned_watchpoint (addr, len_rw); | |
532 | } | |
533 | ||
534 | if (maint_show_dr) | |
535 | i386_show_dr ("remove_watchpoint", addr, len, type); | |
536 | ||
537 | return retval; | |
538 | } | |
539 | ||
540 | /* Return non-zero if we can watch a memory region that starts at | |
541 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 542 | |
52b98211 EZ |
543 | int |
544 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) | |
545 | { | |
7fa2737c MK |
546 | int nregs; |
547 | ||
52b98211 EZ |
548 | /* Compute how many aligned watchpoints we would need to cover this |
549 | region. */ | |
7fa2737c | 550 | nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write); |
52b98211 EZ |
551 | return nregs <= DR_NADDR ? 1 : 0; |
552 | } | |
553 | ||
4aa7a7f5 JJ |
554 | /* If the inferior has some watchpoint that triggered, set the |
555 | address associated with that watchpoint and return non-zero. | |
556 | Otherwise, return zero. */ | |
7fa2737c | 557 | |
4aa7a7f5 | 558 | int |
c03374d5 | 559 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 560 | { |
7fa2737c | 561 | CORE_ADDR addr = 0; |
52b98211 | 562 | int i; |
4aa7a7f5 | 563 | int rc = 0; |
52b98211 EZ |
564 | |
565 | dr_status_mirror = I386_DR_LOW_GET_STATUS (); | |
566 | ||
567 | ALL_DEBUG_REGISTERS(i) | |
568 | { | |
569 | if (I386_DR_WATCH_HIT (i) | |
570 | /* This second condition makes sure DRi is set up for a data | |
571 | watchpoint, not a hardware breakpoint. The reason is | |
572 | that GDB doesn't call the target_stopped_data_address | |
573 | method except for data watchpoints. In other words, I'm | |
f2e7c15d | 574 | being paranoiac. */ |
52b98211 EZ |
575 | && I386_DR_GET_RW_LEN (i) != 0) |
576 | { | |
7fa2737c | 577 | addr = dr_mirror[i]; |
4aa7a7f5 | 578 | rc = 1; |
52b98211 | 579 | if (maint_show_dr) |
7fa2737c | 580 | i386_show_dr ("watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
581 | } |
582 | } | |
7fa2737c | 583 | if (maint_show_dr && addr == 0) |
52b98211 EZ |
584 | i386_show_dr ("stopped_data_addr", 0, 0, hw_write); |
585 | ||
4aa7a7f5 JJ |
586 | if (rc) |
587 | *addr_p = addr; | |
588 | return rc; | |
589 | } | |
590 | ||
591 | int | |
592 | i386_stopped_by_watchpoint (void) | |
593 | { | |
594 | CORE_ADDR addr = 0; | |
c03374d5 | 595 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
596 | } |
597 | ||
598 | /* Return non-zero if the inferior has some break/watchpoint that | |
599 | triggered. */ | |
7fa2737c | 600 | |
52b98211 EZ |
601 | int |
602 | i386_stopped_by_hwbp (void) | |
603 | { | |
604 | int i; | |
605 | ||
606 | dr_status_mirror = I386_DR_LOW_GET_STATUS (); | |
607 | if (maint_show_dr) | |
608 | i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute); | |
609 | ||
610 | ALL_DEBUG_REGISTERS(i) | |
611 | { | |
612 | if (I386_DR_WATCH_HIT (i)) | |
613 | return 1; | |
614 | } | |
615 | ||
616 | return 0; | |
617 | } | |
618 | ||
8181d85f DJ |
619 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
620 | Return 0 on success, EBUSY on failure. */ | |
52b98211 | 621 | int |
8181d85f | 622 | i386_insert_hw_breakpoint (struct bp_target_info *bp_tgt) |
52b98211 EZ |
623 | { |
624 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 625 | CORE_ADDR addr = bp_tgt->placed_address; |
52b98211 EZ |
626 | int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0; |
627 | ||
628 | if (maint_show_dr) | |
629 | i386_show_dr ("insert_hwbp", addr, 1, hw_execute); | |
630 | ||
631 | return retval; | |
632 | } | |
633 | ||
8181d85f DJ |
634 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
635 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 636 | |
52b98211 | 637 | int |
8181d85f | 638 | i386_remove_hw_breakpoint (struct bp_target_info *bp_tgt) |
52b98211 EZ |
639 | { |
640 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 641 | CORE_ADDR addr = bp_tgt->placed_address; |
52b98211 EZ |
642 | int retval = i386_remove_aligned_watchpoint (addr, len_rw); |
643 | ||
644 | if (maint_show_dr) | |
645 | i386_show_dr ("remove_hwbp", addr, 1, hw_execute); | |
646 | ||
647 | return retval; | |
648 | } | |
649 | ||
c03374d5 DJ |
650 | /* Returns the number of hardware watchpoints of type TYPE that we can |
651 | set. Value is positive if we can set CNT watchpoints, zero if | |
652 | setting watchpoints of type TYPE is not supported, and negative if | |
653 | CNT is more than the maximum number of watchpoints of type TYPE | |
654 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
655 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
656 | CNT is the number of such watchpoints used so far (including this | |
657 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
658 | currently enabled. | |
659 | ||
660 | We always return 1 here because we don't have enough information | |
661 | about possible overlap of addresses that they want to watch. As an | |
662 | extreme example, consider the case where all the watchpoints watch | |
663 | the same address and the same region length: then we can handle a | |
664 | virtually unlimited number of watchpoints, due to debug register | |
665 | sharing implemented via reference counts in i386-nat.c. */ | |
666 | ||
667 | static int | |
668 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
669 | { | |
670 | return 1; | |
671 | } | |
672 | ||
673 | void | |
674 | i386_use_watchpoints (struct target_ops *t) | |
675 | { | |
676 | /* After a watchpoint trap, the PC points to the instruction after the | |
677 | one that caused the trap. Therefore we don't need to step over it. | |
678 | But we do need to reset the status register to avoid another trap. */ | |
679 | t->to_have_continuable_watchpoint = 1; | |
680 | ||
681 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
682 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
683 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
684 | t->to_stopped_data_address = i386_stopped_data_address; | |
685 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
686 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
687 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
688 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
689 | } | |
690 | ||
52b98211 | 691 | #endif /* I386_USE_GENERIC_WATCHPOINTS */ |
52b98211 | 692 | \f |
7fa2737c MK |
693 | |
694 | /* Provide a prototype to silence -Wmissing-prototypes. */ | |
695 | void _initialize_i386_nat (void); | |
696 | ||
52b98211 EZ |
697 | void |
698 | _initialize_i386_nat (void) | |
699 | { | |
700 | #ifdef I386_USE_GENERIC_WATCHPOINTS | |
701 | /* A maintenance command to enable printing the internal DRi mirror | |
702 | variables. */ | |
cbe54154 PA |
703 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
704 | &maint_show_dr, _("\ | |
705 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
706 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
52b98211 EZ |
707 | Use \"on\" to enable, \"off\" to disable.\n\ |
708 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
709 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
b66df561 | 710 | triggers a breakpoint or watchpoint."), |
cbe54154 PA |
711 | NULL, |
712 | NULL, | |
713 | &maintenance_set_cmdlist, | |
714 | &maintenance_show_cmdlist); | |
52b98211 EZ |
715 | #endif |
716 | } |