Commit | Line | Data |
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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
0b302171 JB |
3 | Copyright (C) 2001, 2004-2005, 2007-2012 Free Software Foundation, |
4 | Inc. | |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 | 20 | |
9bb9e8ad | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "defs.h" |
23 | #include "breakpoint.h" | |
24 | #include "command.h" | |
25 | #include "gdbcmd.h" | |
c03374d5 | 26 | #include "target.h" |
9bb9e8ad | 27 | #include "gdb_assert.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
9bb9e8ad PM |
40 | struct i386_dr_low_type i386_dr_low; |
41 | ||
52b98211 | 42 | |
e906b9a3 | 43 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 44 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 45 | |
52b98211 EZ |
46 | /* DR7 Debug Control register fields. */ |
47 | ||
48 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
49 | #define DR_CONTROL_SHIFT 16 | |
50 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
51 | #define DR_CONTROL_SIZE 4 | |
52 | ||
53 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
54 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
55 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
56 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
57 | |
58 | /* This is here for completeness. No platform supports this | |
7fa2737c | 59 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
60 | CR4 register needs to be set to support this. */ |
61 | #ifndef DR_RW_IORW | |
7fa2737c | 62 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
63 | #endif |
64 | ||
65 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
66 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
67 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
68 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
69 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
70 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
71 | |
72 | /* Local and Global Enable flags in DR7. | |
73 | ||
74 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
75 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
76 | clears this flag on every task switch. When the Global Enable flag |
77 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
78 | processor never clears this flag. | |
52b98211 EZ |
79 | |
80 | Currently, all watchpoint are locally enabled. If you need to | |
81 | enable them globally, read the comment which pertains to this in | |
82 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
83 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
84 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
85 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
86 | |
87 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
88 | flags). These are only required on i386, to allow detection of the | |
89 | exact instruction which caused a watchpoint to break; i486 and | |
90 | later processors do that automatically. We set these flags for | |
7fa2737c | 91 | backwards compatibility. */ |
52b98211 | 92 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 93 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
94 | |
95 | /* Fields reserved by Intel. This includes the GD (General Detect | |
96 | Enable) flag, which causes a debug exception to be generated when a | |
97 | MOV instruction accesses one of the debug registers. | |
98 | ||
99 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
100 | #define DR_CONTROL_RESERVED (0xFC00) | |
101 | ||
102 | /* Auxiliary helper macros. */ | |
103 | ||
104 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 105 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
106 | |
107 | /* The I'th debug register is vacant if its Local and Global Enable | |
108 | bits are reset in the Debug Control register. */ | |
1ced966e PA |
109 | #define I386_DR_VACANT(state, i) \ |
110 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
52b98211 EZ |
111 | |
112 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
113 | #define I386_DR_LOCAL_ENABLE(state, i) \ |
114 | do { \ | |
115 | (state)->dr_control_mirror |= \ | |
116 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
117 | } while (0) | |
52b98211 EZ |
118 | |
119 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
120 | #define I386_DR_GLOBAL_ENABLE(state, i) \ |
121 | do { \ | |
122 | (state)->dr_control_mirror |= \ | |
123 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
124 | } while (0) | |
52b98211 EZ |
125 | |
126 | /* Disable the break/watchpoint in the I'th debug register. */ | |
1ced966e PA |
127 | #define I386_DR_DISABLE(state, i) \ |
128 | do { \ | |
129 | (state)->dr_control_mirror &= \ | |
130 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
131 | } while (0) | |
52b98211 EZ |
132 | |
133 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e | 134 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ |
52b98211 | 135 | do { \ |
1ced966e PA |
136 | (state)->dr_control_mirror &= \ |
137 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
138 | (state)->dr_control_mirror |= \ | |
139 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
52b98211 EZ |
140 | } while (0) |
141 | ||
142 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
1ced966e PA |
143 | #define I386_DR_GET_RW_LEN(dr7, i) \ |
144 | (((dr7) \ | |
145 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
52b98211 | 146 | |
a79d3c27 JK |
147 | /* Mask that this I'th watchpoint has triggered. */ |
148 | #define I386_DR_WATCH_MASK(i) (1 << (i)) | |
149 | ||
52b98211 | 150 | /* Did the watchpoint whose address is in the I'th register break? */ |
1ced966e | 151 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) |
52b98211 EZ |
152 | |
153 | /* A macro to loop over all debug registers. */ | |
154 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
155 | ||
1ced966e PA |
156 | /* Clear the reference counts and forget everything we knew about the |
157 | debug registers. */ | |
158 | ||
159 | static void | |
160 | i386_init_dregs (struct i386_debug_reg_state *state) | |
161 | { | |
162 | int i; | |
163 | ||
164 | ALL_DEBUG_REGISTERS (i) | |
165 | { | |
166 | state->dr_mirror[i] = 0; | |
167 | state->dr_ref_count[i] = 0; | |
168 | } | |
169 | state->dr_control_mirror = 0; | |
170 | state->dr_status_mirror = 0; | |
171 | } | |
172 | ||
7b50312a PA |
173 | /* The local mirror of the inferior's debug registers. Currently this |
174 | is a global, but it should really be per-inferior. */ | |
1ced966e | 175 | static struct i386_debug_reg_state dr_mirror; |
52b98211 | 176 | |
7b50312a PA |
177 | struct i386_debug_reg_state * |
178 | i386_debug_reg_state (void) | |
179 | { | |
180 | return &dr_mirror; | |
181 | } | |
182 | ||
52b98211 | 183 | /* Whether or not to print the mirrored debug registers. */ |
7fa2737c | 184 | static int maint_show_dr; |
52b98211 EZ |
185 | |
186 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
187 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
188 | ||
189 | /* Internal functions. */ | |
190 | ||
191 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
192 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
193 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
194 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
195 | ||
196 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
197 | according to the length of the region to watch. LEN_RW_BITS is the | |
198 | value of the bit-field from DR7 which describes the length and | |
199 | access type of the region to be watched by this watchpoint. Return | |
200 | 0 on success, -1 on failure. */ | |
1ced966e PA |
201 | static int i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
202 | CORE_ADDR addr, | |
52b98211 EZ |
203 | unsigned len_rw_bits); |
204 | ||
205 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
206 | according to the length of the region to watch. LEN_RW_BITS is the | |
207 | value of the bits from DR7 which describes the length and access | |
208 | type of the region watched by this watchpoint. Return 0 on | |
209 | success, -1 on failure. */ | |
1ced966e PA |
210 | static int i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
211 | CORE_ADDR addr, | |
52b98211 EZ |
212 | unsigned len_rw_bits); |
213 | ||
214 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
215 | number of debug registers required to watch a region at address | |
216 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
217 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
218 | about the number of registers, or -1 on failure. If WHAT is not a |
219 | valid value, bombs through internal_error. */ | |
1ced966e PA |
220 | static int i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
221 | i386_wp_op_t what, | |
52b98211 EZ |
222 | CORE_ADDR addr, int len, |
223 | enum target_hw_bp_type type); | |
224 | ||
225 | /* Implementation. */ | |
226 | ||
7fa2737c MK |
227 | /* Clear the reference counts and forget everything we knew about the |
228 | debug registers. */ | |
229 | ||
52b98211 EZ |
230 | void |
231 | i386_cleanup_dregs (void) | |
232 | { | |
1ced966e | 233 | i386_init_dregs (&dr_mirror); |
52b98211 EZ |
234 | } |
235 | ||
7fa2737c MK |
236 | /* Print the values of the mirrored debug registers. This is called |
237 | when maint_show_dr is non-zero. To set that up, type "maint | |
238 | show-debug-regs" at GDB's prompt. */ | |
239 | ||
52b98211 | 240 | static void |
1ced966e PA |
241 | i386_show_dr (struct i386_debug_reg_state *state, |
242 | const char *func, CORE_ADDR addr, | |
52b98211 EZ |
243 | int len, enum target_hw_bp_type type) |
244 | { | |
5af949e3 | 245 | int addr_size = gdbarch_addr_bit (target_gdbarch) / 8; |
52b98211 EZ |
246 | int i; |
247 | ||
248 | puts_unfiltered (func); | |
249 | if (addr || len) | |
250 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
251 | /* This code is for ia32, so casting CORE_ADDR | |
252 | to unsigned long should be okay. */ | |
253 | (unsigned long)addr, len, | |
254 | type == hw_write ? "data-write" | |
255 | : (type == hw_read ? "data-read" | |
256 | : (type == hw_access ? "data-read/write" | |
257 | : (type == hw_execute ? "instruction-execute" | |
258 | /* FIXME: if/when I/O read/write | |
259 | watchpoints are supported, add them | |
260 | here. */ | |
261 | : "??unknown??")))); | |
262 | puts_unfiltered (":\n"); | |
9bb9e8ad | 263 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
1ced966e PA |
264 | phex (state->dr_control_mirror, 8), |
265 | phex (state->dr_status_mirror, 8)); | |
52b98211 EZ |
266 | ALL_DEBUG_REGISTERS(i) |
267 | { | |
7fa2737c MK |
268 | printf_unfiltered ("\ |
269 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
1ced966e PA |
270 | i, phex (state->dr_mirror[i], addr_size), |
271 | state->dr_ref_count[i], | |
272 | i + 1, phex (state->dr_mirror[i + 1], addr_size), | |
273 | state->dr_ref_count[i+1]); | |
52b98211 EZ |
274 | i++; |
275 | } | |
276 | } | |
277 | ||
278 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
279 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
280 | have the value of 1, 2, or 4. */ | |
281 | ||
52b98211 EZ |
282 | static unsigned |
283 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
284 | { | |
285 | unsigned rw; | |
286 | ||
287 | switch (type) | |
288 | { | |
289 | case hw_execute: | |
290 | rw = DR_RW_EXECUTE; | |
291 | break; | |
292 | case hw_write: | |
293 | rw = DR_RW_WRITE; | |
294 | break; | |
7fa2737c | 295 | case hw_read: |
85d721b8 | 296 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
297 | _("The i386 doesn't support " |
298 | "data-read watchpoints.\n")); | |
52b98211 EZ |
299 | case hw_access: |
300 | rw = DR_RW_READ; | |
301 | break; | |
302 | #if 0 | |
7fa2737c MK |
303 | /* Not yet supported. */ |
304 | case hw_io_access: | |
52b98211 EZ |
305 | rw = DR_RW_IORW; |
306 | break; | |
307 | #endif | |
308 | default: | |
e2e0b3e5 AC |
309 | internal_error (__FILE__, __LINE__, _("\ |
310 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 311 | (int) type); |
52b98211 EZ |
312 | } |
313 | ||
314 | switch (len) | |
315 | { | |
52b98211 EZ |
316 | case 1: |
317 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
318 | case 2: |
319 | return (DR_LEN_2 | rw); | |
320 | case 4: | |
321 | return (DR_LEN_4 | rw); | |
322 | case 8: | |
323 | if (TARGET_HAS_DR_LEN_8) | |
324 | return (DR_LEN_8 | rw); | |
8fbf6b93 | 325 | /* ELSE FALL THROUGH */ |
52b98211 | 326 | default: |
e2e0b3e5 AC |
327 | internal_error (__FILE__, __LINE__, _("\ |
328 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
329 | } |
330 | } | |
331 | ||
332 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
333 | according to the length of the region to watch. LEN_RW_BITS is the | |
334 | value of the bits from DR7 which describes the length and access | |
335 | type of the region to be watched by this watchpoint. Return 0 on | |
336 | success, -1 on failure. */ | |
7fa2737c | 337 | |
52b98211 | 338 | static int |
1ced966e PA |
339 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, |
340 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
341 | { |
342 | int i; | |
343 | ||
9bb9e8ad PM |
344 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
345 | return -1; | |
346 | ||
52b98211 EZ |
347 | /* First, look for an occupied debug register with the same address |
348 | and the same RW and LEN definitions. If we find one, we can | |
349 | reuse it for this watchpoint as well (and save a register). */ | |
350 | ALL_DEBUG_REGISTERS(i) | |
351 | { | |
1ced966e PA |
352 | if (!I386_DR_VACANT (state, i) |
353 | && state->dr_mirror[i] == addr | |
354 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 355 | { |
1ced966e | 356 | state->dr_ref_count[i]++; |
52b98211 EZ |
357 | return 0; |
358 | } | |
359 | } | |
360 | ||
361 | /* Next, look for a vacant debug register. */ | |
362 | ALL_DEBUG_REGISTERS(i) | |
363 | { | |
1ced966e | 364 | if (I386_DR_VACANT (state, i)) |
52b98211 EZ |
365 | break; |
366 | } | |
367 | ||
368 | /* No more debug registers! */ | |
369 | if (i >= DR_NADDR) | |
370 | return -1; | |
371 | ||
372 | /* Now set up the register I to watch our region. */ | |
373 | ||
374 | /* Record the info in our local mirrored array. */ | |
1ced966e PA |
375 | state->dr_mirror[i] = addr; |
376 | state->dr_ref_count[i] = 1; | |
377 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
52b98211 | 378 | /* Note: we only enable the watchpoint locally, i.e. in the current |
7fa2737c | 379 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
380 | watchpoints; however, if any target would want that in the |
381 | future, GDB should probably provide a command to control whether | |
382 | to enable watchpoints globally or locally, and the code below | |
383 | should use global or local enable and slow-down flags as | |
384 | appropriate. */ | |
1ced966e PA |
385 | I386_DR_LOCAL_ENABLE (state, i); |
386 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
387 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
a79d3c27 | 388 | |
52b98211 EZ |
389 | return 0; |
390 | } | |
391 | ||
392 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
393 | according to the length of the region to watch. LEN_RW_BITS is the | |
394 | value of the bits from DR7 which describes the length and access | |
395 | type of the region watched by this watchpoint. Return 0 on | |
396 | success, -1 on failure. */ | |
7fa2737c | 397 | |
52b98211 | 398 | static int |
1ced966e PA |
399 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, |
400 | CORE_ADDR addr, unsigned len_rw_bits) | |
52b98211 EZ |
401 | { |
402 | int i, retval = -1; | |
403 | ||
404 | ALL_DEBUG_REGISTERS(i) | |
405 | { | |
1ced966e PA |
406 | if (!I386_DR_VACANT (state, i) |
407 | && state->dr_mirror[i] == addr | |
408 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
52b98211 | 409 | { |
1ced966e | 410 | if (--state->dr_ref_count[i] == 0) /* no longer in use? */ |
52b98211 EZ |
411 | { |
412 | /* Reset our mirror. */ | |
1ced966e PA |
413 | state->dr_mirror[i] = 0; |
414 | I386_DR_DISABLE (state, i); | |
52b98211 EZ |
415 | } |
416 | retval = 0; | |
417 | } | |
418 | } | |
419 | ||
420 | return retval; | |
421 | } | |
422 | ||
423 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
424 | number of debug registers required to watch a region at address | |
425 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
426 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
427 | about the number of registers, or -1 on failure. If WHAT is not a |
428 | valid value, bombs through internal_error. */ | |
429 | ||
52b98211 | 430 | static int |
1ced966e PA |
431 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, |
432 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
52b98211 EZ |
433 | enum target_hw_bp_type type) |
434 | { | |
1ced966e | 435 | int retval = 0; |
e906b9a3 | 436 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 437 | |
e906b9a3 | 438 | static int size_try_array[8][8] = |
52b98211 | 439 | { |
7fa2737c MK |
440 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
441 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
442 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
443 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
444 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
445 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
446 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
447 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
448 | }; |
449 | ||
450 | while (len > 0) | |
451 | { | |
7fa2737c | 452 | int align = addr % max_wp_len; |
f2e7c15d | 453 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 454 | can watch. */ |
7fa2737c MK |
455 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
456 | int size = size_try_array[try][align]; | |
457 | ||
52b98211 | 458 | if (what == WP_COUNT) |
7fa2737c MK |
459 | { |
460 | /* size_try_array[] is defined such that each iteration | |
461 | through the loop is guaranteed to produce an address and a | |
462 | size that can be watched with a single debug register. | |
463 | Thus, for counting the registers required to watch a | |
464 | region, we simply need to increment the count on each | |
465 | iteration. */ | |
466 | retval++; | |
467 | } | |
52b98211 EZ |
468 | else |
469 | { | |
470 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
471 | ||
472 | if (what == WP_INSERT) | |
1ced966e | 473 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 474 | else if (what == WP_REMOVE) |
1ced966e | 475 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); |
52b98211 | 476 | else |
e2e0b3e5 AC |
477 | internal_error (__FILE__, __LINE__, _("\ |
478 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 | 479 | (int)what); |
1ced966e PA |
480 | if (retval) |
481 | break; | |
52b98211 | 482 | } |
7fa2737c | 483 | |
52b98211 EZ |
484 | addr += size; |
485 | len -= size; | |
486 | } | |
7fa2737c MK |
487 | |
488 | return retval; | |
52b98211 EZ |
489 | } |
490 | ||
1ced966e PA |
491 | /* Update the inferior's debug registers with the new debug registers |
492 | state, in NEW_STATE, and then update our local mirror to match. */ | |
493 | ||
494 | static void | |
495 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *new_state) | |
496 | { | |
497 | int i; | |
498 | ||
499 | ALL_DEBUG_REGISTERS (i) | |
500 | { | |
501 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (&dr_mirror, i)) | |
7b50312a | 502 | i386_dr_low.set_addr (i, new_state->dr_mirror[i]); |
1ced966e PA |
503 | else |
504 | gdb_assert (new_state->dr_mirror[i] == dr_mirror.dr_mirror[i]); | |
505 | } | |
506 | ||
507 | if (new_state->dr_control_mirror != dr_mirror.dr_control_mirror) | |
508 | i386_dr_low.set_control (new_state->dr_control_mirror); | |
509 | ||
510 | dr_mirror = *new_state; | |
511 | } | |
512 | ||
52b98211 EZ |
513 | /* Insert a watchpoint to watch a memory region which starts at |
514 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
515 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 516 | |
9bb9e8ad | 517 | static int |
0cf6dd15 TJB |
518 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type, |
519 | struct expression *cond) | |
52b98211 EZ |
520 | { |
521 | int retval; | |
1ced966e PA |
522 | /* Work on a local copy of the debug registers, and on success, |
523 | commit the change back to the inferior. */ | |
524 | struct i386_debug_reg_state local_state = dr_mirror; | |
52b98211 | 525 | |
85d721b8 PA |
526 | if (type == hw_read) |
527 | return 1; /* unsupported */ | |
528 | ||
e906b9a3 JS |
529 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
530 | || addr % len != 0) | |
1ced966e PA |
531 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
532 | WP_INSERT, addr, len, type); | |
52b98211 EZ |
533 | else |
534 | { | |
535 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
536 | ||
1ced966e PA |
537 | retval = i386_insert_aligned_watchpoint (&local_state, |
538 | addr, len_rw); | |
52b98211 EZ |
539 | } |
540 | ||
1ced966e PA |
541 | if (retval == 0) |
542 | i386_update_inferior_debug_regs (&local_state); | |
543 | ||
52b98211 | 544 | if (maint_show_dr) |
1ced966e | 545 | i386_show_dr (&dr_mirror, "insert_watchpoint", addr, len, type); |
52b98211 EZ |
546 | |
547 | return retval; | |
548 | } | |
549 | ||
550 | /* Remove a watchpoint that watched the memory region which starts at | |
551 | address ADDR, whose length is LEN bytes, and for accesses of the | |
552 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 553 | static int |
0cf6dd15 TJB |
554 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type, |
555 | struct expression *cond) | |
52b98211 EZ |
556 | { |
557 | int retval; | |
1ced966e PA |
558 | /* Work on a local copy of the debug registers, and on success, |
559 | commit the change back to the inferior. */ | |
560 | struct i386_debug_reg_state local_state = dr_mirror; | |
52b98211 | 561 | |
e906b9a3 JS |
562 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
563 | || addr % len != 0) | |
1ced966e PA |
564 | retval = i386_handle_nonaligned_watchpoint (&local_state, |
565 | WP_REMOVE, addr, len, type); | |
52b98211 EZ |
566 | else |
567 | { | |
568 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
569 | ||
1ced966e PA |
570 | retval = i386_remove_aligned_watchpoint (&local_state, |
571 | addr, len_rw); | |
52b98211 EZ |
572 | } |
573 | ||
1ced966e PA |
574 | if (retval == 0) |
575 | i386_update_inferior_debug_regs (&local_state); | |
576 | ||
52b98211 | 577 | if (maint_show_dr) |
1ced966e | 578 | i386_show_dr (&dr_mirror, "remove_watchpoint", addr, len, type); |
52b98211 EZ |
579 | |
580 | return retval; | |
581 | } | |
582 | ||
583 | /* Return non-zero if we can watch a memory region that starts at | |
584 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 585 | |
9bb9e8ad | 586 | static int |
52b98211 EZ |
587 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
588 | { | |
7fa2737c MK |
589 | int nregs; |
590 | ||
52b98211 EZ |
591 | /* Compute how many aligned watchpoints we would need to cover this |
592 | region. */ | |
1ced966e PA |
593 | nregs = i386_handle_nonaligned_watchpoint (&dr_mirror, |
594 | WP_COUNT, addr, len, hw_write); | |
52b98211 EZ |
595 | return nregs <= DR_NADDR ? 1 : 0; |
596 | } | |
597 | ||
4aa7a7f5 | 598 | /* If the inferior has some watchpoint that triggered, set the |
1777feb0 | 599 | address associated with that watchpoint and return non-zero. |
4aa7a7f5 | 600 | Otherwise, return zero. */ |
7fa2737c | 601 | |
9bb9e8ad | 602 | static int |
c03374d5 | 603 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 604 | { |
7fa2737c | 605 | CORE_ADDR addr = 0; |
52b98211 | 606 | int i; |
4aa7a7f5 | 607 | int rc = 0; |
7b50312a PA |
608 | /* The current thread's DR_STATUS. We always need to read this to |
609 | check whether some watchpoint caused the trap. */ | |
1ced966e | 610 | unsigned status; |
7b50312a PA |
611 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a |
612 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
613 | unnecessary extra syscall when no watchpoint triggered. */ | |
614 | int control_p = 0; | |
615 | unsigned control = 0; | |
616 | ||
617 | /* In non-stop/async, threads can be running while we change the | |
618 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
619 | let threads resume. Now, say you delete the watchpoint, or | |
620 | add/remove watchpoints such that dr_mirror changes while threads | |
621 | are running. On targets that support non-stop, | |
622 | inserting/deleting watchpoints updates the global dr_mirror only. | |
623 | It does not update the real thread's debug registers; that's only | |
624 | done prior to resume. Instead, if threads are running when the | |
625 | mirror changes, a temporary and transparent stop on all threads | |
626 | is forced so they can get their copy of the debug registers | |
627 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
628 | having been updated with the new dr_mirror contents, and we | |
629 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
630 | dr_mirror below, we'd mistake the real trapped address (from the | |
631 | last time we had updated debug registers in the thread) with | |
632 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
633 | always represents intention, what we _want_ threads to have in | |
634 | debug registers. To get at the address and cause of the trap, we | |
635 | need to read the state the thread still has in its debug | |
636 | registers. | |
637 | ||
638 | In sum, always get the current debug register values the current | |
639 | thread has, instead of trusting the global mirror. If the thread | |
640 | was running when we last changed watchpoints, the mirror no | |
641 | longer represents what was set in this thread's debug | |
642 | registers. */ | |
643 | status = i386_dr_low.get_status (); | |
52b98211 EZ |
644 | |
645 | ALL_DEBUG_REGISTERS(i) | |
646 | { | |
7b50312a PA |
647 | if (!I386_DR_WATCH_HIT (status, i)) |
648 | continue; | |
649 | ||
650 | if (!control_p) | |
651 | { | |
652 | control = i386_dr_low.get_control (); | |
653 | control_p = 1; | |
654 | } | |
655 | ||
656 | /* This second condition makes sure DRi is set up for a data | |
657 | watchpoint, not a hardware breakpoint. The reason is that | |
658 | GDB doesn't call the target_stopped_data_address method | |
659 | except for data watchpoints. In other words, I'm being | |
660 | paranoiac. */ | |
661 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
52b98211 | 662 | { |
7b50312a | 663 | addr = i386_dr_low.get_addr (i); |
4aa7a7f5 | 664 | rc = 1; |
52b98211 | 665 | if (maint_show_dr) |
1ced966e | 666 | i386_show_dr (&dr_mirror, "watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
667 | } |
668 | } | |
7fa2737c | 669 | if (maint_show_dr && addr == 0) |
1ced966e | 670 | i386_show_dr (&dr_mirror, "stopped_data_addr", 0, 0, hw_write); |
52b98211 | 671 | |
4aa7a7f5 JJ |
672 | if (rc) |
673 | *addr_p = addr; | |
674 | return rc; | |
675 | } | |
676 | ||
9bb9e8ad | 677 | static int |
4aa7a7f5 JJ |
678 | i386_stopped_by_watchpoint (void) |
679 | { | |
680 | CORE_ADDR addr = 0; | |
c03374d5 | 681 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
682 | } |
683 | ||
8181d85f DJ |
684 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
685 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 686 | static int |
a6d9a66e UW |
687 | i386_insert_hw_breakpoint (struct gdbarch *gdbarch, |
688 | struct bp_target_info *bp_tgt) | |
52b98211 EZ |
689 | { |
690 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 691 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
692 | /* Work on a local copy of the debug registers, and on success, |
693 | commit the change back to the inferior. */ | |
694 | struct i386_debug_reg_state local_state = dr_mirror; | |
695 | int retval = i386_insert_aligned_watchpoint (&local_state, | |
1ced966e | 696 | addr, len_rw) ? EBUSY : 0; |
52b98211 | 697 | |
edcc485a MR |
698 | if (retval == 0) |
699 | i386_update_inferior_debug_regs (&local_state); | |
700 | ||
52b98211 | 701 | if (maint_show_dr) |
1ced966e | 702 | i386_show_dr (&dr_mirror, "insert_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
703 | |
704 | return retval; | |
705 | } | |
706 | ||
8181d85f DJ |
707 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
708 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 709 | |
9bb9e8ad | 710 | static int |
a6d9a66e UW |
711 | i386_remove_hw_breakpoint (struct gdbarch *gdbarch, |
712 | struct bp_target_info *bp_tgt) | |
52b98211 EZ |
713 | { |
714 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 715 | CORE_ADDR addr = bp_tgt->placed_address; |
edcc485a MR |
716 | /* Work on a local copy of the debug registers, and on success, |
717 | commit the change back to the inferior. */ | |
718 | struct i386_debug_reg_state local_state = dr_mirror; | |
719 | int retval = i386_remove_aligned_watchpoint (&local_state, | |
1ced966e | 720 | addr, len_rw); |
52b98211 | 721 | |
edcc485a MR |
722 | if (retval == 0) |
723 | i386_update_inferior_debug_regs (&local_state); | |
724 | ||
52b98211 | 725 | if (maint_show_dr) |
1ced966e | 726 | i386_show_dr (&dr_mirror, "remove_hwbp", addr, 1, hw_execute); |
52b98211 EZ |
727 | |
728 | return retval; | |
729 | } | |
730 | ||
c03374d5 DJ |
731 | /* Returns the number of hardware watchpoints of type TYPE that we can |
732 | set. Value is positive if we can set CNT watchpoints, zero if | |
733 | setting watchpoints of type TYPE is not supported, and negative if | |
734 | CNT is more than the maximum number of watchpoints of type TYPE | |
735 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
736 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
737 | CNT is the number of such watchpoints used so far (including this | |
738 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
739 | currently enabled. | |
740 | ||
741 | We always return 1 here because we don't have enough information | |
742 | about possible overlap of addresses that they want to watch. As an | |
743 | extreme example, consider the case where all the watchpoints watch | |
744 | the same address and the same region length: then we can handle a | |
745 | virtually unlimited number of watchpoints, due to debug register | |
746 | sharing implemented via reference counts in i386-nat.c. */ | |
747 | ||
748 | static int | |
749 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
750 | { | |
751 | return 1; | |
752 | } | |
753 | ||
9bb9e8ad PM |
754 | static void |
755 | add_show_debug_regs_command (void) | |
756 | { | |
757 | /* A maintenance command to enable printing the internal DRi mirror | |
758 | variables. */ | |
759 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
760 | &maint_show_dr, _("\ | |
761 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
762 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
763 | Use \"on\" to enable, \"off\" to disable.\n\ | |
764 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
765 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
766 | triggers a breakpoint or watchpoint."), | |
767 | NULL, | |
768 | NULL, | |
769 | &maintenance_set_cmdlist, | |
770 | &maintenance_show_cmdlist); | |
771 | } | |
772 | ||
773 | /* There are only two global functions left. */ | |
774 | ||
c03374d5 DJ |
775 | void |
776 | i386_use_watchpoints (struct target_ops *t) | |
777 | { | |
778 | /* After a watchpoint trap, the PC points to the instruction after the | |
779 | one that caused the trap. Therefore we don't need to step over it. | |
780 | But we do need to reset the status register to avoid another trap. */ | |
781 | t->to_have_continuable_watchpoint = 1; | |
782 | ||
783 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
784 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
785 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
786 | t->to_stopped_data_address = i386_stopped_data_address; | |
787 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
788 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
789 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
790 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
791 | } | |
792 | ||
52b98211 | 793 | void |
9bb9e8ad | 794 | i386_set_debug_register_length (int len) |
52b98211 | 795 | { |
9bb9e8ad PM |
796 | /* This function should be called only once for each native target. */ |
797 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
798 | gdb_assert (len == 4 || len == 8); | |
799 | i386_dr_low.debug_register_length = len; | |
800 | add_show_debug_regs_command (); | |
52b98211 | 801 | } |