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7fa2737c MK |
1 | /* Native-dependent code for the i386. |
2 | ||
0fb0cc75 JB |
3 | Copyright (C) 2001, 2004, 2005, 2007, 2008, 2009 |
4 | Free Software Foundation, Inc. | |
52b98211 EZ |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
52b98211 EZ |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
52b98211 | 20 | |
9bb9e8ad | 21 | #include "i386-nat.h" |
52b98211 EZ |
22 | #include "defs.h" |
23 | #include "breakpoint.h" | |
24 | #include "command.h" | |
25 | #include "gdbcmd.h" | |
c03374d5 | 26 | #include "target.h" |
9bb9e8ad | 27 | #include "gdb_assert.h" |
52b98211 | 28 | |
7fa2737c | 29 | /* Support for hardware watchpoints and breakpoints using the i386 |
52b98211 EZ |
30 | debug registers. |
31 | ||
32 | This provides several functions for inserting and removing | |
7fa2737c MK |
33 | hardware-assisted breakpoints and watchpoints, testing if one or |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
7fa2737c MK |
37 | The functions below implement debug registers sharing by reference |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
52b98211 | 39 | |
9bb9e8ad PM |
40 | struct i386_dr_low_type i386_dr_low; |
41 | ||
52b98211 | 42 | |
e906b9a3 | 43 | /* Support for 8-byte wide hw watchpoints. */ |
9bb9e8ad | 44 | #define TARGET_HAS_DR_LEN_8 (i386_dr_low.debug_register_length == 8) |
e906b9a3 | 45 | |
52b98211 | 46 | /* Debug registers' indices. */ |
7fa2737c MK |
47 | #define DR_NADDR 4 /* The number of debug address registers. */ |
48 | #define DR_STATUS 6 /* Index of debug status register (DR6). */ | |
49 | #define DR_CONTROL 7 /* Index of debug control register (DR7). */ | |
52b98211 EZ |
50 | |
51 | /* DR7 Debug Control register fields. */ | |
52 | ||
53 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
54 | #define DR_CONTROL_SHIFT 16 | |
55 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
56 | #define DR_CONTROL_SIZE 4 | |
57 | ||
58 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
7fa2737c MK |
59 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ |
60 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
61 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
52b98211 EZ |
62 | |
63 | /* This is here for completeness. No platform supports this | |
7fa2737c | 64 | functionality yet (as of March 2001). Note that the DE flag in the |
52b98211 EZ |
65 | CR4 register needs to be set to support this. */ |
66 | #ifndef DR_RW_IORW | |
7fa2737c | 67 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ |
52b98211 EZ |
68 | #endif |
69 | ||
70 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
71 | is so we could OR this with the read/write field defined above. */ | |
7fa2737c MK |
72 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ |
73 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
74 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
75 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
52b98211 EZ |
76 | |
77 | /* Local and Global Enable flags in DR7. | |
78 | ||
79 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
80 | enabled only for the current task; the processor automatically | |
7fa2737c MK |
81 | clears this flag on every task switch. When the Global Enable flag |
82 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
83 | processor never clears this flag. | |
52b98211 EZ |
84 | |
85 | Currently, all watchpoint are locally enabled. If you need to | |
86 | enable them globally, read the comment which pertains to this in | |
87 | i386_insert_aligned_watchpoint below. */ | |
7fa2737c MK |
88 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ |
89 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
90 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
52b98211 EZ |
91 | |
92 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
93 | flags). These are only required on i386, to allow detection of the | |
94 | exact instruction which caused a watchpoint to break; i486 and | |
95 | later processors do that automatically. We set these flags for | |
7fa2737c | 96 | backwards compatibility. */ |
52b98211 | 97 | #define DR_LOCAL_SLOWDOWN (0x100) |
7fa2737c | 98 | #define DR_GLOBAL_SLOWDOWN (0x200) |
52b98211 EZ |
99 | |
100 | /* Fields reserved by Intel. This includes the GD (General Detect | |
101 | Enable) flag, which causes a debug exception to be generated when a | |
102 | MOV instruction accesses one of the debug registers. | |
103 | ||
104 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
105 | #define DR_CONTROL_RESERVED (0xFC00) | |
106 | ||
107 | /* Auxiliary helper macros. */ | |
108 | ||
109 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
7fa2737c | 110 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) |
52b98211 EZ |
111 | |
112 | /* The I'th debug register is vacant if its Local and Global Enable | |
113 | bits are reset in the Debug Control register. */ | |
114 | #define I386_DR_VACANT(i) \ | |
115 | ((dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
116 | ||
117 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
118 | #define I386_DR_LOCAL_ENABLE(i) \ | |
119 | dr_control_mirror |= (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) | |
120 | ||
121 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
122 | #define I386_DR_GLOBAL_ENABLE(i) \ | |
123 | dr_control_mirror |= (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))) | |
124 | ||
125 | /* Disable the break/watchpoint in the I'th debug register. */ | |
126 | #define I386_DR_DISABLE(i) \ | |
127 | dr_control_mirror &= ~(3 << (DR_ENABLE_SIZE * (i))) | |
128 | ||
129 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
130 | #define I386_DR_SET_RW_LEN(i,rwlen) \ | |
131 | do { \ | |
132 | dr_control_mirror &= ~(0x0f << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ | |
133 | dr_control_mirror |= ((rwlen) << (DR_CONTROL_SHIFT+DR_CONTROL_SIZE*(i))); \ | |
134 | } while (0) | |
135 | ||
136 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
137 | #define I386_DR_GET_RW_LEN(i) \ | |
138 | ((dr_control_mirror >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
139 | ||
140 | /* Did the watchpoint whose address is in the I'th register break? */ | |
141 | #define I386_DR_WATCH_HIT(i) (dr_status_mirror & (1 << (i))) | |
142 | ||
143 | /* A macro to loop over all debug registers. */ | |
144 | #define ALL_DEBUG_REGISTERS(i) for (i = 0; i < DR_NADDR; i++) | |
145 | ||
146 | /* Mirror the inferior's DRi registers. We keep the status and | |
147 | control registers separated because they don't hold addresses. */ | |
148 | static CORE_ADDR dr_mirror[DR_NADDR]; | |
9bb9e8ad | 149 | static unsigned long dr_status_mirror, dr_control_mirror; |
52b98211 EZ |
150 | |
151 | /* Reference counts for each debug register. */ | |
7fa2737c | 152 | static int dr_ref_count[DR_NADDR]; |
52b98211 EZ |
153 | |
154 | /* Whether or not to print the mirrored debug registers. */ | |
7fa2737c | 155 | static int maint_show_dr; |
52b98211 EZ |
156 | |
157 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
158 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
159 | ||
160 | /* Internal functions. */ | |
161 | ||
162 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
163 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
164 | have the value of 1, 2, or 4. */ | |
52b98211 EZ |
165 | static unsigned i386_length_and_rw_bits (int len, enum target_hw_bp_type type); |
166 | ||
167 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
168 | according to the length of the region to watch. LEN_RW_BITS is the | |
169 | value of the bit-field from DR7 which describes the length and | |
170 | access type of the region to be watched by this watchpoint. Return | |
171 | 0 on success, -1 on failure. */ | |
172 | static int i386_insert_aligned_watchpoint (CORE_ADDR addr, | |
173 | unsigned len_rw_bits); | |
174 | ||
175 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
176 | according to the length of the region to watch. LEN_RW_BITS is the | |
177 | value of the bits from DR7 which describes the length and access | |
178 | type of the region watched by this watchpoint. Return 0 on | |
179 | success, -1 on failure. */ | |
180 | static int i386_remove_aligned_watchpoint (CORE_ADDR addr, | |
181 | unsigned len_rw_bits); | |
182 | ||
183 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
184 | number of debug registers required to watch a region at address | |
185 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
186 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
187 | about the number of registers, or -1 on failure. If WHAT is not a |
188 | valid value, bombs through internal_error. */ | |
52b98211 EZ |
189 | static int i386_handle_nonaligned_watchpoint (i386_wp_op_t what, |
190 | CORE_ADDR addr, int len, | |
191 | enum target_hw_bp_type type); | |
192 | ||
193 | /* Implementation. */ | |
194 | ||
7fa2737c MK |
195 | /* Clear the reference counts and forget everything we knew about the |
196 | debug registers. */ | |
197 | ||
52b98211 EZ |
198 | void |
199 | i386_cleanup_dregs (void) | |
200 | { | |
201 | int i; | |
202 | ||
203 | ALL_DEBUG_REGISTERS(i) | |
204 | { | |
205 | dr_mirror[i] = 0; | |
206 | dr_ref_count[i] = 0; | |
207 | } | |
208 | dr_control_mirror = 0; | |
209 | dr_status_mirror = 0; | |
210 | } | |
211 | ||
7fa2737c MK |
212 | /* Print the values of the mirrored debug registers. This is called |
213 | when maint_show_dr is non-zero. To set that up, type "maint | |
214 | show-debug-regs" at GDB's prompt. */ | |
215 | ||
52b98211 EZ |
216 | static void |
217 | i386_show_dr (const char *func, CORE_ADDR addr, | |
218 | int len, enum target_hw_bp_type type) | |
219 | { | |
220 | int i; | |
221 | ||
222 | puts_unfiltered (func); | |
223 | if (addr || len) | |
224 | printf_unfiltered (" (addr=%lx, len=%d, type=%s)", | |
225 | /* This code is for ia32, so casting CORE_ADDR | |
226 | to unsigned long should be okay. */ | |
227 | (unsigned long)addr, len, | |
228 | type == hw_write ? "data-write" | |
229 | : (type == hw_read ? "data-read" | |
230 | : (type == hw_access ? "data-read/write" | |
231 | : (type == hw_execute ? "instruction-execute" | |
232 | /* FIXME: if/when I/O read/write | |
233 | watchpoints are supported, add them | |
234 | here. */ | |
235 | : "??unknown??")))); | |
236 | puts_unfiltered (":\n"); | |
9bb9e8ad PM |
237 | printf_unfiltered ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", |
238 | phex (dr_control_mirror, 8), phex (dr_status_mirror, 8)); | |
52b98211 EZ |
239 | ALL_DEBUG_REGISTERS(i) |
240 | { | |
7fa2737c MK |
241 | printf_unfiltered ("\ |
242 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
e906b9a3 JS |
243 | i, paddr(dr_mirror[i]), dr_ref_count[i], |
244 | i+1, paddr(dr_mirror[i+1]), dr_ref_count[i+1]); | |
52b98211 EZ |
245 | i++; |
246 | } | |
247 | } | |
248 | ||
249 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
7fa2737c MK |
250 | region of LEN bytes for accesses of type TYPE. LEN is assumed to |
251 | have the value of 1, 2, or 4. */ | |
252 | ||
52b98211 EZ |
253 | static unsigned |
254 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
255 | { | |
256 | unsigned rw; | |
257 | ||
258 | switch (type) | |
259 | { | |
260 | case hw_execute: | |
261 | rw = DR_RW_EXECUTE; | |
262 | break; | |
263 | case hw_write: | |
264 | rw = DR_RW_WRITE; | |
265 | break; | |
7fa2737c MK |
266 | case hw_read: |
267 | /* The i386 doesn't support data-read watchpoints. */ | |
52b98211 EZ |
268 | case hw_access: |
269 | rw = DR_RW_READ; | |
270 | break; | |
271 | #if 0 | |
7fa2737c MK |
272 | /* Not yet supported. */ |
273 | case hw_io_access: | |
52b98211 EZ |
274 | rw = DR_RW_IORW; |
275 | break; | |
276 | #endif | |
277 | default: | |
e2e0b3e5 AC |
278 | internal_error (__FILE__, __LINE__, _("\ |
279 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
7fa2737c | 280 | (int) type); |
52b98211 EZ |
281 | } |
282 | ||
283 | switch (len) | |
284 | { | |
52b98211 EZ |
285 | case 1: |
286 | return (DR_LEN_1 | rw); | |
e906b9a3 JS |
287 | case 2: |
288 | return (DR_LEN_2 | rw); | |
289 | case 4: | |
290 | return (DR_LEN_4 | rw); | |
291 | case 8: | |
292 | if (TARGET_HAS_DR_LEN_8) | |
293 | return (DR_LEN_8 | rw); | |
52b98211 | 294 | default: |
e2e0b3e5 AC |
295 | internal_error (__FILE__, __LINE__, _("\ |
296 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
52b98211 EZ |
297 | } |
298 | } | |
299 | ||
300 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
301 | according to the length of the region to watch. LEN_RW_BITS is the | |
302 | value of the bits from DR7 which describes the length and access | |
303 | type of the region to be watched by this watchpoint. Return 0 on | |
304 | success, -1 on failure. */ | |
7fa2737c | 305 | |
52b98211 EZ |
306 | static int |
307 | i386_insert_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) | |
308 | { | |
309 | int i; | |
310 | ||
9bb9e8ad PM |
311 | if (!i386_dr_low.set_addr || !i386_dr_low.set_control) |
312 | return -1; | |
313 | ||
52b98211 EZ |
314 | /* First, look for an occupied debug register with the same address |
315 | and the same RW and LEN definitions. If we find one, we can | |
316 | reuse it for this watchpoint as well (and save a register). */ | |
317 | ALL_DEBUG_REGISTERS(i) | |
318 | { | |
319 | if (!I386_DR_VACANT (i) | |
320 | && dr_mirror[i] == addr | |
321 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) | |
322 | { | |
323 | dr_ref_count[i]++; | |
324 | return 0; | |
325 | } | |
326 | } | |
327 | ||
328 | /* Next, look for a vacant debug register. */ | |
329 | ALL_DEBUG_REGISTERS(i) | |
330 | { | |
331 | if (I386_DR_VACANT (i)) | |
332 | break; | |
333 | } | |
334 | ||
335 | /* No more debug registers! */ | |
336 | if (i >= DR_NADDR) | |
337 | return -1; | |
338 | ||
339 | /* Now set up the register I to watch our region. */ | |
340 | ||
341 | /* Record the info in our local mirrored array. */ | |
342 | dr_mirror[i] = addr; | |
343 | dr_ref_count[i] = 1; | |
344 | I386_DR_SET_RW_LEN (i, len_rw_bits); | |
345 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
7fa2737c | 346 | task. Currently, no i386 target allows or supports global |
52b98211 EZ |
347 | watchpoints; however, if any target would want that in the |
348 | future, GDB should probably provide a command to control whether | |
349 | to enable watchpoints globally or locally, and the code below | |
350 | should use global or local enable and slow-down flags as | |
351 | appropriate. */ | |
352 | I386_DR_LOCAL_ENABLE (i); | |
353 | dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
354 | dr_control_mirror &= I386_DR_CONTROL_MASK; | |
355 | ||
356 | /* Finally, actually pass the info to the inferior. */ | |
9bb9e8ad PM |
357 | i386_dr_low.set_addr (i, addr); |
358 | i386_dr_low.set_control (dr_control_mirror); | |
52b98211 EZ |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
363 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
364 | according to the length of the region to watch. LEN_RW_BITS is the | |
365 | value of the bits from DR7 which describes the length and access | |
366 | type of the region watched by this watchpoint. Return 0 on | |
367 | success, -1 on failure. */ | |
7fa2737c | 368 | |
52b98211 EZ |
369 | static int |
370 | i386_remove_aligned_watchpoint (CORE_ADDR addr, unsigned len_rw_bits) | |
371 | { | |
372 | int i, retval = -1; | |
373 | ||
374 | ALL_DEBUG_REGISTERS(i) | |
375 | { | |
376 | if (!I386_DR_VACANT (i) | |
377 | && dr_mirror[i] == addr | |
378 | && I386_DR_GET_RW_LEN (i) == len_rw_bits) | |
379 | { | |
380 | if (--dr_ref_count[i] == 0) /* no longer in use? */ | |
381 | { | |
382 | /* Reset our mirror. */ | |
383 | dr_mirror[i] = 0; | |
384 | I386_DR_DISABLE (i); | |
385 | /* Reset it in the inferior. */ | |
9bb9e8ad PM |
386 | i386_dr_low.set_control (dr_control_mirror); |
387 | if (i386_dr_low.reset_addr) | |
388 | i386_dr_low.reset_addr (i); | |
52b98211 EZ |
389 | } |
390 | retval = 0; | |
391 | } | |
392 | } | |
393 | ||
394 | return retval; | |
395 | } | |
396 | ||
397 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
398 | number of debug registers required to watch a region at address | |
399 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
400 | successful insertion or removal, a positive number when queried | |
7fa2737c MK |
401 | about the number of registers, or -1 on failure. If WHAT is not a |
402 | valid value, bombs through internal_error. */ | |
403 | ||
52b98211 EZ |
404 | static int |
405 | i386_handle_nonaligned_watchpoint (i386_wp_op_t what, CORE_ADDR addr, int len, | |
406 | enum target_hw_bp_type type) | |
407 | { | |
7fa2737c | 408 | int retval = 0, status = 0; |
e906b9a3 | 409 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; |
52b98211 | 410 | |
e906b9a3 | 411 | static int size_try_array[8][8] = |
52b98211 | 412 | { |
7fa2737c MK |
413 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ |
414 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
415 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
416 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
417 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
418 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
419 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
420 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
52b98211 EZ |
421 | }; |
422 | ||
423 | while (len > 0) | |
424 | { | |
7fa2737c | 425 | int align = addr % max_wp_len; |
f2e7c15d | 426 | /* Four (eight on AMD64) is the maximum length a debug register |
e906b9a3 | 427 | can watch. */ |
7fa2737c MK |
428 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); |
429 | int size = size_try_array[try][align]; | |
430 | ||
52b98211 | 431 | if (what == WP_COUNT) |
7fa2737c MK |
432 | { |
433 | /* size_try_array[] is defined such that each iteration | |
434 | through the loop is guaranteed to produce an address and a | |
435 | size that can be watched with a single debug register. | |
436 | Thus, for counting the registers required to watch a | |
437 | region, we simply need to increment the count on each | |
438 | iteration. */ | |
439 | retval++; | |
440 | } | |
52b98211 EZ |
441 | else |
442 | { | |
443 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
444 | ||
445 | if (what == WP_INSERT) | |
446 | status = i386_insert_aligned_watchpoint (addr, len_rw); | |
447 | else if (what == WP_REMOVE) | |
448 | status = i386_remove_aligned_watchpoint (addr, len_rw); | |
449 | else | |
e2e0b3e5 AC |
450 | internal_error (__FILE__, __LINE__, _("\ |
451 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
52b98211 EZ |
452 | (int)what); |
453 | /* We keep the loop going even after a failure, because some | |
454 | of the other aligned watchpoints might still succeed | |
455 | (e.g. if they watch addresses that are already watched, | |
456 | in which case we just increment the reference counts of | |
457 | occupied debug registers). If we break out of the loop | |
458 | too early, we could cause those addresses watched by | |
459 | other watchpoints to be disabled when breakpoint.c reacts | |
460 | to our failure to insert this watchpoint and tries to | |
461 | remove it. */ | |
462 | if (status) | |
7fa2737c | 463 | retval = status; |
52b98211 | 464 | } |
7fa2737c | 465 | |
52b98211 EZ |
466 | addr += size; |
467 | len -= size; | |
468 | } | |
7fa2737c MK |
469 | |
470 | return retval; | |
52b98211 EZ |
471 | } |
472 | ||
473 | /* Insert a watchpoint to watch a memory region which starts at | |
474 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
475 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
7fa2737c | 476 | |
9bb9e8ad | 477 | static int |
52b98211 EZ |
478 | i386_insert_watchpoint (CORE_ADDR addr, int len, int type) |
479 | { | |
480 | int retval; | |
481 | ||
e906b9a3 JS |
482 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
483 | || addr % len != 0) | |
52b98211 EZ |
484 | retval = i386_handle_nonaligned_watchpoint (WP_INSERT, addr, len, type); |
485 | else | |
486 | { | |
487 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
488 | ||
489 | retval = i386_insert_aligned_watchpoint (addr, len_rw); | |
490 | } | |
491 | ||
492 | if (maint_show_dr) | |
493 | i386_show_dr ("insert_watchpoint", addr, len, type); | |
494 | ||
495 | return retval; | |
496 | } | |
497 | ||
498 | /* Remove a watchpoint that watched the memory region which starts at | |
499 | address ADDR, whose length is LEN bytes, and for accesses of the | |
500 | type TYPE. Return 0 on success, -1 on failure. */ | |
9bb9e8ad | 501 | static int |
52b98211 EZ |
502 | i386_remove_watchpoint (CORE_ADDR addr, int len, int type) |
503 | { | |
504 | int retval; | |
505 | ||
e906b9a3 JS |
506 | if (((len != 1 && len !=2 && len !=4) && !(TARGET_HAS_DR_LEN_8 && len == 8)) |
507 | || addr % len != 0) | |
52b98211 EZ |
508 | retval = i386_handle_nonaligned_watchpoint (WP_REMOVE, addr, len, type); |
509 | else | |
510 | { | |
511 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
512 | ||
513 | retval = i386_remove_aligned_watchpoint (addr, len_rw); | |
514 | } | |
515 | ||
516 | if (maint_show_dr) | |
517 | i386_show_dr ("remove_watchpoint", addr, len, type); | |
518 | ||
519 | return retval; | |
520 | } | |
521 | ||
522 | /* Return non-zero if we can watch a memory region that starts at | |
523 | address ADDR and whose length is LEN bytes. */ | |
7fa2737c | 524 | |
9bb9e8ad | 525 | static int |
52b98211 EZ |
526 | i386_region_ok_for_watchpoint (CORE_ADDR addr, int len) |
527 | { | |
7fa2737c MK |
528 | int nregs; |
529 | ||
52b98211 EZ |
530 | /* Compute how many aligned watchpoints we would need to cover this |
531 | region. */ | |
7fa2737c | 532 | nregs = i386_handle_nonaligned_watchpoint (WP_COUNT, addr, len, hw_write); |
52b98211 EZ |
533 | return nregs <= DR_NADDR ? 1 : 0; |
534 | } | |
535 | ||
4aa7a7f5 JJ |
536 | /* If the inferior has some watchpoint that triggered, set the |
537 | address associated with that watchpoint and return non-zero. | |
538 | Otherwise, return zero. */ | |
7fa2737c | 539 | |
9bb9e8ad | 540 | static int |
c03374d5 | 541 | i386_stopped_data_address (struct target_ops *ops, CORE_ADDR *addr_p) |
52b98211 | 542 | { |
7fa2737c | 543 | CORE_ADDR addr = 0; |
52b98211 | 544 | int i; |
4aa7a7f5 | 545 | int rc = 0; |
52b98211 | 546 | |
9bb9e8ad | 547 | dr_status_mirror = i386_dr_low.get_status (); |
52b98211 EZ |
548 | |
549 | ALL_DEBUG_REGISTERS(i) | |
550 | { | |
551 | if (I386_DR_WATCH_HIT (i) | |
552 | /* This second condition makes sure DRi is set up for a data | |
553 | watchpoint, not a hardware breakpoint. The reason is | |
554 | that GDB doesn't call the target_stopped_data_address | |
555 | method except for data watchpoints. In other words, I'm | |
f2e7c15d | 556 | being paranoiac. */ |
52b98211 EZ |
557 | && I386_DR_GET_RW_LEN (i) != 0) |
558 | { | |
7fa2737c | 559 | addr = dr_mirror[i]; |
4aa7a7f5 | 560 | rc = 1; |
52b98211 | 561 | if (maint_show_dr) |
7fa2737c | 562 | i386_show_dr ("watchpoint_hit", addr, -1, hw_write); |
52b98211 EZ |
563 | } |
564 | } | |
7fa2737c | 565 | if (maint_show_dr && addr == 0) |
52b98211 EZ |
566 | i386_show_dr ("stopped_data_addr", 0, 0, hw_write); |
567 | ||
4aa7a7f5 JJ |
568 | if (rc) |
569 | *addr_p = addr; | |
570 | return rc; | |
571 | } | |
572 | ||
9bb9e8ad | 573 | static int |
4aa7a7f5 JJ |
574 | i386_stopped_by_watchpoint (void) |
575 | { | |
576 | CORE_ADDR addr = 0; | |
c03374d5 | 577 | return i386_stopped_data_address (¤t_target, &addr); |
52b98211 EZ |
578 | } |
579 | ||
580 | /* Return non-zero if the inferior has some break/watchpoint that | |
581 | triggered. */ | |
7fa2737c | 582 | |
9bb9e8ad | 583 | static int |
52b98211 EZ |
584 | i386_stopped_by_hwbp (void) |
585 | { | |
586 | int i; | |
587 | ||
9bb9e8ad | 588 | dr_status_mirror = i386_dr_low.get_status (); |
52b98211 EZ |
589 | if (maint_show_dr) |
590 | i386_show_dr ("stopped_by_hwbp", 0, 0, hw_execute); | |
591 | ||
592 | ALL_DEBUG_REGISTERS(i) | |
593 | { | |
594 | if (I386_DR_WATCH_HIT (i)) | |
595 | return 1; | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
8181d85f DJ |
601 | /* Insert a hardware-assisted breakpoint at BP_TGT->placed_address. |
602 | Return 0 on success, EBUSY on failure. */ | |
9bb9e8ad | 603 | static int |
8181d85f | 604 | i386_insert_hw_breakpoint (struct bp_target_info *bp_tgt) |
52b98211 EZ |
605 | { |
606 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 607 | CORE_ADDR addr = bp_tgt->placed_address; |
52b98211 EZ |
608 | int retval = i386_insert_aligned_watchpoint (addr, len_rw) ? EBUSY : 0; |
609 | ||
610 | if (maint_show_dr) | |
611 | i386_show_dr ("insert_hwbp", addr, 1, hw_execute); | |
612 | ||
613 | return retval; | |
614 | } | |
615 | ||
8181d85f DJ |
616 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. |
617 | Return 0 on success, -1 on failure. */ | |
7fa2737c | 618 | |
9bb9e8ad | 619 | static int |
8181d85f | 620 | i386_remove_hw_breakpoint (struct bp_target_info *bp_tgt) |
52b98211 EZ |
621 | { |
622 | unsigned len_rw = i386_length_and_rw_bits (1, hw_execute); | |
8181d85f | 623 | CORE_ADDR addr = bp_tgt->placed_address; |
52b98211 EZ |
624 | int retval = i386_remove_aligned_watchpoint (addr, len_rw); |
625 | ||
626 | if (maint_show_dr) | |
627 | i386_show_dr ("remove_hwbp", addr, 1, hw_execute); | |
628 | ||
629 | return retval; | |
630 | } | |
631 | ||
c03374d5 DJ |
632 | /* Returns the number of hardware watchpoints of type TYPE that we can |
633 | set. Value is positive if we can set CNT watchpoints, zero if | |
634 | setting watchpoints of type TYPE is not supported, and negative if | |
635 | CNT is more than the maximum number of watchpoints of type TYPE | |
636 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
637 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
638 | CNT is the number of such watchpoints used so far (including this | |
639 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
640 | currently enabled. | |
641 | ||
642 | We always return 1 here because we don't have enough information | |
643 | about possible overlap of addresses that they want to watch. As an | |
644 | extreme example, consider the case where all the watchpoints watch | |
645 | the same address and the same region length: then we can handle a | |
646 | virtually unlimited number of watchpoints, due to debug register | |
647 | sharing implemented via reference counts in i386-nat.c. */ | |
648 | ||
649 | static int | |
650 | i386_can_use_hw_breakpoint (int type, int cnt, int othertype) | |
651 | { | |
652 | return 1; | |
653 | } | |
654 | ||
9bb9e8ad PM |
655 | static void |
656 | add_show_debug_regs_command (void) | |
657 | { | |
658 | /* A maintenance command to enable printing the internal DRi mirror | |
659 | variables. */ | |
660 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
661 | &maint_show_dr, _("\ | |
662 | Set whether to show variables that mirror the x86 debug registers."), _("\ | |
663 | Show whether to show variables that mirror the x86 debug registers."), _("\ | |
664 | Use \"on\" to enable, \"off\" to disable.\n\ | |
665 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
666 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
667 | triggers a breakpoint or watchpoint."), | |
668 | NULL, | |
669 | NULL, | |
670 | &maintenance_set_cmdlist, | |
671 | &maintenance_show_cmdlist); | |
672 | } | |
673 | ||
674 | /* There are only two global functions left. */ | |
675 | ||
c03374d5 DJ |
676 | void |
677 | i386_use_watchpoints (struct target_ops *t) | |
678 | { | |
679 | /* After a watchpoint trap, the PC points to the instruction after the | |
680 | one that caused the trap. Therefore we don't need to step over it. | |
681 | But we do need to reset the status register to avoid another trap. */ | |
682 | t->to_have_continuable_watchpoint = 1; | |
683 | ||
684 | t->to_can_use_hw_breakpoint = i386_can_use_hw_breakpoint; | |
685 | t->to_region_ok_for_hw_watchpoint = i386_region_ok_for_watchpoint; | |
686 | t->to_stopped_by_watchpoint = i386_stopped_by_watchpoint; | |
687 | t->to_stopped_data_address = i386_stopped_data_address; | |
688 | t->to_insert_watchpoint = i386_insert_watchpoint; | |
689 | t->to_remove_watchpoint = i386_remove_watchpoint; | |
690 | t->to_insert_hw_breakpoint = i386_insert_hw_breakpoint; | |
691 | t->to_remove_hw_breakpoint = i386_remove_hw_breakpoint; | |
692 | } | |
693 | ||
52b98211 | 694 | void |
9bb9e8ad | 695 | i386_set_debug_register_length (int len) |
52b98211 | 696 | { |
9bb9e8ad PM |
697 | /* This function should be called only once for each native target. */ |
698 | gdb_assert (i386_dr_low.debug_register_length == 0); | |
699 | gdb_assert (len == 4 || len == 8); | |
700 | i386_dr_low.debug_register_length = len; | |
701 | add_show_debug_regs_command (); | |
52b98211 | 702 | } |