Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f AC |
2 | |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, | |
4754a64e | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software |
931aecf5 | 5 | Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
acd5c798 MK |
25 | #include "arch-utils.h" |
26 | #include "command.h" | |
27 | #include "dummy-frame.h" | |
6405b0a6 | 28 | #include "dwarf2-frame.h" |
acd5c798 MK |
29 | #include "doublest.h" |
30 | #include "floatformat.h" | |
c906108c | 31 | #include "frame.h" |
acd5c798 MK |
32 | #include "frame-base.h" |
33 | #include "frame-unwind.h" | |
c906108c | 34 | #include "inferior.h" |
acd5c798 | 35 | #include "gdbcmd.h" |
c906108c | 36 | #include "gdbcore.h" |
dfe01d39 | 37 | #include "objfiles.h" |
acd5c798 MK |
38 | #include "osabi.h" |
39 | #include "regcache.h" | |
40 | #include "reggroups.h" | |
473f17b0 | 41 | #include "regset.h" |
c0d1d883 | 42 | #include "symfile.h" |
c906108c | 43 | #include "symtab.h" |
acd5c798 | 44 | #include "target.h" |
fd0407d6 | 45 | #include "value.h" |
a89aa300 | 46 | #include "dis-asm.h" |
acd5c798 | 47 | |
3d261580 | 48 | #include "gdb_assert.h" |
acd5c798 | 49 | #include "gdb_string.h" |
3d261580 | 50 | |
d2a7c97a | 51 | #include "i386-tdep.h" |
61113f8b | 52 | #include "i387-tdep.h" |
d2a7c97a | 53 | |
c4fc7f1b | 54 | /* Register names. */ |
c40e1eab | 55 | |
fc633446 MK |
56 | static char *i386_register_names[] = |
57 | { | |
58 | "eax", "ecx", "edx", "ebx", | |
59 | "esp", "ebp", "esi", "edi", | |
60 | "eip", "eflags", "cs", "ss", | |
61 | "ds", "es", "fs", "gs", | |
62 | "st0", "st1", "st2", "st3", | |
63 | "st4", "st5", "st6", "st7", | |
64 | "fctrl", "fstat", "ftag", "fiseg", | |
65 | "fioff", "foseg", "fooff", "fop", | |
66 | "xmm0", "xmm1", "xmm2", "xmm3", | |
67 | "xmm4", "xmm5", "xmm6", "xmm7", | |
68 | "mxcsr" | |
69 | }; | |
70 | ||
1cb97e17 | 71 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 72 | |
c4fc7f1b | 73 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
74 | |
75 | static char *i386_mmx_names[] = | |
76 | { | |
77 | "mm0", "mm1", "mm2", "mm3", | |
78 | "mm4", "mm5", "mm6", "mm7" | |
79 | }; | |
c40e1eab | 80 | |
1cb97e17 | 81 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 82 | |
28fc6740 | 83 | static int |
5716833c | 84 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 85 | { |
5716833c MK |
86 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
87 | ||
88 | if (mm0_regnum < 0) | |
89 | return 0; | |
90 | ||
91 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
92 | } |
93 | ||
5716833c | 94 | /* SSE register? */ |
23a34459 | 95 | |
5716833c MK |
96 | static int |
97 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 98 | { |
5716833c MK |
99 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
100 | ||
101 | #define I387_ST0_REGNUM tdep->st0_regnum | |
102 | #define I387_NUM_XMM_REGS tdep->num_xmm_regs | |
103 | ||
104 | if (I387_NUM_XMM_REGS == 0) | |
105 | return 0; | |
106 | ||
107 | return (I387_XMM0_REGNUM <= regnum && regnum < I387_MXCSR_REGNUM); | |
108 | ||
109 | #undef I387_ST0_REGNUM | |
110 | #undef I387_NUM_XMM_REGS | |
23a34459 AC |
111 | } |
112 | ||
5716833c MK |
113 | static int |
114 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 115 | { |
5716833c MK |
116 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
117 | ||
118 | #define I387_ST0_REGNUM tdep->st0_regnum | |
119 | #define I387_NUM_XMM_REGS tdep->num_xmm_regs | |
120 | ||
121 | if (I387_NUM_XMM_REGS == 0) | |
122 | return 0; | |
123 | ||
124 | return (regnum == I387_MXCSR_REGNUM); | |
125 | ||
126 | #undef I387_ST0_REGNUM | |
127 | #undef I387_NUM_XMM_REGS | |
23a34459 AC |
128 | } |
129 | ||
5716833c MK |
130 | #define I387_ST0_REGNUM (gdbarch_tdep (current_gdbarch)->st0_regnum) |
131 | #define I387_MM0_REGNUM (gdbarch_tdep (current_gdbarch)->mm0_regnum) | |
132 | #define I387_NUM_XMM_REGS (gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
133 | ||
134 | /* FP register? */ | |
23a34459 AC |
135 | |
136 | int | |
5716833c | 137 | i386_fp_regnum_p (int regnum) |
23a34459 | 138 | { |
5716833c MK |
139 | if (I387_ST0_REGNUM < 0) |
140 | return 0; | |
141 | ||
142 | return (I387_ST0_REGNUM <= regnum && regnum < I387_FCTRL_REGNUM); | |
23a34459 AC |
143 | } |
144 | ||
145 | int | |
5716833c | 146 | i386_fpc_regnum_p (int regnum) |
23a34459 | 147 | { |
5716833c MK |
148 | if (I387_ST0_REGNUM < 0) |
149 | return 0; | |
150 | ||
151 | return (I387_FCTRL_REGNUM <= regnum && regnum < I387_XMM0_REGNUM); | |
23a34459 AC |
152 | } |
153 | ||
30b0e2d8 | 154 | /* Return the name of register REGNUM. */ |
fc633446 | 155 | |
fa88f677 | 156 | const char * |
30b0e2d8 | 157 | i386_register_name (int regnum) |
fc633446 | 158 | { |
30b0e2d8 MK |
159 | if (i386_mmx_regnum_p (current_gdbarch, regnum)) |
160 | return i386_mmx_names[regnum - I387_MM0_REGNUM]; | |
fc633446 | 161 | |
30b0e2d8 MK |
162 | if (regnum >= 0 && regnum < i386_num_register_names) |
163 | return i386_register_names[regnum]; | |
70913449 | 164 | |
c40e1eab | 165 | return NULL; |
fc633446 MK |
166 | } |
167 | ||
c4fc7f1b | 168 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
169 | number used by GDB. */ |
170 | ||
8201327c | 171 | static int |
c4fc7f1b | 172 | i386_dbx_reg_to_regnum (int reg) |
85540d8c | 173 | { |
c4fc7f1b MK |
174 | /* This implements what GCC calls the "default" register map |
175 | (dbx_register_map[]). */ | |
176 | ||
85540d8c MK |
177 | if (reg >= 0 && reg <= 7) |
178 | { | |
9872ad24 JB |
179 | /* General-purpose registers. The debug info calls %ebp |
180 | register 4, and %esp register 5. */ | |
181 | if (reg == 4) | |
182 | return 5; | |
183 | else if (reg == 5) | |
184 | return 4; | |
185 | else return reg; | |
85540d8c MK |
186 | } |
187 | else if (reg >= 12 && reg <= 19) | |
188 | { | |
189 | /* Floating-point registers. */ | |
5716833c | 190 | return reg - 12 + I387_ST0_REGNUM; |
85540d8c MK |
191 | } |
192 | else if (reg >= 21 && reg <= 28) | |
193 | { | |
194 | /* SSE registers. */ | |
5716833c | 195 | return reg - 21 + I387_XMM0_REGNUM; |
85540d8c MK |
196 | } |
197 | else if (reg >= 29 && reg <= 36) | |
198 | { | |
199 | /* MMX registers. */ | |
5716833c | 200 | return reg - 29 + I387_MM0_REGNUM; |
85540d8c MK |
201 | } |
202 | ||
203 | /* This will hopefully provoke a warning. */ | |
204 | return NUM_REGS + NUM_PSEUDO_REGS; | |
205 | } | |
206 | ||
c4fc7f1b MK |
207 | /* Convert SVR4 register number REG to the appropriate register number |
208 | used by GDB. */ | |
85540d8c | 209 | |
8201327c | 210 | static int |
c4fc7f1b | 211 | i386_svr4_reg_to_regnum (int reg) |
85540d8c | 212 | { |
c4fc7f1b MK |
213 | /* This implements the GCC register map that tries to be compatible |
214 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
215 | ||
216 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
217 | numbers the floating point registers differently. */ |
218 | if (reg >= 0 && reg <= 9) | |
219 | { | |
acd5c798 | 220 | /* General-purpose registers. */ |
85540d8c MK |
221 | return reg; |
222 | } | |
223 | else if (reg >= 11 && reg <= 18) | |
224 | { | |
225 | /* Floating-point registers. */ | |
5716833c | 226 | return reg - 11 + I387_ST0_REGNUM; |
85540d8c MK |
227 | } |
228 | else if (reg >= 21) | |
229 | { | |
c4fc7f1b MK |
230 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
231 | return i386_dbx_reg_to_regnum (reg); | |
85540d8c MK |
232 | } |
233 | ||
234 | /* This will hopefully provoke a warning. */ | |
235 | return NUM_REGS + NUM_PSEUDO_REGS; | |
236 | } | |
5716833c MK |
237 | |
238 | #undef I387_ST0_REGNUM | |
239 | #undef I387_MM0_REGNUM | |
240 | #undef I387_NUM_XMM_REGS | |
fc338970 | 241 | \f |
917317f4 | 242 | |
fc338970 MK |
243 | /* This is the variable that is set with "set disassembly-flavor", and |
244 | its legitimate values. */ | |
53904c9e AC |
245 | static const char att_flavor[] = "att"; |
246 | static const char intel_flavor[] = "intel"; | |
247 | static const char *valid_flavors[] = | |
c5aa993b | 248 | { |
c906108c SS |
249 | att_flavor, |
250 | intel_flavor, | |
251 | NULL | |
252 | }; | |
53904c9e | 253 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 254 | \f |
c906108c | 255 | |
acd5c798 MK |
256 | /* Use the program counter to determine the contents and size of a |
257 | breakpoint instruction. Return a pointer to a string of bytes that | |
258 | encode a breakpoint instruction, store the length of the string in | |
259 | *LEN and optionally adjust *PC to point to the correct memory | |
260 | location for inserting the breakpoint. | |
c906108c | 261 | |
acd5c798 MK |
262 | On the i386 we have a single breakpoint that fits in a single byte |
263 | and can be inserted anywhere. | |
c906108c | 264 | |
acd5c798 MK |
265 | This function is 64-bit safe. */ |
266 | ||
267 | static const unsigned char * | |
268 | i386_breakpoint_from_pc (CORE_ADDR *pc, int *len) | |
c906108c | 269 | { |
acd5c798 MK |
270 | static unsigned char break_insn[] = { 0xcc }; /* int 3 */ |
271 | ||
272 | *len = sizeof (break_insn); | |
273 | return break_insn; | |
c906108c | 274 | } |
fc338970 | 275 | \f |
acd5c798 MK |
276 | #ifdef I386_REGNO_TO_SYMMETRY |
277 | #error "The Sequent Symmetry is no longer supported." | |
278 | #endif | |
c906108c | 279 | |
acd5c798 MK |
280 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
281 | and %esp "belong" to the calling function. Therefore these | |
282 | registers should be saved if they're going to be modified. */ | |
c906108c | 283 | |
acd5c798 MK |
284 | /* The maximum number of saved registers. This should include all |
285 | registers mentioned above, and %eip. */ | |
a3386186 | 286 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
287 | |
288 | struct i386_frame_cache | |
c906108c | 289 | { |
acd5c798 MK |
290 | /* Base address. */ |
291 | CORE_ADDR base; | |
292 | CORE_ADDR sp_offset; | |
293 | CORE_ADDR pc; | |
294 | ||
fd13a04a AC |
295 | /* Saved registers. */ |
296 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 MK |
297 | CORE_ADDR saved_sp; |
298 | int pc_in_eax; | |
299 | ||
300 | /* Stack space reserved for local variables. */ | |
301 | long locals; | |
302 | }; | |
303 | ||
304 | /* Allocate and initialize a frame cache. */ | |
305 | ||
306 | static struct i386_frame_cache * | |
fd13a04a | 307 | i386_alloc_frame_cache (void) |
acd5c798 MK |
308 | { |
309 | struct i386_frame_cache *cache; | |
310 | int i; | |
311 | ||
312 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
313 | ||
314 | /* Base address. */ | |
315 | cache->base = 0; | |
316 | cache->sp_offset = -4; | |
317 | cache->pc = 0; | |
318 | ||
fd13a04a AC |
319 | /* Saved registers. We initialize these to -1 since zero is a valid |
320 | offset (that's where %ebp is supposed to be stored). */ | |
321 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
322 | cache->saved_regs[i] = -1; | |
acd5c798 MK |
323 | cache->saved_sp = 0; |
324 | cache->pc_in_eax = 0; | |
325 | ||
326 | /* Frameless until proven otherwise. */ | |
327 | cache->locals = -1; | |
328 | ||
329 | return cache; | |
330 | } | |
c906108c | 331 | |
acd5c798 MK |
332 | /* If the instruction at PC is a jump, return the address of its |
333 | target. Otherwise, return PC. */ | |
c906108c | 334 | |
acd5c798 MK |
335 | static CORE_ADDR |
336 | i386_follow_jump (CORE_ADDR pc) | |
337 | { | |
338 | unsigned char op; | |
339 | long delta = 0; | |
340 | int data16 = 0; | |
c906108c | 341 | |
acd5c798 MK |
342 | op = read_memory_unsigned_integer (pc, 1); |
343 | if (op == 0x66) | |
c906108c | 344 | { |
c906108c | 345 | data16 = 1; |
acd5c798 | 346 | op = read_memory_unsigned_integer (pc + 1, 1); |
c906108c SS |
347 | } |
348 | ||
acd5c798 | 349 | switch (op) |
c906108c SS |
350 | { |
351 | case 0xe9: | |
fc338970 | 352 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
353 | if (data16) |
354 | { | |
acd5c798 | 355 | delta = read_memory_integer (pc + 2, 2); |
c906108c | 356 | |
fc338970 MK |
357 | /* Include the size of the jmp instruction (including the |
358 | 0x66 prefix). */ | |
acd5c798 | 359 | delta += 4; |
c906108c SS |
360 | } |
361 | else | |
362 | { | |
acd5c798 | 363 | delta = read_memory_integer (pc + 1, 4); |
c906108c | 364 | |
acd5c798 MK |
365 | /* Include the size of the jmp instruction. */ |
366 | delta += 5; | |
c906108c SS |
367 | } |
368 | break; | |
369 | case 0xeb: | |
fc338970 | 370 | /* Relative jump, disp8 (ignore data16). */ |
acd5c798 | 371 | delta = read_memory_integer (pc + data16 + 1, 1); |
c906108c | 372 | |
acd5c798 | 373 | delta += data16 + 2; |
c906108c SS |
374 | break; |
375 | } | |
c906108c | 376 | |
acd5c798 MK |
377 | return pc + delta; |
378 | } | |
fc338970 | 379 | |
acd5c798 MK |
380 | /* Check whether PC points at a prologue for a function returning a |
381 | structure or union. If so, it updates CACHE and returns the | |
382 | address of the first instruction after the code sequence that | |
383 | removes the "hidden" argument from the stack or CURRENT_PC, | |
384 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 385 | |
acd5c798 MK |
386 | static CORE_ADDR |
387 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
388 | struct i386_frame_cache *cache) | |
c906108c | 389 | { |
acd5c798 MK |
390 | /* Functions that return a structure or union start with: |
391 | ||
392 | popl %eax 0x58 | |
393 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
394 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
395 | ||
396 | (the System V compiler puts out the second `xchg' instruction, | |
397 | and the assembler doesn't try to optimize it, so the 'sib' form | |
398 | gets generated). This sequence is used to get the address of the | |
399 | return buffer for a function that returns a structure. */ | |
400 | static unsigned char proto1[3] = { 0x87, 0x04, 0x24 }; | |
401 | static unsigned char proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
402 | unsigned char buf[4]; | |
c906108c SS |
403 | unsigned char op; |
404 | ||
acd5c798 MK |
405 | if (current_pc <= pc) |
406 | return pc; | |
407 | ||
408 | op = read_memory_unsigned_integer (pc, 1); | |
c906108c | 409 | |
acd5c798 MK |
410 | if (op != 0x58) /* popl %eax */ |
411 | return pc; | |
c906108c | 412 | |
acd5c798 MK |
413 | read_memory (pc + 1, buf, 4); |
414 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) | |
415 | return pc; | |
c906108c | 416 | |
acd5c798 | 417 | if (current_pc == pc) |
c906108c | 418 | { |
acd5c798 MK |
419 | cache->sp_offset += 4; |
420 | return current_pc; | |
c906108c SS |
421 | } |
422 | ||
acd5c798 | 423 | if (current_pc == pc + 1) |
c906108c | 424 | { |
acd5c798 MK |
425 | cache->pc_in_eax = 1; |
426 | return current_pc; | |
427 | } | |
428 | ||
429 | if (buf[1] == proto1[1]) | |
430 | return pc + 4; | |
431 | else | |
432 | return pc + 5; | |
433 | } | |
434 | ||
435 | static CORE_ADDR | |
436 | i386_skip_probe (CORE_ADDR pc) | |
437 | { | |
438 | /* A function may start with | |
fc338970 | 439 | |
acd5c798 MK |
440 | pushl constant |
441 | call _probe | |
442 | addl $4, %esp | |
fc338970 | 443 | |
acd5c798 MK |
444 | followed by |
445 | ||
446 | pushl %ebp | |
fc338970 | 447 | |
acd5c798 MK |
448 | etc. */ |
449 | unsigned char buf[8]; | |
450 | unsigned char op; | |
fc338970 | 451 | |
acd5c798 MK |
452 | op = read_memory_unsigned_integer (pc, 1); |
453 | ||
454 | if (op == 0x68 || op == 0x6a) | |
455 | { | |
456 | int delta; | |
c906108c | 457 | |
acd5c798 MK |
458 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
459 | four-byte operand, depending on the opcode. */ | |
c906108c | 460 | if (op == 0x68) |
acd5c798 | 461 | delta = 5; |
c906108c | 462 | else |
acd5c798 | 463 | delta = 2; |
c906108c | 464 | |
acd5c798 MK |
465 | /* Read the following 8 bytes, which should be `call _probe' (6 |
466 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
467 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 468 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 469 | pc += delta + sizeof (buf); |
c906108c SS |
470 | } |
471 | ||
acd5c798 MK |
472 | return pc; |
473 | } | |
474 | ||
37bdc87e MK |
475 | /* Maximum instruction length we need to handle. */ |
476 | #define I386_MAX_INSN_LEN 6 | |
477 | ||
478 | /* Instruction description. */ | |
479 | struct i386_insn | |
480 | { | |
481 | size_t len; | |
482 | unsigned char insn[I386_MAX_INSN_LEN]; | |
483 | unsigned char mask[I386_MAX_INSN_LEN]; | |
484 | }; | |
485 | ||
486 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
487 | the first instruction description that matches. Otherwise, return | |
488 | NULL. */ | |
489 | ||
490 | static struct i386_insn * | |
491 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
492 | { | |
493 | struct i386_insn *insn; | |
494 | unsigned char op; | |
495 | ||
496 | op = read_memory_unsigned_integer (pc, 1); | |
497 | ||
498 | for (insn = skip_insns; insn->len > 0; insn++) | |
499 | { | |
500 | if ((op & insn->mask[0]) == insn->insn[0]) | |
501 | { | |
502 | unsigned char buf[I386_MAX_INSN_LEN - 1]; | |
503 | size_t i; | |
504 | ||
505 | gdb_assert (insn->len > 1); | |
506 | gdb_assert (insn->len <= I386_MAX_INSN_LEN); | |
507 | ||
508 | read_memory (pc + 1, buf, insn->len - 1); | |
509 | for (i = 1; i < insn->len; i++) | |
510 | { | |
511 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
512 | break; | |
513 | ||
514 | return insn; | |
515 | } | |
516 | } | |
517 | } | |
518 | ||
519 | return NULL; | |
520 | } | |
521 | ||
522 | /* Some special instructions that might be migrated by GCC into the | |
523 | part of the prologue that sets up the new stack frame. Because the | |
524 | stack frame hasn't been setup yet, no registers have been saved | |
525 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
526 | touched. */ | |
527 | ||
528 | struct i386_insn i386_frame_setup_skip_insns[] = | |
529 | { | |
530 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
531 | ||
532 | ??? Should we handle 16-bit operand-sizes here? */ | |
533 | ||
534 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
535 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
536 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
537 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
538 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
539 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
540 | { 5, { 0xb8 }, { 0xfe } }, | |
541 | /* `movl imm32, %edx' */ | |
542 | { 5, { 0xba }, { 0xff } }, | |
543 | ||
544 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
545 | encoding for `mov m32, %eax'. | |
546 | ||
547 | ??? Should we handle SIB adressing here? | |
548 | ??? Should we handle 16-bit operand-sizes here? */ | |
549 | ||
550 | /* `movl m32, %eax' */ | |
551 | { 5, { 0xa1 }, { 0xff } }, | |
552 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
553 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
554 | /* `movl m32, %edx' */ | |
555 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
556 | ||
557 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
558 | Because of the symmetry, there are actually two ways to encode | |
559 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
560 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
561 | ||
562 | /* `subl %eax, %eax' */ | |
563 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
564 | /* `subl %ecx, %ecx' */ | |
565 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
566 | /* `subl %edx, %edx' */ | |
567 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
568 | /* `xorl %eax, %eax' */ | |
569 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
570 | /* `xorl %ecx, %ecx' */ | |
571 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
572 | /* `xorl %edx, %edx' */ | |
573 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
574 | { 0 } | |
575 | }; | |
576 | ||
acd5c798 MK |
577 | /* Check whether PC points at a code that sets up a new stack frame. |
578 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
579 | instruction after the sequence that sets up the frame or LIMIT, |
580 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
581 | |
582 | static CORE_ADDR | |
37bdc87e | 583 | i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit, |
acd5c798 MK |
584 | struct i386_frame_cache *cache) |
585 | { | |
37bdc87e | 586 | struct i386_insn *insn; |
acd5c798 | 587 | unsigned char op; |
26604a34 | 588 | int skip = 0; |
acd5c798 | 589 | |
37bdc87e MK |
590 | if (limit <= pc) |
591 | return limit; | |
acd5c798 MK |
592 | |
593 | op = read_memory_unsigned_integer (pc, 1); | |
594 | ||
c906108c | 595 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 596 | { |
acd5c798 MK |
597 | /* Take into account that we've executed the `pushl %ebp' that |
598 | starts this instruction sequence. */ | |
fd13a04a | 599 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 600 | cache->sp_offset += 4; |
37bdc87e | 601 | pc++; |
acd5c798 MK |
602 | |
603 | /* If that's all, return now. */ | |
37bdc87e MK |
604 | if (limit <= pc) |
605 | return limit; | |
26604a34 | 606 | |
b4632131 | 607 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
608 | GCC into the prologue and skip them. At this point in the |
609 | prologue, code should only touch the scratch registers %eax, | |
610 | %ecx and %edx, so while the number of posibilities is sheer, | |
611 | it is limited. | |
5daa5b4e | 612 | |
26604a34 MK |
613 | Make sure we only skip these instructions if we later see the |
614 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 615 | while (pc + skip < limit) |
26604a34 | 616 | { |
37bdc87e MK |
617 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
618 | if (insn == NULL) | |
619 | break; | |
b4632131 | 620 | |
37bdc87e | 621 | skip += insn->len; |
26604a34 MK |
622 | } |
623 | ||
37bdc87e MK |
624 | /* If that's all, return now. */ |
625 | if (limit <= pc + skip) | |
626 | return limit; | |
627 | ||
628 | op = read_memory_unsigned_integer (pc + skip, 1); | |
629 | ||
26604a34 | 630 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 631 | switch (op) |
c906108c SS |
632 | { |
633 | case 0x8b: | |
37bdc87e MK |
634 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec) |
635 | return pc; | |
c906108c SS |
636 | break; |
637 | case 0x89: | |
37bdc87e MK |
638 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5) |
639 | return pc; | |
c906108c SS |
640 | break; |
641 | default: | |
37bdc87e | 642 | return pc; |
c906108c | 643 | } |
acd5c798 | 644 | |
26604a34 MK |
645 | /* OK, we actually have a frame. We just don't know how large |
646 | it is yet. Set its size to zero. We'll adjust it if | |
647 | necessary. We also now commit to skipping the special | |
648 | instructions mentioned before. */ | |
acd5c798 | 649 | cache->locals = 0; |
37bdc87e | 650 | pc += (skip + 2); |
acd5c798 MK |
651 | |
652 | /* If that's all, return now. */ | |
37bdc87e MK |
653 | if (limit <= pc) |
654 | return limit; | |
acd5c798 | 655 | |
fc338970 MK |
656 | /* Check for stack adjustment |
657 | ||
acd5c798 | 658 | subl $XXX, %esp |
fc338970 | 659 | |
fd35795f | 660 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 661 | reg, so we don't have to worry about a data16 prefix. */ |
37bdc87e | 662 | op = read_memory_unsigned_integer (pc, 1); |
c906108c SS |
663 | if (op == 0x83) |
664 | { | |
fd35795f | 665 | /* `subl' with 8-bit immediate. */ |
37bdc87e | 666 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 667 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 668 | return pc; |
acd5c798 | 669 | |
37bdc87e MK |
670 | /* `subl' with signed 8-bit immediate (though it wouldn't |
671 | make sense to be negative). */ | |
672 | cache->locals = read_memory_integer (pc + 2, 1); | |
673 | return pc + 3; | |
c906108c SS |
674 | } |
675 | else if (op == 0x81) | |
676 | { | |
fd35795f | 677 | /* Maybe it is `subl' with a 32-bit immediate. */ |
37bdc87e | 678 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 679 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 680 | return pc; |
acd5c798 | 681 | |
fd35795f | 682 | /* It is `subl' with a 32-bit immediate. */ |
37bdc87e MK |
683 | cache->locals = read_memory_integer (pc + 2, 4); |
684 | return pc + 6; | |
c906108c SS |
685 | } |
686 | else | |
687 | { | |
acd5c798 | 688 | /* Some instruction other than `subl'. */ |
37bdc87e | 689 | return pc; |
c906108c SS |
690 | } |
691 | } | |
37bdc87e | 692 | else if (op == 0xc8) /* enter */ |
c906108c | 693 | { |
acd5c798 MK |
694 | cache->locals = read_memory_unsigned_integer (pc + 1, 2); |
695 | return pc + 4; | |
c906108c | 696 | } |
21d0e8a4 | 697 | |
acd5c798 | 698 | return pc; |
21d0e8a4 MK |
699 | } |
700 | ||
acd5c798 MK |
701 | /* Check whether PC points at code that saves registers on the stack. |
702 | If so, it updates CACHE and returns the address of the first | |
703 | instruction after the register saves or CURRENT_PC, whichever is | |
704 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
705 | |
706 | static CORE_ADDR | |
acd5c798 MK |
707 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
708 | struct i386_frame_cache *cache) | |
6bff26de | 709 | { |
99ab4326 MK |
710 | CORE_ADDR offset = 0; |
711 | unsigned char op; | |
712 | int i; | |
c0d1d883 | 713 | |
99ab4326 MK |
714 | if (cache->locals > 0) |
715 | offset -= cache->locals; | |
716 | for (i = 0; i < 8 && pc < current_pc; i++) | |
717 | { | |
718 | op = read_memory_unsigned_integer (pc, 1); | |
719 | if (op < 0x50 || op > 0x57) | |
720 | break; | |
0d17c81d | 721 | |
99ab4326 MK |
722 | offset -= 4; |
723 | cache->saved_regs[op - 0x50] = offset; | |
724 | cache->sp_offset += 4; | |
725 | pc++; | |
6bff26de MK |
726 | } |
727 | ||
acd5c798 | 728 | return pc; |
22797942 AC |
729 | } |
730 | ||
acd5c798 MK |
731 | /* Do a full analysis of the prologue at PC and update CACHE |
732 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
733 | address where the analysis stopped. | |
ed84f6c1 | 734 | |
fc338970 MK |
735 | We handle these cases: |
736 | ||
737 | The startup sequence can be at the start of the function, or the | |
738 | function can start with a branch to startup code at the end. | |
739 | ||
740 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
741 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
742 | once used in the System V compiler). | |
743 | ||
744 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
745 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
746 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
747 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
748 | |
749 | Next, the registers used by this function are pushed. With the | |
750 | System V compiler they will always be in the order: %edi, %esi, | |
751 | %ebx (and sometimes a harmless bug causes it to also save but not | |
752 | restore %eax); however, the code below is willing to see the pushes | |
753 | in any order, and will handle up to 8 of them. | |
754 | ||
755 | If the setup sequence is at the end of the function, then the next | |
756 | instruction will be a branch back to the start. */ | |
c906108c | 757 | |
acd5c798 MK |
758 | static CORE_ADDR |
759 | i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
760 | struct i386_frame_cache *cache) | |
c906108c | 761 | { |
acd5c798 MK |
762 | pc = i386_follow_jump (pc); |
763 | pc = i386_analyze_struct_return (pc, current_pc, cache); | |
764 | pc = i386_skip_probe (pc); | |
765 | pc = i386_analyze_frame_setup (pc, current_pc, cache); | |
766 | return i386_analyze_register_saves (pc, current_pc, cache); | |
c906108c SS |
767 | } |
768 | ||
fc338970 | 769 | /* Return PC of first real instruction. */ |
c906108c | 770 | |
3a1e71e3 | 771 | static CORE_ADDR |
acd5c798 | 772 | i386_skip_prologue (CORE_ADDR start_pc) |
c906108c | 773 | { |
c5aa993b | 774 | static unsigned char pic_pat[6] = |
acd5c798 MK |
775 | { |
776 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
777 | 0x5b, /* popl %ebx */ | |
c5aa993b | 778 | }; |
acd5c798 MK |
779 | struct i386_frame_cache cache; |
780 | CORE_ADDR pc; | |
781 | unsigned char op; | |
782 | int i; | |
c5aa993b | 783 | |
acd5c798 MK |
784 | cache.locals = -1; |
785 | pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache); | |
786 | if (cache.locals < 0) | |
787 | return start_pc; | |
c5aa993b | 788 | |
acd5c798 | 789 | /* Found valid frame setup. */ |
c906108c | 790 | |
fc338970 MK |
791 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
792 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
793 | %ebx: |
794 | ||
fc338970 MK |
795 | call 0x0 |
796 | popl %ebx | |
797 | movl %ebx,x(%ebp) (optional) | |
798 | addl y,%ebx | |
799 | ||
c906108c SS |
800 | This code is with the rest of the prologue (at the end of the |
801 | function), so we have to skip it to get to the first real | |
802 | instruction at the start of the function. */ | |
c5aa993b | 803 | |
c906108c SS |
804 | for (i = 0; i < 6; i++) |
805 | { | |
acd5c798 | 806 | op = read_memory_unsigned_integer (pc + i, 1); |
c5aa993b | 807 | if (pic_pat[i] != op) |
c906108c SS |
808 | break; |
809 | } | |
810 | if (i == 6) | |
811 | { | |
acd5c798 MK |
812 | int delta = 6; |
813 | ||
814 | op = read_memory_unsigned_integer (pc + delta, 1); | |
c906108c | 815 | |
c5aa993b | 816 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 817 | { |
acd5c798 MK |
818 | op = read_memory_unsigned_integer (pc + delta + 1, 1); |
819 | ||
fc338970 | 820 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 821 | delta += 3; |
fc338970 | 822 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 823 | delta += 6; |
fc338970 | 824 | else /* Unexpected instruction. */ |
acd5c798 MK |
825 | delta = 0; |
826 | ||
827 | op = read_memory_unsigned_integer (pc + delta, 1); | |
c906108c | 828 | } |
acd5c798 | 829 | |
c5aa993b | 830 | /* addl y,%ebx */ |
acd5c798 MK |
831 | if (delta > 0 && op == 0x81 |
832 | && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3); | |
c906108c | 833 | { |
acd5c798 | 834 | pc += delta + 6; |
c906108c SS |
835 | } |
836 | } | |
c5aa993b | 837 | |
e63bbc88 MK |
838 | /* If the function starts with a branch (to startup code at the end) |
839 | the last instruction should bring us back to the first | |
840 | instruction of the real code. */ | |
841 | if (i386_follow_jump (start_pc) != start_pc) | |
842 | pc = i386_follow_jump (pc); | |
843 | ||
844 | return pc; | |
c906108c SS |
845 | } |
846 | ||
acd5c798 | 847 | /* This function is 64-bit safe. */ |
93924b6b | 848 | |
acd5c798 MK |
849 | static CORE_ADDR |
850 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 851 | { |
acd5c798 MK |
852 | char buf[8]; |
853 | ||
854 | frame_unwind_register (next_frame, PC_REGNUM, buf); | |
855 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
93924b6b | 856 | } |
acd5c798 | 857 | \f |
93924b6b | 858 | |
acd5c798 | 859 | /* Normal frames. */ |
c5aa993b | 860 | |
acd5c798 MK |
861 | static struct i386_frame_cache * |
862 | i386_frame_cache (struct frame_info *next_frame, void **this_cache) | |
a7769679 | 863 | { |
acd5c798 | 864 | struct i386_frame_cache *cache; |
c0d1d883 | 865 | char buf[4]; |
acd5c798 MK |
866 | int i; |
867 | ||
868 | if (*this_cache) | |
869 | return *this_cache; | |
870 | ||
fd13a04a | 871 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
872 | *this_cache = cache; |
873 | ||
874 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
875 | which holds the base address for the current stack frame. | |
876 | However, for functions that don't need it, the frame pointer is | |
877 | optional. For these "frameless" functions the frame pointer is | |
878 | actually the frame pointer of the calling frame. Signal | |
879 | trampolines are just a special case of a "frameless" function. | |
880 | They (usually) share their frame pointer with the frame that was | |
881 | in progress when the signal occurred. */ | |
882 | ||
883 | frame_unwind_register (next_frame, I386_EBP_REGNUM, buf); | |
884 | cache->base = extract_unsigned_integer (buf, 4); | |
885 | if (cache->base == 0) | |
886 | return cache; | |
887 | ||
888 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 889 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 MK |
890 | |
891 | cache->pc = frame_func_unwind (next_frame); | |
892 | if (cache->pc != 0) | |
893 | i386_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); | |
894 | ||
895 | if (cache->locals < 0) | |
896 | { | |
897 | /* We didn't find a valid frame, which means that CACHE->base | |
898 | currently holds the frame pointer for our calling frame. If | |
899 | we're at the start of a function, or somewhere half-way its | |
900 | prologue, the function's frame probably hasn't been fully | |
901 | setup yet. Try to reconstruct the base address for the stack | |
902 | frame by looking at the stack pointer. For truly "frameless" | |
903 | functions this might work too. */ | |
904 | ||
905 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); | |
906 | cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset; | |
907 | } | |
908 | ||
909 | /* Now that we have the base address for the stack frame we can | |
910 | calculate the value of %esp in the calling frame. */ | |
911 | cache->saved_sp = cache->base + 8; | |
a7769679 | 912 | |
acd5c798 MK |
913 | /* Adjust all the saved registers such that they contain addresses |
914 | instead of offsets. */ | |
915 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
916 | if (cache->saved_regs[i] != -1) |
917 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
918 | |
919 | return cache; | |
a7769679 MK |
920 | } |
921 | ||
3a1e71e3 | 922 | static void |
acd5c798 MK |
923 | i386_frame_this_id (struct frame_info *next_frame, void **this_cache, |
924 | struct frame_id *this_id) | |
c906108c | 925 | { |
acd5c798 MK |
926 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); |
927 | ||
928 | /* This marks the outermost frame. */ | |
929 | if (cache->base == 0) | |
930 | return; | |
931 | ||
3e210248 | 932 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
933 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
934 | } | |
935 | ||
936 | static void | |
937 | i386_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
938 | int regnum, int *optimizedp, | |
939 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
940 | int *realnump, void *valuep) | |
941 | { | |
942 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); | |
943 | ||
944 | gdb_assert (regnum >= 0); | |
945 | ||
946 | /* The System V ABI says that: | |
947 | ||
948 | "The flags register contains the system flags, such as the | |
949 | direction flag and the carry flag. The direction flag must be | |
950 | set to the forward (that is, zero) direction before entry and | |
951 | upon exit from a function. Other user flags have no specified | |
952 | role in the standard calling sequence and are not preserved." | |
953 | ||
954 | To guarantee the "upon exit" part of that statement we fake a | |
955 | saved flags register that has its direction flag cleared. | |
956 | ||
957 | Note that GCC doesn't seem to rely on the fact that the direction | |
958 | flag is cleared after a function return; it always explicitly | |
959 | clears the flag before operations where it matters. | |
960 | ||
961 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
962 | right thing to do. The way we fake the flags register here makes | |
963 | it impossible to change it. */ | |
964 | ||
965 | if (regnum == I386_EFLAGS_REGNUM) | |
966 | { | |
967 | *optimizedp = 0; | |
968 | *lvalp = not_lval; | |
969 | *addrp = 0; | |
970 | *realnump = -1; | |
971 | if (valuep) | |
972 | { | |
973 | ULONGEST val; | |
c5aa993b | 974 | |
acd5c798 | 975 | /* Clear the direction flag. */ |
f837910f MK |
976 | val = frame_unwind_register_unsigned (next_frame, |
977 | I386_EFLAGS_REGNUM); | |
acd5c798 MK |
978 | val &= ~(1 << 10); |
979 | store_unsigned_integer (valuep, 4, val); | |
980 | } | |
981 | ||
982 | return; | |
983 | } | |
1211c4e4 | 984 | |
acd5c798 | 985 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
c906108c | 986 | { |
00b25ff3 AC |
987 | *optimizedp = 0; |
988 | *lvalp = lval_register; | |
989 | *addrp = 0; | |
990 | *realnump = I386_EAX_REGNUM; | |
991 | if (valuep) | |
992 | frame_unwind_register (next_frame, (*realnump), valuep); | |
acd5c798 MK |
993 | return; |
994 | } | |
995 | ||
996 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
997 | { | |
998 | *optimizedp = 0; | |
999 | *lvalp = not_lval; | |
1000 | *addrp = 0; | |
1001 | *realnump = -1; | |
1002 | if (valuep) | |
c906108c | 1003 | { |
acd5c798 MK |
1004 | /* Store the value. */ |
1005 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
c906108c | 1006 | } |
acd5c798 | 1007 | return; |
c906108c | 1008 | } |
acd5c798 | 1009 | |
fd13a04a AC |
1010 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
1011 | { | |
1012 | *optimizedp = 0; | |
1013 | *lvalp = lval_memory; | |
1014 | *addrp = cache->saved_regs[regnum]; | |
1015 | *realnump = -1; | |
1016 | if (valuep) | |
1017 | { | |
1018 | /* Read the value in from memory. */ | |
1019 | read_memory (*addrp, valuep, | |
1020 | register_size (current_gdbarch, regnum)); | |
1021 | } | |
1022 | return; | |
1023 | } | |
1024 | ||
00b25ff3 AC |
1025 | *optimizedp = 0; |
1026 | *lvalp = lval_register; | |
1027 | *addrp = 0; | |
1028 | *realnump = regnum; | |
1029 | if (valuep) | |
1030 | frame_unwind_register (next_frame, (*realnump), valuep); | |
acd5c798 MK |
1031 | } |
1032 | ||
1033 | static const struct frame_unwind i386_frame_unwind = | |
1034 | { | |
1035 | NORMAL_FRAME, | |
1036 | i386_frame_this_id, | |
1037 | i386_frame_prev_register | |
1038 | }; | |
1039 | ||
1040 | static const struct frame_unwind * | |
336d1bba | 1041 | i386_frame_sniffer (struct frame_info *next_frame) |
acd5c798 MK |
1042 | { |
1043 | return &i386_frame_unwind; | |
1044 | } | |
1045 | \f | |
1046 | ||
1047 | /* Signal trampolines. */ | |
1048 | ||
1049 | static struct i386_frame_cache * | |
1050 | i386_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1051 | { | |
1052 | struct i386_frame_cache *cache; | |
1053 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1054 | CORE_ADDR addr; | |
1055 | char buf[4]; | |
1056 | ||
1057 | if (*this_cache) | |
1058 | return *this_cache; | |
1059 | ||
fd13a04a | 1060 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1061 | |
1062 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); | |
1063 | cache->base = extract_unsigned_integer (buf, 4) - 4; | |
1064 | ||
1065 | addr = tdep->sigcontext_addr (next_frame); | |
a3386186 MK |
1066 | if (tdep->sc_reg_offset) |
1067 | { | |
1068 | int i; | |
1069 | ||
1070 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1071 | ||
1072 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1073 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1074 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1075 | } |
1076 | else | |
1077 | { | |
fd13a04a AC |
1078 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1079 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1080 | } |
acd5c798 MK |
1081 | |
1082 | *this_cache = cache; | |
1083 | return cache; | |
1084 | } | |
1085 | ||
1086 | static void | |
1087 | i386_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1088 | struct frame_id *this_id) | |
1089 | { | |
1090 | struct i386_frame_cache *cache = | |
1091 | i386_sigtramp_frame_cache (next_frame, this_cache); | |
1092 | ||
3e210248 | 1093 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1094 | (*this_id) = frame_id_build (cache->base + 8, frame_pc_unwind (next_frame)); |
1095 | } | |
1096 | ||
1097 | static void | |
1098 | i386_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
1099 | void **this_cache, | |
1100 | int regnum, int *optimizedp, | |
1101 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1102 | int *realnump, void *valuep) | |
1103 | { | |
1104 | /* Make sure we've initialized the cache. */ | |
1105 | i386_sigtramp_frame_cache (next_frame, this_cache); | |
1106 | ||
1107 | i386_frame_prev_register (next_frame, this_cache, regnum, | |
1108 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c | 1109 | } |
c0d1d883 | 1110 | |
acd5c798 MK |
1111 | static const struct frame_unwind i386_sigtramp_frame_unwind = |
1112 | { | |
1113 | SIGTRAMP_FRAME, | |
1114 | i386_sigtramp_frame_this_id, | |
1115 | i386_sigtramp_frame_prev_register | |
1116 | }; | |
1117 | ||
1118 | static const struct frame_unwind * | |
336d1bba | 1119 | i386_sigtramp_frame_sniffer (struct frame_info *next_frame) |
acd5c798 | 1120 | { |
911bc6ee | 1121 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame)); |
acd5c798 | 1122 | |
911bc6ee MK |
1123 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1124 | handler. */ | |
1125 | if (tdep->sigcontext_addr == NULL) | |
1c3545ae MK |
1126 | return NULL; |
1127 | ||
911bc6ee MK |
1128 | if (tdep->sigtramp_p != NULL) |
1129 | { | |
1130 | if (tdep->sigtramp_p (next_frame)) | |
1131 | return &i386_sigtramp_frame_unwind; | |
1132 | } | |
1133 | ||
1134 | if (tdep->sigtramp_start != 0) | |
1135 | { | |
1136 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1137 | ||
1138 | gdb_assert (tdep->sigtramp_end != 0); | |
1139 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
1140 | return &i386_sigtramp_frame_unwind; | |
1141 | } | |
acd5c798 MK |
1142 | |
1143 | return NULL; | |
1144 | } | |
1145 | \f | |
1146 | ||
1147 | static CORE_ADDR | |
1148 | i386_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1149 | { | |
1150 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); | |
1151 | ||
1152 | return cache->base; | |
1153 | } | |
1154 | ||
1155 | static const struct frame_base i386_frame_base = | |
1156 | { | |
1157 | &i386_frame_unwind, | |
1158 | i386_frame_base_address, | |
1159 | i386_frame_base_address, | |
1160 | i386_frame_base_address | |
1161 | }; | |
1162 | ||
acd5c798 MK |
1163 | static struct frame_id |
1164 | i386_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1165 | { | |
1166 | char buf[4]; | |
1167 | CORE_ADDR fp; | |
1168 | ||
1169 | frame_unwind_register (next_frame, I386_EBP_REGNUM, buf); | |
1170 | fp = extract_unsigned_integer (buf, 4); | |
1171 | ||
3e210248 | 1172 | /* See the end of i386_push_dummy_call. */ |
acd5c798 | 1173 | return frame_id_build (fp + 8, frame_pc_unwind (next_frame)); |
c0d1d883 | 1174 | } |
fc338970 | 1175 | \f |
c906108c | 1176 | |
fc338970 MK |
1177 | /* Figure out where the longjmp will land. Slurp the args out of the |
1178 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1179 | structure from which we extract the address that we will land at. |
28bcfd30 | 1180 | This address is copied into PC. This routine returns non-zero on |
acd5c798 MK |
1181 | success. |
1182 | ||
1183 | This function is 64-bit safe. */ | |
c906108c | 1184 | |
8201327c MK |
1185 | static int |
1186 | i386_get_longjmp_target (CORE_ADDR *pc) | |
c906108c | 1187 | { |
28bcfd30 | 1188 | char buf[8]; |
c906108c | 1189 | CORE_ADDR sp, jb_addr; |
8201327c | 1190 | int jb_pc_offset = gdbarch_tdep (current_gdbarch)->jb_pc_offset; |
f9d3c2a8 | 1191 | int len = TYPE_LENGTH (builtin_type_void_func_ptr); |
c906108c | 1192 | |
8201327c MK |
1193 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1194 | longjmp will land. */ | |
1195 | if (jb_pc_offset == -1) | |
c906108c SS |
1196 | return 0; |
1197 | ||
f837910f MK |
1198 | /* Don't use I386_ESP_REGNUM here, since this function is also used |
1199 | for AMD64. */ | |
1200 | regcache_cooked_read (current_regcache, SP_REGNUM, buf); | |
1201 | sp = extract_typed_address (buf, builtin_type_void_data_ptr); | |
28bcfd30 | 1202 | if (target_read_memory (sp + len, buf, len)) |
c906108c SS |
1203 | return 0; |
1204 | ||
f837910f | 1205 | jb_addr = extract_typed_address (buf, builtin_type_void_data_ptr); |
28bcfd30 | 1206 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
8201327c | 1207 | return 0; |
c906108c | 1208 | |
f9d3c2a8 | 1209 | *pc = extract_typed_address (buf, builtin_type_void_func_ptr); |
c906108c SS |
1210 | return 1; |
1211 | } | |
fc338970 | 1212 | \f |
c906108c | 1213 | |
3a1e71e3 | 1214 | static CORE_ADDR |
7d9b040b | 1215 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1216 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1217 | struct value **args, CORE_ADDR sp, int struct_return, | |
1218 | CORE_ADDR struct_addr) | |
22f8ba57 | 1219 | { |
acd5c798 MK |
1220 | char buf[4]; |
1221 | int i; | |
1222 | ||
1223 | /* Push arguments in reverse order. */ | |
1224 | for (i = nargs - 1; i >= 0; i--) | |
22f8ba57 | 1225 | { |
4754a64e | 1226 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); |
acd5c798 MK |
1227 | |
1228 | /* The System V ABI says that: | |
1229 | ||
1230 | "An argument's size is increased, if necessary, to make it a | |
1231 | multiple of [32-bit] words. This may require tail padding, | |
1232 | depending on the size of the argument." | |
1233 | ||
1234 | This makes sure the stack says word-aligned. */ | |
1235 | sp -= (len + 3) & ~3; | |
46615f07 | 1236 | write_memory (sp, value_contents_all (args[i]), len); |
acd5c798 | 1237 | } |
22f8ba57 | 1238 | |
acd5c798 MK |
1239 | /* Push value address. */ |
1240 | if (struct_return) | |
1241 | { | |
22f8ba57 | 1242 | sp -= 4; |
fbd9dcd3 | 1243 | store_unsigned_integer (buf, 4, struct_addr); |
22f8ba57 MK |
1244 | write_memory (sp, buf, 4); |
1245 | } | |
1246 | ||
acd5c798 MK |
1247 | /* Store return address. */ |
1248 | sp -= 4; | |
6a65450a | 1249 | store_unsigned_integer (buf, 4, bp_addr); |
acd5c798 MK |
1250 | write_memory (sp, buf, 4); |
1251 | ||
1252 | /* Finally, update the stack pointer... */ | |
1253 | store_unsigned_integer (buf, 4, sp); | |
1254 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); | |
1255 | ||
1256 | /* ...and fake a frame pointer. */ | |
1257 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1258 | ||
3e210248 AC |
1259 | /* MarkK wrote: This "+ 8" is all over the place: |
1260 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
1261 | i386_unwind_dummy_id). It's there, since all frame unwinders for | |
1262 | a given target have to agree (within a certain margin) on the | |
fd35795f | 1263 | definition of the stack address of a frame. Otherwise |
3e210248 AC |
1264 | frame_id_inner() won't work correctly. Since DWARF2/GCC uses the |
1265 | stack address *before* the function call as a frame's CFA. On | |
1266 | the i386, when %ebp is used as a frame pointer, the offset | |
1267 | between the contents %ebp and the CFA as defined by GCC. */ | |
1268 | return sp + 8; | |
22f8ba57 MK |
1269 | } |
1270 | ||
1a309862 MK |
1271 | /* These registers are used for returning integers (and on some |
1272 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1273 | size and alignment match an integer type). */ |
acd5c798 MK |
1274 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1275 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1276 | |
c5e656c1 MK |
1277 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1278 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1279 | |
3a1e71e3 | 1280 | static void |
c5e656c1 MK |
1281 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
1282 | struct regcache *regcache, void *valbuf) | |
c906108c | 1283 | { |
c5e656c1 | 1284 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1285 | int len = TYPE_LENGTH (type); |
00f8375e | 1286 | char buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1287 | |
1e8d0a7b | 1288 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1289 | { |
5716833c | 1290 | if (tdep->st0_regnum < 0) |
1a309862 | 1291 | { |
8a3fe4f8 | 1292 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1293 | memset (valbuf, 0, len); |
ef9dff19 | 1294 | return; |
1a309862 MK |
1295 | } |
1296 | ||
c6ba6f0d MK |
1297 | /* Floating-point return values can be found in %st(0). Convert |
1298 | its contents to the desired type. This is probably not | |
1299 | exactly how it would happen on the target itself, but it is | |
1300 | the best we can do. */ | |
acd5c798 | 1301 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
00f8375e | 1302 | convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type); |
c906108c SS |
1303 | } |
1304 | else | |
c5aa993b | 1305 | { |
f837910f MK |
1306 | int low_size = register_size (current_gdbarch, LOW_RETURN_REGNUM); |
1307 | int high_size = register_size (current_gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1308 | |
1309 | if (len <= low_size) | |
00f8375e | 1310 | { |
0818c12a | 1311 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1312 | memcpy (valbuf, buf, len); |
1313 | } | |
d4f3574e SS |
1314 | else if (len <= (low_size + high_size)) |
1315 | { | |
0818c12a | 1316 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1317 | memcpy (valbuf, buf, low_size); |
0818c12a | 1318 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
c8048956 | 1319 | memcpy ((char *) valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1320 | } |
1321 | else | |
8e65ff28 | 1322 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1323 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1324 | } |
1325 | } | |
1326 | ||
c5e656c1 MK |
1327 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1328 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1329 | |
3a1e71e3 | 1330 | static void |
c5e656c1 MK |
1331 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
1332 | struct regcache *regcache, const void *valbuf) | |
ef9dff19 | 1333 | { |
c5e656c1 | 1334 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1335 | int len = TYPE_LENGTH (type); |
1336 | ||
5716833c MK |
1337 | /* Define I387_ST0_REGNUM such that we use the proper definitions |
1338 | for the architecture. */ | |
1339 | #define I387_ST0_REGNUM I386_ST0_REGNUM | |
1340 | ||
1e8d0a7b | 1341 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1342 | { |
3d7f4f49 | 1343 | ULONGEST fstat; |
5716833c | 1344 | char buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1345 | |
5716833c | 1346 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1347 | { |
8a3fe4f8 | 1348 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1349 | return; |
1350 | } | |
1351 | ||
635b0cc1 MK |
1352 | /* Returning floating-point values is a bit tricky. Apart from |
1353 | storing the return value in %st(0), we have to simulate the | |
1354 | state of the FPU at function return point. */ | |
1355 | ||
c6ba6f0d MK |
1356 | /* Convert the value found in VALBUF to the extended |
1357 | floating-point format used by the FPU. This is probably | |
1358 | not exactly how it would happen on the target itself, but | |
1359 | it is the best we can do. */ | |
1360 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
acd5c798 | 1361 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1362 | |
635b0cc1 MK |
1363 | /* Set the top of the floating-point register stack to 7. The |
1364 | actual value doesn't really matter, but 7 is what a normal | |
1365 | function return would end up with if the program started out | |
1366 | with a freshly initialized FPU. */ | |
5716833c | 1367 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM, &fstat); |
ccb945b8 | 1368 | fstat |= (7 << 11); |
5716833c | 1369 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM, fstat); |
ccb945b8 | 1370 | |
635b0cc1 MK |
1371 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1372 | the floating-point register stack to 7, the appropriate value | |
1373 | for the tag word is 0x3fff. */ | |
5716833c | 1374 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM, 0x3fff); |
ef9dff19 MK |
1375 | } |
1376 | else | |
1377 | { | |
f837910f MK |
1378 | int low_size = register_size (current_gdbarch, LOW_RETURN_REGNUM); |
1379 | int high_size = register_size (current_gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1380 | |
1381 | if (len <= low_size) | |
3d7f4f49 | 1382 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1383 | else if (len <= (low_size + high_size)) |
1384 | { | |
3d7f4f49 MK |
1385 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1386 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
1387 | len - low_size, (char *) valbuf + low_size); | |
ef9dff19 MK |
1388 | } |
1389 | else | |
8e65ff28 | 1390 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1391 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 | 1392 | } |
5716833c MK |
1393 | |
1394 | #undef I387_ST0_REGNUM | |
ef9dff19 | 1395 | } |
fc338970 | 1396 | \f |
ef9dff19 | 1397 | |
8201327c MK |
1398 | /* This is the variable that is set with "set struct-convention", and |
1399 | its legitimate values. */ | |
1400 | static const char default_struct_convention[] = "default"; | |
1401 | static const char pcc_struct_convention[] = "pcc"; | |
1402 | static const char reg_struct_convention[] = "reg"; | |
1403 | static const char *valid_conventions[] = | |
1404 | { | |
1405 | default_struct_convention, | |
1406 | pcc_struct_convention, | |
1407 | reg_struct_convention, | |
1408 | NULL | |
1409 | }; | |
1410 | static const char *struct_convention = default_struct_convention; | |
1411 | ||
c5e656c1 MK |
1412 | /* Return non-zero if TYPE, which is assumed to be a structure or |
1413 | union type, should be returned in registers for architecture | |
1414 | GDBARCH. */ | |
1415 | ||
8201327c | 1416 | static int |
c5e656c1 | 1417 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 1418 | { |
c5e656c1 MK |
1419 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1420 | enum type_code code = TYPE_CODE (type); | |
1421 | int len = TYPE_LENGTH (type); | |
8201327c | 1422 | |
c5e656c1 MK |
1423 | gdb_assert (code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION); |
1424 | ||
1425 | if (struct_convention == pcc_struct_convention | |
1426 | || (struct_convention == default_struct_convention | |
1427 | && tdep->struct_return == pcc_struct_return)) | |
1428 | return 0; | |
1429 | ||
1430 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
1431 | } | |
1432 | ||
1433 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
1434 | should be returned. If it is supposed to be returned in registers, | |
1435 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
1436 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
1437 | from WRITEBUF into REGCACHE. */ | |
1438 | ||
1439 | static enum return_value_convention | |
1440 | i386_return_value (struct gdbarch *gdbarch, struct type *type, | |
1441 | struct regcache *regcache, void *readbuf, | |
1442 | const void *writebuf) | |
1443 | { | |
1444 | enum type_code code = TYPE_CODE (type); | |
1445 | ||
1446 | if ((code == TYPE_CODE_STRUCT || code == TYPE_CODE_UNION) | |
1447 | && !i386_reg_struct_return_p (gdbarch, type)) | |
31db7b6c MK |
1448 | { |
1449 | /* The System V ABI says that: | |
1450 | ||
1451 | "A function that returns a structure or union also sets %eax | |
1452 | to the value of the original address of the caller's area | |
1453 | before it returns. Thus when the caller receives control | |
1454 | again, the address of the returned object resides in register | |
1455 | %eax and can be used to access the object." | |
1456 | ||
1457 | So the ABI guarantees that we can always find the return | |
1458 | value just after the function has returned. */ | |
1459 | ||
1460 | if (readbuf) | |
1461 | { | |
1462 | ULONGEST addr; | |
1463 | ||
1464 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
1465 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1466 | } | |
1467 | ||
1468 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
1469 | } | |
c5e656c1 MK |
1470 | |
1471 | /* This special case is for structures consisting of a single | |
1472 | `float' or `double' member. These structures are returned in | |
1473 | %st(0). For these structures, we call ourselves recursively, | |
1474 | changing TYPE into the type of the first member of the structure. | |
1475 | Since that should work for all structures that have only one | |
1476 | member, we don't bother to check the member's type here. */ | |
1477 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
1478 | { | |
1479 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1480 | return i386_return_value (gdbarch, type, regcache, readbuf, writebuf); | |
1481 | } | |
1482 | ||
1483 | if (readbuf) | |
1484 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
1485 | if (writebuf) | |
1486 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 1487 | |
c5e656c1 | 1488 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
1489 | } |
1490 | \f | |
1491 | ||
21b4b2f2 JB |
1492 | /* Types for the MMX and SSE registers. */ |
1493 | static struct type *i386_mmx_type; | |
1494 | static struct type *i386_sse_type; | |
1495 | ||
1496 | /* Construct the type for MMX registers. */ | |
1497 | static struct type * | |
1498 | i386_build_mmx_type (void) | |
1499 | { | |
1500 | /* The type we're building is this: */ | |
1501 | #if 0 | |
1502 | union __gdb_builtin_type_vec64i | |
1503 | { | |
1504 | int64_t uint64; | |
1505 | int32_t v2_int32[2]; | |
1506 | int16_t v4_int16[4]; | |
1507 | int8_t v8_int8[8]; | |
1508 | }; | |
1509 | #endif | |
1510 | ||
1511 | if (! i386_mmx_type) | |
1512 | { | |
1513 | struct type *t; | |
1514 | ||
1515 | t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
1516 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
1517 | append_composite_type_field (t, "v2_int32", builtin_type_v2_int32); | |
1518 | append_composite_type_field (t, "v4_int16", builtin_type_v4_int16); | |
1519 | append_composite_type_field (t, "v8_int8", builtin_type_v8_int8); | |
1520 | ||
1521 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
1522 | TYPE_NAME (t) = "builtin_type_vec64i"; | |
1523 | ||
1524 | i386_mmx_type = t; | |
1525 | } | |
1526 | ||
1527 | return i386_mmx_type; | |
1528 | } | |
1529 | ||
1530 | /* Construct the type for SSE registers. */ | |
1531 | static struct type * | |
1532 | i386_build_sse_type (void) | |
1533 | { | |
1534 | if (! i386_sse_type) | |
1535 | { | |
1536 | struct type *t; | |
1537 | ||
1538 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
1539 | append_composite_type_field (t, "v4_float", builtin_type_v4_float); | |
1540 | append_composite_type_field (t, "v2_double", builtin_type_v2_double); | |
1541 | append_composite_type_field (t, "v16_int8", builtin_type_v16_int8); | |
1542 | append_composite_type_field (t, "v8_int16", builtin_type_v8_int16); | |
1543 | append_composite_type_field (t, "v4_int32", builtin_type_v4_int32); | |
1544 | append_composite_type_field (t, "v2_int64", builtin_type_v2_int64); | |
1545 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
1546 | ||
1547 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
1548 | TYPE_NAME (t) = "builtin_type_vec128i"; | |
1549 | ||
1550 | i386_sse_type = t; | |
1551 | } | |
1552 | ||
1553 | return i386_sse_type; | |
1554 | } | |
1555 | ||
d7a0d72c MK |
1556 | /* Return the GDB type object for the "standard" data type of data in |
1557 | register REGNUM. Perhaps %esi and %edi should go here, but | |
1558 | potentially they could be used for things other than address. */ | |
1559 | ||
3a1e71e3 | 1560 | static struct type * |
4e259f09 | 1561 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 1562 | { |
acd5c798 MK |
1563 | if (regnum == I386_EIP_REGNUM |
1564 | || regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) | |
d7a0d72c MK |
1565 | return lookup_pointer_type (builtin_type_void); |
1566 | ||
23a34459 | 1567 | if (i386_fp_regnum_p (regnum)) |
c6ba6f0d | 1568 | return builtin_type_i387_ext; |
d7a0d72c | 1569 | |
5716833c | 1570 | if (i386_sse_regnum_p (gdbarch, regnum)) |
21b4b2f2 | 1571 | return i386_build_sse_type (); |
d7a0d72c | 1572 | |
5716833c | 1573 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
21b4b2f2 | 1574 | return i386_build_mmx_type (); |
28fc6740 | 1575 | |
d7a0d72c MK |
1576 | return builtin_type_int; |
1577 | } | |
1578 | ||
28fc6740 | 1579 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 1580 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
1581 | |
1582 | static int | |
c86c27af | 1583 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 1584 | { |
5716833c MK |
1585 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
1586 | int mmxreg, fpreg; | |
28fc6740 AC |
1587 | ULONGEST fstat; |
1588 | int tos; | |
c86c27af | 1589 | |
5716833c MK |
1590 | /* Define I387_ST0_REGNUM such that we use the proper definitions |
1591 | for REGCACHE's architecture. */ | |
1592 | #define I387_ST0_REGNUM tdep->st0_regnum | |
1593 | ||
1594 | mmxreg = regnum - tdep->mm0_regnum; | |
1595 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM, &fstat); | |
28fc6740 | 1596 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
1597 | fpreg = (mmxreg + tos) % 8; |
1598 | ||
1599 | return (I387_ST0_REGNUM + fpreg); | |
c86c27af | 1600 | |
5716833c | 1601 | #undef I387_ST0_REGNUM |
28fc6740 AC |
1602 | } |
1603 | ||
1604 | static void | |
1605 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1606 | int regnum, void *buf) | |
1607 | { | |
5716833c | 1608 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 1609 | { |
d9d9c31f | 1610 | char mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
1611 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
1612 | ||
28fc6740 | 1613 | /* Extract (always little endian). */ |
c86c27af | 1614 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 1615 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
1616 | } |
1617 | else | |
1618 | regcache_raw_read (regcache, regnum, buf); | |
1619 | } | |
1620 | ||
1621 | static void | |
1622 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1623 | int regnum, const void *buf) | |
1624 | { | |
5716833c | 1625 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 1626 | { |
d9d9c31f | 1627 | char mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
1628 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
1629 | ||
28fc6740 AC |
1630 | /* Read ... */ |
1631 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
1632 | /* ... Modify ... (always little endian). */ | |
f837910f | 1633 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
1634 | /* ... Write. */ |
1635 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
1636 | } | |
1637 | else | |
1638 | regcache_raw_write (regcache, regnum, buf); | |
1639 | } | |
ff2e87ac AC |
1640 | \f |
1641 | ||
ff2e87ac AC |
1642 | /* Return the register number of the register allocated by GCC after |
1643 | REGNUM, or -1 if there is no such register. */ | |
1644 | ||
1645 | static int | |
1646 | i386_next_regnum (int regnum) | |
1647 | { | |
1648 | /* GCC allocates the registers in the order: | |
1649 | ||
1650 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
1651 | ||
1652 | Since storing a variable in %esp doesn't make any sense we return | |
1653 | -1 for %ebp and for %esp itself. */ | |
1654 | static int next_regnum[] = | |
1655 | { | |
1656 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
1657 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
1658 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
1659 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
1660 | -1, -1, /* Slots for %esp and %ebp. */ | |
1661 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
1662 | I386_EBP_REGNUM /* Slot for %edi. */ | |
1663 | }; | |
1664 | ||
de5b9bb9 | 1665 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 1666 | return next_regnum[regnum]; |
28fc6740 | 1667 | |
ff2e87ac AC |
1668 | return -1; |
1669 | } | |
1670 | ||
1671 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
1672 | needs any special handling. */ | |
d7a0d72c | 1673 | |
3a1e71e3 | 1674 | static int |
ff2e87ac | 1675 | i386_convert_register_p (int regnum, struct type *type) |
d7a0d72c | 1676 | { |
de5b9bb9 MK |
1677 | int len = TYPE_LENGTH (type); |
1678 | ||
ff2e87ac AC |
1679 | /* Values may be spread across multiple registers. Most debugging |
1680 | formats aren't expressive enough to specify the locations, so | |
1681 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
1682 | have a length that is a multiple of the word size, since GCC |
1683 | doesn't seem to put any other types into registers. */ | |
1684 | if (len > 4 && len % 4 == 0) | |
1685 | { | |
1686 | int last_regnum = regnum; | |
1687 | ||
1688 | while (len > 4) | |
1689 | { | |
1690 | last_regnum = i386_next_regnum (last_regnum); | |
1691 | len -= 4; | |
1692 | } | |
1693 | ||
1694 | if (last_regnum != -1) | |
1695 | return 1; | |
1696 | } | |
ff2e87ac | 1697 | |
23a34459 | 1698 | return i386_fp_regnum_p (regnum); |
d7a0d72c MK |
1699 | } |
1700 | ||
ff2e87ac AC |
1701 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
1702 | return its contents in TO. */ | |
ac27f131 | 1703 | |
3a1e71e3 | 1704 | static void |
ff2e87ac AC |
1705 | i386_register_to_value (struct frame_info *frame, int regnum, |
1706 | struct type *type, void *to) | |
ac27f131 | 1707 | { |
de5b9bb9 MK |
1708 | int len = TYPE_LENGTH (type); |
1709 | char *buf = to; | |
1710 | ||
ff2e87ac AC |
1711 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
1712 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 1713 | |
ff2e87ac | 1714 | if (i386_fp_regnum_p (regnum)) |
8d7f6b4a | 1715 | { |
d532c08f MK |
1716 | i387_register_to_value (frame, regnum, type, to); |
1717 | return; | |
8d7f6b4a | 1718 | } |
ff2e87ac | 1719 | |
fd35795f | 1720 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
1721 | |
1722 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 1723 | |
de5b9bb9 MK |
1724 | while (len > 0) |
1725 | { | |
1726 | gdb_assert (regnum != -1); | |
1727 | gdb_assert (register_size (current_gdbarch, regnum) == 4); | |
d532c08f | 1728 | |
f837910f | 1729 | get_frame_register (frame, regnum, buf); |
de5b9bb9 MK |
1730 | regnum = i386_next_regnum (regnum); |
1731 | len -= 4; | |
1732 | buf += 4; | |
1733 | } | |
ac27f131 MK |
1734 | } |
1735 | ||
ff2e87ac AC |
1736 | /* Write the contents FROM of a value of type TYPE into register |
1737 | REGNUM in frame FRAME. */ | |
ac27f131 | 1738 | |
3a1e71e3 | 1739 | static void |
ff2e87ac AC |
1740 | i386_value_to_register (struct frame_info *frame, int regnum, |
1741 | struct type *type, const void *from) | |
ac27f131 | 1742 | { |
de5b9bb9 MK |
1743 | int len = TYPE_LENGTH (type); |
1744 | const char *buf = from; | |
1745 | ||
ff2e87ac | 1746 | if (i386_fp_regnum_p (regnum)) |
c6ba6f0d | 1747 | { |
d532c08f MK |
1748 | i387_value_to_register (frame, regnum, type, from); |
1749 | return; | |
1750 | } | |
3d261580 | 1751 | |
fd35795f | 1752 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
1753 | |
1754 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 1755 | |
de5b9bb9 MK |
1756 | while (len > 0) |
1757 | { | |
1758 | gdb_assert (regnum != -1); | |
1759 | gdb_assert (register_size (current_gdbarch, regnum) == 4); | |
d532c08f | 1760 | |
de5b9bb9 MK |
1761 | put_frame_register (frame, regnum, buf); |
1762 | regnum = i386_next_regnum (regnum); | |
1763 | len -= 4; | |
1764 | buf += 4; | |
1765 | } | |
ac27f131 | 1766 | } |
ff2e87ac | 1767 | \f |
7fdafb5a MK |
1768 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
1769 | in the general-purpose register set REGSET to register cache | |
1770 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 1771 | |
20187ed5 | 1772 | void |
473f17b0 MK |
1773 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
1774 | int regnum, const void *gregs, size_t len) | |
1775 | { | |
9ea75c57 | 1776 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 MK |
1777 | const char *regs = gregs; |
1778 | int i; | |
1779 | ||
1780 | gdb_assert (len == tdep->sizeof_gregset); | |
1781 | ||
1782 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
1783 | { | |
1784 | if ((regnum == i || regnum == -1) | |
1785 | && tdep->gregset_reg_offset[i] != -1) | |
1786 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
1787 | } | |
1788 | } | |
1789 | ||
7fdafb5a MK |
1790 | /* Collect register REGNUM from the register cache REGCACHE and store |
1791 | it in the buffer specified by GREGS and LEN as described by the | |
1792 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
1793 | all registers in REGSET. */ | |
1794 | ||
1795 | void | |
1796 | i386_collect_gregset (const struct regset *regset, | |
1797 | const struct regcache *regcache, | |
1798 | int regnum, void *gregs, size_t len) | |
1799 | { | |
1800 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1801 | char *regs = gregs; | |
1802 | int i; | |
1803 | ||
1804 | gdb_assert (len == tdep->sizeof_gregset); | |
1805 | ||
1806 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
1807 | { | |
1808 | if ((regnum == i || regnum == -1) | |
1809 | && tdep->gregset_reg_offset[i] != -1) | |
1810 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
1815 | in the floating-point register set REGSET to register cache | |
1816 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
1817 | |
1818 | static void | |
1819 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
1820 | int regnum, const void *fpregs, size_t len) | |
1821 | { | |
9ea75c57 | 1822 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 1823 | |
66a72d25 MK |
1824 | if (len == I387_SIZEOF_FXSAVE) |
1825 | { | |
1826 | i387_supply_fxsave (regcache, regnum, fpregs); | |
1827 | return; | |
1828 | } | |
1829 | ||
473f17b0 MK |
1830 | gdb_assert (len == tdep->sizeof_fpregset); |
1831 | i387_supply_fsave (regcache, regnum, fpregs); | |
1832 | } | |
8446b36a | 1833 | |
2f305df1 MK |
1834 | /* Collect register REGNUM from the register cache REGCACHE and store |
1835 | it in the buffer specified by FPREGS and LEN as described by the | |
1836 | floating-point register set REGSET. If REGNUM is -1, do this for | |
1837 | all registers in REGSET. */ | |
7fdafb5a MK |
1838 | |
1839 | static void | |
1840 | i386_collect_fpregset (const struct regset *regset, | |
1841 | const struct regcache *regcache, | |
1842 | int regnum, void *fpregs, size_t len) | |
1843 | { | |
1844 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1845 | ||
1846 | if (len == I387_SIZEOF_FXSAVE) | |
1847 | { | |
1848 | i387_collect_fxsave (regcache, regnum, fpregs); | |
1849 | return; | |
1850 | } | |
1851 | ||
1852 | gdb_assert (len == tdep->sizeof_fpregset); | |
1853 | i387_collect_fsave (regcache, regnum, fpregs); | |
1854 | } | |
1855 | ||
8446b36a MK |
1856 | /* Return the appropriate register set for the core section identified |
1857 | by SECT_NAME and SECT_SIZE. */ | |
1858 | ||
1859 | const struct regset * | |
1860 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
1861 | const char *sect_name, size_t sect_size) | |
1862 | { | |
1863 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1864 | ||
1865 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
1866 | { | |
1867 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
1868 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
1869 | i386_collect_gregset); | |
8446b36a MK |
1870 | return tdep->gregset; |
1871 | } | |
1872 | ||
66a72d25 MK |
1873 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
1874 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
1875 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
1876 | { |
1877 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
1878 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
1879 | i386_collect_fpregset); | |
8446b36a MK |
1880 | return tdep->fpregset; |
1881 | } | |
1882 | ||
1883 | return NULL; | |
1884 | } | |
473f17b0 | 1885 | \f |
fc338970 | 1886 | |
c906108c | 1887 | #ifdef STATIC_TRANSFORM_NAME |
fc338970 MK |
1888 | /* SunPRO encodes the static variables. This is not related to C++ |
1889 | mangling, it is done for C too. */ | |
c906108c SS |
1890 | |
1891 | char * | |
fba45db2 | 1892 | sunpro_static_transform_name (char *name) |
c906108c SS |
1893 | { |
1894 | char *p; | |
1895 | if (IS_STATIC_TRANSFORM_NAME (name)) | |
1896 | { | |
fc338970 MK |
1897 | /* For file-local statics there will be a period, a bunch of |
1898 | junk (the contents of which match a string given in the | |
c5aa993b JM |
1899 | N_OPT), a period and the name. For function-local statics |
1900 | there will be a bunch of junk (which seems to change the | |
1901 | second character from 'A' to 'B'), a period, the name of the | |
1902 | function, and the name. So just skip everything before the | |
1903 | last period. */ | |
c906108c SS |
1904 | p = strrchr (name, '.'); |
1905 | if (p != NULL) | |
1906 | name = p + 1; | |
1907 | } | |
1908 | return name; | |
1909 | } | |
1910 | #endif /* STATIC_TRANSFORM_NAME */ | |
fc338970 | 1911 | \f |
c906108c | 1912 | |
fc338970 | 1913 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
1914 | |
1915 | CORE_ADDR | |
1cce71eb | 1916 | i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name) |
c906108c | 1917 | { |
fc338970 | 1918 | if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */ |
c906108c | 1919 | { |
c5aa993b | 1920 | unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4); |
c906108c | 1921 | struct minimal_symbol *indsym = |
fc338970 | 1922 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 1923 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 1924 | |
c5aa993b | 1925 | if (symname) |
c906108c | 1926 | { |
c5aa993b JM |
1927 | if (strncmp (symname, "__imp_", 6) == 0 |
1928 | || strncmp (symname, "_imp_", 5) == 0) | |
c906108c SS |
1929 | return name ? 1 : read_memory_unsigned_integer (indirect, 4); |
1930 | } | |
1931 | } | |
fc338970 | 1932 | return 0; /* Not a trampoline. */ |
c906108c | 1933 | } |
fc338970 MK |
1934 | \f |
1935 | ||
377d9ebd | 1936 | /* Return whether the frame preceding NEXT_FRAME corresponds to a |
911bc6ee | 1937 | sigtramp routine. */ |
8201327c MK |
1938 | |
1939 | static int | |
911bc6ee | 1940 | i386_sigtramp_p (struct frame_info *next_frame) |
8201327c | 1941 | { |
911bc6ee MK |
1942 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1943 | char *name; | |
1944 | ||
1945 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
1946 | return (name && strcmp ("_sigtramp", name) == 0); |
1947 | } | |
1948 | \f | |
1949 | ||
fc338970 MK |
1950 | /* We have two flavours of disassembly. The machinery on this page |
1951 | deals with switching between those. */ | |
c906108c SS |
1952 | |
1953 | static int | |
a89aa300 | 1954 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 1955 | { |
5e3397bb MK |
1956 | gdb_assert (disassembly_flavor == att_flavor |
1957 | || disassembly_flavor == intel_flavor); | |
1958 | ||
1959 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
1960 | constified, cast to prevent a compiler warning. */ | |
1961 | info->disassembler_options = (char *) disassembly_flavor; | |
1962 | info->mach = gdbarch_bfd_arch_info (current_gdbarch)->mach; | |
1963 | ||
1964 | return print_insn_i386 (pc, info); | |
7a292a7a | 1965 | } |
fc338970 | 1966 | \f |
3ce1502b | 1967 | |
8201327c MK |
1968 | /* There are a few i386 architecture variants that differ only |
1969 | slightly from the generic i386 target. For now, we don't give them | |
1970 | their own source file, but include them here. As a consequence, | |
1971 | they'll always be included. */ | |
3ce1502b | 1972 | |
8201327c | 1973 | /* System V Release 4 (SVR4). */ |
3ce1502b | 1974 | |
377d9ebd | 1975 | /* Return whether the frame preceding NEXT_FRAME corresponds to a SVR4 |
911bc6ee MK |
1976 | sigtramp routine. */ |
1977 | ||
8201327c | 1978 | static int |
911bc6ee | 1979 | i386_svr4_sigtramp_p (struct frame_info *next_frame) |
d2a7c97a | 1980 | { |
911bc6ee MK |
1981 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1982 | char *name; | |
1983 | ||
acd5c798 MK |
1984 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
1985 | currently unknown. */ | |
911bc6ee | 1986 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
1987 | return (name && (strcmp ("_sigreturn", name) == 0 |
1988 | || strcmp ("_sigacthandler", name) == 0 | |
1989 | || strcmp ("sigvechandler", name) == 0)); | |
1990 | } | |
d2a7c97a | 1991 | |
acd5c798 MK |
1992 | /* Assuming NEXT_FRAME is for a frame following a SVR4 sigtramp |
1993 | routine, return the address of the associated sigcontext (ucontext) | |
1994 | structure. */ | |
3ce1502b | 1995 | |
3a1e71e3 | 1996 | static CORE_ADDR |
acd5c798 | 1997 | i386_svr4_sigcontext_addr (struct frame_info *next_frame) |
8201327c | 1998 | { |
acd5c798 MK |
1999 | char buf[4]; |
2000 | CORE_ADDR sp; | |
3ce1502b | 2001 | |
acd5c798 MK |
2002 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); |
2003 | sp = extract_unsigned_integer (buf, 4); | |
21d0e8a4 | 2004 | |
acd5c798 | 2005 | return read_memory_unsigned_integer (sp + 8, 4); |
8201327c MK |
2006 | } |
2007 | \f | |
3ce1502b | 2008 | |
8201327c | 2009 | /* Generic ELF. */ |
d2a7c97a | 2010 | |
8201327c MK |
2011 | void |
2012 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2013 | { | |
c4fc7f1b MK |
2014 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2015 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2016 | } |
3ce1502b | 2017 | |
8201327c | 2018 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2019 | |
8201327c MK |
2020 | void |
2021 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2022 | { | |
2023 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2024 | |
8201327c MK |
2025 | /* System V Release 4 uses ELF. */ |
2026 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2027 | |
dfe01d39 | 2028 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2029 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2030 | ||
911bc6ee | 2031 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2032 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2033 | tdep->sc_pc_offset = 36 + 14 * 4; |
2034 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2035 | |
8201327c | 2036 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2037 | } |
2038 | ||
8201327c | 2039 | /* DJGPP. */ |
3ce1502b | 2040 | |
3a1e71e3 | 2041 | static void |
8201327c | 2042 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2043 | { |
8201327c | 2044 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2045 | |
911bc6ee MK |
2046 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2047 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2048 | |
8201327c | 2049 | tdep->jb_pc_offset = 36; |
3ce1502b MK |
2050 | } |
2051 | ||
8201327c | 2052 | /* NetWare. */ |
3ce1502b | 2053 | |
3a1e71e3 | 2054 | static void |
8201327c | 2055 | i386_nw_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2056 | { |
8201327c | 2057 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2058 | |
8201327c | 2059 | tdep->jb_pc_offset = 24; |
d2a7c97a | 2060 | } |
8201327c | 2061 | \f |
2acceee2 | 2062 | |
38c968cf AC |
2063 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2064 | and "sse". */ | |
2065 | ||
2066 | static struct reggroup *i386_sse_reggroup; | |
2067 | static struct reggroup *i386_mmx_reggroup; | |
2068 | ||
2069 | static void | |
2070 | i386_init_reggroups (void) | |
2071 | { | |
2072 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2073 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2074 | } | |
2075 | ||
2076 | static void | |
2077 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2078 | { | |
2079 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2080 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2081 | reggroup_add (gdbarch, general_reggroup); | |
2082 | reggroup_add (gdbarch, float_reggroup); | |
2083 | reggroup_add (gdbarch, all_reggroup); | |
2084 | reggroup_add (gdbarch, save_reggroup); | |
2085 | reggroup_add (gdbarch, restore_reggroup); | |
2086 | reggroup_add (gdbarch, vector_reggroup); | |
2087 | reggroup_add (gdbarch, system_reggroup); | |
2088 | } | |
2089 | ||
2090 | int | |
2091 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2092 | struct reggroup *group) | |
2093 | { | |
5716833c MK |
2094 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2095 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2096 | int fp_regnum_p = (i386_fp_regnum_p (regnum) |
2097 | || i386_fpc_regnum_p (regnum)); | |
5716833c | 2098 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2099 | |
38c968cf AC |
2100 | if (group == i386_mmx_reggroup) |
2101 | return mmx_regnum_p; | |
2102 | if (group == i386_sse_reggroup) | |
2103 | return sse_regnum_p; | |
2104 | if (group == vector_reggroup) | |
2105 | return (mmx_regnum_p || sse_regnum_p); | |
2106 | if (group == float_reggroup) | |
2107 | return fp_regnum_p; | |
2108 | if (group == general_reggroup) | |
2109 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2110 | |
38c968cf AC |
2111 | return default_register_reggroup_p (gdbarch, regnum, group); |
2112 | } | |
38c968cf | 2113 | \f |
acd5c798 | 2114 | |
f837910f MK |
2115 | /* Get the ARGIth function argument for the current function. */ |
2116 | ||
42c466d7 | 2117 | static CORE_ADDR |
143985b7 AF |
2118 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2119 | struct type *type) | |
2120 | { | |
f837910f MK |
2121 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
2122 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4); | |
143985b7 AF |
2123 | } |
2124 | ||
2125 | \f | |
3a1e71e3 | 2126 | static struct gdbarch * |
a62cc96e AC |
2127 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
2128 | { | |
cd3c07fc | 2129 | struct gdbarch_tdep *tdep; |
a62cc96e AC |
2130 | struct gdbarch *gdbarch; |
2131 | ||
4be87837 DJ |
2132 | /* If there is already a candidate, use it. */ |
2133 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2134 | if (arches != NULL) | |
2135 | return arches->gdbarch; | |
a62cc96e AC |
2136 | |
2137 | /* Allocate space for the new architecture. */ | |
2138 | tdep = XMALLOC (struct gdbarch_tdep); | |
2139 | gdbarch = gdbarch_alloc (&info, tdep); | |
2140 | ||
473f17b0 MK |
2141 | /* General-purpose registers. */ |
2142 | tdep->gregset = NULL; | |
2143 | tdep->gregset_reg_offset = NULL; | |
2144 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
2145 | tdep->sizeof_gregset = 0; | |
2146 | ||
2147 | /* Floating-point registers. */ | |
2148 | tdep->fpregset = NULL; | |
2149 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
2150 | ||
5716833c | 2151 | /* The default settings include the FPU registers, the MMX registers |
fd35795f | 2152 | and the SSE registers. This can be overridden for a specific ABI |
5716833c MK |
2153 | by adjusting the members `st0_regnum', `mm0_regnum' and |
2154 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
2155 | will show up in the output of "info all-registers". Ideally we | |
2156 | should try to autodetect whether they are available, such that we | |
2157 | can prevent "info all-registers" from displaying registers that | |
2158 | aren't available. | |
2159 | ||
2160 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
2161 | [the SSE registers] always (even when they don't exist) or never | |
2162 | showing them to the user (even when they do exist), I prefer the | |
2163 | former over the latter. */ | |
2164 | ||
2165 | tdep->st0_regnum = I386_ST0_REGNUM; | |
2166 | ||
2167 | /* The MMX registers are implemented as pseudo-registers. Put off | |
fd35795f | 2168 | calculating the register number for %mm0 until we know the number |
5716833c MK |
2169 | of raw registers. */ |
2170 | tdep->mm0_regnum = 0; | |
2171 | ||
2172 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
49ed40de | 2173 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
d2a7c97a | 2174 | |
8201327c MK |
2175 | tdep->jb_pc_offset = -1; |
2176 | tdep->struct_return = pcc_struct_return; | |
8201327c MK |
2177 | tdep->sigtramp_start = 0; |
2178 | tdep->sigtramp_end = 0; | |
911bc6ee | 2179 | tdep->sigtramp_p = i386_sigtramp_p; |
21d0e8a4 | 2180 | tdep->sigcontext_addr = NULL; |
a3386186 | 2181 | tdep->sc_reg_offset = NULL; |
8201327c | 2182 | tdep->sc_pc_offset = -1; |
21d0e8a4 | 2183 | tdep->sc_sp_offset = -1; |
8201327c | 2184 | |
896fb97d MK |
2185 | /* The format used for `long double' on almost all i386 targets is |
2186 | the i387 extended floating-point format. In fact, of all targets | |
2187 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
2188 | on having a `long double' that's not `long' at all. */ | |
2189 | set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext); | |
21d0e8a4 | 2190 | |
66da5fd8 | 2191 | /* Although the i387 extended floating-point has only 80 significant |
896fb97d MK |
2192 | bits, a `long double' actually takes up 96, probably to enforce |
2193 | alignment. */ | |
2194 | set_gdbarch_long_double_bit (gdbarch, 96); | |
2195 | ||
49ed40de KB |
2196 | /* The default ABI includes general-purpose registers, |
2197 | floating-point registers, and the SSE registers. */ | |
2198 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
acd5c798 MK |
2199 | set_gdbarch_register_name (gdbarch, i386_register_name); |
2200 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
21d0e8a4 | 2201 | |
acd5c798 MK |
2202 | /* Register numbers of various important registers. */ |
2203 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
2204 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
2205 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
2206 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
356a6b3e | 2207 | |
c4fc7f1b MK |
2208 | /* NOTE: kettenis/20040418: GCC does have two possible register |
2209 | numbering schemes on the i386: dbx and SVR4. These schemes | |
2210 | differ in how they number %ebp, %esp, %eflags, and the | |
fd35795f | 2211 | floating-point registers, and are implemented by the arrays |
c4fc7f1b MK |
2212 | dbx_register_map[] and svr4_dbx_register_map in |
2213 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
2214 | gcc/config/i386.c, which it designates as the "default" register | |
2215 | map used in 64bit mode. This last register numbering scheme is | |
d4dc1a91 | 2216 | implemented in dbx64_register_map, and is used for AMD64; see |
c4fc7f1b MK |
2217 | amd64-tdep.c. |
2218 | ||
2219 | Currently, each GCC i386 target always uses the same register | |
2220 | numbering scheme across all its supported debugging formats | |
2221 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
2222 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
2223 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
2224 | respective config header in a manner independent of the requested | |
2225 | output debugging format. | |
2226 | ||
2227 | This does not match the arrangement below, which presumes that | |
2228 | the SDB and stabs numbering schemes differ from the DWARF and | |
2229 | DWARF 2 ones. The reason for this arrangement is that it is | |
2230 | likely to get the numbering scheme for the target's | |
2231 | default/native debug format right. For targets where GCC is the | |
2232 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
2233 | targets where the native toolchain uses a different numbering | |
2234 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
d4dc1a91 BF |
2235 | the defaults below will have to be overridden, like |
2236 | i386_elf_init_abi() does. */ | |
c4fc7f1b MK |
2237 | |
2238 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
2239 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2240 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2241 | ||
2242 | /* Use the SVR4 register numbering scheme for DWARF and DWARF 2. */ | |
2243 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2244 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
356a6b3e MK |
2245 | |
2246 | /* We don't define ECOFF_REG_TO_REGNUM, since ECOFF doesn't seem to | |
2247 | be in use on any of the supported i386 targets. */ | |
2248 | ||
61113f8b MK |
2249 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
2250 | ||
8201327c | 2251 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
96297dab | 2252 | |
a62cc96e | 2253 | /* Call dummy code. */ |
acd5c798 | 2254 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
a62cc96e | 2255 | |
ff2e87ac AC |
2256 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
2257 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
2258 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
b6197528 | 2259 | |
c5e656c1 | 2260 | set_gdbarch_return_value (gdbarch, i386_return_value); |
8201327c | 2261 | |
93924b6b MK |
2262 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
2263 | ||
2264 | /* Stack grows downward. */ | |
2265 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2266 | ||
2267 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
2268 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
42fdc8df | 2269 | |
42fdc8df | 2270 | set_gdbarch_frame_args_skip (gdbarch, 8); |
8201327c | 2271 | |
28fc6740 | 2272 | /* Wire in the MMX registers. */ |
0f751ff2 | 2273 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); |
28fc6740 AC |
2274 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
2275 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
2276 | ||
5e3397bb MK |
2277 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
2278 | ||
acd5c798 | 2279 | set_gdbarch_unwind_dummy_id (gdbarch, i386_unwind_dummy_id); |
acd5c798 MK |
2280 | |
2281 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
2282 | ||
38c968cf AC |
2283 | /* Add the i386 register groups. */ |
2284 | i386_add_reggroups (gdbarch); | |
2285 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
2286 | ||
143985b7 AF |
2287 | /* Helper for function argument information. */ |
2288 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
2289 | ||
6405b0a6 | 2290 | /* Hook in the DWARF CFI frame unwinder. */ |
336d1bba | 2291 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
6405b0a6 | 2292 | |
acd5c798 | 2293 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 2294 | |
3ce1502b | 2295 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2296 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 2297 | |
336d1bba AC |
2298 | frame_unwind_append_sniffer (gdbarch, i386_sigtramp_frame_sniffer); |
2299 | frame_unwind_append_sniffer (gdbarch, i386_frame_sniffer); | |
acd5c798 | 2300 | |
8446b36a MK |
2301 | /* If we have a register mapping, enable the generic core file |
2302 | support, unless it has already been enabled. */ | |
2303 | if (tdep->gregset_reg_offset | |
2304 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
2305 | set_gdbarch_regset_from_core_section (gdbarch, | |
2306 | i386_regset_from_core_section); | |
2307 | ||
5716833c MK |
2308 | /* Unless support for MMX has been disabled, make %mm0 the first |
2309 | pseudo-register. */ | |
2310 | if (tdep->mm0_regnum == 0) | |
2311 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
2312 | ||
a62cc96e AC |
2313 | return gdbarch; |
2314 | } | |
2315 | ||
8201327c MK |
2316 | static enum gdb_osabi |
2317 | i386_coff_osabi_sniffer (bfd *abfd) | |
2318 | { | |
762c5349 MK |
2319 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
2320 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
2321 | return GDB_OSABI_GO32; |
2322 | ||
2323 | return GDB_OSABI_UNKNOWN; | |
2324 | } | |
2325 | ||
2326 | static enum gdb_osabi | |
2327 | i386_nlm_osabi_sniffer (bfd *abfd) | |
2328 | { | |
2329 | return GDB_OSABI_NETWARE; | |
2330 | } | |
2331 | \f | |
2332 | ||
28e9e0f0 MK |
2333 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2334 | void _initialize_i386_tdep (void); | |
2335 | ||
c906108c | 2336 | void |
fba45db2 | 2337 | _initialize_i386_tdep (void) |
c906108c | 2338 | { |
a62cc96e AC |
2339 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
2340 | ||
fc338970 | 2341 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
2342 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
2343 | &disassembly_flavor, _("\ | |
2344 | Set the disassembly flavor."), _("\ | |
2345 | Show the disassembly flavor."), _("\ | |
2346 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
2347 | NULL, | |
2348 | NULL, /* FIXME: i18n: */ | |
2349 | &setlist, &showlist); | |
8201327c MK |
2350 | |
2351 | /* Add the variable that controls the convention for returning | |
2352 | structs. */ | |
7ab04401 AC |
2353 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
2354 | &struct_convention, _("\ | |
2355 | Set the convention for returning small structs."), _("\ | |
2356 | Show the convention for returning small structs."), _("\ | |
2357 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
2358 | is \"default\"."), | |
2359 | NULL, | |
2360 | NULL, /* FIXME: i18n: */ | |
2361 | &setlist, &showlist); | |
8201327c MK |
2362 | |
2363 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
2364 | i386_coff_osabi_sniffer); | |
2365 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_nlm_flavour, | |
2366 | i386_nlm_osabi_sniffer); | |
2367 | ||
05816f70 | 2368 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 2369 | i386_svr4_init_abi); |
05816f70 | 2370 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 2371 | i386_go32_init_abi); |
05816f70 | 2372 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_NETWARE, |
8201327c | 2373 | i386_nw_init_abi); |
38c968cf AC |
2374 | |
2375 | /* Initialize the i386 specific register groups. */ | |
2376 | i386_init_reggroups (); | |
c906108c | 2377 | } |