Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
61baf725 | 3 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
45741a9c | 31 | #include "infrun.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
df7e5265 | 49 | #include "x86-xstate.h" |
d2a7c97a | 50 | |
7ad10968 | 51 | #include "record.h" |
d02ed0bb | 52 | #include "record-full.h" |
22916b07 YQ |
53 | #include "target-descriptions.h" |
54 | #include "arch/i386.h" | |
90884b2b | 55 | |
6710bf39 SS |
56 | #include "ax.h" |
57 | #include "ax-gdb.h" | |
58 | ||
55aa24fb SDJ |
59 | #include "stap-probe.h" |
60 | #include "user-regs.h" | |
61 | #include "cli/cli-utils.h" | |
62 | #include "expression.h" | |
63 | #include "parser-defs.h" | |
64 | #include <ctype.h> | |
325fac50 | 65 | #include <algorithm> |
55aa24fb | 66 | |
c4fc7f1b | 67 | /* Register names. */ |
c40e1eab | 68 | |
90884b2b | 69 | static const char *i386_register_names[] = |
fc633446 MK |
70 | { |
71 | "eax", "ecx", "edx", "ebx", | |
72 | "esp", "ebp", "esi", "edi", | |
73 | "eip", "eflags", "cs", "ss", | |
74 | "ds", "es", "fs", "gs", | |
75 | "st0", "st1", "st2", "st3", | |
76 | "st4", "st5", "st6", "st7", | |
77 | "fctrl", "fstat", "ftag", "fiseg", | |
78 | "fioff", "foseg", "fooff", "fop", | |
79 | "xmm0", "xmm1", "xmm2", "xmm3", | |
80 | "xmm4", "xmm5", "xmm6", "xmm7", | |
81 | "mxcsr" | |
82 | }; | |
83 | ||
01f9f808 MS |
84 | static const char *i386_zmm_names[] = |
85 | { | |
86 | "zmm0", "zmm1", "zmm2", "zmm3", | |
87 | "zmm4", "zmm5", "zmm6", "zmm7" | |
88 | }; | |
89 | ||
90 | static const char *i386_zmmh_names[] = | |
91 | { | |
92 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
93 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
94 | }; | |
95 | ||
96 | static const char *i386_k_names[] = | |
97 | { | |
98 | "k0", "k1", "k2", "k3", | |
99 | "k4", "k5", "k6", "k7" | |
100 | }; | |
101 | ||
c131fcee L |
102 | static const char *i386_ymm_names[] = |
103 | { | |
104 | "ymm0", "ymm1", "ymm2", "ymm3", | |
105 | "ymm4", "ymm5", "ymm6", "ymm7", | |
106 | }; | |
107 | ||
108 | static const char *i386_ymmh_names[] = | |
109 | { | |
110 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
111 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
112 | }; | |
113 | ||
1dbcd68c WT |
114 | static const char *i386_mpx_names[] = |
115 | { | |
116 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
117 | }; | |
118 | ||
51547df6 MS |
119 | static const char* i386_pkeys_names[] = |
120 | { | |
121 | "pkru" | |
122 | }; | |
123 | ||
1dbcd68c WT |
124 | /* Register names for MPX pseudo-registers. */ |
125 | ||
126 | static const char *i386_bnd_names[] = | |
127 | { | |
128 | "bnd0", "bnd1", "bnd2", "bnd3" | |
129 | }; | |
130 | ||
c4fc7f1b | 131 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 132 | |
90884b2b | 133 | static const char *i386_mmx_names[] = |
28fc6740 AC |
134 | { |
135 | "mm0", "mm1", "mm2", "mm3", | |
136 | "mm4", "mm5", "mm6", "mm7" | |
137 | }; | |
c40e1eab | 138 | |
1ba53b71 L |
139 | /* Register names for byte pseudo-registers. */ |
140 | ||
141 | static const char *i386_byte_names[] = | |
142 | { | |
143 | "al", "cl", "dl", "bl", | |
144 | "ah", "ch", "dh", "bh" | |
145 | }; | |
146 | ||
147 | /* Register names for word pseudo-registers. */ | |
148 | ||
149 | static const char *i386_word_names[] = | |
150 | { | |
151 | "ax", "cx", "dx", "bx", | |
9cad29ac | 152 | "", "bp", "si", "di" |
1ba53b71 L |
153 | }; |
154 | ||
01f9f808 MS |
155 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
156 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
157 | we have 16 upper ZMM regs that have to be handled differently. */ | |
158 | ||
159 | const int num_lower_zmm_regs = 16; | |
160 | ||
1ba53b71 | 161 | /* MMX register? */ |
c40e1eab | 162 | |
28fc6740 | 163 | static int |
5716833c | 164 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 165 | { |
1ba53b71 L |
166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
167 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
168 | |
169 | if (mm0_regnum < 0) | |
170 | return 0; | |
171 | ||
1ba53b71 L |
172 | regnum -= mm0_regnum; |
173 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
174 | } | |
175 | ||
176 | /* Byte register? */ | |
177 | ||
178 | int | |
179 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
180 | { | |
181 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
182 | ||
183 | regnum -= tdep->al_regnum; | |
184 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
185 | } | |
186 | ||
187 | /* Word register? */ | |
188 | ||
189 | int | |
190 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
191 | { | |
192 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
193 | ||
194 | regnum -= tdep->ax_regnum; | |
195 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
196 | } | |
197 | ||
198 | /* Dword register? */ | |
199 | ||
200 | int | |
201 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
202 | { | |
203 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
204 | int eax_regnum = tdep->eax_regnum; | |
205 | ||
206 | if (eax_regnum < 0) | |
207 | return 0; | |
208 | ||
209 | regnum -= eax_regnum; | |
210 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
211 | } |
212 | ||
01f9f808 MS |
213 | /* AVX512 register? */ |
214 | ||
215 | int | |
216 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
217 | { | |
218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
219 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
220 | ||
221 | if (zmm0h_regnum < 0) | |
222 | return 0; | |
223 | ||
224 | regnum -= zmm0h_regnum; | |
225 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
226 | } | |
227 | ||
228 | int | |
229 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
230 | { | |
231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
232 | int zmm0_regnum = tdep->zmm0_regnum; | |
233 | ||
234 | if (zmm0_regnum < 0) | |
235 | return 0; | |
236 | ||
237 | regnum -= zmm0_regnum; | |
238 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
239 | } | |
240 | ||
241 | int | |
242 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
243 | { | |
244 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
245 | int k0_regnum = tdep->k0_regnum; | |
246 | ||
247 | if (k0_regnum < 0) | |
248 | return 0; | |
249 | ||
250 | regnum -= k0_regnum; | |
251 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
252 | } | |
253 | ||
9191d390 | 254 | static int |
c131fcee L |
255 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
256 | { | |
257 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
258 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
259 | ||
260 | if (ymm0h_regnum < 0) | |
261 | return 0; | |
262 | ||
263 | regnum -= ymm0h_regnum; | |
264 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
265 | } | |
266 | ||
267 | /* AVX register? */ | |
268 | ||
269 | int | |
270 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
271 | { | |
272 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
273 | int ymm0_regnum = tdep->ymm0_regnum; | |
274 | ||
275 | if (ymm0_regnum < 0) | |
276 | return 0; | |
277 | ||
278 | regnum -= ymm0_regnum; | |
279 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
280 | } | |
281 | ||
01f9f808 MS |
282 | static int |
283 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
284 | { | |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
286 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
287 | ||
288 | if (ymm16h_regnum < 0) | |
289 | return 0; | |
290 | ||
291 | regnum -= ymm16h_regnum; | |
292 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
293 | } | |
294 | ||
295 | int | |
296 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
297 | { | |
298 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
299 | int ymm16_regnum = tdep->ymm16_regnum; | |
300 | ||
301 | if (ymm16_regnum < 0) | |
302 | return 0; | |
303 | ||
304 | regnum -= ymm16_regnum; | |
305 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
306 | } | |
307 | ||
1dbcd68c WT |
308 | /* BND register? */ |
309 | ||
310 | int | |
311 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
312 | { | |
313 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
314 | int bnd0_regnum = tdep->bnd0_regnum; | |
315 | ||
316 | if (bnd0_regnum < 0) | |
317 | return 0; | |
318 | ||
319 | regnum -= bnd0_regnum; | |
320 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
321 | } | |
322 | ||
5716833c | 323 | /* SSE register? */ |
23a34459 | 324 | |
c131fcee L |
325 | int |
326 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 327 | { |
5716833c | 328 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 329 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 330 | |
c131fcee | 331 | if (num_xmm_regs == 0) |
5716833c MK |
332 | return 0; |
333 | ||
c131fcee L |
334 | regnum -= I387_XMM0_REGNUM (tdep); |
335 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
336 | } |
337 | ||
01f9f808 MS |
338 | /* XMM_512 register? */ |
339 | ||
340 | int | |
341 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
342 | { | |
343 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
344 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
345 | ||
346 | if (num_xmm_avx512_regs == 0) | |
347 | return 0; | |
348 | ||
349 | regnum -= I387_XMM16_REGNUM (tdep); | |
350 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
351 | } | |
352 | ||
5716833c MK |
353 | static int |
354 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 355 | { |
5716833c MK |
356 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
357 | ||
20a6ec49 | 358 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
359 | return 0; |
360 | ||
20a6ec49 | 361 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
362 | } |
363 | ||
5716833c | 364 | /* FP register? */ |
23a34459 AC |
365 | |
366 | int | |
20a6ec49 | 367 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 368 | { |
20a6ec49 MD |
369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
370 | ||
371 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
372 | return 0; |
373 | ||
20a6ec49 MD |
374 | return (I387_ST0_REGNUM (tdep) <= regnum |
375 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
376 | } |
377 | ||
378 | int | |
20a6ec49 | 379 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 380 | { |
20a6ec49 MD |
381 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
382 | ||
383 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
384 | return 0; |
385 | ||
20a6ec49 MD |
386 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
387 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
388 | } |
389 | ||
1dbcd68c WT |
390 | /* BNDr (raw) register? */ |
391 | ||
392 | static int | |
393 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
394 | { | |
395 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
396 | ||
397 | if (I387_BND0R_REGNUM (tdep) < 0) | |
398 | return 0; | |
399 | ||
400 | regnum -= tdep->bnd0r_regnum; | |
401 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
402 | } | |
403 | ||
404 | /* BND control register? */ | |
405 | ||
406 | static int | |
407 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
408 | { | |
409 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
410 | ||
411 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
412 | return 0; | |
413 | ||
414 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
415 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
416 | } | |
417 | ||
51547df6 MS |
418 | /* PKRU register? */ |
419 | ||
420 | bool | |
421 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
422 | { | |
423 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
424 | int pkru_regnum = tdep->pkru_regnum; | |
425 | ||
426 | if (pkru_regnum < 0) | |
427 | return false; | |
428 | ||
429 | regnum -= pkru_regnum; | |
430 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
431 | } | |
432 | ||
c131fcee L |
433 | /* Return the name of register REGNUM, or the empty string if it is |
434 | an anonymous register. */ | |
435 | ||
436 | static const char * | |
437 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
438 | { | |
439 | /* Hide the upper YMM registers. */ | |
440 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
441 | return ""; | |
442 | ||
01f9f808 MS |
443 | /* Hide the upper YMM16-31 registers. */ |
444 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
445 | return ""; | |
446 | ||
447 | /* Hide the upper ZMM registers. */ | |
448 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
449 | return ""; | |
450 | ||
c131fcee L |
451 | return tdesc_register_name (gdbarch, regnum); |
452 | } | |
453 | ||
30b0e2d8 | 454 | /* Return the name of register REGNUM. */ |
fc633446 | 455 | |
1ba53b71 | 456 | const char * |
90884b2b | 457 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 458 | { |
1ba53b71 | 459 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
460 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
461 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
462 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
463 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
464 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
465 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
466 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
467 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
468 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
469 | return i386_byte_names[regnum - tdep->al_regnum]; | |
470 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
471 | return i386_word_names[regnum - tdep->ax_regnum]; | |
472 | ||
473 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
474 | } |
475 | ||
c4fc7f1b | 476 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
477 | number used by GDB. */ |
478 | ||
8201327c | 479 | static int |
d3f73121 | 480 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 481 | { |
20a6ec49 MD |
482 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
483 | ||
c4fc7f1b MK |
484 | /* This implements what GCC calls the "default" register map |
485 | (dbx_register_map[]). */ | |
486 | ||
85540d8c MK |
487 | if (reg >= 0 && reg <= 7) |
488 | { | |
9872ad24 JB |
489 | /* General-purpose registers. The debug info calls %ebp |
490 | register 4, and %esp register 5. */ | |
491 | if (reg == 4) | |
492 | return 5; | |
493 | else if (reg == 5) | |
494 | return 4; | |
495 | else return reg; | |
85540d8c MK |
496 | } |
497 | else if (reg >= 12 && reg <= 19) | |
498 | { | |
499 | /* Floating-point registers. */ | |
20a6ec49 | 500 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
501 | } |
502 | else if (reg >= 21 && reg <= 28) | |
503 | { | |
504 | /* SSE registers. */ | |
c131fcee L |
505 | int ymm0_regnum = tdep->ymm0_regnum; |
506 | ||
507 | if (ymm0_regnum >= 0 | |
508 | && i386_xmm_regnum_p (gdbarch, reg)) | |
509 | return reg - 21 + ymm0_regnum; | |
510 | else | |
511 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
512 | } |
513 | else if (reg >= 29 && reg <= 36) | |
514 | { | |
515 | /* MMX registers. */ | |
20a6ec49 | 516 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
517 | } |
518 | ||
519 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 520 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
521 | } |
522 | ||
0fde2c53 | 523 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 524 | used by GDB. */ |
85540d8c | 525 | |
8201327c | 526 | static int |
0fde2c53 | 527 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 528 | { |
20a6ec49 MD |
529 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
530 | ||
c4fc7f1b MK |
531 | /* This implements the GCC register map that tries to be compatible |
532 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
533 | ||
534 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
535 | numbers the floating point registers differently. */ |
536 | if (reg >= 0 && reg <= 9) | |
537 | { | |
acd5c798 | 538 | /* General-purpose registers. */ |
85540d8c MK |
539 | return reg; |
540 | } | |
541 | else if (reg >= 11 && reg <= 18) | |
542 | { | |
543 | /* Floating-point registers. */ | |
20a6ec49 | 544 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 545 | } |
c6f4c129 | 546 | else if (reg >= 21 && reg <= 36) |
85540d8c | 547 | { |
c4fc7f1b | 548 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 549 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
550 | } |
551 | ||
c6f4c129 JB |
552 | switch (reg) |
553 | { | |
20a6ec49 MD |
554 | case 37: return I387_FCTRL_REGNUM (tdep); |
555 | case 38: return I387_FSTAT_REGNUM (tdep); | |
556 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
557 | case 40: return I386_ES_REGNUM; |
558 | case 41: return I386_CS_REGNUM; | |
559 | case 42: return I386_SS_REGNUM; | |
560 | case 43: return I386_DS_REGNUM; | |
561 | case 44: return I386_FS_REGNUM; | |
562 | case 45: return I386_GS_REGNUM; | |
563 | } | |
564 | ||
0fde2c53 DE |
565 | return -1; |
566 | } | |
567 | ||
568 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
569 | num_regs + num_pseudo_regs for other debug formats. */ | |
570 | ||
8f10c932 | 571 | int |
0fde2c53 DE |
572 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
573 | { | |
574 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
575 | ||
576 | if (regnum == -1) | |
577 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
578 | return regnum; | |
85540d8c | 579 | } |
5716833c | 580 | |
fc338970 | 581 | \f |
917317f4 | 582 | |
fc338970 MK |
583 | /* This is the variable that is set with "set disassembly-flavor", and |
584 | its legitimate values. */ | |
53904c9e AC |
585 | static const char att_flavor[] = "att"; |
586 | static const char intel_flavor[] = "intel"; | |
40478521 | 587 | static const char *const valid_flavors[] = |
c5aa993b | 588 | { |
c906108c SS |
589 | att_flavor, |
590 | intel_flavor, | |
591 | NULL | |
592 | }; | |
53904c9e | 593 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 594 | \f |
c906108c | 595 | |
acd5c798 MK |
596 | /* Use the program counter to determine the contents and size of a |
597 | breakpoint instruction. Return a pointer to a string of bytes that | |
598 | encode a breakpoint instruction, store the length of the string in | |
599 | *LEN and optionally adjust *PC to point to the correct memory | |
600 | location for inserting the breakpoint. | |
c906108c | 601 | |
acd5c798 MK |
602 | On the i386 we have a single breakpoint that fits in a single byte |
603 | and can be inserted anywhere. | |
c906108c | 604 | |
acd5c798 | 605 | This function is 64-bit safe. */ |
63c0089f | 606 | |
04180708 YQ |
607 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
608 | ||
609 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 610 | |
237fc4c9 PA |
611 | \f |
612 | /* Displaced instruction handling. */ | |
613 | ||
1903f0e6 DE |
614 | /* Skip the legacy instruction prefixes in INSN. |
615 | Not all prefixes are valid for any particular insn | |
616 | but we needn't care, the insn will fault if it's invalid. | |
617 | The result is a pointer to the first opcode byte, | |
618 | or NULL if we run off the end of the buffer. */ | |
619 | ||
620 | static gdb_byte * | |
621 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
622 | { | |
623 | gdb_byte *end = insn + max_len; | |
624 | ||
625 | while (insn < end) | |
626 | { | |
627 | switch (*insn) | |
628 | { | |
629 | case DATA_PREFIX_OPCODE: | |
630 | case ADDR_PREFIX_OPCODE: | |
631 | case CS_PREFIX_OPCODE: | |
632 | case DS_PREFIX_OPCODE: | |
633 | case ES_PREFIX_OPCODE: | |
634 | case FS_PREFIX_OPCODE: | |
635 | case GS_PREFIX_OPCODE: | |
636 | case SS_PREFIX_OPCODE: | |
637 | case LOCK_PREFIX_OPCODE: | |
638 | case REPE_PREFIX_OPCODE: | |
639 | case REPNE_PREFIX_OPCODE: | |
640 | ++insn; | |
641 | continue; | |
642 | default: | |
643 | return insn; | |
644 | } | |
645 | } | |
646 | ||
647 | return NULL; | |
648 | } | |
237fc4c9 PA |
649 | |
650 | static int | |
1903f0e6 | 651 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 652 | { |
1777feb0 | 653 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
654 | if (insn[0] == 0xea) |
655 | return 1; | |
656 | ||
657 | if (insn[0] == 0xff) | |
658 | { | |
1777feb0 | 659 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
660 | if ((insn[1] & 0x38) == 0x20) |
661 | return 1; | |
662 | ||
1777feb0 | 663 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
664 | if ((insn[1] & 0x38) == 0x28) |
665 | return 1; | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
c2170eef MM |
671 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
672 | ||
673 | static int | |
674 | i386_jmp_p (const gdb_byte *insn) | |
675 | { | |
676 | /* jump short, relative. */ | |
677 | if (insn[0] == 0xeb) | |
678 | return 1; | |
679 | ||
680 | /* jump near, relative. */ | |
681 | if (insn[0] == 0xe9) | |
682 | return 1; | |
683 | ||
684 | return i386_absolute_jmp_p (insn); | |
685 | } | |
686 | ||
237fc4c9 | 687 | static int |
1903f0e6 | 688 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 689 | { |
1777feb0 | 690 | /* call far, absolute. */ |
237fc4c9 PA |
691 | if (insn[0] == 0x9a) |
692 | return 1; | |
693 | ||
694 | if (insn[0] == 0xff) | |
695 | { | |
1777feb0 | 696 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
697 | if ((insn[1] & 0x38) == 0x10) |
698 | return 1; | |
699 | ||
1777feb0 | 700 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
701 | if ((insn[1] & 0x38) == 0x18) |
702 | return 1; | |
703 | } | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
708 | static int | |
1903f0e6 | 709 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
710 | { |
711 | switch (insn[0]) | |
712 | { | |
1777feb0 | 713 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 714 | case 0xc3: /* ret near */ |
1777feb0 | 715 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
716 | case 0xcb: /* ret far */ |
717 | case 0xcf: /* iret */ | |
718 | return 1; | |
719 | ||
720 | default: | |
721 | return 0; | |
722 | } | |
723 | } | |
724 | ||
725 | static int | |
1903f0e6 | 726 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
727 | { |
728 | if (i386_absolute_call_p (insn)) | |
729 | return 1; | |
730 | ||
1777feb0 | 731 | /* call near, relative. */ |
237fc4c9 PA |
732 | if (insn[0] == 0xe8) |
733 | return 1; | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
237fc4c9 PA |
738 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
739 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 740 | |
237fc4c9 | 741 | static int |
b55078be | 742 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 743 | { |
9a7f938f JK |
744 | /* Is it 'int $0x80'? */ |
745 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
746 | /* Or is it 'sysenter'? */ | |
747 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
748 | /* Or is it 'syscall'? */ | |
749 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
750 | { |
751 | *lengthp = 2; | |
752 | return 1; | |
753 | } | |
754 | ||
755 | return 0; | |
756 | } | |
757 | ||
c2170eef MM |
758 | /* The gdbarch insn_is_call method. */ |
759 | ||
760 | static int | |
761 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
762 | { | |
763 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
764 | ||
765 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
766 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
767 | ||
768 | return i386_call_p (insn); | |
769 | } | |
770 | ||
771 | /* The gdbarch insn_is_ret method. */ | |
772 | ||
773 | static int | |
774 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
775 | { | |
776 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
777 | ||
778 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
779 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
780 | ||
781 | return i386_ret_p (insn); | |
782 | } | |
783 | ||
784 | /* The gdbarch insn_is_jump method. */ | |
785 | ||
786 | static int | |
787 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
788 | { | |
789 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
790 | ||
791 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
792 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
793 | ||
794 | return i386_jmp_p (insn); | |
795 | } | |
796 | ||
c2508e90 | 797 | /* Some kernels may run one past a syscall insn, so we have to cope. */ |
b55078be DE |
798 | |
799 | struct displaced_step_closure * | |
800 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
801 | CORE_ADDR from, CORE_ADDR to, | |
802 | struct regcache *regs) | |
803 | { | |
804 | size_t len = gdbarch_max_insn_length (gdbarch); | |
224c3ddb | 805 | gdb_byte *buf = (gdb_byte *) xmalloc (len); |
b55078be DE |
806 | |
807 | read_memory (from, buf, len); | |
808 | ||
809 | /* GDB may get control back after the insn after the syscall. | |
810 | Presumably this is a kernel bug. | |
811 | If this is a syscall, make sure there's a nop afterwards. */ | |
812 | { | |
813 | int syscall_length; | |
814 | gdb_byte *insn; | |
815 | ||
816 | insn = i386_skip_prefixes (buf, len); | |
817 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
818 | insn[syscall_length] = NOP_OPCODE; | |
819 | } | |
820 | ||
821 | write_memory (to, buf, len); | |
822 | ||
823 | if (debug_displaced) | |
824 | { | |
825 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
826 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
827 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
828 | } | |
829 | ||
830 | return (struct displaced_step_closure *) buf; | |
831 | } | |
832 | ||
237fc4c9 PA |
833 | /* Fix up the state of registers and memory after having single-stepped |
834 | a displaced instruction. */ | |
1903f0e6 | 835 | |
237fc4c9 PA |
836 | void |
837 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
838 | struct displaced_step_closure *closure, | |
839 | CORE_ADDR from, CORE_ADDR to, | |
840 | struct regcache *regs) | |
841 | { | |
e17a4113 UW |
842 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
843 | ||
237fc4c9 PA |
844 | /* The offset we applied to the instruction's address. |
845 | This could well be negative (when viewed as a signed 32-bit | |
846 | value), but ULONGEST won't reflect that, so take care when | |
847 | applying it. */ | |
848 | ULONGEST insn_offset = to - from; | |
849 | ||
c2508e90 | 850 | /* Our closure is a copy of the instruction. */ |
237fc4c9 | 851 | gdb_byte *insn = (gdb_byte *) closure; |
1903f0e6 DE |
852 | /* The start of the insn, needed in case we see some prefixes. */ |
853 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
854 | |
855 | if (debug_displaced) | |
856 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 857 | "displaced: fixup (%s, %s), " |
237fc4c9 | 858 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
859 | paddress (gdbarch, from), paddress (gdbarch, to), |
860 | insn[0], insn[1]); | |
237fc4c9 PA |
861 | |
862 | /* The list of issues to contend with here is taken from | |
863 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
864 | Yay for Free Software! */ | |
865 | ||
866 | /* Relocate the %eip, if necessary. */ | |
867 | ||
1903f0e6 DE |
868 | /* The instruction recognizers we use assume any leading prefixes |
869 | have been skipped. */ | |
870 | { | |
871 | /* This is the size of the buffer in closure. */ | |
872 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
873 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
874 | /* If there are too many prefixes, just ignore the insn. | |
875 | It will fault when run. */ | |
876 | if (opcode != NULL) | |
877 | insn = opcode; | |
878 | } | |
879 | ||
237fc4c9 PA |
880 | /* Except in the case of absolute or indirect jump or call |
881 | instructions, or a return instruction, the new eip is relative to | |
882 | the displaced instruction; make it relative. Well, signal | |
883 | handler returns don't need relocation either, but we use the | |
884 | value of %eip to recognize those; see below. */ | |
885 | if (! i386_absolute_jmp_p (insn) | |
886 | && ! i386_absolute_call_p (insn) | |
887 | && ! i386_ret_p (insn)) | |
888 | { | |
889 | ULONGEST orig_eip; | |
b55078be | 890 | int insn_len; |
237fc4c9 PA |
891 | |
892 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
893 | ||
894 | /* A signal trampoline system call changes the %eip, resuming | |
895 | execution of the main program after the signal handler has | |
896 | returned. That makes them like 'return' instructions; we | |
897 | shouldn't relocate %eip. | |
898 | ||
899 | But most system calls don't, and we do need to relocate %eip. | |
900 | ||
901 | Our heuristic for distinguishing these cases: if stepping | |
902 | over the system call instruction left control directly after | |
903 | the instruction, the we relocate --- control almost certainly | |
904 | doesn't belong in the displaced copy. Otherwise, we assume | |
905 | the instruction has put control where it belongs, and leave | |
906 | it unrelocated. Goodness help us if there are PC-relative | |
907 | system calls. */ | |
908 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
909 | && orig_eip != to + (insn - insn_start) + insn_len |
910 | /* GDB can get control back after the insn after the syscall. | |
911 | Presumably this is a kernel bug. | |
912 | i386_displaced_step_copy_insn ensures its a nop, | |
913 | we add one to the length for it. */ | |
914 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
915 | { |
916 | if (debug_displaced) | |
917 | fprintf_unfiltered (gdb_stdlog, | |
918 | "displaced: syscall changed %%eip; " | |
919 | "not relocating\n"); | |
920 | } | |
921 | else | |
922 | { | |
923 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
924 | ||
1903f0e6 DE |
925 | /* If we just stepped over a breakpoint insn, we don't backup |
926 | the pc on purpose; this is to match behaviour without | |
927 | stepping. */ | |
237fc4c9 PA |
928 | |
929 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
930 | ||
931 | if (debug_displaced) | |
932 | fprintf_unfiltered (gdb_stdlog, | |
933 | "displaced: " | |
5af949e3 UW |
934 | "relocated %%eip from %s to %s\n", |
935 | paddress (gdbarch, orig_eip), | |
936 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
937 | } |
938 | } | |
939 | ||
940 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
941 | pushed value, and should be cleared. We'll leave this for later, | |
942 | since GDB already messes up the TF flag when stepping over a | |
943 | pushfl. */ | |
944 | ||
945 | /* If the instruction was a call, the return address now atop the | |
946 | stack is the address following the copied instruction. We need | |
947 | to make it the address following the original instruction. */ | |
948 | if (i386_call_p (insn)) | |
949 | { | |
950 | ULONGEST esp; | |
951 | ULONGEST retaddr; | |
952 | const ULONGEST retaddr_len = 4; | |
953 | ||
954 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 955 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 956 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 957 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
958 | |
959 | if (debug_displaced) | |
960 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
961 | "displaced: relocated return addr at %s to %s\n", |
962 | paddress (gdbarch, esp), | |
963 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
964 | } |
965 | } | |
dde08ee1 PA |
966 | |
967 | static void | |
968 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
969 | { | |
970 | target_write_memory (*to, buf, len); | |
971 | *to += len; | |
972 | } | |
973 | ||
974 | static void | |
975 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
976 | CORE_ADDR *to, CORE_ADDR oldloc) | |
977 | { | |
978 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
979 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
980 | int offset = 0, rel32, newrel; | |
981 | int insn_length; | |
982 | gdb_byte *insn = buf; | |
983 | ||
984 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
985 | ||
986 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
987 | I386_MAX_INSN_LEN, oldloc); | |
988 | ||
989 | /* Get past the prefixes. */ | |
990 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
991 | ||
992 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
993 | the address pushed being the location where the original call in | |
994 | the user program would return to. */ | |
995 | if (insn[0] == 0xe8) | |
996 | { | |
997 | gdb_byte push_buf[16]; | |
998 | unsigned int ret_addr; | |
999 | ||
1000 | /* Where "ret" in the original code will return to. */ | |
1001 | ret_addr = oldloc + insn_length; | |
1777feb0 | 1002 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 1003 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
1004 | /* Push the push. */ |
1005 | append_insns (to, 5, push_buf); | |
1006 | ||
1007 | /* Convert the relative call to a relative jump. */ | |
1008 | insn[0] = 0xe9; | |
1009 | ||
1010 | /* Adjust the destination offset. */ | |
1011 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1012 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1013 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1014 | ||
1015 | if (debug_displaced) | |
1016 | fprintf_unfiltered (gdb_stdlog, | |
1017 | "Adjusted insn rel32=%s at %s to" | |
1018 | " rel32=%s at %s\n", | |
1019 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1020 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1021 | |
1022 | /* Write the adjusted jump into its displaced location. */ | |
1023 | append_insns (to, 5, insn); | |
1024 | return; | |
1025 | } | |
1026 | ||
1027 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1028 | handled above. */ | |
1029 | if (insn[0] == 0xe9) | |
1030 | offset = 1; | |
1031 | /* Adjust conditional jumps. */ | |
1032 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1033 | offset = 2; | |
1034 | ||
1035 | if (offset) | |
1036 | { | |
1037 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1038 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1039 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1040 | if (debug_displaced) |
1041 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1042 | "Adjusted insn rel32=%s at %s to" |
1043 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1044 | hex_string (rel32), paddress (gdbarch, oldloc), |
1045 | hex_string (newrel), paddress (gdbarch, *to)); | |
1046 | } | |
1047 | ||
1048 | /* Write the adjusted instructions into their displaced | |
1049 | location. */ | |
1050 | append_insns (to, insn_length, buf); | |
1051 | } | |
1052 | ||
fc338970 | 1053 | \f |
acd5c798 MK |
1054 | #ifdef I386_REGNO_TO_SYMMETRY |
1055 | #error "The Sequent Symmetry is no longer supported." | |
1056 | #endif | |
c906108c | 1057 | |
acd5c798 MK |
1058 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1059 | and %esp "belong" to the calling function. Therefore these | |
1060 | registers should be saved if they're going to be modified. */ | |
c906108c | 1061 | |
acd5c798 MK |
1062 | /* The maximum number of saved registers. This should include all |
1063 | registers mentioned above, and %eip. */ | |
a3386186 | 1064 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1065 | |
1066 | struct i386_frame_cache | |
c906108c | 1067 | { |
acd5c798 MK |
1068 | /* Base address. */ |
1069 | CORE_ADDR base; | |
8fbca658 | 1070 | int base_p; |
772562f8 | 1071 | LONGEST sp_offset; |
acd5c798 MK |
1072 | CORE_ADDR pc; |
1073 | ||
fd13a04a AC |
1074 | /* Saved registers. */ |
1075 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1076 | CORE_ADDR saved_sp; |
e0c62198 | 1077 | int saved_sp_reg; |
acd5c798 MK |
1078 | int pc_in_eax; |
1079 | ||
1080 | /* Stack space reserved for local variables. */ | |
1081 | long locals; | |
1082 | }; | |
1083 | ||
1084 | /* Allocate and initialize a frame cache. */ | |
1085 | ||
1086 | static struct i386_frame_cache * | |
fd13a04a | 1087 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1088 | { |
1089 | struct i386_frame_cache *cache; | |
1090 | int i; | |
1091 | ||
1092 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1093 | ||
1094 | /* Base address. */ | |
8fbca658 | 1095 | cache->base_p = 0; |
acd5c798 MK |
1096 | cache->base = 0; |
1097 | cache->sp_offset = -4; | |
1098 | cache->pc = 0; | |
1099 | ||
fd13a04a AC |
1100 | /* Saved registers. We initialize these to -1 since zero is a valid |
1101 | offset (that's where %ebp is supposed to be stored). */ | |
1102 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1103 | cache->saved_regs[i] = -1; | |
acd5c798 | 1104 | cache->saved_sp = 0; |
e0c62198 | 1105 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1106 | cache->pc_in_eax = 0; |
1107 | ||
1108 | /* Frameless until proven otherwise. */ | |
1109 | cache->locals = -1; | |
1110 | ||
1111 | return cache; | |
1112 | } | |
c906108c | 1113 | |
acd5c798 MK |
1114 | /* If the instruction at PC is a jump, return the address of its |
1115 | target. Otherwise, return PC. */ | |
c906108c | 1116 | |
acd5c798 | 1117 | static CORE_ADDR |
e17a4113 | 1118 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1119 | { |
e17a4113 | 1120 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1121 | gdb_byte op; |
acd5c798 MK |
1122 | long delta = 0; |
1123 | int data16 = 0; | |
c906108c | 1124 | |
0865b04a | 1125 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1126 | return pc; |
1127 | ||
acd5c798 | 1128 | if (op == 0x66) |
c906108c | 1129 | { |
c906108c | 1130 | data16 = 1; |
0865b04a YQ |
1131 | |
1132 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1133 | } |
1134 | ||
acd5c798 | 1135 | switch (op) |
c906108c SS |
1136 | { |
1137 | case 0xe9: | |
fc338970 | 1138 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1139 | if (data16) |
1140 | { | |
e17a4113 | 1141 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1142 | |
fc338970 MK |
1143 | /* Include the size of the jmp instruction (including the |
1144 | 0x66 prefix). */ | |
acd5c798 | 1145 | delta += 4; |
c906108c SS |
1146 | } |
1147 | else | |
1148 | { | |
e17a4113 | 1149 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1150 | |
acd5c798 MK |
1151 | /* Include the size of the jmp instruction. */ |
1152 | delta += 5; | |
c906108c SS |
1153 | } |
1154 | break; | |
1155 | case 0xeb: | |
fc338970 | 1156 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1157 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1158 | |
acd5c798 | 1159 | delta += data16 + 2; |
c906108c SS |
1160 | break; |
1161 | } | |
c906108c | 1162 | |
acd5c798 MK |
1163 | return pc + delta; |
1164 | } | |
fc338970 | 1165 | |
acd5c798 MK |
1166 | /* Check whether PC points at a prologue for a function returning a |
1167 | structure or union. If so, it updates CACHE and returns the | |
1168 | address of the first instruction after the code sequence that | |
1169 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1170 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1171 | |
acd5c798 MK |
1172 | static CORE_ADDR |
1173 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1174 | struct i386_frame_cache *cache) | |
c906108c | 1175 | { |
acd5c798 MK |
1176 | /* Functions that return a structure or union start with: |
1177 | ||
1178 | popl %eax 0x58 | |
1179 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1180 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1181 | ||
1182 | (the System V compiler puts out the second `xchg' instruction, | |
1183 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1184 | gets generated). This sequence is used to get the address of the | |
1185 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1186 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1187 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1188 | gdb_byte buf[4]; | |
1189 | gdb_byte op; | |
c906108c | 1190 | |
acd5c798 MK |
1191 | if (current_pc <= pc) |
1192 | return pc; | |
1193 | ||
0865b04a | 1194 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1195 | return pc; |
c906108c | 1196 | |
acd5c798 MK |
1197 | if (op != 0x58) /* popl %eax */ |
1198 | return pc; | |
c906108c | 1199 | |
0865b04a | 1200 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1201 | return pc; |
1202 | ||
acd5c798 MK |
1203 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1204 | return pc; | |
c906108c | 1205 | |
acd5c798 | 1206 | if (current_pc == pc) |
c906108c | 1207 | { |
acd5c798 MK |
1208 | cache->sp_offset += 4; |
1209 | return current_pc; | |
c906108c SS |
1210 | } |
1211 | ||
acd5c798 | 1212 | if (current_pc == pc + 1) |
c906108c | 1213 | { |
acd5c798 MK |
1214 | cache->pc_in_eax = 1; |
1215 | return current_pc; | |
1216 | } | |
1217 | ||
1218 | if (buf[1] == proto1[1]) | |
1219 | return pc + 4; | |
1220 | else | |
1221 | return pc + 5; | |
1222 | } | |
1223 | ||
1224 | static CORE_ADDR | |
1225 | i386_skip_probe (CORE_ADDR pc) | |
1226 | { | |
1227 | /* A function may start with | |
fc338970 | 1228 | |
acd5c798 MK |
1229 | pushl constant |
1230 | call _probe | |
1231 | addl $4, %esp | |
fc338970 | 1232 | |
acd5c798 MK |
1233 | followed by |
1234 | ||
1235 | pushl %ebp | |
fc338970 | 1236 | |
acd5c798 | 1237 | etc. */ |
63c0089f MK |
1238 | gdb_byte buf[8]; |
1239 | gdb_byte op; | |
fc338970 | 1240 | |
0865b04a | 1241 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1242 | return pc; |
acd5c798 MK |
1243 | |
1244 | if (op == 0x68 || op == 0x6a) | |
1245 | { | |
1246 | int delta; | |
c906108c | 1247 | |
acd5c798 MK |
1248 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1249 | four-byte operand, depending on the opcode. */ | |
c906108c | 1250 | if (op == 0x68) |
acd5c798 | 1251 | delta = 5; |
c906108c | 1252 | else |
acd5c798 | 1253 | delta = 2; |
c906108c | 1254 | |
acd5c798 MK |
1255 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1256 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1257 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1258 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1259 | pc += delta + sizeof (buf); |
c906108c SS |
1260 | } |
1261 | ||
acd5c798 MK |
1262 | return pc; |
1263 | } | |
1264 | ||
92dd43fa MK |
1265 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1266 | stack pointer. Check whether PC points to such code, and update | |
1267 | CACHE accordingly. Return the first instruction after the code | |
1268 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1269 | recognize the code, return PC. */ | |
1270 | ||
1271 | static CORE_ADDR | |
1272 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1273 | struct i386_frame_cache *cache) | |
1274 | { | |
e0c62198 L |
1275 | /* There are 2 code sequences to re-align stack before the frame |
1276 | gets set up: | |
1277 | ||
1278 | 1. Use a caller-saved saved register: | |
1279 | ||
1280 | leal 4(%esp), %reg | |
1281 | andl $-XXX, %esp | |
1282 | pushl -4(%reg) | |
1283 | ||
1284 | 2. Use a callee-saved saved register: | |
1285 | ||
1286 | pushl %reg | |
1287 | leal 8(%esp), %reg | |
1288 | andl $-XXX, %esp | |
1289 | pushl -4(%reg) | |
1290 | ||
1291 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1292 | ||
1293 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1294 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1295 | */ | |
1296 | ||
1297 | gdb_byte buf[14]; | |
1298 | int reg; | |
1299 | int offset, offset_and; | |
1300 | static int regnums[8] = { | |
1301 | I386_EAX_REGNUM, /* %eax */ | |
1302 | I386_ECX_REGNUM, /* %ecx */ | |
1303 | I386_EDX_REGNUM, /* %edx */ | |
1304 | I386_EBX_REGNUM, /* %ebx */ | |
1305 | I386_ESP_REGNUM, /* %esp */ | |
1306 | I386_EBP_REGNUM, /* %ebp */ | |
1307 | I386_ESI_REGNUM, /* %esi */ | |
1308 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1309 | }; |
92dd43fa | 1310 | |
0865b04a | 1311 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1312 | return pc; |
1313 | ||
1314 | /* Check caller-saved saved register. The first instruction has | |
1315 | to be "leal 4(%esp), %reg". */ | |
1316 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1317 | { | |
1318 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1319 | if ((buf[1] & 0xc7) != 0x44) | |
1320 | return pc; | |
1321 | ||
1322 | /* REG has register number. */ | |
1323 | reg = (buf[1] >> 3) & 7; | |
1324 | offset = 4; | |
1325 | } | |
1326 | else | |
1327 | { | |
1328 | /* Check callee-saved saved register. The first instruction | |
1329 | has to be "pushl %reg". */ | |
1330 | if ((buf[0] & 0xf8) != 0x50) | |
1331 | return pc; | |
1332 | ||
1333 | /* Get register. */ | |
1334 | reg = buf[0] & 0x7; | |
1335 | ||
1336 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1337 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1338 | return pc; | |
1339 | ||
1340 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1341 | if ((buf[2] & 0xc7) != 0x44) | |
1342 | return pc; | |
1343 | ||
1344 | /* REG has register number. Registers in pushl and leal have to | |
1345 | be the same. */ | |
1346 | if (reg != ((buf[2] >> 3) & 7)) | |
1347 | return pc; | |
1348 | ||
1349 | offset = 5; | |
1350 | } | |
1351 | ||
1352 | /* Rigister can't be %esp nor %ebp. */ | |
1353 | if (reg == 4 || reg == 5) | |
1354 | return pc; | |
1355 | ||
1356 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1357 | if (buf[offset + 1] != 0xe4 | |
1358 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1359 | return pc; | |
1360 | ||
1361 | offset_and = offset; | |
1362 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1363 | ||
1364 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1365 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1366 | if (buf[offset] != 0xff | |
1367 | || buf[offset + 2] != 0xfc | |
1368 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1369 | return pc; | |
1370 | ||
1371 | /* R/M has register. Registers in leal and pushl have to be the | |
1372 | same. */ | |
1373 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1374 | return pc; |
1375 | ||
e0c62198 L |
1376 | if (current_pc > pc + offset_and) |
1377 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1378 | |
325fac50 | 1379 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1380 | } |
1381 | ||
37bdc87e | 1382 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1383 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1384 | |
1385 | /* Instruction description. */ | |
1386 | struct i386_insn | |
1387 | { | |
1388 | size_t len; | |
237fc4c9 PA |
1389 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1390 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1391 | }; |
1392 | ||
a3fcb948 | 1393 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1394 | |
a3fcb948 JG |
1395 | static int |
1396 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1397 | { |
63c0089f | 1398 | gdb_byte op; |
37bdc87e | 1399 | |
0865b04a | 1400 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1401 | return 0; |
37bdc87e | 1402 | |
a3fcb948 | 1403 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1404 | { |
a3fcb948 JG |
1405 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1406 | int insn_matched = 1; | |
1407 | size_t i; | |
37bdc87e | 1408 | |
a3fcb948 JG |
1409 | gdb_assert (pattern.len > 1); |
1410 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1411 | |
0865b04a | 1412 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1413 | return 0; |
613e8135 | 1414 | |
a3fcb948 JG |
1415 | for (i = 1; i < pattern.len; i++) |
1416 | { | |
1417 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1418 | insn_matched = 0; | |
37bdc87e | 1419 | } |
a3fcb948 JG |
1420 | return insn_matched; |
1421 | } | |
1422 | return 0; | |
1423 | } | |
1424 | ||
1425 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1426 | the first instruction description that matches. Otherwise, return | |
1427 | NULL. */ | |
1428 | ||
1429 | static struct i386_insn * | |
1430 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1431 | { | |
1432 | struct i386_insn *pattern; | |
1433 | ||
1434 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1435 | { | |
1436 | if (i386_match_pattern (pc, *pattern)) | |
1437 | return pattern; | |
37bdc87e MK |
1438 | } |
1439 | ||
1440 | return NULL; | |
1441 | } | |
1442 | ||
a3fcb948 JG |
1443 | /* Return whether PC points inside a sequence of instructions that |
1444 | matches INSN_PATTERNS. */ | |
1445 | ||
1446 | static int | |
1447 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1448 | { | |
1449 | CORE_ADDR current_pc; | |
1450 | int ix, i; | |
a3fcb948 JG |
1451 | struct i386_insn *insn; |
1452 | ||
1453 | insn = i386_match_insn (pc, insn_patterns); | |
1454 | if (insn == NULL) | |
1455 | return 0; | |
1456 | ||
8bbdd3f4 | 1457 | current_pc = pc; |
a3fcb948 JG |
1458 | ix = insn - insn_patterns; |
1459 | for (i = ix - 1; i >= 0; i--) | |
1460 | { | |
8bbdd3f4 MK |
1461 | current_pc -= insn_patterns[i].len; |
1462 | ||
a3fcb948 JG |
1463 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1464 | return 0; | |
a3fcb948 JG |
1465 | } |
1466 | ||
1467 | current_pc = pc + insn->len; | |
1468 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1469 | { | |
1470 | if (!i386_match_pattern (current_pc, *insn)) | |
1471 | return 0; | |
1472 | ||
1473 | current_pc += insn->len; | |
1474 | } | |
1475 | ||
1476 | return 1; | |
1477 | } | |
1478 | ||
37bdc87e MK |
1479 | /* Some special instructions that might be migrated by GCC into the |
1480 | part of the prologue that sets up the new stack frame. Because the | |
1481 | stack frame hasn't been setup yet, no registers have been saved | |
1482 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1483 | touched. */ | |
1484 | ||
1485 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1486 | { | |
1777feb0 | 1487 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1488 | |
1489 | ??? Should we handle 16-bit operand-sizes here? */ | |
1490 | ||
1491 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1492 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1493 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1494 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1495 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1496 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1497 | { 5, { 0xb8 }, { 0xfe } }, | |
1498 | /* `movl imm32, %edx' */ | |
1499 | { 5, { 0xba }, { 0xff } }, | |
1500 | ||
1501 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1502 | encoding for `mov m32, %eax'. | |
1503 | ||
1504 | ??? Should we handle SIB adressing here? | |
1505 | ??? Should we handle 16-bit operand-sizes here? */ | |
1506 | ||
1507 | /* `movl m32, %eax' */ | |
1508 | { 5, { 0xa1 }, { 0xff } }, | |
1509 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1510 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1511 | /* `movl m32, %edx' */ | |
1512 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1513 | ||
1514 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1515 | Because of the symmetry, there are actually two ways to encode | |
1516 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1517 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1518 | ||
1519 | /* `subl %eax, %eax' */ | |
1520 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1521 | /* `subl %ecx, %ecx' */ | |
1522 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1523 | /* `subl %edx, %edx' */ | |
1524 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1525 | /* `xorl %eax, %eax' */ | |
1526 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1527 | /* `xorl %ecx, %ecx' */ | |
1528 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1529 | /* `xorl %edx, %edx' */ | |
1530 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1531 | { 0 } | |
1532 | }; | |
1533 | ||
e11481da PM |
1534 | |
1535 | /* Check whether PC points to a no-op instruction. */ | |
1536 | static CORE_ADDR | |
1537 | i386_skip_noop (CORE_ADDR pc) | |
1538 | { | |
1539 | gdb_byte op; | |
1540 | int check = 1; | |
1541 | ||
0865b04a | 1542 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1543 | return pc; |
e11481da PM |
1544 | |
1545 | while (check) | |
1546 | { | |
1547 | check = 0; | |
1548 | /* Ignore `nop' instruction. */ | |
1549 | if (op == 0x90) | |
1550 | { | |
1551 | pc += 1; | |
0865b04a | 1552 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1553 | return pc; |
e11481da PM |
1554 | check = 1; |
1555 | } | |
1556 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1557 | Microsoft system dlls often start with | |
1558 | a `mov %edi,%edi' instruction. | |
1559 | The 5 bytes before the function start are | |
1560 | filled with `nop' instructions. | |
1561 | This pattern can be used for hot-patching: | |
1562 | The `mov %edi, %edi' instruction can be replaced by a | |
1563 | near jump to the location of the 5 `nop' instructions | |
1564 | which can be replaced by a 32-bit jump to anywhere | |
1565 | in the 32-bit address space. */ | |
1566 | ||
1567 | else if (op == 0x8b) | |
1568 | { | |
0865b04a | 1569 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1570 | return pc; |
1571 | ||
e11481da PM |
1572 | if (op == 0xff) |
1573 | { | |
1574 | pc += 2; | |
0865b04a | 1575 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1576 | return pc; |
1577 | ||
e11481da PM |
1578 | check = 1; |
1579 | } | |
1580 | } | |
1581 | } | |
1582 | return pc; | |
1583 | } | |
1584 | ||
acd5c798 MK |
1585 | /* Check whether PC points at a code that sets up a new stack frame. |
1586 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1587 | instruction after the sequence that sets up the frame or LIMIT, |
1588 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1589 | |
1590 | static CORE_ADDR | |
e17a4113 UW |
1591 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1592 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1593 | struct i386_frame_cache *cache) |
1594 | { | |
e17a4113 | 1595 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1596 | struct i386_insn *insn; |
63c0089f | 1597 | gdb_byte op; |
26604a34 | 1598 | int skip = 0; |
acd5c798 | 1599 | |
37bdc87e MK |
1600 | if (limit <= pc) |
1601 | return limit; | |
acd5c798 | 1602 | |
0865b04a | 1603 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1604 | return pc; |
acd5c798 | 1605 | |
c906108c | 1606 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1607 | { |
acd5c798 MK |
1608 | /* Take into account that we've executed the `pushl %ebp' that |
1609 | starts this instruction sequence. */ | |
fd13a04a | 1610 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1611 | cache->sp_offset += 4; |
37bdc87e | 1612 | pc++; |
acd5c798 MK |
1613 | |
1614 | /* If that's all, return now. */ | |
37bdc87e MK |
1615 | if (limit <= pc) |
1616 | return limit; | |
26604a34 | 1617 | |
b4632131 | 1618 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1619 | GCC into the prologue and skip them. At this point in the |
1620 | prologue, code should only touch the scratch registers %eax, | |
1621 | %ecx and %edx, so while the number of posibilities is sheer, | |
1622 | it is limited. | |
5daa5b4e | 1623 | |
26604a34 MK |
1624 | Make sure we only skip these instructions if we later see the |
1625 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1626 | while (pc + skip < limit) |
26604a34 | 1627 | { |
37bdc87e MK |
1628 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1629 | if (insn == NULL) | |
1630 | break; | |
b4632131 | 1631 | |
37bdc87e | 1632 | skip += insn->len; |
26604a34 MK |
1633 | } |
1634 | ||
37bdc87e MK |
1635 | /* If that's all, return now. */ |
1636 | if (limit <= pc + skip) | |
1637 | return limit; | |
1638 | ||
0865b04a | 1639 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1640 | return pc + skip; |
37bdc87e | 1641 | |
30f8135b YQ |
1642 | /* The i386 prologue looks like |
1643 | ||
1644 | push %ebp | |
1645 | mov %esp,%ebp | |
1646 | sub $0x10,%esp | |
1647 | ||
1648 | and a different prologue can be generated for atom. | |
1649 | ||
1650 | push %ebp | |
1651 | lea (%esp),%ebp | |
1652 | lea -0x10(%esp),%esp | |
1653 | ||
1654 | We handle both of them here. */ | |
1655 | ||
acd5c798 | 1656 | switch (op) |
c906108c | 1657 | { |
30f8135b | 1658 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1659 | case 0x8b: |
0865b04a | 1660 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1661 | != 0xec) |
37bdc87e | 1662 | return pc; |
30f8135b | 1663 | pc += (skip + 2); |
c906108c SS |
1664 | break; |
1665 | case 0x89: | |
0865b04a | 1666 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1667 | != 0xe5) |
37bdc87e | 1668 | return pc; |
30f8135b YQ |
1669 | pc += (skip + 2); |
1670 | break; | |
1671 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1672 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1673 | != 0x242c) |
1674 | return pc; | |
1675 | pc += (skip + 3); | |
c906108c SS |
1676 | break; |
1677 | default: | |
37bdc87e | 1678 | return pc; |
c906108c | 1679 | } |
acd5c798 | 1680 | |
26604a34 MK |
1681 | /* OK, we actually have a frame. We just don't know how large |
1682 | it is yet. Set its size to zero. We'll adjust it if | |
1683 | necessary. We also now commit to skipping the special | |
1684 | instructions mentioned before. */ | |
acd5c798 MK |
1685 | cache->locals = 0; |
1686 | ||
1687 | /* If that's all, return now. */ | |
37bdc87e MK |
1688 | if (limit <= pc) |
1689 | return limit; | |
acd5c798 | 1690 | |
fc338970 MK |
1691 | /* Check for stack adjustment |
1692 | ||
acd5c798 | 1693 | subl $XXX, %esp |
30f8135b YQ |
1694 | or |
1695 | lea -XXX(%esp),%esp | |
fc338970 | 1696 | |
fd35795f | 1697 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1698 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1699 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1700 | return pc; |
c906108c SS |
1701 | if (op == 0x83) |
1702 | { | |
fd35795f | 1703 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1704 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1705 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1706 | return pc; |
acd5c798 | 1707 | |
37bdc87e MK |
1708 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1709 | make sense to be negative). */ | |
0865b04a | 1710 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1711 | return pc + 3; |
c906108c SS |
1712 | } |
1713 | else if (op == 0x81) | |
1714 | { | |
fd35795f | 1715 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1716 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1717 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1718 | return pc; |
acd5c798 | 1719 | |
fd35795f | 1720 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1721 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1722 | return pc + 6; |
c906108c | 1723 | } |
30f8135b YQ |
1724 | else if (op == 0x8d) |
1725 | { | |
1726 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1727 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1728 | return pc; |
1729 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1730 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1731 | return pc + 4; |
1732 | } | |
c906108c SS |
1733 | else |
1734 | { | |
30f8135b | 1735 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1736 | return pc; |
c906108c SS |
1737 | } |
1738 | } | |
37bdc87e | 1739 | else if (op == 0xc8) /* enter */ |
c906108c | 1740 | { |
0865b04a | 1741 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1742 | return pc + 4; |
c906108c | 1743 | } |
21d0e8a4 | 1744 | |
acd5c798 | 1745 | return pc; |
21d0e8a4 MK |
1746 | } |
1747 | ||
acd5c798 MK |
1748 | /* Check whether PC points at code that saves registers on the stack. |
1749 | If so, it updates CACHE and returns the address of the first | |
1750 | instruction after the register saves or CURRENT_PC, whichever is | |
1751 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1752 | |
1753 | static CORE_ADDR | |
acd5c798 MK |
1754 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1755 | struct i386_frame_cache *cache) | |
6bff26de | 1756 | { |
99ab4326 | 1757 | CORE_ADDR offset = 0; |
63c0089f | 1758 | gdb_byte op; |
99ab4326 | 1759 | int i; |
c0d1d883 | 1760 | |
99ab4326 MK |
1761 | if (cache->locals > 0) |
1762 | offset -= cache->locals; | |
1763 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1764 | { | |
0865b04a | 1765 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1766 | return pc; |
99ab4326 MK |
1767 | if (op < 0x50 || op > 0x57) |
1768 | break; | |
0d17c81d | 1769 | |
99ab4326 MK |
1770 | offset -= 4; |
1771 | cache->saved_regs[op - 0x50] = offset; | |
1772 | cache->sp_offset += 4; | |
1773 | pc++; | |
6bff26de MK |
1774 | } |
1775 | ||
acd5c798 | 1776 | return pc; |
22797942 AC |
1777 | } |
1778 | ||
acd5c798 MK |
1779 | /* Do a full analysis of the prologue at PC and update CACHE |
1780 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1781 | address where the analysis stopped. | |
ed84f6c1 | 1782 | |
fc338970 MK |
1783 | We handle these cases: |
1784 | ||
1785 | The startup sequence can be at the start of the function, or the | |
1786 | function can start with a branch to startup code at the end. | |
1787 | ||
1788 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1789 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1790 | once used in the System V compiler). | |
1791 | ||
1792 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1793 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1794 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1795 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1796 | |
1797 | Next, the registers used by this function are pushed. With the | |
1798 | System V compiler they will always be in the order: %edi, %esi, | |
1799 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1800 | restore %eax); however, the code below is willing to see the pushes | |
1801 | in any order, and will handle up to 8 of them. | |
1802 | ||
1803 | If the setup sequence is at the end of the function, then the next | |
1804 | instruction will be a branch back to the start. */ | |
c906108c | 1805 | |
acd5c798 | 1806 | static CORE_ADDR |
e17a4113 UW |
1807 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1808 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1809 | struct i386_frame_cache *cache) |
c906108c | 1810 | { |
e11481da | 1811 | pc = i386_skip_noop (pc); |
e17a4113 | 1812 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1813 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1814 | pc = i386_skip_probe (pc); | |
92dd43fa | 1815 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1816 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1817 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1818 | } |
1819 | ||
fc338970 | 1820 | /* Return PC of first real instruction. */ |
c906108c | 1821 | |
3a1e71e3 | 1822 | static CORE_ADDR |
6093d2eb | 1823 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1824 | { |
e17a4113 UW |
1825 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1826 | ||
63c0089f | 1827 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1828 | { |
1829 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1830 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1831 | }; |
acd5c798 MK |
1832 | struct i386_frame_cache cache; |
1833 | CORE_ADDR pc; | |
63c0089f | 1834 | gdb_byte op; |
acd5c798 | 1835 | int i; |
56bf0743 | 1836 | CORE_ADDR func_addr; |
4e879fc2 | 1837 | |
56bf0743 KB |
1838 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1839 | { | |
1840 | CORE_ADDR post_prologue_pc | |
1841 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1842 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
1843 | |
1844 | /* Clang always emits a line note before the prologue and another | |
1845 | one after. We trust clang to emit usable line notes. */ | |
1846 | if (post_prologue_pc | |
43f3e411 DE |
1847 | && (cust != NULL |
1848 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 1849 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
325fac50 | 1850 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1851 | } |
1852 | ||
e0f33b1f | 1853 | cache.locals = -1; |
e17a4113 | 1854 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1855 | if (cache.locals < 0) |
1856 | return start_pc; | |
c5aa993b | 1857 | |
acd5c798 | 1858 | /* Found valid frame setup. */ |
c906108c | 1859 | |
fc338970 MK |
1860 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1861 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1862 | %ebx: |
1863 | ||
fc338970 MK |
1864 | call 0x0 |
1865 | popl %ebx | |
1866 | movl %ebx,x(%ebp) (optional) | |
1867 | addl y,%ebx | |
1868 | ||
c906108c SS |
1869 | This code is with the rest of the prologue (at the end of the |
1870 | function), so we have to skip it to get to the first real | |
1871 | instruction at the start of the function. */ | |
c5aa993b | 1872 | |
c906108c SS |
1873 | for (i = 0; i < 6; i++) |
1874 | { | |
0865b04a | 1875 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1876 | return pc; |
1877 | ||
c5aa993b | 1878 | if (pic_pat[i] != op) |
c906108c SS |
1879 | break; |
1880 | } | |
1881 | if (i == 6) | |
1882 | { | |
acd5c798 MK |
1883 | int delta = 6; |
1884 | ||
0865b04a | 1885 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1886 | return pc; |
c906108c | 1887 | |
c5aa993b | 1888 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1889 | { |
0865b04a | 1890 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1891 | |
fc338970 | 1892 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1893 | delta += 3; |
fc338970 | 1894 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1895 | delta += 6; |
fc338970 | 1896 | else /* Unexpected instruction. */ |
acd5c798 MK |
1897 | delta = 0; |
1898 | ||
0865b04a | 1899 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1900 | return pc; |
c906108c | 1901 | } |
acd5c798 | 1902 | |
c5aa993b | 1903 | /* addl y,%ebx */ |
acd5c798 | 1904 | if (delta > 0 && op == 0x81 |
0865b04a | 1905 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1906 | == 0xc3) |
c906108c | 1907 | { |
acd5c798 | 1908 | pc += delta + 6; |
c906108c SS |
1909 | } |
1910 | } | |
c5aa993b | 1911 | |
e63bbc88 MK |
1912 | /* If the function starts with a branch (to startup code at the end) |
1913 | the last instruction should bring us back to the first | |
1914 | instruction of the real code. */ | |
e17a4113 UW |
1915 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1916 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1917 | |
1918 | return pc; | |
c906108c SS |
1919 | } |
1920 | ||
4309257c PM |
1921 | /* Check that the code pointed to by PC corresponds to a call to |
1922 | __main, skip it if so. Return PC otherwise. */ | |
1923 | ||
1924 | CORE_ADDR | |
1925 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1926 | { | |
e17a4113 | 1927 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1928 | gdb_byte op; |
1929 | ||
0865b04a | 1930 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1931 | return pc; |
4309257c PM |
1932 | if (op == 0xe8) |
1933 | { | |
1934 | gdb_byte buf[4]; | |
1935 | ||
0865b04a | 1936 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1937 | { |
1938 | /* Make sure address is computed correctly as a 32bit | |
1939 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1940 | struct bound_minimal_symbol s; |
e17a4113 | 1941 | CORE_ADDR call_dest; |
4309257c | 1942 | |
e17a4113 | 1943 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1944 | call_dest = call_dest & 0xffffffffU; |
1945 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1946 | if (s.minsym != NULL |
efd66ac6 TT |
1947 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1948 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1949 | pc += 5; |
1950 | } | |
1951 | } | |
1952 | ||
1953 | return pc; | |
1954 | } | |
1955 | ||
acd5c798 | 1956 | /* This function is 64-bit safe. */ |
93924b6b | 1957 | |
acd5c798 MK |
1958 | static CORE_ADDR |
1959 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1960 | { |
63c0089f | 1961 | gdb_byte buf[8]; |
acd5c798 | 1962 | |
875f8d0e | 1963 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1964 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1965 | } |
acd5c798 | 1966 | \f |
93924b6b | 1967 | |
acd5c798 | 1968 | /* Normal frames. */ |
c5aa993b | 1969 | |
8fbca658 PA |
1970 | static void |
1971 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1972 | struct i386_frame_cache *cache) | |
a7769679 | 1973 | { |
e17a4113 UW |
1974 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1975 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1976 | gdb_byte buf[4]; |
acd5c798 MK |
1977 | int i; |
1978 | ||
8fbca658 | 1979 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1980 | |
1981 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1982 | which holds the base address for the current stack frame. | |
1983 | However, for functions that don't need it, the frame pointer is | |
1984 | optional. For these "frameless" functions the frame pointer is | |
1985 | actually the frame pointer of the calling frame. Signal | |
1986 | trampolines are just a special case of a "frameless" function. | |
1987 | They (usually) share their frame pointer with the frame that was | |
1988 | in progress when the signal occurred. */ | |
1989 | ||
10458914 | 1990 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1991 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1992 | if (cache->base == 0) |
620fa63a PA |
1993 | { |
1994 | cache->base_p = 1; | |
1995 | return; | |
1996 | } | |
acd5c798 MK |
1997 | |
1998 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1999 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2000 | |
acd5c798 | 2001 | if (cache->pc != 0) |
e17a4113 UW |
2002 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2003 | cache); | |
acd5c798 MK |
2004 | |
2005 | if (cache->locals < 0) | |
2006 | { | |
2007 | /* We didn't find a valid frame, which means that CACHE->base | |
2008 | currently holds the frame pointer for our calling frame. If | |
2009 | we're at the start of a function, or somewhere half-way its | |
2010 | prologue, the function's frame probably hasn't been fully | |
2011 | setup yet. Try to reconstruct the base address for the stack | |
2012 | frame by looking at the stack pointer. For truly "frameless" | |
2013 | functions this might work too. */ | |
2014 | ||
e0c62198 | 2015 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2016 | { |
8fbca658 PA |
2017 | /* Saved stack pointer has been saved. */ |
2018 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2019 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2020 | ||
92dd43fa MK |
2021 | /* We're halfway aligning the stack. */ |
2022 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2023 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2024 | ||
2025 | /* This will be added back below. */ | |
2026 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2027 | } | |
7618e12b | 2028 | else if (cache->pc != 0 |
0865b04a | 2029 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2030 | { |
7618e12b DJ |
2031 | /* We're in a known function, but did not find a frame |
2032 | setup. Assume that the function does not use %ebp. | |
2033 | Alternatively, we may have jumped to an invalid | |
2034 | address; in that case there is definitely no new | |
2035 | frame in %ebp. */ | |
10458914 | 2036 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2037 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2038 | + cache->sp_offset; | |
92dd43fa | 2039 | } |
7618e12b DJ |
2040 | else |
2041 | /* We're in an unknown function. We could not find the start | |
2042 | of the function to analyze the prologue; our best option is | |
2043 | to assume a typical frame layout with the caller's %ebp | |
2044 | saved. */ | |
2045 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2046 | } |
2047 | ||
8fbca658 PA |
2048 | if (cache->saved_sp_reg != -1) |
2049 | { | |
2050 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2051 | register may be unavailable). */ | |
2052 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2053 | && deprecated_frame_register_read (this_frame, |
2054 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2055 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2056 | } | |
acd5c798 MK |
2057 | /* Now that we have the base address for the stack frame we can |
2058 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2059 | else if (cache->saved_sp == 0) |
92dd43fa | 2060 | cache->saved_sp = cache->base + 8; |
a7769679 | 2061 | |
acd5c798 MK |
2062 | /* Adjust all the saved registers such that they contain addresses |
2063 | instead of offsets. */ | |
2064 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2065 | if (cache->saved_regs[i] != -1) |
2066 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2067 | |
8fbca658 PA |
2068 | cache->base_p = 1; |
2069 | } | |
2070 | ||
2071 | static struct i386_frame_cache * | |
2072 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2073 | { | |
8fbca658 PA |
2074 | struct i386_frame_cache *cache; |
2075 | ||
2076 | if (*this_cache) | |
9a3c8263 | 2077 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2078 | |
2079 | cache = i386_alloc_frame_cache (); | |
2080 | *this_cache = cache; | |
2081 | ||
492d29ea | 2082 | TRY |
8fbca658 PA |
2083 | { |
2084 | i386_frame_cache_1 (this_frame, cache); | |
2085 | } | |
492d29ea | 2086 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2087 | { |
2088 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2089 | throw_exception (ex); | |
2090 | } | |
492d29ea | 2091 | END_CATCH |
8fbca658 | 2092 | |
acd5c798 | 2093 | return cache; |
a7769679 MK |
2094 | } |
2095 | ||
3a1e71e3 | 2096 | static void |
10458914 | 2097 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2098 | struct frame_id *this_id) |
c906108c | 2099 | { |
10458914 | 2100 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2101 | |
5ce0145d PA |
2102 | if (!cache->base_p) |
2103 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2104 | else if (cache->base == 0) | |
2105 | { | |
2106 | /* This marks the outermost frame. */ | |
2107 | } | |
2108 | else | |
2109 | { | |
2110 | /* See the end of i386_push_dummy_call. */ | |
2111 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2112 | } | |
acd5c798 MK |
2113 | } |
2114 | ||
8fbca658 PA |
2115 | static enum unwind_stop_reason |
2116 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2117 | void **this_cache) | |
2118 | { | |
2119 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2120 | ||
2121 | if (!cache->base_p) | |
2122 | return UNWIND_UNAVAILABLE; | |
2123 | ||
2124 | /* This marks the outermost frame. */ | |
2125 | if (cache->base == 0) | |
2126 | return UNWIND_OUTERMOST; | |
2127 | ||
2128 | return UNWIND_NO_REASON; | |
2129 | } | |
2130 | ||
10458914 DJ |
2131 | static struct value * |
2132 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2133 | int regnum) | |
acd5c798 | 2134 | { |
10458914 | 2135 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2136 | |
2137 | gdb_assert (regnum >= 0); | |
2138 | ||
2139 | /* The System V ABI says that: | |
2140 | ||
2141 | "The flags register contains the system flags, such as the | |
2142 | direction flag and the carry flag. The direction flag must be | |
2143 | set to the forward (that is, zero) direction before entry and | |
2144 | upon exit from a function. Other user flags have no specified | |
2145 | role in the standard calling sequence and are not preserved." | |
2146 | ||
2147 | To guarantee the "upon exit" part of that statement we fake a | |
2148 | saved flags register that has its direction flag cleared. | |
2149 | ||
2150 | Note that GCC doesn't seem to rely on the fact that the direction | |
2151 | flag is cleared after a function return; it always explicitly | |
2152 | clears the flag before operations where it matters. | |
2153 | ||
2154 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2155 | right thing to do. The way we fake the flags register here makes | |
2156 | it impossible to change it. */ | |
2157 | ||
2158 | if (regnum == I386_EFLAGS_REGNUM) | |
2159 | { | |
10458914 | 2160 | ULONGEST val; |
c5aa993b | 2161 | |
10458914 DJ |
2162 | val = get_frame_register_unsigned (this_frame, regnum); |
2163 | val &= ~(1 << 10); | |
2164 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2165 | } |
1211c4e4 | 2166 | |
acd5c798 | 2167 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2168 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2169 | |
fcf250e2 UW |
2170 | if (regnum == I386_ESP_REGNUM |
2171 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2172 | { |
2173 | /* If the SP has been saved, but we don't know where, then this | |
2174 | means that SAVED_SP_REG register was found unavailable back | |
2175 | when we built the cache. */ | |
fcf250e2 | 2176 | if (cache->saved_sp == 0) |
8fbca658 PA |
2177 | return frame_unwind_got_register (this_frame, regnum, |
2178 | cache->saved_sp_reg); | |
2179 | else | |
2180 | return frame_unwind_got_constant (this_frame, regnum, | |
2181 | cache->saved_sp); | |
2182 | } | |
acd5c798 | 2183 | |
fd13a04a | 2184 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2185 | return frame_unwind_got_memory (this_frame, regnum, |
2186 | cache->saved_regs[regnum]); | |
fd13a04a | 2187 | |
10458914 | 2188 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2189 | } |
2190 | ||
2191 | static const struct frame_unwind i386_frame_unwind = | |
2192 | { | |
2193 | NORMAL_FRAME, | |
8fbca658 | 2194 | i386_frame_unwind_stop_reason, |
acd5c798 | 2195 | i386_frame_this_id, |
10458914 DJ |
2196 | i386_frame_prev_register, |
2197 | NULL, | |
2198 | default_frame_sniffer | |
acd5c798 | 2199 | }; |
06da04c6 MS |
2200 | |
2201 | /* Normal frames, but in a function epilogue. */ | |
2202 | ||
c9cf6e20 MG |
2203 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2204 | ||
2205 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2206 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2207 | the function's stack frame. */ | |
2208 | ||
2209 | static int | |
c9cf6e20 | 2210 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2211 | { |
2212 | gdb_byte insn; | |
43f3e411 | 2213 | struct compunit_symtab *cust; |
e0d00bc7 | 2214 | |
43f3e411 DE |
2215 | cust = find_pc_compunit_symtab (pc); |
2216 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2217 | return 0; |
06da04c6 MS |
2218 | |
2219 | if (target_read_memory (pc, &insn, 1)) | |
2220 | return 0; /* Can't read memory at pc. */ | |
2221 | ||
2222 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2223 | return 0; | |
2224 | ||
2225 | return 1; | |
2226 | } | |
2227 | ||
2228 | static int | |
2229 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2230 | struct frame_info *this_frame, | |
2231 | void **this_prologue_cache) | |
2232 | { | |
2233 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2234 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2235 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2236 | else |
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | static struct i386_frame_cache * | |
2241 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2242 | { | |
06da04c6 | 2243 | struct i386_frame_cache *cache; |
0d6c2135 | 2244 | CORE_ADDR sp; |
06da04c6 MS |
2245 | |
2246 | if (*this_cache) | |
9a3c8263 | 2247 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2248 | |
2249 | cache = i386_alloc_frame_cache (); | |
2250 | *this_cache = cache; | |
2251 | ||
492d29ea | 2252 | TRY |
8fbca658 | 2253 | { |
0d6c2135 | 2254 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2255 | |
0d6c2135 MK |
2256 | /* At this point the stack looks as if we just entered the |
2257 | function, with the return address at the top of the | |
2258 | stack. */ | |
2259 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2260 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2261 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2262 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2263 | |
8fbca658 PA |
2264 | cache->base_p = 1; |
2265 | } | |
492d29ea | 2266 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2267 | { |
2268 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2269 | throw_exception (ex); | |
2270 | } | |
492d29ea | 2271 | END_CATCH |
06da04c6 MS |
2272 | |
2273 | return cache; | |
2274 | } | |
2275 | ||
8fbca658 PA |
2276 | static enum unwind_stop_reason |
2277 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2278 | void **this_cache) | |
2279 | { | |
0d6c2135 MK |
2280 | struct i386_frame_cache *cache = |
2281 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2282 | |
2283 | if (!cache->base_p) | |
2284 | return UNWIND_UNAVAILABLE; | |
2285 | ||
2286 | return UNWIND_NO_REASON; | |
2287 | } | |
2288 | ||
06da04c6 MS |
2289 | static void |
2290 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2291 | void **this_cache, | |
2292 | struct frame_id *this_id) | |
2293 | { | |
0d6c2135 MK |
2294 | struct i386_frame_cache *cache = |
2295 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2296 | |
8fbca658 | 2297 | if (!cache->base_p) |
5ce0145d PA |
2298 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2299 | else | |
2300 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2301 | } |
2302 | ||
0d6c2135 MK |
2303 | static struct value * |
2304 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2305 | void **this_cache, int regnum) | |
2306 | { | |
2307 | /* Make sure we've initialized the cache. */ | |
2308 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2309 | ||
2310 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2311 | } | |
2312 | ||
06da04c6 MS |
2313 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2314 | { | |
2315 | NORMAL_FRAME, | |
8fbca658 | 2316 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2317 | i386_epilogue_frame_this_id, |
0d6c2135 | 2318 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2319 | NULL, |
2320 | i386_epilogue_frame_sniffer | |
2321 | }; | |
acd5c798 MK |
2322 | \f |
2323 | ||
a3fcb948 JG |
2324 | /* Stack-based trampolines. */ |
2325 | ||
2326 | /* These trampolines are used on cross x86 targets, when taking the | |
2327 | address of a nested function. When executing these trampolines, | |
2328 | no stack frame is set up, so we are in a similar situation as in | |
2329 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2330 | ||
2331 | /* Static chain passed in register. */ | |
2332 | ||
2333 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2334 | { | |
2335 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2336 | { 5, { 0xb8 }, { 0xfe } }, | |
2337 | ||
2338 | /* `jmp imm32' */ | |
2339 | { 5, { 0xe9 }, { 0xff } }, | |
2340 | ||
2341 | {0} | |
2342 | }; | |
2343 | ||
2344 | /* Static chain passed on stack (when regparm=3). */ | |
2345 | ||
2346 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2347 | { | |
2348 | /* `push imm32' */ | |
2349 | { 5, { 0x68 }, { 0xff } }, | |
2350 | ||
2351 | /* `jmp imm32' */ | |
2352 | { 5, { 0xe9 }, { 0xff } }, | |
2353 | ||
2354 | {0} | |
2355 | }; | |
2356 | ||
2357 | /* Return whether PC points inside a stack trampoline. */ | |
2358 | ||
2359 | static int | |
6df81a63 | 2360 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2361 | { |
2362 | gdb_byte insn; | |
2c02bd72 | 2363 | const char *name; |
a3fcb948 JG |
2364 | |
2365 | /* A stack trampoline is detected if no name is associated | |
2366 | to the current pc and if it points inside a trampoline | |
2367 | sequence. */ | |
2368 | ||
2369 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2370 | if (name) | |
2371 | return 0; | |
2372 | ||
2373 | if (target_read_memory (pc, &insn, 1)) | |
2374 | return 0; | |
2375 | ||
2376 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2377 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2378 | return 0; | |
2379 | ||
2380 | return 1; | |
2381 | } | |
2382 | ||
2383 | static int | |
2384 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2385 | struct frame_info *this_frame, |
2386 | void **this_cache) | |
a3fcb948 JG |
2387 | { |
2388 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2389 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2390 | else |
2391 | return 0; | |
2392 | } | |
2393 | ||
2394 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2395 | { | |
2396 | NORMAL_FRAME, | |
2397 | i386_epilogue_frame_unwind_stop_reason, | |
2398 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2399 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2400 | NULL, |
2401 | i386_stack_tramp_frame_sniffer | |
2402 | }; | |
2403 | \f | |
6710bf39 SS |
2404 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2405 | ||
2406 | static void | |
2407 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2408 | struct agent_expr *ax, struct axs_value *value, | |
2409 | CORE_ADDR scope) | |
2410 | { | |
2411 | /* The following sequence assumes the traditional use of the base | |
2412 | register. */ | |
2413 | ax_reg (ax, I386_EBP_REGNUM); | |
2414 | ax_const_l (ax, 4); | |
2415 | ax_simple (ax, aop_add); | |
2416 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2417 | value->kind = axs_lvalue_memory; | |
2418 | } | |
2419 | \f | |
a3fcb948 | 2420 | |
acd5c798 MK |
2421 | /* Signal trampolines. */ |
2422 | ||
2423 | static struct i386_frame_cache * | |
10458914 | 2424 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2425 | { |
e17a4113 UW |
2426 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2427 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2428 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2429 | struct i386_frame_cache *cache; |
acd5c798 | 2430 | CORE_ADDR addr; |
63c0089f | 2431 | gdb_byte buf[4]; |
acd5c798 MK |
2432 | |
2433 | if (*this_cache) | |
9a3c8263 | 2434 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2435 | |
fd13a04a | 2436 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2437 | |
492d29ea | 2438 | TRY |
a3386186 | 2439 | { |
8fbca658 PA |
2440 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2441 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2442 | |
8fbca658 PA |
2443 | addr = tdep->sigcontext_addr (this_frame); |
2444 | if (tdep->sc_reg_offset) | |
2445 | { | |
2446 | int i; | |
a3386186 | 2447 | |
8fbca658 PA |
2448 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2449 | ||
2450 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2451 | if (tdep->sc_reg_offset[i] != -1) | |
2452 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2453 | } | |
2454 | else | |
2455 | { | |
2456 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2457 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2458 | } | |
2459 | ||
2460 | cache->base_p = 1; | |
a3386186 | 2461 | } |
492d29ea | 2462 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2463 | { |
2464 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2465 | throw_exception (ex); | |
2466 | } | |
492d29ea | 2467 | END_CATCH |
acd5c798 MK |
2468 | |
2469 | *this_cache = cache; | |
2470 | return cache; | |
2471 | } | |
2472 | ||
8fbca658 PA |
2473 | static enum unwind_stop_reason |
2474 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2475 | void **this_cache) | |
2476 | { | |
2477 | struct i386_frame_cache *cache = | |
2478 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2479 | ||
2480 | if (!cache->base_p) | |
2481 | return UNWIND_UNAVAILABLE; | |
2482 | ||
2483 | return UNWIND_NO_REASON; | |
2484 | } | |
2485 | ||
acd5c798 | 2486 | static void |
10458914 | 2487 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2488 | struct frame_id *this_id) |
2489 | { | |
2490 | struct i386_frame_cache *cache = | |
10458914 | 2491 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2492 | |
8fbca658 | 2493 | if (!cache->base_p) |
5ce0145d PA |
2494 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2495 | else | |
2496 | { | |
2497 | /* See the end of i386_push_dummy_call. */ | |
2498 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2499 | } | |
acd5c798 MK |
2500 | } |
2501 | ||
10458914 DJ |
2502 | static struct value * |
2503 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2504 | void **this_cache, int regnum) | |
acd5c798 MK |
2505 | { |
2506 | /* Make sure we've initialized the cache. */ | |
10458914 | 2507 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2508 | |
10458914 | 2509 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2510 | } |
c0d1d883 | 2511 | |
10458914 DJ |
2512 | static int |
2513 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2514 | struct frame_info *this_frame, | |
2515 | void **this_prologue_cache) | |
acd5c798 | 2516 | { |
10458914 | 2517 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2518 | |
911bc6ee MK |
2519 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2520 | handler. */ | |
2521 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2522 | return 0; |
1c3545ae | 2523 | |
911bc6ee MK |
2524 | if (tdep->sigtramp_p != NULL) |
2525 | { | |
10458914 DJ |
2526 | if (tdep->sigtramp_p (this_frame)) |
2527 | return 1; | |
911bc6ee MK |
2528 | } |
2529 | ||
2530 | if (tdep->sigtramp_start != 0) | |
2531 | { | |
10458914 | 2532 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2533 | |
2534 | gdb_assert (tdep->sigtramp_end != 0); | |
2535 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2536 | return 1; |
911bc6ee | 2537 | } |
acd5c798 | 2538 | |
10458914 | 2539 | return 0; |
acd5c798 | 2540 | } |
10458914 DJ |
2541 | |
2542 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2543 | { | |
2544 | SIGTRAMP_FRAME, | |
8fbca658 | 2545 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2546 | i386_sigtramp_frame_this_id, |
2547 | i386_sigtramp_frame_prev_register, | |
2548 | NULL, | |
2549 | i386_sigtramp_frame_sniffer | |
2550 | }; | |
acd5c798 MK |
2551 | \f |
2552 | ||
2553 | static CORE_ADDR | |
10458914 | 2554 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2555 | { |
10458914 | 2556 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2557 | |
2558 | return cache->base; | |
2559 | } | |
2560 | ||
2561 | static const struct frame_base i386_frame_base = | |
2562 | { | |
2563 | &i386_frame_unwind, | |
2564 | i386_frame_base_address, | |
2565 | i386_frame_base_address, | |
2566 | i386_frame_base_address | |
2567 | }; | |
2568 | ||
acd5c798 | 2569 | static struct frame_id |
10458914 | 2570 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2571 | { |
acd5c798 MK |
2572 | CORE_ADDR fp; |
2573 | ||
10458914 | 2574 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2575 | |
3e210248 | 2576 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2577 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2578 | } |
e04e5beb JM |
2579 | |
2580 | /* _Decimal128 function return values need 16-byte alignment on the | |
2581 | stack. */ | |
2582 | ||
2583 | static CORE_ADDR | |
2584 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2585 | { | |
2586 | return sp & -(CORE_ADDR)16; | |
2587 | } | |
fc338970 | 2588 | \f |
c906108c | 2589 | |
fc338970 MK |
2590 | /* Figure out where the longjmp will land. Slurp the args out of the |
2591 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2592 | structure from which we extract the address that we will land at. |
28bcfd30 | 2593 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2594 | success. */ |
c906108c | 2595 | |
8201327c | 2596 | static int |
60ade65d | 2597 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2598 | { |
436675d3 | 2599 | gdb_byte buf[4]; |
c906108c | 2600 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2601 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2602 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2603 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2604 | |
8201327c MK |
2605 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2606 | longjmp will land. */ | |
2607 | if (jb_pc_offset == -1) | |
c906108c SS |
2608 | return 0; |
2609 | ||
436675d3 | 2610 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2611 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2612 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2613 | return 0; |
2614 | ||
e17a4113 | 2615 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2616 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2617 | return 0; |
c906108c | 2618 | |
e17a4113 | 2619 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2620 | return 1; |
2621 | } | |
fc338970 | 2622 | \f |
c906108c | 2623 | |
7ccc1c74 JM |
2624 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2625 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2626 | unions containing such types must be 16-byte-aligned; other | |
2627 | arguments are 4-byte-aligned. */ | |
2628 | ||
2629 | static int | |
2630 | i386_16_byte_align_p (struct type *type) | |
2631 | { | |
2632 | type = check_typedef (type); | |
2633 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2634 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2635 | && TYPE_LENGTH (type) == 16) | |
2636 | return 1; | |
2637 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2638 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2639 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2640 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2641 | { | |
2642 | int i; | |
2643 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2644 | { | |
2645 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2646 | return 1; | |
2647 | } | |
2648 | } | |
2649 | return 0; | |
2650 | } | |
2651 | ||
a9b8d892 JK |
2652 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2653 | ||
2654 | static CORE_ADDR | |
2655 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2656 | struct value **args, int nargs, struct type *value_type, | |
2657 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2658 | struct regcache *regcache) | |
2659 | { | |
2660 | /* Use 0xcc breakpoint - 1 byte. */ | |
2661 | *bp_addr = sp - 1; | |
2662 | *real_pc = funaddr; | |
2663 | ||
2664 | /* Keep the stack aligned. */ | |
2665 | return sp - 16; | |
2666 | } | |
2667 | ||
3a1e71e3 | 2668 | static CORE_ADDR |
7d9b040b | 2669 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2670 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2671 | struct value **args, CORE_ADDR sp, int struct_return, | |
2672 | CORE_ADDR struct_addr) | |
22f8ba57 | 2673 | { |
e17a4113 | 2674 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2675 | gdb_byte buf[4]; |
acd5c798 | 2676 | int i; |
7ccc1c74 JM |
2677 | int write_pass; |
2678 | int args_space = 0; | |
acd5c798 | 2679 | |
4a612d6f WT |
2680 | /* BND registers can be in arbitrary values at the moment of the |
2681 | inferior call. This can cause boundary violations that are not | |
2682 | due to a real bug or even desired by the user. The best to be done | |
2683 | is set the BND registers to allow access to the whole memory, INIT | |
2684 | state, before pushing the inferior call. */ | |
2685 | i387_reset_bnd_regs (gdbarch, regcache); | |
2686 | ||
7ccc1c74 JM |
2687 | /* Determine the total space required for arguments and struct |
2688 | return address in a first pass (allowing for 16-byte-aligned | |
2689 | arguments), then push arguments in a second pass. */ | |
2690 | ||
2691 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2692 | { |
7ccc1c74 | 2693 | int args_space_used = 0; |
7ccc1c74 JM |
2694 | |
2695 | if (struct_return) | |
2696 | { | |
2697 | if (write_pass) | |
2698 | { | |
2699 | /* Push value address. */ | |
e17a4113 | 2700 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2701 | write_memory (sp, buf, 4); |
2702 | args_space_used += 4; | |
2703 | } | |
2704 | else | |
2705 | args_space += 4; | |
2706 | } | |
2707 | ||
2708 | for (i = 0; i < nargs; i++) | |
2709 | { | |
2710 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2711 | |
7ccc1c74 JM |
2712 | if (write_pass) |
2713 | { | |
2714 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2715 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2716 | |
7ccc1c74 JM |
2717 | write_memory (sp + args_space_used, |
2718 | value_contents_all (args[i]), len); | |
2719 | /* The System V ABI says that: | |
acd5c798 | 2720 | |
7ccc1c74 JM |
2721 | "An argument's size is increased, if necessary, to make it a |
2722 | multiple of [32-bit] words. This may require tail padding, | |
2723 | depending on the size of the argument." | |
22f8ba57 | 2724 | |
7ccc1c74 JM |
2725 | This makes sure the stack stays word-aligned. */ |
2726 | args_space_used += align_up (len, 4); | |
2727 | } | |
2728 | else | |
2729 | { | |
2730 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2731 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2732 | args_space += align_up (len, 4); |
2733 | } | |
2734 | } | |
2735 | ||
2736 | if (!write_pass) | |
2737 | { | |
7ccc1c74 | 2738 | sp -= args_space; |
284c5a60 MK |
2739 | |
2740 | /* The original System V ABI only requires word alignment, | |
2741 | but modern incarnations need 16-byte alignment in order | |
2742 | to support SSE. Since wasting a few bytes here isn't | |
2743 | harmful we unconditionally enforce 16-byte alignment. */ | |
2744 | sp &= ~0xf; | |
7ccc1c74 | 2745 | } |
22f8ba57 MK |
2746 | } |
2747 | ||
acd5c798 MK |
2748 | /* Store return address. */ |
2749 | sp -= 4; | |
e17a4113 | 2750 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2751 | write_memory (sp, buf, 4); |
2752 | ||
2753 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2754 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2755 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2756 | ||
2757 | /* ...and fake a frame pointer. */ | |
2758 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2759 | ||
3e210248 AC |
2760 | /* MarkK wrote: This "+ 8" is all over the place: |
2761 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2762 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2763 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2764 | definition of the stack address of a frame. Otherwise frame id |
2765 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2766 | stack address *before* the function call as a frame's CFA. On |
2767 | the i386, when %ebp is used as a frame pointer, the offset | |
2768 | between the contents %ebp and the CFA as defined by GCC. */ | |
2769 | return sp + 8; | |
22f8ba57 MK |
2770 | } |
2771 | ||
1a309862 MK |
2772 | /* These registers are used for returning integers (and on some |
2773 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2774 | size and alignment match an integer type). */ |
acd5c798 MK |
2775 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2776 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2777 | |
c5e656c1 MK |
2778 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2779 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2780 | |
3a1e71e3 | 2781 | static void |
c5e656c1 | 2782 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2783 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2784 | { |
c5e656c1 | 2785 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2786 | int len = TYPE_LENGTH (type); |
63c0089f | 2787 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2788 | |
1e8d0a7b | 2789 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2790 | { |
5716833c | 2791 | if (tdep->st0_regnum < 0) |
1a309862 | 2792 | { |
8a3fe4f8 | 2793 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2794 | memset (valbuf, 0, len); |
ef9dff19 | 2795 | return; |
1a309862 MK |
2796 | } |
2797 | ||
c6ba6f0d MK |
2798 | /* Floating-point return values can be found in %st(0). Convert |
2799 | its contents to the desired type. This is probably not | |
2800 | exactly how it would happen on the target itself, but it is | |
2801 | the best we can do. */ | |
acd5c798 | 2802 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2803 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2804 | } |
2805 | else | |
c5aa993b | 2806 | { |
875f8d0e UW |
2807 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2808 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2809 | |
2810 | if (len <= low_size) | |
00f8375e | 2811 | { |
0818c12a | 2812 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2813 | memcpy (valbuf, buf, len); |
2814 | } | |
d4f3574e SS |
2815 | else if (len <= (low_size + high_size)) |
2816 | { | |
0818c12a | 2817 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2818 | memcpy (valbuf, buf, low_size); |
0818c12a | 2819 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2820 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2821 | } |
2822 | else | |
8e65ff28 | 2823 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2824 | _("Cannot extract return value of %d bytes long."), |
2825 | len); | |
c906108c SS |
2826 | } |
2827 | } | |
2828 | ||
c5e656c1 MK |
2829 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2830 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2831 | |
3a1e71e3 | 2832 | static void |
c5e656c1 | 2833 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2834 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2835 | { |
c5e656c1 | 2836 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2837 | int len = TYPE_LENGTH (type); |
2838 | ||
1e8d0a7b | 2839 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2840 | { |
3d7f4f49 | 2841 | ULONGEST fstat; |
63c0089f | 2842 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2843 | |
5716833c | 2844 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2845 | { |
8a3fe4f8 | 2846 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2847 | return; |
2848 | } | |
2849 | ||
635b0cc1 MK |
2850 | /* Returning floating-point values is a bit tricky. Apart from |
2851 | storing the return value in %st(0), we have to simulate the | |
2852 | state of the FPU at function return point. */ | |
2853 | ||
c6ba6f0d MK |
2854 | /* Convert the value found in VALBUF to the extended |
2855 | floating-point format used by the FPU. This is probably | |
2856 | not exactly how it would happen on the target itself, but | |
2857 | it is the best we can do. */ | |
27067745 | 2858 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2859 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2860 | |
635b0cc1 MK |
2861 | /* Set the top of the floating-point register stack to 7. The |
2862 | actual value doesn't really matter, but 7 is what a normal | |
2863 | function return would end up with if the program started out | |
2864 | with a freshly initialized FPU. */ | |
20a6ec49 | 2865 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2866 | fstat |= (7 << 11); |
20a6ec49 | 2867 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2868 | |
635b0cc1 MK |
2869 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2870 | the floating-point register stack to 7, the appropriate value | |
2871 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2872 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2873 | } |
2874 | else | |
2875 | { | |
875f8d0e UW |
2876 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2877 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2878 | |
2879 | if (len <= low_size) | |
3d7f4f49 | 2880 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2881 | else if (len <= (low_size + high_size)) |
2882 | { | |
3d7f4f49 MK |
2883 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2884 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2885 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2886 | } |
2887 | else | |
8e65ff28 | 2888 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2889 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2890 | } |
2891 | } | |
fc338970 | 2892 | \f |
ef9dff19 | 2893 | |
8201327c MK |
2894 | /* This is the variable that is set with "set struct-convention", and |
2895 | its legitimate values. */ | |
2896 | static const char default_struct_convention[] = "default"; | |
2897 | static const char pcc_struct_convention[] = "pcc"; | |
2898 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2899 | static const char *const valid_conventions[] = |
8201327c MK |
2900 | { |
2901 | default_struct_convention, | |
2902 | pcc_struct_convention, | |
2903 | reg_struct_convention, | |
2904 | NULL | |
2905 | }; | |
2906 | static const char *struct_convention = default_struct_convention; | |
2907 | ||
0e4377e1 JB |
2908 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2909 | a union type, or an array type, should be returned in registers | |
2910 | for architecture GDBARCH. */ | |
c5e656c1 | 2911 | |
8201327c | 2912 | static int |
c5e656c1 | 2913 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2914 | { |
c5e656c1 MK |
2915 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2916 | enum type_code code = TYPE_CODE (type); | |
2917 | int len = TYPE_LENGTH (type); | |
8201327c | 2918 | |
0e4377e1 JB |
2919 | gdb_assert (code == TYPE_CODE_STRUCT |
2920 | || code == TYPE_CODE_UNION | |
2921 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2922 | |
2923 | if (struct_convention == pcc_struct_convention | |
2924 | || (struct_convention == default_struct_convention | |
2925 | && tdep->struct_return == pcc_struct_return)) | |
2926 | return 0; | |
2927 | ||
9edde48e MK |
2928 | /* Structures consisting of a single `float', `double' or 'long |
2929 | double' member are returned in %st(0). */ | |
2930 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2931 | { | |
2932 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2933 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2934 | return (len == 4 || len == 8 || len == 12); | |
2935 | } | |
2936 | ||
c5e656c1 MK |
2937 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2938 | } | |
2939 | ||
2940 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2941 | should be returned. If it is supposed to be returned in registers, | |
2942 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2943 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2944 | from WRITEBUF into REGCACHE. */ | |
2945 | ||
2946 | static enum return_value_convention | |
6a3a010b | 2947 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2948 | struct type *type, struct regcache *regcache, |
2949 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2950 | { |
2951 | enum type_code code = TYPE_CODE (type); | |
2952 | ||
5daa78cc TJB |
2953 | if (((code == TYPE_CODE_STRUCT |
2954 | || code == TYPE_CODE_UNION | |
2955 | || code == TYPE_CODE_ARRAY) | |
2956 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2957 | /* Complex double and long double uses the struct return covention. */ |
2958 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2959 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2960 | /* 128-bit decimal float uses the struct return convention. */ |
2961 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2962 | { |
2963 | /* The System V ABI says that: | |
2964 | ||
2965 | "A function that returns a structure or union also sets %eax | |
2966 | to the value of the original address of the caller's area | |
2967 | before it returns. Thus when the caller receives control | |
2968 | again, the address of the returned object resides in register | |
2969 | %eax and can be used to access the object." | |
2970 | ||
2971 | So the ABI guarantees that we can always find the return | |
2972 | value just after the function has returned. */ | |
2973 | ||
0e4377e1 JB |
2974 | /* Note that the ABI doesn't mention functions returning arrays, |
2975 | which is something possible in certain languages such as Ada. | |
2976 | In this case, the value is returned as if it was wrapped in | |
2977 | a record, so the convention applied to records also applies | |
2978 | to arrays. */ | |
2979 | ||
31db7b6c MK |
2980 | if (readbuf) |
2981 | { | |
2982 | ULONGEST addr; | |
2983 | ||
2984 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2985 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2986 | } | |
2987 | ||
2988 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2989 | } | |
c5e656c1 MK |
2990 | |
2991 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2992 | `float', `double' or 'long double' member. These structures are |
2993 | returned in %st(0). For these structures, we call ourselves | |
2994 | recursively, changing TYPE into the type of the first member of | |
2995 | the structure. Since that should work for all structures that | |
2996 | have only one member, we don't bother to check the member's type | |
2997 | here. */ | |
c5e656c1 MK |
2998 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2999 | { | |
3000 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 3001 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 3002 | readbuf, writebuf); |
c5e656c1 MK |
3003 | } |
3004 | ||
3005 | if (readbuf) | |
3006 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
3007 | if (writebuf) | |
3008 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3009 | |
c5e656c1 | 3010 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3011 | } |
3012 | \f | |
3013 | ||
27067745 UW |
3014 | struct type * |
3015 | i387_ext_type (struct gdbarch *gdbarch) | |
3016 | { | |
3017 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3018 | ||
3019 | if (!tdep->i387_ext_type) | |
90884b2b L |
3020 | { |
3021 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3022 | gdb_assert (tdep->i387_ext_type != NULL); | |
3023 | } | |
27067745 UW |
3024 | |
3025 | return tdep->i387_ext_type; | |
3026 | } | |
3027 | ||
1dbcd68c WT |
3028 | /* Construct type for pseudo BND registers. We can't use |
3029 | tdesc_find_type since a complement of one value has to be used | |
3030 | to describe the upper bound. */ | |
3031 | ||
3032 | static struct type * | |
3033 | i386_bnd_type (struct gdbarch *gdbarch) | |
3034 | { | |
3035 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3036 | ||
3037 | ||
3038 | if (!tdep->i386_bnd_type) | |
3039 | { | |
870f88f7 | 3040 | struct type *t; |
1dbcd68c WT |
3041 | const struct builtin_type *bt = builtin_type (gdbarch); |
3042 | ||
3043 | /* The type we're building is described bellow: */ | |
3044 | #if 0 | |
3045 | struct __bound128 | |
3046 | { | |
3047 | void *lbound; | |
3048 | void *ubound; /* One complement of raw ubound field. */ | |
3049 | }; | |
3050 | #endif | |
3051 | ||
3052 | t = arch_composite_type (gdbarch, | |
3053 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3054 | ||
3055 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3056 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3057 | ||
3058 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3059 | tdep->i386_bnd_type = t; | |
3060 | } | |
3061 | ||
3062 | return tdep->i386_bnd_type; | |
3063 | } | |
3064 | ||
01f9f808 MS |
3065 | /* Construct vector type for pseudo ZMM registers. We can't use |
3066 | tdesc_find_type since ZMM isn't described in target description. */ | |
3067 | ||
3068 | static struct type * | |
3069 | i386_zmm_type (struct gdbarch *gdbarch) | |
3070 | { | |
3071 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3072 | ||
3073 | if (!tdep->i386_zmm_type) | |
3074 | { | |
3075 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3076 | ||
3077 | /* The type we're building is this: */ | |
3078 | #if 0 | |
3079 | union __gdb_builtin_type_vec512i | |
3080 | { | |
3081 | int128_t uint128[4]; | |
3082 | int64_t v4_int64[8]; | |
3083 | int32_t v8_int32[16]; | |
3084 | int16_t v16_int16[32]; | |
3085 | int8_t v32_int8[64]; | |
3086 | double v4_double[8]; | |
3087 | float v8_float[16]; | |
3088 | }; | |
3089 | #endif | |
3090 | ||
3091 | struct type *t; | |
3092 | ||
3093 | t = arch_composite_type (gdbarch, | |
3094 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3095 | append_composite_type_field (t, "v16_float", | |
3096 | init_vector_type (bt->builtin_float, 16)); | |
3097 | append_composite_type_field (t, "v8_double", | |
3098 | init_vector_type (bt->builtin_double, 8)); | |
3099 | append_composite_type_field (t, "v64_int8", | |
3100 | init_vector_type (bt->builtin_int8, 64)); | |
3101 | append_composite_type_field (t, "v32_int16", | |
3102 | init_vector_type (bt->builtin_int16, 32)); | |
3103 | append_composite_type_field (t, "v16_int32", | |
3104 | init_vector_type (bt->builtin_int32, 16)); | |
3105 | append_composite_type_field (t, "v8_int64", | |
3106 | init_vector_type (bt->builtin_int64, 8)); | |
3107 | append_composite_type_field (t, "v4_int128", | |
3108 | init_vector_type (bt->builtin_int128, 4)); | |
3109 | ||
3110 | TYPE_VECTOR (t) = 1; | |
3111 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3112 | tdep->i386_zmm_type = t; | |
3113 | } | |
3114 | ||
3115 | return tdep->i386_zmm_type; | |
3116 | } | |
3117 | ||
c131fcee L |
3118 | /* Construct vector type for pseudo YMM registers. We can't use |
3119 | tdesc_find_type since YMM isn't described in target description. */ | |
3120 | ||
3121 | static struct type * | |
3122 | i386_ymm_type (struct gdbarch *gdbarch) | |
3123 | { | |
3124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3125 | ||
3126 | if (!tdep->i386_ymm_type) | |
3127 | { | |
3128 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3129 | ||
3130 | /* The type we're building is this: */ | |
3131 | #if 0 | |
3132 | union __gdb_builtin_type_vec256i | |
3133 | { | |
3134 | int128_t uint128[2]; | |
3135 | int64_t v2_int64[4]; | |
3136 | int32_t v4_int32[8]; | |
3137 | int16_t v8_int16[16]; | |
3138 | int8_t v16_int8[32]; | |
3139 | double v2_double[4]; | |
3140 | float v4_float[8]; | |
3141 | }; | |
3142 | #endif | |
3143 | ||
3144 | struct type *t; | |
3145 | ||
3146 | t = arch_composite_type (gdbarch, | |
3147 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3148 | append_composite_type_field (t, "v8_float", | |
3149 | init_vector_type (bt->builtin_float, 8)); | |
3150 | append_composite_type_field (t, "v4_double", | |
3151 | init_vector_type (bt->builtin_double, 4)); | |
3152 | append_composite_type_field (t, "v32_int8", | |
3153 | init_vector_type (bt->builtin_int8, 32)); | |
3154 | append_composite_type_field (t, "v16_int16", | |
3155 | init_vector_type (bt->builtin_int16, 16)); | |
3156 | append_composite_type_field (t, "v8_int32", | |
3157 | init_vector_type (bt->builtin_int32, 8)); | |
3158 | append_composite_type_field (t, "v4_int64", | |
3159 | init_vector_type (bt->builtin_int64, 4)); | |
3160 | append_composite_type_field (t, "v2_int128", | |
3161 | init_vector_type (bt->builtin_int128, 2)); | |
3162 | ||
3163 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3164 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3165 | tdep->i386_ymm_type = t; |
3166 | } | |
3167 | ||
3168 | return tdep->i386_ymm_type; | |
3169 | } | |
3170 | ||
794ac428 | 3171 | /* Construct vector type for MMX registers. */ |
90884b2b | 3172 | static struct type * |
794ac428 UW |
3173 | i386_mmx_type (struct gdbarch *gdbarch) |
3174 | { | |
3175 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3176 | ||
3177 | if (!tdep->i386_mmx_type) | |
3178 | { | |
df4df182 UW |
3179 | const struct builtin_type *bt = builtin_type (gdbarch); |
3180 | ||
794ac428 UW |
3181 | /* The type we're building is this: */ |
3182 | #if 0 | |
3183 | union __gdb_builtin_type_vec64i | |
3184 | { | |
3185 | int64_t uint64; | |
3186 | int32_t v2_int32[2]; | |
3187 | int16_t v4_int16[4]; | |
3188 | int8_t v8_int8[8]; | |
3189 | }; | |
3190 | #endif | |
3191 | ||
3192 | struct type *t; | |
3193 | ||
e9bb382b UW |
3194 | t = arch_composite_type (gdbarch, |
3195 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3196 | |
3197 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3198 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3199 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3200 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3201 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3202 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3203 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3204 | |
876cecd0 | 3205 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3206 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3207 | tdep->i386_mmx_type = t; | |
3208 | } | |
3209 | ||
3210 | return tdep->i386_mmx_type; | |
3211 | } | |
3212 | ||
d7a0d72c | 3213 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3214 | register REGNUM. */ |
d7a0d72c | 3215 | |
fff4548b | 3216 | struct type * |
90884b2b | 3217 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3218 | { |
1dbcd68c WT |
3219 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3220 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3221 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3222 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3223 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3224 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3225 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3226 | return i386_ymm_type (gdbarch); | |
3227 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3228 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3229 | else |
3230 | { | |
3231 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3232 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3233 | return bt->builtin_int8; | |
3234 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3235 | return bt->builtin_int16; | |
3236 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3237 | return bt->builtin_int32; | |
01f9f808 MS |
3238 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3239 | return bt->builtin_int64; | |
1ba53b71 L |
3240 | } |
3241 | ||
3242 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3243 | } |
3244 | ||
28fc6740 | 3245 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3246 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3247 | |
3248 | static int | |
c86c27af | 3249 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3250 | { |
5716833c MK |
3251 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3252 | int mmxreg, fpreg; | |
28fc6740 AC |
3253 | ULONGEST fstat; |
3254 | int tos; | |
c86c27af | 3255 | |
5716833c | 3256 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3257 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3258 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3259 | fpreg = (mmxreg + tos) % 8; |
3260 | ||
20a6ec49 | 3261 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3262 | } |
3263 | ||
3543a589 TT |
3264 | /* A helper function for us by i386_pseudo_register_read_value and |
3265 | amd64_pseudo_register_read_value. It does all the work but reads | |
3266 | the data into an already-allocated value. */ | |
3267 | ||
3268 | void | |
3269 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3270 | struct regcache *regcache, | |
3271 | int regnum, | |
3272 | struct value *result_value) | |
28fc6740 | 3273 | { |
975c21ab | 3274 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3275 | enum register_status status; |
3543a589 | 3276 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3277 | |
5716833c | 3278 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3279 | { |
c86c27af MK |
3280 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3281 | ||
28fc6740 | 3282 | /* Extract (always little endian). */ |
05d1431c PA |
3283 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3284 | if (status != REG_VALID) | |
3543a589 TT |
3285 | mark_value_bytes_unavailable (result_value, 0, |
3286 | TYPE_LENGTH (value_type (result_value))); | |
3287 | else | |
3288 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3289 | } |
3290 | else | |
1ba53b71 L |
3291 | { |
3292 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3293 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3294 | { | |
3295 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3296 | |
1dbcd68c WT |
3297 | /* Extract (always little endian). Read lower 128bits. */ |
3298 | status = regcache_raw_read (regcache, | |
3299 | I387_BND0R_REGNUM (tdep) + regnum, | |
3300 | raw_buf); | |
3301 | if (status != REG_VALID) | |
3302 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3303 | else | |
3304 | { | |
3305 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3306 | LONGEST upper, lower; | |
3307 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3308 | ||
3309 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3310 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3311 | upper = ~upper; | |
3312 | ||
3313 | memcpy (buf, &lower, size); | |
3314 | memcpy (buf + size, &upper, size); | |
3315 | } | |
3316 | } | |
01f9f808 MS |
3317 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3318 | { | |
3319 | regnum -= tdep->k0_regnum; | |
3320 | ||
3321 | /* Extract (always little endian). */ | |
3322 | status = regcache_raw_read (regcache, | |
3323 | tdep->k0_regnum + regnum, | |
3324 | raw_buf); | |
3325 | if (status != REG_VALID) | |
3326 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3327 | else | |
3328 | memcpy (buf, raw_buf, 8); | |
3329 | } | |
3330 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3331 | { | |
3332 | regnum -= tdep->zmm0_regnum; | |
3333 | ||
3334 | if (regnum < num_lower_zmm_regs) | |
3335 | { | |
3336 | /* Extract (always little endian). Read lower 128bits. */ | |
3337 | status = regcache_raw_read (regcache, | |
3338 | I387_XMM0_REGNUM (tdep) + regnum, | |
3339 | raw_buf); | |
3340 | if (status != REG_VALID) | |
3341 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3342 | else | |
3343 | memcpy (buf, raw_buf, 16); | |
3344 | ||
3345 | /* Extract (always little endian). Read upper 128bits. */ | |
3346 | status = regcache_raw_read (regcache, | |
3347 | tdep->ymm0h_regnum + regnum, | |
3348 | raw_buf); | |
3349 | if (status != REG_VALID) | |
3350 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3351 | else | |
3352 | memcpy (buf + 16, raw_buf, 16); | |
3353 | } | |
3354 | else | |
3355 | { | |
3356 | /* Extract (always little endian). Read lower 128bits. */ | |
3357 | status = regcache_raw_read (regcache, | |
3358 | I387_XMM16_REGNUM (tdep) + regnum | |
3359 | - num_lower_zmm_regs, | |
3360 | raw_buf); | |
3361 | if (status != REG_VALID) | |
3362 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3363 | else | |
3364 | memcpy (buf, raw_buf, 16); | |
3365 | ||
3366 | /* Extract (always little endian). Read upper 128bits. */ | |
3367 | status = regcache_raw_read (regcache, | |
3368 | I387_YMM16H_REGNUM (tdep) + regnum | |
3369 | - num_lower_zmm_regs, | |
3370 | raw_buf); | |
3371 | if (status != REG_VALID) | |
3372 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3373 | else | |
3374 | memcpy (buf + 16, raw_buf, 16); | |
3375 | } | |
3376 | ||
3377 | /* Read upper 256bits. */ | |
3378 | status = regcache_raw_read (regcache, | |
3379 | tdep->zmm0h_regnum + regnum, | |
3380 | raw_buf); | |
3381 | if (status != REG_VALID) | |
3382 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3383 | else | |
3384 | memcpy (buf + 32, raw_buf, 32); | |
3385 | } | |
1dbcd68c | 3386 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3387 | { |
3388 | regnum -= tdep->ymm0_regnum; | |
3389 | ||
1777feb0 | 3390 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3391 | status = regcache_raw_read (regcache, |
3392 | I387_XMM0_REGNUM (tdep) + regnum, | |
3393 | raw_buf); | |
3394 | if (status != REG_VALID) | |
3543a589 TT |
3395 | mark_value_bytes_unavailable (result_value, 0, 16); |
3396 | else | |
3397 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3398 | /* Read upper 128bits. */ |
05d1431c PA |
3399 | status = regcache_raw_read (regcache, |
3400 | tdep->ymm0h_regnum + regnum, | |
3401 | raw_buf); | |
3402 | if (status != REG_VALID) | |
3543a589 TT |
3403 | mark_value_bytes_unavailable (result_value, 16, 32); |
3404 | else | |
3405 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3406 | } |
01f9f808 MS |
3407 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3408 | { | |
3409 | regnum -= tdep->ymm16_regnum; | |
3410 | /* Extract (always little endian). Read lower 128bits. */ | |
3411 | status = regcache_raw_read (regcache, | |
3412 | I387_XMM16_REGNUM (tdep) + regnum, | |
3413 | raw_buf); | |
3414 | if (status != REG_VALID) | |
3415 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3416 | else | |
3417 | memcpy (buf, raw_buf, 16); | |
3418 | /* Read upper 128bits. */ | |
3419 | status = regcache_raw_read (regcache, | |
3420 | tdep->ymm16h_regnum + regnum, | |
3421 | raw_buf); | |
3422 | if (status != REG_VALID) | |
3423 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3424 | else | |
3425 | memcpy (buf + 16, raw_buf, 16); | |
3426 | } | |
c131fcee | 3427 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3428 | { |
3429 | int gpnum = regnum - tdep->ax_regnum; | |
3430 | ||
3431 | /* Extract (always little endian). */ | |
05d1431c PA |
3432 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3433 | if (status != REG_VALID) | |
3543a589 TT |
3434 | mark_value_bytes_unavailable (result_value, 0, |
3435 | TYPE_LENGTH (value_type (result_value))); | |
3436 | else | |
3437 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3438 | } |
3439 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3440 | { | |
1ba53b71 L |
3441 | int gpnum = regnum - tdep->al_regnum; |
3442 | ||
3443 | /* Extract (always little endian). We read both lower and | |
3444 | upper registers. */ | |
05d1431c PA |
3445 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3446 | if (status != REG_VALID) | |
3543a589 TT |
3447 | mark_value_bytes_unavailable (result_value, 0, |
3448 | TYPE_LENGTH (value_type (result_value))); | |
3449 | else if (gpnum >= 4) | |
1ba53b71 L |
3450 | memcpy (buf, raw_buf + 1, 1); |
3451 | else | |
3452 | memcpy (buf, raw_buf, 1); | |
3453 | } | |
3454 | else | |
3455 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3456 | } | |
3543a589 TT |
3457 | } |
3458 | ||
3459 | static struct value * | |
3460 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3461 | struct regcache *regcache, | |
3462 | int regnum) | |
3463 | { | |
3464 | struct value *result; | |
3465 | ||
3466 | result = allocate_value (register_type (gdbarch, regnum)); | |
3467 | VALUE_LVAL (result) = lval_register; | |
3468 | VALUE_REGNUM (result) = regnum; | |
3469 | ||
3470 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3471 | |
3543a589 | 3472 | return result; |
28fc6740 AC |
3473 | } |
3474 | ||
1ba53b71 | 3475 | void |
28fc6740 | 3476 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3477 | int regnum, const gdb_byte *buf) |
28fc6740 | 3478 | { |
975c21ab | 3479 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3480 | |
5716833c | 3481 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3482 | { |
c86c27af MK |
3483 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3484 | ||
28fc6740 | 3485 | /* Read ... */ |
1ba53b71 | 3486 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3487 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3488 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3489 | /* ... Write. */ |
1ba53b71 | 3490 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3491 | } |
3492 | else | |
1ba53b71 L |
3493 | { |
3494 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3495 | ||
1dbcd68c WT |
3496 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3497 | { | |
3498 | ULONGEST upper, lower; | |
3499 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3500 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3501 | ||
3502 | /* New values from input value. */ | |
3503 | regnum -= tdep->bnd0_regnum; | |
3504 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3505 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3506 | ||
3507 | /* Fetching register buffer. */ | |
3508 | regcache_raw_read (regcache, | |
3509 | I387_BND0R_REGNUM (tdep) + regnum, | |
3510 | raw_buf); | |
3511 | ||
3512 | upper = ~upper; | |
3513 | ||
3514 | /* Set register bits. */ | |
3515 | memcpy (raw_buf, &lower, 8); | |
3516 | memcpy (raw_buf + 8, &upper, 8); | |
3517 | ||
3518 | ||
3519 | regcache_raw_write (regcache, | |
3520 | I387_BND0R_REGNUM (tdep) + regnum, | |
3521 | raw_buf); | |
3522 | } | |
01f9f808 MS |
3523 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3524 | { | |
3525 | regnum -= tdep->k0_regnum; | |
3526 | ||
3527 | regcache_raw_write (regcache, | |
3528 | tdep->k0_regnum + regnum, | |
3529 | buf); | |
3530 | } | |
3531 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3532 | { | |
3533 | regnum -= tdep->zmm0_regnum; | |
3534 | ||
3535 | if (regnum < num_lower_zmm_regs) | |
3536 | { | |
3537 | /* Write lower 128bits. */ | |
3538 | regcache_raw_write (regcache, | |
3539 | I387_XMM0_REGNUM (tdep) + regnum, | |
3540 | buf); | |
3541 | /* Write upper 128bits. */ | |
3542 | regcache_raw_write (regcache, | |
3543 | I387_YMM0_REGNUM (tdep) + regnum, | |
3544 | buf + 16); | |
3545 | } | |
3546 | else | |
3547 | { | |
3548 | /* Write lower 128bits. */ | |
3549 | regcache_raw_write (regcache, | |
3550 | I387_XMM16_REGNUM (tdep) + regnum | |
3551 | - num_lower_zmm_regs, | |
3552 | buf); | |
3553 | /* Write upper 128bits. */ | |
3554 | regcache_raw_write (regcache, | |
3555 | I387_YMM16H_REGNUM (tdep) + regnum | |
3556 | - num_lower_zmm_regs, | |
3557 | buf + 16); | |
3558 | } | |
3559 | /* Write upper 256bits. */ | |
3560 | regcache_raw_write (regcache, | |
3561 | tdep->zmm0h_regnum + regnum, | |
3562 | buf + 32); | |
3563 | } | |
1dbcd68c | 3564 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3565 | { |
3566 | regnum -= tdep->ymm0_regnum; | |
3567 | ||
3568 | /* ... Write lower 128bits. */ | |
3569 | regcache_raw_write (regcache, | |
3570 | I387_XMM0_REGNUM (tdep) + regnum, | |
3571 | buf); | |
3572 | /* ... Write upper 128bits. */ | |
3573 | regcache_raw_write (regcache, | |
3574 | tdep->ymm0h_regnum + regnum, | |
3575 | buf + 16); | |
3576 | } | |
01f9f808 MS |
3577 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3578 | { | |
3579 | regnum -= tdep->ymm16_regnum; | |
3580 | ||
3581 | /* ... Write lower 128bits. */ | |
3582 | regcache_raw_write (regcache, | |
3583 | I387_XMM16_REGNUM (tdep) + regnum, | |
3584 | buf); | |
3585 | /* ... Write upper 128bits. */ | |
3586 | regcache_raw_write (regcache, | |
3587 | tdep->ymm16h_regnum + regnum, | |
3588 | buf + 16); | |
3589 | } | |
c131fcee | 3590 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3591 | { |
3592 | int gpnum = regnum - tdep->ax_regnum; | |
3593 | ||
3594 | /* Read ... */ | |
3595 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3596 | /* ... Modify ... (always little endian). */ | |
3597 | memcpy (raw_buf, buf, 2); | |
3598 | /* ... Write. */ | |
3599 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3600 | } | |
3601 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3602 | { | |
1ba53b71 L |
3603 | int gpnum = regnum - tdep->al_regnum; |
3604 | ||
3605 | /* Read ... We read both lower and upper registers. */ | |
3606 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3607 | /* ... Modify ... (always little endian). */ | |
3608 | if (gpnum >= 4) | |
3609 | memcpy (raw_buf + 1, buf, 1); | |
3610 | else | |
3611 | memcpy (raw_buf, buf, 1); | |
3612 | /* ... Write. */ | |
3613 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3614 | } | |
3615 | else | |
3616 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3617 | } | |
28fc6740 | 3618 | } |
62e5fd57 MK |
3619 | |
3620 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3621 | ||
3622 | int | |
3623 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3624 | struct agent_expr *ax, int regnum) | |
3625 | { | |
3626 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3627 | ||
3628 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3629 | { | |
3630 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3631 | not care and collect everything... */ | |
3632 | int i; | |
3633 | ||
3634 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3635 | for (i = 0; i < 8; i++) | |
3636 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3637 | return 0; | |
3638 | } | |
3639 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3640 | { | |
3641 | regnum -= tdep->bnd0_regnum; | |
3642 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3643 | return 0; | |
3644 | } | |
3645 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3646 | { | |
3647 | regnum -= tdep->k0_regnum; | |
3648 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3649 | return 0; | |
3650 | } | |
3651 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3652 | { | |
3653 | regnum -= tdep->zmm0_regnum; | |
3654 | if (regnum < num_lower_zmm_regs) | |
3655 | { | |
3656 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3657 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3658 | } | |
3659 | else | |
3660 | { | |
3661 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3662 | - num_lower_zmm_regs); | |
3663 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3664 | - num_lower_zmm_regs); | |
3665 | } | |
3666 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3667 | return 0; | |
3668 | } | |
3669 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3670 | { | |
3671 | regnum -= tdep->ymm0_regnum; | |
3672 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3673 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3674 | return 0; | |
3675 | } | |
3676 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3677 | { | |
3678 | regnum -= tdep->ymm16_regnum; | |
3679 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3680 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3681 | return 0; | |
3682 | } | |
3683 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3684 | { | |
3685 | int gpnum = regnum - tdep->ax_regnum; | |
3686 | ||
3687 | ax_reg_mask (ax, gpnum); | |
3688 | return 0; | |
3689 | } | |
3690 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3691 | { | |
3692 | int gpnum = regnum - tdep->al_regnum; | |
3693 | ||
3694 | ax_reg_mask (ax, gpnum % 4); | |
3695 | return 0; | |
3696 | } | |
3697 | else | |
3698 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3699 | return 1; | |
3700 | } | |
ff2e87ac AC |
3701 | \f |
3702 | ||
ff2e87ac AC |
3703 | /* Return the register number of the register allocated by GCC after |
3704 | REGNUM, or -1 if there is no such register. */ | |
3705 | ||
3706 | static int | |
3707 | i386_next_regnum (int regnum) | |
3708 | { | |
3709 | /* GCC allocates the registers in the order: | |
3710 | ||
3711 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3712 | ||
3713 | Since storing a variable in %esp doesn't make any sense we return | |
3714 | -1 for %ebp and for %esp itself. */ | |
3715 | static int next_regnum[] = | |
3716 | { | |
3717 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3718 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3719 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3720 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3721 | -1, -1, /* Slots for %esp and %ebp. */ | |
3722 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3723 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3724 | }; | |
3725 | ||
de5b9bb9 | 3726 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3727 | return next_regnum[regnum]; |
28fc6740 | 3728 | |
ff2e87ac AC |
3729 | return -1; |
3730 | } | |
3731 | ||
3732 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3733 | needs any special handling. */ | |
d7a0d72c | 3734 | |
3a1e71e3 | 3735 | static int |
1777feb0 MS |
3736 | i386_convert_register_p (struct gdbarch *gdbarch, |
3737 | int regnum, struct type *type) | |
d7a0d72c | 3738 | { |
de5b9bb9 MK |
3739 | int len = TYPE_LENGTH (type); |
3740 | ||
ff2e87ac AC |
3741 | /* Values may be spread across multiple registers. Most debugging |
3742 | formats aren't expressive enough to specify the locations, so | |
3743 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3744 | have a length that is a multiple of the word size, since GCC |
3745 | doesn't seem to put any other types into registers. */ | |
3746 | if (len > 4 && len % 4 == 0) | |
3747 | { | |
3748 | int last_regnum = regnum; | |
3749 | ||
3750 | while (len > 4) | |
3751 | { | |
3752 | last_regnum = i386_next_regnum (last_regnum); | |
3753 | len -= 4; | |
3754 | } | |
3755 | ||
3756 | if (last_regnum != -1) | |
3757 | return 1; | |
3758 | } | |
ff2e87ac | 3759 | |
0abe36f5 | 3760 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3761 | } |
3762 | ||
ff2e87ac AC |
3763 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3764 | return its contents in TO. */ | |
ac27f131 | 3765 | |
8dccd430 | 3766 | static int |
ff2e87ac | 3767 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3768 | struct type *type, gdb_byte *to, |
3769 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3770 | { |
20a6ec49 | 3771 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3772 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3773 | |
20a6ec49 | 3774 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3775 | return i387_register_to_value (frame, regnum, type, to, |
3776 | optimizedp, unavailablep); | |
ff2e87ac | 3777 | |
fd35795f | 3778 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3779 | |
3780 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3781 | |
de5b9bb9 MK |
3782 | while (len > 0) |
3783 | { | |
3784 | gdb_assert (regnum != -1); | |
20a6ec49 | 3785 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3786 | |
8dccd430 PA |
3787 | if (!get_frame_register_bytes (frame, regnum, 0, |
3788 | register_size (gdbarch, regnum), | |
3789 | to, optimizedp, unavailablep)) | |
3790 | return 0; | |
3791 | ||
de5b9bb9 MK |
3792 | regnum = i386_next_regnum (regnum); |
3793 | len -= 4; | |
42835c2b | 3794 | to += 4; |
de5b9bb9 | 3795 | } |
8dccd430 PA |
3796 | |
3797 | *optimizedp = *unavailablep = 0; | |
3798 | return 1; | |
ac27f131 MK |
3799 | } |
3800 | ||
ff2e87ac AC |
3801 | /* Write the contents FROM of a value of type TYPE into register |
3802 | REGNUM in frame FRAME. */ | |
ac27f131 | 3803 | |
3a1e71e3 | 3804 | static void |
ff2e87ac | 3805 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3806 | struct type *type, const gdb_byte *from) |
ac27f131 | 3807 | { |
de5b9bb9 | 3808 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3809 | |
20a6ec49 | 3810 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3811 | { |
d532c08f MK |
3812 | i387_value_to_register (frame, regnum, type, from); |
3813 | return; | |
3814 | } | |
3d261580 | 3815 | |
fd35795f | 3816 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3817 | |
3818 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3819 | |
de5b9bb9 MK |
3820 | while (len > 0) |
3821 | { | |
3822 | gdb_assert (regnum != -1); | |
875f8d0e | 3823 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3824 | |
42835c2b | 3825 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3826 | regnum = i386_next_regnum (regnum); |
3827 | len -= 4; | |
42835c2b | 3828 | from += 4; |
de5b9bb9 | 3829 | } |
ac27f131 | 3830 | } |
ff2e87ac | 3831 | \f |
7fdafb5a MK |
3832 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3833 | in the general-purpose register set REGSET to register cache | |
3834 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3835 | |
20187ed5 | 3836 | void |
473f17b0 MK |
3837 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3838 | int regnum, const void *gregs, size_t len) | |
3839 | { | |
09424cff AA |
3840 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3841 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3842 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3843 | int i; |
3844 | ||
1528345d | 3845 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3846 | |
3847 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3848 | { | |
3849 | if ((regnum == i || regnum == -1) | |
3850 | && tdep->gregset_reg_offset[i] != -1) | |
3851 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3852 | } | |
3853 | } | |
3854 | ||
7fdafb5a MK |
3855 | /* Collect register REGNUM from the register cache REGCACHE and store |
3856 | it in the buffer specified by GREGS and LEN as described by the | |
3857 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3858 | all registers in REGSET. */ | |
3859 | ||
ecc37a5a | 3860 | static void |
7fdafb5a MK |
3861 | i386_collect_gregset (const struct regset *regset, |
3862 | const struct regcache *regcache, | |
3863 | int regnum, void *gregs, size_t len) | |
3864 | { | |
09424cff AA |
3865 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3866 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3867 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3868 | int i; |
3869 | ||
1528345d | 3870 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3871 | |
3872 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3873 | { | |
3874 | if ((regnum == i || regnum == -1) | |
3875 | && tdep->gregset_reg_offset[i] != -1) | |
3876 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3877 | } | |
3878 | } | |
3879 | ||
3880 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3881 | in the floating-point register set REGSET to register cache | |
3882 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3883 | |
3884 | static void | |
3885 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3886 | int regnum, const void *fpregs, size_t len) | |
3887 | { | |
09424cff AA |
3888 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3889 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3890 | |
66a72d25 MK |
3891 | if (len == I387_SIZEOF_FXSAVE) |
3892 | { | |
3893 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3894 | return; | |
3895 | } | |
3896 | ||
1528345d | 3897 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3898 | i387_supply_fsave (regcache, regnum, fpregs); |
3899 | } | |
8446b36a | 3900 | |
2f305df1 MK |
3901 | /* Collect register REGNUM from the register cache REGCACHE and store |
3902 | it in the buffer specified by FPREGS and LEN as described by the | |
3903 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3904 | all registers in REGSET. */ | |
7fdafb5a MK |
3905 | |
3906 | static void | |
3907 | i386_collect_fpregset (const struct regset *regset, | |
3908 | const struct regcache *regcache, | |
3909 | int regnum, void *fpregs, size_t len) | |
3910 | { | |
09424cff AA |
3911 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3912 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3913 | |
3914 | if (len == I387_SIZEOF_FXSAVE) | |
3915 | { | |
3916 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3917 | return; | |
3918 | } | |
3919 | ||
1528345d | 3920 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3921 | i387_collect_fsave (regcache, regnum, fpregs); |
3922 | } | |
3923 | ||
ecc37a5a AA |
3924 | /* Register set definitions. */ |
3925 | ||
3926 | const struct regset i386_gregset = | |
3927 | { | |
3928 | NULL, i386_supply_gregset, i386_collect_gregset | |
3929 | }; | |
3930 | ||
8f0435f7 | 3931 | const struct regset i386_fpregset = |
ecc37a5a AA |
3932 | { |
3933 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3934 | }; | |
3935 | ||
490496c3 | 3936 | /* Default iterator over core file register note sections. */ |
8446b36a | 3937 | |
490496c3 AA |
3938 | void |
3939 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3940 | iterate_over_regset_sections_cb *cb, | |
3941 | void *cb_data, | |
3942 | const struct regcache *regcache) | |
8446b36a MK |
3943 | { |
3944 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3945 | ||
490496c3 AA |
3946 | cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data); |
3947 | if (tdep->sizeof_fpregset) | |
3948 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
8446b36a | 3949 | } |
473f17b0 | 3950 | \f |
fc338970 | 3951 | |
fc338970 | 3952 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3953 | |
3954 | CORE_ADDR | |
e17a4113 UW |
3955 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3956 | CORE_ADDR pc, char *name) | |
c906108c | 3957 | { |
e17a4113 UW |
3958 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3959 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3960 | ||
3961 | /* jmp *(dest) */ | |
3962 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3963 | { |
e17a4113 UW |
3964 | unsigned long indirect = |
3965 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3966 | struct minimal_symbol *indsym = |
7cbd4a93 | 3967 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3968 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3969 | |
c5aa993b | 3970 | if (symname) |
c906108c | 3971 | { |
61012eef GB |
3972 | if (startswith (symname, "__imp_") |
3973 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3974 | return name ? 1 : |
3975 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3976 | } |
3977 | } | |
fc338970 | 3978 | return 0; /* Not a trampoline. */ |
c906108c | 3979 | } |
fc338970 MK |
3980 | \f |
3981 | ||
10458914 DJ |
3982 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3983 | routine. */ | |
8201327c | 3984 | |
4bd207ef | 3985 | int |
10458914 | 3986 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3987 | { |
10458914 | 3988 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3989 | const char *name; |
911bc6ee MK |
3990 | |
3991 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3992 | return (name && strcmp ("_sigtramp", name) == 0); |
3993 | } | |
3994 | \f | |
3995 | ||
fc338970 MK |
3996 | /* We have two flavours of disassembly. The machinery on this page |
3997 | deals with switching between those. */ | |
c906108c SS |
3998 | |
3999 | static int | |
a89aa300 | 4000 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 4001 | { |
5e3397bb MK |
4002 | gdb_assert (disassembly_flavor == att_flavor |
4003 | || disassembly_flavor == intel_flavor); | |
4004 | ||
f995bbe8 | 4005 | info->disassembler_options = disassembly_flavor; |
5e3397bb | 4006 | |
6394c606 | 4007 | return default_print_insn (pc, info); |
7a292a7a | 4008 | } |
fc338970 | 4009 | \f |
3ce1502b | 4010 | |
8201327c MK |
4011 | /* There are a few i386 architecture variants that differ only |
4012 | slightly from the generic i386 target. For now, we don't give them | |
4013 | their own source file, but include them here. As a consequence, | |
4014 | they'll always be included. */ | |
3ce1502b | 4015 | |
8201327c | 4016 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4017 | |
10458914 DJ |
4018 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4019 | routine. */ | |
911bc6ee | 4020 | |
8201327c | 4021 | static int |
10458914 | 4022 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 4023 | { |
10458914 | 4024 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4025 | const char *name; |
911bc6ee | 4026 | |
05b4bd79 | 4027 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4028 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4029 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4030 | || strcmp ("sigvechandler", name) == 0)); |
4031 | } | |
d2a7c97a | 4032 | |
10458914 DJ |
4033 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4034 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4035 | |
3a1e71e3 | 4036 | static CORE_ADDR |
10458914 | 4037 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4038 | { |
e17a4113 UW |
4039 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4040 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4041 | gdb_byte buf[4]; |
acd5c798 | 4042 | CORE_ADDR sp; |
3ce1502b | 4043 | |
10458914 | 4044 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4045 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4046 | |
e17a4113 | 4047 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4048 | } |
55aa24fb SDJ |
4049 | |
4050 | \f | |
4051 | ||
4052 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4053 | gdbarch.h. */ | |
4054 | ||
4055 | int | |
4056 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4057 | { | |
4058 | return (*s == '$' /* Literal number. */ | |
4059 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4060 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4061 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4062 | } | |
4063 | ||
5acfdbae SDJ |
4064 | /* Helper function for i386_stap_parse_special_token. |
4065 | ||
4066 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4067 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4068 | ||
4069 | Return 1 if the operand was parsed successfully, zero | |
4070 | otherwise. */ | |
4071 | ||
4072 | static int | |
4073 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
4074 | struct stap_parse_info *p) | |
4075 | { | |
4076 | const char *s = p->arg; | |
4077 | ||
4078 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4079 | { | |
4080 | int got_minus[3]; | |
4081 | int i; | |
4082 | long displacements[3]; | |
4083 | const char *start; | |
4084 | char *regname; | |
4085 | int len; | |
4086 | struct stoken str; | |
4087 | char *endp; | |
4088 | ||
4089 | got_minus[0] = 0; | |
4090 | if (*s == '+') | |
4091 | ++s; | |
4092 | else if (*s == '-') | |
4093 | { | |
4094 | ++s; | |
4095 | got_minus[0] = 1; | |
4096 | } | |
4097 | ||
d7b30f67 SDJ |
4098 | if (!isdigit ((unsigned char) *s)) |
4099 | return 0; | |
4100 | ||
5acfdbae SDJ |
4101 | displacements[0] = strtol (s, &endp, 10); |
4102 | s = endp; | |
4103 | ||
4104 | if (*s != '+' && *s != '-') | |
4105 | { | |
4106 | /* We are not dealing with a triplet. */ | |
4107 | return 0; | |
4108 | } | |
4109 | ||
4110 | got_minus[1] = 0; | |
4111 | if (*s == '+') | |
4112 | ++s; | |
4113 | else | |
4114 | { | |
4115 | ++s; | |
4116 | got_minus[1] = 1; | |
4117 | } | |
4118 | ||
d7b30f67 SDJ |
4119 | if (!isdigit ((unsigned char) *s)) |
4120 | return 0; | |
4121 | ||
5acfdbae SDJ |
4122 | displacements[1] = strtol (s, &endp, 10); |
4123 | s = endp; | |
4124 | ||
4125 | if (*s != '+' && *s != '-') | |
4126 | { | |
4127 | /* We are not dealing with a triplet. */ | |
4128 | return 0; | |
4129 | } | |
4130 | ||
4131 | got_minus[2] = 0; | |
4132 | if (*s == '+') | |
4133 | ++s; | |
4134 | else | |
4135 | { | |
4136 | ++s; | |
4137 | got_minus[2] = 1; | |
4138 | } | |
4139 | ||
d7b30f67 SDJ |
4140 | if (!isdigit ((unsigned char) *s)) |
4141 | return 0; | |
4142 | ||
5acfdbae SDJ |
4143 | displacements[2] = strtol (s, &endp, 10); |
4144 | s = endp; | |
4145 | ||
4146 | if (*s != '(' || s[1] != '%') | |
4147 | return 0; | |
4148 | ||
4149 | s += 2; | |
4150 | start = s; | |
4151 | ||
4152 | while (isalnum (*s)) | |
4153 | ++s; | |
4154 | ||
4155 | if (*s++ != ')') | |
4156 | return 0; | |
4157 | ||
d7b30f67 | 4158 | len = s - start - 1; |
224c3ddb | 4159 | regname = (char *) alloca (len + 1); |
5acfdbae SDJ |
4160 | |
4161 | strncpy (regname, start, len); | |
4162 | regname[len] = '\0'; | |
4163 | ||
4164 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4165 | error (_("Invalid register name `%s' on expression `%s'."), | |
4166 | regname, p->saved_arg); | |
4167 | ||
4168 | for (i = 0; i < 3; i++) | |
4169 | { | |
410a0ff2 SDJ |
4170 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4171 | write_exp_elt_type | |
4172 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4173 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4174 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4175 | if (got_minus[i]) |
410a0ff2 | 4176 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4177 | } |
4178 | ||
410a0ff2 | 4179 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4180 | str.ptr = regname; |
4181 | str.length = len; | |
410a0ff2 SDJ |
4182 | write_exp_string (&p->pstate, str); |
4183 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4184 | |
410a0ff2 SDJ |
4185 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4186 | write_exp_elt_type (&p->pstate, | |
4187 | builtin_type (gdbarch)->builtin_data_ptr); | |
4188 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4189 | |
410a0ff2 SDJ |
4190 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4191 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4192 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4193 | |
410a0ff2 SDJ |
4194 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4195 | write_exp_elt_type (&p->pstate, | |
4196 | lookup_pointer_type (p->arg_type)); | |
4197 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4198 | |
410a0ff2 | 4199 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4200 | |
4201 | p->arg = s; | |
4202 | ||
4203 | return 1; | |
4204 | } | |
4205 | ||
4206 | return 0; | |
4207 | } | |
4208 | ||
4209 | /* Helper function for i386_stap_parse_special_token. | |
4210 | ||
4211 | This function parses operands of the form `register base + | |
4212 | (register index * size) + offset', as represented in | |
4213 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4214 | ||
4215 | Return 1 if the operand was parsed successfully, zero | |
4216 | otherwise. */ | |
4217 | ||
4218 | static int | |
4219 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4220 | struct stap_parse_info *p) | |
4221 | { | |
4222 | const char *s = p->arg; | |
4223 | ||
4224 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4225 | { | |
4226 | int offset_minus = 0; | |
4227 | long offset = 0; | |
4228 | int size_minus = 0; | |
4229 | long size = 0; | |
4230 | const char *start; | |
4231 | char *base; | |
4232 | int len_base; | |
4233 | char *index; | |
4234 | int len_index; | |
4235 | struct stoken base_token, index_token; | |
4236 | ||
4237 | if (*s == '+') | |
4238 | ++s; | |
4239 | else if (*s == '-') | |
4240 | { | |
4241 | ++s; | |
4242 | offset_minus = 1; | |
4243 | } | |
4244 | ||
4245 | if (offset_minus && !isdigit (*s)) | |
4246 | return 0; | |
4247 | ||
4248 | if (isdigit (*s)) | |
4249 | { | |
4250 | char *endp; | |
4251 | ||
4252 | offset = strtol (s, &endp, 10); | |
4253 | s = endp; | |
4254 | } | |
4255 | ||
4256 | if (*s != '(' || s[1] != '%') | |
4257 | return 0; | |
4258 | ||
4259 | s += 2; | |
4260 | start = s; | |
4261 | ||
4262 | while (isalnum (*s)) | |
4263 | ++s; | |
4264 | ||
4265 | if (*s != ',' || s[1] != '%') | |
4266 | return 0; | |
4267 | ||
4268 | len_base = s - start; | |
224c3ddb | 4269 | base = (char *) alloca (len_base + 1); |
5acfdbae SDJ |
4270 | strncpy (base, start, len_base); |
4271 | base[len_base] = '\0'; | |
4272 | ||
4273 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4274 | error (_("Invalid register name `%s' on expression `%s'."), | |
4275 | base, p->saved_arg); | |
4276 | ||
4277 | s += 2; | |
4278 | start = s; | |
4279 | ||
4280 | while (isalnum (*s)) | |
4281 | ++s; | |
4282 | ||
4283 | len_index = s - start; | |
224c3ddb | 4284 | index = (char *) alloca (len_index + 1); |
5acfdbae SDJ |
4285 | strncpy (index, start, len_index); |
4286 | index[len_index] = '\0'; | |
4287 | ||
4288 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4289 | error (_("Invalid register name `%s' on expression `%s'."), | |
4290 | index, p->saved_arg); | |
4291 | ||
4292 | if (*s != ',' && *s != ')') | |
4293 | return 0; | |
4294 | ||
4295 | if (*s == ',') | |
4296 | { | |
4297 | char *endp; | |
4298 | ||
4299 | ++s; | |
4300 | if (*s == '+') | |
4301 | ++s; | |
4302 | else if (*s == '-') | |
4303 | { | |
4304 | ++s; | |
4305 | size_minus = 1; | |
4306 | } | |
4307 | ||
4308 | size = strtol (s, &endp, 10); | |
4309 | s = endp; | |
4310 | ||
4311 | if (*s != ')') | |
4312 | return 0; | |
4313 | } | |
4314 | ||
4315 | ++s; | |
4316 | ||
4317 | if (offset) | |
4318 | { | |
410a0ff2 SDJ |
4319 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4320 | write_exp_elt_type (&p->pstate, | |
4321 | builtin_type (gdbarch)->builtin_long); | |
4322 | write_exp_elt_longcst (&p->pstate, offset); | |
4323 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4324 | if (offset_minus) |
410a0ff2 | 4325 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4326 | } |
4327 | ||
410a0ff2 | 4328 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4329 | base_token.ptr = base; |
4330 | base_token.length = len_base; | |
410a0ff2 SDJ |
4331 | write_exp_string (&p->pstate, base_token); |
4332 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4333 | |
4334 | if (offset) | |
410a0ff2 | 4335 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4336 | |
410a0ff2 | 4337 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4338 | index_token.ptr = index; |
4339 | index_token.length = len_index; | |
410a0ff2 SDJ |
4340 | write_exp_string (&p->pstate, index_token); |
4341 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4342 | |
4343 | if (size) | |
4344 | { | |
410a0ff2 SDJ |
4345 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4346 | write_exp_elt_type (&p->pstate, | |
4347 | builtin_type (gdbarch)->builtin_long); | |
4348 | write_exp_elt_longcst (&p->pstate, size); | |
4349 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4350 | if (size_minus) |
410a0ff2 SDJ |
4351 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4352 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4353 | } |
4354 | ||
410a0ff2 | 4355 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4356 | |
410a0ff2 SDJ |
4357 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4358 | write_exp_elt_type (&p->pstate, | |
4359 | lookup_pointer_type (p->arg_type)); | |
4360 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4361 | |
410a0ff2 | 4362 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4363 | |
4364 | p->arg = s; | |
4365 | ||
4366 | return 1; | |
4367 | } | |
4368 | ||
4369 | return 0; | |
4370 | } | |
4371 | ||
55aa24fb SDJ |
4372 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4373 | gdbarch.h. */ | |
4374 | ||
4375 | int | |
4376 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4377 | struct stap_parse_info *p) | |
4378 | { | |
55aa24fb SDJ |
4379 | /* In order to parse special tokens, we use a state-machine that go |
4380 | through every known token and try to get a match. */ | |
4381 | enum | |
4382 | { | |
4383 | TRIPLET, | |
4384 | THREE_ARG_DISPLACEMENT, | |
4385 | DONE | |
570dc176 TT |
4386 | }; |
4387 | int current_state; | |
55aa24fb SDJ |
4388 | |
4389 | current_state = TRIPLET; | |
4390 | ||
4391 | /* The special tokens to be parsed here are: | |
4392 | ||
4393 | - `register base + (register index * size) + offset', as represented | |
4394 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4395 | ||
4396 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4397 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4398 | ||
4399 | while (current_state != DONE) | |
4400 | { | |
55aa24fb SDJ |
4401 | switch (current_state) |
4402 | { | |
4403 | case TRIPLET: | |
5acfdbae SDJ |
4404 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4405 | return 1; | |
4406 | break; | |
4407 | ||
55aa24fb | 4408 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4409 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4410 | return 1; | |
4411 | break; | |
55aa24fb SDJ |
4412 | } |
4413 | ||
4414 | /* Advancing to the next state. */ | |
4415 | ++current_state; | |
4416 | } | |
4417 | ||
4418 | return 0; | |
4419 | } | |
4420 | ||
8201327c | 4421 | \f |
3ce1502b | 4422 | |
ac04f72b TT |
4423 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4424 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4425 | ||
4426 | static const char * | |
4427 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4428 | { | |
4429 | return "(x86_64|i.86)"; | |
4430 | } | |
4431 | ||
4432 | \f | |
4433 | ||
8201327c | 4434 | /* Generic ELF. */ |
d2a7c97a | 4435 | |
8201327c MK |
4436 | void |
4437 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4438 | { | |
05c0465e SDJ |
4439 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4440 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4441 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4442 | NULL }; | |
4443 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4444 | NULL }; | |
4445 | ||
c4fc7f1b MK |
4446 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4447 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4448 | |
4449 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4450 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4451 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4452 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4453 | stap_register_indirection_prefixes); | |
4454 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4455 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4456 | set_gdbarch_stap_is_single_operand (gdbarch, |
4457 | i386_stap_is_single_operand); | |
4458 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4459 | i386_stap_parse_special_token); | |
8201327c | 4460 | } |
3ce1502b | 4461 | |
8201327c | 4462 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4463 | |
8201327c MK |
4464 | void |
4465 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4466 | { | |
4467 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4468 | |
8201327c MK |
4469 | /* System V Release 4 uses ELF. */ |
4470 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4471 | |
dfe01d39 | 4472 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4473 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4474 | ||
911bc6ee | 4475 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4476 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4477 | tdep->sc_pc_offset = 36 + 14 * 4; |
4478 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4479 | |
8201327c | 4480 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4481 | } |
4482 | ||
8201327c | 4483 | \f |
2acceee2 | 4484 | |
38c968cf AC |
4485 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4486 | and "sse". */ | |
4487 | ||
4488 | static struct reggroup *i386_sse_reggroup; | |
4489 | static struct reggroup *i386_mmx_reggroup; | |
4490 | ||
4491 | static void | |
4492 | i386_init_reggroups (void) | |
4493 | { | |
4494 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4495 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4496 | } | |
4497 | ||
4498 | static void | |
4499 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4500 | { | |
4501 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4502 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4503 | reggroup_add (gdbarch, general_reggroup); | |
4504 | reggroup_add (gdbarch, float_reggroup); | |
4505 | reggroup_add (gdbarch, all_reggroup); | |
4506 | reggroup_add (gdbarch, save_reggroup); | |
4507 | reggroup_add (gdbarch, restore_reggroup); | |
4508 | reggroup_add (gdbarch, vector_reggroup); | |
4509 | reggroup_add (gdbarch, system_reggroup); | |
4510 | } | |
4511 | ||
4512 | int | |
4513 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4514 | struct reggroup *group) | |
4515 | { | |
c131fcee L |
4516 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4517 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4518 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4519 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4520 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4521 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4522 | |
1ba53b71 L |
4523 | /* Don't include pseudo registers, except for MMX, in any register |
4524 | groups. */ | |
c131fcee | 4525 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4526 | return 0; |
4527 | ||
c131fcee | 4528 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4529 | return 0; |
4530 | ||
c131fcee | 4531 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4532 | return 0; |
4533 | ||
4534 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4535 | if (group == i386_mmx_reggroup) |
4536 | return mmx_regnum_p; | |
1ba53b71 | 4537 | |
51547df6 | 4538 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4539 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4540 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4541 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4542 | if (group == i386_sse_reggroup) |
01f9f808 | 4543 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4544 | |
4545 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4546 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4547 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4548 | ||
22049425 MS |
4549 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4550 | == X86_XSTATE_AVX_AVX512_MASK); | |
4551 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4552 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4553 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4554 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4555 | |
38c968cf | 4556 | if (group == vector_reggroup) |
c131fcee | 4557 | return (mmx_regnum_p |
01f9f808 MS |
4558 | || (zmm_regnum_p && avx512_p) |
4559 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4560 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4561 | || mxcsr_regnum_p); | |
1ba53b71 L |
4562 | |
4563 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4564 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4565 | if (group == float_reggroup) |
4566 | return fp_regnum_p; | |
1ba53b71 | 4567 | |
c131fcee L |
4568 | /* For "info reg all", don't include upper YMM registers nor XMM |
4569 | registers when AVX is supported. */ | |
4570 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4571 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4572 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4573 | if (group == all_reggroup |
01f9f808 MS |
4574 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4575 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4576 | || ymmh_regnum_p | |
4577 | || ymmh_avx512_regnum_p | |
4578 | || zmmh_regnum_p)) | |
c131fcee L |
4579 | return 0; |
4580 | ||
1dbcd68c WT |
4581 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4582 | if (group == all_reggroup | |
df7e5265 | 4583 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4584 | return bnd_regnum_p; |
4585 | ||
4586 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4587 | if (group == all_reggroup | |
df7e5265 | 4588 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4589 | return 0; |
4590 | ||
4591 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4592 | if (group == all_reggroup | |
df7e5265 | 4593 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4594 | return mpx_ctrl_regnum_p; |
4595 | ||
38c968cf | 4596 | if (group == general_reggroup) |
1ba53b71 L |
4597 | return (!fp_regnum_p |
4598 | && !mmx_regnum_p | |
c131fcee L |
4599 | && !mxcsr_regnum_p |
4600 | && !xmm_regnum_p | |
01f9f808 | 4601 | && !xmm_avx512_regnum_p |
c131fcee | 4602 | && !ymm_regnum_p |
1dbcd68c | 4603 | && !ymmh_regnum_p |
01f9f808 MS |
4604 | && !ymm_avx512_regnum_p |
4605 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4606 | && !bndr_regnum_p |
4607 | && !bnd_regnum_p | |
01f9f808 MS |
4608 | && !mpx_ctrl_regnum_p |
4609 | && !zmm_regnum_p | |
51547df6 MS |
4610 | && !zmmh_regnum_p |
4611 | && !pkru_regnum_p); | |
acd5c798 | 4612 | |
38c968cf AC |
4613 | return default_register_reggroup_p (gdbarch, regnum, group); |
4614 | } | |
38c968cf | 4615 | \f |
acd5c798 | 4616 | |
f837910f MK |
4617 | /* Get the ARGIth function argument for the current function. */ |
4618 | ||
42c466d7 | 4619 | static CORE_ADDR |
143985b7 AF |
4620 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4621 | struct type *type) | |
4622 | { | |
e17a4113 UW |
4623 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4624 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4625 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4626 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4627 | } |
4628 | ||
7ad10968 HZ |
4629 | #define PREFIX_REPZ 0x01 |
4630 | #define PREFIX_REPNZ 0x02 | |
4631 | #define PREFIX_LOCK 0x04 | |
4632 | #define PREFIX_DATA 0x08 | |
4633 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4634 | |
7ad10968 HZ |
4635 | /* operand size */ |
4636 | enum | |
4637 | { | |
4638 | OT_BYTE = 0, | |
4639 | OT_WORD, | |
4640 | OT_LONG, | |
cf648174 | 4641 | OT_QUAD, |
a3c4230a | 4642 | OT_DQUAD, |
7ad10968 | 4643 | }; |
473f17b0 | 4644 | |
7ad10968 HZ |
4645 | /* i386 arith/logic operations */ |
4646 | enum | |
4647 | { | |
4648 | OP_ADDL, | |
4649 | OP_ORL, | |
4650 | OP_ADCL, | |
4651 | OP_SBBL, | |
4652 | OP_ANDL, | |
4653 | OP_SUBL, | |
4654 | OP_XORL, | |
4655 | OP_CMPL, | |
4656 | }; | |
5716833c | 4657 | |
7ad10968 HZ |
4658 | struct i386_record_s |
4659 | { | |
cf648174 | 4660 | struct gdbarch *gdbarch; |
7ad10968 | 4661 | struct regcache *regcache; |
df61f520 | 4662 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4663 | CORE_ADDR addr; |
4664 | int aflag; | |
4665 | int dflag; | |
4666 | int override; | |
4667 | uint8_t modrm; | |
4668 | uint8_t mod, reg, rm; | |
4669 | int ot; | |
cf648174 HZ |
4670 | uint8_t rex_x; |
4671 | uint8_t rex_b; | |
4672 | int rip_offset; | |
4673 | int popl_esp_hack; | |
4674 | const int *regmap; | |
7ad10968 | 4675 | }; |
5716833c | 4676 | |
99c1624c PA |
4677 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4678 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4679 | |
7ad10968 HZ |
4680 | static int |
4681 | i386_record_modrm (struct i386_record_s *irp) | |
4682 | { | |
cf648174 | 4683 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4684 | |
4ffa4fc7 PA |
4685 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4686 | return -1; | |
4687 | ||
7ad10968 HZ |
4688 | irp->addr++; |
4689 | irp->mod = (irp->modrm >> 6) & 3; | |
4690 | irp->reg = (irp->modrm >> 3) & 7; | |
4691 | irp->rm = irp->modrm & 7; | |
5716833c | 4692 | |
7ad10968 HZ |
4693 | return 0; |
4694 | } | |
d2a7c97a | 4695 | |
99c1624c PA |
4696 | /* Extract the memory address that the current instruction writes to, |
4697 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4698 | |
7ad10968 | 4699 | static int |
cf648174 | 4700 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4701 | { |
cf648174 | 4702 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4703 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4704 | gdb_byte buf[4]; | |
4705 | ULONGEST offset64; | |
21d0e8a4 | 4706 | |
7ad10968 | 4707 | *addr = 0; |
1e87984a | 4708 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4709 | { |
1e87984a | 4710 | /* 32/64 bits */ |
7ad10968 HZ |
4711 | int havesib = 0; |
4712 | uint8_t scale = 0; | |
648d0c8b | 4713 | uint8_t byte; |
7ad10968 HZ |
4714 | uint8_t index = 0; |
4715 | uint8_t base = irp->rm; | |
896fb97d | 4716 | |
7ad10968 HZ |
4717 | if (base == 4) |
4718 | { | |
4719 | havesib = 1; | |
4ffa4fc7 PA |
4720 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4721 | return -1; | |
7ad10968 | 4722 | irp->addr++; |
648d0c8b MS |
4723 | scale = (byte >> 6) & 3; |
4724 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4725 | base = (byte & 7); | |
7ad10968 | 4726 | } |
cf648174 | 4727 | base |= irp->rex_b; |
21d0e8a4 | 4728 | |
7ad10968 HZ |
4729 | switch (irp->mod) |
4730 | { | |
4731 | case 0: | |
4732 | if ((base & 7) == 5) | |
4733 | { | |
4734 | base = 0xff; | |
4ffa4fc7 PA |
4735 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4736 | return -1; | |
7ad10968 | 4737 | irp->addr += 4; |
60a1502a | 4738 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4739 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4740 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4741 | } |
7ad10968 HZ |
4742 | break; |
4743 | case 1: | |
4ffa4fc7 PA |
4744 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4745 | return -1; | |
7ad10968 | 4746 | irp->addr++; |
60a1502a | 4747 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4748 | break; |
4749 | case 2: | |
4ffa4fc7 PA |
4750 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4751 | return -1; | |
60a1502a | 4752 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4753 | irp->addr += 4; |
4754 | break; | |
4755 | } | |
356a6b3e | 4756 | |
60a1502a | 4757 | offset64 = 0; |
7ad10968 | 4758 | if (base != 0xff) |
cf648174 HZ |
4759 | { |
4760 | if (base == 4 && irp->popl_esp_hack) | |
4761 | *addr += irp->popl_esp_hack; | |
4762 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4763 | &offset64); |
7ad10968 | 4764 | } |
cf648174 HZ |
4765 | if (irp->aflag == 2) |
4766 | { | |
60a1502a | 4767 | *addr += offset64; |
cf648174 HZ |
4768 | } |
4769 | else | |
60a1502a | 4770 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4771 | |
7ad10968 HZ |
4772 | if (havesib && (index != 4 || scale != 0)) |
4773 | { | |
cf648174 | 4774 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4775 | &offset64); |
cf648174 | 4776 | if (irp->aflag == 2) |
60a1502a | 4777 | *addr += offset64 << scale; |
cf648174 | 4778 | else |
60a1502a | 4779 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4780 | } |
e85596e0 L |
4781 | |
4782 | if (!irp->aflag) | |
4783 | { | |
4784 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4785 | address from 32-bit to 64-bit. */ | |
4786 | *addr = (uint32_t) *addr; | |
4787 | } | |
7ad10968 HZ |
4788 | } |
4789 | else | |
4790 | { | |
4791 | /* 16 bits */ | |
4792 | switch (irp->mod) | |
4793 | { | |
4794 | case 0: | |
4795 | if (irp->rm == 6) | |
4796 | { | |
4ffa4fc7 PA |
4797 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4798 | return -1; | |
7ad10968 | 4799 | irp->addr += 2; |
60a1502a | 4800 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4801 | irp->rm = 0; |
4802 | goto no_rm; | |
4803 | } | |
7ad10968 HZ |
4804 | break; |
4805 | case 1: | |
4ffa4fc7 PA |
4806 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4807 | return -1; | |
7ad10968 | 4808 | irp->addr++; |
60a1502a | 4809 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4810 | break; |
4811 | case 2: | |
4ffa4fc7 PA |
4812 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4813 | return -1; | |
7ad10968 | 4814 | irp->addr += 2; |
60a1502a | 4815 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4816 | break; |
4817 | } | |
c4fc7f1b | 4818 | |
7ad10968 HZ |
4819 | switch (irp->rm) |
4820 | { | |
4821 | case 0: | |
cf648174 HZ |
4822 | regcache_raw_read_unsigned (irp->regcache, |
4823 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4824 | &offset64); |
4825 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4826 | regcache_raw_read_unsigned (irp->regcache, |
4827 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4828 | &offset64); |
4829 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4830 | break; |
4831 | case 1: | |
cf648174 HZ |
4832 | regcache_raw_read_unsigned (irp->regcache, |
4833 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4834 | &offset64); |
4835 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4836 | regcache_raw_read_unsigned (irp->regcache, |
4837 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4838 | &offset64); |
4839 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4840 | break; |
4841 | case 2: | |
cf648174 HZ |
4842 | regcache_raw_read_unsigned (irp->regcache, |
4843 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4844 | &offset64); |
4845 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4846 | regcache_raw_read_unsigned (irp->regcache, |
4847 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4848 | &offset64); |
4849 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4850 | break; |
4851 | case 3: | |
cf648174 HZ |
4852 | regcache_raw_read_unsigned (irp->regcache, |
4853 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4854 | &offset64); |
4855 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4856 | regcache_raw_read_unsigned (irp->regcache, |
4857 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4858 | &offset64); |
4859 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4860 | break; |
4861 | case 4: | |
cf648174 HZ |
4862 | regcache_raw_read_unsigned (irp->regcache, |
4863 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4864 | &offset64); |
4865 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4866 | break; |
4867 | case 5: | |
cf648174 HZ |
4868 | regcache_raw_read_unsigned (irp->regcache, |
4869 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4870 | &offset64); |
4871 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4872 | break; |
4873 | case 6: | |
cf648174 HZ |
4874 | regcache_raw_read_unsigned (irp->regcache, |
4875 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4876 | &offset64); |
4877 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4878 | break; |
4879 | case 7: | |
cf648174 HZ |
4880 | regcache_raw_read_unsigned (irp->regcache, |
4881 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4882 | &offset64); |
4883 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4884 | break; |
4885 | } | |
4886 | *addr &= 0xffff; | |
4887 | } | |
c4fc7f1b | 4888 | |
01fe1b41 | 4889 | no_rm: |
7ad10968 HZ |
4890 | return 0; |
4891 | } | |
c4fc7f1b | 4892 | |
99c1624c PA |
4893 | /* Record the address and contents of the memory that will be changed |
4894 | by the current instruction. Return -1 if something goes wrong, 0 | |
4895 | otherwise. */ | |
356a6b3e | 4896 | |
7ad10968 HZ |
4897 | static int |
4898 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4899 | { | |
cf648174 HZ |
4900 | struct gdbarch *gdbarch = irp->gdbarch; |
4901 | uint64_t addr; | |
356a6b3e | 4902 | |
d7877f7e | 4903 | if (irp->override >= 0) |
7ad10968 | 4904 | { |
25ea693b | 4905 | if (record_full_memory_query) |
bb08c432 | 4906 | { |
651ce16a | 4907 | if (yquery (_("\ |
bb08c432 HZ |
4908 | Process record ignores the memory change of instruction at address %s\n\ |
4909 | because it can't get the value of the segment register.\n\ | |
4910 | Do you want to stop the program?"), | |
651ce16a PA |
4911 | paddress (gdbarch, irp->orig_addr))) |
4912 | return -1; | |
bb08c432 HZ |
4913 | } |
4914 | ||
7ad10968 HZ |
4915 | return 0; |
4916 | } | |
61113f8b | 4917 | |
7ad10968 HZ |
4918 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4919 | return -1; | |
96297dab | 4920 | |
25ea693b | 4921 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4922 | return -1; |
a62cc96e | 4923 | |
7ad10968 HZ |
4924 | return 0; |
4925 | } | |
b6197528 | 4926 | |
99c1624c PA |
4927 | /* Record the effects of a push operation. Return -1 if something |
4928 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4929 | |
4930 | static int | |
4931 | i386_record_push (struct i386_record_s *irp, int size) | |
4932 | { | |
648d0c8b | 4933 | ULONGEST addr; |
cf648174 | 4934 | |
25ea693b MM |
4935 | if (record_full_arch_list_add_reg (irp->regcache, |
4936 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4937 | return -1; |
4938 | regcache_raw_read_unsigned (irp->regcache, | |
4939 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4940 | &addr); |
25ea693b | 4941 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4942 | return -1; |
4943 | ||
4944 | return 0; | |
4945 | } | |
4946 | ||
0289bdd7 MS |
4947 | |
4948 | /* Defines contents to record. */ | |
4949 | #define I386_SAVE_FPU_REGS 0xfffd | |
4950 | #define I386_SAVE_FPU_ENV 0xfffe | |
4951 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4952 | ||
99c1624c PA |
4953 | /* Record the values of the floating point registers which will be |
4954 | changed by the current instruction. Returns -1 if something is | |
4955 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4956 | |
4957 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4958 | struct i386_record_s *ir, | |
4959 | uint32_t iregnum) | |
4960 | { | |
4961 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4962 | int i; | |
4963 | ||
4964 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4965 | happen. Currently we store st0-st7 registers, but we need not store all | |
4966 | registers all the time, in future we use ftag register and record only | |
4967 | those who are not marked as an empty. */ | |
4968 | ||
4969 | if (I386_SAVE_FPU_REGS == iregnum) | |
4970 | { | |
4971 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4972 | { | |
25ea693b | 4973 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4974 | return -1; |
4975 | } | |
4976 | } | |
4977 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4978 | { | |
4979 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4980 | { | |
25ea693b | 4981 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4982 | return -1; |
4983 | } | |
4984 | } | |
4985 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4986 | { | |
4987 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4988 | { | |
25ea693b | 4989 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4990 | return -1; |
4991 | } | |
4992 | } | |
4993 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4994 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4995 | { | |
25ea693b | 4996 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4997 | return -1; |
4998 | } | |
4999 | else | |
5000 | { | |
5001 | /* Parameter error. */ | |
5002 | return -1; | |
5003 | } | |
5004 | if(I386_SAVE_FPU_ENV != iregnum) | |
5005 | { | |
5006 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5007 | { | |
25ea693b | 5008 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5009 | return -1; |
5010 | } | |
5011 | } | |
5012 | return 0; | |
5013 | } | |
5014 | ||
99c1624c PA |
5015 | /* Parse the current instruction, and record the values of the |
5016 | registers and memory that will be changed by the current | |
5017 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5018 | |
25ea693b MM |
5019 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5020 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5021 | |
a6b808b4 | 5022 | int |
7ad10968 | 5023 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5024 | CORE_ADDR input_addr) |
7ad10968 | 5025 | { |
60a1502a | 5026 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5027 | int prefixes = 0; |
580879fc | 5028 | int regnum = 0; |
425b824a | 5029 | uint32_t opcode; |
f4644a3f | 5030 | uint8_t opcode8; |
648d0c8b | 5031 | ULONGEST addr; |
975c21ab | 5032 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5033 | struct i386_record_s ir; |
0289bdd7 | 5034 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5035 | uint8_t rex_w = -1; |
5036 | uint8_t rex_r = 0; | |
7ad10968 | 5037 | |
8408d274 | 5038 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5039 | ir.regcache = regcache; |
648d0c8b MS |
5040 | ir.addr = input_addr; |
5041 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5042 | ir.aflag = 1; |
5043 | ir.dflag = 1; | |
cf648174 HZ |
5044 | ir.override = -1; |
5045 | ir.popl_esp_hack = 0; | |
a3c4230a | 5046 | ir.regmap = tdep->record_regmap; |
cf648174 | 5047 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5048 | |
5049 | if (record_debug > 1) | |
5050 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
5051 | "addr = %s\n", |
5052 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5053 | |
5054 | /* prefixes */ | |
5055 | while (1) | |
5056 | { | |
4ffa4fc7 PA |
5057 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5058 | return -1; | |
7ad10968 | 5059 | ir.addr++; |
425b824a | 5060 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5061 | { |
01fe1b41 | 5062 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5063 | prefixes |= PREFIX_REPZ; |
5064 | break; | |
01fe1b41 | 5065 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5066 | prefixes |= PREFIX_REPNZ; |
5067 | break; | |
01fe1b41 | 5068 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5069 | prefixes |= PREFIX_LOCK; |
5070 | break; | |
01fe1b41 | 5071 | case CS_PREFIX_OPCODE: |
cf648174 | 5072 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5073 | break; |
01fe1b41 | 5074 | case SS_PREFIX_OPCODE: |
cf648174 | 5075 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5076 | break; |
01fe1b41 | 5077 | case DS_PREFIX_OPCODE: |
cf648174 | 5078 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5079 | break; |
01fe1b41 | 5080 | case ES_PREFIX_OPCODE: |
cf648174 | 5081 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5082 | break; |
01fe1b41 | 5083 | case FS_PREFIX_OPCODE: |
cf648174 | 5084 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5085 | break; |
01fe1b41 | 5086 | case GS_PREFIX_OPCODE: |
cf648174 | 5087 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5088 | break; |
01fe1b41 | 5089 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5090 | prefixes |= PREFIX_DATA; |
5091 | break; | |
01fe1b41 | 5092 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5093 | prefixes |= PREFIX_ADDR; |
5094 | break; | |
d691bec7 MS |
5095 | case 0x40: /* i386 inc %eax */ |
5096 | case 0x41: /* i386 inc %ecx */ | |
5097 | case 0x42: /* i386 inc %edx */ | |
5098 | case 0x43: /* i386 inc %ebx */ | |
5099 | case 0x44: /* i386 inc %esp */ | |
5100 | case 0x45: /* i386 inc %ebp */ | |
5101 | case 0x46: /* i386 inc %esi */ | |
5102 | case 0x47: /* i386 inc %edi */ | |
5103 | case 0x48: /* i386 dec %eax */ | |
5104 | case 0x49: /* i386 dec %ecx */ | |
5105 | case 0x4a: /* i386 dec %edx */ | |
5106 | case 0x4b: /* i386 dec %ebx */ | |
5107 | case 0x4c: /* i386 dec %esp */ | |
5108 | case 0x4d: /* i386 dec %ebp */ | |
5109 | case 0x4e: /* i386 dec %esi */ | |
5110 | case 0x4f: /* i386 dec %edi */ | |
5111 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5112 | { |
5113 | /* REX */ | |
425b824a MS |
5114 | rex_w = (opcode8 >> 3) & 1; |
5115 | rex_r = (opcode8 & 0x4) << 1; | |
5116 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5117 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5118 | } |
d691bec7 MS |
5119 | else /* 32 bit target */ |
5120 | goto out_prefixes; | |
cf648174 | 5121 | break; |
7ad10968 HZ |
5122 | default: |
5123 | goto out_prefixes; | |
5124 | break; | |
5125 | } | |
5126 | } | |
01fe1b41 | 5127 | out_prefixes: |
cf648174 HZ |
5128 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5129 | { | |
5130 | ir.dflag = 2; | |
5131 | } | |
5132 | else | |
5133 | { | |
5134 | if (prefixes & PREFIX_DATA) | |
5135 | ir.dflag ^= 1; | |
5136 | } | |
7ad10968 HZ |
5137 | if (prefixes & PREFIX_ADDR) |
5138 | ir.aflag ^= 1; | |
cf648174 HZ |
5139 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5140 | ir.aflag = 2; | |
7ad10968 | 5141 | |
1777feb0 | 5142 | /* Now check op code. */ |
425b824a | 5143 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5144 | reswitch: |
7ad10968 HZ |
5145 | switch (opcode) |
5146 | { | |
5147 | case 0x0f: | |
4ffa4fc7 PA |
5148 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5149 | return -1; | |
7ad10968 | 5150 | ir.addr++; |
a3c4230a | 5151 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5152 | goto reswitch; |
5153 | break; | |
93924b6b | 5154 | |
a38bba38 | 5155 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5156 | case 0x01: |
5157 | case 0x02: | |
5158 | case 0x03: | |
5159 | case 0x04: | |
5160 | case 0x05: | |
5161 | case 0x08: | |
5162 | case 0x09: | |
5163 | case 0x0a: | |
5164 | case 0x0b: | |
5165 | case 0x0c: | |
5166 | case 0x0d: | |
5167 | case 0x10: | |
5168 | case 0x11: | |
5169 | case 0x12: | |
5170 | case 0x13: | |
5171 | case 0x14: | |
5172 | case 0x15: | |
5173 | case 0x18: | |
5174 | case 0x19: | |
5175 | case 0x1a: | |
5176 | case 0x1b: | |
5177 | case 0x1c: | |
5178 | case 0x1d: | |
5179 | case 0x20: | |
5180 | case 0x21: | |
5181 | case 0x22: | |
5182 | case 0x23: | |
5183 | case 0x24: | |
5184 | case 0x25: | |
5185 | case 0x28: | |
5186 | case 0x29: | |
5187 | case 0x2a: | |
5188 | case 0x2b: | |
5189 | case 0x2c: | |
5190 | case 0x2d: | |
5191 | case 0x30: | |
5192 | case 0x31: | |
5193 | case 0x32: | |
5194 | case 0x33: | |
5195 | case 0x34: | |
5196 | case 0x35: | |
5197 | case 0x38: | |
5198 | case 0x39: | |
5199 | case 0x3a: | |
5200 | case 0x3b: | |
5201 | case 0x3c: | |
5202 | case 0x3d: | |
5203 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5204 | { | |
5205 | if ((opcode & 1) == 0) | |
5206 | ir.ot = OT_BYTE; | |
5207 | else | |
5208 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5209 | |
7ad10968 HZ |
5210 | switch ((opcode >> 1) & 3) |
5211 | { | |
a38bba38 | 5212 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5213 | if (i386_record_modrm (&ir)) |
5214 | return -1; | |
5215 | if (ir.mod != 3) | |
5216 | { | |
5217 | if (i386_record_lea_modrm (&ir)) | |
5218 | return -1; | |
5219 | } | |
5220 | else | |
5221 | { | |
cf648174 HZ |
5222 | ir.rm |= ir.rex_b; |
5223 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5224 | ir.rm &= 0x3; |
25ea693b | 5225 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5226 | } |
5227 | break; | |
a38bba38 | 5228 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5229 | if (i386_record_modrm (&ir)) |
5230 | return -1; | |
cf648174 HZ |
5231 | ir.reg |= rex_r; |
5232 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5233 | ir.reg &= 0x3; |
25ea693b | 5234 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5235 | break; |
a38bba38 | 5236 | case 2: /* OP A, Iv */ |
25ea693b | 5237 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5238 | break; |
5239 | } | |
5240 | } | |
25ea693b | 5241 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5242 | break; |
42fdc8df | 5243 | |
a38bba38 | 5244 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5245 | case 0x81: |
5246 | case 0x82: | |
5247 | case 0x83: | |
5248 | if (i386_record_modrm (&ir)) | |
5249 | return -1; | |
8201327c | 5250 | |
7ad10968 HZ |
5251 | if (ir.reg != OP_CMPL) |
5252 | { | |
5253 | if ((opcode & 1) == 0) | |
5254 | ir.ot = OT_BYTE; | |
5255 | else | |
5256 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5257 | |
7ad10968 HZ |
5258 | if (ir.mod != 3) |
5259 | { | |
cf648174 HZ |
5260 | if (opcode == 0x83) |
5261 | ir.rip_offset = 1; | |
5262 | else | |
5263 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5264 | if (i386_record_lea_modrm (&ir)) |
5265 | return -1; | |
5266 | } | |
5267 | else | |
25ea693b | 5268 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5269 | } |
25ea693b | 5270 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5271 | break; |
5e3397bb | 5272 | |
a38bba38 | 5273 | case 0x40: /* inc */ |
7ad10968 HZ |
5274 | case 0x41: |
5275 | case 0x42: | |
5276 | case 0x43: | |
5277 | case 0x44: | |
5278 | case 0x45: | |
5279 | case 0x46: | |
5280 | case 0x47: | |
a38bba38 MS |
5281 | |
5282 | case 0x48: /* dec */ | |
7ad10968 HZ |
5283 | case 0x49: |
5284 | case 0x4a: | |
5285 | case 0x4b: | |
5286 | case 0x4c: | |
5287 | case 0x4d: | |
5288 | case 0x4e: | |
5289 | case 0x4f: | |
a38bba38 | 5290 | |
25ea693b MM |
5291 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5292 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5293 | break; |
acd5c798 | 5294 | |
a38bba38 | 5295 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5296 | case 0xf7: |
5297 | if ((opcode & 1) == 0) | |
5298 | ir.ot = OT_BYTE; | |
5299 | else | |
5300 | ir.ot = ir.dflag + OT_WORD; | |
5301 | if (i386_record_modrm (&ir)) | |
5302 | return -1; | |
acd5c798 | 5303 | |
cf648174 HZ |
5304 | if (ir.mod != 3 && ir.reg == 0) |
5305 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5306 | ||
7ad10968 HZ |
5307 | switch (ir.reg) |
5308 | { | |
a38bba38 | 5309 | case 0: /* test */ |
25ea693b | 5310 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5311 | break; |
a38bba38 MS |
5312 | case 2: /* not */ |
5313 | case 3: /* neg */ | |
7ad10968 HZ |
5314 | if (ir.mod != 3) |
5315 | { | |
5316 | if (i386_record_lea_modrm (&ir)) | |
5317 | return -1; | |
5318 | } | |
5319 | else | |
5320 | { | |
cf648174 HZ |
5321 | ir.rm |= ir.rex_b; |
5322 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5323 | ir.rm &= 0x3; |
25ea693b | 5324 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5325 | } |
a38bba38 | 5326 | if (ir.reg == 3) /* neg */ |
25ea693b | 5327 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5328 | break; |
a38bba38 MS |
5329 | case 4: /* mul */ |
5330 | case 5: /* imul */ | |
5331 | case 6: /* div */ | |
5332 | case 7: /* idiv */ | |
25ea693b | 5333 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5334 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5335 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5336 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5337 | break; |
5338 | default: | |
5339 | ir.addr -= 2; | |
5340 | opcode = opcode << 8 | ir.modrm; | |
5341 | goto no_support; | |
5342 | break; | |
5343 | } | |
5344 | break; | |
5345 | ||
a38bba38 MS |
5346 | case 0xfe: /* GRP4 */ |
5347 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5348 | if (i386_record_modrm (&ir)) |
5349 | return -1; | |
5350 | if (ir.reg >= 2 && opcode == 0xfe) | |
5351 | { | |
5352 | ir.addr -= 2; | |
5353 | opcode = opcode << 8 | ir.modrm; | |
5354 | goto no_support; | |
5355 | } | |
7ad10968 HZ |
5356 | switch (ir.reg) |
5357 | { | |
a38bba38 MS |
5358 | case 0: /* inc */ |
5359 | case 1: /* dec */ | |
cf648174 HZ |
5360 | if ((opcode & 1) == 0) |
5361 | ir.ot = OT_BYTE; | |
5362 | else | |
5363 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5364 | if (ir.mod != 3) |
5365 | { | |
5366 | if (i386_record_lea_modrm (&ir)) | |
5367 | return -1; | |
5368 | } | |
5369 | else | |
5370 | { | |
cf648174 HZ |
5371 | ir.rm |= ir.rex_b; |
5372 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5373 | ir.rm &= 0x3; |
25ea693b | 5374 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5375 | } |
25ea693b | 5376 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5377 | break; |
a38bba38 | 5378 | case 2: /* call */ |
cf648174 HZ |
5379 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5380 | ir.dflag = 2; | |
5381 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5382 | return -1; |
25ea693b | 5383 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5384 | break; |
a38bba38 | 5385 | case 3: /* lcall */ |
25ea693b | 5386 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5387 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5388 | return -1; |
25ea693b | 5389 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5390 | break; |
a38bba38 MS |
5391 | case 4: /* jmp */ |
5392 | case 5: /* ljmp */ | |
25ea693b | 5393 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5394 | break; |
a38bba38 | 5395 | case 6: /* push */ |
cf648174 HZ |
5396 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5397 | ir.dflag = 2; | |
5398 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5399 | return -1; | |
7ad10968 HZ |
5400 | break; |
5401 | default: | |
5402 | ir.addr -= 2; | |
5403 | opcode = opcode << 8 | ir.modrm; | |
5404 | goto no_support; | |
5405 | break; | |
5406 | } | |
5407 | break; | |
5408 | ||
a38bba38 | 5409 | case 0x84: /* test */ |
7ad10968 HZ |
5410 | case 0x85: |
5411 | case 0xa8: | |
5412 | case 0xa9: | |
25ea693b | 5413 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5414 | break; |
5415 | ||
a38bba38 | 5416 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5417 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5418 | break; |
5419 | ||
a38bba38 | 5420 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5421 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5422 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5423 | break; |
5424 | ||
a38bba38 | 5425 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5426 | case 0x69: |
5427 | case 0x6b: | |
5428 | ir.ot = ir.dflag + OT_WORD; | |
5429 | if (i386_record_modrm (&ir)) | |
5430 | return -1; | |
cf648174 HZ |
5431 | if (opcode == 0x69) |
5432 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5433 | else if (opcode == 0x6b) | |
5434 | ir.rip_offset = 1; | |
5435 | ir.reg |= rex_r; | |
5436 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5437 | ir.reg &= 0x3; |
25ea693b MM |
5438 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5440 | break; |
5441 | ||
a38bba38 | 5442 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5443 | case 0x0fc1: |
5444 | if ((opcode & 1) == 0) | |
5445 | ir.ot = OT_BYTE; | |
5446 | else | |
5447 | ir.ot = ir.dflag + OT_WORD; | |
5448 | if (i386_record_modrm (&ir)) | |
5449 | return -1; | |
cf648174 | 5450 | ir.reg |= rex_r; |
7ad10968 HZ |
5451 | if (ir.mod == 3) |
5452 | { | |
cf648174 | 5453 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5454 | ir.reg &= 0x3; |
25ea693b | 5455 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5456 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5457 | ir.rm &= 0x3; |
25ea693b | 5458 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5459 | } |
5460 | else | |
5461 | { | |
5462 | if (i386_record_lea_modrm (&ir)) | |
5463 | return -1; | |
cf648174 | 5464 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5465 | ir.reg &= 0x3; |
25ea693b | 5466 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5467 | } |
25ea693b | 5468 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5469 | break; |
5470 | ||
a38bba38 | 5471 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5472 | case 0x0fb1: |
5473 | if ((opcode & 1) == 0) | |
5474 | ir.ot = OT_BYTE; | |
5475 | else | |
5476 | ir.ot = ir.dflag + OT_WORD; | |
5477 | if (i386_record_modrm (&ir)) | |
5478 | return -1; | |
5479 | if (ir.mod == 3) | |
5480 | { | |
cf648174 | 5481 | ir.reg |= rex_r; |
25ea693b | 5482 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5483 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5484 | ir.reg &= 0x3; |
25ea693b | 5485 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5486 | } |
5487 | else | |
5488 | { | |
25ea693b | 5489 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5490 | if (i386_record_lea_modrm (&ir)) |
5491 | return -1; | |
5492 | } | |
25ea693b | 5493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5494 | break; |
5495 | ||
20b477a7 | 5496 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5497 | if (i386_record_modrm (&ir)) |
5498 | return -1; | |
5499 | if (ir.mod == 3) | |
5500 | { | |
20b477a7 LM |
5501 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5502 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5503 | has bits 111 (/7). */ | |
5504 | if (ir.reg == 6 || ir.reg == 7) | |
5505 | { | |
5506 | /* The storage register is described by the 3 R/M bits, but the | |
5507 | REX.B prefix may be used to give access to registers | |
5508 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5509 | in the range R8~R15. | |
5510 | ||
5511 | REX.W may also be used to access 64-bit registers, but we | |
5512 | already record entire registers and not just partial bits | |
5513 | of them. */ | |
5514 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5515 | /* These instructions also set conditional bits. */ | |
5516 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5517 | break; | |
5518 | } | |
5519 | else | |
5520 | { | |
5521 | /* We don't handle this particular instruction yet. */ | |
5522 | ir.addr -= 2; | |
5523 | opcode = opcode << 8 | ir.modrm; | |
5524 | goto no_support; | |
5525 | } | |
7ad10968 | 5526 | } |
25ea693b MM |
5527 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5528 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5529 | if (i386_record_lea_modrm (&ir)) |
5530 | return -1; | |
25ea693b | 5531 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5532 | break; |
5533 | ||
a38bba38 | 5534 | case 0x50: /* push */ |
7ad10968 HZ |
5535 | case 0x51: |
5536 | case 0x52: | |
5537 | case 0x53: | |
5538 | case 0x54: | |
5539 | case 0x55: | |
5540 | case 0x56: | |
5541 | case 0x57: | |
5542 | case 0x68: | |
5543 | case 0x6a: | |
cf648174 HZ |
5544 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5545 | ir.dflag = 2; | |
5546 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5547 | return -1; | |
5548 | break; | |
5549 | ||
a38bba38 MS |
5550 | case 0x06: /* push es */ |
5551 | case 0x0e: /* push cs */ | |
5552 | case 0x16: /* push ss */ | |
5553 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5554 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5555 | { | |
5556 | ir.addr -= 1; | |
5557 | goto no_support; | |
5558 | } | |
5559 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5560 | return -1; | |
5561 | break; | |
5562 | ||
a38bba38 MS |
5563 | case 0x0fa0: /* push fs */ |
5564 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5565 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5566 | { | |
5567 | ir.addr -= 2; | |
5568 | goto no_support; | |
5569 | } | |
5570 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5571 | return -1; |
cf648174 HZ |
5572 | break; |
5573 | ||
a38bba38 | 5574 | case 0x60: /* pusha */ |
cf648174 HZ |
5575 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5576 | { | |
5577 | ir.addr -= 1; | |
5578 | goto no_support; | |
5579 | } | |
5580 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5581 | return -1; |
5582 | break; | |
5583 | ||
a38bba38 | 5584 | case 0x58: /* pop */ |
7ad10968 HZ |
5585 | case 0x59: |
5586 | case 0x5a: | |
5587 | case 0x5b: | |
5588 | case 0x5c: | |
5589 | case 0x5d: | |
5590 | case 0x5e: | |
5591 | case 0x5f: | |
25ea693b MM |
5592 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5593 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5594 | break; |
5595 | ||
a38bba38 | 5596 | case 0x61: /* popa */ |
cf648174 HZ |
5597 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5598 | { | |
5599 | ir.addr -= 1; | |
5600 | goto no_support; | |
7ad10968 | 5601 | } |
425b824a MS |
5602 | for (regnum = X86_RECORD_REAX_REGNUM; |
5603 | regnum <= X86_RECORD_REDI_REGNUM; | |
5604 | regnum++) | |
25ea693b | 5605 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5606 | break; |
5607 | ||
a38bba38 | 5608 | case 0x8f: /* pop */ |
cf648174 HZ |
5609 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5610 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5611 | else | |
5612 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5613 | if (i386_record_modrm (&ir)) |
5614 | return -1; | |
5615 | if (ir.mod == 3) | |
25ea693b | 5616 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5617 | else |
5618 | { | |
cf648174 | 5619 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5620 | if (i386_record_lea_modrm (&ir)) |
5621 | return -1; | |
5622 | } | |
25ea693b | 5623 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5624 | break; |
5625 | ||
a38bba38 | 5626 | case 0xc8: /* enter */ |
25ea693b | 5627 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5628 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5629 | ir.dflag = 2; | |
5630 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5631 | return -1; |
5632 | break; | |
5633 | ||
a38bba38 | 5634 | case 0xc9: /* leave */ |
25ea693b MM |
5635 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5636 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5637 | break; |
5638 | ||
a38bba38 | 5639 | case 0x07: /* pop es */ |
cf648174 HZ |
5640 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5641 | { | |
5642 | ir.addr -= 1; | |
5643 | goto no_support; | |
5644 | } | |
25ea693b MM |
5645 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5646 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5647 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5648 | break; |
5649 | ||
a38bba38 | 5650 | case 0x17: /* pop ss */ |
cf648174 HZ |
5651 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5652 | { | |
5653 | ir.addr -= 1; | |
5654 | goto no_support; | |
5655 | } | |
25ea693b MM |
5656 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5657 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5658 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5659 | break; |
5660 | ||
a38bba38 | 5661 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5662 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5663 | { | |
5664 | ir.addr -= 1; | |
5665 | goto no_support; | |
5666 | } | |
25ea693b MM |
5667 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5668 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5669 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5670 | break; |
5671 | ||
a38bba38 | 5672 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5673 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5674 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5675 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5676 | break; |
5677 | ||
a38bba38 | 5678 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5679 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5680 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5682 | break; |
5683 | ||
a38bba38 | 5684 | case 0x88: /* mov */ |
7ad10968 HZ |
5685 | case 0x89: |
5686 | case 0xc6: | |
5687 | case 0xc7: | |
5688 | if ((opcode & 1) == 0) | |
5689 | ir.ot = OT_BYTE; | |
5690 | else | |
5691 | ir.ot = ir.dflag + OT_WORD; | |
5692 | ||
5693 | if (i386_record_modrm (&ir)) | |
5694 | return -1; | |
5695 | ||
5696 | if (ir.mod != 3) | |
5697 | { | |
cf648174 HZ |
5698 | if (opcode == 0xc6 || opcode == 0xc7) |
5699 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5700 | if (i386_record_lea_modrm (&ir)) |
5701 | return -1; | |
5702 | } | |
5703 | else | |
5704 | { | |
cf648174 HZ |
5705 | if (opcode == 0xc6 || opcode == 0xc7) |
5706 | ir.rm |= ir.rex_b; | |
5707 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5708 | ir.rm &= 0x3; |
25ea693b | 5709 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5710 | } |
7ad10968 | 5711 | break; |
cf648174 | 5712 | |
a38bba38 | 5713 | case 0x8a: /* mov */ |
7ad10968 HZ |
5714 | case 0x8b: |
5715 | if ((opcode & 1) == 0) | |
5716 | ir.ot = OT_BYTE; | |
5717 | else | |
5718 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5719 | if (i386_record_modrm (&ir)) |
5720 | return -1; | |
cf648174 HZ |
5721 | ir.reg |= rex_r; |
5722 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5723 | ir.reg &= 0x3; |
25ea693b | 5724 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5725 | break; |
7ad10968 | 5726 | |
a38bba38 | 5727 | case 0x8c: /* mov seg */ |
cf648174 | 5728 | if (i386_record_modrm (&ir)) |
7ad10968 | 5729 | return -1; |
cf648174 HZ |
5730 | if (ir.reg > 5) |
5731 | { | |
5732 | ir.addr -= 2; | |
5733 | opcode = opcode << 8 | ir.modrm; | |
5734 | goto no_support; | |
5735 | } | |
5736 | ||
5737 | if (ir.mod == 3) | |
25ea693b | 5738 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5739 | else |
5740 | { | |
5741 | ir.ot = OT_WORD; | |
5742 | if (i386_record_lea_modrm (&ir)) | |
5743 | return -1; | |
5744 | } | |
7ad10968 HZ |
5745 | break; |
5746 | ||
a38bba38 | 5747 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5748 | if (i386_record_modrm (&ir)) |
5749 | return -1; | |
7ad10968 HZ |
5750 | switch (ir.reg) |
5751 | { | |
5752 | case 0: | |
425b824a | 5753 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5754 | break; |
5755 | case 2: | |
425b824a | 5756 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5757 | break; |
5758 | case 3: | |
425b824a | 5759 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5760 | break; |
5761 | case 4: | |
425b824a | 5762 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5763 | break; |
5764 | case 5: | |
425b824a | 5765 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5766 | break; |
5767 | default: | |
5768 | ir.addr -= 2; | |
5769 | opcode = opcode << 8 | ir.modrm; | |
5770 | goto no_support; | |
5771 | break; | |
5772 | } | |
25ea693b MM |
5773 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5774 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5775 | break; |
5776 | ||
a38bba38 MS |
5777 | case 0x0fb6: /* movzbS */ |
5778 | case 0x0fb7: /* movzwS */ | |
5779 | case 0x0fbe: /* movsbS */ | |
5780 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5781 | if (i386_record_modrm (&ir)) |
5782 | return -1; | |
25ea693b | 5783 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5784 | break; |
5785 | ||
a38bba38 | 5786 | case 0x8d: /* lea */ |
7ad10968 HZ |
5787 | if (i386_record_modrm (&ir)) |
5788 | return -1; | |
5789 | if (ir.mod == 3) | |
5790 | { | |
5791 | ir.addr -= 2; | |
5792 | opcode = opcode << 8 | ir.modrm; | |
5793 | goto no_support; | |
5794 | } | |
7ad10968 | 5795 | ir.ot = ir.dflag; |
cf648174 HZ |
5796 | ir.reg |= rex_r; |
5797 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5798 | ir.reg &= 0x3; |
25ea693b | 5799 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5800 | break; |
5801 | ||
a38bba38 | 5802 | case 0xa0: /* mov EAX */ |
7ad10968 | 5803 | case 0xa1: |
a38bba38 MS |
5804 | |
5805 | case 0xd7: /* xlat */ | |
25ea693b | 5806 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5807 | break; |
5808 | ||
a38bba38 | 5809 | case 0xa2: /* mov EAX */ |
7ad10968 | 5810 | case 0xa3: |
d7877f7e | 5811 | if (ir.override >= 0) |
cf648174 | 5812 | { |
25ea693b | 5813 | if (record_full_memory_query) |
bb08c432 | 5814 | { |
651ce16a | 5815 | if (yquery (_("\ |
bb08c432 HZ |
5816 | Process record ignores the memory change of instruction at address %s\n\ |
5817 | because it can't get the value of the segment register.\n\ | |
5818 | Do you want to stop the program?"), | |
651ce16a | 5819 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
5820 | return -1; |
5821 | } | |
cf648174 HZ |
5822 | } |
5823 | else | |
5824 | { | |
5825 | if ((opcode & 1) == 0) | |
5826 | ir.ot = OT_BYTE; | |
5827 | else | |
5828 | ir.ot = ir.dflag + OT_WORD; | |
5829 | if (ir.aflag == 2) | |
5830 | { | |
4ffa4fc7 PA |
5831 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5832 | return -1; | |
cf648174 | 5833 | ir.addr += 8; |
60a1502a | 5834 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5835 | } |
5836 | else if (ir.aflag) | |
5837 | { | |
4ffa4fc7 PA |
5838 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5839 | return -1; | |
cf648174 | 5840 | ir.addr += 4; |
60a1502a | 5841 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5842 | } |
5843 | else | |
5844 | { | |
4ffa4fc7 PA |
5845 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5846 | return -1; | |
cf648174 | 5847 | ir.addr += 2; |
60a1502a | 5848 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5849 | } |
25ea693b | 5850 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5851 | return -1; |
5852 | } | |
7ad10968 HZ |
5853 | break; |
5854 | ||
a38bba38 | 5855 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5856 | case 0xb1: |
5857 | case 0xb2: | |
5858 | case 0xb3: | |
5859 | case 0xb4: | |
5860 | case 0xb5: | |
5861 | case 0xb6: | |
5862 | case 0xb7: | |
25ea693b MM |
5863 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5864 | ? ((opcode & 0x7) | ir.rex_b) | |
5865 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5866 | break; |
5867 | ||
a38bba38 | 5868 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5869 | case 0xb9: |
5870 | case 0xba: | |
5871 | case 0xbb: | |
5872 | case 0xbc: | |
5873 | case 0xbd: | |
5874 | case 0xbe: | |
5875 | case 0xbf: | |
25ea693b | 5876 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5877 | break; |
5878 | ||
a38bba38 | 5879 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5880 | case 0x92: |
5881 | case 0x93: | |
5882 | case 0x94: | |
5883 | case 0x95: | |
5884 | case 0x96: | |
5885 | case 0x97: | |
25ea693b MM |
5886 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5887 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5888 | break; |
5889 | ||
a38bba38 | 5890 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5891 | case 0x87: |
5892 | if ((opcode & 1) == 0) | |
5893 | ir.ot = OT_BYTE; | |
5894 | else | |
5895 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5896 | if (i386_record_modrm (&ir)) |
5897 | return -1; | |
7ad10968 HZ |
5898 | if (ir.mod == 3) |
5899 | { | |
86839d38 | 5900 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5901 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5902 | ir.rm &= 0x3; | |
25ea693b | 5903 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5904 | } |
5905 | else | |
5906 | { | |
5907 | if (i386_record_lea_modrm (&ir)) | |
5908 | return -1; | |
5909 | } | |
cf648174 HZ |
5910 | ir.reg |= rex_r; |
5911 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5912 | ir.reg &= 0x3; |
25ea693b | 5913 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5914 | break; |
5915 | ||
a38bba38 MS |
5916 | case 0xc4: /* les Gv */ |
5917 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5918 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5919 | { | |
5920 | ir.addr -= 1; | |
5921 | goto no_support; | |
5922 | } | |
d3f323f3 | 5923 | /* FALLTHROUGH */ |
a38bba38 MS |
5924 | case 0x0fb2: /* lss Gv */ |
5925 | case 0x0fb4: /* lfs Gv */ | |
5926 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5927 | if (i386_record_modrm (&ir)) |
5928 | return -1; | |
5929 | if (ir.mod == 3) | |
5930 | { | |
5931 | if (opcode > 0xff) | |
5932 | ir.addr -= 3; | |
5933 | else | |
5934 | ir.addr -= 2; | |
5935 | opcode = opcode << 8 | ir.modrm; | |
5936 | goto no_support; | |
5937 | } | |
7ad10968 HZ |
5938 | switch (opcode) |
5939 | { | |
a38bba38 | 5940 | case 0xc4: /* les Gv */ |
425b824a | 5941 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5942 | break; |
a38bba38 | 5943 | case 0xc5: /* lds Gv */ |
425b824a | 5944 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5945 | break; |
a38bba38 | 5946 | case 0x0fb2: /* lss Gv */ |
425b824a | 5947 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5948 | break; |
a38bba38 | 5949 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5950 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5951 | break; |
a38bba38 | 5952 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5953 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5954 | break; |
5955 | } | |
25ea693b MM |
5956 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5957 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5958 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5959 | break; |
5960 | ||
a38bba38 | 5961 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5962 | case 0xc1: |
5963 | case 0xd0: | |
5964 | case 0xd1: | |
5965 | case 0xd2: | |
5966 | case 0xd3: | |
5967 | if ((opcode & 1) == 0) | |
5968 | ir.ot = OT_BYTE; | |
5969 | else | |
5970 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5971 | if (i386_record_modrm (&ir)) |
5972 | return -1; | |
7ad10968 HZ |
5973 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5974 | { | |
5975 | if (i386_record_lea_modrm (&ir)) | |
5976 | return -1; | |
5977 | } | |
5978 | else | |
5979 | { | |
cf648174 HZ |
5980 | ir.rm |= ir.rex_b; |
5981 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5982 | ir.rm &= 0x3; |
25ea693b | 5983 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5984 | } |
25ea693b | 5985 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5986 | break; |
5987 | ||
5988 | case 0x0fa4: | |
5989 | case 0x0fa5: | |
5990 | case 0x0fac: | |
5991 | case 0x0fad: | |
5992 | if (i386_record_modrm (&ir)) | |
5993 | return -1; | |
5994 | if (ir.mod == 3) | |
5995 | { | |
25ea693b | 5996 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5997 | return -1; |
5998 | } | |
5999 | else | |
6000 | { | |
6001 | if (i386_record_lea_modrm (&ir)) | |
6002 | return -1; | |
6003 | } | |
6004 | break; | |
6005 | ||
a38bba38 | 6006 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
6007 | case 0xd9: |
6008 | case 0xda: | |
6009 | case 0xdb: | |
6010 | case 0xdc: | |
6011 | case 0xdd: | |
6012 | case 0xde: | |
6013 | case 0xdf: | |
6014 | if (i386_record_modrm (&ir)) | |
6015 | return -1; | |
6016 | ir.reg |= ((opcode & 7) << 3); | |
6017 | if (ir.mod != 3) | |
6018 | { | |
1777feb0 | 6019 | /* Memory. */ |
955db0c0 | 6020 | uint64_t addr64; |
7ad10968 | 6021 | |
955db0c0 | 6022 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6023 | return -1; |
6024 | switch (ir.reg) | |
6025 | { | |
7ad10968 | 6026 | case 0x02: |
0289bdd7 MS |
6027 | case 0x12: |
6028 | case 0x22: | |
6029 | case 0x32: | |
6030 | /* For fcom, ficom nothing to do. */ | |
6031 | break; | |
7ad10968 | 6032 | case 0x03: |
0289bdd7 MS |
6033 | case 0x13: |
6034 | case 0x23: | |
6035 | case 0x33: | |
6036 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
6037 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6038 | return -1; | |
6039 | break; | |
6040 | case 0x00: | |
6041 | case 0x01: | |
7ad10968 HZ |
6042 | case 0x04: |
6043 | case 0x05: | |
6044 | case 0x06: | |
6045 | case 0x07: | |
6046 | case 0x10: | |
6047 | case 0x11: | |
7ad10968 HZ |
6048 | case 0x14: |
6049 | case 0x15: | |
6050 | case 0x16: | |
6051 | case 0x17: | |
6052 | case 0x20: | |
6053 | case 0x21: | |
7ad10968 HZ |
6054 | case 0x24: |
6055 | case 0x25: | |
6056 | case 0x26: | |
6057 | case 0x27: | |
6058 | case 0x30: | |
6059 | case 0x31: | |
7ad10968 HZ |
6060 | case 0x34: |
6061 | case 0x35: | |
6062 | case 0x36: | |
6063 | case 0x37: | |
0289bdd7 MS |
6064 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6065 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6066 | of code, always affects st(0) register. */ | |
6067 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6068 | return -1; | |
7ad10968 HZ |
6069 | break; |
6070 | case 0x08: | |
6071 | case 0x0a: | |
6072 | case 0x0b: | |
6073 | case 0x18: | |
6074 | case 0x19: | |
6075 | case 0x1a: | |
6076 | case 0x1b: | |
0289bdd7 | 6077 | case 0x1d: |
7ad10968 HZ |
6078 | case 0x28: |
6079 | case 0x29: | |
6080 | case 0x2a: | |
6081 | case 0x2b: | |
6082 | case 0x38: | |
6083 | case 0x39: | |
6084 | case 0x3a: | |
6085 | case 0x3b: | |
0289bdd7 MS |
6086 | case 0x3c: |
6087 | case 0x3d: | |
7ad10968 HZ |
6088 | switch (ir.reg & 7) |
6089 | { | |
6090 | case 0: | |
0289bdd7 MS |
6091 | /* Handling fld, fild. */ |
6092 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6093 | return -1; | |
7ad10968 HZ |
6094 | break; |
6095 | case 1: | |
6096 | switch (ir.reg >> 4) | |
6097 | { | |
6098 | case 0: | |
25ea693b | 6099 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6100 | return -1; |
6101 | break; | |
6102 | case 2: | |
25ea693b | 6103 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6104 | return -1; |
6105 | break; | |
6106 | case 3: | |
0289bdd7 | 6107 | break; |
7ad10968 | 6108 | default: |
25ea693b | 6109 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6110 | return -1; |
6111 | break; | |
6112 | } | |
6113 | break; | |
6114 | default: | |
6115 | switch (ir.reg >> 4) | |
6116 | { | |
6117 | case 0: | |
25ea693b | 6118 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6119 | return -1; |
6120 | if (3 == (ir.reg & 7)) | |
6121 | { | |
6122 | /* For fstp m32fp. */ | |
6123 | if (i386_record_floats (gdbarch, &ir, | |
6124 | I386_SAVE_FPU_REGS)) | |
6125 | return -1; | |
6126 | } | |
6127 | break; | |
7ad10968 | 6128 | case 1: |
25ea693b | 6129 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6130 | return -1; |
0289bdd7 MS |
6131 | if ((3 == (ir.reg & 7)) |
6132 | || (5 == (ir.reg & 7)) | |
6133 | || (7 == (ir.reg & 7))) | |
6134 | { | |
6135 | /* For fstp insn. */ | |
6136 | if (i386_record_floats (gdbarch, &ir, | |
6137 | I386_SAVE_FPU_REGS)) | |
6138 | return -1; | |
6139 | } | |
7ad10968 HZ |
6140 | break; |
6141 | case 2: | |
25ea693b | 6142 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6143 | return -1; |
0289bdd7 MS |
6144 | if (3 == (ir.reg & 7)) |
6145 | { | |
6146 | /* For fstp m64fp. */ | |
6147 | if (i386_record_floats (gdbarch, &ir, | |
6148 | I386_SAVE_FPU_REGS)) | |
6149 | return -1; | |
6150 | } | |
7ad10968 HZ |
6151 | break; |
6152 | case 3: | |
0289bdd7 MS |
6153 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6154 | { | |
6155 | /* For fistp, fbld, fild, fbstp. */ | |
6156 | if (i386_record_floats (gdbarch, &ir, | |
6157 | I386_SAVE_FPU_REGS)) | |
6158 | return -1; | |
6159 | } | |
6160 | /* Fall through */ | |
7ad10968 | 6161 | default: |
25ea693b | 6162 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6163 | return -1; |
6164 | break; | |
6165 | } | |
6166 | break; | |
6167 | } | |
6168 | break; | |
6169 | case 0x0c: | |
0289bdd7 MS |
6170 | /* Insn fldenv. */ |
6171 | if (i386_record_floats (gdbarch, &ir, | |
6172 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6173 | return -1; | |
6174 | break; | |
7ad10968 | 6175 | case 0x0d: |
0289bdd7 MS |
6176 | /* Insn fldcw. */ |
6177 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6178 | return -1; | |
6179 | break; | |
7ad10968 | 6180 | case 0x2c: |
0289bdd7 MS |
6181 | /* Insn frstor. */ |
6182 | if (i386_record_floats (gdbarch, &ir, | |
6183 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6184 | return -1; | |
7ad10968 HZ |
6185 | break; |
6186 | case 0x0e: | |
6187 | if (ir.dflag) | |
6188 | { | |
25ea693b | 6189 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6190 | return -1; |
6191 | } | |
6192 | else | |
6193 | { | |
25ea693b | 6194 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6195 | return -1; |
6196 | } | |
6197 | break; | |
6198 | case 0x0f: | |
6199 | case 0x2f: | |
25ea693b | 6200 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6201 | return -1; |
0289bdd7 MS |
6202 | /* Insn fstp, fbstp. */ |
6203 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6204 | return -1; | |
7ad10968 HZ |
6205 | break; |
6206 | case 0x1f: | |
6207 | case 0x3e: | |
25ea693b | 6208 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6209 | return -1; |
6210 | break; | |
6211 | case 0x2e: | |
6212 | if (ir.dflag) | |
6213 | { | |
25ea693b | 6214 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6215 | return -1; |
955db0c0 | 6216 | addr64 += 28; |
7ad10968 HZ |
6217 | } |
6218 | else | |
6219 | { | |
25ea693b | 6220 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6221 | return -1; |
955db0c0 | 6222 | addr64 += 14; |
7ad10968 | 6223 | } |
25ea693b | 6224 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6225 | return -1; |
0289bdd7 MS |
6226 | /* Insn fsave. */ |
6227 | if (i386_record_floats (gdbarch, &ir, | |
6228 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6229 | return -1; | |
7ad10968 HZ |
6230 | break; |
6231 | case 0x3f: | |
25ea693b | 6232 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6233 | return -1; |
0289bdd7 MS |
6234 | /* Insn fistp. */ |
6235 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6236 | return -1; | |
7ad10968 HZ |
6237 | break; |
6238 | default: | |
6239 | ir.addr -= 2; | |
6240 | opcode = opcode << 8 | ir.modrm; | |
6241 | goto no_support; | |
6242 | break; | |
6243 | } | |
6244 | } | |
0289bdd7 MS |
6245 | /* Opcode is an extension of modR/M byte. */ |
6246 | else | |
6247 | { | |
6248 | switch (opcode) | |
6249 | { | |
6250 | case 0xd8: | |
6251 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6252 | return -1; | |
6253 | break; | |
6254 | case 0xd9: | |
6255 | if (0x0c == (ir.modrm >> 4)) | |
6256 | { | |
6257 | if ((ir.modrm & 0x0f) <= 7) | |
6258 | { | |
6259 | if (i386_record_floats (gdbarch, &ir, | |
6260 | I386_SAVE_FPU_REGS)) | |
6261 | return -1; | |
6262 | } | |
6263 | else | |
6264 | { | |
6265 | if (i386_record_floats (gdbarch, &ir, | |
6266 | I387_ST0_REGNUM (tdep))) | |
6267 | return -1; | |
6268 | /* If only st(0) is changing, then we have already | |
6269 | recorded. */ | |
6270 | if ((ir.modrm & 0x0f) - 0x08) | |
6271 | { | |
6272 | if (i386_record_floats (gdbarch, &ir, | |
6273 | I387_ST0_REGNUM (tdep) + | |
6274 | ((ir.modrm & 0x0f) - 0x08))) | |
6275 | return -1; | |
6276 | } | |
6277 | } | |
6278 | } | |
6279 | else | |
6280 | { | |
6281 | switch (ir.modrm) | |
6282 | { | |
6283 | case 0xe0: | |
6284 | case 0xe1: | |
6285 | case 0xf0: | |
6286 | case 0xf5: | |
6287 | case 0xf8: | |
6288 | case 0xfa: | |
6289 | case 0xfc: | |
6290 | case 0xfe: | |
6291 | case 0xff: | |
6292 | if (i386_record_floats (gdbarch, &ir, | |
6293 | I387_ST0_REGNUM (tdep))) | |
6294 | return -1; | |
6295 | break; | |
6296 | case 0xf1: | |
6297 | case 0xf2: | |
6298 | case 0xf3: | |
6299 | case 0xf4: | |
6300 | case 0xf6: | |
6301 | case 0xf7: | |
6302 | case 0xe8: | |
6303 | case 0xe9: | |
6304 | case 0xea: | |
6305 | case 0xeb: | |
6306 | case 0xec: | |
6307 | case 0xed: | |
6308 | case 0xee: | |
6309 | case 0xf9: | |
6310 | case 0xfb: | |
6311 | if (i386_record_floats (gdbarch, &ir, | |
6312 | I386_SAVE_FPU_REGS)) | |
6313 | return -1; | |
6314 | break; | |
6315 | case 0xfd: | |
6316 | if (i386_record_floats (gdbarch, &ir, | |
6317 | I387_ST0_REGNUM (tdep))) | |
6318 | return -1; | |
6319 | if (i386_record_floats (gdbarch, &ir, | |
6320 | I387_ST0_REGNUM (tdep) + 1)) | |
6321 | return -1; | |
6322 | break; | |
6323 | } | |
6324 | } | |
6325 | break; | |
6326 | case 0xda: | |
6327 | if (0xe9 == ir.modrm) | |
6328 | { | |
6329 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6330 | return -1; | |
6331 | } | |
6332 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6333 | { | |
6334 | if (i386_record_floats (gdbarch, &ir, | |
6335 | I387_ST0_REGNUM (tdep))) | |
6336 | return -1; | |
6337 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6338 | { | |
6339 | if (i386_record_floats (gdbarch, &ir, | |
6340 | I387_ST0_REGNUM (tdep) + | |
6341 | (ir.modrm & 0x0f))) | |
6342 | return -1; | |
6343 | } | |
6344 | else if ((ir.modrm & 0x0f) - 0x08) | |
6345 | { | |
6346 | if (i386_record_floats (gdbarch, &ir, | |
6347 | I387_ST0_REGNUM (tdep) + | |
6348 | ((ir.modrm & 0x0f) - 0x08))) | |
6349 | return -1; | |
6350 | } | |
6351 | } | |
6352 | break; | |
6353 | case 0xdb: | |
6354 | if (0xe3 == ir.modrm) | |
6355 | { | |
6356 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6357 | return -1; | |
6358 | } | |
6359 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6360 | { | |
6361 | if (i386_record_floats (gdbarch, &ir, | |
6362 | I387_ST0_REGNUM (tdep))) | |
6363 | return -1; | |
6364 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6365 | { | |
6366 | if (i386_record_floats (gdbarch, &ir, | |
6367 | I387_ST0_REGNUM (tdep) + | |
6368 | (ir.modrm & 0x0f))) | |
6369 | return -1; | |
6370 | } | |
6371 | else if ((ir.modrm & 0x0f) - 0x08) | |
6372 | { | |
6373 | if (i386_record_floats (gdbarch, &ir, | |
6374 | I387_ST0_REGNUM (tdep) + | |
6375 | ((ir.modrm & 0x0f) - 0x08))) | |
6376 | return -1; | |
6377 | } | |
6378 | } | |
6379 | break; | |
6380 | case 0xdc: | |
6381 | if ((0x0c == ir.modrm >> 4) | |
6382 | || (0x0d == ir.modrm >> 4) | |
6383 | || (0x0f == ir.modrm >> 4)) | |
6384 | { | |
6385 | if ((ir.modrm & 0x0f) <= 7) | |
6386 | { | |
6387 | if (i386_record_floats (gdbarch, &ir, | |
6388 | I387_ST0_REGNUM (tdep) + | |
6389 | (ir.modrm & 0x0f))) | |
6390 | return -1; | |
6391 | } | |
6392 | else | |
6393 | { | |
6394 | if (i386_record_floats (gdbarch, &ir, | |
6395 | I387_ST0_REGNUM (tdep) + | |
6396 | ((ir.modrm & 0x0f) - 0x08))) | |
6397 | return -1; | |
6398 | } | |
6399 | } | |
6400 | break; | |
6401 | case 0xdd: | |
6402 | if (0x0c == ir.modrm >> 4) | |
6403 | { | |
6404 | if (i386_record_floats (gdbarch, &ir, | |
6405 | I387_FTAG_REGNUM (tdep))) | |
6406 | return -1; | |
6407 | } | |
6408 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6409 | { | |
6410 | if ((ir.modrm & 0x0f) <= 7) | |
6411 | { | |
6412 | if (i386_record_floats (gdbarch, &ir, | |
6413 | I387_ST0_REGNUM (tdep) + | |
6414 | (ir.modrm & 0x0f))) | |
6415 | return -1; | |
6416 | } | |
6417 | else | |
6418 | { | |
6419 | if (i386_record_floats (gdbarch, &ir, | |
6420 | I386_SAVE_FPU_REGS)) | |
6421 | return -1; | |
6422 | } | |
6423 | } | |
6424 | break; | |
6425 | case 0xde: | |
6426 | if ((0x0c == ir.modrm >> 4) | |
6427 | || (0x0e == ir.modrm >> 4) | |
6428 | || (0x0f == ir.modrm >> 4) | |
6429 | || (0xd9 == ir.modrm)) | |
6430 | { | |
6431 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6432 | return -1; | |
6433 | } | |
6434 | break; | |
6435 | case 0xdf: | |
6436 | if (0xe0 == ir.modrm) | |
6437 | { | |
25ea693b MM |
6438 | if (record_full_arch_list_add_reg (ir.regcache, |
6439 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6440 | return -1; |
6441 | } | |
6442 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6443 | { | |
6444 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6445 | return -1; | |
6446 | } | |
6447 | break; | |
6448 | } | |
6449 | } | |
7ad10968 | 6450 | break; |
7ad10968 | 6451 | /* string ops */ |
a38bba38 | 6452 | case 0xa4: /* movsS */ |
7ad10968 | 6453 | case 0xa5: |
a38bba38 | 6454 | case 0xaa: /* stosS */ |
7ad10968 | 6455 | case 0xab: |
a38bba38 | 6456 | case 0x6c: /* insS */ |
7ad10968 | 6457 | case 0x6d: |
cf648174 | 6458 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6459 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6460 | &addr); |
6461 | if (addr) | |
cf648174 | 6462 | { |
77d7dc92 HZ |
6463 | ULONGEST es, ds; |
6464 | ||
6465 | if ((opcode & 1) == 0) | |
6466 | ir.ot = OT_BYTE; | |
6467 | else | |
6468 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6469 | regcache_raw_read_unsigned (ir.regcache, |
6470 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6471 | &addr); |
77d7dc92 | 6472 | |
d7877f7e HZ |
6473 | regcache_raw_read_unsigned (ir.regcache, |
6474 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6475 | &es); | |
6476 | regcache_raw_read_unsigned (ir.regcache, | |
6477 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6478 | &ds); | |
6479 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6480 | { |
6481 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6482 | if (record_full_memory_query) |
bb08c432 | 6483 | { |
651ce16a | 6484 | if (yquery (_("\ |
bb08c432 HZ |
6485 | Process record ignores the memory change of instruction at address %s\n\ |
6486 | because it can't get the value of the segment register.\n\ | |
6487 | Do you want to stop the program?"), | |
651ce16a | 6488 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
6489 | return -1; |
6490 | } | |
df61f520 HZ |
6491 | } |
6492 | else | |
6493 | { | |
25ea693b | 6494 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6495 | return -1; |
77d7dc92 HZ |
6496 | } |
6497 | ||
6498 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6499 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6500 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6501 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6502 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6504 | } |
cf648174 | 6505 | break; |
7ad10968 | 6506 | |
a38bba38 | 6507 | case 0xa6: /* cmpsS */ |
cf648174 | 6508 | case 0xa7: |
25ea693b MM |
6509 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6510 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6511 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6512 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6513 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6514 | break; |
6515 | ||
a38bba38 | 6516 | case 0xac: /* lodsS */ |
7ad10968 | 6517 | case 0xad: |
25ea693b MM |
6518 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6519 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6520 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6522 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6523 | break; |
6524 | ||
a38bba38 | 6525 | case 0xae: /* scasS */ |
7ad10968 | 6526 | case 0xaf: |
25ea693b | 6527 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6528 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6529 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6530 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6531 | break; |
6532 | ||
a38bba38 | 6533 | case 0x6e: /* outsS */ |
cf648174 | 6534 | case 0x6f: |
25ea693b | 6535 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6536 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6537 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6538 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6539 | break; |
6540 | ||
a38bba38 | 6541 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6542 | case 0xe5: |
6543 | case 0xec: | |
6544 | case 0xed: | |
25ea693b MM |
6545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6546 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6547 | break; |
6548 | ||
6549 | case 0xe6: | |
6550 | case 0xe7: | |
6551 | case 0xee: | |
6552 | case 0xef: | |
6553 | break; | |
6554 | ||
6555 | /* control */ | |
a38bba38 MS |
6556 | case 0xc2: /* ret im */ |
6557 | case 0xc3: /* ret */ | |
25ea693b MM |
6558 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6559 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6560 | break; |
6561 | ||
a38bba38 MS |
6562 | case 0xca: /* lret im */ |
6563 | case 0xcb: /* lret */ | |
6564 | case 0xcf: /* iret */ | |
25ea693b MM |
6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6566 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6567 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6568 | break; |
6569 | ||
a38bba38 | 6570 | case 0xe8: /* call im */ |
cf648174 HZ |
6571 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6572 | ir.dflag = 2; | |
6573 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6574 | return -1; | |
7ad10968 HZ |
6575 | break; |
6576 | ||
a38bba38 | 6577 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6578 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6579 | { | |
6580 | ir.addr -= 1; | |
6581 | goto no_support; | |
6582 | } | |
25ea693b | 6583 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6584 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6585 | return -1; | |
7ad10968 HZ |
6586 | break; |
6587 | ||
a38bba38 MS |
6588 | case 0xe9: /* jmp im */ |
6589 | case 0xea: /* ljmp im */ | |
6590 | case 0xeb: /* jmp Jb */ | |
6591 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6592 | case 0x71: |
6593 | case 0x72: | |
6594 | case 0x73: | |
6595 | case 0x74: | |
6596 | case 0x75: | |
6597 | case 0x76: | |
6598 | case 0x77: | |
6599 | case 0x78: | |
6600 | case 0x79: | |
6601 | case 0x7a: | |
6602 | case 0x7b: | |
6603 | case 0x7c: | |
6604 | case 0x7d: | |
6605 | case 0x7e: | |
6606 | case 0x7f: | |
a38bba38 | 6607 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6608 | case 0x0f81: |
6609 | case 0x0f82: | |
6610 | case 0x0f83: | |
6611 | case 0x0f84: | |
6612 | case 0x0f85: | |
6613 | case 0x0f86: | |
6614 | case 0x0f87: | |
6615 | case 0x0f88: | |
6616 | case 0x0f89: | |
6617 | case 0x0f8a: | |
6618 | case 0x0f8b: | |
6619 | case 0x0f8c: | |
6620 | case 0x0f8d: | |
6621 | case 0x0f8e: | |
6622 | case 0x0f8f: | |
6623 | break; | |
6624 | ||
a38bba38 | 6625 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6626 | case 0x0f91: |
6627 | case 0x0f92: | |
6628 | case 0x0f93: | |
6629 | case 0x0f94: | |
6630 | case 0x0f95: | |
6631 | case 0x0f96: | |
6632 | case 0x0f97: | |
6633 | case 0x0f98: | |
6634 | case 0x0f99: | |
6635 | case 0x0f9a: | |
6636 | case 0x0f9b: | |
6637 | case 0x0f9c: | |
6638 | case 0x0f9d: | |
6639 | case 0x0f9e: | |
6640 | case 0x0f9f: | |
25ea693b | 6641 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6642 | ir.ot = OT_BYTE; |
6643 | if (i386_record_modrm (&ir)) | |
6644 | return -1; | |
6645 | if (ir.mod == 3) | |
25ea693b MM |
6646 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6647 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6648 | else |
6649 | { | |
6650 | if (i386_record_lea_modrm (&ir)) | |
6651 | return -1; | |
6652 | } | |
6653 | break; | |
6654 | ||
a38bba38 | 6655 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6656 | case 0x0f41: |
6657 | case 0x0f42: | |
6658 | case 0x0f43: | |
6659 | case 0x0f44: | |
6660 | case 0x0f45: | |
6661 | case 0x0f46: | |
6662 | case 0x0f47: | |
6663 | case 0x0f48: | |
6664 | case 0x0f49: | |
6665 | case 0x0f4a: | |
6666 | case 0x0f4b: | |
6667 | case 0x0f4c: | |
6668 | case 0x0f4d: | |
6669 | case 0x0f4e: | |
6670 | case 0x0f4f: | |
6671 | if (i386_record_modrm (&ir)) | |
6672 | return -1; | |
cf648174 | 6673 | ir.reg |= rex_r; |
7ad10968 HZ |
6674 | if (ir.dflag == OT_BYTE) |
6675 | ir.reg &= 0x3; | |
25ea693b | 6676 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6677 | break; |
6678 | ||
6679 | /* flags */ | |
a38bba38 | 6680 | case 0x9c: /* pushf */ |
25ea693b | 6681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6682 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6683 | ir.dflag = 2; | |
6684 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6685 | return -1; | |
7ad10968 HZ |
6686 | break; |
6687 | ||
a38bba38 | 6688 | case 0x9d: /* popf */ |
25ea693b MM |
6689 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6690 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6691 | break; |
6692 | ||
a38bba38 | 6693 | case 0x9e: /* sahf */ |
cf648174 HZ |
6694 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6695 | { | |
6696 | ir.addr -= 1; | |
6697 | goto no_support; | |
6698 | } | |
d3f323f3 | 6699 | /* FALLTHROUGH */ |
a38bba38 MS |
6700 | case 0xf5: /* cmc */ |
6701 | case 0xf8: /* clc */ | |
6702 | case 0xf9: /* stc */ | |
6703 | case 0xfc: /* cld */ | |
6704 | case 0xfd: /* std */ | |
25ea693b | 6705 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6706 | break; |
6707 | ||
a38bba38 | 6708 | case 0x9f: /* lahf */ |
cf648174 HZ |
6709 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6710 | { | |
6711 | ir.addr -= 1; | |
6712 | goto no_support; | |
6713 | } | |
25ea693b MM |
6714 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6715 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6716 | break; |
6717 | ||
6718 | /* bit operations */ | |
a38bba38 | 6719 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6720 | ir.ot = ir.dflag + OT_WORD; |
6721 | if (i386_record_modrm (&ir)) | |
6722 | return -1; | |
6723 | if (ir.reg < 4) | |
6724 | { | |
cf648174 | 6725 | ir.addr -= 2; |
7ad10968 HZ |
6726 | opcode = opcode << 8 | ir.modrm; |
6727 | goto no_support; | |
6728 | } | |
cf648174 | 6729 | if (ir.reg != 4) |
7ad10968 | 6730 | { |
cf648174 | 6731 | if (ir.mod == 3) |
25ea693b | 6732 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6733 | else |
6734 | { | |
cf648174 | 6735 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6736 | return -1; |
6737 | } | |
6738 | } | |
25ea693b | 6739 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6740 | break; |
6741 | ||
a38bba38 | 6742 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6743 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6744 | break; |
6745 | ||
a38bba38 MS |
6746 | case 0x0fab: /* bts */ |
6747 | case 0x0fb3: /* btr */ | |
6748 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6749 | ir.ot = ir.dflag + OT_WORD; |
6750 | if (i386_record_modrm (&ir)) | |
6751 | return -1; | |
6752 | if (ir.mod == 3) | |
25ea693b | 6753 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6754 | else |
6755 | { | |
955db0c0 MS |
6756 | uint64_t addr64; |
6757 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6758 | return -1; |
6759 | regcache_raw_read_unsigned (ir.regcache, | |
6760 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6761 | &addr); |
cf648174 HZ |
6762 | switch (ir.dflag) |
6763 | { | |
6764 | case 0: | |
648d0c8b | 6765 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6766 | break; |
6767 | case 1: | |
648d0c8b | 6768 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6769 | break; |
6770 | case 2: | |
648d0c8b | 6771 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6772 | break; |
6773 | } | |
25ea693b | 6774 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6775 | return -1; |
6776 | if (i386_record_lea_modrm (&ir)) | |
6777 | return -1; | |
6778 | } | |
25ea693b | 6779 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6780 | break; |
6781 | ||
a38bba38 MS |
6782 | case 0x0fbc: /* bsf */ |
6783 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6784 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6785 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6786 | break; |
6787 | ||
6788 | /* bcd */ | |
a38bba38 MS |
6789 | case 0x27: /* daa */ |
6790 | case 0x2f: /* das */ | |
6791 | case 0x37: /* aaa */ | |
6792 | case 0x3f: /* aas */ | |
6793 | case 0xd4: /* aam */ | |
6794 | case 0xd5: /* aad */ | |
cf648174 HZ |
6795 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6796 | { | |
6797 | ir.addr -= 1; | |
6798 | goto no_support; | |
6799 | } | |
25ea693b MM |
6800 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6801 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6802 | break; |
6803 | ||
6804 | /* misc */ | |
a38bba38 | 6805 | case 0x90: /* nop */ |
7ad10968 HZ |
6806 | if (prefixes & PREFIX_LOCK) |
6807 | { | |
6808 | ir.addr -= 1; | |
6809 | goto no_support; | |
6810 | } | |
6811 | break; | |
6812 | ||
a38bba38 | 6813 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6814 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6815 | return -1; | |
425b824a | 6816 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6817 | ir.addr++; |
6818 | goto reswitch; | |
7ad10968 HZ |
6819 | break; |
6820 | ||
7ad10968 | 6821 | /* XXX */ |
a38bba38 | 6822 | case 0xcc: /* int3 */ |
a3c4230a | 6823 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6824 | "int3.\n")); |
6825 | ir.addr -= 1; | |
6826 | goto no_support; | |
6827 | break; | |
6828 | ||
7ad10968 | 6829 | /* XXX */ |
a38bba38 | 6830 | case 0xcd: /* int */ |
7ad10968 HZ |
6831 | { |
6832 | int ret; | |
425b824a | 6833 | uint8_t interrupt; |
4ffa4fc7 PA |
6834 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6835 | return -1; | |
7ad10968 | 6836 | ir.addr++; |
425b824a | 6837 | if (interrupt != 0x80 |
a3c4230a | 6838 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6839 | { |
a3c4230a | 6840 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6841 | "instruction int 0x%02x.\n"), |
425b824a | 6842 | interrupt); |
7ad10968 HZ |
6843 | ir.addr -= 2; |
6844 | goto no_support; | |
6845 | } | |
a3c4230a | 6846 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6847 | if (ret) |
6848 | return ret; | |
6849 | } | |
6850 | break; | |
6851 | ||
7ad10968 | 6852 | /* XXX */ |
a38bba38 | 6853 | case 0xce: /* into */ |
a3c4230a | 6854 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6855 | "instruction into.\n")); |
6856 | ir.addr -= 1; | |
6857 | goto no_support; | |
6858 | break; | |
6859 | ||
a38bba38 MS |
6860 | case 0xfa: /* cli */ |
6861 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6862 | break; |
6863 | ||
a38bba38 | 6864 | case 0x62: /* bound */ |
a3c4230a | 6865 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6866 | "instruction bound.\n")); |
6867 | ir.addr -= 1; | |
6868 | goto no_support; | |
6869 | break; | |
6870 | ||
a38bba38 | 6871 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6872 | case 0x0fc9: |
6873 | case 0x0fca: | |
6874 | case 0x0fcb: | |
6875 | case 0x0fcc: | |
6876 | case 0x0fcd: | |
6877 | case 0x0fce: | |
6878 | case 0x0fcf: | |
25ea693b | 6879 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6880 | break; |
6881 | ||
a38bba38 | 6882 | case 0xd6: /* salc */ |
cf648174 HZ |
6883 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6884 | { | |
6885 | ir.addr -= 1; | |
6886 | goto no_support; | |
6887 | } | |
25ea693b MM |
6888 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6889 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6890 | break; |
6891 | ||
a38bba38 MS |
6892 | case 0xe0: /* loopnz */ |
6893 | case 0xe1: /* loopz */ | |
6894 | case 0xe2: /* loop */ | |
6895 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6896 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6897 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6898 | break; |
6899 | ||
a38bba38 | 6900 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6901 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6902 | "instruction wrmsr.\n")); |
6903 | ir.addr -= 2; | |
6904 | goto no_support; | |
6905 | break; | |
6906 | ||
a38bba38 | 6907 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6908 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6909 | "instruction rdmsr.\n")); |
6910 | ir.addr -= 2; | |
6911 | goto no_support; | |
6912 | break; | |
6913 | ||
a38bba38 | 6914 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6915 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6916 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6917 | break; |
6918 | ||
a38bba38 | 6919 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6920 | { |
6921 | int ret; | |
cf648174 HZ |
6922 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6923 | { | |
6924 | ir.addr -= 2; | |
6925 | goto no_support; | |
6926 | } | |
a3c4230a | 6927 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6928 | { |
a3c4230a | 6929 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6930 | "instruction sysenter.\n")); |
6931 | ir.addr -= 2; | |
6932 | goto no_support; | |
6933 | } | |
a3c4230a | 6934 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6935 | if (ret) |
6936 | return ret; | |
6937 | } | |
6938 | break; | |
6939 | ||
a38bba38 | 6940 | case 0x0f35: /* sysexit */ |
a3c4230a | 6941 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6942 | "instruction sysexit.\n")); |
6943 | ir.addr -= 2; | |
6944 | goto no_support; | |
6945 | break; | |
6946 | ||
a38bba38 | 6947 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6948 | { |
6949 | int ret; | |
a3c4230a | 6950 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6951 | { |
a3c4230a | 6952 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6953 | "instruction syscall.\n")); |
6954 | ir.addr -= 2; | |
6955 | goto no_support; | |
6956 | } | |
a3c4230a | 6957 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6958 | if (ret) |
6959 | return ret; | |
6960 | } | |
6961 | break; | |
6962 | ||
a38bba38 | 6963 | case 0x0f07: /* sysret */ |
a3c4230a | 6964 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6965 | "instruction sysret.\n")); |
6966 | ir.addr -= 2; | |
6967 | goto no_support; | |
6968 | break; | |
6969 | ||
a38bba38 | 6970 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6971 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6972 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6973 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6974 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6975 | break; |
6976 | ||
a38bba38 | 6977 | case 0xf4: /* hlt */ |
a3c4230a | 6978 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6979 | "instruction hlt.\n")); |
6980 | ir.addr -= 1; | |
6981 | goto no_support; | |
6982 | break; | |
6983 | ||
6984 | case 0x0f00: | |
6985 | if (i386_record_modrm (&ir)) | |
6986 | return -1; | |
6987 | switch (ir.reg) | |
6988 | { | |
a38bba38 MS |
6989 | case 0: /* sldt */ |
6990 | case 1: /* str */ | |
7ad10968 | 6991 | if (ir.mod == 3) |
25ea693b | 6992 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6993 | else |
6994 | { | |
6995 | ir.ot = OT_WORD; | |
6996 | if (i386_record_lea_modrm (&ir)) | |
6997 | return -1; | |
6998 | } | |
6999 | break; | |
a38bba38 MS |
7000 | case 2: /* lldt */ |
7001 | case 3: /* ltr */ | |
7ad10968 | 7002 | break; |
a38bba38 MS |
7003 | case 4: /* verr */ |
7004 | case 5: /* verw */ | |
25ea693b | 7005 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7006 | break; |
7007 | default: | |
7008 | ir.addr -= 3; | |
7009 | opcode = opcode << 8 | ir.modrm; | |
7010 | goto no_support; | |
7011 | break; | |
7012 | } | |
7013 | break; | |
7014 | ||
7015 | case 0x0f01: | |
7016 | if (i386_record_modrm (&ir)) | |
7017 | return -1; | |
7018 | switch (ir.reg) | |
7019 | { | |
a38bba38 | 7020 | case 0: /* sgdt */ |
7ad10968 | 7021 | { |
955db0c0 | 7022 | uint64_t addr64; |
7ad10968 HZ |
7023 | |
7024 | if (ir.mod == 3) | |
7025 | { | |
7026 | ir.addr -= 3; | |
7027 | opcode = opcode << 8 | ir.modrm; | |
7028 | goto no_support; | |
7029 | } | |
d7877f7e | 7030 | if (ir.override >= 0) |
7ad10968 | 7031 | { |
25ea693b | 7032 | if (record_full_memory_query) |
bb08c432 | 7033 | { |
651ce16a | 7034 | if (yquery (_("\ |
bb08c432 HZ |
7035 | Process record ignores the memory change of instruction at address %s\n\ |
7036 | because it can't get the value of the segment register.\n\ | |
7037 | Do you want to stop the program?"), | |
651ce16a PA |
7038 | paddress (gdbarch, ir.orig_addr))) |
7039 | return -1; | |
bb08c432 | 7040 | } |
7ad10968 HZ |
7041 | } |
7042 | else | |
7043 | { | |
955db0c0 | 7044 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7045 | return -1; |
25ea693b | 7046 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7047 | return -1; |
955db0c0 | 7048 | addr64 += 2; |
cf648174 HZ |
7049 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7050 | { | |
25ea693b | 7051 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7052 | return -1; |
7053 | } | |
7054 | else | |
7055 | { | |
25ea693b | 7056 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7057 | return -1; |
7058 | } | |
7ad10968 HZ |
7059 | } |
7060 | } | |
7061 | break; | |
7062 | case 1: | |
7063 | if (ir.mod == 3) | |
7064 | { | |
7065 | switch (ir.rm) | |
7066 | { | |
a38bba38 | 7067 | case 0: /* monitor */ |
7ad10968 | 7068 | break; |
a38bba38 | 7069 | case 1: /* mwait */ |
25ea693b | 7070 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7071 | break; |
7072 | default: | |
7073 | ir.addr -= 3; | |
7074 | opcode = opcode << 8 | ir.modrm; | |
7075 | goto no_support; | |
7076 | break; | |
7077 | } | |
7078 | } | |
7079 | else | |
7080 | { | |
7081 | /* sidt */ | |
d7877f7e | 7082 | if (ir.override >= 0) |
7ad10968 | 7083 | { |
25ea693b | 7084 | if (record_full_memory_query) |
bb08c432 | 7085 | { |
651ce16a | 7086 | if (yquery (_("\ |
bb08c432 HZ |
7087 | Process record ignores the memory change of instruction at address %s\n\ |
7088 | because it can't get the value of the segment register.\n\ | |
7089 | Do you want to stop the program?"), | |
651ce16a | 7090 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
7091 | return -1; |
7092 | } | |
7ad10968 HZ |
7093 | } |
7094 | else | |
7095 | { | |
955db0c0 | 7096 | uint64_t addr64; |
7ad10968 | 7097 | |
955db0c0 | 7098 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7099 | return -1; |
25ea693b | 7100 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7101 | return -1; |
955db0c0 | 7102 | addr64 += 2; |
cf648174 HZ |
7103 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7104 | { | |
25ea693b | 7105 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7106 | return -1; |
7107 | } | |
7108 | else | |
7109 | { | |
25ea693b | 7110 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7111 | return -1; |
7112 | } | |
7ad10968 HZ |
7113 | } |
7114 | } | |
7115 | break; | |
a38bba38 | 7116 | case 2: /* lgdt */ |
3800e645 MS |
7117 | if (ir.mod == 3) |
7118 | { | |
7119 | /* xgetbv */ | |
7120 | if (ir.rm == 0) | |
7121 | { | |
25ea693b MM |
7122 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7123 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7124 | break; |
7125 | } | |
7126 | /* xsetbv */ | |
7127 | else if (ir.rm == 1) | |
7128 | break; | |
7129 | } | |
a38bba38 | 7130 | case 3: /* lidt */ |
7ad10968 HZ |
7131 | if (ir.mod == 3) |
7132 | { | |
7133 | ir.addr -= 3; | |
7134 | opcode = opcode << 8 | ir.modrm; | |
7135 | goto no_support; | |
7136 | } | |
7137 | break; | |
a38bba38 | 7138 | case 4: /* smsw */ |
7ad10968 HZ |
7139 | if (ir.mod == 3) |
7140 | { | |
25ea693b | 7141 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7142 | return -1; |
7143 | } | |
7144 | else | |
7145 | { | |
7146 | ir.ot = OT_WORD; | |
7147 | if (i386_record_lea_modrm (&ir)) | |
7148 | return -1; | |
7149 | } | |
25ea693b | 7150 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7151 | break; |
a38bba38 | 7152 | case 6: /* lmsw */ |
25ea693b | 7153 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7154 | break; |
a38bba38 | 7155 | case 7: /* invlpg */ |
cf648174 HZ |
7156 | if (ir.mod == 3) |
7157 | { | |
7158 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7159 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7160 | else |
7161 | { | |
7162 | ir.addr -= 3; | |
7163 | opcode = opcode << 8 | ir.modrm; | |
7164 | goto no_support; | |
7165 | } | |
7166 | } | |
7167 | else | |
25ea693b | 7168 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7169 | break; |
7170 | default: | |
7171 | ir.addr -= 3; | |
7172 | opcode = opcode << 8 | ir.modrm; | |
7173 | goto no_support; | |
7ad10968 HZ |
7174 | break; |
7175 | } | |
7176 | break; | |
7177 | ||
a38bba38 MS |
7178 | case 0x0f08: /* invd */ |
7179 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7180 | break; |
7181 | ||
a38bba38 | 7182 | case 0x63: /* arpl */ |
7ad10968 HZ |
7183 | if (i386_record_modrm (&ir)) |
7184 | return -1; | |
cf648174 HZ |
7185 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7186 | { | |
25ea693b MM |
7187 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7188 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7189 | } |
7ad10968 | 7190 | else |
cf648174 HZ |
7191 | { |
7192 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7193 | if (i386_record_lea_modrm (&ir)) | |
7194 | return -1; | |
7195 | } | |
7196 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7197 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7198 | break; |
7199 | ||
a38bba38 MS |
7200 | case 0x0f02: /* lar */ |
7201 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7202 | if (i386_record_modrm (&ir)) |
7203 | return -1; | |
25ea693b MM |
7204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7205 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7206 | break; |
7207 | ||
7208 | case 0x0f18: | |
cf648174 HZ |
7209 | if (i386_record_modrm (&ir)) |
7210 | return -1; | |
7211 | if (ir.mod == 3 && ir.reg == 3) | |
7212 | { | |
7213 | ir.addr -= 3; | |
7214 | opcode = opcode << 8 | ir.modrm; | |
7215 | goto no_support; | |
7216 | } | |
7ad10968 HZ |
7217 | break; |
7218 | ||
7ad10968 HZ |
7219 | case 0x0f19: |
7220 | case 0x0f1a: | |
7221 | case 0x0f1b: | |
7222 | case 0x0f1c: | |
7223 | case 0x0f1d: | |
7224 | case 0x0f1e: | |
7225 | case 0x0f1f: | |
a38bba38 | 7226 | /* nop (multi byte) */ |
7ad10968 HZ |
7227 | break; |
7228 | ||
a38bba38 MS |
7229 | case 0x0f20: /* mov reg, crN */ |
7230 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7231 | if (i386_record_modrm (&ir)) |
7232 | return -1; | |
7233 | if ((ir.modrm & 0xc0) != 0xc0) | |
7234 | { | |
cf648174 | 7235 | ir.addr -= 3; |
7ad10968 HZ |
7236 | opcode = opcode << 8 | ir.modrm; |
7237 | goto no_support; | |
7238 | } | |
7239 | switch (ir.reg) | |
7240 | { | |
7241 | case 0: | |
7242 | case 2: | |
7243 | case 3: | |
7244 | case 4: | |
7245 | case 8: | |
7246 | if (opcode & 2) | |
25ea693b | 7247 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7248 | else |
25ea693b | 7249 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7250 | break; |
7251 | default: | |
cf648174 | 7252 | ir.addr -= 3; |
7ad10968 HZ |
7253 | opcode = opcode << 8 | ir.modrm; |
7254 | goto no_support; | |
7255 | break; | |
7256 | } | |
7257 | break; | |
7258 | ||
a38bba38 MS |
7259 | case 0x0f21: /* mov reg, drN */ |
7260 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7261 | if (i386_record_modrm (&ir)) |
7262 | return -1; | |
7263 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7264 | || ir.reg == 5 || ir.reg >= 8) | |
7265 | { | |
cf648174 | 7266 | ir.addr -= 3; |
7ad10968 HZ |
7267 | opcode = opcode << 8 | ir.modrm; |
7268 | goto no_support; | |
7269 | } | |
7270 | if (opcode & 2) | |
25ea693b | 7271 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7272 | else |
25ea693b | 7273 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7274 | break; |
7275 | ||
a38bba38 | 7276 | case 0x0f06: /* clts */ |
25ea693b | 7277 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7278 | break; |
7279 | ||
a3c4230a HZ |
7280 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7281 | ||
7282 | case 0x0f0d: /* 3DNow! prefetch */ | |
7283 | break; | |
7284 | ||
7285 | case 0x0f0e: /* 3DNow! femms */ | |
7286 | case 0x0f77: /* emms */ | |
7287 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7288 | goto no_support; | |
25ea693b | 7289 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7290 | break; |
7291 | ||
7292 | case 0x0f0f: /* 3DNow! data */ | |
7293 | if (i386_record_modrm (&ir)) | |
7294 | return -1; | |
4ffa4fc7 PA |
7295 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7296 | return -1; | |
a3c4230a HZ |
7297 | ir.addr++; |
7298 | switch (opcode8) | |
7299 | { | |
7300 | case 0x0c: /* 3DNow! pi2fw */ | |
7301 | case 0x0d: /* 3DNow! pi2fd */ | |
7302 | case 0x1c: /* 3DNow! pf2iw */ | |
7303 | case 0x1d: /* 3DNow! pf2id */ | |
7304 | case 0x8a: /* 3DNow! pfnacc */ | |
7305 | case 0x8e: /* 3DNow! pfpnacc */ | |
7306 | case 0x90: /* 3DNow! pfcmpge */ | |
7307 | case 0x94: /* 3DNow! pfmin */ | |
7308 | case 0x96: /* 3DNow! pfrcp */ | |
7309 | case 0x97: /* 3DNow! pfrsqrt */ | |
7310 | case 0x9a: /* 3DNow! pfsub */ | |
7311 | case 0x9e: /* 3DNow! pfadd */ | |
7312 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7313 | case 0xa4: /* 3DNow! pfmax */ | |
7314 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7315 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7316 | case 0xaa: /* 3DNow! pfsubr */ | |
7317 | case 0xae: /* 3DNow! pfacc */ | |
7318 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7319 | case 0xb4: /* 3DNow! pfmul */ | |
7320 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7321 | case 0xb7: /* 3DNow! pmulhrw */ | |
7322 | case 0xbb: /* 3DNow! pswapd */ | |
7323 | case 0xbf: /* 3DNow! pavgusb */ | |
7324 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7325 | goto no_support_3dnow_data; | |
25ea693b | 7326 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7327 | break; |
7328 | ||
7329 | default: | |
7330 | no_support_3dnow_data: | |
7331 | opcode = (opcode << 8) | opcode8; | |
7332 | goto no_support; | |
7333 | break; | |
7334 | } | |
7335 | break; | |
7336 | ||
7337 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7338 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7339 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7340 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7341 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7342 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7343 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7344 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7345 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7346 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7347 | break; |
7348 | ||
7349 | case 0x0fae: | |
7350 | if (i386_record_modrm (&ir)) | |
7351 | return -1; | |
7352 | switch(ir.reg) | |
7353 | { | |
7354 | case 0: /* fxsave */ | |
7355 | { | |
7356 | uint64_t tmpu64; | |
7357 | ||
25ea693b | 7358 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7359 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7360 | return -1; | |
25ea693b | 7361 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7362 | return -1; |
7363 | } | |
7364 | break; | |
7365 | ||
7366 | case 1: /* fxrstor */ | |
7367 | { | |
7368 | int i; | |
7369 | ||
25ea693b | 7370 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7371 | |
7372 | for (i = I387_MM0_REGNUM (tdep); | |
7373 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7374 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7375 | |
7376 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7377 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7378 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7379 | |
7380 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7381 | record_full_arch_list_add_reg (ir.regcache, |
7382 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7383 | |
7384 | for (i = I387_ST0_REGNUM (tdep); | |
7385 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7386 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7387 | |
7388 | for (i = I387_FCTRL_REGNUM (tdep); | |
7389 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7390 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7391 | } |
7392 | break; | |
7393 | ||
7394 | case 2: /* ldmxcsr */ | |
7395 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7396 | goto no_support; | |
25ea693b | 7397 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7398 | break; |
7399 | ||
7400 | case 3: /* stmxcsr */ | |
7401 | ir.ot = OT_LONG; | |
7402 | if (i386_record_lea_modrm (&ir)) | |
7403 | return -1; | |
7404 | break; | |
7405 | ||
7406 | case 5: /* lfence */ | |
7407 | case 6: /* mfence */ | |
7408 | case 7: /* sfence clflush */ | |
7409 | break; | |
7410 | ||
7411 | default: | |
7412 | opcode = (opcode << 8) | ir.modrm; | |
7413 | goto no_support; | |
7414 | break; | |
7415 | } | |
7416 | break; | |
7417 | ||
7418 | case 0x0fc3: /* movnti */ | |
7419 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7420 | if (i386_record_modrm (&ir)) | |
7421 | return -1; | |
7422 | if (ir.mod == 3) | |
7423 | goto no_support; | |
7424 | ir.reg |= rex_r; | |
7425 | if (i386_record_lea_modrm (&ir)) | |
7426 | return -1; | |
7427 | break; | |
7428 | ||
7429 | /* Add prefix to opcode. */ | |
7430 | case 0x0f10: | |
7431 | case 0x0f11: | |
7432 | case 0x0f12: | |
7433 | case 0x0f13: | |
7434 | case 0x0f14: | |
7435 | case 0x0f15: | |
7436 | case 0x0f16: | |
7437 | case 0x0f17: | |
7438 | case 0x0f28: | |
7439 | case 0x0f29: | |
7440 | case 0x0f2a: | |
7441 | case 0x0f2b: | |
7442 | case 0x0f2c: | |
7443 | case 0x0f2d: | |
7444 | case 0x0f2e: | |
7445 | case 0x0f2f: | |
7446 | case 0x0f38: | |
7447 | case 0x0f39: | |
7448 | case 0x0f3a: | |
7449 | case 0x0f50: | |
7450 | case 0x0f51: | |
7451 | case 0x0f52: | |
7452 | case 0x0f53: | |
7453 | case 0x0f54: | |
7454 | case 0x0f55: | |
7455 | case 0x0f56: | |
7456 | case 0x0f57: | |
7457 | case 0x0f58: | |
7458 | case 0x0f59: | |
7459 | case 0x0f5a: | |
7460 | case 0x0f5b: | |
7461 | case 0x0f5c: | |
7462 | case 0x0f5d: | |
7463 | case 0x0f5e: | |
7464 | case 0x0f5f: | |
7465 | case 0x0f60: | |
7466 | case 0x0f61: | |
7467 | case 0x0f62: | |
7468 | case 0x0f63: | |
7469 | case 0x0f64: | |
7470 | case 0x0f65: | |
7471 | case 0x0f66: | |
7472 | case 0x0f67: | |
7473 | case 0x0f68: | |
7474 | case 0x0f69: | |
7475 | case 0x0f6a: | |
7476 | case 0x0f6b: | |
7477 | case 0x0f6c: | |
7478 | case 0x0f6d: | |
7479 | case 0x0f6e: | |
7480 | case 0x0f6f: | |
7481 | case 0x0f70: | |
7482 | case 0x0f71: | |
7483 | case 0x0f72: | |
7484 | case 0x0f73: | |
7485 | case 0x0f74: | |
7486 | case 0x0f75: | |
7487 | case 0x0f76: | |
7488 | case 0x0f7c: | |
7489 | case 0x0f7d: | |
7490 | case 0x0f7e: | |
7491 | case 0x0f7f: | |
7492 | case 0x0fb8: | |
7493 | case 0x0fc2: | |
7494 | case 0x0fc4: | |
7495 | case 0x0fc5: | |
7496 | case 0x0fc6: | |
7497 | case 0x0fd0: | |
7498 | case 0x0fd1: | |
7499 | case 0x0fd2: | |
7500 | case 0x0fd3: | |
7501 | case 0x0fd4: | |
7502 | case 0x0fd5: | |
7503 | case 0x0fd6: | |
7504 | case 0x0fd7: | |
7505 | case 0x0fd8: | |
7506 | case 0x0fd9: | |
7507 | case 0x0fda: | |
7508 | case 0x0fdb: | |
7509 | case 0x0fdc: | |
7510 | case 0x0fdd: | |
7511 | case 0x0fde: | |
7512 | case 0x0fdf: | |
7513 | case 0x0fe0: | |
7514 | case 0x0fe1: | |
7515 | case 0x0fe2: | |
7516 | case 0x0fe3: | |
7517 | case 0x0fe4: | |
7518 | case 0x0fe5: | |
7519 | case 0x0fe6: | |
7520 | case 0x0fe7: | |
7521 | case 0x0fe8: | |
7522 | case 0x0fe9: | |
7523 | case 0x0fea: | |
7524 | case 0x0feb: | |
7525 | case 0x0fec: | |
7526 | case 0x0fed: | |
7527 | case 0x0fee: | |
7528 | case 0x0fef: | |
7529 | case 0x0ff0: | |
7530 | case 0x0ff1: | |
7531 | case 0x0ff2: | |
7532 | case 0x0ff3: | |
7533 | case 0x0ff4: | |
7534 | case 0x0ff5: | |
7535 | case 0x0ff6: | |
7536 | case 0x0ff7: | |
7537 | case 0x0ff8: | |
7538 | case 0x0ff9: | |
7539 | case 0x0ffa: | |
7540 | case 0x0ffb: | |
7541 | case 0x0ffc: | |
7542 | case 0x0ffd: | |
7543 | case 0x0ffe: | |
f9fda3f5 L |
7544 | /* Mask out PREFIX_ADDR. */ |
7545 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7546 | { |
7547 | case PREFIX_REPNZ: | |
7548 | opcode |= 0xf20000; | |
7549 | break; | |
7550 | case PREFIX_DATA: | |
7551 | opcode |= 0x660000; | |
7552 | break; | |
7553 | case PREFIX_REPZ: | |
7554 | opcode |= 0xf30000; | |
7555 | break; | |
7556 | } | |
7557 | reswitch_prefix_add: | |
7558 | switch (opcode) | |
7559 | { | |
7560 | case 0x0f38: | |
7561 | case 0x660f38: | |
7562 | case 0xf20f38: | |
7563 | case 0x0f3a: | |
7564 | case 0x660f3a: | |
4ffa4fc7 PA |
7565 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7566 | return -1; | |
a3c4230a HZ |
7567 | ir.addr++; |
7568 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7569 | goto reswitch_prefix_add; | |
7570 | break; | |
7571 | ||
7572 | case 0x0f10: /* movups */ | |
7573 | case 0x660f10: /* movupd */ | |
7574 | case 0xf30f10: /* movss */ | |
7575 | case 0xf20f10: /* movsd */ | |
7576 | case 0x0f12: /* movlps */ | |
7577 | case 0x660f12: /* movlpd */ | |
7578 | case 0xf30f12: /* movsldup */ | |
7579 | case 0xf20f12: /* movddup */ | |
7580 | case 0x0f14: /* unpcklps */ | |
7581 | case 0x660f14: /* unpcklpd */ | |
7582 | case 0x0f15: /* unpckhps */ | |
7583 | case 0x660f15: /* unpckhpd */ | |
7584 | case 0x0f16: /* movhps */ | |
7585 | case 0x660f16: /* movhpd */ | |
7586 | case 0xf30f16: /* movshdup */ | |
7587 | case 0x0f28: /* movaps */ | |
7588 | case 0x660f28: /* movapd */ | |
7589 | case 0x0f2a: /* cvtpi2ps */ | |
7590 | case 0x660f2a: /* cvtpi2pd */ | |
7591 | case 0xf30f2a: /* cvtsi2ss */ | |
7592 | case 0xf20f2a: /* cvtsi2sd */ | |
7593 | case 0x0f2c: /* cvttps2pi */ | |
7594 | case 0x660f2c: /* cvttpd2pi */ | |
7595 | case 0x0f2d: /* cvtps2pi */ | |
7596 | case 0x660f2d: /* cvtpd2pi */ | |
7597 | case 0x660f3800: /* pshufb */ | |
7598 | case 0x660f3801: /* phaddw */ | |
7599 | case 0x660f3802: /* phaddd */ | |
7600 | case 0x660f3803: /* phaddsw */ | |
7601 | case 0x660f3804: /* pmaddubsw */ | |
7602 | case 0x660f3805: /* phsubw */ | |
7603 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7604 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7605 | case 0x660f3808: /* psignb */ |
7606 | case 0x660f3809: /* psignw */ | |
7607 | case 0x660f380a: /* psignd */ | |
7608 | case 0x660f380b: /* pmulhrsw */ | |
7609 | case 0x660f3810: /* pblendvb */ | |
7610 | case 0x660f3814: /* blendvps */ | |
7611 | case 0x660f3815: /* blendvpd */ | |
7612 | case 0x660f381c: /* pabsb */ | |
7613 | case 0x660f381d: /* pabsw */ | |
7614 | case 0x660f381e: /* pabsd */ | |
7615 | case 0x660f3820: /* pmovsxbw */ | |
7616 | case 0x660f3821: /* pmovsxbd */ | |
7617 | case 0x660f3822: /* pmovsxbq */ | |
7618 | case 0x660f3823: /* pmovsxwd */ | |
7619 | case 0x660f3824: /* pmovsxwq */ | |
7620 | case 0x660f3825: /* pmovsxdq */ | |
7621 | case 0x660f3828: /* pmuldq */ | |
7622 | case 0x660f3829: /* pcmpeqq */ | |
7623 | case 0x660f382a: /* movntdqa */ | |
7624 | case 0x660f3a08: /* roundps */ | |
7625 | case 0x660f3a09: /* roundpd */ | |
7626 | case 0x660f3a0a: /* roundss */ | |
7627 | case 0x660f3a0b: /* roundsd */ | |
7628 | case 0x660f3a0c: /* blendps */ | |
7629 | case 0x660f3a0d: /* blendpd */ | |
7630 | case 0x660f3a0e: /* pblendw */ | |
7631 | case 0x660f3a0f: /* palignr */ | |
7632 | case 0x660f3a20: /* pinsrb */ | |
7633 | case 0x660f3a21: /* insertps */ | |
7634 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7635 | case 0x660f3a40: /* dpps */ | |
7636 | case 0x660f3a41: /* dppd */ | |
7637 | case 0x660f3a42: /* mpsadbw */ | |
7638 | case 0x660f3a60: /* pcmpestrm */ | |
7639 | case 0x660f3a61: /* pcmpestri */ | |
7640 | case 0x660f3a62: /* pcmpistrm */ | |
7641 | case 0x660f3a63: /* pcmpistri */ | |
7642 | case 0x0f51: /* sqrtps */ | |
7643 | case 0x660f51: /* sqrtpd */ | |
7644 | case 0xf20f51: /* sqrtsd */ | |
7645 | case 0xf30f51: /* sqrtss */ | |
7646 | case 0x0f52: /* rsqrtps */ | |
7647 | case 0xf30f52: /* rsqrtss */ | |
7648 | case 0x0f53: /* rcpps */ | |
7649 | case 0xf30f53: /* rcpss */ | |
7650 | case 0x0f54: /* andps */ | |
7651 | case 0x660f54: /* andpd */ | |
7652 | case 0x0f55: /* andnps */ | |
7653 | case 0x660f55: /* andnpd */ | |
7654 | case 0x0f56: /* orps */ | |
7655 | case 0x660f56: /* orpd */ | |
7656 | case 0x0f57: /* xorps */ | |
7657 | case 0x660f57: /* xorpd */ | |
7658 | case 0x0f58: /* addps */ | |
7659 | case 0x660f58: /* addpd */ | |
7660 | case 0xf20f58: /* addsd */ | |
7661 | case 0xf30f58: /* addss */ | |
7662 | case 0x0f59: /* mulps */ | |
7663 | case 0x660f59: /* mulpd */ | |
7664 | case 0xf20f59: /* mulsd */ | |
7665 | case 0xf30f59: /* mulss */ | |
7666 | case 0x0f5a: /* cvtps2pd */ | |
7667 | case 0x660f5a: /* cvtpd2ps */ | |
7668 | case 0xf20f5a: /* cvtsd2ss */ | |
7669 | case 0xf30f5a: /* cvtss2sd */ | |
7670 | case 0x0f5b: /* cvtdq2ps */ | |
7671 | case 0x660f5b: /* cvtps2dq */ | |
7672 | case 0xf30f5b: /* cvttps2dq */ | |
7673 | case 0x0f5c: /* subps */ | |
7674 | case 0x660f5c: /* subpd */ | |
7675 | case 0xf20f5c: /* subsd */ | |
7676 | case 0xf30f5c: /* subss */ | |
7677 | case 0x0f5d: /* minps */ | |
7678 | case 0x660f5d: /* minpd */ | |
7679 | case 0xf20f5d: /* minsd */ | |
7680 | case 0xf30f5d: /* minss */ | |
7681 | case 0x0f5e: /* divps */ | |
7682 | case 0x660f5e: /* divpd */ | |
7683 | case 0xf20f5e: /* divsd */ | |
7684 | case 0xf30f5e: /* divss */ | |
7685 | case 0x0f5f: /* maxps */ | |
7686 | case 0x660f5f: /* maxpd */ | |
7687 | case 0xf20f5f: /* maxsd */ | |
7688 | case 0xf30f5f: /* maxss */ | |
7689 | case 0x660f60: /* punpcklbw */ | |
7690 | case 0x660f61: /* punpcklwd */ | |
7691 | case 0x660f62: /* punpckldq */ | |
7692 | case 0x660f63: /* packsswb */ | |
7693 | case 0x660f64: /* pcmpgtb */ | |
7694 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7695 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7696 | case 0x660f67: /* packuswb */ |
7697 | case 0x660f68: /* punpckhbw */ | |
7698 | case 0x660f69: /* punpckhwd */ | |
7699 | case 0x660f6a: /* punpckhdq */ | |
7700 | case 0x660f6b: /* packssdw */ | |
7701 | case 0x660f6c: /* punpcklqdq */ | |
7702 | case 0x660f6d: /* punpckhqdq */ | |
7703 | case 0x660f6e: /* movd */ | |
7704 | case 0x660f6f: /* movdqa */ | |
7705 | case 0xf30f6f: /* movdqu */ | |
7706 | case 0x660f70: /* pshufd */ | |
7707 | case 0xf20f70: /* pshuflw */ | |
7708 | case 0xf30f70: /* pshufhw */ | |
7709 | case 0x660f74: /* pcmpeqb */ | |
7710 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7711 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7712 | case 0x660f7c: /* haddpd */ |
7713 | case 0xf20f7c: /* haddps */ | |
7714 | case 0x660f7d: /* hsubpd */ | |
7715 | case 0xf20f7d: /* hsubps */ | |
7716 | case 0xf30f7e: /* movq */ | |
7717 | case 0x0fc2: /* cmpps */ | |
7718 | case 0x660fc2: /* cmppd */ | |
7719 | case 0xf20fc2: /* cmpsd */ | |
7720 | case 0xf30fc2: /* cmpss */ | |
7721 | case 0x660fc4: /* pinsrw */ | |
7722 | case 0x0fc6: /* shufps */ | |
7723 | case 0x660fc6: /* shufpd */ | |
7724 | case 0x660fd0: /* addsubpd */ | |
7725 | case 0xf20fd0: /* addsubps */ | |
7726 | case 0x660fd1: /* psrlw */ | |
7727 | case 0x660fd2: /* psrld */ | |
7728 | case 0x660fd3: /* psrlq */ | |
7729 | case 0x660fd4: /* paddq */ | |
7730 | case 0x660fd5: /* pmullw */ | |
7731 | case 0xf30fd6: /* movq2dq */ | |
7732 | case 0x660fd8: /* psubusb */ | |
7733 | case 0x660fd9: /* psubusw */ | |
7734 | case 0x660fda: /* pminub */ | |
7735 | case 0x660fdb: /* pand */ | |
7736 | case 0x660fdc: /* paddusb */ | |
7737 | case 0x660fdd: /* paddusw */ | |
7738 | case 0x660fde: /* pmaxub */ | |
7739 | case 0x660fdf: /* pandn */ | |
7740 | case 0x660fe0: /* pavgb */ | |
7741 | case 0x660fe1: /* psraw */ | |
7742 | case 0x660fe2: /* psrad */ | |
7743 | case 0x660fe3: /* pavgw */ | |
7744 | case 0x660fe4: /* pmulhuw */ | |
7745 | case 0x660fe5: /* pmulhw */ | |
7746 | case 0x660fe6: /* cvttpd2dq */ | |
7747 | case 0xf20fe6: /* cvtpd2dq */ | |
7748 | case 0xf30fe6: /* cvtdq2pd */ | |
7749 | case 0x660fe8: /* psubsb */ | |
7750 | case 0x660fe9: /* psubsw */ | |
7751 | case 0x660fea: /* pminsw */ | |
7752 | case 0x660feb: /* por */ | |
7753 | case 0x660fec: /* paddsb */ | |
7754 | case 0x660fed: /* paddsw */ | |
7755 | case 0x660fee: /* pmaxsw */ | |
7756 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7757 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7758 | case 0x660ff1: /* psllw */ |
7759 | case 0x660ff2: /* pslld */ | |
7760 | case 0x660ff3: /* psllq */ | |
7761 | case 0x660ff4: /* pmuludq */ | |
7762 | case 0x660ff5: /* pmaddwd */ | |
7763 | case 0x660ff6: /* psadbw */ | |
7764 | case 0x660ff8: /* psubb */ | |
7765 | case 0x660ff9: /* psubw */ | |
56d2815c | 7766 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7767 | case 0x660ffb: /* psubq */ |
7768 | case 0x660ffc: /* paddb */ | |
7769 | case 0x660ffd: /* paddw */ | |
56d2815c | 7770 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7771 | if (i386_record_modrm (&ir)) |
7772 | return -1; | |
7773 | ir.reg |= rex_r; | |
c131fcee | 7774 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7775 | goto no_support; |
25ea693b MM |
7776 | record_full_arch_list_add_reg (ir.regcache, |
7777 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7778 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7779 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7780 | break; |
7781 | ||
7782 | case 0x0f11: /* movups */ | |
7783 | case 0x660f11: /* movupd */ | |
7784 | case 0xf30f11: /* movss */ | |
7785 | case 0xf20f11: /* movsd */ | |
7786 | case 0x0f13: /* movlps */ | |
7787 | case 0x660f13: /* movlpd */ | |
7788 | case 0x0f17: /* movhps */ | |
7789 | case 0x660f17: /* movhpd */ | |
7790 | case 0x0f29: /* movaps */ | |
7791 | case 0x660f29: /* movapd */ | |
7792 | case 0x660f3a14: /* pextrb */ | |
7793 | case 0x660f3a15: /* pextrw */ | |
7794 | case 0x660f3a16: /* pextrd pextrq */ | |
7795 | case 0x660f3a17: /* extractps */ | |
7796 | case 0x660f7f: /* movdqa */ | |
7797 | case 0xf30f7f: /* movdqu */ | |
7798 | if (i386_record_modrm (&ir)) | |
7799 | return -1; | |
7800 | if (ir.mod == 3) | |
7801 | { | |
7802 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7803 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7804 | goto no_support; | |
7805 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7806 | if (!i386_xmm_regnum_p (gdbarch, |
7807 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7808 | goto no_support; |
25ea693b MM |
7809 | record_full_arch_list_add_reg (ir.regcache, |
7810 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7811 | } |
7812 | else | |
7813 | { | |
7814 | switch (opcode) | |
7815 | { | |
7816 | case 0x660f3a14: | |
7817 | ir.ot = OT_BYTE; | |
7818 | break; | |
7819 | case 0x660f3a15: | |
7820 | ir.ot = OT_WORD; | |
7821 | break; | |
7822 | case 0x660f3a16: | |
7823 | ir.ot = OT_LONG; | |
7824 | break; | |
7825 | case 0x660f3a17: | |
7826 | ir.ot = OT_QUAD; | |
7827 | break; | |
7828 | default: | |
7829 | ir.ot = OT_DQUAD; | |
7830 | break; | |
7831 | } | |
7832 | if (i386_record_lea_modrm (&ir)) | |
7833 | return -1; | |
7834 | } | |
7835 | break; | |
7836 | ||
7837 | case 0x0f2b: /* movntps */ | |
7838 | case 0x660f2b: /* movntpd */ | |
7839 | case 0x0fe7: /* movntq */ | |
7840 | case 0x660fe7: /* movntdq */ | |
7841 | if (ir.mod == 3) | |
7842 | goto no_support; | |
7843 | if (opcode == 0x0fe7) | |
7844 | ir.ot = OT_QUAD; | |
7845 | else | |
7846 | ir.ot = OT_DQUAD; | |
7847 | if (i386_record_lea_modrm (&ir)) | |
7848 | return -1; | |
7849 | break; | |
7850 | ||
7851 | case 0xf30f2c: /* cvttss2si */ | |
7852 | case 0xf20f2c: /* cvttsd2si */ | |
7853 | case 0xf30f2d: /* cvtss2si */ | |
7854 | case 0xf20f2d: /* cvtsd2si */ | |
7855 | case 0xf20f38f0: /* crc32 */ | |
7856 | case 0xf20f38f1: /* crc32 */ | |
7857 | case 0x0f50: /* movmskps */ | |
7858 | case 0x660f50: /* movmskpd */ | |
7859 | case 0x0fc5: /* pextrw */ | |
7860 | case 0x660fc5: /* pextrw */ | |
7861 | case 0x0fd7: /* pmovmskb */ | |
7862 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7863 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7864 | break; |
7865 | ||
7866 | case 0x0f3800: /* pshufb */ | |
7867 | case 0x0f3801: /* phaddw */ | |
7868 | case 0x0f3802: /* phaddd */ | |
7869 | case 0x0f3803: /* phaddsw */ | |
7870 | case 0x0f3804: /* pmaddubsw */ | |
7871 | case 0x0f3805: /* phsubw */ | |
7872 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7873 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7874 | case 0x0f3808: /* psignb */ |
7875 | case 0x0f3809: /* psignw */ | |
7876 | case 0x0f380a: /* psignd */ | |
7877 | case 0x0f380b: /* pmulhrsw */ | |
7878 | case 0x0f381c: /* pabsb */ | |
7879 | case 0x0f381d: /* pabsw */ | |
7880 | case 0x0f381e: /* pabsd */ | |
7881 | case 0x0f382b: /* packusdw */ | |
7882 | case 0x0f3830: /* pmovzxbw */ | |
7883 | case 0x0f3831: /* pmovzxbd */ | |
7884 | case 0x0f3832: /* pmovzxbq */ | |
7885 | case 0x0f3833: /* pmovzxwd */ | |
7886 | case 0x0f3834: /* pmovzxwq */ | |
7887 | case 0x0f3835: /* pmovzxdq */ | |
7888 | case 0x0f3837: /* pcmpgtq */ | |
7889 | case 0x0f3838: /* pminsb */ | |
7890 | case 0x0f3839: /* pminsd */ | |
7891 | case 0x0f383a: /* pminuw */ | |
7892 | case 0x0f383b: /* pminud */ | |
7893 | case 0x0f383c: /* pmaxsb */ | |
7894 | case 0x0f383d: /* pmaxsd */ | |
7895 | case 0x0f383e: /* pmaxuw */ | |
7896 | case 0x0f383f: /* pmaxud */ | |
7897 | case 0x0f3840: /* pmulld */ | |
7898 | case 0x0f3841: /* phminposuw */ | |
7899 | case 0x0f3a0f: /* palignr */ | |
7900 | case 0x0f60: /* punpcklbw */ | |
7901 | case 0x0f61: /* punpcklwd */ | |
7902 | case 0x0f62: /* punpckldq */ | |
7903 | case 0x0f63: /* packsswb */ | |
7904 | case 0x0f64: /* pcmpgtb */ | |
7905 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7906 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7907 | case 0x0f67: /* packuswb */ |
7908 | case 0x0f68: /* punpckhbw */ | |
7909 | case 0x0f69: /* punpckhwd */ | |
7910 | case 0x0f6a: /* punpckhdq */ | |
7911 | case 0x0f6b: /* packssdw */ | |
7912 | case 0x0f6e: /* movd */ | |
7913 | case 0x0f6f: /* movq */ | |
7914 | case 0x0f70: /* pshufw */ | |
7915 | case 0x0f74: /* pcmpeqb */ | |
7916 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7917 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7918 | case 0x0fc4: /* pinsrw */ |
7919 | case 0x0fd1: /* psrlw */ | |
7920 | case 0x0fd2: /* psrld */ | |
7921 | case 0x0fd3: /* psrlq */ | |
7922 | case 0x0fd4: /* paddq */ | |
7923 | case 0x0fd5: /* pmullw */ | |
7924 | case 0xf20fd6: /* movdq2q */ | |
7925 | case 0x0fd8: /* psubusb */ | |
7926 | case 0x0fd9: /* psubusw */ | |
7927 | case 0x0fda: /* pminub */ | |
7928 | case 0x0fdb: /* pand */ | |
7929 | case 0x0fdc: /* paddusb */ | |
7930 | case 0x0fdd: /* paddusw */ | |
7931 | case 0x0fde: /* pmaxub */ | |
7932 | case 0x0fdf: /* pandn */ | |
7933 | case 0x0fe0: /* pavgb */ | |
7934 | case 0x0fe1: /* psraw */ | |
7935 | case 0x0fe2: /* psrad */ | |
7936 | case 0x0fe3: /* pavgw */ | |
7937 | case 0x0fe4: /* pmulhuw */ | |
7938 | case 0x0fe5: /* pmulhw */ | |
7939 | case 0x0fe8: /* psubsb */ | |
7940 | case 0x0fe9: /* psubsw */ | |
7941 | case 0x0fea: /* pminsw */ | |
7942 | case 0x0feb: /* por */ | |
7943 | case 0x0fec: /* paddsb */ | |
7944 | case 0x0fed: /* paddsw */ | |
7945 | case 0x0fee: /* pmaxsw */ | |
7946 | case 0x0fef: /* pxor */ | |
7947 | case 0x0ff1: /* psllw */ | |
7948 | case 0x0ff2: /* pslld */ | |
7949 | case 0x0ff3: /* psllq */ | |
7950 | case 0x0ff4: /* pmuludq */ | |
7951 | case 0x0ff5: /* pmaddwd */ | |
7952 | case 0x0ff6: /* psadbw */ | |
7953 | case 0x0ff8: /* psubb */ | |
7954 | case 0x0ff9: /* psubw */ | |
56d2815c | 7955 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7956 | case 0x0ffb: /* psubq */ |
7957 | case 0x0ffc: /* paddb */ | |
7958 | case 0x0ffd: /* paddw */ | |
56d2815c | 7959 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7960 | if (i386_record_modrm (&ir)) |
7961 | return -1; | |
7962 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7963 | goto no_support; | |
25ea693b MM |
7964 | record_full_arch_list_add_reg (ir.regcache, |
7965 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7966 | break; |
7967 | ||
7968 | case 0x0f71: /* psllw */ | |
7969 | case 0x0f72: /* pslld */ | |
7970 | case 0x0f73: /* psllq */ | |
7971 | if (i386_record_modrm (&ir)) | |
7972 | return -1; | |
7973 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7974 | goto no_support; | |
25ea693b MM |
7975 | record_full_arch_list_add_reg (ir.regcache, |
7976 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7977 | break; |
7978 | ||
7979 | case 0x660f71: /* psllw */ | |
7980 | case 0x660f72: /* pslld */ | |
7981 | case 0x660f73: /* psllq */ | |
7982 | if (i386_record_modrm (&ir)) | |
7983 | return -1; | |
7984 | ir.rm |= ir.rex_b; | |
c131fcee | 7985 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7986 | goto no_support; |
25ea693b MM |
7987 | record_full_arch_list_add_reg (ir.regcache, |
7988 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7989 | break; |
7990 | ||
7991 | case 0x0f7e: /* movd */ | |
7992 | case 0x660f7e: /* movd */ | |
7993 | if (i386_record_modrm (&ir)) | |
7994 | return -1; | |
7995 | if (ir.mod == 3) | |
25ea693b | 7996 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7997 | else |
7998 | { | |
7999 | if (ir.dflag == 2) | |
8000 | ir.ot = OT_QUAD; | |
8001 | else | |
8002 | ir.ot = OT_LONG; | |
8003 | if (i386_record_lea_modrm (&ir)) | |
8004 | return -1; | |
8005 | } | |
8006 | break; | |
8007 | ||
8008 | case 0x0f7f: /* movq */ | |
8009 | if (i386_record_modrm (&ir)) | |
8010 | return -1; | |
8011 | if (ir.mod == 3) | |
8012 | { | |
8013 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8014 | goto no_support; | |
25ea693b MM |
8015 | record_full_arch_list_add_reg (ir.regcache, |
8016 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8017 | } |
8018 | else | |
8019 | { | |
8020 | ir.ot = OT_QUAD; | |
8021 | if (i386_record_lea_modrm (&ir)) | |
8022 | return -1; | |
8023 | } | |
8024 | break; | |
8025 | ||
8026 | case 0xf30fb8: /* popcnt */ | |
8027 | if (i386_record_modrm (&ir)) | |
8028 | return -1; | |
25ea693b MM |
8029 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8030 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
8031 | break; |
8032 | ||
8033 | case 0x660fd6: /* movq */ | |
8034 | if (i386_record_modrm (&ir)) | |
8035 | return -1; | |
8036 | if (ir.mod == 3) | |
8037 | { | |
8038 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
8039 | if (!i386_xmm_regnum_p (gdbarch, |
8040 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 8041 | goto no_support; |
25ea693b MM |
8042 | record_full_arch_list_add_reg (ir.regcache, |
8043 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8044 | } |
8045 | else | |
8046 | { | |
8047 | ir.ot = OT_QUAD; | |
8048 | if (i386_record_lea_modrm (&ir)) | |
8049 | return -1; | |
8050 | } | |
8051 | break; | |
8052 | ||
8053 | case 0x660f3817: /* ptest */ | |
8054 | case 0x0f2e: /* ucomiss */ | |
8055 | case 0x660f2e: /* ucomisd */ | |
8056 | case 0x0f2f: /* comiss */ | |
8057 | case 0x660f2f: /* comisd */ | |
25ea693b | 8058 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8059 | break; |
8060 | ||
8061 | case 0x0ff7: /* maskmovq */ | |
8062 | regcache_raw_read_unsigned (ir.regcache, | |
8063 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8064 | &addr); | |
25ea693b | 8065 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8066 | return -1; |
8067 | break; | |
8068 | ||
8069 | case 0x660ff7: /* maskmovdqu */ | |
8070 | regcache_raw_read_unsigned (ir.regcache, | |
8071 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8072 | &addr); | |
25ea693b | 8073 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8074 | return -1; |
8075 | break; | |
8076 | ||
8077 | default: | |
8078 | goto no_support; | |
8079 | break; | |
8080 | } | |
8081 | break; | |
7ad10968 HZ |
8082 | |
8083 | default: | |
7ad10968 HZ |
8084 | goto no_support; |
8085 | break; | |
8086 | } | |
8087 | ||
cf648174 | 8088 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8089 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8090 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8091 | return -1; |
8092 | ||
8093 | return 0; | |
8094 | ||
01fe1b41 | 8095 | no_support: |
a3c4230a HZ |
8096 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8097 | "at address %s.\n"), | |
8098 | (unsigned int) (opcode), | |
8099 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8100 | return -1; |
8101 | } | |
8102 | ||
cf648174 HZ |
8103 | static const int i386_record_regmap[] = |
8104 | { | |
8105 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8106 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8107 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8108 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8109 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8110 | }; | |
8111 | ||
7a697b8d | 8112 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8113 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8114 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8115 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8116 | middle of the tracepoint jump. On x86, it may be possible to use |
8117 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8118 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8119 | of instruction to replace, and 0 if not, plus an explanatory |
8120 | string. */ | |
8121 | ||
8122 | static int | |
6b940e6a PL |
8123 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
8124 | char **msg) | |
7a697b8d SS |
8125 | { |
8126 | int len, jumplen; | |
7a697b8d | 8127 | |
405f8e94 SS |
8128 | /* Ask the target for the minimum instruction length supported. */ |
8129 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8130 | ||
8131 | if (jumplen < 0) | |
8132 | { | |
8133 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8134 | operation, assume that fast tracepoints will always be implemented | |
8135 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8136 | jumplen = 5; | |
8137 | } | |
8138 | else if (jumplen == 0) | |
8139 | { | |
8140 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8141 | returns zero, then the IPA has not loaded yet. In this case, | |
8142 | we optimistically assume that truncated 2-byte relative jumps | |
8143 | will be available on x86, and compensate later if this assumption | |
8144 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8145 | jumps will always be used. */ | |
8146 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8147 | } | |
7a697b8d | 8148 | |
7a697b8d | 8149 | /* Check for fit. */ |
be85ce7d | 8150 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8151 | |
7a697b8d SS |
8152 | if (len < jumplen) |
8153 | { | |
8154 | /* Return a bit of target-specific detail to add to the caller's | |
8155 | generic failure message. */ | |
8156 | if (msg) | |
1777feb0 MS |
8157 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8158 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8159 | len, jumplen); |
8160 | return 0; | |
8161 | } | |
405f8e94 SS |
8162 | else |
8163 | { | |
8164 | if (msg) | |
8165 | *msg = NULL; | |
8166 | return 1; | |
8167 | } | |
7a697b8d SS |
8168 | } |
8169 | ||
00d5215e UW |
8170 | /* Return a floating-point format for a floating-point variable of |
8171 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8172 | If no suitable type is found, return NULL. */ | |
8173 | ||
8174 | const struct floatformat ** | |
8175 | i386_floatformat_for_type (struct gdbarch *gdbarch, | |
8176 | const char *name, int len) | |
8177 | { | |
8178 | if (len == 128 && name) | |
8179 | if (strcmp (name, "__float128") == 0 | |
8180 | || strcmp (name, "_Float128") == 0 | |
8181 | || strcmp (name, "complex _Float128") == 0) | |
8182 | return floatformats_ia64_quad; | |
8183 | ||
8184 | return default_floatformat_for_type (gdbarch, name, len); | |
8185 | } | |
8186 | ||
90884b2b L |
8187 | static int |
8188 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8189 | struct tdesc_arch_data *tdesc_data) | |
8190 | { | |
8191 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8192 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8193 | |
8194 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
51547df6 | 8195 | *feature_avx512, *feature_pkeys; |
90884b2b L |
8196 | int i, num_regs, valid_p; |
8197 | ||
8198 | if (! tdesc_has_registers (tdesc)) | |
8199 | return 0; | |
8200 | ||
8201 | /* Get core registers. */ | |
8202 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8203 | if (feature_core == NULL) |
8204 | return 0; | |
90884b2b L |
8205 | |
8206 | /* Get SSE registers. */ | |
c131fcee | 8207 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8208 | |
c131fcee L |
8209 | /* Try AVX registers. */ |
8210 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8211 | ||
1dbcd68c WT |
8212 | /* Try MPX registers. */ |
8213 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8214 | ||
01f9f808 MS |
8215 | /* Try AVX512 registers. */ |
8216 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8217 | ||
51547df6 MS |
8218 | /* Try PKEYS */ |
8219 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8220 | ||
90884b2b L |
8221 | valid_p = 1; |
8222 | ||
c131fcee | 8223 | /* The XCR0 bits. */ |
01f9f808 MS |
8224 | if (feature_avx512) |
8225 | { | |
8226 | /* AVX512 register description requires AVX register description. */ | |
8227 | if (!feature_avx) | |
8228 | return 0; | |
8229 | ||
a1fa17ee | 8230 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8231 | |
8232 | /* It may have been set by OSABI initialization function. */ | |
8233 | if (tdep->k0_regnum < 0) | |
8234 | { | |
8235 | tdep->k_register_names = i386_k_names; | |
8236 | tdep->k0_regnum = I386_K0_REGNUM; | |
8237 | } | |
8238 | ||
8239 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8240 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8241 | tdep->k0_regnum + i, | |
8242 | i386_k_names[i]); | |
8243 | ||
8244 | if (tdep->num_zmm_regs == 0) | |
8245 | { | |
8246 | tdep->zmmh_register_names = i386_zmmh_names; | |
8247 | tdep->num_zmm_regs = 8; | |
8248 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8249 | } | |
8250 | ||
8251 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8252 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8253 | tdep->zmm0h_regnum + i, | |
8254 | tdep->zmmh_register_names[i]); | |
8255 | ||
8256 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8257 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8258 | tdep->xmm16_regnum + i, | |
8259 | tdep->xmm_avx512_register_names[i]); | |
8260 | ||
8261 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8262 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8263 | tdep->ymm16h_regnum + i, | |
8264 | tdep->ymm16h_register_names[i]); | |
8265 | } | |
c131fcee L |
8266 | if (feature_avx) |
8267 | { | |
3a13a53b L |
8268 | /* AVX register description requires SSE register description. */ |
8269 | if (!feature_sse) | |
8270 | return 0; | |
8271 | ||
01f9f808 | 8272 | if (!feature_avx512) |
df7e5265 | 8273 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8274 | |
8275 | /* It may have been set by OSABI initialization function. */ | |
8276 | if (tdep->num_ymm_regs == 0) | |
8277 | { | |
8278 | tdep->ymmh_register_names = i386_ymmh_names; | |
8279 | tdep->num_ymm_regs = 8; | |
8280 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8281 | } | |
8282 | ||
8283 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8284 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8285 | tdep->ymm0h_regnum + i, | |
8286 | tdep->ymmh_register_names[i]); | |
8287 | } | |
3a13a53b | 8288 | else if (feature_sse) |
df7e5265 | 8289 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8290 | else |
8291 | { | |
df7e5265 | 8292 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8293 | tdep->num_xmm_regs = 0; |
8294 | } | |
c131fcee | 8295 | |
90884b2b L |
8296 | num_regs = tdep->num_core_regs; |
8297 | for (i = 0; i < num_regs; i++) | |
8298 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8299 | tdep->register_names[i]); | |
8300 | ||
3a13a53b L |
8301 | if (feature_sse) |
8302 | { | |
8303 | /* Need to include %mxcsr, so add one. */ | |
8304 | num_regs += tdep->num_xmm_regs + 1; | |
8305 | for (; i < num_regs; i++) | |
8306 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8307 | tdep->register_names[i]); | |
8308 | } | |
90884b2b | 8309 | |
1dbcd68c WT |
8310 | if (feature_mpx) |
8311 | { | |
df7e5265 | 8312 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8313 | |
8314 | if (tdep->bnd0r_regnum < 0) | |
8315 | { | |
8316 | tdep->mpx_register_names = i386_mpx_names; | |
8317 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8318 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8319 | } | |
8320 | ||
8321 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8322 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8323 | I387_BND0R_REGNUM (tdep) + i, | |
8324 | tdep->mpx_register_names[i]); | |
8325 | } | |
8326 | ||
51547df6 MS |
8327 | if (feature_pkeys) |
8328 | { | |
8329 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8330 | if (tdep->pkru_regnum < 0) | |
8331 | { | |
8332 | tdep->pkeys_register_names = i386_pkeys_names; | |
8333 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8334 | tdep->num_pkeys_regs = 1; | |
8335 | } | |
8336 | ||
8337 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8338 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8339 | I387_PKRU_REGNUM (tdep) + i, | |
8340 | tdep->pkeys_register_names[i]); | |
8341 | } | |
8342 | ||
90884b2b L |
8343 | return valid_p; |
8344 | } | |
8345 | ||
7ad10968 | 8346 | \f |
ad9eb1fd DE |
8347 | /* Note: This is called for both i386 and amd64. */ |
8348 | ||
7ad10968 HZ |
8349 | static struct gdbarch * |
8350 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8351 | { | |
8352 | struct gdbarch_tdep *tdep; | |
8353 | struct gdbarch *gdbarch; | |
90884b2b L |
8354 | struct tdesc_arch_data *tdesc_data; |
8355 | const struct target_desc *tdesc; | |
1ba53b71 | 8356 | int mm0_regnum; |
c131fcee | 8357 | int ymm0_regnum; |
1dbcd68c WT |
8358 | int bnd0_regnum; |
8359 | int num_bnd_cooked; | |
7ad10968 HZ |
8360 | |
8361 | /* If there is already a candidate, use it. */ | |
8362 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8363 | if (arches != NULL) | |
8364 | return arches->gdbarch; | |
8365 | ||
ad9eb1fd | 8366 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8367 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8368 | gdbarch = gdbarch_alloc (&info, tdep); |
8369 | ||
8370 | /* General-purpose registers. */ | |
7ad10968 HZ |
8371 | tdep->gregset_reg_offset = NULL; |
8372 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8373 | tdep->sizeof_gregset = 0; | |
8374 | ||
8375 | /* Floating-point registers. */ | |
7ad10968 | 8376 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8377 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8378 | |
8379 | /* The default settings include the FPU registers, the MMX registers | |
8380 | and the SSE registers. This can be overridden for a specific ABI | |
8381 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8382 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8383 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8384 | |
8385 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8386 | ||
7ad10968 HZ |
8387 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8388 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8389 | ||
8390 | tdep->jb_pc_offset = -1; | |
8391 | tdep->struct_return = pcc_struct_return; | |
8392 | tdep->sigtramp_start = 0; | |
8393 | tdep->sigtramp_end = 0; | |
8394 | tdep->sigtramp_p = i386_sigtramp_p; | |
8395 | tdep->sigcontext_addr = NULL; | |
8396 | tdep->sc_reg_offset = NULL; | |
8397 | tdep->sc_pc_offset = -1; | |
8398 | tdep->sc_sp_offset = -1; | |
8399 | ||
c131fcee L |
8400 | tdep->xsave_xcr0_offset = -1; |
8401 | ||
cf648174 HZ |
8402 | tdep->record_regmap = i386_record_regmap; |
8403 | ||
205c306f DM |
8404 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8405 | ||
7ad10968 HZ |
8406 | /* The format used for `long double' on almost all i386 targets is |
8407 | the i387 extended floating-point format. In fact, of all targets | |
8408 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8409 | on having a `long double' that's not `long' at all. */ | |
8410 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8411 | ||
8412 | /* Although the i387 extended floating-point has only 80 significant | |
8413 | bits, a `long double' actually takes up 96, probably to enforce | |
8414 | alignment. */ | |
8415 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8416 | ||
00d5215e UW |
8417 | /* Support for floating-point data type variants. */ |
8418 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8419 | ||
7ad10968 HZ |
8420 | /* Register numbers of various important registers. */ |
8421 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8422 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8423 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8424 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8425 | ||
8426 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8427 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8428 | differ in how they number %ebp, %esp, %eflags, and the | |
8429 | floating-point registers, and are implemented by the arrays | |
8430 | dbx_register_map[] and svr4_dbx_register_map in | |
8431 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8432 | gcc/config/i386.c, which it designates as the "default" register | |
8433 | map used in 64bit mode. This last register numbering scheme is | |
8434 | implemented in dbx64_register_map, and is used for AMD64; see | |
8435 | amd64-tdep.c. | |
8436 | ||
8437 | Currently, each GCC i386 target always uses the same register | |
8438 | numbering scheme across all its supported debugging formats | |
8439 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8440 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8441 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8442 | respective config header in a manner independent of the requested | |
8443 | output debugging format. | |
8444 | ||
8445 | This does not match the arrangement below, which presumes that | |
8446 | the SDB and stabs numbering schemes differ from the DWARF and | |
8447 | DWARF 2 ones. The reason for this arrangement is that it is | |
8448 | likely to get the numbering scheme for the target's | |
8449 | default/native debug format right. For targets where GCC is the | |
8450 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8451 | targets where the native toolchain uses a different numbering | |
8452 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8453 | the defaults below will have to be overridden, like | |
8454 | i386_elf_init_abi() does. */ | |
8455 | ||
8456 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8457 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8458 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8459 | ||
8460 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8461 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8462 | |
8463 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8464 | be in use on any of the supported i386 targets. */ | |
8465 | ||
8466 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8467 | ||
8468 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8469 | ||
8470 | /* Call dummy code. */ | |
a9b8d892 JK |
8471 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8472 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8473 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8474 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8475 | |
8476 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8477 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8478 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8479 | ||
8480 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8481 | ||
8482 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8483 | ||
8484 | /* Stack grows downward. */ | |
8485 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8486 | ||
04180708 YQ |
8487 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8488 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8489 | ||
7ad10968 HZ |
8490 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8491 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8492 | ||
8493 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8494 | ||
7ad10968 HZ |
8495 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8496 | ||
8497 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8498 | ||
8499 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8500 | ||
8501 | /* Add the i386 register groups. */ | |
8502 | i386_add_reggroups (gdbarch); | |
90884b2b | 8503 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8504 | |
143985b7 AF |
8505 | /* Helper for function argument information. */ |
8506 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8507 | ||
06da04c6 | 8508 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8509 | appended to the list first, so that it supercedes the DWARF |
8510 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8511 | currently fails). */ |
8512 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8513 | ||
8514 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8515 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8516 | CFI info will be used if it is available. */ |
10458914 | 8517 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8518 | |
acd5c798 | 8519 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8520 | |
1ba53b71 | 8521 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8522 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8523 | i386_pseudo_register_read_value); | |
90884b2b | 8524 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8525 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8526 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8527 | |
8528 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8529 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8530 | ||
c131fcee L |
8531 | /* Override the normal target description method to make the AVX |
8532 | upper halves anonymous. */ | |
8533 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8534 | ||
8535 | /* Even though the default ABI only includes general-purpose registers, | |
8536 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8537 | gap for the upper AVX, MPX and AVX512 registers. */ |
51547df6 | 8538 | set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS); |
90884b2b | 8539 | |
ac04f72b TT |
8540 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8541 | ||
90884b2b L |
8542 | /* Get the x86 target description from INFO. */ |
8543 | tdesc = info.target_desc; | |
8544 | if (! tdesc_has_registers (tdesc)) | |
ca1fa5ee | 8545 | tdesc = i386_target_description (X86_XSTATE_SSE_MASK); |
90884b2b L |
8546 | tdep->tdesc = tdesc; |
8547 | ||
8548 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8549 | tdep->register_names = i386_register_names; | |
8550 | ||
c131fcee L |
8551 | /* No upper YMM registers. */ |
8552 | tdep->ymmh_register_names = NULL; | |
8553 | tdep->ymm0h_regnum = -1; | |
8554 | ||
01f9f808 MS |
8555 | /* No upper ZMM registers. */ |
8556 | tdep->zmmh_register_names = NULL; | |
8557 | tdep->zmm0h_regnum = -1; | |
8558 | ||
8559 | /* No high XMM registers. */ | |
8560 | tdep->xmm_avx512_register_names = NULL; | |
8561 | tdep->xmm16_regnum = -1; | |
8562 | ||
8563 | /* No upper YMM16-31 registers. */ | |
8564 | tdep->ymm16h_register_names = NULL; | |
8565 | tdep->ymm16h_regnum = -1; | |
8566 | ||
1ba53b71 L |
8567 | tdep->num_byte_regs = 8; |
8568 | tdep->num_word_regs = 8; | |
8569 | tdep->num_dword_regs = 0; | |
8570 | tdep->num_mmx_regs = 8; | |
c131fcee | 8571 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8572 | |
1dbcd68c WT |
8573 | /* No MPX registers. */ |
8574 | tdep->bnd0r_regnum = -1; | |
8575 | tdep->bndcfgu_regnum = -1; | |
8576 | ||
01f9f808 MS |
8577 | /* No AVX512 registers. */ |
8578 | tdep->k0_regnum = -1; | |
8579 | tdep->num_zmm_regs = 0; | |
8580 | tdep->num_ymm_avx512_regs = 0; | |
8581 | tdep->num_xmm_avx512_regs = 0; | |
8582 | ||
51547df6 MS |
8583 | /* No PKEYS registers */ |
8584 | tdep->pkru_regnum = -1; | |
8585 | tdep->num_pkeys_regs = 0; | |
8586 | ||
90884b2b L |
8587 | tdesc_data = tdesc_data_alloc (); |
8588 | ||
dde08ee1 PA |
8589 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8590 | ||
6710bf39 SS |
8591 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8592 | ||
c2170eef MM |
8593 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8594 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8595 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8596 | ||
ad9eb1fd DE |
8597 | /* Hook in ABI-specific overrides, if they have been registered. |
8598 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8599 | a 32-bit i386 into a 64-bit amd64. */ | |
0dba2a6c | 8600 | info.tdesc_data = tdesc_data; |
4be87837 | 8601 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8602 | |
c131fcee L |
8603 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8604 | { | |
8605 | tdesc_data_cleanup (tdesc_data); | |
8606 | xfree (tdep); | |
8607 | gdbarch_free (gdbarch); | |
8608 | return NULL; | |
8609 | } | |
8610 | ||
1dbcd68c WT |
8611 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8612 | ||
1ba53b71 L |
8613 | /* Wire in pseudo registers. Number of pseudo registers may be |
8614 | changed. */ | |
8615 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8616 | + tdep->num_word_regs | |
8617 | + tdep->num_dword_regs | |
c131fcee | 8618 | + tdep->num_mmx_regs |
1dbcd68c | 8619 | + tdep->num_ymm_regs |
01f9f808 MS |
8620 | + num_bnd_cooked |
8621 | + tdep->num_ymm_avx512_regs | |
8622 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8623 | |
90884b2b L |
8624 | /* Target description may be changed. */ |
8625 | tdesc = tdep->tdesc; | |
8626 | ||
90884b2b L |
8627 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8628 | ||
8629 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8630 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8631 | ||
1ba53b71 L |
8632 | /* Make %al the first pseudo-register. */ |
8633 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8634 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8635 | ||
c131fcee | 8636 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8637 | if (tdep->num_dword_regs) |
8638 | { | |
1c6272a6 | 8639 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8640 | tdep->eax_regnum = ymm0_regnum; |
8641 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8642 | } |
8643 | else | |
8644 | tdep->eax_regnum = -1; | |
8645 | ||
c131fcee L |
8646 | mm0_regnum = ymm0_regnum; |
8647 | if (tdep->num_ymm_regs) | |
8648 | { | |
1c6272a6 | 8649 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8650 | tdep->ymm0_regnum = ymm0_regnum; |
8651 | mm0_regnum += tdep->num_ymm_regs; | |
8652 | } | |
8653 | else | |
8654 | tdep->ymm0_regnum = -1; | |
8655 | ||
01f9f808 MS |
8656 | if (tdep->num_ymm_avx512_regs) |
8657 | { | |
8658 | /* Support YMM16-31 pseudo registers if available. */ | |
8659 | tdep->ymm16_regnum = mm0_regnum; | |
8660 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8661 | } | |
8662 | else | |
8663 | tdep->ymm16_regnum = -1; | |
8664 | ||
8665 | if (tdep->num_zmm_regs) | |
8666 | { | |
8667 | /* Support ZMM pseudo-register if it is available. */ | |
8668 | tdep->zmm0_regnum = mm0_regnum; | |
8669 | mm0_regnum += tdep->num_zmm_regs; | |
8670 | } | |
8671 | else | |
8672 | tdep->zmm0_regnum = -1; | |
8673 | ||
1dbcd68c | 8674 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8675 | if (tdep->num_mmx_regs != 0) |
8676 | { | |
1c6272a6 | 8677 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8678 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8679 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8680 | } |
8681 | else | |
8682 | tdep->mm0_regnum = -1; | |
8683 | ||
1dbcd68c WT |
8684 | if (tdep->bnd0r_regnum > 0) |
8685 | tdep->bnd0_regnum = bnd0_regnum; | |
8686 | else | |
8687 | tdep-> bnd0_regnum = -1; | |
8688 | ||
06da04c6 | 8689 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8690 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8691 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8692 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8693 | |
8446b36a MK |
8694 | /* If we have a register mapping, enable the generic core file |
8695 | support, unless it has already been enabled. */ | |
8696 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8697 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8698 | set_gdbarch_iterate_over_regset_sections |
8699 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8700 | |
7a697b8d SS |
8701 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8702 | i386_fast_tracepoint_valid_at); | |
8703 | ||
a62cc96e AC |
8704 | return gdbarch; |
8705 | } | |
8706 | ||
8201327c MK |
8707 | \f |
8708 | ||
97de3545 JB |
8709 | /* Return the target description for a specified XSAVE feature mask. */ |
8710 | ||
8711 | const struct target_desc * | |
8712 | i386_target_description (uint64_t xcr0) | |
8713 | { | |
22916b07 YQ |
8714 | static target_desc *i386_tdescs \ |
8715 | [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/] = {}; | |
8716 | target_desc **tdesc; | |
8717 | ||
8718 | tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] | |
8719 | [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
8720 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
8721 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
8722 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0]; | |
8723 | ||
8724 | if (*tdesc == NULL) | |
8725 | *tdesc = i386_create_target_description (xcr0, false); | |
8726 | ||
8727 | return *tdesc; | |
97de3545 JB |
8728 | } |
8729 | ||
29c1c244 WT |
8730 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8731 | ||
8732 | /* Find the bound directory base address. */ | |
8733 | ||
8734 | static unsigned long | |
8735 | i386_mpx_bd_base (void) | |
8736 | { | |
8737 | struct regcache *rcache; | |
8738 | struct gdbarch_tdep *tdep; | |
8739 | ULONGEST ret; | |
8740 | enum register_status regstatus; | |
29c1c244 WT |
8741 | |
8742 | rcache = get_current_regcache (); | |
8743 | tdep = gdbarch_tdep (get_regcache_arch (rcache)); | |
8744 | ||
8745 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8746 | ||
8747 | if (regstatus != REG_VALID) | |
8748 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8749 | ||
8750 | return ret & MPX_BASE_MASK; | |
8751 | } | |
8752 | ||
012b3a21 | 8753 | int |
29c1c244 WT |
8754 | i386_mpx_enabled (void) |
8755 | { | |
8756 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8757 | const struct target_desc *tdesc = tdep->tdesc; | |
8758 | ||
8759 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8760 | } | |
8761 | ||
8762 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8763 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8764 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8765 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8766 | ||
8767 | /* Find the bound table entry given the pointer location and the base | |
8768 | address of the table. */ | |
8769 | ||
8770 | static CORE_ADDR | |
8771 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8772 | { | |
8773 | CORE_ADDR offset1; | |
8774 | CORE_ADDR offset2; | |
8775 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8776 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8777 | CORE_ADDR bd_entry_addr; | |
8778 | CORE_ADDR bt_addr; | |
8779 | CORE_ADDR bd_entry; | |
8780 | struct gdbarch *gdbarch = get_current_arch (); | |
8781 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8782 | ||
8783 | ||
8784 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8785 | { | |
966f0aef | 8786 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8787 | bd_ptr_r_shift = 20; |
8788 | bd_ptr_l_shift = 3; | |
8789 | bt_select_r_shift = 3; | |
8790 | bt_select_l_shift = 5; | |
966f0aef WT |
8791 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8792 | ||
8793 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8794 | error (_("bound table examination not supported\ |
8795 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8796 | } |
8797 | else | |
8798 | { | |
8799 | mpx_bd_mask = MPX_BD_MASK_32; | |
8800 | bd_ptr_r_shift = 12; | |
8801 | bd_ptr_l_shift = 2; | |
8802 | bt_select_r_shift = 2; | |
8803 | bt_select_l_shift = 4; | |
8804 | bt_mask = MPX_BT_MASK_32; | |
8805 | } | |
8806 | ||
8807 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8808 | bd_entry_addr = bd_base + offset1; | |
8809 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8810 | ||
8811 | if ((bd_entry & 0x1) == 0) | |
8812 | error (_("Invalid bounds directory entry at %s."), | |
8813 | paddress (get_current_arch (), bd_entry_addr)); | |
8814 | ||
8815 | /* Clearing status bit. */ | |
8816 | bd_entry--; | |
8817 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8818 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8819 | ||
8820 | return bt_addr + offset2; | |
8821 | } | |
8822 | ||
8823 | /* Print routine for the mpx bounds. */ | |
8824 | ||
8825 | static void | |
8826 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8827 | { | |
8828 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8829 | LONGEST size; |
29c1c244 WT |
8830 | struct gdbarch *gdbarch = get_current_arch (); |
8831 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8832 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8833 | ||
8834 | if (bounds_in_map == 1) | |
8835 | { | |
112e8700 SM |
8836 | uiout->text ("Null bounds on map:"); |
8837 | uiout->text (" pointer value = "); | |
8838 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8839 | uiout->text ("."); | |
8840 | uiout->text ("\n"); | |
29c1c244 WT |
8841 | } |
8842 | else | |
8843 | { | |
112e8700 SM |
8844 | uiout->text ("{lbound = "); |
8845 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8846 | uiout->text (", ubound = "); | |
29c1c244 WT |
8847 | |
8848 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8849 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8850 | uiout->text ("}: pointer value = "); | |
8851 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8852 | |
8853 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8854 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8855 | else | |
8856 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8857 | ||
8858 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8859 | -1 represents in this sense full memory access, and there is no need | |
8860 | one to the size. */ | |
8861 | ||
8862 | size = (size > -1 ? size + 1 : size); | |
112e8700 SM |
8863 | uiout->text (", size = "); |
8864 | uiout->field_fmt ("size", "%s", plongest (size)); | |
29c1c244 | 8865 | |
112e8700 SM |
8866 | uiout->text (", metadata = "); |
8867 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8868 | uiout->text ("\n"); | |
29c1c244 WT |
8869 | } |
8870 | } | |
8871 | ||
8872 | /* Implement the command "show mpx bound". */ | |
8873 | ||
8874 | static void | |
c4a3e68e | 8875 | i386_mpx_info_bounds (const char *args, int from_tty) |
29c1c244 WT |
8876 | { |
8877 | CORE_ADDR bd_base = 0; | |
8878 | CORE_ADDR addr; | |
8879 | CORE_ADDR bt_entry_addr = 0; | |
8880 | CORE_ADDR bt_entry[4]; | |
8881 | int i; | |
8882 | struct gdbarch *gdbarch = get_current_arch (); | |
8883 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8884 | ||
ae71e7b5 MR |
8885 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8886 | || !i386_mpx_enabled ()) | |
118ca224 | 8887 | { |
bc504a31 | 8888 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8889 | "supported on this target.\n")); |
8890 | return; | |
8891 | } | |
29c1c244 WT |
8892 | |
8893 | if (args == NULL) | |
118ca224 PP |
8894 | { |
8895 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8896 | return; | |
8897 | } | |
29c1c244 WT |
8898 | |
8899 | addr = parse_and_eval_address (args); | |
8900 | ||
8901 | bd_base = i386_mpx_bd_base (); | |
8902 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8903 | ||
8904 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8905 | ||
8906 | for (i = 0; i < 4; i++) | |
8907 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8908 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8909 | data_ptr_type); |
8910 | ||
8911 | i386_mpx_print_bounds (bt_entry); | |
8912 | } | |
8913 | ||
8914 | /* Implement the command "set mpx bound". */ | |
8915 | ||
8916 | static void | |
c4a3e68e | 8917 | i386_mpx_set_bounds (const char *args, int from_tty) |
29c1c244 WT |
8918 | { |
8919 | CORE_ADDR bd_base = 0; | |
8920 | CORE_ADDR addr, lower, upper; | |
8921 | CORE_ADDR bt_entry_addr = 0; | |
8922 | CORE_ADDR bt_entry[2]; | |
8923 | const char *input = args; | |
8924 | int i; | |
8925 | struct gdbarch *gdbarch = get_current_arch (); | |
8926 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8927 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8928 | ||
ae71e7b5 MR |
8929 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8930 | || !i386_mpx_enabled ()) | |
bc504a31 | 8931 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
8932 | on this target.")); |
8933 | ||
8934 | if (args == NULL) | |
8935 | error (_("Pointer value expected.")); | |
8936 | ||
8937 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8938 | ||
8939 | if (input[0] == ',') | |
8940 | ++input; | |
8941 | if (input[0] == '\0') | |
8942 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8943 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8944 | ||
8945 | if (input[0] == ',') | |
8946 | ++input; | |
8947 | if (input[0] == '\0') | |
8948 | error (_("Wrong number of arguments; Missing upper bound.")); | |
8949 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
8950 | ||
8951 | bd_base = i386_mpx_bd_base (); | |
8952 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8953 | for (i = 0; i < 2; i++) | |
8954 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8955 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8956 | data_ptr_type); |
8957 | bt_entry[0] = (uint64_t) lower; | |
8958 | bt_entry[1] = ~(uint64_t) upper; | |
8959 | ||
8960 | for (i = 0; i < 2; i++) | |
132874d7 AB |
8961 | write_memory_unsigned_integer (bt_entry_addr |
8962 | + i * TYPE_LENGTH (data_ptr_type), | |
8963 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
8964 | bt_entry[i]); |
8965 | } | |
8966 | ||
8967 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
8968 | ||
8969 | /* Helper function for the CLI commands. */ | |
8970 | ||
8971 | static void | |
981a3fb3 | 8972 | set_mpx_cmd (const char *args, int from_tty) |
29c1c244 | 8973 | { |
118ca224 | 8974 | help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout); |
29c1c244 WT |
8975 | } |
8976 | ||
8977 | /* Helper function for the CLI commands. */ | |
8978 | ||
8979 | static void | |
981a3fb3 | 8980 | show_mpx_cmd (const char *args, int from_tty) |
29c1c244 WT |
8981 | { |
8982 | cmd_show_list (mpx_show_cmdlist, from_tty, ""); | |
8983 | } | |
8984 | ||
c906108c | 8985 | void |
fba45db2 | 8986 | _initialize_i386_tdep (void) |
c906108c | 8987 | { |
a62cc96e AC |
8988 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8989 | ||
fc338970 | 8990 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8991 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8992 | &disassembly_flavor, _("\ | |
8993 | Set the disassembly flavor."), _("\ | |
8994 | Show the disassembly flavor."), _("\ | |
8995 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8996 | NULL, | |
8997 | NULL, /* FIXME: i18n: */ | |
8998 | &setlist, &showlist); | |
8201327c MK |
8999 | |
9000 | /* Add the variable that controls the convention for returning | |
9001 | structs. */ | |
7ab04401 AC |
9002 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9003 | &struct_convention, _("\ | |
9004 | Set the convention for returning small structs."), _("\ | |
9005 | Show the convention for returning small structs."), _("\ | |
9006 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9007 | is \"default\"."), | |
9008 | NULL, | |
9009 | NULL, /* FIXME: i18n: */ | |
9010 | &setlist, &showlist); | |
8201327c | 9011 | |
29c1c244 WT |
9012 | /* Add "mpx" prefix for the set commands. */ |
9013 | ||
9014 | add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\ | |
bc504a31 | 9015 | Set Intel Memory Protection Extensions specific variables."), |
118ca224 | 9016 | &mpx_set_cmdlist, "set mpx ", |
29c1c244 WT |
9017 | 0 /* allow-unknown */, &setlist); |
9018 | ||
9019 | /* Add "mpx" prefix for the show commands. */ | |
9020 | ||
9021 | add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\ | |
bc504a31 | 9022 | Show Intel Memory Protection Extensions specific variables."), |
29c1c244 WT |
9023 | &mpx_show_cmdlist, "show mpx ", |
9024 | 0 /* allow-unknown */, &showlist); | |
9025 | ||
9026 | /* Add "bound" command for the show mpx commands list. */ | |
9027 | ||
9028 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9029 | "Show the memory bounds for a given array/pointer storage\ | |
9030 | in the bound table.", | |
9031 | &mpx_show_cmdlist); | |
9032 | ||
9033 | /* Add "bound" command for the set mpx commands list. */ | |
9034 | ||
9035 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9036 | "Set the memory bounds for a given array/pointer storage\ | |
9037 | in the bound table.", | |
9038 | &mpx_set_cmdlist); | |
9039 | ||
05816f70 | 9040 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9041 | i386_svr4_init_abi); |
38c968cf | 9042 | |
209bd28e | 9043 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9044 | i386_init_reggroups (); |
90884b2b | 9045 | |
c8d5aac9 L |
9046 | /* Tell remote stub that we support XML target description. */ |
9047 | register_remote_support_xml ("i386"); | |
22916b07 YQ |
9048 | |
9049 | #if GDB_SELF_TEST | |
9050 | struct | |
9051 | { | |
9052 | const char *xml; | |
9053 | uint64_t mask; | |
9054 | } xml_masks[] = { | |
9055 | { "i386/i386.xml", X86_XSTATE_SSE_MASK }, | |
9056 | { "i386/i386-mmx.xml", X86_XSTATE_X87_MASK }, | |
9057 | { "i386/i386-avx.xml", X86_XSTATE_AVX_MASK }, | |
9058 | { "i386/i386-mpx.xml", X86_XSTATE_MPX_MASK }, | |
9059 | { "i386/i386-avx-mpx.xml", X86_XSTATE_AVX_MPX_MASK }, | |
9060 | { "i386/i386-avx-avx512.xml", X86_XSTATE_AVX_AVX512_MASK }, | |
9061 | { "i386/i386-avx-mpx-avx512-pku.xml", | |
9062 | X86_XSTATE_AVX_MPX_AVX512_PKU_MASK }, | |
9063 | }; | |
9064 | ||
9065 | for (auto &a : xml_masks) | |
9066 | { | |
9067 | auto tdesc = i386_target_description (a.mask); | |
9068 | ||
9069 | selftests::record_xml_tdesc (a.xml, tdesc); | |
9070 | } | |
9071 | #endif /* GDB_SELF_TEST */ | |
c906108c | 9072 | } |