Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
9b254dd1 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
5ae96ec1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
acd5c798 MK |
23 | #include "arch-utils.h" |
24 | #include "command.h" | |
25 | #include "dummy-frame.h" | |
6405b0a6 | 26 | #include "dwarf2-frame.h" |
acd5c798 | 27 | #include "doublest.h" |
c906108c | 28 | #include "frame.h" |
acd5c798 MK |
29 | #include "frame-base.h" |
30 | #include "frame-unwind.h" | |
c906108c | 31 | #include "inferior.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
acd5c798 | 45 | |
3d261580 | 46 | #include "gdb_assert.h" |
acd5c798 | 47 | #include "gdb_string.h" |
3d261580 | 48 | |
d2a7c97a | 49 | #include "i386-tdep.h" |
61113f8b | 50 | #include "i387-tdep.h" |
d2a7c97a | 51 | |
c4fc7f1b | 52 | /* Register names. */ |
c40e1eab | 53 | |
fc633446 MK |
54 | static char *i386_register_names[] = |
55 | { | |
56 | "eax", "ecx", "edx", "ebx", | |
57 | "esp", "ebp", "esi", "edi", | |
58 | "eip", "eflags", "cs", "ss", | |
59 | "ds", "es", "fs", "gs", | |
60 | "st0", "st1", "st2", "st3", | |
61 | "st4", "st5", "st6", "st7", | |
62 | "fctrl", "fstat", "ftag", "fiseg", | |
63 | "fioff", "foseg", "fooff", "fop", | |
64 | "xmm0", "xmm1", "xmm2", "xmm3", | |
65 | "xmm4", "xmm5", "xmm6", "xmm7", | |
66 | "mxcsr" | |
67 | }; | |
68 | ||
1cb97e17 | 69 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 70 | |
c4fc7f1b | 71 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
72 | |
73 | static char *i386_mmx_names[] = | |
74 | { | |
75 | "mm0", "mm1", "mm2", "mm3", | |
76 | "mm4", "mm5", "mm6", "mm7" | |
77 | }; | |
c40e1eab | 78 | |
1cb97e17 | 79 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 80 | |
28fc6740 | 81 | static int |
5716833c | 82 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 83 | { |
5716833c MK |
84 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
85 | ||
86 | if (mm0_regnum < 0) | |
87 | return 0; | |
88 | ||
89 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
90 | } |
91 | ||
5716833c | 92 | /* SSE register? */ |
23a34459 | 93 | |
5716833c MK |
94 | static int |
95 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 96 | { |
5716833c MK |
97 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
98 | ||
20a6ec49 | 99 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
100 | return 0; |
101 | ||
20a6ec49 MD |
102 | return (I387_XMM0_REGNUM (tdep) <= regnum |
103 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
104 | } |
105 | ||
5716833c MK |
106 | static int |
107 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 108 | { |
5716833c MK |
109 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
110 | ||
20a6ec49 | 111 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
112 | return 0; |
113 | ||
20a6ec49 | 114 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
115 | } |
116 | ||
5716833c | 117 | /* FP register? */ |
23a34459 AC |
118 | |
119 | int | |
20a6ec49 | 120 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 121 | { |
20a6ec49 MD |
122 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
123 | ||
124 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
125 | return 0; |
126 | ||
20a6ec49 MD |
127 | return (I387_ST0_REGNUM (tdep) <= regnum |
128 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
129 | } |
130 | ||
131 | int | |
20a6ec49 | 132 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 133 | { |
20a6ec49 MD |
134 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
135 | ||
136 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
137 | return 0; |
138 | ||
20a6ec49 MD |
139 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
140 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
141 | } |
142 | ||
30b0e2d8 | 143 | /* Return the name of register REGNUM. */ |
fc633446 | 144 | |
fa88f677 | 145 | const char * |
d93859e2 | 146 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 147 | { |
d93859e2 | 148 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
20a6ec49 | 149 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; |
fc633446 | 150 | |
30b0e2d8 MK |
151 | if (regnum >= 0 && regnum < i386_num_register_names) |
152 | return i386_register_names[regnum]; | |
70913449 | 153 | |
c40e1eab | 154 | return NULL; |
fc633446 MK |
155 | } |
156 | ||
c4fc7f1b | 157 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
158 | number used by GDB. */ |
159 | ||
8201327c | 160 | static int |
d3f73121 | 161 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 162 | { |
20a6ec49 MD |
163 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
164 | ||
c4fc7f1b MK |
165 | /* This implements what GCC calls the "default" register map |
166 | (dbx_register_map[]). */ | |
167 | ||
85540d8c MK |
168 | if (reg >= 0 && reg <= 7) |
169 | { | |
9872ad24 JB |
170 | /* General-purpose registers. The debug info calls %ebp |
171 | register 4, and %esp register 5. */ | |
172 | if (reg == 4) | |
173 | return 5; | |
174 | else if (reg == 5) | |
175 | return 4; | |
176 | else return reg; | |
85540d8c MK |
177 | } |
178 | else if (reg >= 12 && reg <= 19) | |
179 | { | |
180 | /* Floating-point registers. */ | |
20a6ec49 | 181 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
182 | } |
183 | else if (reg >= 21 && reg <= 28) | |
184 | { | |
185 | /* SSE registers. */ | |
20a6ec49 | 186 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
187 | } |
188 | else if (reg >= 29 && reg <= 36) | |
189 | { | |
190 | /* MMX registers. */ | |
20a6ec49 | 191 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
192 | } |
193 | ||
194 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 195 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
196 | } |
197 | ||
c4fc7f1b MK |
198 | /* Convert SVR4 register number REG to the appropriate register number |
199 | used by GDB. */ | |
85540d8c | 200 | |
8201327c | 201 | static int |
d3f73121 | 202 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 203 | { |
20a6ec49 MD |
204 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
205 | ||
c4fc7f1b MK |
206 | /* This implements the GCC register map that tries to be compatible |
207 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
208 | ||
209 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
210 | numbers the floating point registers differently. */ |
211 | if (reg >= 0 && reg <= 9) | |
212 | { | |
acd5c798 | 213 | /* General-purpose registers. */ |
85540d8c MK |
214 | return reg; |
215 | } | |
216 | else if (reg >= 11 && reg <= 18) | |
217 | { | |
218 | /* Floating-point registers. */ | |
20a6ec49 | 219 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 220 | } |
c6f4c129 | 221 | else if (reg >= 21 && reg <= 36) |
85540d8c | 222 | { |
c4fc7f1b | 223 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 224 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
225 | } |
226 | ||
c6f4c129 JB |
227 | switch (reg) |
228 | { | |
20a6ec49 MD |
229 | case 37: return I387_FCTRL_REGNUM (tdep); |
230 | case 38: return I387_FSTAT_REGNUM (tdep); | |
231 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
232 | case 40: return I386_ES_REGNUM; |
233 | case 41: return I386_CS_REGNUM; | |
234 | case 42: return I386_SS_REGNUM; | |
235 | case 43: return I386_DS_REGNUM; | |
236 | case 44: return I386_FS_REGNUM; | |
237 | case 45: return I386_GS_REGNUM; | |
238 | } | |
239 | ||
85540d8c | 240 | /* This will hopefully provoke a warning. */ |
d3f73121 | 241 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 242 | } |
5716833c | 243 | |
fc338970 | 244 | \f |
917317f4 | 245 | |
fc338970 MK |
246 | /* This is the variable that is set with "set disassembly-flavor", and |
247 | its legitimate values. */ | |
53904c9e AC |
248 | static const char att_flavor[] = "att"; |
249 | static const char intel_flavor[] = "intel"; | |
250 | static const char *valid_flavors[] = | |
c5aa993b | 251 | { |
c906108c SS |
252 | att_flavor, |
253 | intel_flavor, | |
254 | NULL | |
255 | }; | |
53904c9e | 256 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 257 | \f |
c906108c | 258 | |
acd5c798 MK |
259 | /* Use the program counter to determine the contents and size of a |
260 | breakpoint instruction. Return a pointer to a string of bytes that | |
261 | encode a breakpoint instruction, store the length of the string in | |
262 | *LEN and optionally adjust *PC to point to the correct memory | |
263 | location for inserting the breakpoint. | |
c906108c | 264 | |
acd5c798 MK |
265 | On the i386 we have a single breakpoint that fits in a single byte |
266 | and can be inserted anywhere. | |
c906108c | 267 | |
acd5c798 | 268 | This function is 64-bit safe. */ |
63c0089f MK |
269 | |
270 | static const gdb_byte * | |
67d57894 | 271 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 272 | { |
63c0089f MK |
273 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
274 | ||
acd5c798 MK |
275 | *len = sizeof (break_insn); |
276 | return break_insn; | |
c906108c | 277 | } |
237fc4c9 PA |
278 | \f |
279 | /* Displaced instruction handling. */ | |
280 | ||
281 | ||
282 | static int | |
283 | i386_absolute_jmp_p (gdb_byte *insn) | |
284 | { | |
285 | /* jmp far (absolute address in operand) */ | |
286 | if (insn[0] == 0xea) | |
287 | return 1; | |
288 | ||
289 | if (insn[0] == 0xff) | |
290 | { | |
291 | /* jump near, absolute indirect (/4) */ | |
292 | if ((insn[1] & 0x38) == 0x20) | |
293 | return 1; | |
294 | ||
295 | /* jump far, absolute indirect (/5) */ | |
296 | if ((insn[1] & 0x38) == 0x28) | |
297 | return 1; | |
298 | } | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int | |
304 | i386_absolute_call_p (gdb_byte *insn) | |
305 | { | |
306 | /* call far, absolute */ | |
307 | if (insn[0] == 0x9a) | |
308 | return 1; | |
309 | ||
310 | if (insn[0] == 0xff) | |
311 | { | |
312 | /* Call near, absolute indirect (/2) */ | |
313 | if ((insn[1] & 0x38) == 0x10) | |
314 | return 1; | |
315 | ||
316 | /* Call far, absolute indirect (/3) */ | |
317 | if ((insn[1] & 0x38) == 0x18) | |
318 | return 1; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int | |
325 | i386_ret_p (gdb_byte *insn) | |
326 | { | |
327 | switch (insn[0]) | |
328 | { | |
329 | case 0xc2: /* ret near, pop N bytes */ | |
330 | case 0xc3: /* ret near */ | |
331 | case 0xca: /* ret far, pop N bytes */ | |
332 | case 0xcb: /* ret far */ | |
333 | case 0xcf: /* iret */ | |
334 | return 1; | |
335 | ||
336 | default: | |
337 | return 0; | |
338 | } | |
339 | } | |
340 | ||
341 | static int | |
342 | i386_call_p (gdb_byte *insn) | |
343 | { | |
344 | if (i386_absolute_call_p (insn)) | |
345 | return 1; | |
346 | ||
347 | /* call near, relative */ | |
348 | if (insn[0] == 0xe8) | |
349 | return 1; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
354 | static int | |
355 | i386_breakpoint_p (gdb_byte *insn) | |
356 | { | |
357 | return insn[0] == 0xcc; /* int 3 */ | |
358 | } | |
359 | ||
360 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its | |
361 | length in bytes. Otherwise, return zero. */ | |
362 | static int | |
363 | i386_syscall_p (gdb_byte *insn, ULONGEST *lengthp) | |
364 | { | |
365 | if (insn[0] == 0xcd) | |
366 | { | |
367 | *lengthp = 2; | |
368 | return 1; | |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | /* Fix up the state of registers and memory after having single-stepped | |
375 | a displaced instruction. */ | |
376 | void | |
377 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
378 | struct displaced_step_closure *closure, | |
379 | CORE_ADDR from, CORE_ADDR to, | |
380 | struct regcache *regs) | |
381 | { | |
382 | /* The offset we applied to the instruction's address. | |
383 | This could well be negative (when viewed as a signed 32-bit | |
384 | value), but ULONGEST won't reflect that, so take care when | |
385 | applying it. */ | |
386 | ULONGEST insn_offset = to - from; | |
387 | ||
388 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
389 | copy of the instruction. */ | |
390 | gdb_byte *insn = (gdb_byte *) closure; | |
391 | ||
392 | if (debug_displaced) | |
393 | fprintf_unfiltered (gdb_stdlog, | |
394 | "displaced: fixup (0x%s, 0x%s), " | |
395 | "insn = 0x%02x 0x%02x ...\n", | |
396 | paddr_nz (from), paddr_nz (to), insn[0], insn[1]); | |
397 | ||
398 | /* The list of issues to contend with here is taken from | |
399 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
400 | Yay for Free Software! */ | |
401 | ||
402 | /* Relocate the %eip, if necessary. */ | |
403 | ||
404 | /* Except in the case of absolute or indirect jump or call | |
405 | instructions, or a return instruction, the new eip is relative to | |
406 | the displaced instruction; make it relative. Well, signal | |
407 | handler returns don't need relocation either, but we use the | |
408 | value of %eip to recognize those; see below. */ | |
409 | if (! i386_absolute_jmp_p (insn) | |
410 | && ! i386_absolute_call_p (insn) | |
411 | && ! i386_ret_p (insn)) | |
412 | { | |
413 | ULONGEST orig_eip; | |
414 | ULONGEST insn_len; | |
415 | ||
416 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
417 | ||
418 | /* A signal trampoline system call changes the %eip, resuming | |
419 | execution of the main program after the signal handler has | |
420 | returned. That makes them like 'return' instructions; we | |
421 | shouldn't relocate %eip. | |
422 | ||
423 | But most system calls don't, and we do need to relocate %eip. | |
424 | ||
425 | Our heuristic for distinguishing these cases: if stepping | |
426 | over the system call instruction left control directly after | |
427 | the instruction, the we relocate --- control almost certainly | |
428 | doesn't belong in the displaced copy. Otherwise, we assume | |
429 | the instruction has put control where it belongs, and leave | |
430 | it unrelocated. Goodness help us if there are PC-relative | |
431 | system calls. */ | |
432 | if (i386_syscall_p (insn, &insn_len) | |
433 | && orig_eip != to + insn_len) | |
434 | { | |
435 | if (debug_displaced) | |
436 | fprintf_unfiltered (gdb_stdlog, | |
437 | "displaced: syscall changed %%eip; " | |
438 | "not relocating\n"); | |
439 | } | |
440 | else | |
441 | { | |
442 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
443 | ||
444 | /* If we have stepped over a breakpoint, set the %eip to | |
445 | point at the breakpoint instruction itself. | |
446 | ||
447 | (gdbarch_decr_pc_after_break was never something the core | |
448 | of GDB should have been concerned with; arch-specific | |
449 | code should be making PC values consistent before | |
450 | presenting them to GDB.) */ | |
451 | if (i386_breakpoint_p (insn)) | |
452 | { | |
caac8896 PA |
453 | if (debug_displaced) |
454 | fprintf_unfiltered (gdb_stdlog, | |
455 | "displaced: stepped breakpoint\n"); | |
237fc4c9 PA |
456 | eip--; |
457 | } | |
458 | ||
459 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
460 | ||
461 | if (debug_displaced) | |
462 | fprintf_unfiltered (gdb_stdlog, | |
463 | "displaced: " | |
464 | "relocated %%eip from 0x%s to 0x%s\n", | |
465 | paddr_nz (orig_eip), paddr_nz (eip)); | |
466 | } | |
467 | } | |
468 | ||
469 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
470 | pushed value, and should be cleared. We'll leave this for later, | |
471 | since GDB already messes up the TF flag when stepping over a | |
472 | pushfl. */ | |
473 | ||
474 | /* If the instruction was a call, the return address now atop the | |
475 | stack is the address following the copied instruction. We need | |
476 | to make it the address following the original instruction. */ | |
477 | if (i386_call_p (insn)) | |
478 | { | |
479 | ULONGEST esp; | |
480 | ULONGEST retaddr; | |
481 | const ULONGEST retaddr_len = 4; | |
482 | ||
483 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
484 | retaddr = read_memory_unsigned_integer (esp, retaddr_len); | |
485 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; | |
486 | write_memory_unsigned_integer (esp, retaddr_len, retaddr); | |
487 | ||
488 | if (debug_displaced) | |
489 | fprintf_unfiltered (gdb_stdlog, | |
490 | "displaced: relocated return addr at 0x%s " | |
491 | "to 0x%s\n", | |
492 | paddr_nz (esp), | |
493 | paddr_nz (retaddr)); | |
494 | } | |
495 | } | |
496 | ||
497 | ||
fc338970 | 498 | \f |
acd5c798 MK |
499 | #ifdef I386_REGNO_TO_SYMMETRY |
500 | #error "The Sequent Symmetry is no longer supported." | |
501 | #endif | |
c906108c | 502 | |
acd5c798 MK |
503 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
504 | and %esp "belong" to the calling function. Therefore these | |
505 | registers should be saved if they're going to be modified. */ | |
c906108c | 506 | |
acd5c798 MK |
507 | /* The maximum number of saved registers. This should include all |
508 | registers mentioned above, and %eip. */ | |
a3386186 | 509 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
510 | |
511 | struct i386_frame_cache | |
c906108c | 512 | { |
acd5c798 MK |
513 | /* Base address. */ |
514 | CORE_ADDR base; | |
772562f8 | 515 | LONGEST sp_offset; |
acd5c798 MK |
516 | CORE_ADDR pc; |
517 | ||
fd13a04a AC |
518 | /* Saved registers. */ |
519 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 520 | CORE_ADDR saved_sp; |
92dd43fa | 521 | int stack_align; |
acd5c798 MK |
522 | int pc_in_eax; |
523 | ||
524 | /* Stack space reserved for local variables. */ | |
525 | long locals; | |
526 | }; | |
527 | ||
528 | /* Allocate and initialize a frame cache. */ | |
529 | ||
530 | static struct i386_frame_cache * | |
fd13a04a | 531 | i386_alloc_frame_cache (void) |
acd5c798 MK |
532 | { |
533 | struct i386_frame_cache *cache; | |
534 | int i; | |
535 | ||
536 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
537 | ||
538 | /* Base address. */ | |
539 | cache->base = 0; | |
540 | cache->sp_offset = -4; | |
541 | cache->pc = 0; | |
542 | ||
fd13a04a AC |
543 | /* Saved registers. We initialize these to -1 since zero is a valid |
544 | offset (that's where %ebp is supposed to be stored). */ | |
545 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
546 | cache->saved_regs[i] = -1; | |
acd5c798 | 547 | cache->saved_sp = 0; |
92dd43fa | 548 | cache->stack_align = 0; |
acd5c798 MK |
549 | cache->pc_in_eax = 0; |
550 | ||
551 | /* Frameless until proven otherwise. */ | |
552 | cache->locals = -1; | |
553 | ||
554 | return cache; | |
555 | } | |
c906108c | 556 | |
acd5c798 MK |
557 | /* If the instruction at PC is a jump, return the address of its |
558 | target. Otherwise, return PC. */ | |
c906108c | 559 | |
acd5c798 MK |
560 | static CORE_ADDR |
561 | i386_follow_jump (CORE_ADDR pc) | |
562 | { | |
63c0089f | 563 | gdb_byte op; |
acd5c798 MK |
564 | long delta = 0; |
565 | int data16 = 0; | |
c906108c | 566 | |
8defab1a | 567 | target_read_memory (pc, &op, 1); |
acd5c798 | 568 | if (op == 0x66) |
c906108c | 569 | { |
c906108c | 570 | data16 = 1; |
acd5c798 | 571 | op = read_memory_unsigned_integer (pc + 1, 1); |
c906108c SS |
572 | } |
573 | ||
acd5c798 | 574 | switch (op) |
c906108c SS |
575 | { |
576 | case 0xe9: | |
fc338970 | 577 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
578 | if (data16) |
579 | { | |
acd5c798 | 580 | delta = read_memory_integer (pc + 2, 2); |
c906108c | 581 | |
fc338970 MK |
582 | /* Include the size of the jmp instruction (including the |
583 | 0x66 prefix). */ | |
acd5c798 | 584 | delta += 4; |
c906108c SS |
585 | } |
586 | else | |
587 | { | |
acd5c798 | 588 | delta = read_memory_integer (pc + 1, 4); |
c906108c | 589 | |
acd5c798 MK |
590 | /* Include the size of the jmp instruction. */ |
591 | delta += 5; | |
c906108c SS |
592 | } |
593 | break; | |
594 | case 0xeb: | |
fc338970 | 595 | /* Relative jump, disp8 (ignore data16). */ |
acd5c798 | 596 | delta = read_memory_integer (pc + data16 + 1, 1); |
c906108c | 597 | |
acd5c798 | 598 | delta += data16 + 2; |
c906108c SS |
599 | break; |
600 | } | |
c906108c | 601 | |
acd5c798 MK |
602 | return pc + delta; |
603 | } | |
fc338970 | 604 | |
acd5c798 MK |
605 | /* Check whether PC points at a prologue for a function returning a |
606 | structure or union. If so, it updates CACHE and returns the | |
607 | address of the first instruction after the code sequence that | |
608 | removes the "hidden" argument from the stack or CURRENT_PC, | |
609 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 610 | |
acd5c798 MK |
611 | static CORE_ADDR |
612 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
613 | struct i386_frame_cache *cache) | |
c906108c | 614 | { |
acd5c798 MK |
615 | /* Functions that return a structure or union start with: |
616 | ||
617 | popl %eax 0x58 | |
618 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
619 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
620 | ||
621 | (the System V compiler puts out the second `xchg' instruction, | |
622 | and the assembler doesn't try to optimize it, so the 'sib' form | |
623 | gets generated). This sequence is used to get the address of the | |
624 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
625 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
626 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
627 | gdb_byte buf[4]; | |
628 | gdb_byte op; | |
c906108c | 629 | |
acd5c798 MK |
630 | if (current_pc <= pc) |
631 | return pc; | |
632 | ||
8defab1a | 633 | target_read_memory (pc, &op, 1); |
c906108c | 634 | |
acd5c798 MK |
635 | if (op != 0x58) /* popl %eax */ |
636 | return pc; | |
c906108c | 637 | |
8defab1a | 638 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
639 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
640 | return pc; | |
c906108c | 641 | |
acd5c798 | 642 | if (current_pc == pc) |
c906108c | 643 | { |
acd5c798 MK |
644 | cache->sp_offset += 4; |
645 | return current_pc; | |
c906108c SS |
646 | } |
647 | ||
acd5c798 | 648 | if (current_pc == pc + 1) |
c906108c | 649 | { |
acd5c798 MK |
650 | cache->pc_in_eax = 1; |
651 | return current_pc; | |
652 | } | |
653 | ||
654 | if (buf[1] == proto1[1]) | |
655 | return pc + 4; | |
656 | else | |
657 | return pc + 5; | |
658 | } | |
659 | ||
660 | static CORE_ADDR | |
661 | i386_skip_probe (CORE_ADDR pc) | |
662 | { | |
663 | /* A function may start with | |
fc338970 | 664 | |
acd5c798 MK |
665 | pushl constant |
666 | call _probe | |
667 | addl $4, %esp | |
fc338970 | 668 | |
acd5c798 MK |
669 | followed by |
670 | ||
671 | pushl %ebp | |
fc338970 | 672 | |
acd5c798 | 673 | etc. */ |
63c0089f MK |
674 | gdb_byte buf[8]; |
675 | gdb_byte op; | |
fc338970 | 676 | |
8defab1a | 677 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
678 | |
679 | if (op == 0x68 || op == 0x6a) | |
680 | { | |
681 | int delta; | |
c906108c | 682 | |
acd5c798 MK |
683 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
684 | four-byte operand, depending on the opcode. */ | |
c906108c | 685 | if (op == 0x68) |
acd5c798 | 686 | delta = 5; |
c906108c | 687 | else |
acd5c798 | 688 | delta = 2; |
c906108c | 689 | |
acd5c798 MK |
690 | /* Read the following 8 bytes, which should be `call _probe' (6 |
691 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
692 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 693 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 694 | pc += delta + sizeof (buf); |
c906108c SS |
695 | } |
696 | ||
acd5c798 MK |
697 | return pc; |
698 | } | |
699 | ||
92dd43fa MK |
700 | /* GCC 4.1 and later, can put code in the prologue to realign the |
701 | stack pointer. Check whether PC points to such code, and update | |
702 | CACHE accordingly. Return the first instruction after the code | |
703 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
704 | recognize the code, return PC. */ | |
705 | ||
706 | static CORE_ADDR | |
707 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
708 | struct i386_frame_cache *cache) | |
709 | { | |
92a56b20 JB |
710 | /* The register used by the compiler to perform the stack re-alignment |
711 | is, in order of preference, either %ecx, %edx, or %eax. GCC should | |
712 | never use %ebx as it always treats it as callee-saved, whereas | |
713 | the compiler can only use caller-saved registers. */ | |
ade52156 | 714 | static const gdb_byte insns_ecx[10] = { |
92dd43fa MK |
715 | 0x8d, 0x4c, 0x24, 0x04, /* leal 4(%esp), %ecx */ |
716 | 0x83, 0xe4, 0xf0, /* andl $-16, %esp */ | |
717 | 0xff, 0x71, 0xfc /* pushl -4(%ecx) */ | |
718 | }; | |
ade52156 JB |
719 | static const gdb_byte insns_edx[10] = { |
720 | 0x8d, 0x54, 0x24, 0x04, /* leal 4(%esp), %edx */ | |
721 | 0x83, 0xe4, 0xf0, /* andl $-16, %esp */ | |
722 | 0xff, 0x72, 0xfc /* pushl -4(%edx) */ | |
723 | }; | |
724 | static const gdb_byte insns_eax[10] = { | |
725 | 0x8d, 0x44, 0x24, 0x04, /* leal 4(%esp), %eax */ | |
726 | 0x83, 0xe4, 0xf0, /* andl $-16, %esp */ | |
727 | 0xff, 0x70, 0xfc /* pushl -4(%eax) */ | |
728 | }; | |
92dd43fa MK |
729 | gdb_byte buf[10]; |
730 | ||
731 | if (target_read_memory (pc, buf, sizeof buf) | |
ade52156 JB |
732 | || (memcmp (buf, insns_ecx, sizeof buf) != 0 |
733 | && memcmp (buf, insns_edx, sizeof buf) != 0 | |
734 | && memcmp (buf, insns_eax, sizeof buf) != 0)) | |
92dd43fa MK |
735 | return pc; |
736 | ||
737 | if (current_pc > pc + 4) | |
738 | cache->stack_align = 1; | |
739 | ||
740 | return min (pc + 10, current_pc); | |
741 | } | |
742 | ||
37bdc87e | 743 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 744 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
745 | |
746 | /* Instruction description. */ | |
747 | struct i386_insn | |
748 | { | |
749 | size_t len; | |
237fc4c9 PA |
750 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
751 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
752 | }; |
753 | ||
754 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
755 | the first instruction description that matches. Otherwise, return | |
756 | NULL. */ | |
757 | ||
758 | static struct i386_insn * | |
759 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
760 | { | |
761 | struct i386_insn *insn; | |
63c0089f | 762 | gdb_byte op; |
37bdc87e | 763 | |
8defab1a | 764 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
765 | |
766 | for (insn = skip_insns; insn->len > 0; insn++) | |
767 | { | |
768 | if ((op & insn->mask[0]) == insn->insn[0]) | |
769 | { | |
237fc4c9 | 770 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 771 | int insn_matched = 1; |
37bdc87e MK |
772 | size_t i; |
773 | ||
774 | gdb_assert (insn->len > 1); | |
237fc4c9 | 775 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 776 | |
8defab1a | 777 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
778 | for (i = 1; i < insn->len; i++) |
779 | { | |
780 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 781 | insn_matched = 0; |
37bdc87e | 782 | } |
613e8135 MK |
783 | |
784 | if (insn_matched) | |
785 | return insn; | |
37bdc87e MK |
786 | } |
787 | } | |
788 | ||
789 | return NULL; | |
790 | } | |
791 | ||
792 | /* Some special instructions that might be migrated by GCC into the | |
793 | part of the prologue that sets up the new stack frame. Because the | |
794 | stack frame hasn't been setup yet, no registers have been saved | |
795 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
796 | touched. */ | |
797 | ||
798 | struct i386_insn i386_frame_setup_skip_insns[] = | |
799 | { | |
800 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
801 | ||
802 | ??? Should we handle 16-bit operand-sizes here? */ | |
803 | ||
804 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
805 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
806 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
807 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
808 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
809 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
810 | { 5, { 0xb8 }, { 0xfe } }, | |
811 | /* `movl imm32, %edx' */ | |
812 | { 5, { 0xba }, { 0xff } }, | |
813 | ||
814 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
815 | encoding for `mov m32, %eax'. | |
816 | ||
817 | ??? Should we handle SIB adressing here? | |
818 | ??? Should we handle 16-bit operand-sizes here? */ | |
819 | ||
820 | /* `movl m32, %eax' */ | |
821 | { 5, { 0xa1 }, { 0xff } }, | |
822 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
823 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
824 | /* `movl m32, %edx' */ | |
825 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
826 | ||
827 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
828 | Because of the symmetry, there are actually two ways to encode | |
829 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
830 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
831 | ||
832 | /* `subl %eax, %eax' */ | |
833 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
834 | /* `subl %ecx, %ecx' */ | |
835 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
836 | /* `subl %edx, %edx' */ | |
837 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
838 | /* `xorl %eax, %eax' */ | |
839 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
840 | /* `xorl %ecx, %ecx' */ | |
841 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
842 | /* `xorl %edx, %edx' */ | |
843 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
844 | { 0 } | |
845 | }; | |
846 | ||
e11481da PM |
847 | |
848 | /* Check whether PC points to a no-op instruction. */ | |
849 | static CORE_ADDR | |
850 | i386_skip_noop (CORE_ADDR pc) | |
851 | { | |
852 | gdb_byte op; | |
853 | int check = 1; | |
854 | ||
8defab1a | 855 | target_read_memory (pc, &op, 1); |
e11481da PM |
856 | |
857 | while (check) | |
858 | { | |
859 | check = 0; | |
860 | /* Ignore `nop' instruction. */ | |
861 | if (op == 0x90) | |
862 | { | |
863 | pc += 1; | |
8defab1a | 864 | target_read_memory (pc, &op, 1); |
e11481da PM |
865 | check = 1; |
866 | } | |
867 | /* Ignore no-op instruction `mov %edi, %edi'. | |
868 | Microsoft system dlls often start with | |
869 | a `mov %edi,%edi' instruction. | |
870 | The 5 bytes before the function start are | |
871 | filled with `nop' instructions. | |
872 | This pattern can be used for hot-patching: | |
873 | The `mov %edi, %edi' instruction can be replaced by a | |
874 | near jump to the location of the 5 `nop' instructions | |
875 | which can be replaced by a 32-bit jump to anywhere | |
876 | in the 32-bit address space. */ | |
877 | ||
878 | else if (op == 0x8b) | |
879 | { | |
8defab1a | 880 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
881 | if (op == 0xff) |
882 | { | |
883 | pc += 2; | |
8defab1a | 884 | target_read_memory (pc, &op, 1); |
e11481da PM |
885 | check = 1; |
886 | } | |
887 | } | |
888 | } | |
889 | return pc; | |
890 | } | |
891 | ||
acd5c798 MK |
892 | /* Check whether PC points at a code that sets up a new stack frame. |
893 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
894 | instruction after the sequence that sets up the frame or LIMIT, |
895 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
896 | |
897 | static CORE_ADDR | |
37bdc87e | 898 | i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit, |
acd5c798 MK |
899 | struct i386_frame_cache *cache) |
900 | { | |
37bdc87e | 901 | struct i386_insn *insn; |
63c0089f | 902 | gdb_byte op; |
26604a34 | 903 | int skip = 0; |
acd5c798 | 904 | |
37bdc87e MK |
905 | if (limit <= pc) |
906 | return limit; | |
acd5c798 | 907 | |
8defab1a | 908 | target_read_memory (pc, &op, 1); |
acd5c798 | 909 | |
c906108c | 910 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 911 | { |
acd5c798 MK |
912 | /* Take into account that we've executed the `pushl %ebp' that |
913 | starts this instruction sequence. */ | |
fd13a04a | 914 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 915 | cache->sp_offset += 4; |
37bdc87e | 916 | pc++; |
acd5c798 MK |
917 | |
918 | /* If that's all, return now. */ | |
37bdc87e MK |
919 | if (limit <= pc) |
920 | return limit; | |
26604a34 | 921 | |
b4632131 | 922 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
923 | GCC into the prologue and skip them. At this point in the |
924 | prologue, code should only touch the scratch registers %eax, | |
925 | %ecx and %edx, so while the number of posibilities is sheer, | |
926 | it is limited. | |
5daa5b4e | 927 | |
26604a34 MK |
928 | Make sure we only skip these instructions if we later see the |
929 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 930 | while (pc + skip < limit) |
26604a34 | 931 | { |
37bdc87e MK |
932 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
933 | if (insn == NULL) | |
934 | break; | |
b4632131 | 935 | |
37bdc87e | 936 | skip += insn->len; |
26604a34 MK |
937 | } |
938 | ||
37bdc87e MK |
939 | /* If that's all, return now. */ |
940 | if (limit <= pc + skip) | |
941 | return limit; | |
942 | ||
8defab1a | 943 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 944 | |
26604a34 | 945 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 946 | switch (op) |
c906108c SS |
947 | { |
948 | case 0x8b: | |
37bdc87e MK |
949 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec) |
950 | return pc; | |
c906108c SS |
951 | break; |
952 | case 0x89: | |
37bdc87e MK |
953 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5) |
954 | return pc; | |
c906108c SS |
955 | break; |
956 | default: | |
37bdc87e | 957 | return pc; |
c906108c | 958 | } |
acd5c798 | 959 | |
26604a34 MK |
960 | /* OK, we actually have a frame. We just don't know how large |
961 | it is yet. Set its size to zero. We'll adjust it if | |
962 | necessary. We also now commit to skipping the special | |
963 | instructions mentioned before. */ | |
acd5c798 | 964 | cache->locals = 0; |
37bdc87e | 965 | pc += (skip + 2); |
acd5c798 MK |
966 | |
967 | /* If that's all, return now. */ | |
37bdc87e MK |
968 | if (limit <= pc) |
969 | return limit; | |
acd5c798 | 970 | |
fc338970 MK |
971 | /* Check for stack adjustment |
972 | ||
acd5c798 | 973 | subl $XXX, %esp |
fc338970 | 974 | |
fd35795f | 975 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 976 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 977 | target_read_memory (pc, &op, 1); |
c906108c SS |
978 | if (op == 0x83) |
979 | { | |
fd35795f | 980 | /* `subl' with 8-bit immediate. */ |
37bdc87e | 981 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 982 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 983 | return pc; |
acd5c798 | 984 | |
37bdc87e MK |
985 | /* `subl' with signed 8-bit immediate (though it wouldn't |
986 | make sense to be negative). */ | |
987 | cache->locals = read_memory_integer (pc + 2, 1); | |
988 | return pc + 3; | |
c906108c SS |
989 | } |
990 | else if (op == 0x81) | |
991 | { | |
fd35795f | 992 | /* Maybe it is `subl' with a 32-bit immediate. */ |
37bdc87e | 993 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 994 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 995 | return pc; |
acd5c798 | 996 | |
fd35795f | 997 | /* It is `subl' with a 32-bit immediate. */ |
37bdc87e MK |
998 | cache->locals = read_memory_integer (pc + 2, 4); |
999 | return pc + 6; | |
c906108c SS |
1000 | } |
1001 | else | |
1002 | { | |
acd5c798 | 1003 | /* Some instruction other than `subl'. */ |
37bdc87e | 1004 | return pc; |
c906108c SS |
1005 | } |
1006 | } | |
37bdc87e | 1007 | else if (op == 0xc8) /* enter */ |
c906108c | 1008 | { |
acd5c798 MK |
1009 | cache->locals = read_memory_unsigned_integer (pc + 1, 2); |
1010 | return pc + 4; | |
c906108c | 1011 | } |
21d0e8a4 | 1012 | |
acd5c798 | 1013 | return pc; |
21d0e8a4 MK |
1014 | } |
1015 | ||
acd5c798 MK |
1016 | /* Check whether PC points at code that saves registers on the stack. |
1017 | If so, it updates CACHE and returns the address of the first | |
1018 | instruction after the register saves or CURRENT_PC, whichever is | |
1019 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1020 | |
1021 | static CORE_ADDR | |
acd5c798 MK |
1022 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1023 | struct i386_frame_cache *cache) | |
6bff26de | 1024 | { |
99ab4326 | 1025 | CORE_ADDR offset = 0; |
63c0089f | 1026 | gdb_byte op; |
99ab4326 | 1027 | int i; |
c0d1d883 | 1028 | |
99ab4326 MK |
1029 | if (cache->locals > 0) |
1030 | offset -= cache->locals; | |
1031 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1032 | { | |
8defab1a | 1033 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1034 | if (op < 0x50 || op > 0x57) |
1035 | break; | |
0d17c81d | 1036 | |
99ab4326 MK |
1037 | offset -= 4; |
1038 | cache->saved_regs[op - 0x50] = offset; | |
1039 | cache->sp_offset += 4; | |
1040 | pc++; | |
6bff26de MK |
1041 | } |
1042 | ||
acd5c798 | 1043 | return pc; |
22797942 AC |
1044 | } |
1045 | ||
acd5c798 MK |
1046 | /* Do a full analysis of the prologue at PC and update CACHE |
1047 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1048 | address where the analysis stopped. | |
ed84f6c1 | 1049 | |
fc338970 MK |
1050 | We handle these cases: |
1051 | ||
1052 | The startup sequence can be at the start of the function, or the | |
1053 | function can start with a branch to startup code at the end. | |
1054 | ||
1055 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1056 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1057 | once used in the System V compiler). | |
1058 | ||
1059 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1060 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1061 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1062 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1063 | |
1064 | Next, the registers used by this function are pushed. With the | |
1065 | System V compiler they will always be in the order: %edi, %esi, | |
1066 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1067 | restore %eax); however, the code below is willing to see the pushes | |
1068 | in any order, and will handle up to 8 of them. | |
1069 | ||
1070 | If the setup sequence is at the end of the function, then the next | |
1071 | instruction will be a branch back to the start. */ | |
c906108c | 1072 | |
acd5c798 MK |
1073 | static CORE_ADDR |
1074 | i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
1075 | struct i386_frame_cache *cache) | |
c906108c | 1076 | { |
e11481da | 1077 | pc = i386_skip_noop (pc); |
acd5c798 MK |
1078 | pc = i386_follow_jump (pc); |
1079 | pc = i386_analyze_struct_return (pc, current_pc, cache); | |
1080 | pc = i386_skip_probe (pc); | |
92dd43fa | 1081 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
acd5c798 MK |
1082 | pc = i386_analyze_frame_setup (pc, current_pc, cache); |
1083 | return i386_analyze_register_saves (pc, current_pc, cache); | |
c906108c SS |
1084 | } |
1085 | ||
fc338970 | 1086 | /* Return PC of first real instruction. */ |
c906108c | 1087 | |
3a1e71e3 | 1088 | static CORE_ADDR |
6093d2eb | 1089 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1090 | { |
63c0089f | 1091 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1092 | { |
1093 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1094 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1095 | }; |
acd5c798 MK |
1096 | struct i386_frame_cache cache; |
1097 | CORE_ADDR pc; | |
63c0089f | 1098 | gdb_byte op; |
acd5c798 | 1099 | int i; |
c5aa993b | 1100 | |
acd5c798 MK |
1101 | cache.locals = -1; |
1102 | pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache); | |
1103 | if (cache.locals < 0) | |
1104 | return start_pc; | |
c5aa993b | 1105 | |
acd5c798 | 1106 | /* Found valid frame setup. */ |
c906108c | 1107 | |
fc338970 MK |
1108 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1109 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1110 | %ebx: |
1111 | ||
fc338970 MK |
1112 | call 0x0 |
1113 | popl %ebx | |
1114 | movl %ebx,x(%ebp) (optional) | |
1115 | addl y,%ebx | |
1116 | ||
c906108c SS |
1117 | This code is with the rest of the prologue (at the end of the |
1118 | function), so we have to skip it to get to the first real | |
1119 | instruction at the start of the function. */ | |
c5aa993b | 1120 | |
c906108c SS |
1121 | for (i = 0; i < 6; i++) |
1122 | { | |
8defab1a | 1123 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1124 | if (pic_pat[i] != op) |
c906108c SS |
1125 | break; |
1126 | } | |
1127 | if (i == 6) | |
1128 | { | |
acd5c798 MK |
1129 | int delta = 6; |
1130 | ||
8defab1a | 1131 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1132 | |
c5aa993b | 1133 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1134 | { |
acd5c798 MK |
1135 | op = read_memory_unsigned_integer (pc + delta + 1, 1); |
1136 | ||
fc338970 | 1137 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1138 | delta += 3; |
fc338970 | 1139 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1140 | delta += 6; |
fc338970 | 1141 | else /* Unexpected instruction. */ |
acd5c798 MK |
1142 | delta = 0; |
1143 | ||
8defab1a | 1144 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1145 | } |
acd5c798 | 1146 | |
c5aa993b | 1147 | /* addl y,%ebx */ |
acd5c798 | 1148 | if (delta > 0 && op == 0x81 |
d5d6fca5 | 1149 | && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3) |
c906108c | 1150 | { |
acd5c798 | 1151 | pc += delta + 6; |
c906108c SS |
1152 | } |
1153 | } | |
c5aa993b | 1154 | |
e63bbc88 MK |
1155 | /* If the function starts with a branch (to startup code at the end) |
1156 | the last instruction should bring us back to the first | |
1157 | instruction of the real code. */ | |
1158 | if (i386_follow_jump (start_pc) != start_pc) | |
1159 | pc = i386_follow_jump (pc); | |
1160 | ||
1161 | return pc; | |
c906108c SS |
1162 | } |
1163 | ||
4309257c PM |
1164 | /* Check that the code pointed to by PC corresponds to a call to |
1165 | __main, skip it if so. Return PC otherwise. */ | |
1166 | ||
1167 | CORE_ADDR | |
1168 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1169 | { | |
1170 | gdb_byte op; | |
1171 | ||
1172 | target_read_memory (pc, &op, 1); | |
1173 | if (op == 0xe8) | |
1174 | { | |
1175 | gdb_byte buf[4]; | |
1176 | ||
1177 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1178 | { | |
1179 | /* Make sure address is computed correctly as a 32bit | |
1180 | integer even if CORE_ADDR is 64 bit wide. */ | |
1181 | struct minimal_symbol *s; | |
1182 | CORE_ADDR call_dest = pc + 5 + extract_signed_integer (buf, 4); | |
1183 | ||
1184 | call_dest = call_dest & 0xffffffffU; | |
1185 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1186 | if (s != NULL | |
1187 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1188 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1189 | pc += 5; | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | return pc; | |
1194 | } | |
1195 | ||
acd5c798 | 1196 | /* This function is 64-bit safe. */ |
93924b6b | 1197 | |
acd5c798 MK |
1198 | static CORE_ADDR |
1199 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1200 | { |
63c0089f | 1201 | gdb_byte buf[8]; |
acd5c798 | 1202 | |
875f8d0e | 1203 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
acd5c798 | 1204 | return extract_typed_address (buf, builtin_type_void_func_ptr); |
93924b6b | 1205 | } |
acd5c798 | 1206 | \f |
93924b6b | 1207 | |
acd5c798 | 1208 | /* Normal frames. */ |
c5aa993b | 1209 | |
acd5c798 | 1210 | static struct i386_frame_cache * |
10458914 | 1211 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1212 | { |
acd5c798 | 1213 | struct i386_frame_cache *cache; |
63c0089f | 1214 | gdb_byte buf[4]; |
acd5c798 MK |
1215 | int i; |
1216 | ||
1217 | if (*this_cache) | |
1218 | return *this_cache; | |
1219 | ||
fd13a04a | 1220 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1221 | *this_cache = cache; |
1222 | ||
1223 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1224 | which holds the base address for the current stack frame. | |
1225 | However, for functions that don't need it, the frame pointer is | |
1226 | optional. For these "frameless" functions the frame pointer is | |
1227 | actually the frame pointer of the calling frame. Signal | |
1228 | trampolines are just a special case of a "frameless" function. | |
1229 | They (usually) share their frame pointer with the frame that was | |
1230 | in progress when the signal occurred. */ | |
1231 | ||
10458914 | 1232 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
acd5c798 MK |
1233 | cache->base = extract_unsigned_integer (buf, 4); |
1234 | if (cache->base == 0) | |
1235 | return cache; | |
1236 | ||
1237 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1238 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1239 | |
10458914 | 1240 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1241 | if (cache->pc != 0) |
10458914 | 1242 | i386_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache); |
acd5c798 | 1243 | |
92dd43fa MK |
1244 | if (cache->stack_align) |
1245 | { | |
1246 | /* Saved stack pointer has been saved in %ecx. */ | |
10458914 | 1247 | get_frame_register (this_frame, I386_ECX_REGNUM, buf); |
92dd43fa MK |
1248 | cache->saved_sp = extract_unsigned_integer(buf, 4); |
1249 | } | |
1250 | ||
acd5c798 MK |
1251 | if (cache->locals < 0) |
1252 | { | |
1253 | /* We didn't find a valid frame, which means that CACHE->base | |
1254 | currently holds the frame pointer for our calling frame. If | |
1255 | we're at the start of a function, or somewhere half-way its | |
1256 | prologue, the function's frame probably hasn't been fully | |
1257 | setup yet. Try to reconstruct the base address for the stack | |
1258 | frame by looking at the stack pointer. For truly "frameless" | |
1259 | functions this might work too. */ | |
1260 | ||
92dd43fa MK |
1261 | if (cache->stack_align) |
1262 | { | |
1263 | /* We're halfway aligning the stack. */ | |
1264 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1265 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1266 | ||
1267 | /* This will be added back below. */ | |
1268 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1269 | } | |
1270 | else | |
1271 | { | |
10458914 | 1272 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
92dd43fa MK |
1273 | cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset; |
1274 | } | |
acd5c798 MK |
1275 | } |
1276 | ||
1277 | /* Now that we have the base address for the stack frame we can | |
1278 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1279 | if (cache->saved_sp == 0) |
1280 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1281 | |
acd5c798 MK |
1282 | /* Adjust all the saved registers such that they contain addresses |
1283 | instead of offsets. */ | |
1284 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1285 | if (cache->saved_regs[i] != -1) |
1286 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1287 | |
1288 | return cache; | |
a7769679 MK |
1289 | } |
1290 | ||
3a1e71e3 | 1291 | static void |
10458914 | 1292 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1293 | struct frame_id *this_id) |
c906108c | 1294 | { |
10458914 | 1295 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1296 | |
1297 | /* This marks the outermost frame. */ | |
1298 | if (cache->base == 0) | |
1299 | return; | |
1300 | ||
3e210248 | 1301 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1302 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1303 | } | |
1304 | ||
10458914 DJ |
1305 | static struct value * |
1306 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1307 | int regnum) | |
acd5c798 | 1308 | { |
10458914 | 1309 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1310 | |
1311 | gdb_assert (regnum >= 0); | |
1312 | ||
1313 | /* The System V ABI says that: | |
1314 | ||
1315 | "The flags register contains the system flags, such as the | |
1316 | direction flag and the carry flag. The direction flag must be | |
1317 | set to the forward (that is, zero) direction before entry and | |
1318 | upon exit from a function. Other user flags have no specified | |
1319 | role in the standard calling sequence and are not preserved." | |
1320 | ||
1321 | To guarantee the "upon exit" part of that statement we fake a | |
1322 | saved flags register that has its direction flag cleared. | |
1323 | ||
1324 | Note that GCC doesn't seem to rely on the fact that the direction | |
1325 | flag is cleared after a function return; it always explicitly | |
1326 | clears the flag before operations where it matters. | |
1327 | ||
1328 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1329 | right thing to do. The way we fake the flags register here makes | |
1330 | it impossible to change it. */ | |
1331 | ||
1332 | if (regnum == I386_EFLAGS_REGNUM) | |
1333 | { | |
10458914 | 1334 | ULONGEST val; |
c5aa993b | 1335 | |
10458914 DJ |
1336 | val = get_frame_register_unsigned (this_frame, regnum); |
1337 | val &= ~(1 << 10); | |
1338 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1339 | } |
1211c4e4 | 1340 | |
acd5c798 | 1341 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1342 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1343 | |
1344 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1345 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1346 | |
fd13a04a | 1347 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1348 | return frame_unwind_got_memory (this_frame, regnum, |
1349 | cache->saved_regs[regnum]); | |
fd13a04a | 1350 | |
10458914 | 1351 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1352 | } |
1353 | ||
1354 | static const struct frame_unwind i386_frame_unwind = | |
1355 | { | |
1356 | NORMAL_FRAME, | |
1357 | i386_frame_this_id, | |
10458914 DJ |
1358 | i386_frame_prev_register, |
1359 | NULL, | |
1360 | default_frame_sniffer | |
acd5c798 | 1361 | }; |
acd5c798 MK |
1362 | \f |
1363 | ||
1364 | /* Signal trampolines. */ | |
1365 | ||
1366 | static struct i386_frame_cache * | |
10458914 | 1367 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 MK |
1368 | { |
1369 | struct i386_frame_cache *cache; | |
10458914 | 1370 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1371 | CORE_ADDR addr; |
63c0089f | 1372 | gdb_byte buf[4]; |
acd5c798 MK |
1373 | |
1374 | if (*this_cache) | |
1375 | return *this_cache; | |
1376 | ||
fd13a04a | 1377 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1378 | |
10458914 | 1379 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 MK |
1380 | cache->base = extract_unsigned_integer (buf, 4) - 4; |
1381 | ||
10458914 | 1382 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1383 | if (tdep->sc_reg_offset) |
1384 | { | |
1385 | int i; | |
1386 | ||
1387 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1388 | ||
1389 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1390 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1391 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1392 | } |
1393 | else | |
1394 | { | |
fd13a04a AC |
1395 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1396 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1397 | } |
acd5c798 MK |
1398 | |
1399 | *this_cache = cache; | |
1400 | return cache; | |
1401 | } | |
1402 | ||
1403 | static void | |
10458914 | 1404 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1405 | struct frame_id *this_id) |
1406 | { | |
1407 | struct i386_frame_cache *cache = | |
10458914 | 1408 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1409 | |
3e210248 | 1410 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1411 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1412 | } |
1413 | ||
10458914 DJ |
1414 | static struct value * |
1415 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1416 | void **this_cache, int regnum) | |
acd5c798 MK |
1417 | { |
1418 | /* Make sure we've initialized the cache. */ | |
10458914 | 1419 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1420 | |
10458914 | 1421 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1422 | } |
c0d1d883 | 1423 | |
10458914 DJ |
1424 | static int |
1425 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1426 | struct frame_info *this_frame, | |
1427 | void **this_prologue_cache) | |
acd5c798 | 1428 | { |
10458914 | 1429 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1430 | |
911bc6ee MK |
1431 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1432 | handler. */ | |
1433 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1434 | return 0; |
1c3545ae | 1435 | |
911bc6ee MK |
1436 | if (tdep->sigtramp_p != NULL) |
1437 | { | |
10458914 DJ |
1438 | if (tdep->sigtramp_p (this_frame)) |
1439 | return 1; | |
911bc6ee MK |
1440 | } |
1441 | ||
1442 | if (tdep->sigtramp_start != 0) | |
1443 | { | |
10458914 | 1444 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1445 | |
1446 | gdb_assert (tdep->sigtramp_end != 0); | |
1447 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1448 | return 1; |
911bc6ee | 1449 | } |
acd5c798 | 1450 | |
10458914 | 1451 | return 0; |
acd5c798 | 1452 | } |
10458914 DJ |
1453 | |
1454 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1455 | { | |
1456 | SIGTRAMP_FRAME, | |
1457 | i386_sigtramp_frame_this_id, | |
1458 | i386_sigtramp_frame_prev_register, | |
1459 | NULL, | |
1460 | i386_sigtramp_frame_sniffer | |
1461 | }; | |
acd5c798 MK |
1462 | \f |
1463 | ||
1464 | static CORE_ADDR | |
10458914 | 1465 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1466 | { |
10458914 | 1467 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1468 | |
1469 | return cache->base; | |
1470 | } | |
1471 | ||
1472 | static const struct frame_base i386_frame_base = | |
1473 | { | |
1474 | &i386_frame_unwind, | |
1475 | i386_frame_base_address, | |
1476 | i386_frame_base_address, | |
1477 | i386_frame_base_address | |
1478 | }; | |
1479 | ||
acd5c798 | 1480 | static struct frame_id |
10458914 | 1481 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1482 | { |
acd5c798 MK |
1483 | CORE_ADDR fp; |
1484 | ||
10458914 | 1485 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1486 | |
3e210248 | 1487 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1488 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1489 | } |
fc338970 | 1490 | \f |
c906108c | 1491 | |
fc338970 MK |
1492 | /* Figure out where the longjmp will land. Slurp the args out of the |
1493 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1494 | structure from which we extract the address that we will land at. |
28bcfd30 | 1495 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1496 | success. */ |
c906108c | 1497 | |
8201327c | 1498 | static int |
60ade65d | 1499 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1500 | { |
436675d3 | 1501 | gdb_byte buf[4]; |
c906108c | 1502 | CORE_ADDR sp, jb_addr; |
20a6ec49 MD |
1503 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1504 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
c906108c | 1505 | |
8201327c MK |
1506 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1507 | longjmp will land. */ | |
1508 | if (jb_pc_offset == -1) | |
c906108c SS |
1509 | return 0; |
1510 | ||
436675d3 PA |
1511 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
1512 | sp = extract_unsigned_integer (buf, 4); | |
1513 | if (target_read_memory (sp + 4, buf, 4)) | |
c906108c SS |
1514 | return 0; |
1515 | ||
436675d3 PA |
1516 | jb_addr = extract_unsigned_integer (buf, 4); |
1517 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) | |
8201327c | 1518 | return 0; |
c906108c | 1519 | |
436675d3 | 1520 | *pc = extract_unsigned_integer (buf, 4); |
c906108c SS |
1521 | return 1; |
1522 | } | |
fc338970 | 1523 | \f |
c906108c | 1524 | |
7ccc1c74 JM |
1525 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1526 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1527 | unions containing such types must be 16-byte-aligned; other | |
1528 | arguments are 4-byte-aligned. */ | |
1529 | ||
1530 | static int | |
1531 | i386_16_byte_align_p (struct type *type) | |
1532 | { | |
1533 | type = check_typedef (type); | |
1534 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1535 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1536 | && TYPE_LENGTH (type) == 16) | |
1537 | return 1; | |
1538 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1539 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1540 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1541 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1542 | { | |
1543 | int i; | |
1544 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1545 | { | |
1546 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1547 | return 1; | |
1548 | } | |
1549 | } | |
1550 | return 0; | |
1551 | } | |
1552 | ||
3a1e71e3 | 1553 | static CORE_ADDR |
7d9b040b | 1554 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1555 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1556 | struct value **args, CORE_ADDR sp, int struct_return, | |
1557 | CORE_ADDR struct_addr) | |
22f8ba57 | 1558 | { |
63c0089f | 1559 | gdb_byte buf[4]; |
acd5c798 | 1560 | int i; |
7ccc1c74 JM |
1561 | int write_pass; |
1562 | int args_space = 0; | |
acd5c798 | 1563 | |
7ccc1c74 JM |
1564 | /* Determine the total space required for arguments and struct |
1565 | return address in a first pass (allowing for 16-byte-aligned | |
1566 | arguments), then push arguments in a second pass. */ | |
1567 | ||
1568 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1569 | { |
7ccc1c74 JM |
1570 | int args_space_used = 0; |
1571 | int have_16_byte_aligned_arg = 0; | |
1572 | ||
1573 | if (struct_return) | |
1574 | { | |
1575 | if (write_pass) | |
1576 | { | |
1577 | /* Push value address. */ | |
1578 | store_unsigned_integer (buf, 4, struct_addr); | |
1579 | write_memory (sp, buf, 4); | |
1580 | args_space_used += 4; | |
1581 | } | |
1582 | else | |
1583 | args_space += 4; | |
1584 | } | |
1585 | ||
1586 | for (i = 0; i < nargs; i++) | |
1587 | { | |
1588 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1589 | |
7ccc1c74 JM |
1590 | if (write_pass) |
1591 | { | |
1592 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1593 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1594 | |
7ccc1c74 JM |
1595 | write_memory (sp + args_space_used, |
1596 | value_contents_all (args[i]), len); | |
1597 | /* The System V ABI says that: | |
acd5c798 | 1598 | |
7ccc1c74 JM |
1599 | "An argument's size is increased, if necessary, to make it a |
1600 | multiple of [32-bit] words. This may require tail padding, | |
1601 | depending on the size of the argument." | |
22f8ba57 | 1602 | |
7ccc1c74 JM |
1603 | This makes sure the stack stays word-aligned. */ |
1604 | args_space_used += align_up (len, 4); | |
1605 | } | |
1606 | else | |
1607 | { | |
1608 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1609 | { | |
1610 | args_space = align_up (args_space, 16); | |
1611 | have_16_byte_aligned_arg = 1; | |
1612 | } | |
1613 | args_space += align_up (len, 4); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | if (!write_pass) | |
1618 | { | |
1619 | if (have_16_byte_aligned_arg) | |
1620 | args_space = align_up (args_space, 16); | |
1621 | sp -= args_space; | |
1622 | } | |
22f8ba57 MK |
1623 | } |
1624 | ||
acd5c798 MK |
1625 | /* Store return address. */ |
1626 | sp -= 4; | |
6a65450a | 1627 | store_unsigned_integer (buf, 4, bp_addr); |
acd5c798 MK |
1628 | write_memory (sp, buf, 4); |
1629 | ||
1630 | /* Finally, update the stack pointer... */ | |
1631 | store_unsigned_integer (buf, 4, sp); | |
1632 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); | |
1633 | ||
1634 | /* ...and fake a frame pointer. */ | |
1635 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1636 | ||
3e210248 AC |
1637 | /* MarkK wrote: This "+ 8" is all over the place: |
1638 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1639 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1640 | a given target have to agree (within a certain margin) on the |
fd35795f | 1641 | definition of the stack address of a frame. Otherwise |
3e210248 AC |
1642 | frame_id_inner() won't work correctly. Since DWARF2/GCC uses the |
1643 | stack address *before* the function call as a frame's CFA. On | |
1644 | the i386, when %ebp is used as a frame pointer, the offset | |
1645 | between the contents %ebp and the CFA as defined by GCC. */ | |
1646 | return sp + 8; | |
22f8ba57 MK |
1647 | } |
1648 | ||
1a309862 MK |
1649 | /* These registers are used for returning integers (and on some |
1650 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1651 | size and alignment match an integer type). */ |
acd5c798 MK |
1652 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1653 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1654 | |
c5e656c1 MK |
1655 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1656 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1657 | |
3a1e71e3 | 1658 | static void |
c5e656c1 | 1659 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1660 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1661 | { |
c5e656c1 | 1662 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1663 | int len = TYPE_LENGTH (type); |
63c0089f | 1664 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1665 | |
1e8d0a7b | 1666 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1667 | { |
5716833c | 1668 | if (tdep->st0_regnum < 0) |
1a309862 | 1669 | { |
8a3fe4f8 | 1670 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1671 | memset (valbuf, 0, len); |
ef9dff19 | 1672 | return; |
1a309862 MK |
1673 | } |
1674 | ||
c6ba6f0d MK |
1675 | /* Floating-point return values can be found in %st(0). Convert |
1676 | its contents to the desired type. This is probably not | |
1677 | exactly how it would happen on the target itself, but it is | |
1678 | the best we can do. */ | |
acd5c798 | 1679 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
00f8375e | 1680 | convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type); |
c906108c SS |
1681 | } |
1682 | else | |
c5aa993b | 1683 | { |
875f8d0e UW |
1684 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1685 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1686 | |
1687 | if (len <= low_size) | |
00f8375e | 1688 | { |
0818c12a | 1689 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1690 | memcpy (valbuf, buf, len); |
1691 | } | |
d4f3574e SS |
1692 | else if (len <= (low_size + high_size)) |
1693 | { | |
0818c12a | 1694 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1695 | memcpy (valbuf, buf, low_size); |
0818c12a | 1696 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1697 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1698 | } |
1699 | else | |
8e65ff28 | 1700 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1701 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1702 | } |
1703 | } | |
1704 | ||
c5e656c1 MK |
1705 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1706 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1707 | |
3a1e71e3 | 1708 | static void |
c5e656c1 | 1709 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1710 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1711 | { |
c5e656c1 | 1712 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1713 | int len = TYPE_LENGTH (type); |
1714 | ||
1e8d0a7b | 1715 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1716 | { |
3d7f4f49 | 1717 | ULONGEST fstat; |
63c0089f | 1718 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1719 | |
5716833c | 1720 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1721 | { |
8a3fe4f8 | 1722 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1723 | return; |
1724 | } | |
1725 | ||
635b0cc1 MK |
1726 | /* Returning floating-point values is a bit tricky. Apart from |
1727 | storing the return value in %st(0), we have to simulate the | |
1728 | state of the FPU at function return point. */ | |
1729 | ||
c6ba6f0d MK |
1730 | /* Convert the value found in VALBUF to the extended |
1731 | floating-point format used by the FPU. This is probably | |
1732 | not exactly how it would happen on the target itself, but | |
1733 | it is the best we can do. */ | |
1734 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
acd5c798 | 1735 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1736 | |
635b0cc1 MK |
1737 | /* Set the top of the floating-point register stack to 7. The |
1738 | actual value doesn't really matter, but 7 is what a normal | |
1739 | function return would end up with if the program started out | |
1740 | with a freshly initialized FPU. */ | |
20a6ec49 | 1741 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1742 | fstat |= (7 << 11); |
20a6ec49 | 1743 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1744 | |
635b0cc1 MK |
1745 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1746 | the floating-point register stack to 7, the appropriate value | |
1747 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1748 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1749 | } |
1750 | else | |
1751 | { | |
875f8d0e UW |
1752 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1753 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1754 | |
1755 | if (len <= low_size) | |
3d7f4f49 | 1756 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1757 | else if (len <= (low_size + high_size)) |
1758 | { | |
3d7f4f49 MK |
1759 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1760 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1761 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1762 | } |
1763 | else | |
8e65ff28 | 1764 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1765 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1766 | } |
1767 | } | |
fc338970 | 1768 | \f |
ef9dff19 | 1769 | |
8201327c MK |
1770 | /* This is the variable that is set with "set struct-convention", and |
1771 | its legitimate values. */ | |
1772 | static const char default_struct_convention[] = "default"; | |
1773 | static const char pcc_struct_convention[] = "pcc"; | |
1774 | static const char reg_struct_convention[] = "reg"; | |
1775 | static const char *valid_conventions[] = | |
1776 | { | |
1777 | default_struct_convention, | |
1778 | pcc_struct_convention, | |
1779 | reg_struct_convention, | |
1780 | NULL | |
1781 | }; | |
1782 | static const char *struct_convention = default_struct_convention; | |
1783 | ||
0e4377e1 JB |
1784 | /* Return non-zero if TYPE, which is assumed to be a structure, |
1785 | a union type, or an array type, should be returned in registers | |
1786 | for architecture GDBARCH. */ | |
c5e656c1 | 1787 | |
8201327c | 1788 | static int |
c5e656c1 | 1789 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 1790 | { |
c5e656c1 MK |
1791 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1792 | enum type_code code = TYPE_CODE (type); | |
1793 | int len = TYPE_LENGTH (type); | |
8201327c | 1794 | |
0e4377e1 JB |
1795 | gdb_assert (code == TYPE_CODE_STRUCT |
1796 | || code == TYPE_CODE_UNION | |
1797 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
1798 | |
1799 | if (struct_convention == pcc_struct_convention | |
1800 | || (struct_convention == default_struct_convention | |
1801 | && tdep->struct_return == pcc_struct_return)) | |
1802 | return 0; | |
1803 | ||
9edde48e MK |
1804 | /* Structures consisting of a single `float', `double' or 'long |
1805 | double' member are returned in %st(0). */ | |
1806 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
1807 | { | |
1808 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1809 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1810 | return (len == 4 || len == 8 || len == 12); | |
1811 | } | |
1812 | ||
c5e656c1 MK |
1813 | return (len == 1 || len == 2 || len == 4 || len == 8); |
1814 | } | |
1815 | ||
1816 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
1817 | should be returned. If it is supposed to be returned in registers, | |
1818 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
1819 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
1820 | from WRITEBUF into REGCACHE. */ | |
1821 | ||
1822 | static enum return_value_convention | |
c055b101 CV |
1823 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1824 | struct type *type, struct regcache *regcache, | |
1825 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
1826 | { |
1827 | enum type_code code = TYPE_CODE (type); | |
1828 | ||
5daa78cc TJB |
1829 | if (((code == TYPE_CODE_STRUCT |
1830 | || code == TYPE_CODE_UNION | |
1831 | || code == TYPE_CODE_ARRAY) | |
1832 | && !i386_reg_struct_return_p (gdbarch, type)) | |
1833 | /* 128-bit decimal float uses the struct return convention. */ | |
1834 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
1835 | { |
1836 | /* The System V ABI says that: | |
1837 | ||
1838 | "A function that returns a structure or union also sets %eax | |
1839 | to the value of the original address of the caller's area | |
1840 | before it returns. Thus when the caller receives control | |
1841 | again, the address of the returned object resides in register | |
1842 | %eax and can be used to access the object." | |
1843 | ||
1844 | So the ABI guarantees that we can always find the return | |
1845 | value just after the function has returned. */ | |
1846 | ||
0e4377e1 JB |
1847 | /* Note that the ABI doesn't mention functions returning arrays, |
1848 | which is something possible in certain languages such as Ada. | |
1849 | In this case, the value is returned as if it was wrapped in | |
1850 | a record, so the convention applied to records also applies | |
1851 | to arrays. */ | |
1852 | ||
31db7b6c MK |
1853 | if (readbuf) |
1854 | { | |
1855 | ULONGEST addr; | |
1856 | ||
1857 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
1858 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1859 | } | |
1860 | ||
1861 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
1862 | } | |
c5e656c1 MK |
1863 | |
1864 | /* This special case is for structures consisting of a single | |
9edde48e MK |
1865 | `float', `double' or 'long double' member. These structures are |
1866 | returned in %st(0). For these structures, we call ourselves | |
1867 | recursively, changing TYPE into the type of the first member of | |
1868 | the structure. Since that should work for all structures that | |
1869 | have only one member, we don't bother to check the member's type | |
1870 | here. */ | |
c5e656c1 MK |
1871 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
1872 | { | |
1873 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
1874 | return i386_return_value (gdbarch, func_type, type, regcache, |
1875 | readbuf, writebuf); | |
c5e656c1 MK |
1876 | } |
1877 | ||
1878 | if (readbuf) | |
1879 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
1880 | if (writebuf) | |
1881 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 1882 | |
c5e656c1 | 1883 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
1884 | } |
1885 | \f | |
1886 | ||
5ae96ec1 MK |
1887 | /* Type for %eflags. */ |
1888 | struct type *i386_eflags_type; | |
1889 | ||
794ac428 | 1890 | /* Type for %mxcsr. */ |
878d9193 | 1891 | struct type *i386_mxcsr_type; |
5ae96ec1 MK |
1892 | |
1893 | /* Construct types for ISA-specific registers. */ | |
1894 | static void | |
1895 | i386_init_types (void) | |
1896 | { | |
1897 | struct type *type; | |
1898 | ||
1899 | type = init_flags_type ("builtin_type_i386_eflags", 4); | |
1900 | append_flags_type_flag (type, 0, "CF"); | |
1901 | append_flags_type_flag (type, 1, NULL); | |
1902 | append_flags_type_flag (type, 2, "PF"); | |
1903 | append_flags_type_flag (type, 4, "AF"); | |
1904 | append_flags_type_flag (type, 6, "ZF"); | |
1905 | append_flags_type_flag (type, 7, "SF"); | |
1906 | append_flags_type_flag (type, 8, "TF"); | |
1907 | append_flags_type_flag (type, 9, "IF"); | |
1908 | append_flags_type_flag (type, 10, "DF"); | |
1909 | append_flags_type_flag (type, 11, "OF"); | |
1910 | append_flags_type_flag (type, 14, "NT"); | |
1911 | append_flags_type_flag (type, 16, "RF"); | |
1912 | append_flags_type_flag (type, 17, "VM"); | |
1913 | append_flags_type_flag (type, 18, "AC"); | |
1914 | append_flags_type_flag (type, 19, "VIF"); | |
1915 | append_flags_type_flag (type, 20, "VIP"); | |
1916 | append_flags_type_flag (type, 21, "ID"); | |
1917 | i386_eflags_type = type; | |
21b4b2f2 | 1918 | |
878d9193 MK |
1919 | type = init_flags_type ("builtin_type_i386_mxcsr", 4); |
1920 | append_flags_type_flag (type, 0, "IE"); | |
1921 | append_flags_type_flag (type, 1, "DE"); | |
1922 | append_flags_type_flag (type, 2, "ZE"); | |
1923 | append_flags_type_flag (type, 3, "OE"); | |
1924 | append_flags_type_flag (type, 4, "UE"); | |
1925 | append_flags_type_flag (type, 5, "PE"); | |
1926 | append_flags_type_flag (type, 6, "DAZ"); | |
1927 | append_flags_type_flag (type, 7, "IM"); | |
1928 | append_flags_type_flag (type, 8, "DM"); | |
1929 | append_flags_type_flag (type, 9, "ZM"); | |
1930 | append_flags_type_flag (type, 10, "OM"); | |
1931 | append_flags_type_flag (type, 11, "UM"); | |
1932 | append_flags_type_flag (type, 12, "PM"); | |
1933 | append_flags_type_flag (type, 15, "FZ"); | |
1934 | i386_mxcsr_type = type; | |
21b4b2f2 JB |
1935 | } |
1936 | ||
794ac428 UW |
1937 | /* Construct vector type for MMX registers. */ |
1938 | struct type * | |
1939 | i386_mmx_type (struct gdbarch *gdbarch) | |
1940 | { | |
1941 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1942 | ||
1943 | if (!tdep->i386_mmx_type) | |
1944 | { | |
1945 | /* The type we're building is this: */ | |
1946 | #if 0 | |
1947 | union __gdb_builtin_type_vec64i | |
1948 | { | |
1949 | int64_t uint64; | |
1950 | int32_t v2_int32[2]; | |
1951 | int16_t v4_int16[4]; | |
1952 | int8_t v8_int8[8]; | |
1953 | }; | |
1954 | #endif | |
1955 | ||
1956 | struct type *t; | |
1957 | ||
1958 | t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
1959 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
1960 | append_composite_type_field (t, "v2_int32", | |
1961 | init_vector_type (builtin_type_int32, 2)); | |
1962 | append_composite_type_field (t, "v4_int16", | |
1963 | init_vector_type (builtin_type_int16, 4)); | |
1964 | append_composite_type_field (t, "v8_int8", | |
1965 | init_vector_type (builtin_type_int8, 8)); | |
1966 | ||
1967 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
1968 | TYPE_NAME (t) = "builtin_type_vec64i"; | |
1969 | tdep->i386_mmx_type = t; | |
1970 | } | |
1971 | ||
1972 | return tdep->i386_mmx_type; | |
1973 | } | |
1974 | ||
1975 | struct type * | |
1976 | i386_sse_type (struct gdbarch *gdbarch) | |
1977 | { | |
1978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1979 | ||
1980 | if (!tdep->i386_sse_type) | |
1981 | { | |
1982 | /* The type we're building is this: */ | |
1983 | #if 0 | |
1984 | union __gdb_builtin_type_vec128i | |
1985 | { | |
1986 | int128_t uint128; | |
1987 | int64_t v2_int64[2]; | |
1988 | int32_t v4_int32[4]; | |
1989 | int16_t v8_int16[8]; | |
1990 | int8_t v16_int8[16]; | |
1991 | double v2_double[2]; | |
1992 | float v4_float[4]; | |
1993 | }; | |
1994 | #endif | |
1995 | ||
1996 | struct type *t; | |
1997 | ||
1998 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
1999 | append_composite_type_field (t, "v4_float", | |
2000 | init_vector_type (builtin_type_float, 4)); | |
2001 | append_composite_type_field (t, "v2_double", | |
2002 | init_vector_type (builtin_type_double, 2)); | |
2003 | append_composite_type_field (t, "v16_int8", | |
2004 | init_vector_type (builtin_type_int8, 16)); | |
2005 | append_composite_type_field (t, "v8_int16", | |
2006 | init_vector_type (builtin_type_int16, 8)); | |
2007 | append_composite_type_field (t, "v4_int32", | |
2008 | init_vector_type (builtin_type_int32, 4)); | |
2009 | append_composite_type_field (t, "v2_int64", | |
2010 | init_vector_type (builtin_type_int64, 2)); | |
2011 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
2012 | ||
2013 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
2014 | TYPE_NAME (t) = "builtin_type_vec128i"; | |
2015 | tdep->i386_sse_type = t; | |
2016 | } | |
2017 | ||
2018 | return tdep->i386_sse_type; | |
2019 | } | |
2020 | ||
d7a0d72c MK |
2021 | /* Return the GDB type object for the "standard" data type of data in |
2022 | register REGNUM. Perhaps %esi and %edi should go here, but | |
2023 | potentially they could be used for things other than address. */ | |
2024 | ||
3a1e71e3 | 2025 | static struct type * |
4e259f09 | 2026 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2027 | { |
ab533587 MK |
2028 | if (regnum == I386_EIP_REGNUM) |
2029 | return builtin_type_void_func_ptr; | |
2030 | ||
5ae96ec1 MK |
2031 | if (regnum == I386_EFLAGS_REGNUM) |
2032 | return i386_eflags_type; | |
2033 | ||
ab533587 MK |
2034 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) |
2035 | return builtin_type_void_data_ptr; | |
d7a0d72c | 2036 | |
20a6ec49 | 2037 | if (i386_fp_regnum_p (gdbarch, regnum)) |
c6ba6f0d | 2038 | return builtin_type_i387_ext; |
d7a0d72c | 2039 | |
878d9193 | 2040 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
794ac428 | 2041 | return i386_mmx_type (gdbarch); |
878d9193 | 2042 | |
5716833c | 2043 | if (i386_sse_regnum_p (gdbarch, regnum)) |
794ac428 | 2044 | return i386_sse_type (gdbarch); |
d7a0d72c | 2045 | |
20a6ec49 | 2046 | if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch))) |
878d9193 MK |
2047 | return i386_mxcsr_type; |
2048 | ||
d7a0d72c MK |
2049 | return builtin_type_int; |
2050 | } | |
2051 | ||
28fc6740 | 2052 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2053 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2054 | |
2055 | static int | |
c86c27af | 2056 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2057 | { |
5716833c MK |
2058 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2059 | int mmxreg, fpreg; | |
28fc6740 AC |
2060 | ULONGEST fstat; |
2061 | int tos; | |
c86c27af | 2062 | |
5716833c | 2063 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2064 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2065 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2066 | fpreg = (mmxreg + tos) % 8; |
2067 | ||
20a6ec49 | 2068 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2069 | } |
2070 | ||
2071 | static void | |
2072 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2073 | int regnum, gdb_byte *buf) |
28fc6740 | 2074 | { |
5716833c | 2075 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2076 | { |
63c0089f | 2077 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2078 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2079 | ||
28fc6740 | 2080 | /* Extract (always little endian). */ |
c86c27af | 2081 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2082 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2083 | } |
2084 | else | |
2085 | regcache_raw_read (regcache, regnum, buf); | |
2086 | } | |
2087 | ||
2088 | static void | |
2089 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2090 | int regnum, const gdb_byte *buf) |
28fc6740 | 2091 | { |
5716833c | 2092 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2093 | { |
63c0089f | 2094 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2095 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2096 | ||
28fc6740 AC |
2097 | /* Read ... */ |
2098 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2099 | /* ... Modify ... (always little endian). */ | |
f837910f | 2100 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2101 | /* ... Write. */ |
2102 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2103 | } | |
2104 | else | |
2105 | regcache_raw_write (regcache, regnum, buf); | |
2106 | } | |
ff2e87ac AC |
2107 | \f |
2108 | ||
ff2e87ac AC |
2109 | /* Return the register number of the register allocated by GCC after |
2110 | REGNUM, or -1 if there is no such register. */ | |
2111 | ||
2112 | static int | |
2113 | i386_next_regnum (int regnum) | |
2114 | { | |
2115 | /* GCC allocates the registers in the order: | |
2116 | ||
2117 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2118 | ||
2119 | Since storing a variable in %esp doesn't make any sense we return | |
2120 | -1 for %ebp and for %esp itself. */ | |
2121 | static int next_regnum[] = | |
2122 | { | |
2123 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2124 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2125 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2126 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2127 | -1, -1, /* Slots for %esp and %ebp. */ | |
2128 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2129 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2130 | }; | |
2131 | ||
de5b9bb9 | 2132 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2133 | return next_regnum[regnum]; |
28fc6740 | 2134 | |
ff2e87ac AC |
2135 | return -1; |
2136 | } | |
2137 | ||
2138 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2139 | needs any special handling. */ | |
d7a0d72c | 2140 | |
3a1e71e3 | 2141 | static int |
0abe36f5 | 2142 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2143 | { |
de5b9bb9 MK |
2144 | int len = TYPE_LENGTH (type); |
2145 | ||
ff2e87ac AC |
2146 | /* Values may be spread across multiple registers. Most debugging |
2147 | formats aren't expressive enough to specify the locations, so | |
2148 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2149 | have a length that is a multiple of the word size, since GCC |
2150 | doesn't seem to put any other types into registers. */ | |
2151 | if (len > 4 && len % 4 == 0) | |
2152 | { | |
2153 | int last_regnum = regnum; | |
2154 | ||
2155 | while (len > 4) | |
2156 | { | |
2157 | last_regnum = i386_next_regnum (last_regnum); | |
2158 | len -= 4; | |
2159 | } | |
2160 | ||
2161 | if (last_regnum != -1) | |
2162 | return 1; | |
2163 | } | |
ff2e87ac | 2164 | |
0abe36f5 | 2165 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2166 | } |
2167 | ||
ff2e87ac AC |
2168 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2169 | return its contents in TO. */ | |
ac27f131 | 2170 | |
3a1e71e3 | 2171 | static void |
ff2e87ac | 2172 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2173 | struct type *type, gdb_byte *to) |
ac27f131 | 2174 | { |
20a6ec49 | 2175 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2176 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2177 | |
ff2e87ac AC |
2178 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2179 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2180 | |
20a6ec49 | 2181 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2182 | { |
d532c08f MK |
2183 | i387_register_to_value (frame, regnum, type, to); |
2184 | return; | |
8d7f6b4a | 2185 | } |
ff2e87ac | 2186 | |
fd35795f | 2187 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2188 | |
2189 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2190 | |
de5b9bb9 MK |
2191 | while (len > 0) |
2192 | { | |
2193 | gdb_assert (regnum != -1); | |
20a6ec49 | 2194 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2195 | |
42835c2b | 2196 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2197 | regnum = i386_next_regnum (regnum); |
2198 | len -= 4; | |
42835c2b | 2199 | to += 4; |
de5b9bb9 | 2200 | } |
ac27f131 MK |
2201 | } |
2202 | ||
ff2e87ac AC |
2203 | /* Write the contents FROM of a value of type TYPE into register |
2204 | REGNUM in frame FRAME. */ | |
ac27f131 | 2205 | |
3a1e71e3 | 2206 | static void |
ff2e87ac | 2207 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2208 | struct type *type, const gdb_byte *from) |
ac27f131 | 2209 | { |
de5b9bb9 | 2210 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2211 | |
20a6ec49 | 2212 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2213 | { |
d532c08f MK |
2214 | i387_value_to_register (frame, regnum, type, from); |
2215 | return; | |
2216 | } | |
3d261580 | 2217 | |
fd35795f | 2218 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2219 | |
2220 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2221 | |
de5b9bb9 MK |
2222 | while (len > 0) |
2223 | { | |
2224 | gdb_assert (regnum != -1); | |
875f8d0e | 2225 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2226 | |
42835c2b | 2227 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2228 | regnum = i386_next_regnum (regnum); |
2229 | len -= 4; | |
42835c2b | 2230 | from += 4; |
de5b9bb9 | 2231 | } |
ac27f131 | 2232 | } |
ff2e87ac | 2233 | \f |
7fdafb5a MK |
2234 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2235 | in the general-purpose register set REGSET to register cache | |
2236 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2237 | |
20187ed5 | 2238 | void |
473f17b0 MK |
2239 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2240 | int regnum, const void *gregs, size_t len) | |
2241 | { | |
9ea75c57 | 2242 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2243 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2244 | int i; |
2245 | ||
2246 | gdb_assert (len == tdep->sizeof_gregset); | |
2247 | ||
2248 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2249 | { | |
2250 | if ((regnum == i || regnum == -1) | |
2251 | && tdep->gregset_reg_offset[i] != -1) | |
2252 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2253 | } | |
2254 | } | |
2255 | ||
7fdafb5a MK |
2256 | /* Collect register REGNUM from the register cache REGCACHE and store |
2257 | it in the buffer specified by GREGS and LEN as described by the | |
2258 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2259 | all registers in REGSET. */ | |
2260 | ||
2261 | void | |
2262 | i386_collect_gregset (const struct regset *regset, | |
2263 | const struct regcache *regcache, | |
2264 | int regnum, void *gregs, size_t len) | |
2265 | { | |
2266 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2267 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2268 | int i; |
2269 | ||
2270 | gdb_assert (len == tdep->sizeof_gregset); | |
2271 | ||
2272 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2273 | { | |
2274 | if ((regnum == i || regnum == -1) | |
2275 | && tdep->gregset_reg_offset[i] != -1) | |
2276 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2277 | } | |
2278 | } | |
2279 | ||
2280 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2281 | in the floating-point register set REGSET to register cache | |
2282 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2283 | |
2284 | static void | |
2285 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2286 | int regnum, const void *fpregs, size_t len) | |
2287 | { | |
9ea75c57 | 2288 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2289 | |
66a72d25 MK |
2290 | if (len == I387_SIZEOF_FXSAVE) |
2291 | { | |
2292 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2293 | return; | |
2294 | } | |
2295 | ||
473f17b0 MK |
2296 | gdb_assert (len == tdep->sizeof_fpregset); |
2297 | i387_supply_fsave (regcache, regnum, fpregs); | |
2298 | } | |
8446b36a | 2299 | |
2f305df1 MK |
2300 | /* Collect register REGNUM from the register cache REGCACHE and store |
2301 | it in the buffer specified by FPREGS and LEN as described by the | |
2302 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2303 | all registers in REGSET. */ | |
7fdafb5a MK |
2304 | |
2305 | static void | |
2306 | i386_collect_fpregset (const struct regset *regset, | |
2307 | const struct regcache *regcache, | |
2308 | int regnum, void *fpregs, size_t len) | |
2309 | { | |
2310 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2311 | ||
2312 | if (len == I387_SIZEOF_FXSAVE) | |
2313 | { | |
2314 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2315 | return; | |
2316 | } | |
2317 | ||
2318 | gdb_assert (len == tdep->sizeof_fpregset); | |
2319 | i387_collect_fsave (regcache, regnum, fpregs); | |
2320 | } | |
2321 | ||
8446b36a MK |
2322 | /* Return the appropriate register set for the core section identified |
2323 | by SECT_NAME and SECT_SIZE. */ | |
2324 | ||
2325 | const struct regset * | |
2326 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2327 | const char *sect_name, size_t sect_size) | |
2328 | { | |
2329 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2330 | ||
2331 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2332 | { | |
2333 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2334 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2335 | i386_collect_gregset); | |
8446b36a MK |
2336 | return tdep->gregset; |
2337 | } | |
2338 | ||
66a72d25 MK |
2339 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2340 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2341 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2342 | { |
2343 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2344 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2345 | i386_collect_fpregset); | |
8446b36a MK |
2346 | return tdep->fpregset; |
2347 | } | |
2348 | ||
2349 | return NULL; | |
2350 | } | |
473f17b0 | 2351 | \f |
fc338970 | 2352 | |
fc338970 | 2353 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2354 | |
2355 | CORE_ADDR | |
1cce71eb | 2356 | i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name) |
c906108c | 2357 | { |
fc338970 | 2358 | if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */ |
c906108c | 2359 | { |
c5aa993b | 2360 | unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4); |
c906108c | 2361 | struct minimal_symbol *indsym = |
fc338970 | 2362 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2363 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2364 | |
c5aa993b | 2365 | if (symname) |
c906108c | 2366 | { |
c5aa993b JM |
2367 | if (strncmp (symname, "__imp_", 6) == 0 |
2368 | || strncmp (symname, "_imp_", 5) == 0) | |
c906108c SS |
2369 | return name ? 1 : read_memory_unsigned_integer (indirect, 4); |
2370 | } | |
2371 | } | |
fc338970 | 2372 | return 0; /* Not a trampoline. */ |
c906108c | 2373 | } |
fc338970 MK |
2374 | \f |
2375 | ||
10458914 DJ |
2376 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2377 | routine. */ | |
8201327c MK |
2378 | |
2379 | static int | |
10458914 | 2380 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2381 | { |
10458914 | 2382 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2383 | char *name; |
2384 | ||
2385 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2386 | return (name && strcmp ("_sigtramp", name) == 0); |
2387 | } | |
2388 | \f | |
2389 | ||
fc338970 MK |
2390 | /* We have two flavours of disassembly. The machinery on this page |
2391 | deals with switching between those. */ | |
c906108c SS |
2392 | |
2393 | static int | |
a89aa300 | 2394 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2395 | { |
5e3397bb MK |
2396 | gdb_assert (disassembly_flavor == att_flavor |
2397 | || disassembly_flavor == intel_flavor); | |
2398 | ||
2399 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2400 | constified, cast to prevent a compiler warning. */ | |
2401 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2402 | |
2403 | return print_insn_i386 (pc, info); | |
7a292a7a | 2404 | } |
fc338970 | 2405 | \f |
3ce1502b | 2406 | |
8201327c MK |
2407 | /* There are a few i386 architecture variants that differ only |
2408 | slightly from the generic i386 target. For now, we don't give them | |
2409 | their own source file, but include them here. As a consequence, | |
2410 | they'll always be included. */ | |
3ce1502b | 2411 | |
8201327c | 2412 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2413 | |
10458914 DJ |
2414 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2415 | routine. */ | |
911bc6ee | 2416 | |
8201327c | 2417 | static int |
10458914 | 2418 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2419 | { |
10458914 | 2420 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2421 | char *name; |
2422 | ||
acd5c798 MK |
2423 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2424 | currently unknown. */ | |
911bc6ee | 2425 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2426 | return (name && (strcmp ("_sigreturn", name) == 0 |
2427 | || strcmp ("_sigacthandler", name) == 0 | |
2428 | || strcmp ("sigvechandler", name) == 0)); | |
2429 | } | |
d2a7c97a | 2430 | |
10458914 DJ |
2431 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2432 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2433 | |
3a1e71e3 | 2434 | static CORE_ADDR |
10458914 | 2435 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2436 | { |
63c0089f | 2437 | gdb_byte buf[4]; |
acd5c798 | 2438 | CORE_ADDR sp; |
3ce1502b | 2439 | |
10458914 | 2440 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 | 2441 | sp = extract_unsigned_integer (buf, 4); |
21d0e8a4 | 2442 | |
acd5c798 | 2443 | return read_memory_unsigned_integer (sp + 8, 4); |
8201327c MK |
2444 | } |
2445 | \f | |
3ce1502b | 2446 | |
8201327c | 2447 | /* Generic ELF. */ |
d2a7c97a | 2448 | |
8201327c MK |
2449 | void |
2450 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2451 | { | |
c4fc7f1b MK |
2452 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2453 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2454 | } |
3ce1502b | 2455 | |
8201327c | 2456 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2457 | |
8201327c MK |
2458 | void |
2459 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2460 | { | |
2461 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2462 | |
8201327c MK |
2463 | /* System V Release 4 uses ELF. */ |
2464 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2465 | |
dfe01d39 | 2466 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2467 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2468 | ||
911bc6ee | 2469 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2470 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2471 | tdep->sc_pc_offset = 36 + 14 * 4; |
2472 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2473 | |
8201327c | 2474 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2475 | } |
2476 | ||
8201327c | 2477 | /* DJGPP. */ |
3ce1502b | 2478 | |
3a1e71e3 | 2479 | static void |
8201327c | 2480 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2481 | { |
8201327c | 2482 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2483 | |
911bc6ee MK |
2484 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2485 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2486 | |
8201327c | 2487 | tdep->jb_pc_offset = 36; |
3ce1502b | 2488 | } |
8201327c | 2489 | \f |
2acceee2 | 2490 | |
38c968cf AC |
2491 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2492 | and "sse". */ | |
2493 | ||
2494 | static struct reggroup *i386_sse_reggroup; | |
2495 | static struct reggroup *i386_mmx_reggroup; | |
2496 | ||
2497 | static void | |
2498 | i386_init_reggroups (void) | |
2499 | { | |
2500 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2501 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2502 | } | |
2503 | ||
2504 | static void | |
2505 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2506 | { | |
2507 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2508 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2509 | reggroup_add (gdbarch, general_reggroup); | |
2510 | reggroup_add (gdbarch, float_reggroup); | |
2511 | reggroup_add (gdbarch, all_reggroup); | |
2512 | reggroup_add (gdbarch, save_reggroup); | |
2513 | reggroup_add (gdbarch, restore_reggroup); | |
2514 | reggroup_add (gdbarch, vector_reggroup); | |
2515 | reggroup_add (gdbarch, system_reggroup); | |
2516 | } | |
2517 | ||
2518 | int | |
2519 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2520 | struct reggroup *group) | |
2521 | { | |
5716833c MK |
2522 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2523 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2524 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2525 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2526 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2527 | |
38c968cf AC |
2528 | if (group == i386_mmx_reggroup) |
2529 | return mmx_regnum_p; | |
2530 | if (group == i386_sse_reggroup) | |
2531 | return sse_regnum_p; | |
2532 | if (group == vector_reggroup) | |
2533 | return (mmx_regnum_p || sse_regnum_p); | |
2534 | if (group == float_reggroup) | |
2535 | return fp_regnum_p; | |
2536 | if (group == general_reggroup) | |
2537 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2538 | |
38c968cf AC |
2539 | return default_register_reggroup_p (gdbarch, regnum, group); |
2540 | } | |
38c968cf | 2541 | \f |
acd5c798 | 2542 | |
f837910f MK |
2543 | /* Get the ARGIth function argument for the current function. */ |
2544 | ||
42c466d7 | 2545 | static CORE_ADDR |
143985b7 AF |
2546 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2547 | struct type *type) | |
2548 | { | |
f837910f MK |
2549 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
2550 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4); | |
143985b7 AF |
2551 | } |
2552 | ||
2553 | \f | |
3a1e71e3 | 2554 | static struct gdbarch * |
a62cc96e AC |
2555 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
2556 | { | |
cd3c07fc | 2557 | struct gdbarch_tdep *tdep; |
a62cc96e AC |
2558 | struct gdbarch *gdbarch; |
2559 | ||
4be87837 DJ |
2560 | /* If there is already a candidate, use it. */ |
2561 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2562 | if (arches != NULL) | |
2563 | return arches->gdbarch; | |
a62cc96e AC |
2564 | |
2565 | /* Allocate space for the new architecture. */ | |
794ac428 | 2566 | tdep = XCALLOC (1, struct gdbarch_tdep); |
a62cc96e AC |
2567 | gdbarch = gdbarch_alloc (&info, tdep); |
2568 | ||
473f17b0 MK |
2569 | /* General-purpose registers. */ |
2570 | tdep->gregset = NULL; | |
2571 | tdep->gregset_reg_offset = NULL; | |
2572 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
2573 | tdep->sizeof_gregset = 0; | |
2574 | ||
2575 | /* Floating-point registers. */ | |
2576 | tdep->fpregset = NULL; | |
2577 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
2578 | ||
5716833c | 2579 | /* The default settings include the FPU registers, the MMX registers |
fd35795f | 2580 | and the SSE registers. This can be overridden for a specific ABI |
5716833c MK |
2581 | by adjusting the members `st0_regnum', `mm0_regnum' and |
2582 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
2583 | will show up in the output of "info all-registers". Ideally we | |
2584 | should try to autodetect whether they are available, such that we | |
2585 | can prevent "info all-registers" from displaying registers that | |
2586 | aren't available. | |
2587 | ||
2588 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
2589 | [the SSE registers] always (even when they don't exist) or never | |
2590 | showing them to the user (even when they do exist), I prefer the | |
2591 | former over the latter. */ | |
2592 | ||
2593 | tdep->st0_regnum = I386_ST0_REGNUM; | |
2594 | ||
2595 | /* The MMX registers are implemented as pseudo-registers. Put off | |
fd35795f | 2596 | calculating the register number for %mm0 until we know the number |
5716833c MK |
2597 | of raw registers. */ |
2598 | tdep->mm0_regnum = 0; | |
2599 | ||
2600 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
49ed40de | 2601 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
d2a7c97a | 2602 | |
8201327c MK |
2603 | tdep->jb_pc_offset = -1; |
2604 | tdep->struct_return = pcc_struct_return; | |
8201327c MK |
2605 | tdep->sigtramp_start = 0; |
2606 | tdep->sigtramp_end = 0; | |
911bc6ee | 2607 | tdep->sigtramp_p = i386_sigtramp_p; |
21d0e8a4 | 2608 | tdep->sigcontext_addr = NULL; |
a3386186 | 2609 | tdep->sc_reg_offset = NULL; |
8201327c | 2610 | tdep->sc_pc_offset = -1; |
21d0e8a4 | 2611 | tdep->sc_sp_offset = -1; |
8201327c | 2612 | |
896fb97d MK |
2613 | /* The format used for `long double' on almost all i386 targets is |
2614 | the i387 extended floating-point format. In fact, of all targets | |
2615 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
2616 | on having a `long double' that's not `long' at all. */ | |
8da61cc4 | 2617 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); |
21d0e8a4 | 2618 | |
66da5fd8 | 2619 | /* Although the i387 extended floating-point has only 80 significant |
896fb97d MK |
2620 | bits, a `long double' actually takes up 96, probably to enforce |
2621 | alignment. */ | |
2622 | set_gdbarch_long_double_bit (gdbarch, 96); | |
2623 | ||
49ed40de KB |
2624 | /* The default ABI includes general-purpose registers, |
2625 | floating-point registers, and the SSE registers. */ | |
2626 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
acd5c798 MK |
2627 | set_gdbarch_register_name (gdbarch, i386_register_name); |
2628 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
21d0e8a4 | 2629 | |
acd5c798 MK |
2630 | /* Register numbers of various important registers. */ |
2631 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
2632 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
2633 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
2634 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
356a6b3e | 2635 | |
c4fc7f1b MK |
2636 | /* NOTE: kettenis/20040418: GCC does have two possible register |
2637 | numbering schemes on the i386: dbx and SVR4. These schemes | |
2638 | differ in how they number %ebp, %esp, %eflags, and the | |
fd35795f | 2639 | floating-point registers, and are implemented by the arrays |
c4fc7f1b MK |
2640 | dbx_register_map[] and svr4_dbx_register_map in |
2641 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
2642 | gcc/config/i386.c, which it designates as the "default" register | |
2643 | map used in 64bit mode. This last register numbering scheme is | |
d4dc1a91 | 2644 | implemented in dbx64_register_map, and is used for AMD64; see |
c4fc7f1b MK |
2645 | amd64-tdep.c. |
2646 | ||
2647 | Currently, each GCC i386 target always uses the same register | |
2648 | numbering scheme across all its supported debugging formats | |
2649 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
2650 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
2651 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
2652 | respective config header in a manner independent of the requested | |
2653 | output debugging format. | |
2654 | ||
2655 | This does not match the arrangement below, which presumes that | |
2656 | the SDB and stabs numbering schemes differ from the DWARF and | |
2657 | DWARF 2 ones. The reason for this arrangement is that it is | |
2658 | likely to get the numbering scheme for the target's | |
2659 | default/native debug format right. For targets where GCC is the | |
2660 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
2661 | targets where the native toolchain uses a different numbering | |
2662 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
d4dc1a91 BF |
2663 | the defaults below will have to be overridden, like |
2664 | i386_elf_init_abi() does. */ | |
c4fc7f1b MK |
2665 | |
2666 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
2667 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2668 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2669 | ||
ba2b1c56 | 2670 | /* Use the SVR4 register numbering scheme for DWARF 2. */ |
c4fc7f1b | 2671 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
356a6b3e | 2672 | |
055d23b8 | 2673 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to |
356a6b3e MK |
2674 | be in use on any of the supported i386 targets. */ |
2675 | ||
61113f8b MK |
2676 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
2677 | ||
8201327c | 2678 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
96297dab | 2679 | |
a62cc96e | 2680 | /* Call dummy code. */ |
acd5c798 | 2681 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
a62cc96e | 2682 | |
ff2e87ac AC |
2683 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
2684 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
2685 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
b6197528 | 2686 | |
c5e656c1 | 2687 | set_gdbarch_return_value (gdbarch, i386_return_value); |
8201327c | 2688 | |
93924b6b MK |
2689 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
2690 | ||
2691 | /* Stack grows downward. */ | |
2692 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2693 | ||
2694 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
2695 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
237fc4c9 | 2696 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); |
42fdc8df | 2697 | |
42fdc8df | 2698 | set_gdbarch_frame_args_skip (gdbarch, 8); |
8201327c | 2699 | |
28fc6740 | 2700 | /* Wire in the MMX registers. */ |
0f751ff2 | 2701 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); |
28fc6740 AC |
2702 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
2703 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
2704 | ||
5e3397bb MK |
2705 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
2706 | ||
10458914 | 2707 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); |
acd5c798 MK |
2708 | |
2709 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
2710 | ||
38c968cf AC |
2711 | /* Add the i386 register groups. */ |
2712 | i386_add_reggroups (gdbarch); | |
2713 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
2714 | ||
143985b7 AF |
2715 | /* Helper for function argument information. */ |
2716 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
2717 | ||
6405b0a6 | 2718 | /* Hook in the DWARF CFI frame unwinder. */ |
10458914 | 2719 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 2720 | |
acd5c798 | 2721 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 2722 | |
3ce1502b | 2723 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2724 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 2725 | |
10458914 DJ |
2726 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
2727 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 2728 | |
8446b36a MK |
2729 | /* If we have a register mapping, enable the generic core file |
2730 | support, unless it has already been enabled. */ | |
2731 | if (tdep->gregset_reg_offset | |
2732 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
2733 | set_gdbarch_regset_from_core_section (gdbarch, | |
2734 | i386_regset_from_core_section); | |
2735 | ||
5716833c MK |
2736 | /* Unless support for MMX has been disabled, make %mm0 the first |
2737 | pseudo-register. */ | |
2738 | if (tdep->mm0_regnum == 0) | |
2739 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
2740 | ||
a62cc96e AC |
2741 | return gdbarch; |
2742 | } | |
2743 | ||
8201327c MK |
2744 | static enum gdb_osabi |
2745 | i386_coff_osabi_sniffer (bfd *abfd) | |
2746 | { | |
762c5349 MK |
2747 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
2748 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
2749 | return GDB_OSABI_GO32; |
2750 | ||
2751 | return GDB_OSABI_UNKNOWN; | |
2752 | } | |
8201327c MK |
2753 | \f |
2754 | ||
28e9e0f0 MK |
2755 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2756 | void _initialize_i386_tdep (void); | |
2757 | ||
c906108c | 2758 | void |
fba45db2 | 2759 | _initialize_i386_tdep (void) |
c906108c | 2760 | { |
a62cc96e AC |
2761 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
2762 | ||
fc338970 | 2763 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
2764 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
2765 | &disassembly_flavor, _("\ | |
2766 | Set the disassembly flavor."), _("\ | |
2767 | Show the disassembly flavor."), _("\ | |
2768 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
2769 | NULL, | |
2770 | NULL, /* FIXME: i18n: */ | |
2771 | &setlist, &showlist); | |
8201327c MK |
2772 | |
2773 | /* Add the variable that controls the convention for returning | |
2774 | structs. */ | |
7ab04401 AC |
2775 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
2776 | &struct_convention, _("\ | |
2777 | Set the convention for returning small structs."), _("\ | |
2778 | Show the convention for returning small structs."), _("\ | |
2779 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
2780 | is \"default\"."), | |
2781 | NULL, | |
2782 | NULL, /* FIXME: i18n: */ | |
2783 | &setlist, &showlist); | |
8201327c MK |
2784 | |
2785 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
2786 | i386_coff_osabi_sniffer); | |
8201327c | 2787 | |
05816f70 | 2788 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 2789 | i386_svr4_init_abi); |
05816f70 | 2790 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 2791 | i386_go32_init_abi); |
38c968cf | 2792 | |
5ae96ec1 | 2793 | /* Initialize the i386-specific register groups & types. */ |
38c968cf | 2794 | i386_init_reggroups (); |
5ae96ec1 | 2795 | i386_init_types(); |
c906108c | 2796 | } |