Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
c8d5aac9 | 47 | #include "remote.h" |
acd5c798 | 48 | |
3d261580 | 49 | #include "gdb_assert.h" |
acd5c798 | 50 | #include "gdb_string.h" |
3d261580 | 51 | |
d2a7c97a | 52 | #include "i386-tdep.h" |
61113f8b | 53 | #include "i387-tdep.h" |
c131fcee | 54 | #include "i386-xstate.h" |
d2a7c97a | 55 | |
7ad10968 HZ |
56 | #include "record.h" |
57 | #include <stdint.h> | |
58 | ||
90884b2b | 59 | #include "features/i386/i386.c" |
c131fcee | 60 | #include "features/i386/i386-avx.c" |
3a13a53b | 61 | #include "features/i386/i386-mmx.c" |
90884b2b | 62 | |
c4fc7f1b | 63 | /* Register names. */ |
c40e1eab | 64 | |
90884b2b | 65 | static const char *i386_register_names[] = |
fc633446 MK |
66 | { |
67 | "eax", "ecx", "edx", "ebx", | |
68 | "esp", "ebp", "esi", "edi", | |
69 | "eip", "eflags", "cs", "ss", | |
70 | "ds", "es", "fs", "gs", | |
71 | "st0", "st1", "st2", "st3", | |
72 | "st4", "st5", "st6", "st7", | |
73 | "fctrl", "fstat", "ftag", "fiseg", | |
74 | "fioff", "foseg", "fooff", "fop", | |
75 | "xmm0", "xmm1", "xmm2", "xmm3", | |
76 | "xmm4", "xmm5", "xmm6", "xmm7", | |
77 | "mxcsr" | |
78 | }; | |
79 | ||
c131fcee L |
80 | static const char *i386_ymm_names[] = |
81 | { | |
82 | "ymm0", "ymm1", "ymm2", "ymm3", | |
83 | "ymm4", "ymm5", "ymm6", "ymm7", | |
84 | }; | |
85 | ||
86 | static const char *i386_ymmh_names[] = | |
87 | { | |
88 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
89 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
90 | }; | |
91 | ||
c4fc7f1b | 92 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 93 | |
90884b2b | 94 | static const char *i386_mmx_names[] = |
28fc6740 AC |
95 | { |
96 | "mm0", "mm1", "mm2", "mm3", | |
97 | "mm4", "mm5", "mm6", "mm7" | |
98 | }; | |
c40e1eab | 99 | |
1ba53b71 L |
100 | /* Register names for byte pseudo-registers. */ |
101 | ||
102 | static const char *i386_byte_names[] = | |
103 | { | |
104 | "al", "cl", "dl", "bl", | |
105 | "ah", "ch", "dh", "bh" | |
106 | }; | |
107 | ||
108 | /* Register names for word pseudo-registers. */ | |
109 | ||
110 | static const char *i386_word_names[] = | |
111 | { | |
112 | "ax", "cx", "dx", "bx", | |
9cad29ac | 113 | "", "bp", "si", "di" |
1ba53b71 L |
114 | }; |
115 | ||
116 | /* MMX register? */ | |
c40e1eab | 117 | |
28fc6740 | 118 | static int |
5716833c | 119 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 120 | { |
1ba53b71 L |
121 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
122 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
123 | |
124 | if (mm0_regnum < 0) | |
125 | return 0; | |
126 | ||
1ba53b71 L |
127 | regnum -= mm0_regnum; |
128 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
129 | } | |
130 | ||
131 | /* Byte register? */ | |
132 | ||
133 | int | |
134 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
135 | { | |
136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
137 | ||
138 | regnum -= tdep->al_regnum; | |
139 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
140 | } | |
141 | ||
142 | /* Word register? */ | |
143 | ||
144 | int | |
145 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
146 | { | |
147 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
148 | ||
149 | regnum -= tdep->ax_regnum; | |
150 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
151 | } | |
152 | ||
153 | /* Dword register? */ | |
154 | ||
155 | int | |
156 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
157 | { | |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
159 | int eax_regnum = tdep->eax_regnum; | |
160 | ||
161 | if (eax_regnum < 0) | |
162 | return 0; | |
163 | ||
164 | regnum -= eax_regnum; | |
165 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
166 | } |
167 | ||
c131fcee L |
168 | int |
169 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
170 | { | |
171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
172 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
173 | ||
174 | if (ymm0h_regnum < 0) | |
175 | return 0; | |
176 | ||
177 | regnum -= ymm0h_regnum; | |
178 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
179 | } | |
180 | ||
181 | /* AVX register? */ | |
182 | ||
183 | int | |
184 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
185 | { | |
186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
187 | int ymm0_regnum = tdep->ymm0_regnum; | |
188 | ||
189 | if (ymm0_regnum < 0) | |
190 | return 0; | |
191 | ||
192 | regnum -= ymm0_regnum; | |
193 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
194 | } | |
195 | ||
5716833c | 196 | /* SSE register? */ |
23a34459 | 197 | |
c131fcee L |
198 | int |
199 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 200 | { |
5716833c | 201 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 202 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 203 | |
c131fcee | 204 | if (num_xmm_regs == 0) |
5716833c MK |
205 | return 0; |
206 | ||
c131fcee L |
207 | regnum -= I387_XMM0_REGNUM (tdep); |
208 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
209 | } |
210 | ||
5716833c MK |
211 | static int |
212 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 213 | { |
5716833c MK |
214 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
215 | ||
20a6ec49 | 216 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
217 | return 0; |
218 | ||
20a6ec49 | 219 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
220 | } |
221 | ||
5716833c | 222 | /* FP register? */ |
23a34459 AC |
223 | |
224 | int | |
20a6ec49 | 225 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 226 | { |
20a6ec49 MD |
227 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
228 | ||
229 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
230 | return 0; |
231 | ||
20a6ec49 MD |
232 | return (I387_ST0_REGNUM (tdep) <= regnum |
233 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
234 | } |
235 | ||
236 | int | |
20a6ec49 | 237 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 238 | { |
20a6ec49 MD |
239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
240 | ||
241 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
242 | return 0; |
243 | ||
20a6ec49 MD |
244 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
245 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
246 | } |
247 | ||
c131fcee L |
248 | /* Return the name of register REGNUM, or the empty string if it is |
249 | an anonymous register. */ | |
250 | ||
251 | static const char * | |
252 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
253 | { | |
254 | /* Hide the upper YMM registers. */ | |
255 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
256 | return ""; | |
257 | ||
258 | return tdesc_register_name (gdbarch, regnum); | |
259 | } | |
260 | ||
30b0e2d8 | 261 | /* Return the name of register REGNUM. */ |
fc633446 | 262 | |
1ba53b71 | 263 | const char * |
90884b2b | 264 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 265 | { |
1ba53b71 L |
266 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
267 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
268 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
269 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
270 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
271 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
272 | return i386_byte_names[regnum - tdep->al_regnum]; | |
273 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
274 | return i386_word_names[regnum - tdep->ax_regnum]; | |
275 | ||
276 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
277 | } |
278 | ||
c4fc7f1b | 279 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
280 | number used by GDB. */ |
281 | ||
8201327c | 282 | static int |
d3f73121 | 283 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 284 | { |
20a6ec49 MD |
285 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
286 | ||
c4fc7f1b MK |
287 | /* This implements what GCC calls the "default" register map |
288 | (dbx_register_map[]). */ | |
289 | ||
85540d8c MK |
290 | if (reg >= 0 && reg <= 7) |
291 | { | |
9872ad24 JB |
292 | /* General-purpose registers. The debug info calls %ebp |
293 | register 4, and %esp register 5. */ | |
294 | if (reg == 4) | |
295 | return 5; | |
296 | else if (reg == 5) | |
297 | return 4; | |
298 | else return reg; | |
85540d8c MK |
299 | } |
300 | else if (reg >= 12 && reg <= 19) | |
301 | { | |
302 | /* Floating-point registers. */ | |
20a6ec49 | 303 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
304 | } |
305 | else if (reg >= 21 && reg <= 28) | |
306 | { | |
307 | /* SSE registers. */ | |
c131fcee L |
308 | int ymm0_regnum = tdep->ymm0_regnum; |
309 | ||
310 | if (ymm0_regnum >= 0 | |
311 | && i386_xmm_regnum_p (gdbarch, reg)) | |
312 | return reg - 21 + ymm0_regnum; | |
313 | else | |
314 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
315 | } |
316 | else if (reg >= 29 && reg <= 36) | |
317 | { | |
318 | /* MMX registers. */ | |
20a6ec49 | 319 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
320 | } |
321 | ||
322 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 323 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
324 | } |
325 | ||
c4fc7f1b MK |
326 | /* Convert SVR4 register number REG to the appropriate register number |
327 | used by GDB. */ | |
85540d8c | 328 | |
8201327c | 329 | static int |
d3f73121 | 330 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 331 | { |
20a6ec49 MD |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
333 | ||
c4fc7f1b MK |
334 | /* This implements the GCC register map that tries to be compatible |
335 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
336 | ||
337 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
338 | numbers the floating point registers differently. */ |
339 | if (reg >= 0 && reg <= 9) | |
340 | { | |
acd5c798 | 341 | /* General-purpose registers. */ |
85540d8c MK |
342 | return reg; |
343 | } | |
344 | else if (reg >= 11 && reg <= 18) | |
345 | { | |
346 | /* Floating-point registers. */ | |
20a6ec49 | 347 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 348 | } |
c6f4c129 | 349 | else if (reg >= 21 && reg <= 36) |
85540d8c | 350 | { |
c4fc7f1b | 351 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 352 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
353 | } |
354 | ||
c6f4c129 JB |
355 | switch (reg) |
356 | { | |
20a6ec49 MD |
357 | case 37: return I387_FCTRL_REGNUM (tdep); |
358 | case 38: return I387_FSTAT_REGNUM (tdep); | |
359 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
360 | case 40: return I386_ES_REGNUM; |
361 | case 41: return I386_CS_REGNUM; | |
362 | case 42: return I386_SS_REGNUM; | |
363 | case 43: return I386_DS_REGNUM; | |
364 | case 44: return I386_FS_REGNUM; | |
365 | case 45: return I386_GS_REGNUM; | |
366 | } | |
367 | ||
85540d8c | 368 | /* This will hopefully provoke a warning. */ |
d3f73121 | 369 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 370 | } |
5716833c | 371 | |
fc338970 | 372 | \f |
917317f4 | 373 | |
fc338970 MK |
374 | /* This is the variable that is set with "set disassembly-flavor", and |
375 | its legitimate values. */ | |
53904c9e AC |
376 | static const char att_flavor[] = "att"; |
377 | static const char intel_flavor[] = "intel"; | |
378 | static const char *valid_flavors[] = | |
c5aa993b | 379 | { |
c906108c SS |
380 | att_flavor, |
381 | intel_flavor, | |
382 | NULL | |
383 | }; | |
53904c9e | 384 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 385 | \f |
c906108c | 386 | |
acd5c798 MK |
387 | /* Use the program counter to determine the contents and size of a |
388 | breakpoint instruction. Return a pointer to a string of bytes that | |
389 | encode a breakpoint instruction, store the length of the string in | |
390 | *LEN and optionally adjust *PC to point to the correct memory | |
391 | location for inserting the breakpoint. | |
c906108c | 392 | |
acd5c798 MK |
393 | On the i386 we have a single breakpoint that fits in a single byte |
394 | and can be inserted anywhere. | |
c906108c | 395 | |
acd5c798 | 396 | This function is 64-bit safe. */ |
63c0089f MK |
397 | |
398 | static const gdb_byte * | |
67d57894 | 399 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 400 | { |
63c0089f MK |
401 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
402 | ||
acd5c798 MK |
403 | *len = sizeof (break_insn); |
404 | return break_insn; | |
c906108c | 405 | } |
237fc4c9 PA |
406 | \f |
407 | /* Displaced instruction handling. */ | |
408 | ||
1903f0e6 DE |
409 | /* Skip the legacy instruction prefixes in INSN. |
410 | Not all prefixes are valid for any particular insn | |
411 | but we needn't care, the insn will fault if it's invalid. | |
412 | The result is a pointer to the first opcode byte, | |
413 | or NULL if we run off the end of the buffer. */ | |
414 | ||
415 | static gdb_byte * | |
416 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
417 | { | |
418 | gdb_byte *end = insn + max_len; | |
419 | ||
420 | while (insn < end) | |
421 | { | |
422 | switch (*insn) | |
423 | { | |
424 | case DATA_PREFIX_OPCODE: | |
425 | case ADDR_PREFIX_OPCODE: | |
426 | case CS_PREFIX_OPCODE: | |
427 | case DS_PREFIX_OPCODE: | |
428 | case ES_PREFIX_OPCODE: | |
429 | case FS_PREFIX_OPCODE: | |
430 | case GS_PREFIX_OPCODE: | |
431 | case SS_PREFIX_OPCODE: | |
432 | case LOCK_PREFIX_OPCODE: | |
433 | case REPE_PREFIX_OPCODE: | |
434 | case REPNE_PREFIX_OPCODE: | |
435 | ++insn; | |
436 | continue; | |
437 | default: | |
438 | return insn; | |
439 | } | |
440 | } | |
441 | ||
442 | return NULL; | |
443 | } | |
237fc4c9 PA |
444 | |
445 | static int | |
1903f0e6 | 446 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
447 | { |
448 | /* jmp far (absolute address in operand) */ | |
449 | if (insn[0] == 0xea) | |
450 | return 1; | |
451 | ||
452 | if (insn[0] == 0xff) | |
453 | { | |
454 | /* jump near, absolute indirect (/4) */ | |
455 | if ((insn[1] & 0x38) == 0x20) | |
456 | return 1; | |
457 | ||
458 | /* jump far, absolute indirect (/5) */ | |
459 | if ((insn[1] & 0x38) == 0x28) | |
460 | return 1; | |
461 | } | |
462 | ||
463 | return 0; | |
464 | } | |
465 | ||
466 | static int | |
1903f0e6 | 467 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
468 | { |
469 | /* call far, absolute */ | |
470 | if (insn[0] == 0x9a) | |
471 | return 1; | |
472 | ||
473 | if (insn[0] == 0xff) | |
474 | { | |
475 | /* Call near, absolute indirect (/2) */ | |
476 | if ((insn[1] & 0x38) == 0x10) | |
477 | return 1; | |
478 | ||
479 | /* Call far, absolute indirect (/3) */ | |
480 | if ((insn[1] & 0x38) == 0x18) | |
481 | return 1; | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
487 | static int | |
1903f0e6 | 488 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
489 | { |
490 | switch (insn[0]) | |
491 | { | |
492 | case 0xc2: /* ret near, pop N bytes */ | |
493 | case 0xc3: /* ret near */ | |
494 | case 0xca: /* ret far, pop N bytes */ | |
495 | case 0xcb: /* ret far */ | |
496 | case 0xcf: /* iret */ | |
497 | return 1; | |
498 | ||
499 | default: | |
500 | return 0; | |
501 | } | |
502 | } | |
503 | ||
504 | static int | |
1903f0e6 | 505 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
506 | { |
507 | if (i386_absolute_call_p (insn)) | |
508 | return 1; | |
509 | ||
510 | /* call near, relative */ | |
511 | if (insn[0] == 0xe8) | |
512 | return 1; | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
237fc4c9 PA |
517 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
518 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 519 | |
237fc4c9 | 520 | static int |
1903f0e6 | 521 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
522 | { |
523 | if (insn[0] == 0xcd) | |
524 | { | |
525 | *lengthp = 2; | |
526 | return 1; | |
527 | } | |
528 | ||
529 | return 0; | |
530 | } | |
531 | ||
532 | /* Fix up the state of registers and memory after having single-stepped | |
533 | a displaced instruction. */ | |
1903f0e6 | 534 | |
237fc4c9 PA |
535 | void |
536 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
537 | struct displaced_step_closure *closure, | |
538 | CORE_ADDR from, CORE_ADDR to, | |
539 | struct regcache *regs) | |
540 | { | |
e17a4113 UW |
541 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
542 | ||
237fc4c9 PA |
543 | /* The offset we applied to the instruction's address. |
544 | This could well be negative (when viewed as a signed 32-bit | |
545 | value), but ULONGEST won't reflect that, so take care when | |
546 | applying it. */ | |
547 | ULONGEST insn_offset = to - from; | |
548 | ||
549 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
550 | copy of the instruction. */ | |
551 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
552 | /* The start of the insn, needed in case we see some prefixes. */ |
553 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
554 | |
555 | if (debug_displaced) | |
556 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 557 | "displaced: fixup (%s, %s), " |
237fc4c9 | 558 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
559 | paddress (gdbarch, from), paddress (gdbarch, to), |
560 | insn[0], insn[1]); | |
237fc4c9 PA |
561 | |
562 | /* The list of issues to contend with here is taken from | |
563 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
564 | Yay for Free Software! */ | |
565 | ||
566 | /* Relocate the %eip, if necessary. */ | |
567 | ||
1903f0e6 DE |
568 | /* The instruction recognizers we use assume any leading prefixes |
569 | have been skipped. */ | |
570 | { | |
571 | /* This is the size of the buffer in closure. */ | |
572 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
573 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
574 | /* If there are too many prefixes, just ignore the insn. | |
575 | It will fault when run. */ | |
576 | if (opcode != NULL) | |
577 | insn = opcode; | |
578 | } | |
579 | ||
237fc4c9 PA |
580 | /* Except in the case of absolute or indirect jump or call |
581 | instructions, or a return instruction, the new eip is relative to | |
582 | the displaced instruction; make it relative. Well, signal | |
583 | handler returns don't need relocation either, but we use the | |
584 | value of %eip to recognize those; see below. */ | |
585 | if (! i386_absolute_jmp_p (insn) | |
586 | && ! i386_absolute_call_p (insn) | |
587 | && ! i386_ret_p (insn)) | |
588 | { | |
589 | ULONGEST orig_eip; | |
590 | ULONGEST insn_len; | |
591 | ||
592 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
593 | ||
594 | /* A signal trampoline system call changes the %eip, resuming | |
595 | execution of the main program after the signal handler has | |
596 | returned. That makes them like 'return' instructions; we | |
597 | shouldn't relocate %eip. | |
598 | ||
599 | But most system calls don't, and we do need to relocate %eip. | |
600 | ||
601 | Our heuristic for distinguishing these cases: if stepping | |
602 | over the system call instruction left control directly after | |
603 | the instruction, the we relocate --- control almost certainly | |
604 | doesn't belong in the displaced copy. Otherwise, we assume | |
605 | the instruction has put control where it belongs, and leave | |
606 | it unrelocated. Goodness help us if there are PC-relative | |
607 | system calls. */ | |
608 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 609 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
610 | { |
611 | if (debug_displaced) | |
612 | fprintf_unfiltered (gdb_stdlog, | |
613 | "displaced: syscall changed %%eip; " | |
614 | "not relocating\n"); | |
615 | } | |
616 | else | |
617 | { | |
618 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
619 | ||
1903f0e6 DE |
620 | /* If we just stepped over a breakpoint insn, we don't backup |
621 | the pc on purpose; this is to match behaviour without | |
622 | stepping. */ | |
237fc4c9 PA |
623 | |
624 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
625 | ||
626 | if (debug_displaced) | |
627 | fprintf_unfiltered (gdb_stdlog, | |
628 | "displaced: " | |
5af949e3 UW |
629 | "relocated %%eip from %s to %s\n", |
630 | paddress (gdbarch, orig_eip), | |
631 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
632 | } |
633 | } | |
634 | ||
635 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
636 | pushed value, and should be cleared. We'll leave this for later, | |
637 | since GDB already messes up the TF flag when stepping over a | |
638 | pushfl. */ | |
639 | ||
640 | /* If the instruction was a call, the return address now atop the | |
641 | stack is the address following the copied instruction. We need | |
642 | to make it the address following the original instruction. */ | |
643 | if (i386_call_p (insn)) | |
644 | { | |
645 | ULONGEST esp; | |
646 | ULONGEST retaddr; | |
647 | const ULONGEST retaddr_len = 4; | |
648 | ||
649 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 650 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 651 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 652 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
653 | |
654 | if (debug_displaced) | |
655 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
656 | "displaced: relocated return addr at %s to %s\n", |
657 | paddress (gdbarch, esp), | |
658 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
659 | } |
660 | } | |
dde08ee1 PA |
661 | |
662 | static void | |
663 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
664 | { | |
665 | target_write_memory (*to, buf, len); | |
666 | *to += len; | |
667 | } | |
668 | ||
669 | static void | |
670 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
671 | CORE_ADDR *to, CORE_ADDR oldloc) | |
672 | { | |
673 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
674 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
675 | int offset = 0, rel32, newrel; | |
676 | int insn_length; | |
677 | gdb_byte *insn = buf; | |
678 | ||
679 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
680 | ||
681 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
682 | I386_MAX_INSN_LEN, oldloc); | |
683 | ||
684 | /* Get past the prefixes. */ | |
685 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
686 | ||
687 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
688 | the address pushed being the location where the original call in | |
689 | the user program would return to. */ | |
690 | if (insn[0] == 0xe8) | |
691 | { | |
692 | gdb_byte push_buf[16]; | |
693 | unsigned int ret_addr; | |
694 | ||
695 | /* Where "ret" in the original code will return to. */ | |
696 | ret_addr = oldloc + insn_length; | |
697 | push_buf[0] = 0x68; /* pushq $... */ | |
698 | memcpy (&push_buf[1], &ret_addr, 4); | |
699 | /* Push the push. */ | |
700 | append_insns (to, 5, push_buf); | |
701 | ||
702 | /* Convert the relative call to a relative jump. */ | |
703 | insn[0] = 0xe9; | |
704 | ||
705 | /* Adjust the destination offset. */ | |
706 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
707 | newrel = (oldloc - *to) + rel32; | |
708 | store_signed_integer (insn + 1, 4, newrel, byte_order); | |
709 | ||
710 | /* Write the adjusted jump into its displaced location. */ | |
711 | append_insns (to, 5, insn); | |
712 | return; | |
713 | } | |
714 | ||
715 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
716 | handled above. */ | |
717 | if (insn[0] == 0xe9) | |
718 | offset = 1; | |
719 | /* Adjust conditional jumps. */ | |
720 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
721 | offset = 2; | |
722 | ||
723 | if (offset) | |
724 | { | |
725 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
726 | newrel = (oldloc - *to) + rel32; | |
727 | store_signed_integer (insn + offset, 4, newrel, byte_order); | |
728 | if (debug_displaced) | |
729 | fprintf_unfiltered (gdb_stdlog, | |
730 | "Adjusted insn rel32=0x%s at 0x%s to" | |
731 | " rel32=0x%s at 0x%s\n", | |
732 | hex_string (rel32), paddress (gdbarch, oldloc), | |
733 | hex_string (newrel), paddress (gdbarch, *to)); | |
734 | } | |
735 | ||
736 | /* Write the adjusted instructions into their displaced | |
737 | location. */ | |
738 | append_insns (to, insn_length, buf); | |
739 | } | |
740 | ||
fc338970 | 741 | \f |
acd5c798 MK |
742 | #ifdef I386_REGNO_TO_SYMMETRY |
743 | #error "The Sequent Symmetry is no longer supported." | |
744 | #endif | |
c906108c | 745 | |
acd5c798 MK |
746 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
747 | and %esp "belong" to the calling function. Therefore these | |
748 | registers should be saved if they're going to be modified. */ | |
c906108c | 749 | |
acd5c798 MK |
750 | /* The maximum number of saved registers. This should include all |
751 | registers mentioned above, and %eip. */ | |
a3386186 | 752 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
753 | |
754 | struct i386_frame_cache | |
c906108c | 755 | { |
acd5c798 MK |
756 | /* Base address. */ |
757 | CORE_ADDR base; | |
772562f8 | 758 | LONGEST sp_offset; |
acd5c798 MK |
759 | CORE_ADDR pc; |
760 | ||
fd13a04a AC |
761 | /* Saved registers. */ |
762 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 763 | CORE_ADDR saved_sp; |
e0c62198 | 764 | int saved_sp_reg; |
acd5c798 MK |
765 | int pc_in_eax; |
766 | ||
767 | /* Stack space reserved for local variables. */ | |
768 | long locals; | |
769 | }; | |
770 | ||
771 | /* Allocate and initialize a frame cache. */ | |
772 | ||
773 | static struct i386_frame_cache * | |
fd13a04a | 774 | i386_alloc_frame_cache (void) |
acd5c798 MK |
775 | { |
776 | struct i386_frame_cache *cache; | |
777 | int i; | |
778 | ||
779 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
780 | ||
781 | /* Base address. */ | |
782 | cache->base = 0; | |
783 | cache->sp_offset = -4; | |
784 | cache->pc = 0; | |
785 | ||
fd13a04a AC |
786 | /* Saved registers. We initialize these to -1 since zero is a valid |
787 | offset (that's where %ebp is supposed to be stored). */ | |
788 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
789 | cache->saved_regs[i] = -1; | |
acd5c798 | 790 | cache->saved_sp = 0; |
e0c62198 | 791 | cache->saved_sp_reg = -1; |
acd5c798 MK |
792 | cache->pc_in_eax = 0; |
793 | ||
794 | /* Frameless until proven otherwise. */ | |
795 | cache->locals = -1; | |
796 | ||
797 | return cache; | |
798 | } | |
c906108c | 799 | |
acd5c798 MK |
800 | /* If the instruction at PC is a jump, return the address of its |
801 | target. Otherwise, return PC. */ | |
c906108c | 802 | |
acd5c798 | 803 | static CORE_ADDR |
e17a4113 | 804 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 805 | { |
e17a4113 | 806 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 807 | gdb_byte op; |
acd5c798 MK |
808 | long delta = 0; |
809 | int data16 = 0; | |
c906108c | 810 | |
8defab1a | 811 | target_read_memory (pc, &op, 1); |
acd5c798 | 812 | if (op == 0x66) |
c906108c | 813 | { |
c906108c | 814 | data16 = 1; |
e17a4113 | 815 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
816 | } |
817 | ||
acd5c798 | 818 | switch (op) |
c906108c SS |
819 | { |
820 | case 0xe9: | |
fc338970 | 821 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
822 | if (data16) |
823 | { | |
e17a4113 | 824 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 825 | |
fc338970 MK |
826 | /* Include the size of the jmp instruction (including the |
827 | 0x66 prefix). */ | |
acd5c798 | 828 | delta += 4; |
c906108c SS |
829 | } |
830 | else | |
831 | { | |
e17a4113 | 832 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 833 | |
acd5c798 MK |
834 | /* Include the size of the jmp instruction. */ |
835 | delta += 5; | |
c906108c SS |
836 | } |
837 | break; | |
838 | case 0xeb: | |
fc338970 | 839 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 840 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 841 | |
acd5c798 | 842 | delta += data16 + 2; |
c906108c SS |
843 | break; |
844 | } | |
c906108c | 845 | |
acd5c798 MK |
846 | return pc + delta; |
847 | } | |
fc338970 | 848 | |
acd5c798 MK |
849 | /* Check whether PC points at a prologue for a function returning a |
850 | structure or union. If so, it updates CACHE and returns the | |
851 | address of the first instruction after the code sequence that | |
852 | removes the "hidden" argument from the stack or CURRENT_PC, | |
853 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 854 | |
acd5c798 MK |
855 | static CORE_ADDR |
856 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
857 | struct i386_frame_cache *cache) | |
c906108c | 858 | { |
acd5c798 MK |
859 | /* Functions that return a structure or union start with: |
860 | ||
861 | popl %eax 0x58 | |
862 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
863 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
864 | ||
865 | (the System V compiler puts out the second `xchg' instruction, | |
866 | and the assembler doesn't try to optimize it, so the 'sib' form | |
867 | gets generated). This sequence is used to get the address of the | |
868 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
869 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
870 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
871 | gdb_byte buf[4]; | |
872 | gdb_byte op; | |
c906108c | 873 | |
acd5c798 MK |
874 | if (current_pc <= pc) |
875 | return pc; | |
876 | ||
8defab1a | 877 | target_read_memory (pc, &op, 1); |
c906108c | 878 | |
acd5c798 MK |
879 | if (op != 0x58) /* popl %eax */ |
880 | return pc; | |
c906108c | 881 | |
8defab1a | 882 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
883 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
884 | return pc; | |
c906108c | 885 | |
acd5c798 | 886 | if (current_pc == pc) |
c906108c | 887 | { |
acd5c798 MK |
888 | cache->sp_offset += 4; |
889 | return current_pc; | |
c906108c SS |
890 | } |
891 | ||
acd5c798 | 892 | if (current_pc == pc + 1) |
c906108c | 893 | { |
acd5c798 MK |
894 | cache->pc_in_eax = 1; |
895 | return current_pc; | |
896 | } | |
897 | ||
898 | if (buf[1] == proto1[1]) | |
899 | return pc + 4; | |
900 | else | |
901 | return pc + 5; | |
902 | } | |
903 | ||
904 | static CORE_ADDR | |
905 | i386_skip_probe (CORE_ADDR pc) | |
906 | { | |
907 | /* A function may start with | |
fc338970 | 908 | |
acd5c798 MK |
909 | pushl constant |
910 | call _probe | |
911 | addl $4, %esp | |
fc338970 | 912 | |
acd5c798 MK |
913 | followed by |
914 | ||
915 | pushl %ebp | |
fc338970 | 916 | |
acd5c798 | 917 | etc. */ |
63c0089f MK |
918 | gdb_byte buf[8]; |
919 | gdb_byte op; | |
fc338970 | 920 | |
8defab1a | 921 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
922 | |
923 | if (op == 0x68 || op == 0x6a) | |
924 | { | |
925 | int delta; | |
c906108c | 926 | |
acd5c798 MK |
927 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
928 | four-byte operand, depending on the opcode. */ | |
c906108c | 929 | if (op == 0x68) |
acd5c798 | 930 | delta = 5; |
c906108c | 931 | else |
acd5c798 | 932 | delta = 2; |
c906108c | 933 | |
acd5c798 MK |
934 | /* Read the following 8 bytes, which should be `call _probe' (6 |
935 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
936 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 937 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 938 | pc += delta + sizeof (buf); |
c906108c SS |
939 | } |
940 | ||
acd5c798 MK |
941 | return pc; |
942 | } | |
943 | ||
92dd43fa MK |
944 | /* GCC 4.1 and later, can put code in the prologue to realign the |
945 | stack pointer. Check whether PC points to such code, and update | |
946 | CACHE accordingly. Return the first instruction after the code | |
947 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
948 | recognize the code, return PC. */ | |
949 | ||
950 | static CORE_ADDR | |
951 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
952 | struct i386_frame_cache *cache) | |
953 | { | |
e0c62198 L |
954 | /* There are 2 code sequences to re-align stack before the frame |
955 | gets set up: | |
956 | ||
957 | 1. Use a caller-saved saved register: | |
958 | ||
959 | leal 4(%esp), %reg | |
960 | andl $-XXX, %esp | |
961 | pushl -4(%reg) | |
962 | ||
963 | 2. Use a callee-saved saved register: | |
964 | ||
965 | pushl %reg | |
966 | leal 8(%esp), %reg | |
967 | andl $-XXX, %esp | |
968 | pushl -4(%reg) | |
969 | ||
970 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
971 | ||
972 | 0x83 0xe4 0xf0 andl $-16, %esp | |
973 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
974 | */ | |
975 | ||
976 | gdb_byte buf[14]; | |
977 | int reg; | |
978 | int offset, offset_and; | |
979 | static int regnums[8] = { | |
980 | I386_EAX_REGNUM, /* %eax */ | |
981 | I386_ECX_REGNUM, /* %ecx */ | |
982 | I386_EDX_REGNUM, /* %edx */ | |
983 | I386_EBX_REGNUM, /* %ebx */ | |
984 | I386_ESP_REGNUM, /* %esp */ | |
985 | I386_EBP_REGNUM, /* %ebp */ | |
986 | I386_ESI_REGNUM, /* %esi */ | |
987 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 988 | }; |
92dd43fa | 989 | |
e0c62198 L |
990 | if (target_read_memory (pc, buf, sizeof buf)) |
991 | return pc; | |
992 | ||
993 | /* Check caller-saved saved register. The first instruction has | |
994 | to be "leal 4(%esp), %reg". */ | |
995 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
996 | { | |
997 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
998 | if ((buf[1] & 0xc7) != 0x44) | |
999 | return pc; | |
1000 | ||
1001 | /* REG has register number. */ | |
1002 | reg = (buf[1] >> 3) & 7; | |
1003 | offset = 4; | |
1004 | } | |
1005 | else | |
1006 | { | |
1007 | /* Check callee-saved saved register. The first instruction | |
1008 | has to be "pushl %reg". */ | |
1009 | if ((buf[0] & 0xf8) != 0x50) | |
1010 | return pc; | |
1011 | ||
1012 | /* Get register. */ | |
1013 | reg = buf[0] & 0x7; | |
1014 | ||
1015 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1016 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1017 | return pc; | |
1018 | ||
1019 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1020 | if ((buf[2] & 0xc7) != 0x44) | |
1021 | return pc; | |
1022 | ||
1023 | /* REG has register number. Registers in pushl and leal have to | |
1024 | be the same. */ | |
1025 | if (reg != ((buf[2] >> 3) & 7)) | |
1026 | return pc; | |
1027 | ||
1028 | offset = 5; | |
1029 | } | |
1030 | ||
1031 | /* Rigister can't be %esp nor %ebp. */ | |
1032 | if (reg == 4 || reg == 5) | |
1033 | return pc; | |
1034 | ||
1035 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1036 | if (buf[offset + 1] != 0xe4 | |
1037 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1038 | return pc; | |
1039 | ||
1040 | offset_and = offset; | |
1041 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1042 | ||
1043 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1044 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1045 | if (buf[offset] != 0xff | |
1046 | || buf[offset + 2] != 0xfc | |
1047 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1048 | return pc; | |
1049 | ||
1050 | /* R/M has register. Registers in leal and pushl have to be the | |
1051 | same. */ | |
1052 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1053 | return pc; |
1054 | ||
e0c62198 L |
1055 | if (current_pc > pc + offset_and) |
1056 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1057 | |
e0c62198 | 1058 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1059 | } |
1060 | ||
37bdc87e | 1061 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1062 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1063 | |
1064 | /* Instruction description. */ | |
1065 | struct i386_insn | |
1066 | { | |
1067 | size_t len; | |
237fc4c9 PA |
1068 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1069 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1070 | }; |
1071 | ||
1072 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
1073 | the first instruction description that matches. Otherwise, return | |
1074 | NULL. */ | |
1075 | ||
1076 | static struct i386_insn * | |
1077 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
1078 | { | |
1079 | struct i386_insn *insn; | |
63c0089f | 1080 | gdb_byte op; |
37bdc87e | 1081 | |
8defab1a | 1082 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
1083 | |
1084 | for (insn = skip_insns; insn->len > 0; insn++) | |
1085 | { | |
1086 | if ((op & insn->mask[0]) == insn->insn[0]) | |
1087 | { | |
237fc4c9 | 1088 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 1089 | int insn_matched = 1; |
37bdc87e MK |
1090 | size_t i; |
1091 | ||
1092 | gdb_assert (insn->len > 1); | |
237fc4c9 | 1093 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 1094 | |
8defab1a | 1095 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
1096 | for (i = 1; i < insn->len; i++) |
1097 | { | |
1098 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 1099 | insn_matched = 0; |
37bdc87e | 1100 | } |
613e8135 MK |
1101 | |
1102 | if (insn_matched) | |
1103 | return insn; | |
37bdc87e MK |
1104 | } |
1105 | } | |
1106 | ||
1107 | return NULL; | |
1108 | } | |
1109 | ||
1110 | /* Some special instructions that might be migrated by GCC into the | |
1111 | part of the prologue that sets up the new stack frame. Because the | |
1112 | stack frame hasn't been setup yet, no registers have been saved | |
1113 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1114 | touched. */ | |
1115 | ||
1116 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1117 | { | |
1118 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
1119 | ||
1120 | ??? Should we handle 16-bit operand-sizes here? */ | |
1121 | ||
1122 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1123 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1124 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1125 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1126 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1127 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1128 | { 5, { 0xb8 }, { 0xfe } }, | |
1129 | /* `movl imm32, %edx' */ | |
1130 | { 5, { 0xba }, { 0xff } }, | |
1131 | ||
1132 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1133 | encoding for `mov m32, %eax'. | |
1134 | ||
1135 | ??? Should we handle SIB adressing here? | |
1136 | ??? Should we handle 16-bit operand-sizes here? */ | |
1137 | ||
1138 | /* `movl m32, %eax' */ | |
1139 | { 5, { 0xa1 }, { 0xff } }, | |
1140 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1141 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1142 | /* `movl m32, %edx' */ | |
1143 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1144 | ||
1145 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1146 | Because of the symmetry, there are actually two ways to encode | |
1147 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1148 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1149 | ||
1150 | /* `subl %eax, %eax' */ | |
1151 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1152 | /* `subl %ecx, %ecx' */ | |
1153 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1154 | /* `subl %edx, %edx' */ | |
1155 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1156 | /* `xorl %eax, %eax' */ | |
1157 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1158 | /* `xorl %ecx, %ecx' */ | |
1159 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1160 | /* `xorl %edx, %edx' */ | |
1161 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1162 | { 0 } | |
1163 | }; | |
1164 | ||
e11481da PM |
1165 | |
1166 | /* Check whether PC points to a no-op instruction. */ | |
1167 | static CORE_ADDR | |
1168 | i386_skip_noop (CORE_ADDR pc) | |
1169 | { | |
1170 | gdb_byte op; | |
1171 | int check = 1; | |
1172 | ||
8defab1a | 1173 | target_read_memory (pc, &op, 1); |
e11481da PM |
1174 | |
1175 | while (check) | |
1176 | { | |
1177 | check = 0; | |
1178 | /* Ignore `nop' instruction. */ | |
1179 | if (op == 0x90) | |
1180 | { | |
1181 | pc += 1; | |
8defab1a | 1182 | target_read_memory (pc, &op, 1); |
e11481da PM |
1183 | check = 1; |
1184 | } | |
1185 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1186 | Microsoft system dlls often start with | |
1187 | a `mov %edi,%edi' instruction. | |
1188 | The 5 bytes before the function start are | |
1189 | filled with `nop' instructions. | |
1190 | This pattern can be used for hot-patching: | |
1191 | The `mov %edi, %edi' instruction can be replaced by a | |
1192 | near jump to the location of the 5 `nop' instructions | |
1193 | which can be replaced by a 32-bit jump to anywhere | |
1194 | in the 32-bit address space. */ | |
1195 | ||
1196 | else if (op == 0x8b) | |
1197 | { | |
8defab1a | 1198 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
1199 | if (op == 0xff) |
1200 | { | |
1201 | pc += 2; | |
8defab1a | 1202 | target_read_memory (pc, &op, 1); |
e11481da PM |
1203 | check = 1; |
1204 | } | |
1205 | } | |
1206 | } | |
1207 | return pc; | |
1208 | } | |
1209 | ||
acd5c798 MK |
1210 | /* Check whether PC points at a code that sets up a new stack frame. |
1211 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1212 | instruction after the sequence that sets up the frame or LIMIT, |
1213 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1214 | |
1215 | static CORE_ADDR | |
e17a4113 UW |
1216 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1217 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1218 | struct i386_frame_cache *cache) |
1219 | { | |
e17a4113 | 1220 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1221 | struct i386_insn *insn; |
63c0089f | 1222 | gdb_byte op; |
26604a34 | 1223 | int skip = 0; |
acd5c798 | 1224 | |
37bdc87e MK |
1225 | if (limit <= pc) |
1226 | return limit; | |
acd5c798 | 1227 | |
8defab1a | 1228 | target_read_memory (pc, &op, 1); |
acd5c798 | 1229 | |
c906108c | 1230 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1231 | { |
acd5c798 MK |
1232 | /* Take into account that we've executed the `pushl %ebp' that |
1233 | starts this instruction sequence. */ | |
fd13a04a | 1234 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1235 | cache->sp_offset += 4; |
37bdc87e | 1236 | pc++; |
acd5c798 MK |
1237 | |
1238 | /* If that's all, return now. */ | |
37bdc87e MK |
1239 | if (limit <= pc) |
1240 | return limit; | |
26604a34 | 1241 | |
b4632131 | 1242 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1243 | GCC into the prologue and skip them. At this point in the |
1244 | prologue, code should only touch the scratch registers %eax, | |
1245 | %ecx and %edx, so while the number of posibilities is sheer, | |
1246 | it is limited. | |
5daa5b4e | 1247 | |
26604a34 MK |
1248 | Make sure we only skip these instructions if we later see the |
1249 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1250 | while (pc + skip < limit) |
26604a34 | 1251 | { |
37bdc87e MK |
1252 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1253 | if (insn == NULL) | |
1254 | break; | |
b4632131 | 1255 | |
37bdc87e | 1256 | skip += insn->len; |
26604a34 MK |
1257 | } |
1258 | ||
37bdc87e MK |
1259 | /* If that's all, return now. */ |
1260 | if (limit <= pc + skip) | |
1261 | return limit; | |
1262 | ||
8defab1a | 1263 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1264 | |
26604a34 | 1265 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1266 | switch (op) |
c906108c SS |
1267 | { |
1268 | case 0x8b: | |
e17a4113 UW |
1269 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1270 | != 0xec) | |
37bdc87e | 1271 | return pc; |
c906108c SS |
1272 | break; |
1273 | case 0x89: | |
e17a4113 UW |
1274 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1275 | != 0xe5) | |
37bdc87e | 1276 | return pc; |
c906108c SS |
1277 | break; |
1278 | default: | |
37bdc87e | 1279 | return pc; |
c906108c | 1280 | } |
acd5c798 | 1281 | |
26604a34 MK |
1282 | /* OK, we actually have a frame. We just don't know how large |
1283 | it is yet. Set its size to zero. We'll adjust it if | |
1284 | necessary. We also now commit to skipping the special | |
1285 | instructions mentioned before. */ | |
acd5c798 | 1286 | cache->locals = 0; |
37bdc87e | 1287 | pc += (skip + 2); |
acd5c798 MK |
1288 | |
1289 | /* If that's all, return now. */ | |
37bdc87e MK |
1290 | if (limit <= pc) |
1291 | return limit; | |
acd5c798 | 1292 | |
fc338970 MK |
1293 | /* Check for stack adjustment |
1294 | ||
acd5c798 | 1295 | subl $XXX, %esp |
fc338970 | 1296 | |
fd35795f | 1297 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1298 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1299 | target_read_memory (pc, &op, 1); |
c906108c SS |
1300 | if (op == 0x83) |
1301 | { | |
fd35795f | 1302 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1303 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1304 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1305 | return pc; |
acd5c798 | 1306 | |
37bdc87e MK |
1307 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1308 | make sense to be negative). */ | |
e17a4113 | 1309 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1310 | return pc + 3; |
c906108c SS |
1311 | } |
1312 | else if (op == 0x81) | |
1313 | { | |
fd35795f | 1314 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1315 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1316 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1317 | return pc; |
acd5c798 | 1318 | |
fd35795f | 1319 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1320 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1321 | return pc + 6; |
c906108c SS |
1322 | } |
1323 | else | |
1324 | { | |
acd5c798 | 1325 | /* Some instruction other than `subl'. */ |
37bdc87e | 1326 | return pc; |
c906108c SS |
1327 | } |
1328 | } | |
37bdc87e | 1329 | else if (op == 0xc8) /* enter */ |
c906108c | 1330 | { |
e17a4113 | 1331 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1332 | return pc + 4; |
c906108c | 1333 | } |
21d0e8a4 | 1334 | |
acd5c798 | 1335 | return pc; |
21d0e8a4 MK |
1336 | } |
1337 | ||
acd5c798 MK |
1338 | /* Check whether PC points at code that saves registers on the stack. |
1339 | If so, it updates CACHE and returns the address of the first | |
1340 | instruction after the register saves or CURRENT_PC, whichever is | |
1341 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1342 | |
1343 | static CORE_ADDR | |
acd5c798 MK |
1344 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1345 | struct i386_frame_cache *cache) | |
6bff26de | 1346 | { |
99ab4326 | 1347 | CORE_ADDR offset = 0; |
63c0089f | 1348 | gdb_byte op; |
99ab4326 | 1349 | int i; |
c0d1d883 | 1350 | |
99ab4326 MK |
1351 | if (cache->locals > 0) |
1352 | offset -= cache->locals; | |
1353 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1354 | { | |
8defab1a | 1355 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1356 | if (op < 0x50 || op > 0x57) |
1357 | break; | |
0d17c81d | 1358 | |
99ab4326 MK |
1359 | offset -= 4; |
1360 | cache->saved_regs[op - 0x50] = offset; | |
1361 | cache->sp_offset += 4; | |
1362 | pc++; | |
6bff26de MK |
1363 | } |
1364 | ||
acd5c798 | 1365 | return pc; |
22797942 AC |
1366 | } |
1367 | ||
acd5c798 MK |
1368 | /* Do a full analysis of the prologue at PC and update CACHE |
1369 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1370 | address where the analysis stopped. | |
ed84f6c1 | 1371 | |
fc338970 MK |
1372 | We handle these cases: |
1373 | ||
1374 | The startup sequence can be at the start of the function, or the | |
1375 | function can start with a branch to startup code at the end. | |
1376 | ||
1377 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1378 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1379 | once used in the System V compiler). | |
1380 | ||
1381 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1382 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1383 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1384 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1385 | |
1386 | Next, the registers used by this function are pushed. With the | |
1387 | System V compiler they will always be in the order: %edi, %esi, | |
1388 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1389 | restore %eax); however, the code below is willing to see the pushes | |
1390 | in any order, and will handle up to 8 of them. | |
1391 | ||
1392 | If the setup sequence is at the end of the function, then the next | |
1393 | instruction will be a branch back to the start. */ | |
c906108c | 1394 | |
acd5c798 | 1395 | static CORE_ADDR |
e17a4113 UW |
1396 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1397 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1398 | struct i386_frame_cache *cache) |
c906108c | 1399 | { |
e11481da | 1400 | pc = i386_skip_noop (pc); |
e17a4113 | 1401 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1402 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1403 | pc = i386_skip_probe (pc); | |
92dd43fa | 1404 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1405 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1406 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1407 | } |
1408 | ||
fc338970 | 1409 | /* Return PC of first real instruction. */ |
c906108c | 1410 | |
3a1e71e3 | 1411 | static CORE_ADDR |
6093d2eb | 1412 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1413 | { |
e17a4113 UW |
1414 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1415 | ||
63c0089f | 1416 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1417 | { |
1418 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1419 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1420 | }; |
acd5c798 MK |
1421 | struct i386_frame_cache cache; |
1422 | CORE_ADDR pc; | |
63c0089f | 1423 | gdb_byte op; |
acd5c798 | 1424 | int i; |
c5aa993b | 1425 | |
acd5c798 | 1426 | cache.locals = -1; |
e17a4113 | 1427 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1428 | if (cache.locals < 0) |
1429 | return start_pc; | |
c5aa993b | 1430 | |
acd5c798 | 1431 | /* Found valid frame setup. */ |
c906108c | 1432 | |
fc338970 MK |
1433 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1434 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1435 | %ebx: |
1436 | ||
fc338970 MK |
1437 | call 0x0 |
1438 | popl %ebx | |
1439 | movl %ebx,x(%ebp) (optional) | |
1440 | addl y,%ebx | |
1441 | ||
c906108c SS |
1442 | This code is with the rest of the prologue (at the end of the |
1443 | function), so we have to skip it to get to the first real | |
1444 | instruction at the start of the function. */ | |
c5aa993b | 1445 | |
c906108c SS |
1446 | for (i = 0; i < 6; i++) |
1447 | { | |
8defab1a | 1448 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1449 | if (pic_pat[i] != op) |
c906108c SS |
1450 | break; |
1451 | } | |
1452 | if (i == 6) | |
1453 | { | |
acd5c798 MK |
1454 | int delta = 6; |
1455 | ||
8defab1a | 1456 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1457 | |
c5aa993b | 1458 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1459 | { |
e17a4113 | 1460 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1461 | |
fc338970 | 1462 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1463 | delta += 3; |
fc338970 | 1464 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1465 | delta += 6; |
fc338970 | 1466 | else /* Unexpected instruction. */ |
acd5c798 MK |
1467 | delta = 0; |
1468 | ||
8defab1a | 1469 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1470 | } |
acd5c798 | 1471 | |
c5aa993b | 1472 | /* addl y,%ebx */ |
acd5c798 | 1473 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1474 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1475 | == 0xc3) | |
c906108c | 1476 | { |
acd5c798 | 1477 | pc += delta + 6; |
c906108c SS |
1478 | } |
1479 | } | |
c5aa993b | 1480 | |
e63bbc88 MK |
1481 | /* If the function starts with a branch (to startup code at the end) |
1482 | the last instruction should bring us back to the first | |
1483 | instruction of the real code. */ | |
e17a4113 UW |
1484 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1485 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1486 | |
1487 | return pc; | |
c906108c SS |
1488 | } |
1489 | ||
4309257c PM |
1490 | /* Check that the code pointed to by PC corresponds to a call to |
1491 | __main, skip it if so. Return PC otherwise. */ | |
1492 | ||
1493 | CORE_ADDR | |
1494 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1495 | { | |
e17a4113 | 1496 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1497 | gdb_byte op; |
1498 | ||
1499 | target_read_memory (pc, &op, 1); | |
1500 | if (op == 0xe8) | |
1501 | { | |
1502 | gdb_byte buf[4]; | |
1503 | ||
1504 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1505 | { | |
1506 | /* Make sure address is computed correctly as a 32bit | |
1507 | integer even if CORE_ADDR is 64 bit wide. */ | |
1508 | struct minimal_symbol *s; | |
e17a4113 | 1509 | CORE_ADDR call_dest; |
4309257c | 1510 | |
e17a4113 | 1511 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1512 | call_dest = call_dest & 0xffffffffU; |
1513 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1514 | if (s != NULL | |
1515 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1516 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1517 | pc += 5; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | return pc; | |
1522 | } | |
1523 | ||
acd5c798 | 1524 | /* This function is 64-bit safe. */ |
93924b6b | 1525 | |
acd5c798 MK |
1526 | static CORE_ADDR |
1527 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1528 | { |
63c0089f | 1529 | gdb_byte buf[8]; |
acd5c798 | 1530 | |
875f8d0e | 1531 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1532 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1533 | } |
acd5c798 | 1534 | \f |
93924b6b | 1535 | |
acd5c798 | 1536 | /* Normal frames. */ |
c5aa993b | 1537 | |
acd5c798 | 1538 | static struct i386_frame_cache * |
10458914 | 1539 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1540 | { |
e17a4113 UW |
1541 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1542 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1543 | struct i386_frame_cache *cache; |
63c0089f | 1544 | gdb_byte buf[4]; |
acd5c798 MK |
1545 | int i; |
1546 | ||
1547 | if (*this_cache) | |
1548 | return *this_cache; | |
1549 | ||
fd13a04a | 1550 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1551 | *this_cache = cache; |
1552 | ||
1553 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1554 | which holds the base address for the current stack frame. | |
1555 | However, for functions that don't need it, the frame pointer is | |
1556 | optional. For these "frameless" functions the frame pointer is | |
1557 | actually the frame pointer of the calling frame. Signal | |
1558 | trampolines are just a special case of a "frameless" function. | |
1559 | They (usually) share their frame pointer with the frame that was | |
1560 | in progress when the signal occurred. */ | |
1561 | ||
10458914 | 1562 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1563 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1564 | if (cache->base == 0) |
1565 | return cache; | |
1566 | ||
1567 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1568 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1569 | |
10458914 | 1570 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1571 | if (cache->pc != 0) |
e17a4113 UW |
1572 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1573 | cache); | |
acd5c798 | 1574 | |
e0c62198 | 1575 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1576 | { |
e0c62198 L |
1577 | /* Saved stack pointer has been saved. */ |
1578 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1579 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1580 | } |
1581 | ||
acd5c798 MK |
1582 | if (cache->locals < 0) |
1583 | { | |
1584 | /* We didn't find a valid frame, which means that CACHE->base | |
1585 | currently holds the frame pointer for our calling frame. If | |
1586 | we're at the start of a function, or somewhere half-way its | |
1587 | prologue, the function's frame probably hasn't been fully | |
1588 | setup yet. Try to reconstruct the base address for the stack | |
1589 | frame by looking at the stack pointer. For truly "frameless" | |
1590 | functions this might work too. */ | |
1591 | ||
e0c62198 | 1592 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1593 | { |
1594 | /* We're halfway aligning the stack. */ | |
1595 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1596 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1597 | ||
1598 | /* This will be added back below. */ | |
1599 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1600 | } | |
7618e12b DJ |
1601 | else if (cache->pc != 0 |
1602 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1603 | { |
7618e12b DJ |
1604 | /* We're in a known function, but did not find a frame |
1605 | setup. Assume that the function does not use %ebp. | |
1606 | Alternatively, we may have jumped to an invalid | |
1607 | address; in that case there is definitely no new | |
1608 | frame in %ebp. */ | |
10458914 | 1609 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1610 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1611 | + cache->sp_offset; | |
92dd43fa | 1612 | } |
7618e12b DJ |
1613 | else |
1614 | /* We're in an unknown function. We could not find the start | |
1615 | of the function to analyze the prologue; our best option is | |
1616 | to assume a typical frame layout with the caller's %ebp | |
1617 | saved. */ | |
1618 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1619 | } |
1620 | ||
1621 | /* Now that we have the base address for the stack frame we can | |
1622 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1623 | if (cache->saved_sp == 0) |
1624 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1625 | |
acd5c798 MK |
1626 | /* Adjust all the saved registers such that they contain addresses |
1627 | instead of offsets. */ | |
1628 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1629 | if (cache->saved_regs[i] != -1) |
1630 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1631 | |
1632 | return cache; | |
a7769679 MK |
1633 | } |
1634 | ||
3a1e71e3 | 1635 | static void |
10458914 | 1636 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1637 | struct frame_id *this_id) |
c906108c | 1638 | { |
10458914 | 1639 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1640 | |
1641 | /* This marks the outermost frame. */ | |
1642 | if (cache->base == 0) | |
1643 | return; | |
1644 | ||
3e210248 | 1645 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1646 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1647 | } | |
1648 | ||
10458914 DJ |
1649 | static struct value * |
1650 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1651 | int regnum) | |
acd5c798 | 1652 | { |
10458914 | 1653 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1654 | |
1655 | gdb_assert (regnum >= 0); | |
1656 | ||
1657 | /* The System V ABI says that: | |
1658 | ||
1659 | "The flags register contains the system flags, such as the | |
1660 | direction flag and the carry flag. The direction flag must be | |
1661 | set to the forward (that is, zero) direction before entry and | |
1662 | upon exit from a function. Other user flags have no specified | |
1663 | role in the standard calling sequence and are not preserved." | |
1664 | ||
1665 | To guarantee the "upon exit" part of that statement we fake a | |
1666 | saved flags register that has its direction flag cleared. | |
1667 | ||
1668 | Note that GCC doesn't seem to rely on the fact that the direction | |
1669 | flag is cleared after a function return; it always explicitly | |
1670 | clears the flag before operations where it matters. | |
1671 | ||
1672 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1673 | right thing to do. The way we fake the flags register here makes | |
1674 | it impossible to change it. */ | |
1675 | ||
1676 | if (regnum == I386_EFLAGS_REGNUM) | |
1677 | { | |
10458914 | 1678 | ULONGEST val; |
c5aa993b | 1679 | |
10458914 DJ |
1680 | val = get_frame_register_unsigned (this_frame, regnum); |
1681 | val &= ~(1 << 10); | |
1682 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1683 | } |
1211c4e4 | 1684 | |
acd5c798 | 1685 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1686 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1687 | |
1688 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1689 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1690 | |
fd13a04a | 1691 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1692 | return frame_unwind_got_memory (this_frame, regnum, |
1693 | cache->saved_regs[regnum]); | |
fd13a04a | 1694 | |
10458914 | 1695 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1696 | } |
1697 | ||
1698 | static const struct frame_unwind i386_frame_unwind = | |
1699 | { | |
1700 | NORMAL_FRAME, | |
1701 | i386_frame_this_id, | |
10458914 DJ |
1702 | i386_frame_prev_register, |
1703 | NULL, | |
1704 | default_frame_sniffer | |
acd5c798 | 1705 | }; |
06da04c6 MS |
1706 | |
1707 | /* Normal frames, but in a function epilogue. */ | |
1708 | ||
1709 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1710 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1711 | the function's stack frame. */ | |
1712 | ||
1713 | static int | |
1714 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1715 | { | |
1716 | gdb_byte insn; | |
1717 | ||
1718 | if (target_read_memory (pc, &insn, 1)) | |
1719 | return 0; /* Can't read memory at pc. */ | |
1720 | ||
1721 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1722 | return 0; | |
1723 | ||
1724 | return 1; | |
1725 | } | |
1726 | ||
1727 | static int | |
1728 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1729 | struct frame_info *this_frame, | |
1730 | void **this_prologue_cache) | |
1731 | { | |
1732 | if (frame_relative_level (this_frame) == 0) | |
1733 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1734 | get_frame_pc (this_frame)); | |
1735 | else | |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | static struct i386_frame_cache * | |
1740 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1741 | { | |
1742 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1743 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1744 | struct i386_frame_cache *cache; | |
1745 | gdb_byte buf[4]; | |
1746 | ||
1747 | if (*this_cache) | |
1748 | return *this_cache; | |
1749 | ||
1750 | cache = i386_alloc_frame_cache (); | |
1751 | *this_cache = cache; | |
1752 | ||
1753 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1754 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1755 | cache->base = extract_unsigned_integer (buf, 4, | |
1756 | byte_order) + cache->sp_offset; | |
1757 | ||
1758 | /* Cache pc will be the frame func. */ | |
1759 | cache->pc = get_frame_pc (this_frame); | |
1760 | ||
1761 | /* The saved %esp will be at cache->base plus 8. */ | |
1762 | cache->saved_sp = cache->base + 8; | |
1763 | ||
1764 | /* The saved %eip will be at cache->base plus 4. */ | |
1765 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1766 | ||
1767 | return cache; | |
1768 | } | |
1769 | ||
1770 | static void | |
1771 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1772 | void **this_cache, | |
1773 | struct frame_id *this_id) | |
1774 | { | |
1775 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1776 | this_cache); | |
1777 | ||
1778 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1779 | } | |
1780 | ||
1781 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1782 | { | |
1783 | NORMAL_FRAME, | |
1784 | i386_epilogue_frame_this_id, | |
1785 | i386_frame_prev_register, | |
1786 | NULL, | |
1787 | i386_epilogue_frame_sniffer | |
1788 | }; | |
acd5c798 MK |
1789 | \f |
1790 | ||
1791 | /* Signal trampolines. */ | |
1792 | ||
1793 | static struct i386_frame_cache * | |
10458914 | 1794 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1795 | { |
e17a4113 UW |
1796 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1797 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1798 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1799 | struct i386_frame_cache *cache; |
acd5c798 | 1800 | CORE_ADDR addr; |
63c0089f | 1801 | gdb_byte buf[4]; |
acd5c798 MK |
1802 | |
1803 | if (*this_cache) | |
1804 | return *this_cache; | |
1805 | ||
fd13a04a | 1806 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1807 | |
10458914 | 1808 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1809 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1810 | |
10458914 | 1811 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1812 | if (tdep->sc_reg_offset) |
1813 | { | |
1814 | int i; | |
1815 | ||
1816 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1817 | ||
1818 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1819 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1820 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1821 | } |
1822 | else | |
1823 | { | |
fd13a04a AC |
1824 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1825 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1826 | } |
acd5c798 MK |
1827 | |
1828 | *this_cache = cache; | |
1829 | return cache; | |
1830 | } | |
1831 | ||
1832 | static void | |
10458914 | 1833 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1834 | struct frame_id *this_id) |
1835 | { | |
1836 | struct i386_frame_cache *cache = | |
10458914 | 1837 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1838 | |
3e210248 | 1839 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1840 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1841 | } |
1842 | ||
10458914 DJ |
1843 | static struct value * |
1844 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1845 | void **this_cache, int regnum) | |
acd5c798 MK |
1846 | { |
1847 | /* Make sure we've initialized the cache. */ | |
10458914 | 1848 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1849 | |
10458914 | 1850 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1851 | } |
c0d1d883 | 1852 | |
10458914 DJ |
1853 | static int |
1854 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1855 | struct frame_info *this_frame, | |
1856 | void **this_prologue_cache) | |
acd5c798 | 1857 | { |
10458914 | 1858 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1859 | |
911bc6ee MK |
1860 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1861 | handler. */ | |
1862 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1863 | return 0; |
1c3545ae | 1864 | |
911bc6ee MK |
1865 | if (tdep->sigtramp_p != NULL) |
1866 | { | |
10458914 DJ |
1867 | if (tdep->sigtramp_p (this_frame)) |
1868 | return 1; | |
911bc6ee MK |
1869 | } |
1870 | ||
1871 | if (tdep->sigtramp_start != 0) | |
1872 | { | |
10458914 | 1873 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1874 | |
1875 | gdb_assert (tdep->sigtramp_end != 0); | |
1876 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1877 | return 1; |
911bc6ee | 1878 | } |
acd5c798 | 1879 | |
10458914 | 1880 | return 0; |
acd5c798 | 1881 | } |
10458914 DJ |
1882 | |
1883 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1884 | { | |
1885 | SIGTRAMP_FRAME, | |
1886 | i386_sigtramp_frame_this_id, | |
1887 | i386_sigtramp_frame_prev_register, | |
1888 | NULL, | |
1889 | i386_sigtramp_frame_sniffer | |
1890 | }; | |
acd5c798 MK |
1891 | \f |
1892 | ||
1893 | static CORE_ADDR | |
10458914 | 1894 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1895 | { |
10458914 | 1896 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1897 | |
1898 | return cache->base; | |
1899 | } | |
1900 | ||
1901 | static const struct frame_base i386_frame_base = | |
1902 | { | |
1903 | &i386_frame_unwind, | |
1904 | i386_frame_base_address, | |
1905 | i386_frame_base_address, | |
1906 | i386_frame_base_address | |
1907 | }; | |
1908 | ||
acd5c798 | 1909 | static struct frame_id |
10458914 | 1910 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1911 | { |
acd5c798 MK |
1912 | CORE_ADDR fp; |
1913 | ||
10458914 | 1914 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1915 | |
3e210248 | 1916 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1917 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1918 | } |
fc338970 | 1919 | \f |
c906108c | 1920 | |
fc338970 MK |
1921 | /* Figure out where the longjmp will land. Slurp the args out of the |
1922 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1923 | structure from which we extract the address that we will land at. |
28bcfd30 | 1924 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1925 | success. */ |
c906108c | 1926 | |
8201327c | 1927 | static int |
60ade65d | 1928 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1929 | { |
436675d3 | 1930 | gdb_byte buf[4]; |
c906108c | 1931 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1932 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1933 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1934 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1935 | |
8201327c MK |
1936 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1937 | longjmp will land. */ | |
1938 | if (jb_pc_offset == -1) | |
c906108c SS |
1939 | return 0; |
1940 | ||
436675d3 | 1941 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1942 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1943 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1944 | return 0; |
1945 | ||
e17a4113 | 1946 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1947 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1948 | return 0; |
c906108c | 1949 | |
e17a4113 | 1950 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1951 | return 1; |
1952 | } | |
fc338970 | 1953 | \f |
c906108c | 1954 | |
7ccc1c74 JM |
1955 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1956 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1957 | unions containing such types must be 16-byte-aligned; other | |
1958 | arguments are 4-byte-aligned. */ | |
1959 | ||
1960 | static int | |
1961 | i386_16_byte_align_p (struct type *type) | |
1962 | { | |
1963 | type = check_typedef (type); | |
1964 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1965 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1966 | && TYPE_LENGTH (type) == 16) | |
1967 | return 1; | |
1968 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1969 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1970 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1971 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1972 | { | |
1973 | int i; | |
1974 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1975 | { | |
1976 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1977 | return 1; | |
1978 | } | |
1979 | } | |
1980 | return 0; | |
1981 | } | |
1982 | ||
3a1e71e3 | 1983 | static CORE_ADDR |
7d9b040b | 1984 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1985 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1986 | struct value **args, CORE_ADDR sp, int struct_return, | |
1987 | CORE_ADDR struct_addr) | |
22f8ba57 | 1988 | { |
e17a4113 | 1989 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1990 | gdb_byte buf[4]; |
acd5c798 | 1991 | int i; |
7ccc1c74 JM |
1992 | int write_pass; |
1993 | int args_space = 0; | |
acd5c798 | 1994 | |
7ccc1c74 JM |
1995 | /* Determine the total space required for arguments and struct |
1996 | return address in a first pass (allowing for 16-byte-aligned | |
1997 | arguments), then push arguments in a second pass. */ | |
1998 | ||
1999 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2000 | { |
7ccc1c74 JM |
2001 | int args_space_used = 0; |
2002 | int have_16_byte_aligned_arg = 0; | |
2003 | ||
2004 | if (struct_return) | |
2005 | { | |
2006 | if (write_pass) | |
2007 | { | |
2008 | /* Push value address. */ | |
e17a4113 | 2009 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2010 | write_memory (sp, buf, 4); |
2011 | args_space_used += 4; | |
2012 | } | |
2013 | else | |
2014 | args_space += 4; | |
2015 | } | |
2016 | ||
2017 | for (i = 0; i < nargs; i++) | |
2018 | { | |
2019 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2020 | |
7ccc1c74 JM |
2021 | if (write_pass) |
2022 | { | |
2023 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2024 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2025 | |
7ccc1c74 JM |
2026 | write_memory (sp + args_space_used, |
2027 | value_contents_all (args[i]), len); | |
2028 | /* The System V ABI says that: | |
acd5c798 | 2029 | |
7ccc1c74 JM |
2030 | "An argument's size is increased, if necessary, to make it a |
2031 | multiple of [32-bit] words. This may require tail padding, | |
2032 | depending on the size of the argument." | |
22f8ba57 | 2033 | |
7ccc1c74 JM |
2034 | This makes sure the stack stays word-aligned. */ |
2035 | args_space_used += align_up (len, 4); | |
2036 | } | |
2037 | else | |
2038 | { | |
2039 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2040 | { | |
2041 | args_space = align_up (args_space, 16); | |
2042 | have_16_byte_aligned_arg = 1; | |
2043 | } | |
2044 | args_space += align_up (len, 4); | |
2045 | } | |
2046 | } | |
2047 | ||
2048 | if (!write_pass) | |
2049 | { | |
2050 | if (have_16_byte_aligned_arg) | |
2051 | args_space = align_up (args_space, 16); | |
2052 | sp -= args_space; | |
2053 | } | |
22f8ba57 MK |
2054 | } |
2055 | ||
acd5c798 MK |
2056 | /* Store return address. */ |
2057 | sp -= 4; | |
e17a4113 | 2058 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2059 | write_memory (sp, buf, 4); |
2060 | ||
2061 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2062 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2063 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2064 | ||
2065 | /* ...and fake a frame pointer. */ | |
2066 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2067 | ||
3e210248 AC |
2068 | /* MarkK wrote: This "+ 8" is all over the place: |
2069 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2070 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2071 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2072 | definition of the stack address of a frame. Otherwise frame id |
2073 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2074 | stack address *before* the function call as a frame's CFA. On |
2075 | the i386, when %ebp is used as a frame pointer, the offset | |
2076 | between the contents %ebp and the CFA as defined by GCC. */ | |
2077 | return sp + 8; | |
22f8ba57 MK |
2078 | } |
2079 | ||
1a309862 MK |
2080 | /* These registers are used for returning integers (and on some |
2081 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2082 | size and alignment match an integer type). */ |
acd5c798 MK |
2083 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2084 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2085 | |
c5e656c1 MK |
2086 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2087 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2088 | |
3a1e71e3 | 2089 | static void |
c5e656c1 | 2090 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2091 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2092 | { |
c5e656c1 | 2093 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2094 | int len = TYPE_LENGTH (type); |
63c0089f | 2095 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2096 | |
1e8d0a7b | 2097 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2098 | { |
5716833c | 2099 | if (tdep->st0_regnum < 0) |
1a309862 | 2100 | { |
8a3fe4f8 | 2101 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2102 | memset (valbuf, 0, len); |
ef9dff19 | 2103 | return; |
1a309862 MK |
2104 | } |
2105 | ||
c6ba6f0d MK |
2106 | /* Floating-point return values can be found in %st(0). Convert |
2107 | its contents to the desired type. This is probably not | |
2108 | exactly how it would happen on the target itself, but it is | |
2109 | the best we can do. */ | |
acd5c798 | 2110 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2111 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2112 | } |
2113 | else | |
c5aa993b | 2114 | { |
875f8d0e UW |
2115 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2116 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2117 | |
2118 | if (len <= low_size) | |
00f8375e | 2119 | { |
0818c12a | 2120 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2121 | memcpy (valbuf, buf, len); |
2122 | } | |
d4f3574e SS |
2123 | else if (len <= (low_size + high_size)) |
2124 | { | |
0818c12a | 2125 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2126 | memcpy (valbuf, buf, low_size); |
0818c12a | 2127 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2128 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2129 | } |
2130 | else | |
8e65ff28 | 2131 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2132 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
2133 | } |
2134 | } | |
2135 | ||
c5e656c1 MK |
2136 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2137 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2138 | |
3a1e71e3 | 2139 | static void |
c5e656c1 | 2140 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2141 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2142 | { |
c5e656c1 | 2143 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2144 | int len = TYPE_LENGTH (type); |
2145 | ||
1e8d0a7b | 2146 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2147 | { |
3d7f4f49 | 2148 | ULONGEST fstat; |
63c0089f | 2149 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2150 | |
5716833c | 2151 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2152 | { |
8a3fe4f8 | 2153 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2154 | return; |
2155 | } | |
2156 | ||
635b0cc1 MK |
2157 | /* Returning floating-point values is a bit tricky. Apart from |
2158 | storing the return value in %st(0), we have to simulate the | |
2159 | state of the FPU at function return point. */ | |
2160 | ||
c6ba6f0d MK |
2161 | /* Convert the value found in VALBUF to the extended |
2162 | floating-point format used by the FPU. This is probably | |
2163 | not exactly how it would happen on the target itself, but | |
2164 | it is the best we can do. */ | |
27067745 | 2165 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2166 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2167 | |
635b0cc1 MK |
2168 | /* Set the top of the floating-point register stack to 7. The |
2169 | actual value doesn't really matter, but 7 is what a normal | |
2170 | function return would end up with if the program started out | |
2171 | with a freshly initialized FPU. */ | |
20a6ec49 | 2172 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2173 | fstat |= (7 << 11); |
20a6ec49 | 2174 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2175 | |
635b0cc1 MK |
2176 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2177 | the floating-point register stack to 7, the appropriate value | |
2178 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2179 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2180 | } |
2181 | else | |
2182 | { | |
875f8d0e UW |
2183 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2184 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2185 | |
2186 | if (len <= low_size) | |
3d7f4f49 | 2187 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2188 | else if (len <= (low_size + high_size)) |
2189 | { | |
3d7f4f49 MK |
2190 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2191 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2192 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2193 | } |
2194 | else | |
8e65ff28 | 2195 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2196 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2197 | } |
2198 | } | |
fc338970 | 2199 | \f |
ef9dff19 | 2200 | |
8201327c MK |
2201 | /* This is the variable that is set with "set struct-convention", and |
2202 | its legitimate values. */ | |
2203 | static const char default_struct_convention[] = "default"; | |
2204 | static const char pcc_struct_convention[] = "pcc"; | |
2205 | static const char reg_struct_convention[] = "reg"; | |
2206 | static const char *valid_conventions[] = | |
2207 | { | |
2208 | default_struct_convention, | |
2209 | pcc_struct_convention, | |
2210 | reg_struct_convention, | |
2211 | NULL | |
2212 | }; | |
2213 | static const char *struct_convention = default_struct_convention; | |
2214 | ||
0e4377e1 JB |
2215 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2216 | a union type, or an array type, should be returned in registers | |
2217 | for architecture GDBARCH. */ | |
c5e656c1 | 2218 | |
8201327c | 2219 | static int |
c5e656c1 | 2220 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2221 | { |
c5e656c1 MK |
2222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2223 | enum type_code code = TYPE_CODE (type); | |
2224 | int len = TYPE_LENGTH (type); | |
8201327c | 2225 | |
0e4377e1 JB |
2226 | gdb_assert (code == TYPE_CODE_STRUCT |
2227 | || code == TYPE_CODE_UNION | |
2228 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2229 | |
2230 | if (struct_convention == pcc_struct_convention | |
2231 | || (struct_convention == default_struct_convention | |
2232 | && tdep->struct_return == pcc_struct_return)) | |
2233 | return 0; | |
2234 | ||
9edde48e MK |
2235 | /* Structures consisting of a single `float', `double' or 'long |
2236 | double' member are returned in %st(0). */ | |
2237 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2238 | { | |
2239 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2240 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2241 | return (len == 4 || len == 8 || len == 12); | |
2242 | } | |
2243 | ||
c5e656c1 MK |
2244 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2245 | } | |
2246 | ||
2247 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2248 | should be returned. If it is supposed to be returned in registers, | |
2249 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2250 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2251 | from WRITEBUF into REGCACHE. */ | |
2252 | ||
2253 | static enum return_value_convention | |
c055b101 CV |
2254 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2255 | struct type *type, struct regcache *regcache, | |
2256 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2257 | { |
2258 | enum type_code code = TYPE_CODE (type); | |
2259 | ||
5daa78cc TJB |
2260 | if (((code == TYPE_CODE_STRUCT |
2261 | || code == TYPE_CODE_UNION | |
2262 | || code == TYPE_CODE_ARRAY) | |
2263 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2264 | /* 128-bit decimal float uses the struct return convention. */ | |
2265 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2266 | { |
2267 | /* The System V ABI says that: | |
2268 | ||
2269 | "A function that returns a structure or union also sets %eax | |
2270 | to the value of the original address of the caller's area | |
2271 | before it returns. Thus when the caller receives control | |
2272 | again, the address of the returned object resides in register | |
2273 | %eax and can be used to access the object." | |
2274 | ||
2275 | So the ABI guarantees that we can always find the return | |
2276 | value just after the function has returned. */ | |
2277 | ||
0e4377e1 JB |
2278 | /* Note that the ABI doesn't mention functions returning arrays, |
2279 | which is something possible in certain languages such as Ada. | |
2280 | In this case, the value is returned as if it was wrapped in | |
2281 | a record, so the convention applied to records also applies | |
2282 | to arrays. */ | |
2283 | ||
31db7b6c MK |
2284 | if (readbuf) |
2285 | { | |
2286 | ULONGEST addr; | |
2287 | ||
2288 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2289 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2290 | } | |
2291 | ||
2292 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2293 | } | |
c5e656c1 MK |
2294 | |
2295 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2296 | `float', `double' or 'long double' member. These structures are |
2297 | returned in %st(0). For these structures, we call ourselves | |
2298 | recursively, changing TYPE into the type of the first member of | |
2299 | the structure. Since that should work for all structures that | |
2300 | have only one member, we don't bother to check the member's type | |
2301 | here. */ | |
c5e656c1 MK |
2302 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2303 | { | |
2304 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2305 | return i386_return_value (gdbarch, func_type, type, regcache, |
2306 | readbuf, writebuf); | |
c5e656c1 MK |
2307 | } |
2308 | ||
2309 | if (readbuf) | |
2310 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2311 | if (writebuf) | |
2312 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2313 | |
c5e656c1 | 2314 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2315 | } |
2316 | \f | |
2317 | ||
27067745 UW |
2318 | struct type * |
2319 | i387_ext_type (struct gdbarch *gdbarch) | |
2320 | { | |
2321 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2322 | ||
2323 | if (!tdep->i387_ext_type) | |
90884b2b L |
2324 | { |
2325 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2326 | gdb_assert (tdep->i387_ext_type != NULL); | |
2327 | } | |
27067745 UW |
2328 | |
2329 | return tdep->i387_ext_type; | |
2330 | } | |
2331 | ||
c131fcee L |
2332 | /* Construct vector type for pseudo YMM registers. We can't use |
2333 | tdesc_find_type since YMM isn't described in target description. */ | |
2334 | ||
2335 | static struct type * | |
2336 | i386_ymm_type (struct gdbarch *gdbarch) | |
2337 | { | |
2338 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2339 | ||
2340 | if (!tdep->i386_ymm_type) | |
2341 | { | |
2342 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2343 | ||
2344 | /* The type we're building is this: */ | |
2345 | #if 0 | |
2346 | union __gdb_builtin_type_vec256i | |
2347 | { | |
2348 | int128_t uint128[2]; | |
2349 | int64_t v2_int64[4]; | |
2350 | int32_t v4_int32[8]; | |
2351 | int16_t v8_int16[16]; | |
2352 | int8_t v16_int8[32]; | |
2353 | double v2_double[4]; | |
2354 | float v4_float[8]; | |
2355 | }; | |
2356 | #endif | |
2357 | ||
2358 | struct type *t; | |
2359 | ||
2360 | t = arch_composite_type (gdbarch, | |
2361 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2362 | append_composite_type_field (t, "v8_float", | |
2363 | init_vector_type (bt->builtin_float, 8)); | |
2364 | append_composite_type_field (t, "v4_double", | |
2365 | init_vector_type (bt->builtin_double, 4)); | |
2366 | append_composite_type_field (t, "v32_int8", | |
2367 | init_vector_type (bt->builtin_int8, 32)); | |
2368 | append_composite_type_field (t, "v16_int16", | |
2369 | init_vector_type (bt->builtin_int16, 16)); | |
2370 | append_composite_type_field (t, "v8_int32", | |
2371 | init_vector_type (bt->builtin_int32, 8)); | |
2372 | append_composite_type_field (t, "v4_int64", | |
2373 | init_vector_type (bt->builtin_int64, 4)); | |
2374 | append_composite_type_field (t, "v2_int128", | |
2375 | init_vector_type (bt->builtin_int128, 2)); | |
2376 | ||
2377 | TYPE_VECTOR (t) = 1; | |
2378 | TYPE_NAME (t) = "builtin_type_vec128i"; | |
2379 | tdep->i386_ymm_type = t; | |
2380 | } | |
2381 | ||
2382 | return tdep->i386_ymm_type; | |
2383 | } | |
2384 | ||
794ac428 | 2385 | /* Construct vector type for MMX registers. */ |
90884b2b | 2386 | static struct type * |
794ac428 UW |
2387 | i386_mmx_type (struct gdbarch *gdbarch) |
2388 | { | |
2389 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2390 | ||
2391 | if (!tdep->i386_mmx_type) | |
2392 | { | |
df4df182 UW |
2393 | const struct builtin_type *bt = builtin_type (gdbarch); |
2394 | ||
794ac428 UW |
2395 | /* The type we're building is this: */ |
2396 | #if 0 | |
2397 | union __gdb_builtin_type_vec64i | |
2398 | { | |
2399 | int64_t uint64; | |
2400 | int32_t v2_int32[2]; | |
2401 | int16_t v4_int16[4]; | |
2402 | int8_t v8_int8[8]; | |
2403 | }; | |
2404 | #endif | |
2405 | ||
2406 | struct type *t; | |
2407 | ||
e9bb382b UW |
2408 | t = arch_composite_type (gdbarch, |
2409 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2410 | |
2411 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2412 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2413 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2414 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2415 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2416 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2417 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2418 | |
876cecd0 | 2419 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2420 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2421 | tdep->i386_mmx_type = t; | |
2422 | } | |
2423 | ||
2424 | return tdep->i386_mmx_type; | |
2425 | } | |
2426 | ||
d7a0d72c | 2427 | /* Return the GDB type object for the "standard" data type of data in |
90884b2b | 2428 | register REGNUM. */ |
d7a0d72c | 2429 | |
3a1e71e3 | 2430 | static struct type * |
90884b2b | 2431 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2432 | { |
1ba53b71 L |
2433 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2434 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2435 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2436 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2437 | else |
2438 | { | |
2439 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2440 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2441 | return bt->builtin_int8; | |
2442 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2443 | return bt->builtin_int16; | |
2444 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2445 | return bt->builtin_int32; | |
2446 | } | |
2447 | ||
2448 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2449 | } |
2450 | ||
28fc6740 | 2451 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2452 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2453 | |
2454 | static int | |
c86c27af | 2455 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2456 | { |
5716833c MK |
2457 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2458 | int mmxreg, fpreg; | |
28fc6740 AC |
2459 | ULONGEST fstat; |
2460 | int tos; | |
c86c27af | 2461 | |
5716833c | 2462 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2463 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2464 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2465 | fpreg = (mmxreg + tos) % 8; |
2466 | ||
20a6ec49 | 2467 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2468 | } |
2469 | ||
1ba53b71 | 2470 | void |
28fc6740 | 2471 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2472 | int regnum, gdb_byte *buf) |
28fc6740 | 2473 | { |
1ba53b71 L |
2474 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2475 | ||
5716833c | 2476 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2477 | { |
c86c27af MK |
2478 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2479 | ||
28fc6740 | 2480 | /* Extract (always little endian). */ |
1ba53b71 L |
2481 | regcache_raw_read (regcache, fpnum, raw_buf); |
2482 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2483 | } |
2484 | else | |
1ba53b71 L |
2485 | { |
2486 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2487 | ||
c131fcee L |
2488 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2489 | { | |
2490 | regnum -= tdep->ymm0_regnum; | |
2491 | ||
2492 | /* Extract (always little endian). Read lower 128bits. */ | |
2493 | regcache_raw_read (regcache, | |
2494 | I387_XMM0_REGNUM (tdep) + regnum, | |
2495 | raw_buf); | |
2496 | memcpy (buf, raw_buf, 16); | |
2497 | /* Read upper 128bits. */ | |
2498 | regcache_raw_read (regcache, | |
2499 | tdep->ymm0h_regnum + regnum, | |
2500 | raw_buf); | |
2501 | memcpy (buf + 16, raw_buf, 16); | |
2502 | } | |
2503 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2504 | { |
2505 | int gpnum = regnum - tdep->ax_regnum; | |
2506 | ||
2507 | /* Extract (always little endian). */ | |
2508 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2509 | memcpy (buf, raw_buf, 2); | |
2510 | } | |
2511 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2512 | { | |
2513 | /* Check byte pseudo registers last since this function will | |
2514 | be called from amd64_pseudo_register_read, which handles | |
2515 | byte pseudo registers differently. */ | |
2516 | int gpnum = regnum - tdep->al_regnum; | |
2517 | ||
2518 | /* Extract (always little endian). We read both lower and | |
2519 | upper registers. */ | |
2520 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2521 | if (gpnum >= 4) | |
2522 | memcpy (buf, raw_buf + 1, 1); | |
2523 | else | |
2524 | memcpy (buf, raw_buf, 1); | |
2525 | } | |
2526 | else | |
2527 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2528 | } | |
28fc6740 AC |
2529 | } |
2530 | ||
1ba53b71 | 2531 | void |
28fc6740 | 2532 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2533 | int regnum, const gdb_byte *buf) |
28fc6740 | 2534 | { |
1ba53b71 L |
2535 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2536 | ||
5716833c | 2537 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2538 | { |
c86c27af MK |
2539 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2540 | ||
28fc6740 | 2541 | /* Read ... */ |
1ba53b71 | 2542 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2543 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2544 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2545 | /* ... Write. */ |
1ba53b71 | 2546 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2547 | } |
2548 | else | |
1ba53b71 L |
2549 | { |
2550 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2551 | ||
c131fcee L |
2552 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2553 | { | |
2554 | regnum -= tdep->ymm0_regnum; | |
2555 | ||
2556 | /* ... Write lower 128bits. */ | |
2557 | regcache_raw_write (regcache, | |
2558 | I387_XMM0_REGNUM (tdep) + regnum, | |
2559 | buf); | |
2560 | /* ... Write upper 128bits. */ | |
2561 | regcache_raw_write (regcache, | |
2562 | tdep->ymm0h_regnum + regnum, | |
2563 | buf + 16); | |
2564 | } | |
2565 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2566 | { |
2567 | int gpnum = regnum - tdep->ax_regnum; | |
2568 | ||
2569 | /* Read ... */ | |
2570 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2571 | /* ... Modify ... (always little endian). */ | |
2572 | memcpy (raw_buf, buf, 2); | |
2573 | /* ... Write. */ | |
2574 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2575 | } | |
2576 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2577 | { | |
2578 | /* Check byte pseudo registers last since this function will | |
2579 | be called from amd64_pseudo_register_read, which handles | |
2580 | byte pseudo registers differently. */ | |
2581 | int gpnum = regnum - tdep->al_regnum; | |
2582 | ||
2583 | /* Read ... We read both lower and upper registers. */ | |
2584 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2585 | /* ... Modify ... (always little endian). */ | |
2586 | if (gpnum >= 4) | |
2587 | memcpy (raw_buf + 1, buf, 1); | |
2588 | else | |
2589 | memcpy (raw_buf, buf, 1); | |
2590 | /* ... Write. */ | |
2591 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2592 | } | |
2593 | else | |
2594 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2595 | } | |
28fc6740 | 2596 | } |
ff2e87ac AC |
2597 | \f |
2598 | ||
ff2e87ac AC |
2599 | /* Return the register number of the register allocated by GCC after |
2600 | REGNUM, or -1 if there is no such register. */ | |
2601 | ||
2602 | static int | |
2603 | i386_next_regnum (int regnum) | |
2604 | { | |
2605 | /* GCC allocates the registers in the order: | |
2606 | ||
2607 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2608 | ||
2609 | Since storing a variable in %esp doesn't make any sense we return | |
2610 | -1 for %ebp and for %esp itself. */ | |
2611 | static int next_regnum[] = | |
2612 | { | |
2613 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2614 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2615 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2616 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2617 | -1, -1, /* Slots for %esp and %ebp. */ | |
2618 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2619 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2620 | }; | |
2621 | ||
de5b9bb9 | 2622 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2623 | return next_regnum[regnum]; |
28fc6740 | 2624 | |
ff2e87ac AC |
2625 | return -1; |
2626 | } | |
2627 | ||
2628 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2629 | needs any special handling. */ | |
d7a0d72c | 2630 | |
3a1e71e3 | 2631 | static int |
0abe36f5 | 2632 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2633 | { |
de5b9bb9 MK |
2634 | int len = TYPE_LENGTH (type); |
2635 | ||
ff2e87ac AC |
2636 | /* Values may be spread across multiple registers. Most debugging |
2637 | formats aren't expressive enough to specify the locations, so | |
2638 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2639 | have a length that is a multiple of the word size, since GCC |
2640 | doesn't seem to put any other types into registers. */ | |
2641 | if (len > 4 && len % 4 == 0) | |
2642 | { | |
2643 | int last_regnum = regnum; | |
2644 | ||
2645 | while (len > 4) | |
2646 | { | |
2647 | last_regnum = i386_next_regnum (last_regnum); | |
2648 | len -= 4; | |
2649 | } | |
2650 | ||
2651 | if (last_regnum != -1) | |
2652 | return 1; | |
2653 | } | |
ff2e87ac | 2654 | |
0abe36f5 | 2655 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2656 | } |
2657 | ||
ff2e87ac AC |
2658 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2659 | return its contents in TO. */ | |
ac27f131 | 2660 | |
3a1e71e3 | 2661 | static void |
ff2e87ac | 2662 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2663 | struct type *type, gdb_byte *to) |
ac27f131 | 2664 | { |
20a6ec49 | 2665 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2666 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2667 | |
ff2e87ac AC |
2668 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2669 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2670 | |
20a6ec49 | 2671 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2672 | { |
d532c08f MK |
2673 | i387_register_to_value (frame, regnum, type, to); |
2674 | return; | |
8d7f6b4a | 2675 | } |
ff2e87ac | 2676 | |
fd35795f | 2677 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2678 | |
2679 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2680 | |
de5b9bb9 MK |
2681 | while (len > 0) |
2682 | { | |
2683 | gdb_assert (regnum != -1); | |
20a6ec49 | 2684 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2685 | |
42835c2b | 2686 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2687 | regnum = i386_next_regnum (regnum); |
2688 | len -= 4; | |
42835c2b | 2689 | to += 4; |
de5b9bb9 | 2690 | } |
ac27f131 MK |
2691 | } |
2692 | ||
ff2e87ac AC |
2693 | /* Write the contents FROM of a value of type TYPE into register |
2694 | REGNUM in frame FRAME. */ | |
ac27f131 | 2695 | |
3a1e71e3 | 2696 | static void |
ff2e87ac | 2697 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2698 | struct type *type, const gdb_byte *from) |
ac27f131 | 2699 | { |
de5b9bb9 | 2700 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2701 | |
20a6ec49 | 2702 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2703 | { |
d532c08f MK |
2704 | i387_value_to_register (frame, regnum, type, from); |
2705 | return; | |
2706 | } | |
3d261580 | 2707 | |
fd35795f | 2708 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2709 | |
2710 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2711 | |
de5b9bb9 MK |
2712 | while (len > 0) |
2713 | { | |
2714 | gdb_assert (regnum != -1); | |
875f8d0e | 2715 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2716 | |
42835c2b | 2717 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2718 | regnum = i386_next_regnum (regnum); |
2719 | len -= 4; | |
42835c2b | 2720 | from += 4; |
de5b9bb9 | 2721 | } |
ac27f131 | 2722 | } |
ff2e87ac | 2723 | \f |
7fdafb5a MK |
2724 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2725 | in the general-purpose register set REGSET to register cache | |
2726 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2727 | |
20187ed5 | 2728 | void |
473f17b0 MK |
2729 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2730 | int regnum, const void *gregs, size_t len) | |
2731 | { | |
9ea75c57 | 2732 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2733 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2734 | int i; |
2735 | ||
2736 | gdb_assert (len == tdep->sizeof_gregset); | |
2737 | ||
2738 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2739 | { | |
2740 | if ((regnum == i || regnum == -1) | |
2741 | && tdep->gregset_reg_offset[i] != -1) | |
2742 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2743 | } | |
2744 | } | |
2745 | ||
7fdafb5a MK |
2746 | /* Collect register REGNUM from the register cache REGCACHE and store |
2747 | it in the buffer specified by GREGS and LEN as described by the | |
2748 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2749 | all registers in REGSET. */ | |
2750 | ||
2751 | void | |
2752 | i386_collect_gregset (const struct regset *regset, | |
2753 | const struct regcache *regcache, | |
2754 | int regnum, void *gregs, size_t len) | |
2755 | { | |
2756 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2757 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2758 | int i; |
2759 | ||
2760 | gdb_assert (len == tdep->sizeof_gregset); | |
2761 | ||
2762 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2763 | { | |
2764 | if ((regnum == i || regnum == -1) | |
2765 | && tdep->gregset_reg_offset[i] != -1) | |
2766 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2767 | } | |
2768 | } | |
2769 | ||
2770 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2771 | in the floating-point register set REGSET to register cache | |
2772 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2773 | |
2774 | static void | |
2775 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2776 | int regnum, const void *fpregs, size_t len) | |
2777 | { | |
9ea75c57 | 2778 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2779 | |
66a72d25 MK |
2780 | if (len == I387_SIZEOF_FXSAVE) |
2781 | { | |
2782 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2783 | return; | |
2784 | } | |
2785 | ||
473f17b0 MK |
2786 | gdb_assert (len == tdep->sizeof_fpregset); |
2787 | i387_supply_fsave (regcache, regnum, fpregs); | |
2788 | } | |
8446b36a | 2789 | |
2f305df1 MK |
2790 | /* Collect register REGNUM from the register cache REGCACHE and store |
2791 | it in the buffer specified by FPREGS and LEN as described by the | |
2792 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2793 | all registers in REGSET. */ | |
7fdafb5a MK |
2794 | |
2795 | static void | |
2796 | i386_collect_fpregset (const struct regset *regset, | |
2797 | const struct regcache *regcache, | |
2798 | int regnum, void *fpregs, size_t len) | |
2799 | { | |
2800 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2801 | ||
2802 | if (len == I387_SIZEOF_FXSAVE) | |
2803 | { | |
2804 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2805 | return; | |
2806 | } | |
2807 | ||
2808 | gdb_assert (len == tdep->sizeof_fpregset); | |
2809 | i387_collect_fsave (regcache, regnum, fpregs); | |
2810 | } | |
2811 | ||
c131fcee L |
2812 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
2813 | ||
2814 | static void | |
2815 | i386_supply_xstateregset (const struct regset *regset, | |
2816 | struct regcache *regcache, int regnum, | |
2817 | const void *xstateregs, size_t len) | |
2818 | { | |
c131fcee L |
2819 | i387_supply_xsave (regcache, regnum, xstateregs); |
2820 | } | |
2821 | ||
2822 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
2823 | ||
2824 | static void | |
2825 | i386_collect_xstateregset (const struct regset *regset, | |
2826 | const struct regcache *regcache, | |
2827 | int regnum, void *xstateregs, size_t len) | |
2828 | { | |
c131fcee L |
2829 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
2830 | } | |
2831 | ||
8446b36a MK |
2832 | /* Return the appropriate register set for the core section identified |
2833 | by SECT_NAME and SECT_SIZE. */ | |
2834 | ||
2835 | const struct regset * | |
2836 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2837 | const char *sect_name, size_t sect_size) | |
2838 | { | |
2839 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2840 | ||
2841 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2842 | { | |
2843 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2844 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2845 | i386_collect_gregset); | |
8446b36a MK |
2846 | return tdep->gregset; |
2847 | } | |
2848 | ||
66a72d25 MK |
2849 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2850 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2851 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2852 | { |
2853 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2854 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2855 | i386_collect_fpregset); | |
8446b36a MK |
2856 | return tdep->fpregset; |
2857 | } | |
2858 | ||
c131fcee L |
2859 | if (strcmp (sect_name, ".reg-xstate") == 0) |
2860 | { | |
2861 | if (tdep->xstateregset == NULL) | |
2862 | tdep->xstateregset = regset_alloc (gdbarch, | |
2863 | i386_supply_xstateregset, | |
2864 | i386_collect_xstateregset); | |
2865 | ||
2866 | return tdep->xstateregset; | |
2867 | } | |
2868 | ||
8446b36a MK |
2869 | return NULL; |
2870 | } | |
473f17b0 | 2871 | \f |
fc338970 | 2872 | |
fc338970 | 2873 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2874 | |
2875 | CORE_ADDR | |
e17a4113 UW |
2876 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2877 | CORE_ADDR pc, char *name) | |
c906108c | 2878 | { |
e17a4113 UW |
2879 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2880 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2881 | ||
2882 | /* jmp *(dest) */ | |
2883 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2884 | { |
e17a4113 UW |
2885 | unsigned long indirect = |
2886 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2887 | struct minimal_symbol *indsym = |
fc338970 | 2888 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2889 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2890 | |
c5aa993b | 2891 | if (symname) |
c906108c | 2892 | { |
c5aa993b JM |
2893 | if (strncmp (symname, "__imp_", 6) == 0 |
2894 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2895 | return name ? 1 : |
2896 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2897 | } |
2898 | } | |
fc338970 | 2899 | return 0; /* Not a trampoline. */ |
c906108c | 2900 | } |
fc338970 MK |
2901 | \f |
2902 | ||
10458914 DJ |
2903 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2904 | routine. */ | |
8201327c | 2905 | |
4bd207ef | 2906 | int |
10458914 | 2907 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2908 | { |
10458914 | 2909 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2910 | char *name; |
2911 | ||
2912 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2913 | return (name && strcmp ("_sigtramp", name) == 0); |
2914 | } | |
2915 | \f | |
2916 | ||
fc338970 MK |
2917 | /* We have two flavours of disassembly. The machinery on this page |
2918 | deals with switching between those. */ | |
c906108c SS |
2919 | |
2920 | static int | |
a89aa300 | 2921 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2922 | { |
5e3397bb MK |
2923 | gdb_assert (disassembly_flavor == att_flavor |
2924 | || disassembly_flavor == intel_flavor); | |
2925 | ||
2926 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2927 | constified, cast to prevent a compiler warning. */ | |
2928 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2929 | |
2930 | return print_insn_i386 (pc, info); | |
7a292a7a | 2931 | } |
fc338970 | 2932 | \f |
3ce1502b | 2933 | |
8201327c MK |
2934 | /* There are a few i386 architecture variants that differ only |
2935 | slightly from the generic i386 target. For now, we don't give them | |
2936 | their own source file, but include them here. As a consequence, | |
2937 | they'll always be included. */ | |
3ce1502b | 2938 | |
8201327c | 2939 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2940 | |
10458914 DJ |
2941 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2942 | routine. */ | |
911bc6ee | 2943 | |
8201327c | 2944 | static int |
10458914 | 2945 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2946 | { |
10458914 | 2947 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2948 | char *name; |
2949 | ||
acd5c798 MK |
2950 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2951 | currently unknown. */ | |
911bc6ee | 2952 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2953 | return (name && (strcmp ("_sigreturn", name) == 0 |
2954 | || strcmp ("_sigacthandler", name) == 0 | |
2955 | || strcmp ("sigvechandler", name) == 0)); | |
2956 | } | |
d2a7c97a | 2957 | |
10458914 DJ |
2958 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2959 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2960 | |
3a1e71e3 | 2961 | static CORE_ADDR |
10458914 | 2962 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2963 | { |
e17a4113 UW |
2964 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2965 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2966 | gdb_byte buf[4]; |
acd5c798 | 2967 | CORE_ADDR sp; |
3ce1502b | 2968 | |
10458914 | 2969 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2970 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2971 | |
e17a4113 | 2972 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2973 | } |
2974 | \f | |
3ce1502b | 2975 | |
8201327c | 2976 | /* Generic ELF. */ |
d2a7c97a | 2977 | |
8201327c MK |
2978 | void |
2979 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2980 | { | |
c4fc7f1b MK |
2981 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2982 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2983 | } |
3ce1502b | 2984 | |
8201327c | 2985 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2986 | |
8201327c MK |
2987 | void |
2988 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2989 | { | |
2990 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2991 | |
8201327c MK |
2992 | /* System V Release 4 uses ELF. */ |
2993 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2994 | |
dfe01d39 | 2995 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2996 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2997 | ||
911bc6ee | 2998 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2999 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3000 | tdep->sc_pc_offset = 36 + 14 * 4; |
3001 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3002 | |
8201327c | 3003 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3004 | } |
3005 | ||
8201327c | 3006 | /* DJGPP. */ |
3ce1502b | 3007 | |
3a1e71e3 | 3008 | static void |
8201327c | 3009 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3010 | { |
8201327c | 3011 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3012 | |
911bc6ee MK |
3013 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3014 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3015 | |
8201327c | 3016 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3017 | |
3018 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3019 | if (! tdesc_has_registers (info.target_desc)) |
3020 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3021 | |
3022 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3023 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3024 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3025 | set_gdbarch_sdb_reg_to_regnum. */ | |
3026 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3027 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3028 | |
3029 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3030 | } |
8201327c | 3031 | \f |
2acceee2 | 3032 | |
38c968cf AC |
3033 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3034 | and "sse". */ | |
3035 | ||
3036 | static struct reggroup *i386_sse_reggroup; | |
3037 | static struct reggroup *i386_mmx_reggroup; | |
3038 | ||
3039 | static void | |
3040 | i386_init_reggroups (void) | |
3041 | { | |
3042 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3043 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3044 | } | |
3045 | ||
3046 | static void | |
3047 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3048 | { | |
3049 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3050 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3051 | reggroup_add (gdbarch, general_reggroup); | |
3052 | reggroup_add (gdbarch, float_reggroup); | |
3053 | reggroup_add (gdbarch, all_reggroup); | |
3054 | reggroup_add (gdbarch, save_reggroup); | |
3055 | reggroup_add (gdbarch, restore_reggroup); | |
3056 | reggroup_add (gdbarch, vector_reggroup); | |
3057 | reggroup_add (gdbarch, system_reggroup); | |
3058 | } | |
3059 | ||
3060 | int | |
3061 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3062 | struct reggroup *group) | |
3063 | { | |
c131fcee L |
3064 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3065 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3066 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3067 | |
1ba53b71 L |
3068 | /* Don't include pseudo registers, except for MMX, in any register |
3069 | groups. */ | |
c131fcee | 3070 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3071 | return 0; |
3072 | ||
c131fcee | 3073 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3074 | return 0; |
3075 | ||
c131fcee | 3076 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3077 | return 0; |
3078 | ||
3079 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3080 | if (group == i386_mmx_reggroup) |
3081 | return mmx_regnum_p; | |
1ba53b71 | 3082 | |
c131fcee L |
3083 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3084 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3085 | if (group == i386_sse_reggroup) |
c131fcee L |
3086 | return xmm_regnum_p || mxcsr_regnum_p; |
3087 | ||
3088 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3089 | if (group == vector_reggroup) |
c131fcee L |
3090 | return (mmx_regnum_p |
3091 | || ymm_regnum_p | |
3092 | || mxcsr_regnum_p | |
3093 | || (xmm_regnum_p | |
3094 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3095 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3096 | |
3097 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3098 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3099 | if (group == float_reggroup) |
3100 | return fp_regnum_p; | |
1ba53b71 | 3101 | |
c131fcee L |
3102 | /* For "info reg all", don't include upper YMM registers nor XMM |
3103 | registers when AVX is supported. */ | |
3104 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3105 | if (group == all_reggroup | |
3106 | && ((xmm_regnum_p | |
3107 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3108 | || ymmh_regnum_p)) | |
3109 | return 0; | |
3110 | ||
38c968cf | 3111 | if (group == general_reggroup) |
1ba53b71 L |
3112 | return (!fp_regnum_p |
3113 | && !mmx_regnum_p | |
c131fcee L |
3114 | && !mxcsr_regnum_p |
3115 | && !xmm_regnum_p | |
3116 | && !ymm_regnum_p | |
3117 | && !ymmh_regnum_p); | |
acd5c798 | 3118 | |
38c968cf AC |
3119 | return default_register_reggroup_p (gdbarch, regnum, group); |
3120 | } | |
38c968cf | 3121 | \f |
acd5c798 | 3122 | |
f837910f MK |
3123 | /* Get the ARGIth function argument for the current function. */ |
3124 | ||
42c466d7 | 3125 | static CORE_ADDR |
143985b7 AF |
3126 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3127 | struct type *type) | |
3128 | { | |
e17a4113 UW |
3129 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3130 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 3131 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3132 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3133 | } |
3134 | ||
514f746b AR |
3135 | static void |
3136 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3137 | { | |
3138 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3139 | ||
3140 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3141 | adjust the PC in the regcache. */ | |
3142 | current_pc += 1; | |
3143 | regcache_write_pc (regcache, current_pc); | |
3144 | } | |
3145 | ||
3146 | ||
7ad10968 HZ |
3147 | #define PREFIX_REPZ 0x01 |
3148 | #define PREFIX_REPNZ 0x02 | |
3149 | #define PREFIX_LOCK 0x04 | |
3150 | #define PREFIX_DATA 0x08 | |
3151 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3152 | |
7ad10968 HZ |
3153 | /* operand size */ |
3154 | enum | |
3155 | { | |
3156 | OT_BYTE = 0, | |
3157 | OT_WORD, | |
3158 | OT_LONG, | |
cf648174 | 3159 | OT_QUAD, |
a3c4230a | 3160 | OT_DQUAD, |
7ad10968 | 3161 | }; |
473f17b0 | 3162 | |
7ad10968 HZ |
3163 | /* i386 arith/logic operations */ |
3164 | enum | |
3165 | { | |
3166 | OP_ADDL, | |
3167 | OP_ORL, | |
3168 | OP_ADCL, | |
3169 | OP_SBBL, | |
3170 | OP_ANDL, | |
3171 | OP_SUBL, | |
3172 | OP_XORL, | |
3173 | OP_CMPL, | |
3174 | }; | |
5716833c | 3175 | |
7ad10968 HZ |
3176 | struct i386_record_s |
3177 | { | |
cf648174 | 3178 | struct gdbarch *gdbarch; |
7ad10968 | 3179 | struct regcache *regcache; |
df61f520 | 3180 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3181 | CORE_ADDR addr; |
3182 | int aflag; | |
3183 | int dflag; | |
3184 | int override; | |
3185 | uint8_t modrm; | |
3186 | uint8_t mod, reg, rm; | |
3187 | int ot; | |
cf648174 HZ |
3188 | uint8_t rex_x; |
3189 | uint8_t rex_b; | |
3190 | int rip_offset; | |
3191 | int popl_esp_hack; | |
3192 | const int *regmap; | |
7ad10968 | 3193 | }; |
5716833c | 3194 | |
7ad10968 HZ |
3195 | /* Parse "modrm" part in current memory address that irp->addr point to |
3196 | Return -1 if something wrong. */ | |
5716833c | 3197 | |
7ad10968 HZ |
3198 | static int |
3199 | i386_record_modrm (struct i386_record_s *irp) | |
3200 | { | |
cf648174 | 3201 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3202 | |
7ad10968 HZ |
3203 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3204 | { | |
3205 | if (record_debug) | |
3206 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3207 | "addr %s len = 1.\n"), |
3208 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3209 | return -1; |
3210 | } | |
3211 | irp->addr++; | |
3212 | irp->mod = (irp->modrm >> 6) & 3; | |
3213 | irp->reg = (irp->modrm >> 3) & 7; | |
3214 | irp->rm = irp->modrm & 7; | |
5716833c | 3215 | |
7ad10968 HZ |
3216 | return 0; |
3217 | } | |
d2a7c97a | 3218 | |
7ad10968 HZ |
3219 | /* Get the memory address that current instruction write to and set it to |
3220 | the argument "addr". | |
3221 | Return -1 if something wrong. */ | |
8201327c | 3222 | |
7ad10968 | 3223 | static int |
cf648174 | 3224 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3225 | { |
cf648174 | 3226 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3227 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3228 | gdb_byte buf[4]; | |
3229 | ULONGEST offset64; | |
21d0e8a4 | 3230 | |
7ad10968 HZ |
3231 | *addr = 0; |
3232 | if (irp->aflag) | |
3233 | { | |
3234 | /* 32 bits */ | |
3235 | int havesib = 0; | |
3236 | uint8_t scale = 0; | |
648d0c8b | 3237 | uint8_t byte; |
7ad10968 HZ |
3238 | uint8_t index = 0; |
3239 | uint8_t base = irp->rm; | |
896fb97d | 3240 | |
7ad10968 HZ |
3241 | if (base == 4) |
3242 | { | |
3243 | havesib = 1; | |
648d0c8b | 3244 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3245 | { |
3246 | if (record_debug) | |
3247 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3248 | "at addr %s len = 1.\n"), |
3249 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3250 | return -1; |
3251 | } | |
3252 | irp->addr++; | |
648d0c8b MS |
3253 | scale = (byte >> 6) & 3; |
3254 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3255 | base = (byte & 7); | |
7ad10968 | 3256 | } |
cf648174 | 3257 | base |= irp->rex_b; |
21d0e8a4 | 3258 | |
7ad10968 HZ |
3259 | switch (irp->mod) |
3260 | { | |
3261 | case 0: | |
3262 | if ((base & 7) == 5) | |
3263 | { | |
3264 | base = 0xff; | |
60a1502a | 3265 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3266 | { |
3267 | if (record_debug) | |
3268 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3269 | "memory at addr %s len = 4.\n"), |
3270 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3271 | return -1; |
3272 | } | |
3273 | irp->addr += 4; | |
60a1502a | 3274 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3275 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3276 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 3277 | } |
7ad10968 HZ |
3278 | break; |
3279 | case 1: | |
60a1502a | 3280 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3281 | { |
3282 | if (record_debug) | |
3283 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3284 | "at addr %s len = 1.\n"), |
3285 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3286 | return -1; |
3287 | } | |
3288 | irp->addr++; | |
60a1502a | 3289 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3290 | break; |
3291 | case 2: | |
60a1502a | 3292 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3293 | { |
3294 | if (record_debug) | |
3295 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3296 | "at addr %s len = 4.\n"), |
3297 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3298 | return -1; |
3299 | } | |
60a1502a | 3300 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3301 | irp->addr += 4; |
3302 | break; | |
3303 | } | |
356a6b3e | 3304 | |
60a1502a | 3305 | offset64 = 0; |
7ad10968 | 3306 | if (base != 0xff) |
cf648174 HZ |
3307 | { |
3308 | if (base == 4 && irp->popl_esp_hack) | |
3309 | *addr += irp->popl_esp_hack; | |
3310 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3311 | &offset64); |
7ad10968 | 3312 | } |
cf648174 HZ |
3313 | if (irp->aflag == 2) |
3314 | { | |
60a1502a | 3315 | *addr += offset64; |
cf648174 HZ |
3316 | } |
3317 | else | |
60a1502a | 3318 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3319 | |
7ad10968 HZ |
3320 | if (havesib && (index != 4 || scale != 0)) |
3321 | { | |
cf648174 | 3322 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3323 | &offset64); |
cf648174 | 3324 | if (irp->aflag == 2) |
60a1502a | 3325 | *addr += offset64 << scale; |
cf648174 | 3326 | else |
60a1502a | 3327 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3328 | } |
3329 | } | |
3330 | else | |
3331 | { | |
3332 | /* 16 bits */ | |
3333 | switch (irp->mod) | |
3334 | { | |
3335 | case 0: | |
3336 | if (irp->rm == 6) | |
3337 | { | |
60a1502a | 3338 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3339 | { |
3340 | if (record_debug) | |
3341 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3342 | "memory at addr %s len = 2.\n"), |
3343 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3344 | return -1; |
3345 | } | |
3346 | irp->addr += 2; | |
60a1502a | 3347 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3348 | irp->rm = 0; |
3349 | goto no_rm; | |
3350 | } | |
7ad10968 HZ |
3351 | break; |
3352 | case 1: | |
60a1502a | 3353 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3354 | { |
3355 | if (record_debug) | |
3356 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3357 | "at addr %s len = 1.\n"), |
3358 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3359 | return -1; |
3360 | } | |
3361 | irp->addr++; | |
60a1502a | 3362 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3363 | break; |
3364 | case 2: | |
60a1502a | 3365 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3366 | { |
3367 | if (record_debug) | |
3368 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3369 | "at addr %s len = 2.\n"), |
3370 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3371 | return -1; |
3372 | } | |
3373 | irp->addr += 2; | |
60a1502a | 3374 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3375 | break; |
3376 | } | |
c4fc7f1b | 3377 | |
7ad10968 HZ |
3378 | switch (irp->rm) |
3379 | { | |
3380 | case 0: | |
cf648174 HZ |
3381 | regcache_raw_read_unsigned (irp->regcache, |
3382 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3383 | &offset64); |
3384 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3385 | regcache_raw_read_unsigned (irp->regcache, |
3386 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3387 | &offset64); |
3388 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3389 | break; |
3390 | case 1: | |
cf648174 HZ |
3391 | regcache_raw_read_unsigned (irp->regcache, |
3392 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3393 | &offset64); |
3394 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3395 | regcache_raw_read_unsigned (irp->regcache, |
3396 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3397 | &offset64); |
3398 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3399 | break; |
3400 | case 2: | |
cf648174 HZ |
3401 | regcache_raw_read_unsigned (irp->regcache, |
3402 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3403 | &offset64); |
3404 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3405 | regcache_raw_read_unsigned (irp->regcache, |
3406 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3407 | &offset64); |
3408 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3409 | break; |
3410 | case 3: | |
cf648174 HZ |
3411 | regcache_raw_read_unsigned (irp->regcache, |
3412 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3413 | &offset64); |
3414 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3415 | regcache_raw_read_unsigned (irp->regcache, |
3416 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3417 | &offset64); |
3418 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3419 | break; |
3420 | case 4: | |
cf648174 HZ |
3421 | regcache_raw_read_unsigned (irp->regcache, |
3422 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3423 | &offset64); |
3424 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3425 | break; |
3426 | case 5: | |
cf648174 HZ |
3427 | regcache_raw_read_unsigned (irp->regcache, |
3428 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3429 | &offset64); |
3430 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3431 | break; |
3432 | case 6: | |
cf648174 HZ |
3433 | regcache_raw_read_unsigned (irp->regcache, |
3434 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3435 | &offset64); |
3436 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3437 | break; |
3438 | case 7: | |
cf648174 HZ |
3439 | regcache_raw_read_unsigned (irp->regcache, |
3440 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3441 | &offset64); |
3442 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3443 | break; |
3444 | } | |
3445 | *addr &= 0xffff; | |
3446 | } | |
c4fc7f1b | 3447 | |
01fe1b41 | 3448 | no_rm: |
7ad10968 HZ |
3449 | return 0; |
3450 | } | |
c4fc7f1b | 3451 | |
7ad10968 HZ |
3452 | /* Record the value of the memory that willbe changed in current instruction |
3453 | to "record_arch_list". | |
3454 | Return -1 if something wrong. */ | |
356a6b3e | 3455 | |
7ad10968 HZ |
3456 | static int |
3457 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3458 | { | |
cf648174 HZ |
3459 | struct gdbarch *gdbarch = irp->gdbarch; |
3460 | uint64_t addr; | |
356a6b3e | 3461 | |
d7877f7e | 3462 | if (irp->override >= 0) |
7ad10968 | 3463 | { |
df61f520 HZ |
3464 | warning (_("Process record ignores the memory change " |
3465 | "of instruction at address %s because it " | |
3466 | "can't get the value of the segment register."), | |
3467 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3468 | return 0; |
3469 | } | |
61113f8b | 3470 | |
7ad10968 HZ |
3471 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3472 | return -1; | |
96297dab | 3473 | |
7ad10968 HZ |
3474 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3475 | return -1; | |
a62cc96e | 3476 | |
7ad10968 HZ |
3477 | return 0; |
3478 | } | |
b6197528 | 3479 | |
cf648174 HZ |
3480 | /* Record the push operation to "record_arch_list". |
3481 | Return -1 if something wrong. */ | |
3482 | ||
3483 | static int | |
3484 | i386_record_push (struct i386_record_s *irp, int size) | |
3485 | { | |
648d0c8b | 3486 | ULONGEST addr; |
cf648174 HZ |
3487 | |
3488 | if (record_arch_list_add_reg (irp->regcache, | |
3489 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3490 | return -1; | |
3491 | regcache_raw_read_unsigned (irp->regcache, | |
3492 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3493 | &addr); |
3494 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3495 | return -1; |
3496 | ||
3497 | return 0; | |
3498 | } | |
3499 | ||
0289bdd7 MS |
3500 | |
3501 | /* Defines contents to record. */ | |
3502 | #define I386_SAVE_FPU_REGS 0xfffd | |
3503 | #define I386_SAVE_FPU_ENV 0xfffe | |
3504 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3505 | ||
3506 | /* Record the value of floating point registers which will be changed by the | |
3507 | current instruction to "record_arch_list". Return -1 if something is wrong. | |
3508 | */ | |
3509 | ||
3510 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3511 | struct i386_record_s *ir, | |
3512 | uint32_t iregnum) | |
3513 | { | |
3514 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3515 | int i; | |
3516 | ||
3517 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3518 | happen. Currently we store st0-st7 registers, but we need not store all | |
3519 | registers all the time, in future we use ftag register and record only | |
3520 | those who are not marked as an empty. */ | |
3521 | ||
3522 | if (I386_SAVE_FPU_REGS == iregnum) | |
3523 | { | |
3524 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3525 | { | |
3526 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3527 | return -1; | |
3528 | } | |
3529 | } | |
3530 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3531 | { | |
3532 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3533 | { | |
3534 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3535 | return -1; | |
3536 | } | |
3537 | } | |
3538 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3539 | { | |
3540 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3541 | { | |
3542 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3543 | return -1; | |
3544 | } | |
3545 | } | |
3546 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3547 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3548 | { | |
3549 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3550 | return -1; | |
3551 | } | |
3552 | else | |
3553 | { | |
3554 | /* Parameter error. */ | |
3555 | return -1; | |
3556 | } | |
3557 | if(I386_SAVE_FPU_ENV != iregnum) | |
3558 | { | |
3559 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3560 | { | |
3561 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3562 | return -1; | |
3563 | } | |
3564 | } | |
3565 | return 0; | |
3566 | } | |
3567 | ||
7ad10968 HZ |
3568 | /* Parse the current instruction and record the values of the registers and |
3569 | memory that will be changed in current instruction to "record_arch_list". | |
3570 | Return -1 if something wrong. */ | |
8201327c | 3571 | |
cf648174 HZ |
3572 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3573 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3574 | ||
a6b808b4 | 3575 | int |
7ad10968 | 3576 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3577 | CORE_ADDR input_addr) |
7ad10968 | 3578 | { |
60a1502a | 3579 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3580 | int prefixes = 0; |
580879fc | 3581 | int regnum = 0; |
425b824a MS |
3582 | uint32_t opcode; |
3583 | uint8_t opcode8; | |
648d0c8b | 3584 | ULONGEST addr; |
60a1502a | 3585 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3586 | struct i386_record_s ir; |
0289bdd7 | 3587 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3588 | int rex = 0; |
3589 | uint8_t rex_w = -1; | |
3590 | uint8_t rex_r = 0; | |
7ad10968 | 3591 | |
8408d274 | 3592 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3593 | ir.regcache = regcache; |
648d0c8b MS |
3594 | ir.addr = input_addr; |
3595 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3596 | ir.aflag = 1; |
3597 | ir.dflag = 1; | |
cf648174 HZ |
3598 | ir.override = -1; |
3599 | ir.popl_esp_hack = 0; | |
a3c4230a | 3600 | ir.regmap = tdep->record_regmap; |
cf648174 | 3601 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
3602 | |
3603 | if (record_debug > 1) | |
3604 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3605 | "addr = %s\n", |
3606 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3607 | |
3608 | /* prefixes */ | |
3609 | while (1) | |
3610 | { | |
425b824a | 3611 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3612 | { |
3613 | if (record_debug) | |
3614 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3615 | "addr %s len = 1.\n"), |
3616 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3617 | return -1; |
3618 | } | |
3619 | ir.addr++; | |
425b824a | 3620 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 3621 | { |
01fe1b41 | 3622 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3623 | prefixes |= PREFIX_REPZ; |
3624 | break; | |
01fe1b41 | 3625 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3626 | prefixes |= PREFIX_REPNZ; |
3627 | break; | |
01fe1b41 | 3628 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3629 | prefixes |= PREFIX_LOCK; |
3630 | break; | |
01fe1b41 | 3631 | case CS_PREFIX_OPCODE: |
cf648174 | 3632 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3633 | break; |
01fe1b41 | 3634 | case SS_PREFIX_OPCODE: |
cf648174 | 3635 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3636 | break; |
01fe1b41 | 3637 | case DS_PREFIX_OPCODE: |
cf648174 | 3638 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3639 | break; |
01fe1b41 | 3640 | case ES_PREFIX_OPCODE: |
cf648174 | 3641 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3642 | break; |
01fe1b41 | 3643 | case FS_PREFIX_OPCODE: |
cf648174 | 3644 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3645 | break; |
01fe1b41 | 3646 | case GS_PREFIX_OPCODE: |
cf648174 | 3647 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3648 | break; |
01fe1b41 | 3649 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3650 | prefixes |= PREFIX_DATA; |
3651 | break; | |
01fe1b41 | 3652 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3653 | prefixes |= PREFIX_ADDR; |
3654 | break; | |
d691bec7 MS |
3655 | case 0x40: /* i386 inc %eax */ |
3656 | case 0x41: /* i386 inc %ecx */ | |
3657 | case 0x42: /* i386 inc %edx */ | |
3658 | case 0x43: /* i386 inc %ebx */ | |
3659 | case 0x44: /* i386 inc %esp */ | |
3660 | case 0x45: /* i386 inc %ebp */ | |
3661 | case 0x46: /* i386 inc %esi */ | |
3662 | case 0x47: /* i386 inc %edi */ | |
3663 | case 0x48: /* i386 dec %eax */ | |
3664 | case 0x49: /* i386 dec %ecx */ | |
3665 | case 0x4a: /* i386 dec %edx */ | |
3666 | case 0x4b: /* i386 dec %ebx */ | |
3667 | case 0x4c: /* i386 dec %esp */ | |
3668 | case 0x4d: /* i386 dec %ebp */ | |
3669 | case 0x4e: /* i386 dec %esi */ | |
3670 | case 0x4f: /* i386 dec %edi */ | |
3671 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3672 | { |
3673 | /* REX */ | |
3674 | rex = 1; | |
425b824a MS |
3675 | rex_w = (opcode8 >> 3) & 1; |
3676 | rex_r = (opcode8 & 0x4) << 1; | |
3677 | ir.rex_x = (opcode8 & 0x2) << 2; | |
3678 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 3679 | } |
d691bec7 MS |
3680 | else /* 32 bit target */ |
3681 | goto out_prefixes; | |
cf648174 | 3682 | break; |
7ad10968 HZ |
3683 | default: |
3684 | goto out_prefixes; | |
3685 | break; | |
3686 | } | |
3687 | } | |
01fe1b41 | 3688 | out_prefixes: |
cf648174 HZ |
3689 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3690 | { | |
3691 | ir.dflag = 2; | |
3692 | } | |
3693 | else | |
3694 | { | |
3695 | if (prefixes & PREFIX_DATA) | |
3696 | ir.dflag ^= 1; | |
3697 | } | |
7ad10968 HZ |
3698 | if (prefixes & PREFIX_ADDR) |
3699 | ir.aflag ^= 1; | |
cf648174 HZ |
3700 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3701 | ir.aflag = 2; | |
7ad10968 HZ |
3702 | |
3703 | /* now check op code */ | |
425b824a | 3704 | opcode = (uint32_t) opcode8; |
01fe1b41 | 3705 | reswitch: |
7ad10968 HZ |
3706 | switch (opcode) |
3707 | { | |
3708 | case 0x0f: | |
425b824a | 3709 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
3710 | { |
3711 | if (record_debug) | |
3712 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3713 | "addr %s len = 1.\n"), |
3714 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3715 | return -1; |
3716 | } | |
3717 | ir.addr++; | |
a3c4230a | 3718 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
3719 | goto reswitch; |
3720 | break; | |
93924b6b | 3721 | |
a38bba38 | 3722 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3723 | case 0x01: |
3724 | case 0x02: | |
3725 | case 0x03: | |
3726 | case 0x04: | |
3727 | case 0x05: | |
3728 | case 0x08: | |
3729 | case 0x09: | |
3730 | case 0x0a: | |
3731 | case 0x0b: | |
3732 | case 0x0c: | |
3733 | case 0x0d: | |
3734 | case 0x10: | |
3735 | case 0x11: | |
3736 | case 0x12: | |
3737 | case 0x13: | |
3738 | case 0x14: | |
3739 | case 0x15: | |
3740 | case 0x18: | |
3741 | case 0x19: | |
3742 | case 0x1a: | |
3743 | case 0x1b: | |
3744 | case 0x1c: | |
3745 | case 0x1d: | |
3746 | case 0x20: | |
3747 | case 0x21: | |
3748 | case 0x22: | |
3749 | case 0x23: | |
3750 | case 0x24: | |
3751 | case 0x25: | |
3752 | case 0x28: | |
3753 | case 0x29: | |
3754 | case 0x2a: | |
3755 | case 0x2b: | |
3756 | case 0x2c: | |
3757 | case 0x2d: | |
3758 | case 0x30: | |
3759 | case 0x31: | |
3760 | case 0x32: | |
3761 | case 0x33: | |
3762 | case 0x34: | |
3763 | case 0x35: | |
3764 | case 0x38: | |
3765 | case 0x39: | |
3766 | case 0x3a: | |
3767 | case 0x3b: | |
3768 | case 0x3c: | |
3769 | case 0x3d: | |
3770 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3771 | { | |
3772 | if ((opcode & 1) == 0) | |
3773 | ir.ot = OT_BYTE; | |
3774 | else | |
3775 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3776 | |
7ad10968 HZ |
3777 | switch ((opcode >> 1) & 3) |
3778 | { | |
a38bba38 | 3779 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3780 | if (i386_record_modrm (&ir)) |
3781 | return -1; | |
3782 | if (ir.mod != 3) | |
3783 | { | |
3784 | if (i386_record_lea_modrm (&ir)) | |
3785 | return -1; | |
3786 | } | |
3787 | else | |
3788 | { | |
cf648174 HZ |
3789 | ir.rm |= ir.rex_b; |
3790 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3791 | ir.rm &= 0x3; |
cf648174 | 3792 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3793 | } |
3794 | break; | |
a38bba38 | 3795 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3796 | if (i386_record_modrm (&ir)) |
3797 | return -1; | |
cf648174 HZ |
3798 | ir.reg |= rex_r; |
3799 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3800 | ir.reg &= 0x3; |
cf648174 | 3801 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3802 | break; |
a38bba38 | 3803 | case 2: /* OP A, Iv */ |
cf648174 | 3804 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3805 | break; |
3806 | } | |
3807 | } | |
cf648174 | 3808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3809 | break; |
42fdc8df | 3810 | |
a38bba38 | 3811 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3812 | case 0x81: |
3813 | case 0x82: | |
3814 | case 0x83: | |
3815 | if (i386_record_modrm (&ir)) | |
3816 | return -1; | |
8201327c | 3817 | |
7ad10968 HZ |
3818 | if (ir.reg != OP_CMPL) |
3819 | { | |
3820 | if ((opcode & 1) == 0) | |
3821 | ir.ot = OT_BYTE; | |
3822 | else | |
3823 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3824 | |
7ad10968 HZ |
3825 | if (ir.mod != 3) |
3826 | { | |
cf648174 HZ |
3827 | if (opcode == 0x83) |
3828 | ir.rip_offset = 1; | |
3829 | else | |
3830 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3831 | if (i386_record_lea_modrm (&ir)) |
3832 | return -1; | |
3833 | } | |
3834 | else | |
cf648174 | 3835 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3836 | } |
cf648174 | 3837 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3838 | break; |
5e3397bb | 3839 | |
a38bba38 | 3840 | case 0x40: /* inc */ |
7ad10968 HZ |
3841 | case 0x41: |
3842 | case 0x42: | |
3843 | case 0x43: | |
3844 | case 0x44: | |
3845 | case 0x45: | |
3846 | case 0x46: | |
3847 | case 0x47: | |
a38bba38 MS |
3848 | |
3849 | case 0x48: /* dec */ | |
7ad10968 HZ |
3850 | case 0x49: |
3851 | case 0x4a: | |
3852 | case 0x4b: | |
3853 | case 0x4c: | |
3854 | case 0x4d: | |
3855 | case 0x4e: | |
3856 | case 0x4f: | |
a38bba38 | 3857 | |
cf648174 HZ |
3858 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3859 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3860 | break; |
acd5c798 | 3861 | |
a38bba38 | 3862 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3863 | case 0xf7: |
3864 | if ((opcode & 1) == 0) | |
3865 | ir.ot = OT_BYTE; | |
3866 | else | |
3867 | ir.ot = ir.dflag + OT_WORD; | |
3868 | if (i386_record_modrm (&ir)) | |
3869 | return -1; | |
acd5c798 | 3870 | |
cf648174 HZ |
3871 | if (ir.mod != 3 && ir.reg == 0) |
3872 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3873 | ||
7ad10968 HZ |
3874 | switch (ir.reg) |
3875 | { | |
a38bba38 | 3876 | case 0: /* test */ |
cf648174 | 3877 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3878 | break; |
a38bba38 MS |
3879 | case 2: /* not */ |
3880 | case 3: /* neg */ | |
7ad10968 HZ |
3881 | if (ir.mod != 3) |
3882 | { | |
3883 | if (i386_record_lea_modrm (&ir)) | |
3884 | return -1; | |
3885 | } | |
3886 | else | |
3887 | { | |
cf648174 HZ |
3888 | ir.rm |= ir.rex_b; |
3889 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3890 | ir.rm &= 0x3; |
cf648174 | 3891 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3892 | } |
a38bba38 | 3893 | if (ir.reg == 3) /* neg */ |
cf648174 | 3894 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3895 | break; |
a38bba38 MS |
3896 | case 4: /* mul */ |
3897 | case 5: /* imul */ | |
3898 | case 6: /* div */ | |
3899 | case 7: /* idiv */ | |
cf648174 | 3900 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3901 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3902 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3903 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3904 | break; |
3905 | default: | |
3906 | ir.addr -= 2; | |
3907 | opcode = opcode << 8 | ir.modrm; | |
3908 | goto no_support; | |
3909 | break; | |
3910 | } | |
3911 | break; | |
3912 | ||
a38bba38 MS |
3913 | case 0xfe: /* GRP4 */ |
3914 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
3915 | if (i386_record_modrm (&ir)) |
3916 | return -1; | |
3917 | if (ir.reg >= 2 && opcode == 0xfe) | |
3918 | { | |
3919 | ir.addr -= 2; | |
3920 | opcode = opcode << 8 | ir.modrm; | |
3921 | goto no_support; | |
3922 | } | |
7ad10968 HZ |
3923 | switch (ir.reg) |
3924 | { | |
a38bba38 MS |
3925 | case 0: /* inc */ |
3926 | case 1: /* dec */ | |
cf648174 HZ |
3927 | if ((opcode & 1) == 0) |
3928 | ir.ot = OT_BYTE; | |
3929 | else | |
3930 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3931 | if (ir.mod != 3) |
3932 | { | |
3933 | if (i386_record_lea_modrm (&ir)) | |
3934 | return -1; | |
3935 | } | |
3936 | else | |
3937 | { | |
cf648174 HZ |
3938 | ir.rm |= ir.rex_b; |
3939 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3940 | ir.rm &= 0x3; |
cf648174 | 3941 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3942 | } |
cf648174 | 3943 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3944 | break; |
a38bba38 | 3945 | case 2: /* call */ |
cf648174 HZ |
3946 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3947 | ir.dflag = 2; | |
3948 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3949 | return -1; |
cf648174 | 3950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3951 | break; |
a38bba38 | 3952 | case 3: /* lcall */ |
cf648174 HZ |
3953 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3954 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3955 | return -1; |
cf648174 | 3956 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3957 | break; |
a38bba38 MS |
3958 | case 4: /* jmp */ |
3959 | case 5: /* ljmp */ | |
cf648174 HZ |
3960 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3961 | break; | |
a38bba38 | 3962 | case 6: /* push */ |
cf648174 HZ |
3963 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3964 | ir.dflag = 2; | |
3965 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3966 | return -1; | |
7ad10968 HZ |
3967 | break; |
3968 | default: | |
3969 | ir.addr -= 2; | |
3970 | opcode = opcode << 8 | ir.modrm; | |
3971 | goto no_support; | |
3972 | break; | |
3973 | } | |
3974 | break; | |
3975 | ||
a38bba38 | 3976 | case 0x84: /* test */ |
7ad10968 HZ |
3977 | case 0x85: |
3978 | case 0xa8: | |
3979 | case 0xa9: | |
cf648174 | 3980 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3981 | break; |
3982 | ||
a38bba38 | 3983 | case 0x98: /* CWDE/CBW */ |
cf648174 | 3984 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3985 | break; |
3986 | ||
a38bba38 | 3987 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
3988 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3989 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3990 | break; |
3991 | ||
a38bba38 | 3992 | case 0x0faf: /* imul */ |
7ad10968 HZ |
3993 | case 0x69: |
3994 | case 0x6b: | |
3995 | ir.ot = ir.dflag + OT_WORD; | |
3996 | if (i386_record_modrm (&ir)) | |
3997 | return -1; | |
cf648174 HZ |
3998 | if (opcode == 0x69) |
3999 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4000 | else if (opcode == 0x6b) | |
4001 | ir.rip_offset = 1; | |
4002 | ir.reg |= rex_r; | |
4003 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4004 | ir.reg &= 0x3; |
cf648174 HZ |
4005 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4006 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4007 | break; |
4008 | ||
a38bba38 | 4009 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4010 | case 0x0fc1: |
4011 | if ((opcode & 1) == 0) | |
4012 | ir.ot = OT_BYTE; | |
4013 | else | |
4014 | ir.ot = ir.dflag + OT_WORD; | |
4015 | if (i386_record_modrm (&ir)) | |
4016 | return -1; | |
cf648174 | 4017 | ir.reg |= rex_r; |
7ad10968 HZ |
4018 | if (ir.mod == 3) |
4019 | { | |
cf648174 | 4020 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4021 | ir.reg &= 0x3; |
cf648174 HZ |
4022 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4023 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4024 | ir.rm &= 0x3; |
cf648174 | 4025 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4026 | } |
4027 | else | |
4028 | { | |
4029 | if (i386_record_lea_modrm (&ir)) | |
4030 | return -1; | |
cf648174 | 4031 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4032 | ir.reg &= 0x3; |
cf648174 | 4033 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4034 | } |
cf648174 | 4035 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4036 | break; |
4037 | ||
a38bba38 | 4038 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4039 | case 0x0fb1: |
4040 | if ((opcode & 1) == 0) | |
4041 | ir.ot = OT_BYTE; | |
4042 | else | |
4043 | ir.ot = ir.dflag + OT_WORD; | |
4044 | if (i386_record_modrm (&ir)) | |
4045 | return -1; | |
4046 | if (ir.mod == 3) | |
4047 | { | |
cf648174 HZ |
4048 | ir.reg |= rex_r; |
4049 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4050 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4051 | ir.reg &= 0x3; |
cf648174 | 4052 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4053 | } |
4054 | else | |
4055 | { | |
cf648174 | 4056 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4057 | if (i386_record_lea_modrm (&ir)) |
4058 | return -1; | |
4059 | } | |
cf648174 | 4060 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4061 | break; |
4062 | ||
a38bba38 | 4063 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4064 | if (i386_record_modrm (&ir)) |
4065 | return -1; | |
4066 | if (ir.mod == 3) | |
4067 | { | |
4068 | ir.addr -= 2; | |
4069 | opcode = opcode << 8 | ir.modrm; | |
4070 | goto no_support; | |
4071 | } | |
cf648174 HZ |
4072 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4073 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4074 | if (i386_record_lea_modrm (&ir)) |
4075 | return -1; | |
cf648174 | 4076 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4077 | break; |
4078 | ||
a38bba38 | 4079 | case 0x50: /* push */ |
7ad10968 HZ |
4080 | case 0x51: |
4081 | case 0x52: | |
4082 | case 0x53: | |
4083 | case 0x54: | |
4084 | case 0x55: | |
4085 | case 0x56: | |
4086 | case 0x57: | |
4087 | case 0x68: | |
4088 | case 0x6a: | |
cf648174 HZ |
4089 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4090 | ir.dflag = 2; | |
4091 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4092 | return -1; | |
4093 | break; | |
4094 | ||
a38bba38 MS |
4095 | case 0x06: /* push es */ |
4096 | case 0x0e: /* push cs */ | |
4097 | case 0x16: /* push ss */ | |
4098 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4099 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4100 | { | |
4101 | ir.addr -= 1; | |
4102 | goto no_support; | |
4103 | } | |
4104 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4105 | return -1; | |
4106 | break; | |
4107 | ||
a38bba38 MS |
4108 | case 0x0fa0: /* push fs */ |
4109 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4110 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4111 | { | |
4112 | ir.addr -= 2; | |
4113 | goto no_support; | |
4114 | } | |
4115 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4116 | return -1; |
cf648174 HZ |
4117 | break; |
4118 | ||
a38bba38 | 4119 | case 0x60: /* pusha */ |
cf648174 HZ |
4120 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4121 | { | |
4122 | ir.addr -= 1; | |
4123 | goto no_support; | |
4124 | } | |
4125 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4126 | return -1; |
4127 | break; | |
4128 | ||
a38bba38 | 4129 | case 0x58: /* pop */ |
7ad10968 HZ |
4130 | case 0x59: |
4131 | case 0x5a: | |
4132 | case 0x5b: | |
4133 | case 0x5c: | |
4134 | case 0x5d: | |
4135 | case 0x5e: | |
4136 | case 0x5f: | |
cf648174 HZ |
4137 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4138 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4139 | break; |
4140 | ||
a38bba38 | 4141 | case 0x61: /* popa */ |
cf648174 HZ |
4142 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4143 | { | |
4144 | ir.addr -= 1; | |
4145 | goto no_support; | |
7ad10968 | 4146 | } |
425b824a MS |
4147 | for (regnum = X86_RECORD_REAX_REGNUM; |
4148 | regnum <= X86_RECORD_REDI_REGNUM; | |
4149 | regnum++) | |
4150 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4151 | break; |
4152 | ||
a38bba38 | 4153 | case 0x8f: /* pop */ |
cf648174 HZ |
4154 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4155 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4156 | else | |
4157 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4158 | if (i386_record_modrm (&ir)) |
4159 | return -1; | |
4160 | if (ir.mod == 3) | |
cf648174 | 4161 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4162 | else |
4163 | { | |
cf648174 | 4164 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4165 | if (i386_record_lea_modrm (&ir)) |
4166 | return -1; | |
4167 | } | |
cf648174 | 4168 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4169 | break; |
4170 | ||
a38bba38 | 4171 | case 0xc8: /* enter */ |
cf648174 HZ |
4172 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4173 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4174 | ir.dflag = 2; | |
4175 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4176 | return -1; |
4177 | break; | |
4178 | ||
a38bba38 | 4179 | case 0xc9: /* leave */ |
cf648174 HZ |
4180 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4181 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4182 | break; |
4183 | ||
a38bba38 | 4184 | case 0x07: /* pop es */ |
cf648174 HZ |
4185 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4186 | { | |
4187 | ir.addr -= 1; | |
4188 | goto no_support; | |
4189 | } | |
4190 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4191 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4192 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4193 | break; |
4194 | ||
a38bba38 | 4195 | case 0x17: /* pop ss */ |
cf648174 HZ |
4196 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4197 | { | |
4198 | ir.addr -= 1; | |
4199 | goto no_support; | |
4200 | } | |
4201 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4202 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4203 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4204 | break; |
4205 | ||
a38bba38 | 4206 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4207 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4208 | { | |
4209 | ir.addr -= 1; | |
4210 | goto no_support; | |
4211 | } | |
4212 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4213 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4214 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4215 | break; |
4216 | ||
a38bba38 | 4217 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4218 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4219 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4220 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4221 | break; |
4222 | ||
a38bba38 | 4223 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4224 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4225 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4226 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4227 | break; |
4228 | ||
a38bba38 | 4229 | case 0x88: /* mov */ |
7ad10968 HZ |
4230 | case 0x89: |
4231 | case 0xc6: | |
4232 | case 0xc7: | |
4233 | if ((opcode & 1) == 0) | |
4234 | ir.ot = OT_BYTE; | |
4235 | else | |
4236 | ir.ot = ir.dflag + OT_WORD; | |
4237 | ||
4238 | if (i386_record_modrm (&ir)) | |
4239 | return -1; | |
4240 | ||
4241 | if (ir.mod != 3) | |
4242 | { | |
cf648174 HZ |
4243 | if (opcode == 0xc6 || opcode == 0xc7) |
4244 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4245 | if (i386_record_lea_modrm (&ir)) |
4246 | return -1; | |
4247 | } | |
4248 | else | |
4249 | { | |
cf648174 HZ |
4250 | if (opcode == 0xc6 || opcode == 0xc7) |
4251 | ir.rm |= ir.rex_b; | |
4252 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4253 | ir.rm &= 0x3; |
cf648174 | 4254 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4255 | } |
7ad10968 | 4256 | break; |
cf648174 | 4257 | |
a38bba38 | 4258 | case 0x8a: /* mov */ |
7ad10968 HZ |
4259 | case 0x8b: |
4260 | if ((opcode & 1) == 0) | |
4261 | ir.ot = OT_BYTE; | |
4262 | else | |
4263 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4264 | if (i386_record_modrm (&ir)) |
4265 | return -1; | |
cf648174 HZ |
4266 | ir.reg |= rex_r; |
4267 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4268 | ir.reg &= 0x3; |
cf648174 HZ |
4269 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4270 | break; | |
7ad10968 | 4271 | |
a38bba38 | 4272 | case 0x8c: /* mov seg */ |
cf648174 | 4273 | if (i386_record_modrm (&ir)) |
7ad10968 | 4274 | return -1; |
cf648174 HZ |
4275 | if (ir.reg > 5) |
4276 | { | |
4277 | ir.addr -= 2; | |
4278 | opcode = opcode << 8 | ir.modrm; | |
4279 | goto no_support; | |
4280 | } | |
4281 | ||
4282 | if (ir.mod == 3) | |
4283 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4284 | else | |
4285 | { | |
4286 | ir.ot = OT_WORD; | |
4287 | if (i386_record_lea_modrm (&ir)) | |
4288 | return -1; | |
4289 | } | |
7ad10968 HZ |
4290 | break; |
4291 | ||
a38bba38 | 4292 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4293 | if (i386_record_modrm (&ir)) |
4294 | return -1; | |
7ad10968 HZ |
4295 | switch (ir.reg) |
4296 | { | |
4297 | case 0: | |
425b824a | 4298 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4299 | break; |
4300 | case 2: | |
425b824a | 4301 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4302 | break; |
4303 | case 3: | |
425b824a | 4304 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4305 | break; |
4306 | case 4: | |
425b824a | 4307 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4308 | break; |
4309 | case 5: | |
425b824a | 4310 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4311 | break; |
4312 | default: | |
4313 | ir.addr -= 2; | |
4314 | opcode = opcode << 8 | ir.modrm; | |
4315 | goto no_support; | |
4316 | break; | |
4317 | } | |
425b824a | 4318 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4319 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4320 | break; |
4321 | ||
a38bba38 MS |
4322 | case 0x0fb6: /* movzbS */ |
4323 | case 0x0fb7: /* movzwS */ | |
4324 | case 0x0fbe: /* movsbS */ | |
4325 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4326 | if (i386_record_modrm (&ir)) |
4327 | return -1; | |
cf648174 | 4328 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4329 | break; |
4330 | ||
a38bba38 | 4331 | case 0x8d: /* lea */ |
7ad10968 HZ |
4332 | if (i386_record_modrm (&ir)) |
4333 | return -1; | |
4334 | if (ir.mod == 3) | |
4335 | { | |
4336 | ir.addr -= 2; | |
4337 | opcode = opcode << 8 | ir.modrm; | |
4338 | goto no_support; | |
4339 | } | |
7ad10968 | 4340 | ir.ot = ir.dflag; |
cf648174 HZ |
4341 | ir.reg |= rex_r; |
4342 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4343 | ir.reg &= 0x3; |
cf648174 | 4344 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4345 | break; |
4346 | ||
a38bba38 | 4347 | case 0xa0: /* mov EAX */ |
7ad10968 | 4348 | case 0xa1: |
a38bba38 MS |
4349 | |
4350 | case 0xd7: /* xlat */ | |
cf648174 | 4351 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4352 | break; |
4353 | ||
a38bba38 | 4354 | case 0xa2: /* mov EAX */ |
7ad10968 | 4355 | case 0xa3: |
d7877f7e | 4356 | if (ir.override >= 0) |
cf648174 | 4357 | { |
df61f520 | 4358 | warning (_("Process record ignores the memory change " |
926569ae | 4359 | "of instruction at address %s because " |
df61f520 HZ |
4360 | "it can't get the value of the segment " |
4361 | "register."), | |
4362 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
4363 | } |
4364 | else | |
4365 | { | |
4366 | if ((opcode & 1) == 0) | |
4367 | ir.ot = OT_BYTE; | |
4368 | else | |
4369 | ir.ot = ir.dflag + OT_WORD; | |
4370 | if (ir.aflag == 2) | |
4371 | { | |
60a1502a | 4372 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4373 | { |
4374 | if (record_debug) | |
4375 | printf_unfiltered (_("Process record: error reading " | |
4376 | "memory at addr 0x%s len = 8.\n"), | |
4377 | paddress (gdbarch, ir.addr)); | |
4378 | return -1; | |
4379 | } | |
4380 | ir.addr += 8; | |
60a1502a | 4381 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4382 | } |
4383 | else if (ir.aflag) | |
4384 | { | |
60a1502a | 4385 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4386 | { |
4387 | if (record_debug) | |
4388 | printf_unfiltered (_("Process record: error reading " | |
4389 | "memory at addr 0x%s len = 4.\n"), | |
4390 | paddress (gdbarch, ir.addr)); | |
4391 | return -1; | |
4392 | } | |
4393 | ir.addr += 4; | |
60a1502a | 4394 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4395 | } |
4396 | else | |
4397 | { | |
60a1502a | 4398 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4399 | { |
4400 | if (record_debug) | |
4401 | printf_unfiltered (_("Process record: error reading " | |
4402 | "memory at addr 0x%s len = 2.\n"), | |
4403 | paddress (gdbarch, ir.addr)); | |
4404 | return -1; | |
4405 | } | |
4406 | ir.addr += 2; | |
60a1502a | 4407 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4408 | } |
648d0c8b | 4409 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4410 | return -1; |
4411 | } | |
7ad10968 HZ |
4412 | break; |
4413 | ||
a38bba38 | 4414 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4415 | case 0xb1: |
4416 | case 0xb2: | |
4417 | case 0xb3: | |
4418 | case 0xb4: | |
4419 | case 0xb5: | |
4420 | case 0xb6: | |
4421 | case 0xb7: | |
cf648174 HZ |
4422 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4423 | ? ((opcode & 0x7) | ir.rex_b) | |
4424 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4425 | break; |
4426 | ||
a38bba38 | 4427 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4428 | case 0xb9: |
4429 | case 0xba: | |
4430 | case 0xbb: | |
4431 | case 0xbc: | |
4432 | case 0xbd: | |
4433 | case 0xbe: | |
4434 | case 0xbf: | |
cf648174 | 4435 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4436 | break; |
4437 | ||
a38bba38 | 4438 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4439 | case 0x92: |
4440 | case 0x93: | |
4441 | case 0x94: | |
4442 | case 0x95: | |
4443 | case 0x96: | |
4444 | case 0x97: | |
cf648174 HZ |
4445 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4446 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4447 | break; |
4448 | ||
a38bba38 | 4449 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4450 | case 0x87: |
4451 | if ((opcode & 1) == 0) | |
4452 | ir.ot = OT_BYTE; | |
4453 | else | |
4454 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4455 | if (i386_record_modrm (&ir)) |
4456 | return -1; | |
7ad10968 HZ |
4457 | if (ir.mod == 3) |
4458 | { | |
86839d38 | 4459 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4460 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4461 | ir.rm &= 0x3; | |
4462 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4463 | } |
4464 | else | |
4465 | { | |
4466 | if (i386_record_lea_modrm (&ir)) | |
4467 | return -1; | |
4468 | } | |
cf648174 HZ |
4469 | ir.reg |= rex_r; |
4470 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4471 | ir.reg &= 0x3; |
cf648174 | 4472 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4473 | break; |
4474 | ||
a38bba38 MS |
4475 | case 0xc4: /* les Gv */ |
4476 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4477 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4478 | { | |
4479 | ir.addr -= 1; | |
4480 | goto no_support; | |
4481 | } | |
a38bba38 MS |
4482 | case 0x0fb2: /* lss Gv */ |
4483 | case 0x0fb4: /* lfs Gv */ | |
4484 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4485 | if (i386_record_modrm (&ir)) |
4486 | return -1; | |
4487 | if (ir.mod == 3) | |
4488 | { | |
4489 | if (opcode > 0xff) | |
4490 | ir.addr -= 3; | |
4491 | else | |
4492 | ir.addr -= 2; | |
4493 | opcode = opcode << 8 | ir.modrm; | |
4494 | goto no_support; | |
4495 | } | |
7ad10968 HZ |
4496 | switch (opcode) |
4497 | { | |
a38bba38 | 4498 | case 0xc4: /* les Gv */ |
425b824a | 4499 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4500 | break; |
a38bba38 | 4501 | case 0xc5: /* lds Gv */ |
425b824a | 4502 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4503 | break; |
a38bba38 | 4504 | case 0x0fb2: /* lss Gv */ |
425b824a | 4505 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4506 | break; |
a38bba38 | 4507 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4508 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4509 | break; |
a38bba38 | 4510 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4511 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4512 | break; |
4513 | } | |
425b824a | 4514 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4515 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4516 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4517 | break; |
4518 | ||
a38bba38 | 4519 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4520 | case 0xc1: |
4521 | case 0xd0: | |
4522 | case 0xd1: | |
4523 | case 0xd2: | |
4524 | case 0xd3: | |
4525 | if ((opcode & 1) == 0) | |
4526 | ir.ot = OT_BYTE; | |
4527 | else | |
4528 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4529 | if (i386_record_modrm (&ir)) |
4530 | return -1; | |
7ad10968 HZ |
4531 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4532 | { | |
4533 | if (i386_record_lea_modrm (&ir)) | |
4534 | return -1; | |
4535 | } | |
4536 | else | |
4537 | { | |
cf648174 HZ |
4538 | ir.rm |= ir.rex_b; |
4539 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4540 | ir.rm &= 0x3; |
cf648174 | 4541 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4542 | } |
cf648174 | 4543 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4544 | break; |
4545 | ||
4546 | case 0x0fa4: | |
4547 | case 0x0fa5: | |
4548 | case 0x0fac: | |
4549 | case 0x0fad: | |
4550 | if (i386_record_modrm (&ir)) | |
4551 | return -1; | |
4552 | if (ir.mod == 3) | |
4553 | { | |
4554 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4555 | return -1; | |
4556 | } | |
4557 | else | |
4558 | { | |
4559 | if (i386_record_lea_modrm (&ir)) | |
4560 | return -1; | |
4561 | } | |
4562 | break; | |
4563 | ||
a38bba38 | 4564 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4565 | case 0xd9: |
4566 | case 0xda: | |
4567 | case 0xdb: | |
4568 | case 0xdc: | |
4569 | case 0xdd: | |
4570 | case 0xde: | |
4571 | case 0xdf: | |
4572 | if (i386_record_modrm (&ir)) | |
4573 | return -1; | |
4574 | ir.reg |= ((opcode & 7) << 3); | |
4575 | if (ir.mod != 3) | |
4576 | { | |
0289bdd7 | 4577 | /* Memory. */ |
955db0c0 | 4578 | uint64_t addr64; |
7ad10968 | 4579 | |
955db0c0 | 4580 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4581 | return -1; |
4582 | switch (ir.reg) | |
4583 | { | |
7ad10968 | 4584 | case 0x02: |
0289bdd7 MS |
4585 | case 0x12: |
4586 | case 0x22: | |
4587 | case 0x32: | |
4588 | /* For fcom, ficom nothing to do. */ | |
4589 | break; | |
7ad10968 | 4590 | case 0x03: |
0289bdd7 MS |
4591 | case 0x13: |
4592 | case 0x23: | |
4593 | case 0x33: | |
4594 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4595 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4596 | return -1; | |
4597 | break; | |
4598 | case 0x00: | |
4599 | case 0x01: | |
7ad10968 HZ |
4600 | case 0x04: |
4601 | case 0x05: | |
4602 | case 0x06: | |
4603 | case 0x07: | |
4604 | case 0x10: | |
4605 | case 0x11: | |
7ad10968 HZ |
4606 | case 0x14: |
4607 | case 0x15: | |
4608 | case 0x16: | |
4609 | case 0x17: | |
4610 | case 0x20: | |
4611 | case 0x21: | |
7ad10968 HZ |
4612 | case 0x24: |
4613 | case 0x25: | |
4614 | case 0x26: | |
4615 | case 0x27: | |
4616 | case 0x30: | |
4617 | case 0x31: | |
7ad10968 HZ |
4618 | case 0x34: |
4619 | case 0x35: | |
4620 | case 0x36: | |
4621 | case 0x37: | |
0289bdd7 MS |
4622 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4623 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4624 | of code, always affects st(0) register. */ | |
4625 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4626 | return -1; | |
7ad10968 HZ |
4627 | break; |
4628 | case 0x08: | |
4629 | case 0x0a: | |
4630 | case 0x0b: | |
4631 | case 0x18: | |
4632 | case 0x19: | |
4633 | case 0x1a: | |
4634 | case 0x1b: | |
0289bdd7 | 4635 | case 0x1d: |
7ad10968 HZ |
4636 | case 0x28: |
4637 | case 0x29: | |
4638 | case 0x2a: | |
4639 | case 0x2b: | |
4640 | case 0x38: | |
4641 | case 0x39: | |
4642 | case 0x3a: | |
4643 | case 0x3b: | |
0289bdd7 MS |
4644 | case 0x3c: |
4645 | case 0x3d: | |
7ad10968 HZ |
4646 | switch (ir.reg & 7) |
4647 | { | |
4648 | case 0: | |
0289bdd7 MS |
4649 | /* Handling fld, fild. */ |
4650 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4651 | return -1; | |
7ad10968 HZ |
4652 | break; |
4653 | case 1: | |
4654 | switch (ir.reg >> 4) | |
4655 | { | |
4656 | case 0: | |
955db0c0 | 4657 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
4658 | return -1; |
4659 | break; | |
4660 | case 2: | |
955db0c0 | 4661 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
4662 | return -1; |
4663 | break; | |
4664 | case 3: | |
0289bdd7 | 4665 | break; |
7ad10968 | 4666 | default: |
955db0c0 | 4667 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4668 | return -1; |
4669 | break; | |
4670 | } | |
4671 | break; | |
4672 | default: | |
4673 | switch (ir.reg >> 4) | |
4674 | { | |
4675 | case 0: | |
955db0c0 | 4676 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
4677 | return -1; |
4678 | if (3 == (ir.reg & 7)) | |
4679 | { | |
4680 | /* For fstp m32fp. */ | |
4681 | if (i386_record_floats (gdbarch, &ir, | |
4682 | I386_SAVE_FPU_REGS)) | |
4683 | return -1; | |
4684 | } | |
4685 | break; | |
7ad10968 | 4686 | case 1: |
955db0c0 | 4687 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 4688 | return -1; |
0289bdd7 MS |
4689 | if ((3 == (ir.reg & 7)) |
4690 | || (5 == (ir.reg & 7)) | |
4691 | || (7 == (ir.reg & 7))) | |
4692 | { | |
4693 | /* For fstp insn. */ | |
4694 | if (i386_record_floats (gdbarch, &ir, | |
4695 | I386_SAVE_FPU_REGS)) | |
4696 | return -1; | |
4697 | } | |
7ad10968 HZ |
4698 | break; |
4699 | case 2: | |
955db0c0 | 4700 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4701 | return -1; |
0289bdd7 MS |
4702 | if (3 == (ir.reg & 7)) |
4703 | { | |
4704 | /* For fstp m64fp. */ | |
4705 | if (i386_record_floats (gdbarch, &ir, | |
4706 | I386_SAVE_FPU_REGS)) | |
4707 | return -1; | |
4708 | } | |
7ad10968 HZ |
4709 | break; |
4710 | case 3: | |
0289bdd7 MS |
4711 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4712 | { | |
4713 | /* For fistp, fbld, fild, fbstp. */ | |
4714 | if (i386_record_floats (gdbarch, &ir, | |
4715 | I386_SAVE_FPU_REGS)) | |
4716 | return -1; | |
4717 | } | |
4718 | /* Fall through */ | |
7ad10968 | 4719 | default: |
955db0c0 | 4720 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
4721 | return -1; |
4722 | break; | |
4723 | } | |
4724 | break; | |
4725 | } | |
4726 | break; | |
4727 | case 0x0c: | |
0289bdd7 MS |
4728 | /* Insn fldenv. */ |
4729 | if (i386_record_floats (gdbarch, &ir, | |
4730 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4731 | return -1; | |
4732 | break; | |
7ad10968 | 4733 | case 0x0d: |
0289bdd7 MS |
4734 | /* Insn fldcw. */ |
4735 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4736 | return -1; | |
4737 | break; | |
7ad10968 | 4738 | case 0x2c: |
0289bdd7 MS |
4739 | /* Insn frstor. */ |
4740 | if (i386_record_floats (gdbarch, &ir, | |
4741 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4742 | return -1; | |
7ad10968 HZ |
4743 | break; |
4744 | case 0x0e: | |
4745 | if (ir.dflag) | |
4746 | { | |
955db0c0 | 4747 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
4748 | return -1; |
4749 | } | |
4750 | else | |
4751 | { | |
955db0c0 | 4752 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
4753 | return -1; |
4754 | } | |
4755 | break; | |
4756 | case 0x0f: | |
4757 | case 0x2f: | |
955db0c0 | 4758 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 4759 | return -1; |
0289bdd7 MS |
4760 | /* Insn fstp, fbstp. */ |
4761 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4762 | return -1; | |
7ad10968 HZ |
4763 | break; |
4764 | case 0x1f: | |
4765 | case 0x3e: | |
955db0c0 | 4766 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
4767 | return -1; |
4768 | break; | |
4769 | case 0x2e: | |
4770 | if (ir.dflag) | |
4771 | { | |
955db0c0 | 4772 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 4773 | return -1; |
955db0c0 | 4774 | addr64 += 28; |
7ad10968 HZ |
4775 | } |
4776 | else | |
4777 | { | |
955db0c0 | 4778 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 4779 | return -1; |
955db0c0 | 4780 | addr64 += 14; |
7ad10968 | 4781 | } |
955db0c0 | 4782 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 4783 | return -1; |
0289bdd7 MS |
4784 | /* Insn fsave. */ |
4785 | if (i386_record_floats (gdbarch, &ir, | |
4786 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4787 | return -1; | |
7ad10968 HZ |
4788 | break; |
4789 | case 0x3f: | |
955db0c0 | 4790 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 4791 | return -1; |
0289bdd7 MS |
4792 | /* Insn fistp. */ |
4793 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4794 | return -1; | |
7ad10968 HZ |
4795 | break; |
4796 | default: | |
4797 | ir.addr -= 2; | |
4798 | opcode = opcode << 8 | ir.modrm; | |
4799 | goto no_support; | |
4800 | break; | |
4801 | } | |
4802 | } | |
0289bdd7 MS |
4803 | /* Opcode is an extension of modR/M byte. */ |
4804 | else | |
4805 | { | |
4806 | switch (opcode) | |
4807 | { | |
4808 | case 0xd8: | |
4809 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4810 | return -1; | |
4811 | break; | |
4812 | case 0xd9: | |
4813 | if (0x0c == (ir.modrm >> 4)) | |
4814 | { | |
4815 | if ((ir.modrm & 0x0f) <= 7) | |
4816 | { | |
4817 | if (i386_record_floats (gdbarch, &ir, | |
4818 | I386_SAVE_FPU_REGS)) | |
4819 | return -1; | |
4820 | } | |
4821 | else | |
4822 | { | |
4823 | if (i386_record_floats (gdbarch, &ir, | |
4824 | I387_ST0_REGNUM (tdep))) | |
4825 | return -1; | |
4826 | /* If only st(0) is changing, then we have already | |
4827 | recorded. */ | |
4828 | if ((ir.modrm & 0x0f) - 0x08) | |
4829 | { | |
4830 | if (i386_record_floats (gdbarch, &ir, | |
4831 | I387_ST0_REGNUM (tdep) + | |
4832 | ((ir.modrm & 0x0f) - 0x08))) | |
4833 | return -1; | |
4834 | } | |
4835 | } | |
4836 | } | |
4837 | else | |
4838 | { | |
4839 | switch (ir.modrm) | |
4840 | { | |
4841 | case 0xe0: | |
4842 | case 0xe1: | |
4843 | case 0xf0: | |
4844 | case 0xf5: | |
4845 | case 0xf8: | |
4846 | case 0xfa: | |
4847 | case 0xfc: | |
4848 | case 0xfe: | |
4849 | case 0xff: | |
4850 | if (i386_record_floats (gdbarch, &ir, | |
4851 | I387_ST0_REGNUM (tdep))) | |
4852 | return -1; | |
4853 | break; | |
4854 | case 0xf1: | |
4855 | case 0xf2: | |
4856 | case 0xf3: | |
4857 | case 0xf4: | |
4858 | case 0xf6: | |
4859 | case 0xf7: | |
4860 | case 0xe8: | |
4861 | case 0xe9: | |
4862 | case 0xea: | |
4863 | case 0xeb: | |
4864 | case 0xec: | |
4865 | case 0xed: | |
4866 | case 0xee: | |
4867 | case 0xf9: | |
4868 | case 0xfb: | |
4869 | if (i386_record_floats (gdbarch, &ir, | |
4870 | I386_SAVE_FPU_REGS)) | |
4871 | return -1; | |
4872 | break; | |
4873 | case 0xfd: | |
4874 | if (i386_record_floats (gdbarch, &ir, | |
4875 | I387_ST0_REGNUM (tdep))) | |
4876 | return -1; | |
4877 | if (i386_record_floats (gdbarch, &ir, | |
4878 | I387_ST0_REGNUM (tdep) + 1)) | |
4879 | return -1; | |
4880 | break; | |
4881 | } | |
4882 | } | |
4883 | break; | |
4884 | case 0xda: | |
4885 | if (0xe9 == ir.modrm) | |
4886 | { | |
4887 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4888 | return -1; | |
4889 | } | |
4890 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4891 | { | |
4892 | if (i386_record_floats (gdbarch, &ir, | |
4893 | I387_ST0_REGNUM (tdep))) | |
4894 | return -1; | |
4895 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4896 | { | |
4897 | if (i386_record_floats (gdbarch, &ir, | |
4898 | I387_ST0_REGNUM (tdep) + | |
4899 | (ir.modrm & 0x0f))) | |
4900 | return -1; | |
4901 | } | |
4902 | else if ((ir.modrm & 0x0f) - 0x08) | |
4903 | { | |
4904 | if (i386_record_floats (gdbarch, &ir, | |
4905 | I387_ST0_REGNUM (tdep) + | |
4906 | ((ir.modrm & 0x0f) - 0x08))) | |
4907 | return -1; | |
4908 | } | |
4909 | } | |
4910 | break; | |
4911 | case 0xdb: | |
4912 | if (0xe3 == ir.modrm) | |
4913 | { | |
4914 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
4915 | return -1; | |
4916 | } | |
4917 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4918 | { | |
4919 | if (i386_record_floats (gdbarch, &ir, | |
4920 | I387_ST0_REGNUM (tdep))) | |
4921 | return -1; | |
4922 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4923 | { | |
4924 | if (i386_record_floats (gdbarch, &ir, | |
4925 | I387_ST0_REGNUM (tdep) + | |
4926 | (ir.modrm & 0x0f))) | |
4927 | return -1; | |
4928 | } | |
4929 | else if ((ir.modrm & 0x0f) - 0x08) | |
4930 | { | |
4931 | if (i386_record_floats (gdbarch, &ir, | |
4932 | I387_ST0_REGNUM (tdep) + | |
4933 | ((ir.modrm & 0x0f) - 0x08))) | |
4934 | return -1; | |
4935 | } | |
4936 | } | |
4937 | break; | |
4938 | case 0xdc: | |
4939 | if ((0x0c == ir.modrm >> 4) | |
4940 | || (0x0d == ir.modrm >> 4) | |
4941 | || (0x0f == ir.modrm >> 4)) | |
4942 | { | |
4943 | if ((ir.modrm & 0x0f) <= 7) | |
4944 | { | |
4945 | if (i386_record_floats (gdbarch, &ir, | |
4946 | I387_ST0_REGNUM (tdep) + | |
4947 | (ir.modrm & 0x0f))) | |
4948 | return -1; | |
4949 | } | |
4950 | else | |
4951 | { | |
4952 | if (i386_record_floats (gdbarch, &ir, | |
4953 | I387_ST0_REGNUM (tdep) + | |
4954 | ((ir.modrm & 0x0f) - 0x08))) | |
4955 | return -1; | |
4956 | } | |
4957 | } | |
4958 | break; | |
4959 | case 0xdd: | |
4960 | if (0x0c == ir.modrm >> 4) | |
4961 | { | |
4962 | if (i386_record_floats (gdbarch, &ir, | |
4963 | I387_FTAG_REGNUM (tdep))) | |
4964 | return -1; | |
4965 | } | |
4966 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4967 | { | |
4968 | if ((ir.modrm & 0x0f) <= 7) | |
4969 | { | |
4970 | if (i386_record_floats (gdbarch, &ir, | |
4971 | I387_ST0_REGNUM (tdep) + | |
4972 | (ir.modrm & 0x0f))) | |
4973 | return -1; | |
4974 | } | |
4975 | else | |
4976 | { | |
4977 | if (i386_record_floats (gdbarch, &ir, | |
4978 | I386_SAVE_FPU_REGS)) | |
4979 | return -1; | |
4980 | } | |
4981 | } | |
4982 | break; | |
4983 | case 0xde: | |
4984 | if ((0x0c == ir.modrm >> 4) | |
4985 | || (0x0e == ir.modrm >> 4) | |
4986 | || (0x0f == ir.modrm >> 4) | |
4987 | || (0xd9 == ir.modrm)) | |
4988 | { | |
4989 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4990 | return -1; | |
4991 | } | |
4992 | break; | |
4993 | case 0xdf: | |
4994 | if (0xe0 == ir.modrm) | |
4995 | { | |
4996 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4997 | return -1; | |
4998 | } | |
4999 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5000 | { | |
5001 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5002 | return -1; | |
5003 | } | |
5004 | break; | |
5005 | } | |
5006 | } | |
7ad10968 | 5007 | break; |
7ad10968 | 5008 | /* string ops */ |
a38bba38 | 5009 | case 0xa4: /* movsS */ |
7ad10968 | 5010 | case 0xa5: |
a38bba38 | 5011 | case 0xaa: /* stosS */ |
7ad10968 | 5012 | case 0xab: |
a38bba38 | 5013 | case 0x6c: /* insS */ |
7ad10968 | 5014 | case 0x6d: |
cf648174 | 5015 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5016 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5017 | &addr); |
5018 | if (addr) | |
cf648174 | 5019 | { |
77d7dc92 HZ |
5020 | ULONGEST es, ds; |
5021 | ||
5022 | if ((opcode & 1) == 0) | |
5023 | ir.ot = OT_BYTE; | |
5024 | else | |
5025 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5026 | regcache_raw_read_unsigned (ir.regcache, |
5027 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5028 | &addr); |
77d7dc92 | 5029 | |
d7877f7e HZ |
5030 | regcache_raw_read_unsigned (ir.regcache, |
5031 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5032 | &es); | |
5033 | regcache_raw_read_unsigned (ir.regcache, | |
5034 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5035 | &ds); | |
5036 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5037 | { |
5038 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 5039 | warning (_("Process record ignores the memory " |
926569ae | 5040 | "change of instruction at address %s " |
df61f520 HZ |
5041 | "because it can't get the value of the " |
5042 | "ES segment register."), | |
5043 | paddress (gdbarch, ir.orig_addr)); | |
5044 | } | |
5045 | else | |
5046 | { | |
648d0c8b | 5047 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5048 | return -1; |
77d7dc92 HZ |
5049 | } |
5050 | ||
5051 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5052 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5053 | if (opcode == 0xa4 || opcode == 0xa5) |
5054 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5055 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5056 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5057 | } | |
cf648174 | 5058 | break; |
7ad10968 | 5059 | |
a38bba38 | 5060 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5061 | case 0xa7: |
5062 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5063 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5064 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5065 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5066 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5067 | break; |
5068 | ||
a38bba38 | 5069 | case 0xac: /* lodsS */ |
7ad10968 | 5070 | case 0xad: |
cf648174 HZ |
5071 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5072 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5073 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5074 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5075 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5076 | break; |
5077 | ||
a38bba38 | 5078 | case 0xae: /* scasS */ |
7ad10968 | 5079 | case 0xaf: |
cf648174 | 5080 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5081 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5082 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5083 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5084 | break; |
5085 | ||
a38bba38 | 5086 | case 0x6e: /* outsS */ |
cf648174 HZ |
5087 | case 0x6f: |
5088 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5089 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5090 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5091 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5092 | break; |
5093 | ||
a38bba38 | 5094 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5095 | case 0xe5: |
5096 | case 0xec: | |
5097 | case 0xed: | |
cf648174 HZ |
5098 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5099 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5100 | break; |
5101 | ||
5102 | case 0xe6: | |
5103 | case 0xe7: | |
5104 | case 0xee: | |
5105 | case 0xef: | |
5106 | break; | |
5107 | ||
5108 | /* control */ | |
a38bba38 MS |
5109 | case 0xc2: /* ret im */ |
5110 | case 0xc3: /* ret */ | |
cf648174 HZ |
5111 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5112 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5113 | break; | |
5114 | ||
a38bba38 MS |
5115 | case 0xca: /* lret im */ |
5116 | case 0xcb: /* lret */ | |
5117 | case 0xcf: /* iret */ | |
cf648174 HZ |
5118 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5119 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5120 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5121 | break; |
5122 | ||
a38bba38 | 5123 | case 0xe8: /* call im */ |
cf648174 HZ |
5124 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5125 | ir.dflag = 2; | |
5126 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5127 | return -1; | |
7ad10968 HZ |
5128 | break; |
5129 | ||
a38bba38 | 5130 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5131 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5132 | { | |
5133 | ir.addr -= 1; | |
5134 | goto no_support; | |
5135 | } | |
5136 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5137 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5138 | return -1; | |
7ad10968 HZ |
5139 | break; |
5140 | ||
a38bba38 MS |
5141 | case 0xe9: /* jmp im */ |
5142 | case 0xea: /* ljmp im */ | |
5143 | case 0xeb: /* jmp Jb */ | |
5144 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5145 | case 0x71: |
5146 | case 0x72: | |
5147 | case 0x73: | |
5148 | case 0x74: | |
5149 | case 0x75: | |
5150 | case 0x76: | |
5151 | case 0x77: | |
5152 | case 0x78: | |
5153 | case 0x79: | |
5154 | case 0x7a: | |
5155 | case 0x7b: | |
5156 | case 0x7c: | |
5157 | case 0x7d: | |
5158 | case 0x7e: | |
5159 | case 0x7f: | |
a38bba38 | 5160 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5161 | case 0x0f81: |
5162 | case 0x0f82: | |
5163 | case 0x0f83: | |
5164 | case 0x0f84: | |
5165 | case 0x0f85: | |
5166 | case 0x0f86: | |
5167 | case 0x0f87: | |
5168 | case 0x0f88: | |
5169 | case 0x0f89: | |
5170 | case 0x0f8a: | |
5171 | case 0x0f8b: | |
5172 | case 0x0f8c: | |
5173 | case 0x0f8d: | |
5174 | case 0x0f8e: | |
5175 | case 0x0f8f: | |
5176 | break; | |
5177 | ||
a38bba38 | 5178 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5179 | case 0x0f91: |
5180 | case 0x0f92: | |
5181 | case 0x0f93: | |
5182 | case 0x0f94: | |
5183 | case 0x0f95: | |
5184 | case 0x0f96: | |
5185 | case 0x0f97: | |
5186 | case 0x0f98: | |
5187 | case 0x0f99: | |
5188 | case 0x0f9a: | |
5189 | case 0x0f9b: | |
5190 | case 0x0f9c: | |
5191 | case 0x0f9d: | |
5192 | case 0x0f9e: | |
5193 | case 0x0f9f: | |
cf648174 | 5194 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5195 | ir.ot = OT_BYTE; |
5196 | if (i386_record_modrm (&ir)) | |
5197 | return -1; | |
5198 | if (ir.mod == 3) | |
cf648174 HZ |
5199 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5200 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5201 | else |
5202 | { | |
5203 | if (i386_record_lea_modrm (&ir)) | |
5204 | return -1; | |
5205 | } | |
5206 | break; | |
5207 | ||
a38bba38 | 5208 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5209 | case 0x0f41: |
5210 | case 0x0f42: | |
5211 | case 0x0f43: | |
5212 | case 0x0f44: | |
5213 | case 0x0f45: | |
5214 | case 0x0f46: | |
5215 | case 0x0f47: | |
5216 | case 0x0f48: | |
5217 | case 0x0f49: | |
5218 | case 0x0f4a: | |
5219 | case 0x0f4b: | |
5220 | case 0x0f4c: | |
5221 | case 0x0f4d: | |
5222 | case 0x0f4e: | |
5223 | case 0x0f4f: | |
5224 | if (i386_record_modrm (&ir)) | |
5225 | return -1; | |
cf648174 | 5226 | ir.reg |= rex_r; |
7ad10968 HZ |
5227 | if (ir.dflag == OT_BYTE) |
5228 | ir.reg &= 0x3; | |
cf648174 | 5229 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5230 | break; |
5231 | ||
5232 | /* flags */ | |
a38bba38 | 5233 | case 0x9c: /* pushf */ |
cf648174 HZ |
5234 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5235 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5236 | ir.dflag = 2; | |
5237 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5238 | return -1; | |
7ad10968 HZ |
5239 | break; |
5240 | ||
a38bba38 | 5241 | case 0x9d: /* popf */ |
cf648174 HZ |
5242 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5243 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5244 | break; |
5245 | ||
a38bba38 | 5246 | case 0x9e: /* sahf */ |
cf648174 HZ |
5247 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5248 | { | |
5249 | ir.addr -= 1; | |
5250 | goto no_support; | |
5251 | } | |
a38bba38 MS |
5252 | case 0xf5: /* cmc */ |
5253 | case 0xf8: /* clc */ | |
5254 | case 0xf9: /* stc */ | |
5255 | case 0xfc: /* cld */ | |
5256 | case 0xfd: /* std */ | |
cf648174 | 5257 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5258 | break; |
5259 | ||
a38bba38 | 5260 | case 0x9f: /* lahf */ |
cf648174 HZ |
5261 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5262 | { | |
5263 | ir.addr -= 1; | |
5264 | goto no_support; | |
5265 | } | |
5266 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5267 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5268 | break; |
5269 | ||
5270 | /* bit operations */ | |
a38bba38 | 5271 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5272 | ir.ot = ir.dflag + OT_WORD; |
5273 | if (i386_record_modrm (&ir)) | |
5274 | return -1; | |
5275 | if (ir.reg < 4) | |
5276 | { | |
cf648174 | 5277 | ir.addr -= 2; |
7ad10968 HZ |
5278 | opcode = opcode << 8 | ir.modrm; |
5279 | goto no_support; | |
5280 | } | |
cf648174 | 5281 | if (ir.reg != 4) |
7ad10968 | 5282 | { |
cf648174 HZ |
5283 | if (ir.mod == 3) |
5284 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5285 | else |
5286 | { | |
cf648174 | 5287 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5288 | return -1; |
5289 | } | |
5290 | } | |
cf648174 | 5291 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5292 | break; |
5293 | ||
a38bba38 | 5294 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5295 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5296 | break; | |
5297 | ||
a38bba38 MS |
5298 | case 0x0fab: /* bts */ |
5299 | case 0x0fb3: /* btr */ | |
5300 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5301 | ir.ot = ir.dflag + OT_WORD; |
5302 | if (i386_record_modrm (&ir)) | |
5303 | return -1; | |
5304 | if (ir.mod == 3) | |
5305 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5306 | else | |
5307 | { | |
955db0c0 MS |
5308 | uint64_t addr64; |
5309 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5310 | return -1; |
5311 | regcache_raw_read_unsigned (ir.regcache, | |
5312 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5313 | &addr); |
cf648174 HZ |
5314 | switch (ir.dflag) |
5315 | { | |
5316 | case 0: | |
648d0c8b | 5317 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5318 | break; |
5319 | case 1: | |
648d0c8b | 5320 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5321 | break; |
5322 | case 2: | |
648d0c8b | 5323 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5324 | break; |
5325 | } | |
955db0c0 | 5326 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5327 | return -1; |
5328 | if (i386_record_lea_modrm (&ir)) | |
5329 | return -1; | |
5330 | } | |
5331 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5332 | break; |
5333 | ||
a38bba38 MS |
5334 | case 0x0fbc: /* bsf */ |
5335 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5336 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5337 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5338 | break; |
5339 | ||
5340 | /* bcd */ | |
a38bba38 MS |
5341 | case 0x27: /* daa */ |
5342 | case 0x2f: /* das */ | |
5343 | case 0x37: /* aaa */ | |
5344 | case 0x3f: /* aas */ | |
5345 | case 0xd4: /* aam */ | |
5346 | case 0xd5: /* aad */ | |
cf648174 HZ |
5347 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5348 | { | |
5349 | ir.addr -= 1; | |
5350 | goto no_support; | |
5351 | } | |
5352 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5353 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5354 | break; |
5355 | ||
5356 | /* misc */ | |
a38bba38 | 5357 | case 0x90: /* nop */ |
7ad10968 HZ |
5358 | if (prefixes & PREFIX_LOCK) |
5359 | { | |
5360 | ir.addr -= 1; | |
5361 | goto no_support; | |
5362 | } | |
5363 | break; | |
5364 | ||
a38bba38 | 5365 | case 0x9b: /* fwait */ |
425b824a | 5366 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5367 | { |
5368 | if (record_debug) | |
5369 | printf_unfiltered (_("Process record: error reading memory at " | |
5370 | "addr 0x%s len = 1.\n"), | |
5371 | paddress (gdbarch, ir.addr)); | |
5372 | return -1; | |
5373 | } | |
425b824a | 5374 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5375 | ir.addr++; |
5376 | goto reswitch; | |
7ad10968 HZ |
5377 | break; |
5378 | ||
7ad10968 | 5379 | /* XXX */ |
a38bba38 | 5380 | case 0xcc: /* int3 */ |
a3c4230a | 5381 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
5382 | "int3.\n")); |
5383 | ir.addr -= 1; | |
5384 | goto no_support; | |
5385 | break; | |
5386 | ||
7ad10968 | 5387 | /* XXX */ |
a38bba38 | 5388 | case 0xcd: /* int */ |
7ad10968 HZ |
5389 | { |
5390 | int ret; | |
425b824a MS |
5391 | uint8_t interrupt; |
5392 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5393 | { |
5394 | if (record_debug) | |
5395 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5396 | "at addr %s len = 1.\n"), |
5397 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5398 | return -1; |
5399 | } | |
5400 | ir.addr++; | |
425b824a | 5401 | if (interrupt != 0x80 |
a3c4230a | 5402 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 5403 | { |
a3c4230a | 5404 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 5405 | "instruction int 0x%02x.\n"), |
425b824a | 5406 | interrupt); |
7ad10968 HZ |
5407 | ir.addr -= 2; |
5408 | goto no_support; | |
5409 | } | |
a3c4230a | 5410 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
5411 | if (ret) |
5412 | return ret; | |
5413 | } | |
5414 | break; | |
5415 | ||
7ad10968 | 5416 | /* XXX */ |
a38bba38 | 5417 | case 0xce: /* into */ |
a3c4230a | 5418 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5419 | "instruction into.\n")); |
5420 | ir.addr -= 1; | |
5421 | goto no_support; | |
5422 | break; | |
5423 | ||
a38bba38 MS |
5424 | case 0xfa: /* cli */ |
5425 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5426 | break; |
5427 | ||
a38bba38 | 5428 | case 0x62: /* bound */ |
a3c4230a | 5429 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5430 | "instruction bound.\n")); |
5431 | ir.addr -= 1; | |
5432 | goto no_support; | |
5433 | break; | |
5434 | ||
a38bba38 | 5435 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5436 | case 0x0fc9: |
5437 | case 0x0fca: | |
5438 | case 0x0fcb: | |
5439 | case 0x0fcc: | |
5440 | case 0x0fcd: | |
5441 | case 0x0fce: | |
5442 | case 0x0fcf: | |
cf648174 | 5443 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5444 | break; |
5445 | ||
a38bba38 | 5446 | case 0xd6: /* salc */ |
cf648174 HZ |
5447 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5448 | { | |
5449 | ir.addr -= 1; | |
5450 | goto no_support; | |
5451 | } | |
5452 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5453 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5454 | break; |
5455 | ||
a38bba38 MS |
5456 | case 0xe0: /* loopnz */ |
5457 | case 0xe1: /* loopz */ | |
5458 | case 0xe2: /* loop */ | |
5459 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5460 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5461 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5462 | break; |
5463 | ||
a38bba38 | 5464 | case 0x0f30: /* wrmsr */ |
a3c4230a | 5465 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5466 | "instruction wrmsr.\n")); |
5467 | ir.addr -= 2; | |
5468 | goto no_support; | |
5469 | break; | |
5470 | ||
a38bba38 | 5471 | case 0x0f32: /* rdmsr */ |
a3c4230a | 5472 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5473 | "instruction rdmsr.\n")); |
5474 | ir.addr -= 2; | |
5475 | goto no_support; | |
5476 | break; | |
5477 | ||
a38bba38 | 5478 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
5479 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5480 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5481 | break; |
5482 | ||
a38bba38 | 5483 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5484 | { |
5485 | int ret; | |
cf648174 HZ |
5486 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5487 | { | |
5488 | ir.addr -= 2; | |
5489 | goto no_support; | |
5490 | } | |
a3c4230a | 5491 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 5492 | { |
a3c4230a | 5493 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5494 | "instruction sysenter.\n")); |
5495 | ir.addr -= 2; | |
5496 | goto no_support; | |
5497 | } | |
a3c4230a | 5498 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
5499 | if (ret) |
5500 | return ret; | |
5501 | } | |
5502 | break; | |
5503 | ||
a38bba38 | 5504 | case 0x0f35: /* sysexit */ |
a3c4230a | 5505 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5506 | "instruction sysexit.\n")); |
5507 | ir.addr -= 2; | |
5508 | goto no_support; | |
5509 | break; | |
5510 | ||
a38bba38 | 5511 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5512 | { |
5513 | int ret; | |
a3c4230a | 5514 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 5515 | { |
a3c4230a | 5516 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5517 | "instruction syscall.\n")); |
5518 | ir.addr -= 2; | |
5519 | goto no_support; | |
5520 | } | |
a3c4230a | 5521 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
5522 | if (ret) |
5523 | return ret; | |
5524 | } | |
5525 | break; | |
5526 | ||
a38bba38 | 5527 | case 0x0f07: /* sysret */ |
a3c4230a | 5528 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5529 | "instruction sysret.\n")); |
5530 | ir.addr -= 2; | |
5531 | goto no_support; | |
5532 | break; | |
5533 | ||
a38bba38 | 5534 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5535 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5536 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5537 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5538 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5539 | break; |
5540 | ||
a38bba38 | 5541 | case 0xf4: /* hlt */ |
a3c4230a | 5542 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5543 | "instruction hlt.\n")); |
5544 | ir.addr -= 1; | |
5545 | goto no_support; | |
5546 | break; | |
5547 | ||
5548 | case 0x0f00: | |
5549 | if (i386_record_modrm (&ir)) | |
5550 | return -1; | |
5551 | switch (ir.reg) | |
5552 | { | |
a38bba38 MS |
5553 | case 0: /* sldt */ |
5554 | case 1: /* str */ | |
7ad10968 | 5555 | if (ir.mod == 3) |
cf648174 | 5556 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5557 | else |
5558 | { | |
5559 | ir.ot = OT_WORD; | |
5560 | if (i386_record_lea_modrm (&ir)) | |
5561 | return -1; | |
5562 | } | |
5563 | break; | |
a38bba38 MS |
5564 | case 2: /* lldt */ |
5565 | case 3: /* ltr */ | |
7ad10968 | 5566 | break; |
a38bba38 MS |
5567 | case 4: /* verr */ |
5568 | case 5: /* verw */ | |
cf648174 | 5569 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5570 | break; |
5571 | default: | |
5572 | ir.addr -= 3; | |
5573 | opcode = opcode << 8 | ir.modrm; | |
5574 | goto no_support; | |
5575 | break; | |
5576 | } | |
5577 | break; | |
5578 | ||
5579 | case 0x0f01: | |
5580 | if (i386_record_modrm (&ir)) | |
5581 | return -1; | |
5582 | switch (ir.reg) | |
5583 | { | |
a38bba38 | 5584 | case 0: /* sgdt */ |
7ad10968 | 5585 | { |
955db0c0 | 5586 | uint64_t addr64; |
7ad10968 HZ |
5587 | |
5588 | if (ir.mod == 3) | |
5589 | { | |
5590 | ir.addr -= 3; | |
5591 | opcode = opcode << 8 | ir.modrm; | |
5592 | goto no_support; | |
5593 | } | |
d7877f7e | 5594 | if (ir.override >= 0) |
7ad10968 | 5595 | { |
df61f520 HZ |
5596 | warning (_("Process record ignores the memory " |
5597 | "change of instruction at " | |
5598 | "address %s because it can't get " | |
5599 | "the value of the segment " | |
5600 | "register."), | |
5601 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5602 | } |
5603 | else | |
5604 | { | |
955db0c0 | 5605 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5606 | return -1; |
955db0c0 | 5607 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5608 | return -1; |
955db0c0 | 5609 | addr64 += 2; |
cf648174 HZ |
5610 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5611 | { | |
955db0c0 | 5612 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5613 | return -1; |
5614 | } | |
5615 | else | |
5616 | { | |
955db0c0 | 5617 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5618 | return -1; |
5619 | } | |
7ad10968 HZ |
5620 | } |
5621 | } | |
5622 | break; | |
5623 | case 1: | |
5624 | if (ir.mod == 3) | |
5625 | { | |
5626 | switch (ir.rm) | |
5627 | { | |
a38bba38 | 5628 | case 0: /* monitor */ |
7ad10968 | 5629 | break; |
a38bba38 | 5630 | case 1: /* mwait */ |
cf648174 | 5631 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5632 | break; |
5633 | default: | |
5634 | ir.addr -= 3; | |
5635 | opcode = opcode << 8 | ir.modrm; | |
5636 | goto no_support; | |
5637 | break; | |
5638 | } | |
5639 | } | |
5640 | else | |
5641 | { | |
5642 | /* sidt */ | |
d7877f7e | 5643 | if (ir.override >= 0) |
7ad10968 | 5644 | { |
df61f520 HZ |
5645 | warning (_("Process record ignores the memory " |
5646 | "change of instruction at " | |
5647 | "address %s because it can't get " | |
5648 | "the value of the segment " | |
5649 | "register."), | |
5650 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5651 | } |
5652 | else | |
5653 | { | |
955db0c0 | 5654 | uint64_t addr64; |
7ad10968 | 5655 | |
955db0c0 | 5656 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 5657 | return -1; |
955db0c0 | 5658 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5659 | return -1; |
955db0c0 | 5660 | addr64 += 2; |
cf648174 HZ |
5661 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5662 | { | |
955db0c0 | 5663 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
5664 | return -1; |
5665 | } | |
5666 | else | |
5667 | { | |
955db0c0 | 5668 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
5669 | return -1; |
5670 | } | |
7ad10968 HZ |
5671 | } |
5672 | } | |
5673 | break; | |
a38bba38 | 5674 | case 2: /* lgdt */ |
3800e645 MS |
5675 | if (ir.mod == 3) |
5676 | { | |
5677 | /* xgetbv */ | |
5678 | if (ir.rm == 0) | |
5679 | { | |
5680 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5681 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5682 | break; | |
5683 | } | |
5684 | /* xsetbv */ | |
5685 | else if (ir.rm == 1) | |
5686 | break; | |
5687 | } | |
a38bba38 | 5688 | case 3: /* lidt */ |
7ad10968 HZ |
5689 | if (ir.mod == 3) |
5690 | { | |
5691 | ir.addr -= 3; | |
5692 | opcode = opcode << 8 | ir.modrm; | |
5693 | goto no_support; | |
5694 | } | |
5695 | break; | |
a38bba38 | 5696 | case 4: /* smsw */ |
7ad10968 HZ |
5697 | if (ir.mod == 3) |
5698 | { | |
cf648174 | 5699 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5700 | return -1; |
5701 | } | |
5702 | else | |
5703 | { | |
5704 | ir.ot = OT_WORD; | |
5705 | if (i386_record_lea_modrm (&ir)) | |
5706 | return -1; | |
5707 | } | |
cf648174 | 5708 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5709 | break; |
a38bba38 | 5710 | case 6: /* lmsw */ |
cf648174 HZ |
5711 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5712 | break; | |
a38bba38 | 5713 | case 7: /* invlpg */ |
cf648174 HZ |
5714 | if (ir.mod == 3) |
5715 | { | |
5716 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5717 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5718 | else | |
5719 | { | |
5720 | ir.addr -= 3; | |
5721 | opcode = opcode << 8 | ir.modrm; | |
5722 | goto no_support; | |
5723 | } | |
5724 | } | |
5725 | else | |
5726 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5727 | break; | |
5728 | default: | |
5729 | ir.addr -= 3; | |
5730 | opcode = opcode << 8 | ir.modrm; | |
5731 | goto no_support; | |
7ad10968 HZ |
5732 | break; |
5733 | } | |
5734 | break; | |
5735 | ||
a38bba38 MS |
5736 | case 0x0f08: /* invd */ |
5737 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5738 | break; |
5739 | ||
a38bba38 | 5740 | case 0x63: /* arpl */ |
7ad10968 HZ |
5741 | if (i386_record_modrm (&ir)) |
5742 | return -1; | |
cf648174 HZ |
5743 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5744 | { | |
5745 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5746 | ? (ir.reg | rex_r) : ir.rm); | |
5747 | } | |
7ad10968 | 5748 | else |
cf648174 HZ |
5749 | { |
5750 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5751 | if (i386_record_lea_modrm (&ir)) | |
5752 | return -1; | |
5753 | } | |
5754 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5755 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5756 | break; |
5757 | ||
a38bba38 MS |
5758 | case 0x0f02: /* lar */ |
5759 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5760 | if (i386_record_modrm (&ir)) |
5761 | return -1; | |
cf648174 HZ |
5762 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5763 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5764 | break; |
5765 | ||
5766 | case 0x0f18: | |
cf648174 HZ |
5767 | if (i386_record_modrm (&ir)) |
5768 | return -1; | |
5769 | if (ir.mod == 3 && ir.reg == 3) | |
5770 | { | |
5771 | ir.addr -= 3; | |
5772 | opcode = opcode << 8 | ir.modrm; | |
5773 | goto no_support; | |
5774 | } | |
7ad10968 HZ |
5775 | break; |
5776 | ||
7ad10968 HZ |
5777 | case 0x0f19: |
5778 | case 0x0f1a: | |
5779 | case 0x0f1b: | |
5780 | case 0x0f1c: | |
5781 | case 0x0f1d: | |
5782 | case 0x0f1e: | |
5783 | case 0x0f1f: | |
a38bba38 | 5784 | /* nop (multi byte) */ |
7ad10968 HZ |
5785 | break; |
5786 | ||
a38bba38 MS |
5787 | case 0x0f20: /* mov reg, crN */ |
5788 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5789 | if (i386_record_modrm (&ir)) |
5790 | return -1; | |
5791 | if ((ir.modrm & 0xc0) != 0xc0) | |
5792 | { | |
cf648174 | 5793 | ir.addr -= 3; |
7ad10968 HZ |
5794 | opcode = opcode << 8 | ir.modrm; |
5795 | goto no_support; | |
5796 | } | |
5797 | switch (ir.reg) | |
5798 | { | |
5799 | case 0: | |
5800 | case 2: | |
5801 | case 3: | |
5802 | case 4: | |
5803 | case 8: | |
5804 | if (opcode & 2) | |
cf648174 | 5805 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5806 | else |
cf648174 | 5807 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5808 | break; |
5809 | default: | |
cf648174 | 5810 | ir.addr -= 3; |
7ad10968 HZ |
5811 | opcode = opcode << 8 | ir.modrm; |
5812 | goto no_support; | |
5813 | break; | |
5814 | } | |
5815 | break; | |
5816 | ||
a38bba38 MS |
5817 | case 0x0f21: /* mov reg, drN */ |
5818 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5819 | if (i386_record_modrm (&ir)) |
5820 | return -1; | |
5821 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5822 | || ir.reg == 5 || ir.reg >= 8) | |
5823 | { | |
cf648174 | 5824 | ir.addr -= 3; |
7ad10968 HZ |
5825 | opcode = opcode << 8 | ir.modrm; |
5826 | goto no_support; | |
5827 | } | |
5828 | if (opcode & 2) | |
cf648174 | 5829 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5830 | else |
cf648174 | 5831 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5832 | break; |
5833 | ||
a38bba38 | 5834 | case 0x0f06: /* clts */ |
cf648174 | 5835 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5836 | break; |
5837 | ||
a3c4230a HZ |
5838 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
5839 | ||
5840 | case 0x0f0d: /* 3DNow! prefetch */ | |
5841 | break; | |
5842 | ||
5843 | case 0x0f0e: /* 3DNow! femms */ | |
5844 | case 0x0f77: /* emms */ | |
5845 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
5846 | goto no_support; | |
5847 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
5848 | break; | |
5849 | ||
5850 | case 0x0f0f: /* 3DNow! data */ | |
5851 | if (i386_record_modrm (&ir)) | |
5852 | return -1; | |
5853 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
5854 | { | |
5855 | printf_unfiltered (_("Process record: error reading memory at " | |
5856 | "addr %s len = 1.\n"), | |
5857 | paddress (gdbarch, ir.addr)); | |
5858 | return -1; | |
5859 | } | |
5860 | ir.addr++; | |
5861 | switch (opcode8) | |
5862 | { | |
5863 | case 0x0c: /* 3DNow! pi2fw */ | |
5864 | case 0x0d: /* 3DNow! pi2fd */ | |
5865 | case 0x1c: /* 3DNow! pf2iw */ | |
5866 | case 0x1d: /* 3DNow! pf2id */ | |
5867 | case 0x8a: /* 3DNow! pfnacc */ | |
5868 | case 0x8e: /* 3DNow! pfpnacc */ | |
5869 | case 0x90: /* 3DNow! pfcmpge */ | |
5870 | case 0x94: /* 3DNow! pfmin */ | |
5871 | case 0x96: /* 3DNow! pfrcp */ | |
5872 | case 0x97: /* 3DNow! pfrsqrt */ | |
5873 | case 0x9a: /* 3DNow! pfsub */ | |
5874 | case 0x9e: /* 3DNow! pfadd */ | |
5875 | case 0xa0: /* 3DNow! pfcmpgt */ | |
5876 | case 0xa4: /* 3DNow! pfmax */ | |
5877 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
5878 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
5879 | case 0xaa: /* 3DNow! pfsubr */ | |
5880 | case 0xae: /* 3DNow! pfacc */ | |
5881 | case 0xb0: /* 3DNow! pfcmpeq */ | |
5882 | case 0xb4: /* 3DNow! pfmul */ | |
5883 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
5884 | case 0xb7: /* 3DNow! pmulhrw */ | |
5885 | case 0xbb: /* 3DNow! pswapd */ | |
5886 | case 0xbf: /* 3DNow! pavgusb */ | |
5887 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
5888 | goto no_support_3dnow_data; | |
5889 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
5890 | break; | |
5891 | ||
5892 | default: | |
5893 | no_support_3dnow_data: | |
5894 | opcode = (opcode << 8) | opcode8; | |
5895 | goto no_support; | |
5896 | break; | |
5897 | } | |
5898 | break; | |
5899 | ||
5900 | case 0x0faa: /* rsm */ | |
5901 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5902 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5903 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5904 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5905 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
5906 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5907 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
5908 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5909 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5910 | break; | |
5911 | ||
5912 | case 0x0fae: | |
5913 | if (i386_record_modrm (&ir)) | |
5914 | return -1; | |
5915 | switch(ir.reg) | |
5916 | { | |
5917 | case 0: /* fxsave */ | |
5918 | { | |
5919 | uint64_t tmpu64; | |
5920 | ||
5921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5922 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
5923 | return -1; | |
5924 | if (record_arch_list_add_mem (tmpu64, 512)) | |
5925 | return -1; | |
5926 | } | |
5927 | break; | |
5928 | ||
5929 | case 1: /* fxrstor */ | |
5930 | { | |
5931 | int i; | |
5932 | ||
5933 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5934 | ||
5935 | for (i = I387_MM0_REGNUM (tdep); | |
5936 | i386_mmx_regnum_p (gdbarch, i); i++) | |
5937 | record_arch_list_add_reg (ir.regcache, i); | |
5938 | ||
5939 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 5940 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
5941 | record_arch_list_add_reg (ir.regcache, i); |
5942 | ||
5943 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
5944 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
5945 | ||
5946 | for (i = I387_ST0_REGNUM (tdep); | |
5947 | i386_fp_regnum_p (gdbarch, i); i++) | |
5948 | record_arch_list_add_reg (ir.regcache, i); | |
5949 | ||
5950 | for (i = I387_FCTRL_REGNUM (tdep); | |
5951 | i386_fpc_regnum_p (gdbarch, i); i++) | |
5952 | record_arch_list_add_reg (ir.regcache, i); | |
5953 | } | |
5954 | break; | |
5955 | ||
5956 | case 2: /* ldmxcsr */ | |
5957 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
5958 | goto no_support; | |
5959 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
5960 | break; | |
5961 | ||
5962 | case 3: /* stmxcsr */ | |
5963 | ir.ot = OT_LONG; | |
5964 | if (i386_record_lea_modrm (&ir)) | |
5965 | return -1; | |
5966 | break; | |
5967 | ||
5968 | case 5: /* lfence */ | |
5969 | case 6: /* mfence */ | |
5970 | case 7: /* sfence clflush */ | |
5971 | break; | |
5972 | ||
5973 | default: | |
5974 | opcode = (opcode << 8) | ir.modrm; | |
5975 | goto no_support; | |
5976 | break; | |
5977 | } | |
5978 | break; | |
5979 | ||
5980 | case 0x0fc3: /* movnti */ | |
5981 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
5982 | if (i386_record_modrm (&ir)) | |
5983 | return -1; | |
5984 | if (ir.mod == 3) | |
5985 | goto no_support; | |
5986 | ir.reg |= rex_r; | |
5987 | if (i386_record_lea_modrm (&ir)) | |
5988 | return -1; | |
5989 | break; | |
5990 | ||
5991 | /* Add prefix to opcode. */ | |
5992 | case 0x0f10: | |
5993 | case 0x0f11: | |
5994 | case 0x0f12: | |
5995 | case 0x0f13: | |
5996 | case 0x0f14: | |
5997 | case 0x0f15: | |
5998 | case 0x0f16: | |
5999 | case 0x0f17: | |
6000 | case 0x0f28: | |
6001 | case 0x0f29: | |
6002 | case 0x0f2a: | |
6003 | case 0x0f2b: | |
6004 | case 0x0f2c: | |
6005 | case 0x0f2d: | |
6006 | case 0x0f2e: | |
6007 | case 0x0f2f: | |
6008 | case 0x0f38: | |
6009 | case 0x0f39: | |
6010 | case 0x0f3a: | |
6011 | case 0x0f50: | |
6012 | case 0x0f51: | |
6013 | case 0x0f52: | |
6014 | case 0x0f53: | |
6015 | case 0x0f54: | |
6016 | case 0x0f55: | |
6017 | case 0x0f56: | |
6018 | case 0x0f57: | |
6019 | case 0x0f58: | |
6020 | case 0x0f59: | |
6021 | case 0x0f5a: | |
6022 | case 0x0f5b: | |
6023 | case 0x0f5c: | |
6024 | case 0x0f5d: | |
6025 | case 0x0f5e: | |
6026 | case 0x0f5f: | |
6027 | case 0x0f60: | |
6028 | case 0x0f61: | |
6029 | case 0x0f62: | |
6030 | case 0x0f63: | |
6031 | case 0x0f64: | |
6032 | case 0x0f65: | |
6033 | case 0x0f66: | |
6034 | case 0x0f67: | |
6035 | case 0x0f68: | |
6036 | case 0x0f69: | |
6037 | case 0x0f6a: | |
6038 | case 0x0f6b: | |
6039 | case 0x0f6c: | |
6040 | case 0x0f6d: | |
6041 | case 0x0f6e: | |
6042 | case 0x0f6f: | |
6043 | case 0x0f70: | |
6044 | case 0x0f71: | |
6045 | case 0x0f72: | |
6046 | case 0x0f73: | |
6047 | case 0x0f74: | |
6048 | case 0x0f75: | |
6049 | case 0x0f76: | |
6050 | case 0x0f7c: | |
6051 | case 0x0f7d: | |
6052 | case 0x0f7e: | |
6053 | case 0x0f7f: | |
6054 | case 0x0fb8: | |
6055 | case 0x0fc2: | |
6056 | case 0x0fc4: | |
6057 | case 0x0fc5: | |
6058 | case 0x0fc6: | |
6059 | case 0x0fd0: | |
6060 | case 0x0fd1: | |
6061 | case 0x0fd2: | |
6062 | case 0x0fd3: | |
6063 | case 0x0fd4: | |
6064 | case 0x0fd5: | |
6065 | case 0x0fd6: | |
6066 | case 0x0fd7: | |
6067 | case 0x0fd8: | |
6068 | case 0x0fd9: | |
6069 | case 0x0fda: | |
6070 | case 0x0fdb: | |
6071 | case 0x0fdc: | |
6072 | case 0x0fdd: | |
6073 | case 0x0fde: | |
6074 | case 0x0fdf: | |
6075 | case 0x0fe0: | |
6076 | case 0x0fe1: | |
6077 | case 0x0fe2: | |
6078 | case 0x0fe3: | |
6079 | case 0x0fe4: | |
6080 | case 0x0fe5: | |
6081 | case 0x0fe6: | |
6082 | case 0x0fe7: | |
6083 | case 0x0fe8: | |
6084 | case 0x0fe9: | |
6085 | case 0x0fea: | |
6086 | case 0x0feb: | |
6087 | case 0x0fec: | |
6088 | case 0x0fed: | |
6089 | case 0x0fee: | |
6090 | case 0x0fef: | |
6091 | case 0x0ff0: | |
6092 | case 0x0ff1: | |
6093 | case 0x0ff2: | |
6094 | case 0x0ff3: | |
6095 | case 0x0ff4: | |
6096 | case 0x0ff5: | |
6097 | case 0x0ff6: | |
6098 | case 0x0ff7: | |
6099 | case 0x0ff8: | |
6100 | case 0x0ff9: | |
6101 | case 0x0ffa: | |
6102 | case 0x0ffb: | |
6103 | case 0x0ffc: | |
6104 | case 0x0ffd: | |
6105 | case 0x0ffe: | |
6106 | switch (prefixes) | |
6107 | { | |
6108 | case PREFIX_REPNZ: | |
6109 | opcode |= 0xf20000; | |
6110 | break; | |
6111 | case PREFIX_DATA: | |
6112 | opcode |= 0x660000; | |
6113 | break; | |
6114 | case PREFIX_REPZ: | |
6115 | opcode |= 0xf30000; | |
6116 | break; | |
6117 | } | |
6118 | reswitch_prefix_add: | |
6119 | switch (opcode) | |
6120 | { | |
6121 | case 0x0f38: | |
6122 | case 0x660f38: | |
6123 | case 0xf20f38: | |
6124 | case 0x0f3a: | |
6125 | case 0x660f3a: | |
6126 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6127 | { | |
6128 | printf_unfiltered (_("Process record: error reading memory at " | |
6129 | "addr %s len = 1.\n"), | |
6130 | paddress (gdbarch, ir.addr)); | |
6131 | return -1; | |
6132 | } | |
6133 | ir.addr++; | |
6134 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6135 | goto reswitch_prefix_add; | |
6136 | break; | |
6137 | ||
6138 | case 0x0f10: /* movups */ | |
6139 | case 0x660f10: /* movupd */ | |
6140 | case 0xf30f10: /* movss */ | |
6141 | case 0xf20f10: /* movsd */ | |
6142 | case 0x0f12: /* movlps */ | |
6143 | case 0x660f12: /* movlpd */ | |
6144 | case 0xf30f12: /* movsldup */ | |
6145 | case 0xf20f12: /* movddup */ | |
6146 | case 0x0f14: /* unpcklps */ | |
6147 | case 0x660f14: /* unpcklpd */ | |
6148 | case 0x0f15: /* unpckhps */ | |
6149 | case 0x660f15: /* unpckhpd */ | |
6150 | case 0x0f16: /* movhps */ | |
6151 | case 0x660f16: /* movhpd */ | |
6152 | case 0xf30f16: /* movshdup */ | |
6153 | case 0x0f28: /* movaps */ | |
6154 | case 0x660f28: /* movapd */ | |
6155 | case 0x0f2a: /* cvtpi2ps */ | |
6156 | case 0x660f2a: /* cvtpi2pd */ | |
6157 | case 0xf30f2a: /* cvtsi2ss */ | |
6158 | case 0xf20f2a: /* cvtsi2sd */ | |
6159 | case 0x0f2c: /* cvttps2pi */ | |
6160 | case 0x660f2c: /* cvttpd2pi */ | |
6161 | case 0x0f2d: /* cvtps2pi */ | |
6162 | case 0x660f2d: /* cvtpd2pi */ | |
6163 | case 0x660f3800: /* pshufb */ | |
6164 | case 0x660f3801: /* phaddw */ | |
6165 | case 0x660f3802: /* phaddd */ | |
6166 | case 0x660f3803: /* phaddsw */ | |
6167 | case 0x660f3804: /* pmaddubsw */ | |
6168 | case 0x660f3805: /* phsubw */ | |
6169 | case 0x660f3806: /* phsubd */ | |
6170 | case 0x660f3807: /* phaddsw */ | |
6171 | case 0x660f3808: /* psignb */ | |
6172 | case 0x660f3809: /* psignw */ | |
6173 | case 0x660f380a: /* psignd */ | |
6174 | case 0x660f380b: /* pmulhrsw */ | |
6175 | case 0x660f3810: /* pblendvb */ | |
6176 | case 0x660f3814: /* blendvps */ | |
6177 | case 0x660f3815: /* blendvpd */ | |
6178 | case 0x660f381c: /* pabsb */ | |
6179 | case 0x660f381d: /* pabsw */ | |
6180 | case 0x660f381e: /* pabsd */ | |
6181 | case 0x660f3820: /* pmovsxbw */ | |
6182 | case 0x660f3821: /* pmovsxbd */ | |
6183 | case 0x660f3822: /* pmovsxbq */ | |
6184 | case 0x660f3823: /* pmovsxwd */ | |
6185 | case 0x660f3824: /* pmovsxwq */ | |
6186 | case 0x660f3825: /* pmovsxdq */ | |
6187 | case 0x660f3828: /* pmuldq */ | |
6188 | case 0x660f3829: /* pcmpeqq */ | |
6189 | case 0x660f382a: /* movntdqa */ | |
6190 | case 0x660f3a08: /* roundps */ | |
6191 | case 0x660f3a09: /* roundpd */ | |
6192 | case 0x660f3a0a: /* roundss */ | |
6193 | case 0x660f3a0b: /* roundsd */ | |
6194 | case 0x660f3a0c: /* blendps */ | |
6195 | case 0x660f3a0d: /* blendpd */ | |
6196 | case 0x660f3a0e: /* pblendw */ | |
6197 | case 0x660f3a0f: /* palignr */ | |
6198 | case 0x660f3a20: /* pinsrb */ | |
6199 | case 0x660f3a21: /* insertps */ | |
6200 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6201 | case 0x660f3a40: /* dpps */ | |
6202 | case 0x660f3a41: /* dppd */ | |
6203 | case 0x660f3a42: /* mpsadbw */ | |
6204 | case 0x660f3a60: /* pcmpestrm */ | |
6205 | case 0x660f3a61: /* pcmpestri */ | |
6206 | case 0x660f3a62: /* pcmpistrm */ | |
6207 | case 0x660f3a63: /* pcmpistri */ | |
6208 | case 0x0f51: /* sqrtps */ | |
6209 | case 0x660f51: /* sqrtpd */ | |
6210 | case 0xf20f51: /* sqrtsd */ | |
6211 | case 0xf30f51: /* sqrtss */ | |
6212 | case 0x0f52: /* rsqrtps */ | |
6213 | case 0xf30f52: /* rsqrtss */ | |
6214 | case 0x0f53: /* rcpps */ | |
6215 | case 0xf30f53: /* rcpss */ | |
6216 | case 0x0f54: /* andps */ | |
6217 | case 0x660f54: /* andpd */ | |
6218 | case 0x0f55: /* andnps */ | |
6219 | case 0x660f55: /* andnpd */ | |
6220 | case 0x0f56: /* orps */ | |
6221 | case 0x660f56: /* orpd */ | |
6222 | case 0x0f57: /* xorps */ | |
6223 | case 0x660f57: /* xorpd */ | |
6224 | case 0x0f58: /* addps */ | |
6225 | case 0x660f58: /* addpd */ | |
6226 | case 0xf20f58: /* addsd */ | |
6227 | case 0xf30f58: /* addss */ | |
6228 | case 0x0f59: /* mulps */ | |
6229 | case 0x660f59: /* mulpd */ | |
6230 | case 0xf20f59: /* mulsd */ | |
6231 | case 0xf30f59: /* mulss */ | |
6232 | case 0x0f5a: /* cvtps2pd */ | |
6233 | case 0x660f5a: /* cvtpd2ps */ | |
6234 | case 0xf20f5a: /* cvtsd2ss */ | |
6235 | case 0xf30f5a: /* cvtss2sd */ | |
6236 | case 0x0f5b: /* cvtdq2ps */ | |
6237 | case 0x660f5b: /* cvtps2dq */ | |
6238 | case 0xf30f5b: /* cvttps2dq */ | |
6239 | case 0x0f5c: /* subps */ | |
6240 | case 0x660f5c: /* subpd */ | |
6241 | case 0xf20f5c: /* subsd */ | |
6242 | case 0xf30f5c: /* subss */ | |
6243 | case 0x0f5d: /* minps */ | |
6244 | case 0x660f5d: /* minpd */ | |
6245 | case 0xf20f5d: /* minsd */ | |
6246 | case 0xf30f5d: /* minss */ | |
6247 | case 0x0f5e: /* divps */ | |
6248 | case 0x660f5e: /* divpd */ | |
6249 | case 0xf20f5e: /* divsd */ | |
6250 | case 0xf30f5e: /* divss */ | |
6251 | case 0x0f5f: /* maxps */ | |
6252 | case 0x660f5f: /* maxpd */ | |
6253 | case 0xf20f5f: /* maxsd */ | |
6254 | case 0xf30f5f: /* maxss */ | |
6255 | case 0x660f60: /* punpcklbw */ | |
6256 | case 0x660f61: /* punpcklwd */ | |
6257 | case 0x660f62: /* punpckldq */ | |
6258 | case 0x660f63: /* packsswb */ | |
6259 | case 0x660f64: /* pcmpgtb */ | |
6260 | case 0x660f65: /* pcmpgtw */ | |
6261 | case 0x660f66: /* pcmpgtl */ | |
6262 | case 0x660f67: /* packuswb */ | |
6263 | case 0x660f68: /* punpckhbw */ | |
6264 | case 0x660f69: /* punpckhwd */ | |
6265 | case 0x660f6a: /* punpckhdq */ | |
6266 | case 0x660f6b: /* packssdw */ | |
6267 | case 0x660f6c: /* punpcklqdq */ | |
6268 | case 0x660f6d: /* punpckhqdq */ | |
6269 | case 0x660f6e: /* movd */ | |
6270 | case 0x660f6f: /* movdqa */ | |
6271 | case 0xf30f6f: /* movdqu */ | |
6272 | case 0x660f70: /* pshufd */ | |
6273 | case 0xf20f70: /* pshuflw */ | |
6274 | case 0xf30f70: /* pshufhw */ | |
6275 | case 0x660f74: /* pcmpeqb */ | |
6276 | case 0x660f75: /* pcmpeqw */ | |
6277 | case 0x660f76: /* pcmpeql */ | |
6278 | case 0x660f7c: /* haddpd */ | |
6279 | case 0xf20f7c: /* haddps */ | |
6280 | case 0x660f7d: /* hsubpd */ | |
6281 | case 0xf20f7d: /* hsubps */ | |
6282 | case 0xf30f7e: /* movq */ | |
6283 | case 0x0fc2: /* cmpps */ | |
6284 | case 0x660fc2: /* cmppd */ | |
6285 | case 0xf20fc2: /* cmpsd */ | |
6286 | case 0xf30fc2: /* cmpss */ | |
6287 | case 0x660fc4: /* pinsrw */ | |
6288 | case 0x0fc6: /* shufps */ | |
6289 | case 0x660fc6: /* shufpd */ | |
6290 | case 0x660fd0: /* addsubpd */ | |
6291 | case 0xf20fd0: /* addsubps */ | |
6292 | case 0x660fd1: /* psrlw */ | |
6293 | case 0x660fd2: /* psrld */ | |
6294 | case 0x660fd3: /* psrlq */ | |
6295 | case 0x660fd4: /* paddq */ | |
6296 | case 0x660fd5: /* pmullw */ | |
6297 | case 0xf30fd6: /* movq2dq */ | |
6298 | case 0x660fd8: /* psubusb */ | |
6299 | case 0x660fd9: /* psubusw */ | |
6300 | case 0x660fda: /* pminub */ | |
6301 | case 0x660fdb: /* pand */ | |
6302 | case 0x660fdc: /* paddusb */ | |
6303 | case 0x660fdd: /* paddusw */ | |
6304 | case 0x660fde: /* pmaxub */ | |
6305 | case 0x660fdf: /* pandn */ | |
6306 | case 0x660fe0: /* pavgb */ | |
6307 | case 0x660fe1: /* psraw */ | |
6308 | case 0x660fe2: /* psrad */ | |
6309 | case 0x660fe3: /* pavgw */ | |
6310 | case 0x660fe4: /* pmulhuw */ | |
6311 | case 0x660fe5: /* pmulhw */ | |
6312 | case 0x660fe6: /* cvttpd2dq */ | |
6313 | case 0xf20fe6: /* cvtpd2dq */ | |
6314 | case 0xf30fe6: /* cvtdq2pd */ | |
6315 | case 0x660fe8: /* psubsb */ | |
6316 | case 0x660fe9: /* psubsw */ | |
6317 | case 0x660fea: /* pminsw */ | |
6318 | case 0x660feb: /* por */ | |
6319 | case 0x660fec: /* paddsb */ | |
6320 | case 0x660fed: /* paddsw */ | |
6321 | case 0x660fee: /* pmaxsw */ | |
6322 | case 0x660fef: /* pxor */ | |
6323 | case 0x660ff0: /* lddqu */ | |
6324 | case 0x660ff1: /* psllw */ | |
6325 | case 0x660ff2: /* pslld */ | |
6326 | case 0x660ff3: /* psllq */ | |
6327 | case 0x660ff4: /* pmuludq */ | |
6328 | case 0x660ff5: /* pmaddwd */ | |
6329 | case 0x660ff6: /* psadbw */ | |
6330 | case 0x660ff8: /* psubb */ | |
6331 | case 0x660ff9: /* psubw */ | |
6332 | case 0x660ffa: /* psubl */ | |
6333 | case 0x660ffb: /* psubq */ | |
6334 | case 0x660ffc: /* paddb */ | |
6335 | case 0x660ffd: /* paddw */ | |
6336 | case 0x660ffe: /* paddl */ | |
6337 | if (i386_record_modrm (&ir)) | |
6338 | return -1; | |
6339 | ir.reg |= rex_r; | |
c131fcee | 6340 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
6341 | goto no_support; |
6342 | record_arch_list_add_reg (ir.regcache, | |
6343 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
6344 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
6345 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6346 | break; | |
6347 | ||
6348 | case 0x0f11: /* movups */ | |
6349 | case 0x660f11: /* movupd */ | |
6350 | case 0xf30f11: /* movss */ | |
6351 | case 0xf20f11: /* movsd */ | |
6352 | case 0x0f13: /* movlps */ | |
6353 | case 0x660f13: /* movlpd */ | |
6354 | case 0x0f17: /* movhps */ | |
6355 | case 0x660f17: /* movhpd */ | |
6356 | case 0x0f29: /* movaps */ | |
6357 | case 0x660f29: /* movapd */ | |
6358 | case 0x660f3a14: /* pextrb */ | |
6359 | case 0x660f3a15: /* pextrw */ | |
6360 | case 0x660f3a16: /* pextrd pextrq */ | |
6361 | case 0x660f3a17: /* extractps */ | |
6362 | case 0x660f7f: /* movdqa */ | |
6363 | case 0xf30f7f: /* movdqu */ | |
6364 | if (i386_record_modrm (&ir)) | |
6365 | return -1; | |
6366 | if (ir.mod == 3) | |
6367 | { | |
6368 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
6369 | || opcode == 0x0f17 || opcode == 0x660f17) | |
6370 | goto no_support; | |
6371 | ir.rm |= ir.rex_b; | |
c131fcee | 6372 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6373 | goto no_support; |
6374 | record_arch_list_add_reg (ir.regcache, | |
6375 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6376 | } | |
6377 | else | |
6378 | { | |
6379 | switch (opcode) | |
6380 | { | |
6381 | case 0x660f3a14: | |
6382 | ir.ot = OT_BYTE; | |
6383 | break; | |
6384 | case 0x660f3a15: | |
6385 | ir.ot = OT_WORD; | |
6386 | break; | |
6387 | case 0x660f3a16: | |
6388 | ir.ot = OT_LONG; | |
6389 | break; | |
6390 | case 0x660f3a17: | |
6391 | ir.ot = OT_QUAD; | |
6392 | break; | |
6393 | default: | |
6394 | ir.ot = OT_DQUAD; | |
6395 | break; | |
6396 | } | |
6397 | if (i386_record_lea_modrm (&ir)) | |
6398 | return -1; | |
6399 | } | |
6400 | break; | |
6401 | ||
6402 | case 0x0f2b: /* movntps */ | |
6403 | case 0x660f2b: /* movntpd */ | |
6404 | case 0x0fe7: /* movntq */ | |
6405 | case 0x660fe7: /* movntdq */ | |
6406 | if (ir.mod == 3) | |
6407 | goto no_support; | |
6408 | if (opcode == 0x0fe7) | |
6409 | ir.ot = OT_QUAD; | |
6410 | else | |
6411 | ir.ot = OT_DQUAD; | |
6412 | if (i386_record_lea_modrm (&ir)) | |
6413 | return -1; | |
6414 | break; | |
6415 | ||
6416 | case 0xf30f2c: /* cvttss2si */ | |
6417 | case 0xf20f2c: /* cvttsd2si */ | |
6418 | case 0xf30f2d: /* cvtss2si */ | |
6419 | case 0xf20f2d: /* cvtsd2si */ | |
6420 | case 0xf20f38f0: /* crc32 */ | |
6421 | case 0xf20f38f1: /* crc32 */ | |
6422 | case 0x0f50: /* movmskps */ | |
6423 | case 0x660f50: /* movmskpd */ | |
6424 | case 0x0fc5: /* pextrw */ | |
6425 | case 0x660fc5: /* pextrw */ | |
6426 | case 0x0fd7: /* pmovmskb */ | |
6427 | case 0x660fd7: /* pmovmskb */ | |
6428 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6429 | break; | |
6430 | ||
6431 | case 0x0f3800: /* pshufb */ | |
6432 | case 0x0f3801: /* phaddw */ | |
6433 | case 0x0f3802: /* phaddd */ | |
6434 | case 0x0f3803: /* phaddsw */ | |
6435 | case 0x0f3804: /* pmaddubsw */ | |
6436 | case 0x0f3805: /* phsubw */ | |
6437 | case 0x0f3806: /* phsubd */ | |
6438 | case 0x0f3807: /* phaddsw */ | |
6439 | case 0x0f3808: /* psignb */ | |
6440 | case 0x0f3809: /* psignw */ | |
6441 | case 0x0f380a: /* psignd */ | |
6442 | case 0x0f380b: /* pmulhrsw */ | |
6443 | case 0x0f381c: /* pabsb */ | |
6444 | case 0x0f381d: /* pabsw */ | |
6445 | case 0x0f381e: /* pabsd */ | |
6446 | case 0x0f382b: /* packusdw */ | |
6447 | case 0x0f3830: /* pmovzxbw */ | |
6448 | case 0x0f3831: /* pmovzxbd */ | |
6449 | case 0x0f3832: /* pmovzxbq */ | |
6450 | case 0x0f3833: /* pmovzxwd */ | |
6451 | case 0x0f3834: /* pmovzxwq */ | |
6452 | case 0x0f3835: /* pmovzxdq */ | |
6453 | case 0x0f3837: /* pcmpgtq */ | |
6454 | case 0x0f3838: /* pminsb */ | |
6455 | case 0x0f3839: /* pminsd */ | |
6456 | case 0x0f383a: /* pminuw */ | |
6457 | case 0x0f383b: /* pminud */ | |
6458 | case 0x0f383c: /* pmaxsb */ | |
6459 | case 0x0f383d: /* pmaxsd */ | |
6460 | case 0x0f383e: /* pmaxuw */ | |
6461 | case 0x0f383f: /* pmaxud */ | |
6462 | case 0x0f3840: /* pmulld */ | |
6463 | case 0x0f3841: /* phminposuw */ | |
6464 | case 0x0f3a0f: /* palignr */ | |
6465 | case 0x0f60: /* punpcklbw */ | |
6466 | case 0x0f61: /* punpcklwd */ | |
6467 | case 0x0f62: /* punpckldq */ | |
6468 | case 0x0f63: /* packsswb */ | |
6469 | case 0x0f64: /* pcmpgtb */ | |
6470 | case 0x0f65: /* pcmpgtw */ | |
6471 | case 0x0f66: /* pcmpgtl */ | |
6472 | case 0x0f67: /* packuswb */ | |
6473 | case 0x0f68: /* punpckhbw */ | |
6474 | case 0x0f69: /* punpckhwd */ | |
6475 | case 0x0f6a: /* punpckhdq */ | |
6476 | case 0x0f6b: /* packssdw */ | |
6477 | case 0x0f6e: /* movd */ | |
6478 | case 0x0f6f: /* movq */ | |
6479 | case 0x0f70: /* pshufw */ | |
6480 | case 0x0f74: /* pcmpeqb */ | |
6481 | case 0x0f75: /* pcmpeqw */ | |
6482 | case 0x0f76: /* pcmpeql */ | |
6483 | case 0x0fc4: /* pinsrw */ | |
6484 | case 0x0fd1: /* psrlw */ | |
6485 | case 0x0fd2: /* psrld */ | |
6486 | case 0x0fd3: /* psrlq */ | |
6487 | case 0x0fd4: /* paddq */ | |
6488 | case 0x0fd5: /* pmullw */ | |
6489 | case 0xf20fd6: /* movdq2q */ | |
6490 | case 0x0fd8: /* psubusb */ | |
6491 | case 0x0fd9: /* psubusw */ | |
6492 | case 0x0fda: /* pminub */ | |
6493 | case 0x0fdb: /* pand */ | |
6494 | case 0x0fdc: /* paddusb */ | |
6495 | case 0x0fdd: /* paddusw */ | |
6496 | case 0x0fde: /* pmaxub */ | |
6497 | case 0x0fdf: /* pandn */ | |
6498 | case 0x0fe0: /* pavgb */ | |
6499 | case 0x0fe1: /* psraw */ | |
6500 | case 0x0fe2: /* psrad */ | |
6501 | case 0x0fe3: /* pavgw */ | |
6502 | case 0x0fe4: /* pmulhuw */ | |
6503 | case 0x0fe5: /* pmulhw */ | |
6504 | case 0x0fe8: /* psubsb */ | |
6505 | case 0x0fe9: /* psubsw */ | |
6506 | case 0x0fea: /* pminsw */ | |
6507 | case 0x0feb: /* por */ | |
6508 | case 0x0fec: /* paddsb */ | |
6509 | case 0x0fed: /* paddsw */ | |
6510 | case 0x0fee: /* pmaxsw */ | |
6511 | case 0x0fef: /* pxor */ | |
6512 | case 0x0ff1: /* psllw */ | |
6513 | case 0x0ff2: /* pslld */ | |
6514 | case 0x0ff3: /* psllq */ | |
6515 | case 0x0ff4: /* pmuludq */ | |
6516 | case 0x0ff5: /* pmaddwd */ | |
6517 | case 0x0ff6: /* psadbw */ | |
6518 | case 0x0ff8: /* psubb */ | |
6519 | case 0x0ff9: /* psubw */ | |
6520 | case 0x0ffa: /* psubl */ | |
6521 | case 0x0ffb: /* psubq */ | |
6522 | case 0x0ffc: /* paddb */ | |
6523 | case 0x0ffd: /* paddw */ | |
6524 | case 0x0ffe: /* paddl */ | |
6525 | if (i386_record_modrm (&ir)) | |
6526 | return -1; | |
6527 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6528 | goto no_support; | |
6529 | record_arch_list_add_reg (ir.regcache, | |
6530 | I387_MM0_REGNUM (tdep) + ir.reg); | |
6531 | break; | |
6532 | ||
6533 | case 0x0f71: /* psllw */ | |
6534 | case 0x0f72: /* pslld */ | |
6535 | case 0x0f73: /* psllq */ | |
6536 | if (i386_record_modrm (&ir)) | |
6537 | return -1; | |
6538 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6539 | goto no_support; | |
6540 | record_arch_list_add_reg (ir.regcache, | |
6541 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6542 | break; | |
6543 | ||
6544 | case 0x660f71: /* psllw */ | |
6545 | case 0x660f72: /* pslld */ | |
6546 | case 0x660f73: /* psllq */ | |
6547 | if (i386_record_modrm (&ir)) | |
6548 | return -1; | |
6549 | ir.rm |= ir.rex_b; | |
c131fcee | 6550 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6551 | goto no_support; |
6552 | record_arch_list_add_reg (ir.regcache, | |
6553 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6554 | break; | |
6555 | ||
6556 | case 0x0f7e: /* movd */ | |
6557 | case 0x660f7e: /* movd */ | |
6558 | if (i386_record_modrm (&ir)) | |
6559 | return -1; | |
6560 | if (ir.mod == 3) | |
6561 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6562 | else | |
6563 | { | |
6564 | if (ir.dflag == 2) | |
6565 | ir.ot = OT_QUAD; | |
6566 | else | |
6567 | ir.ot = OT_LONG; | |
6568 | if (i386_record_lea_modrm (&ir)) | |
6569 | return -1; | |
6570 | } | |
6571 | break; | |
6572 | ||
6573 | case 0x0f7f: /* movq */ | |
6574 | if (i386_record_modrm (&ir)) | |
6575 | return -1; | |
6576 | if (ir.mod == 3) | |
6577 | { | |
6578 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6579 | goto no_support; | |
6580 | record_arch_list_add_reg (ir.regcache, | |
6581 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6582 | } | |
6583 | else | |
6584 | { | |
6585 | ir.ot = OT_QUAD; | |
6586 | if (i386_record_lea_modrm (&ir)) | |
6587 | return -1; | |
6588 | } | |
6589 | break; | |
6590 | ||
6591 | case 0xf30fb8: /* popcnt */ | |
6592 | if (i386_record_modrm (&ir)) | |
6593 | return -1; | |
6594 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
6595 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6596 | break; | |
6597 | ||
6598 | case 0x660fd6: /* movq */ | |
6599 | if (i386_record_modrm (&ir)) | |
6600 | return -1; | |
6601 | if (ir.mod == 3) | |
6602 | { | |
6603 | ir.rm |= ir.rex_b; | |
c131fcee | 6604 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6605 | goto no_support; |
6606 | record_arch_list_add_reg (ir.regcache, | |
6607 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6608 | } | |
6609 | else | |
6610 | { | |
6611 | ir.ot = OT_QUAD; | |
6612 | if (i386_record_lea_modrm (&ir)) | |
6613 | return -1; | |
6614 | } | |
6615 | break; | |
6616 | ||
6617 | case 0x660f3817: /* ptest */ | |
6618 | case 0x0f2e: /* ucomiss */ | |
6619 | case 0x660f2e: /* ucomisd */ | |
6620 | case 0x0f2f: /* comiss */ | |
6621 | case 0x660f2f: /* comisd */ | |
6622 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6623 | break; | |
6624 | ||
6625 | case 0x0ff7: /* maskmovq */ | |
6626 | regcache_raw_read_unsigned (ir.regcache, | |
6627 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6628 | &addr); | |
6629 | if (record_arch_list_add_mem (addr, 64)) | |
6630 | return -1; | |
6631 | break; | |
6632 | ||
6633 | case 0x660ff7: /* maskmovdqu */ | |
6634 | regcache_raw_read_unsigned (ir.regcache, | |
6635 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6636 | &addr); | |
6637 | if (record_arch_list_add_mem (addr, 128)) | |
6638 | return -1; | |
6639 | break; | |
6640 | ||
6641 | default: | |
6642 | goto no_support; | |
6643 | break; | |
6644 | } | |
6645 | break; | |
7ad10968 HZ |
6646 | |
6647 | default: | |
7ad10968 HZ |
6648 | goto no_support; |
6649 | break; | |
6650 | } | |
6651 | ||
cf648174 HZ |
6652 | /* In the future, maybe still need to deal with need_dasm. */ |
6653 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
6654 | if (record_arch_list_add_end ()) |
6655 | return -1; | |
6656 | ||
6657 | return 0; | |
6658 | ||
01fe1b41 | 6659 | no_support: |
a3c4230a HZ |
6660 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
6661 | "at address %s.\n"), | |
6662 | (unsigned int) (opcode), | |
6663 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
6664 | return -1; |
6665 | } | |
6666 | ||
cf648174 HZ |
6667 | static const int i386_record_regmap[] = |
6668 | { | |
6669 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
6670 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
6671 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6672 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
6673 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
6674 | }; | |
6675 | ||
7a697b8d SS |
6676 | /* Check that the given address appears suitable for a fast |
6677 | tracepoint, which on x86 means that we need an instruction of at | |
6678 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
6679 | jump and not have to worry about program jumps to an address in the | |
6680 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
6681 | of instruction to replace, and 0 if not, plus an explanatory | |
6682 | string. */ | |
6683 | ||
6684 | static int | |
6685 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
6686 | CORE_ADDR addr, int *isize, char **msg) | |
6687 | { | |
6688 | int len, jumplen; | |
6689 | static struct ui_file *gdb_null = NULL; | |
6690 | ||
6691 | /* This is based on the target agent using a 4-byte relative jump. | |
6692 | Alternate future possibilities include 8-byte offset for x86-84, | |
6693 | or 3-byte jumps if the program has trampoline space close by. */ | |
6694 | jumplen = 5; | |
6695 | ||
6696 | /* Dummy file descriptor for the disassembler. */ | |
6697 | if (!gdb_null) | |
6698 | gdb_null = ui_file_new (); | |
6699 | ||
6700 | /* Check for fit. */ | |
6701 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
6702 | if (len < jumplen) | |
6703 | { | |
6704 | /* Return a bit of target-specific detail to add to the caller's | |
6705 | generic failure message. */ | |
6706 | if (msg) | |
6707 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), | |
6708 | len, jumplen); | |
6709 | return 0; | |
6710 | } | |
6711 | ||
6712 | if (isize) | |
6713 | *isize = len; | |
6714 | if (msg) | |
6715 | *msg = NULL; | |
6716 | return 1; | |
6717 | } | |
6718 | ||
90884b2b L |
6719 | static int |
6720 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
6721 | struct tdesc_arch_data *tdesc_data) | |
6722 | { | |
6723 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
6724 | const struct tdesc_feature *feature_core; |
6725 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
6726 | int i, num_regs, valid_p; |
6727 | ||
6728 | if (! tdesc_has_registers (tdesc)) | |
6729 | return 0; | |
6730 | ||
6731 | /* Get core registers. */ | |
6732 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
6733 | if (feature_core == NULL) |
6734 | return 0; | |
90884b2b L |
6735 | |
6736 | /* Get SSE registers. */ | |
c131fcee | 6737 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 6738 | |
c131fcee L |
6739 | /* Try AVX registers. */ |
6740 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
6741 | ||
90884b2b L |
6742 | valid_p = 1; |
6743 | ||
c131fcee L |
6744 | /* The XCR0 bits. */ |
6745 | if (feature_avx) | |
6746 | { | |
3a13a53b L |
6747 | /* AVX register description requires SSE register description. */ |
6748 | if (!feature_sse) | |
6749 | return 0; | |
6750 | ||
c131fcee L |
6751 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
6752 | ||
6753 | /* It may have been set by OSABI initialization function. */ | |
6754 | if (tdep->num_ymm_regs == 0) | |
6755 | { | |
6756 | tdep->ymmh_register_names = i386_ymmh_names; | |
6757 | tdep->num_ymm_regs = 8; | |
6758 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
6759 | } | |
6760 | ||
6761 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
6762 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
6763 | tdep->ymm0h_regnum + i, | |
6764 | tdep->ymmh_register_names[i]); | |
6765 | } | |
3a13a53b | 6766 | else if (feature_sse) |
c131fcee | 6767 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
6768 | else |
6769 | { | |
6770 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
6771 | tdep->num_xmm_regs = 0; | |
6772 | } | |
c131fcee | 6773 | |
90884b2b L |
6774 | num_regs = tdep->num_core_regs; |
6775 | for (i = 0; i < num_regs; i++) | |
6776 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
6777 | tdep->register_names[i]); | |
6778 | ||
3a13a53b L |
6779 | if (feature_sse) |
6780 | { | |
6781 | /* Need to include %mxcsr, so add one. */ | |
6782 | num_regs += tdep->num_xmm_regs + 1; | |
6783 | for (; i < num_regs; i++) | |
6784 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
6785 | tdep->register_names[i]); | |
6786 | } | |
90884b2b L |
6787 | |
6788 | return valid_p; | |
6789 | } | |
6790 | ||
7ad10968 HZ |
6791 | \f |
6792 | static struct gdbarch * | |
6793 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
6794 | { | |
6795 | struct gdbarch_tdep *tdep; | |
6796 | struct gdbarch *gdbarch; | |
90884b2b L |
6797 | struct tdesc_arch_data *tdesc_data; |
6798 | const struct target_desc *tdesc; | |
1ba53b71 | 6799 | int mm0_regnum; |
c131fcee | 6800 | int ymm0_regnum; |
7ad10968 HZ |
6801 | |
6802 | /* If there is already a candidate, use it. */ | |
6803 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
6804 | if (arches != NULL) | |
6805 | return arches->gdbarch; | |
6806 | ||
6807 | /* Allocate space for the new architecture. */ | |
6808 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
6809 | gdbarch = gdbarch_alloc (&info, tdep); | |
6810 | ||
6811 | /* General-purpose registers. */ | |
6812 | tdep->gregset = NULL; | |
6813 | tdep->gregset_reg_offset = NULL; | |
6814 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
6815 | tdep->sizeof_gregset = 0; | |
6816 | ||
6817 | /* Floating-point registers. */ | |
6818 | tdep->fpregset = NULL; | |
6819 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
6820 | ||
c131fcee L |
6821 | tdep->xstateregset = NULL; |
6822 | ||
7ad10968 HZ |
6823 | /* The default settings include the FPU registers, the MMX registers |
6824 | and the SSE registers. This can be overridden for a specific ABI | |
6825 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
6826 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 6827 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
6828 | |
6829 | tdep->st0_regnum = I386_ST0_REGNUM; | |
6830 | ||
7ad10968 HZ |
6831 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
6832 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
6833 | ||
6834 | tdep->jb_pc_offset = -1; | |
6835 | tdep->struct_return = pcc_struct_return; | |
6836 | tdep->sigtramp_start = 0; | |
6837 | tdep->sigtramp_end = 0; | |
6838 | tdep->sigtramp_p = i386_sigtramp_p; | |
6839 | tdep->sigcontext_addr = NULL; | |
6840 | tdep->sc_reg_offset = NULL; | |
6841 | tdep->sc_pc_offset = -1; | |
6842 | tdep->sc_sp_offset = -1; | |
6843 | ||
c131fcee L |
6844 | tdep->xsave_xcr0_offset = -1; |
6845 | ||
cf648174 HZ |
6846 | tdep->record_regmap = i386_record_regmap; |
6847 | ||
7ad10968 HZ |
6848 | /* The format used for `long double' on almost all i386 targets is |
6849 | the i387 extended floating-point format. In fact, of all targets | |
6850 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
6851 | on having a `long double' that's not `long' at all. */ | |
6852 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
6853 | ||
6854 | /* Although the i387 extended floating-point has only 80 significant | |
6855 | bits, a `long double' actually takes up 96, probably to enforce | |
6856 | alignment. */ | |
6857 | set_gdbarch_long_double_bit (gdbarch, 96); | |
6858 | ||
7ad10968 HZ |
6859 | /* Register numbers of various important registers. */ |
6860 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
6861 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
6862 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
6863 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
6864 | ||
6865 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
6866 | numbering schemes on the i386: dbx and SVR4. These schemes | |
6867 | differ in how they number %ebp, %esp, %eflags, and the | |
6868 | floating-point registers, and are implemented by the arrays | |
6869 | dbx_register_map[] and svr4_dbx_register_map in | |
6870 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
6871 | gcc/config/i386.c, which it designates as the "default" register | |
6872 | map used in 64bit mode. This last register numbering scheme is | |
6873 | implemented in dbx64_register_map, and is used for AMD64; see | |
6874 | amd64-tdep.c. | |
6875 | ||
6876 | Currently, each GCC i386 target always uses the same register | |
6877 | numbering scheme across all its supported debugging formats | |
6878 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
6879 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
6880 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
6881 | respective config header in a manner independent of the requested | |
6882 | output debugging format. | |
6883 | ||
6884 | This does not match the arrangement below, which presumes that | |
6885 | the SDB and stabs numbering schemes differ from the DWARF and | |
6886 | DWARF 2 ones. The reason for this arrangement is that it is | |
6887 | likely to get the numbering scheme for the target's | |
6888 | default/native debug format right. For targets where GCC is the | |
6889 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
6890 | targets where the native toolchain uses a different numbering | |
6891 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
6892 | the defaults below will have to be overridden, like | |
6893 | i386_elf_init_abi() does. */ | |
6894 | ||
6895 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
6896 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
6897 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
6898 | ||
6899 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
6900 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
6901 | ||
6902 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
6903 | be in use on any of the supported i386 targets. */ | |
6904 | ||
6905 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
6906 | ||
6907 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
6908 | ||
6909 | /* Call dummy code. */ | |
6910 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
6911 | ||
6912 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
6913 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
6914 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
6915 | ||
6916 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
6917 | ||
6918 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
6919 | ||
6920 | /* Stack grows downward. */ | |
6921 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
6922 | ||
6923 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
6924 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
6925 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
6926 | ||
6927 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
6928 | ||
7ad10968 HZ |
6929 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
6930 | ||
6931 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
6932 | ||
6933 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
6934 | ||
6935 | /* Add the i386 register groups. */ | |
6936 | i386_add_reggroups (gdbarch); | |
90884b2b | 6937 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 6938 | |
143985b7 AF |
6939 | /* Helper for function argument information. */ |
6940 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
6941 | ||
06da04c6 MS |
6942 | /* Hook the function epilogue frame unwinder. This unwinder is |
6943 | appended to the list first, so that it supercedes the Dwarf | |
6944 | unwinder in function epilogues (where the Dwarf unwinder | |
6945 | currently fails). */ | |
6946 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
6947 | ||
6948 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
6949 | to the list before the prologue-based unwinders, so that Dwarf | |
6950 | CFI info will be used if it is available. */ | |
10458914 | 6951 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 6952 | |
acd5c798 | 6953 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 6954 | |
1ba53b71 | 6955 | /* Pseudo registers may be changed by amd64_init_abi. */ |
90884b2b L |
6956 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
6957 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
6958 | ||
6959 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
6960 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
6961 | ||
c131fcee L |
6962 | /* Override the normal target description method to make the AVX |
6963 | upper halves anonymous. */ | |
6964 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
6965 | ||
6966 | /* Even though the default ABI only includes general-purpose registers, | |
6967 | floating-point registers and the SSE registers, we have to leave a | |
6968 | gap for the upper AVX registers. */ | |
6969 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
6970 | |
6971 | /* Get the x86 target description from INFO. */ | |
6972 | tdesc = info.target_desc; | |
6973 | if (! tdesc_has_registers (tdesc)) | |
6974 | tdesc = tdesc_i386; | |
6975 | tdep->tdesc = tdesc; | |
6976 | ||
6977 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
6978 | tdep->register_names = i386_register_names; | |
6979 | ||
c131fcee L |
6980 | /* No upper YMM registers. */ |
6981 | tdep->ymmh_register_names = NULL; | |
6982 | tdep->ymm0h_regnum = -1; | |
6983 | ||
1ba53b71 L |
6984 | tdep->num_byte_regs = 8; |
6985 | tdep->num_word_regs = 8; | |
6986 | tdep->num_dword_regs = 0; | |
6987 | tdep->num_mmx_regs = 8; | |
c131fcee | 6988 | tdep->num_ymm_regs = 0; |
1ba53b71 | 6989 | |
90884b2b L |
6990 | tdesc_data = tdesc_data_alloc (); |
6991 | ||
dde08ee1 PA |
6992 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
6993 | ||
3ce1502b | 6994 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 6995 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 6996 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 6997 | |
c131fcee L |
6998 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
6999 | { | |
7000 | tdesc_data_cleanup (tdesc_data); | |
7001 | xfree (tdep); | |
7002 | gdbarch_free (gdbarch); | |
7003 | return NULL; | |
7004 | } | |
7005 | ||
1ba53b71 L |
7006 | /* Wire in pseudo registers. Number of pseudo registers may be |
7007 | changed. */ | |
7008 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7009 | + tdep->num_word_regs | |
7010 | + tdep->num_dword_regs | |
c131fcee L |
7011 | + tdep->num_mmx_regs |
7012 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7013 | |
90884b2b L |
7014 | /* Target description may be changed. */ |
7015 | tdesc = tdep->tdesc; | |
7016 | ||
90884b2b L |
7017 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7018 | ||
7019 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7020 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7021 | ||
1ba53b71 L |
7022 | /* Make %al the first pseudo-register. */ |
7023 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7024 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7025 | ||
c131fcee | 7026 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7027 | if (tdep->num_dword_regs) |
7028 | { | |
7029 | /* Support dword pseudo-registesr if it hasn't been disabled, */ | |
c131fcee L |
7030 | tdep->eax_regnum = ymm0_regnum; |
7031 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7032 | } |
7033 | else | |
7034 | tdep->eax_regnum = -1; | |
7035 | ||
c131fcee L |
7036 | mm0_regnum = ymm0_regnum; |
7037 | if (tdep->num_ymm_regs) | |
7038 | { | |
7039 | /* Support YMM pseudo-registesr if it is available, */ | |
7040 | tdep->ymm0_regnum = ymm0_regnum; | |
7041 | mm0_regnum += tdep->num_ymm_regs; | |
7042 | } | |
7043 | else | |
7044 | tdep->ymm0_regnum = -1; | |
7045 | ||
1ba53b71 L |
7046 | if (tdep->num_mmx_regs != 0) |
7047 | { | |
7048 | /* Support MMX pseudo-registesr if MMX hasn't been disabled, */ | |
7049 | tdep->mm0_regnum = mm0_regnum; | |
7050 | } | |
7051 | else | |
7052 | tdep->mm0_regnum = -1; | |
7053 | ||
06da04c6 | 7054 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
7055 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7056 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7057 | |
8446b36a MK |
7058 | /* If we have a register mapping, enable the generic core file |
7059 | support, unless it has already been enabled. */ | |
7060 | if (tdep->gregset_reg_offset | |
7061 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7062 | set_gdbarch_regset_from_core_section (gdbarch, | |
7063 | i386_regset_from_core_section); | |
7064 | ||
514f746b AR |
7065 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7066 | i386_skip_permanent_breakpoint); | |
7067 | ||
7a697b8d SS |
7068 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7069 | i386_fast_tracepoint_valid_at); | |
7070 | ||
a62cc96e AC |
7071 | return gdbarch; |
7072 | } | |
7073 | ||
8201327c MK |
7074 | static enum gdb_osabi |
7075 | i386_coff_osabi_sniffer (bfd *abfd) | |
7076 | { | |
762c5349 MK |
7077 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7078 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7079 | return GDB_OSABI_GO32; |
7080 | ||
7081 | return GDB_OSABI_UNKNOWN; | |
7082 | } | |
8201327c MK |
7083 | \f |
7084 | ||
28e9e0f0 MK |
7085 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7086 | void _initialize_i386_tdep (void); | |
7087 | ||
c906108c | 7088 | void |
fba45db2 | 7089 | _initialize_i386_tdep (void) |
c906108c | 7090 | { |
a62cc96e AC |
7091 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7092 | ||
fc338970 | 7093 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7094 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7095 | &disassembly_flavor, _("\ | |
7096 | Set the disassembly flavor."), _("\ | |
7097 | Show the disassembly flavor."), _("\ | |
7098 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7099 | NULL, | |
7100 | NULL, /* FIXME: i18n: */ | |
7101 | &setlist, &showlist); | |
8201327c MK |
7102 | |
7103 | /* Add the variable that controls the convention for returning | |
7104 | structs. */ | |
7ab04401 AC |
7105 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7106 | &struct_convention, _("\ | |
7107 | Set the convention for returning small structs."), _("\ | |
7108 | Show the convention for returning small structs."), _("\ | |
7109 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7110 | is \"default\"."), | |
7111 | NULL, | |
7112 | NULL, /* FIXME: i18n: */ | |
7113 | &setlist, &showlist); | |
8201327c MK |
7114 | |
7115 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7116 | i386_coff_osabi_sniffer); | |
8201327c | 7117 | |
05816f70 | 7118 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7119 | i386_svr4_init_abi); |
05816f70 | 7120 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7121 | i386_go32_init_abi); |
38c968cf | 7122 | |
209bd28e | 7123 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7124 | i386_init_reggroups (); |
90884b2b L |
7125 | |
7126 | /* Initialize the standard target descriptions. */ | |
7127 | initialize_tdesc_i386 (); | |
3a13a53b | 7128 | initialize_tdesc_i386_mmx (); |
c131fcee | 7129 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7130 | |
7131 | /* Tell remote stub that we support XML target description. */ | |
7132 | register_remote_support_xml ("i386"); | |
c906108c | 7133 | } |