Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
5ae96ec1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
acd5c798 | 46 | |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
d2a7c97a | 52 | |
7ad10968 HZ |
53 | #include "record.h" |
54 | #include <stdint.h> | |
55 | ||
c4fc7f1b | 56 | /* Register names. */ |
c40e1eab | 57 | |
fc633446 MK |
58 | static char *i386_register_names[] = |
59 | { | |
60 | "eax", "ecx", "edx", "ebx", | |
61 | "esp", "ebp", "esi", "edi", | |
62 | "eip", "eflags", "cs", "ss", | |
63 | "ds", "es", "fs", "gs", | |
64 | "st0", "st1", "st2", "st3", | |
65 | "st4", "st5", "st6", "st7", | |
66 | "fctrl", "fstat", "ftag", "fiseg", | |
67 | "fioff", "foseg", "fooff", "fop", | |
68 | "xmm0", "xmm1", "xmm2", "xmm3", | |
69 | "xmm4", "xmm5", "xmm6", "xmm7", | |
70 | "mxcsr" | |
71 | }; | |
72 | ||
1cb97e17 | 73 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 74 | |
c4fc7f1b | 75 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
76 | |
77 | static char *i386_mmx_names[] = | |
78 | { | |
79 | "mm0", "mm1", "mm2", "mm3", | |
80 | "mm4", "mm5", "mm6", "mm7" | |
81 | }; | |
c40e1eab | 82 | |
1cb97e17 | 83 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 84 | |
28fc6740 | 85 | static int |
5716833c | 86 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 87 | { |
5716833c MK |
88 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
89 | ||
90 | if (mm0_regnum < 0) | |
91 | return 0; | |
92 | ||
93 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
94 | } |
95 | ||
5716833c | 96 | /* SSE register? */ |
23a34459 | 97 | |
5716833c MK |
98 | static int |
99 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 100 | { |
5716833c MK |
101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
102 | ||
20a6ec49 | 103 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
104 | return 0; |
105 | ||
20a6ec49 MD |
106 | return (I387_XMM0_REGNUM (tdep) <= regnum |
107 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
108 | } |
109 | ||
5716833c MK |
110 | static int |
111 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 112 | { |
5716833c MK |
113 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
114 | ||
20a6ec49 | 115 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
116 | return 0; |
117 | ||
20a6ec49 | 118 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
119 | } |
120 | ||
5716833c | 121 | /* FP register? */ |
23a34459 AC |
122 | |
123 | int | |
20a6ec49 | 124 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 125 | { |
20a6ec49 MD |
126 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
127 | ||
128 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
129 | return 0; |
130 | ||
20a6ec49 MD |
131 | return (I387_ST0_REGNUM (tdep) <= regnum |
132 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
133 | } |
134 | ||
135 | int | |
20a6ec49 | 136 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 137 | { |
20a6ec49 MD |
138 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
139 | ||
140 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
141 | return 0; |
142 | ||
20a6ec49 MD |
143 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
144 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
145 | } |
146 | ||
30b0e2d8 | 147 | /* Return the name of register REGNUM. */ |
fc633446 | 148 | |
fa88f677 | 149 | const char * |
d93859e2 | 150 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 151 | { |
d93859e2 | 152 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
20a6ec49 | 153 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; |
fc633446 | 154 | |
30b0e2d8 MK |
155 | if (regnum >= 0 && regnum < i386_num_register_names) |
156 | return i386_register_names[regnum]; | |
70913449 | 157 | |
c40e1eab | 158 | return NULL; |
fc633446 MK |
159 | } |
160 | ||
c4fc7f1b | 161 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
162 | number used by GDB. */ |
163 | ||
8201327c | 164 | static int |
d3f73121 | 165 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 166 | { |
20a6ec49 MD |
167 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
168 | ||
c4fc7f1b MK |
169 | /* This implements what GCC calls the "default" register map |
170 | (dbx_register_map[]). */ | |
171 | ||
85540d8c MK |
172 | if (reg >= 0 && reg <= 7) |
173 | { | |
9872ad24 JB |
174 | /* General-purpose registers. The debug info calls %ebp |
175 | register 4, and %esp register 5. */ | |
176 | if (reg == 4) | |
177 | return 5; | |
178 | else if (reg == 5) | |
179 | return 4; | |
180 | else return reg; | |
85540d8c MK |
181 | } |
182 | else if (reg >= 12 && reg <= 19) | |
183 | { | |
184 | /* Floating-point registers. */ | |
20a6ec49 | 185 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
186 | } |
187 | else if (reg >= 21 && reg <= 28) | |
188 | { | |
189 | /* SSE registers. */ | |
20a6ec49 | 190 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
191 | } |
192 | else if (reg >= 29 && reg <= 36) | |
193 | { | |
194 | /* MMX registers. */ | |
20a6ec49 | 195 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
196 | } |
197 | ||
198 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 199 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
200 | } |
201 | ||
c4fc7f1b MK |
202 | /* Convert SVR4 register number REG to the appropriate register number |
203 | used by GDB. */ | |
85540d8c | 204 | |
8201327c | 205 | static int |
d3f73121 | 206 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 207 | { |
20a6ec49 MD |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
209 | ||
c4fc7f1b MK |
210 | /* This implements the GCC register map that tries to be compatible |
211 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
212 | ||
213 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
214 | numbers the floating point registers differently. */ |
215 | if (reg >= 0 && reg <= 9) | |
216 | { | |
acd5c798 | 217 | /* General-purpose registers. */ |
85540d8c MK |
218 | return reg; |
219 | } | |
220 | else if (reg >= 11 && reg <= 18) | |
221 | { | |
222 | /* Floating-point registers. */ | |
20a6ec49 | 223 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 224 | } |
c6f4c129 | 225 | else if (reg >= 21 && reg <= 36) |
85540d8c | 226 | { |
c4fc7f1b | 227 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 228 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
229 | } |
230 | ||
c6f4c129 JB |
231 | switch (reg) |
232 | { | |
20a6ec49 MD |
233 | case 37: return I387_FCTRL_REGNUM (tdep); |
234 | case 38: return I387_FSTAT_REGNUM (tdep); | |
235 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
236 | case 40: return I386_ES_REGNUM; |
237 | case 41: return I386_CS_REGNUM; | |
238 | case 42: return I386_SS_REGNUM; | |
239 | case 43: return I386_DS_REGNUM; | |
240 | case 44: return I386_FS_REGNUM; | |
241 | case 45: return I386_GS_REGNUM; | |
242 | } | |
243 | ||
85540d8c | 244 | /* This will hopefully provoke a warning. */ |
d3f73121 | 245 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 246 | } |
5716833c | 247 | |
fc338970 | 248 | \f |
917317f4 | 249 | |
fc338970 MK |
250 | /* This is the variable that is set with "set disassembly-flavor", and |
251 | its legitimate values. */ | |
53904c9e AC |
252 | static const char att_flavor[] = "att"; |
253 | static const char intel_flavor[] = "intel"; | |
254 | static const char *valid_flavors[] = | |
c5aa993b | 255 | { |
c906108c SS |
256 | att_flavor, |
257 | intel_flavor, | |
258 | NULL | |
259 | }; | |
53904c9e | 260 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 261 | \f |
c906108c | 262 | |
acd5c798 MK |
263 | /* Use the program counter to determine the contents and size of a |
264 | breakpoint instruction. Return a pointer to a string of bytes that | |
265 | encode a breakpoint instruction, store the length of the string in | |
266 | *LEN and optionally adjust *PC to point to the correct memory | |
267 | location for inserting the breakpoint. | |
c906108c | 268 | |
acd5c798 MK |
269 | On the i386 we have a single breakpoint that fits in a single byte |
270 | and can be inserted anywhere. | |
c906108c | 271 | |
acd5c798 | 272 | This function is 64-bit safe. */ |
63c0089f MK |
273 | |
274 | static const gdb_byte * | |
67d57894 | 275 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 276 | { |
63c0089f MK |
277 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
278 | ||
acd5c798 MK |
279 | *len = sizeof (break_insn); |
280 | return break_insn; | |
c906108c | 281 | } |
237fc4c9 PA |
282 | \f |
283 | /* Displaced instruction handling. */ | |
284 | ||
1903f0e6 DE |
285 | /* Skip the legacy instruction prefixes in INSN. |
286 | Not all prefixes are valid for any particular insn | |
287 | but we needn't care, the insn will fault if it's invalid. | |
288 | The result is a pointer to the first opcode byte, | |
289 | or NULL if we run off the end of the buffer. */ | |
290 | ||
291 | static gdb_byte * | |
292 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
293 | { | |
294 | gdb_byte *end = insn + max_len; | |
295 | ||
296 | while (insn < end) | |
297 | { | |
298 | switch (*insn) | |
299 | { | |
300 | case DATA_PREFIX_OPCODE: | |
301 | case ADDR_PREFIX_OPCODE: | |
302 | case CS_PREFIX_OPCODE: | |
303 | case DS_PREFIX_OPCODE: | |
304 | case ES_PREFIX_OPCODE: | |
305 | case FS_PREFIX_OPCODE: | |
306 | case GS_PREFIX_OPCODE: | |
307 | case SS_PREFIX_OPCODE: | |
308 | case LOCK_PREFIX_OPCODE: | |
309 | case REPE_PREFIX_OPCODE: | |
310 | case REPNE_PREFIX_OPCODE: | |
311 | ++insn; | |
312 | continue; | |
313 | default: | |
314 | return insn; | |
315 | } | |
316 | } | |
317 | ||
318 | return NULL; | |
319 | } | |
237fc4c9 PA |
320 | |
321 | static int | |
1903f0e6 | 322 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
323 | { |
324 | /* jmp far (absolute address in operand) */ | |
325 | if (insn[0] == 0xea) | |
326 | return 1; | |
327 | ||
328 | if (insn[0] == 0xff) | |
329 | { | |
330 | /* jump near, absolute indirect (/4) */ | |
331 | if ((insn[1] & 0x38) == 0x20) | |
332 | return 1; | |
333 | ||
334 | /* jump far, absolute indirect (/5) */ | |
335 | if ((insn[1] & 0x38) == 0x28) | |
336 | return 1; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int | |
1903f0e6 | 343 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
344 | { |
345 | /* call far, absolute */ | |
346 | if (insn[0] == 0x9a) | |
347 | return 1; | |
348 | ||
349 | if (insn[0] == 0xff) | |
350 | { | |
351 | /* Call near, absolute indirect (/2) */ | |
352 | if ((insn[1] & 0x38) == 0x10) | |
353 | return 1; | |
354 | ||
355 | /* Call far, absolute indirect (/3) */ | |
356 | if ((insn[1] & 0x38) == 0x18) | |
357 | return 1; | |
358 | } | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int | |
1903f0e6 | 364 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
365 | { |
366 | switch (insn[0]) | |
367 | { | |
368 | case 0xc2: /* ret near, pop N bytes */ | |
369 | case 0xc3: /* ret near */ | |
370 | case 0xca: /* ret far, pop N bytes */ | |
371 | case 0xcb: /* ret far */ | |
372 | case 0xcf: /* iret */ | |
373 | return 1; | |
374 | ||
375 | default: | |
376 | return 0; | |
377 | } | |
378 | } | |
379 | ||
380 | static int | |
1903f0e6 | 381 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
382 | { |
383 | if (i386_absolute_call_p (insn)) | |
384 | return 1; | |
385 | ||
386 | /* call near, relative */ | |
387 | if (insn[0] == 0xe8) | |
388 | return 1; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
237fc4c9 PA |
393 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
394 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 395 | |
237fc4c9 | 396 | static int |
1903f0e6 | 397 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
398 | { |
399 | if (insn[0] == 0xcd) | |
400 | { | |
401 | *lengthp = 2; | |
402 | return 1; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | /* Fix up the state of registers and memory after having single-stepped | |
409 | a displaced instruction. */ | |
1903f0e6 | 410 | |
237fc4c9 PA |
411 | void |
412 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
413 | struct displaced_step_closure *closure, | |
414 | CORE_ADDR from, CORE_ADDR to, | |
415 | struct regcache *regs) | |
416 | { | |
417 | /* The offset we applied to the instruction's address. | |
418 | This could well be negative (when viewed as a signed 32-bit | |
419 | value), but ULONGEST won't reflect that, so take care when | |
420 | applying it. */ | |
421 | ULONGEST insn_offset = to - from; | |
422 | ||
423 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
424 | copy of the instruction. */ | |
425 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
426 | /* The start of the insn, needed in case we see some prefixes. */ |
427 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
428 | |
429 | if (debug_displaced) | |
430 | fprintf_unfiltered (gdb_stdlog, | |
431 | "displaced: fixup (0x%s, 0x%s), " | |
432 | "insn = 0x%02x 0x%02x ...\n", | |
433 | paddr_nz (from), paddr_nz (to), insn[0], insn[1]); | |
434 | ||
435 | /* The list of issues to contend with here is taken from | |
436 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
437 | Yay for Free Software! */ | |
438 | ||
439 | /* Relocate the %eip, if necessary. */ | |
440 | ||
1903f0e6 DE |
441 | /* The instruction recognizers we use assume any leading prefixes |
442 | have been skipped. */ | |
443 | { | |
444 | /* This is the size of the buffer in closure. */ | |
445 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
446 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
447 | /* If there are too many prefixes, just ignore the insn. | |
448 | It will fault when run. */ | |
449 | if (opcode != NULL) | |
450 | insn = opcode; | |
451 | } | |
452 | ||
237fc4c9 PA |
453 | /* Except in the case of absolute or indirect jump or call |
454 | instructions, or a return instruction, the new eip is relative to | |
455 | the displaced instruction; make it relative. Well, signal | |
456 | handler returns don't need relocation either, but we use the | |
457 | value of %eip to recognize those; see below. */ | |
458 | if (! i386_absolute_jmp_p (insn) | |
459 | && ! i386_absolute_call_p (insn) | |
460 | && ! i386_ret_p (insn)) | |
461 | { | |
462 | ULONGEST orig_eip; | |
463 | ULONGEST insn_len; | |
464 | ||
465 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
466 | ||
467 | /* A signal trampoline system call changes the %eip, resuming | |
468 | execution of the main program after the signal handler has | |
469 | returned. That makes them like 'return' instructions; we | |
470 | shouldn't relocate %eip. | |
471 | ||
472 | But most system calls don't, and we do need to relocate %eip. | |
473 | ||
474 | Our heuristic for distinguishing these cases: if stepping | |
475 | over the system call instruction left control directly after | |
476 | the instruction, the we relocate --- control almost certainly | |
477 | doesn't belong in the displaced copy. Otherwise, we assume | |
478 | the instruction has put control where it belongs, and leave | |
479 | it unrelocated. Goodness help us if there are PC-relative | |
480 | system calls. */ | |
481 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 482 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
483 | { |
484 | if (debug_displaced) | |
485 | fprintf_unfiltered (gdb_stdlog, | |
486 | "displaced: syscall changed %%eip; " | |
487 | "not relocating\n"); | |
488 | } | |
489 | else | |
490 | { | |
491 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
492 | ||
1903f0e6 DE |
493 | /* If we just stepped over a breakpoint insn, we don't backup |
494 | the pc on purpose; this is to match behaviour without | |
495 | stepping. */ | |
237fc4c9 PA |
496 | |
497 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
498 | ||
499 | if (debug_displaced) | |
500 | fprintf_unfiltered (gdb_stdlog, | |
501 | "displaced: " | |
502 | "relocated %%eip from 0x%s to 0x%s\n", | |
503 | paddr_nz (orig_eip), paddr_nz (eip)); | |
504 | } | |
505 | } | |
506 | ||
507 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
508 | pushed value, and should be cleared. We'll leave this for later, | |
509 | since GDB already messes up the TF flag when stepping over a | |
510 | pushfl. */ | |
511 | ||
512 | /* If the instruction was a call, the return address now atop the | |
513 | stack is the address following the copied instruction. We need | |
514 | to make it the address following the original instruction. */ | |
515 | if (i386_call_p (insn)) | |
516 | { | |
517 | ULONGEST esp; | |
518 | ULONGEST retaddr; | |
519 | const ULONGEST retaddr_len = 4; | |
520 | ||
521 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
522 | retaddr = read_memory_unsigned_integer (esp, retaddr_len); | |
523 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; | |
524 | write_memory_unsigned_integer (esp, retaddr_len, retaddr); | |
525 | ||
526 | if (debug_displaced) | |
527 | fprintf_unfiltered (gdb_stdlog, | |
528 | "displaced: relocated return addr at 0x%s " | |
529 | "to 0x%s\n", | |
530 | paddr_nz (esp), | |
531 | paddr_nz (retaddr)); | |
532 | } | |
533 | } | |
fc338970 | 534 | \f |
acd5c798 MK |
535 | #ifdef I386_REGNO_TO_SYMMETRY |
536 | #error "The Sequent Symmetry is no longer supported." | |
537 | #endif | |
c906108c | 538 | |
acd5c798 MK |
539 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
540 | and %esp "belong" to the calling function. Therefore these | |
541 | registers should be saved if they're going to be modified. */ | |
c906108c | 542 | |
acd5c798 MK |
543 | /* The maximum number of saved registers. This should include all |
544 | registers mentioned above, and %eip. */ | |
a3386186 | 545 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
546 | |
547 | struct i386_frame_cache | |
c906108c | 548 | { |
acd5c798 MK |
549 | /* Base address. */ |
550 | CORE_ADDR base; | |
772562f8 | 551 | LONGEST sp_offset; |
acd5c798 MK |
552 | CORE_ADDR pc; |
553 | ||
fd13a04a AC |
554 | /* Saved registers. */ |
555 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 556 | CORE_ADDR saved_sp; |
e0c62198 | 557 | int saved_sp_reg; |
acd5c798 MK |
558 | int pc_in_eax; |
559 | ||
560 | /* Stack space reserved for local variables. */ | |
561 | long locals; | |
562 | }; | |
563 | ||
564 | /* Allocate and initialize a frame cache. */ | |
565 | ||
566 | static struct i386_frame_cache * | |
fd13a04a | 567 | i386_alloc_frame_cache (void) |
acd5c798 MK |
568 | { |
569 | struct i386_frame_cache *cache; | |
570 | int i; | |
571 | ||
572 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
573 | ||
574 | /* Base address. */ | |
575 | cache->base = 0; | |
576 | cache->sp_offset = -4; | |
577 | cache->pc = 0; | |
578 | ||
fd13a04a AC |
579 | /* Saved registers. We initialize these to -1 since zero is a valid |
580 | offset (that's where %ebp is supposed to be stored). */ | |
581 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
582 | cache->saved_regs[i] = -1; | |
acd5c798 | 583 | cache->saved_sp = 0; |
e0c62198 | 584 | cache->saved_sp_reg = -1; |
acd5c798 MK |
585 | cache->pc_in_eax = 0; |
586 | ||
587 | /* Frameless until proven otherwise. */ | |
588 | cache->locals = -1; | |
589 | ||
590 | return cache; | |
591 | } | |
c906108c | 592 | |
acd5c798 MK |
593 | /* If the instruction at PC is a jump, return the address of its |
594 | target. Otherwise, return PC. */ | |
c906108c | 595 | |
acd5c798 MK |
596 | static CORE_ADDR |
597 | i386_follow_jump (CORE_ADDR pc) | |
598 | { | |
63c0089f | 599 | gdb_byte op; |
acd5c798 MK |
600 | long delta = 0; |
601 | int data16 = 0; | |
c906108c | 602 | |
8defab1a | 603 | target_read_memory (pc, &op, 1); |
acd5c798 | 604 | if (op == 0x66) |
c906108c | 605 | { |
c906108c | 606 | data16 = 1; |
acd5c798 | 607 | op = read_memory_unsigned_integer (pc + 1, 1); |
c906108c SS |
608 | } |
609 | ||
acd5c798 | 610 | switch (op) |
c906108c SS |
611 | { |
612 | case 0xe9: | |
fc338970 | 613 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
614 | if (data16) |
615 | { | |
acd5c798 | 616 | delta = read_memory_integer (pc + 2, 2); |
c906108c | 617 | |
fc338970 MK |
618 | /* Include the size of the jmp instruction (including the |
619 | 0x66 prefix). */ | |
acd5c798 | 620 | delta += 4; |
c906108c SS |
621 | } |
622 | else | |
623 | { | |
acd5c798 | 624 | delta = read_memory_integer (pc + 1, 4); |
c906108c | 625 | |
acd5c798 MK |
626 | /* Include the size of the jmp instruction. */ |
627 | delta += 5; | |
c906108c SS |
628 | } |
629 | break; | |
630 | case 0xeb: | |
fc338970 | 631 | /* Relative jump, disp8 (ignore data16). */ |
acd5c798 | 632 | delta = read_memory_integer (pc + data16 + 1, 1); |
c906108c | 633 | |
acd5c798 | 634 | delta += data16 + 2; |
c906108c SS |
635 | break; |
636 | } | |
c906108c | 637 | |
acd5c798 MK |
638 | return pc + delta; |
639 | } | |
fc338970 | 640 | |
acd5c798 MK |
641 | /* Check whether PC points at a prologue for a function returning a |
642 | structure or union. If so, it updates CACHE and returns the | |
643 | address of the first instruction after the code sequence that | |
644 | removes the "hidden" argument from the stack or CURRENT_PC, | |
645 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 646 | |
acd5c798 MK |
647 | static CORE_ADDR |
648 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
649 | struct i386_frame_cache *cache) | |
c906108c | 650 | { |
acd5c798 MK |
651 | /* Functions that return a structure or union start with: |
652 | ||
653 | popl %eax 0x58 | |
654 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
655 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
656 | ||
657 | (the System V compiler puts out the second `xchg' instruction, | |
658 | and the assembler doesn't try to optimize it, so the 'sib' form | |
659 | gets generated). This sequence is used to get the address of the | |
660 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
661 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
662 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
663 | gdb_byte buf[4]; | |
664 | gdb_byte op; | |
c906108c | 665 | |
acd5c798 MK |
666 | if (current_pc <= pc) |
667 | return pc; | |
668 | ||
8defab1a | 669 | target_read_memory (pc, &op, 1); |
c906108c | 670 | |
acd5c798 MK |
671 | if (op != 0x58) /* popl %eax */ |
672 | return pc; | |
c906108c | 673 | |
8defab1a | 674 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
675 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
676 | return pc; | |
c906108c | 677 | |
acd5c798 | 678 | if (current_pc == pc) |
c906108c | 679 | { |
acd5c798 MK |
680 | cache->sp_offset += 4; |
681 | return current_pc; | |
c906108c SS |
682 | } |
683 | ||
acd5c798 | 684 | if (current_pc == pc + 1) |
c906108c | 685 | { |
acd5c798 MK |
686 | cache->pc_in_eax = 1; |
687 | return current_pc; | |
688 | } | |
689 | ||
690 | if (buf[1] == proto1[1]) | |
691 | return pc + 4; | |
692 | else | |
693 | return pc + 5; | |
694 | } | |
695 | ||
696 | static CORE_ADDR | |
697 | i386_skip_probe (CORE_ADDR pc) | |
698 | { | |
699 | /* A function may start with | |
fc338970 | 700 | |
acd5c798 MK |
701 | pushl constant |
702 | call _probe | |
703 | addl $4, %esp | |
fc338970 | 704 | |
acd5c798 MK |
705 | followed by |
706 | ||
707 | pushl %ebp | |
fc338970 | 708 | |
acd5c798 | 709 | etc. */ |
63c0089f MK |
710 | gdb_byte buf[8]; |
711 | gdb_byte op; | |
fc338970 | 712 | |
8defab1a | 713 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
714 | |
715 | if (op == 0x68 || op == 0x6a) | |
716 | { | |
717 | int delta; | |
c906108c | 718 | |
acd5c798 MK |
719 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
720 | four-byte operand, depending on the opcode. */ | |
c906108c | 721 | if (op == 0x68) |
acd5c798 | 722 | delta = 5; |
c906108c | 723 | else |
acd5c798 | 724 | delta = 2; |
c906108c | 725 | |
acd5c798 MK |
726 | /* Read the following 8 bytes, which should be `call _probe' (6 |
727 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
728 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 729 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 730 | pc += delta + sizeof (buf); |
c906108c SS |
731 | } |
732 | ||
acd5c798 MK |
733 | return pc; |
734 | } | |
735 | ||
92dd43fa MK |
736 | /* GCC 4.1 and later, can put code in the prologue to realign the |
737 | stack pointer. Check whether PC points to such code, and update | |
738 | CACHE accordingly. Return the first instruction after the code | |
739 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
740 | recognize the code, return PC. */ | |
741 | ||
742 | static CORE_ADDR | |
743 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
744 | struct i386_frame_cache *cache) | |
745 | { | |
e0c62198 L |
746 | /* There are 2 code sequences to re-align stack before the frame |
747 | gets set up: | |
748 | ||
749 | 1. Use a caller-saved saved register: | |
750 | ||
751 | leal 4(%esp), %reg | |
752 | andl $-XXX, %esp | |
753 | pushl -4(%reg) | |
754 | ||
755 | 2. Use a callee-saved saved register: | |
756 | ||
757 | pushl %reg | |
758 | leal 8(%esp), %reg | |
759 | andl $-XXX, %esp | |
760 | pushl -4(%reg) | |
761 | ||
762 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
763 | ||
764 | 0x83 0xe4 0xf0 andl $-16, %esp | |
765 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
766 | */ | |
767 | ||
768 | gdb_byte buf[14]; | |
769 | int reg; | |
770 | int offset, offset_and; | |
771 | static int regnums[8] = { | |
772 | I386_EAX_REGNUM, /* %eax */ | |
773 | I386_ECX_REGNUM, /* %ecx */ | |
774 | I386_EDX_REGNUM, /* %edx */ | |
775 | I386_EBX_REGNUM, /* %ebx */ | |
776 | I386_ESP_REGNUM, /* %esp */ | |
777 | I386_EBP_REGNUM, /* %ebp */ | |
778 | I386_ESI_REGNUM, /* %esi */ | |
779 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 780 | }; |
92dd43fa | 781 | |
e0c62198 L |
782 | if (target_read_memory (pc, buf, sizeof buf)) |
783 | return pc; | |
784 | ||
785 | /* Check caller-saved saved register. The first instruction has | |
786 | to be "leal 4(%esp), %reg". */ | |
787 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
788 | { | |
789 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
790 | if ((buf[1] & 0xc7) != 0x44) | |
791 | return pc; | |
792 | ||
793 | /* REG has register number. */ | |
794 | reg = (buf[1] >> 3) & 7; | |
795 | offset = 4; | |
796 | } | |
797 | else | |
798 | { | |
799 | /* Check callee-saved saved register. The first instruction | |
800 | has to be "pushl %reg". */ | |
801 | if ((buf[0] & 0xf8) != 0x50) | |
802 | return pc; | |
803 | ||
804 | /* Get register. */ | |
805 | reg = buf[0] & 0x7; | |
806 | ||
807 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
808 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
809 | return pc; | |
810 | ||
811 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
812 | if ((buf[2] & 0xc7) != 0x44) | |
813 | return pc; | |
814 | ||
815 | /* REG has register number. Registers in pushl and leal have to | |
816 | be the same. */ | |
817 | if (reg != ((buf[2] >> 3) & 7)) | |
818 | return pc; | |
819 | ||
820 | offset = 5; | |
821 | } | |
822 | ||
823 | /* Rigister can't be %esp nor %ebp. */ | |
824 | if (reg == 4 || reg == 5) | |
825 | return pc; | |
826 | ||
827 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
828 | if (buf[offset + 1] != 0xe4 | |
829 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
830 | return pc; | |
831 | ||
832 | offset_and = offset; | |
833 | offset += buf[offset] == 0x81 ? 6 : 3; | |
834 | ||
835 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
836 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
837 | if (buf[offset] != 0xff | |
838 | || buf[offset + 2] != 0xfc | |
839 | || (buf[offset + 1] & 0xf8) != 0x70) | |
840 | return pc; | |
841 | ||
842 | /* R/M has register. Registers in leal and pushl have to be the | |
843 | same. */ | |
844 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
845 | return pc; |
846 | ||
e0c62198 L |
847 | if (current_pc > pc + offset_and) |
848 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 849 | |
e0c62198 | 850 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
851 | } |
852 | ||
37bdc87e | 853 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 854 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
855 | |
856 | /* Instruction description. */ | |
857 | struct i386_insn | |
858 | { | |
859 | size_t len; | |
237fc4c9 PA |
860 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
861 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
862 | }; |
863 | ||
864 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
865 | the first instruction description that matches. Otherwise, return | |
866 | NULL. */ | |
867 | ||
868 | static struct i386_insn * | |
869 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
870 | { | |
871 | struct i386_insn *insn; | |
63c0089f | 872 | gdb_byte op; |
37bdc87e | 873 | |
8defab1a | 874 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
875 | |
876 | for (insn = skip_insns; insn->len > 0; insn++) | |
877 | { | |
878 | if ((op & insn->mask[0]) == insn->insn[0]) | |
879 | { | |
237fc4c9 | 880 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 881 | int insn_matched = 1; |
37bdc87e MK |
882 | size_t i; |
883 | ||
884 | gdb_assert (insn->len > 1); | |
237fc4c9 | 885 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 886 | |
8defab1a | 887 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
888 | for (i = 1; i < insn->len; i++) |
889 | { | |
890 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 891 | insn_matched = 0; |
37bdc87e | 892 | } |
613e8135 MK |
893 | |
894 | if (insn_matched) | |
895 | return insn; | |
37bdc87e MK |
896 | } |
897 | } | |
898 | ||
899 | return NULL; | |
900 | } | |
901 | ||
902 | /* Some special instructions that might be migrated by GCC into the | |
903 | part of the prologue that sets up the new stack frame. Because the | |
904 | stack frame hasn't been setup yet, no registers have been saved | |
905 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
906 | touched. */ | |
907 | ||
908 | struct i386_insn i386_frame_setup_skip_insns[] = | |
909 | { | |
910 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
911 | ||
912 | ??? Should we handle 16-bit operand-sizes here? */ | |
913 | ||
914 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
915 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
916 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
917 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
918 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
919 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
920 | { 5, { 0xb8 }, { 0xfe } }, | |
921 | /* `movl imm32, %edx' */ | |
922 | { 5, { 0xba }, { 0xff } }, | |
923 | ||
924 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
925 | encoding for `mov m32, %eax'. | |
926 | ||
927 | ??? Should we handle SIB adressing here? | |
928 | ??? Should we handle 16-bit operand-sizes here? */ | |
929 | ||
930 | /* `movl m32, %eax' */ | |
931 | { 5, { 0xa1 }, { 0xff } }, | |
932 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
933 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
934 | /* `movl m32, %edx' */ | |
935 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
936 | ||
937 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
938 | Because of the symmetry, there are actually two ways to encode | |
939 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
940 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
941 | ||
942 | /* `subl %eax, %eax' */ | |
943 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
944 | /* `subl %ecx, %ecx' */ | |
945 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
946 | /* `subl %edx, %edx' */ | |
947 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
948 | /* `xorl %eax, %eax' */ | |
949 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
950 | /* `xorl %ecx, %ecx' */ | |
951 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
952 | /* `xorl %edx, %edx' */ | |
953 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
954 | { 0 } | |
955 | }; | |
956 | ||
e11481da PM |
957 | |
958 | /* Check whether PC points to a no-op instruction. */ | |
959 | static CORE_ADDR | |
960 | i386_skip_noop (CORE_ADDR pc) | |
961 | { | |
962 | gdb_byte op; | |
963 | int check = 1; | |
964 | ||
8defab1a | 965 | target_read_memory (pc, &op, 1); |
e11481da PM |
966 | |
967 | while (check) | |
968 | { | |
969 | check = 0; | |
970 | /* Ignore `nop' instruction. */ | |
971 | if (op == 0x90) | |
972 | { | |
973 | pc += 1; | |
8defab1a | 974 | target_read_memory (pc, &op, 1); |
e11481da PM |
975 | check = 1; |
976 | } | |
977 | /* Ignore no-op instruction `mov %edi, %edi'. | |
978 | Microsoft system dlls often start with | |
979 | a `mov %edi,%edi' instruction. | |
980 | The 5 bytes before the function start are | |
981 | filled with `nop' instructions. | |
982 | This pattern can be used for hot-patching: | |
983 | The `mov %edi, %edi' instruction can be replaced by a | |
984 | near jump to the location of the 5 `nop' instructions | |
985 | which can be replaced by a 32-bit jump to anywhere | |
986 | in the 32-bit address space. */ | |
987 | ||
988 | else if (op == 0x8b) | |
989 | { | |
8defab1a | 990 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
991 | if (op == 0xff) |
992 | { | |
993 | pc += 2; | |
8defab1a | 994 | target_read_memory (pc, &op, 1); |
e11481da PM |
995 | check = 1; |
996 | } | |
997 | } | |
998 | } | |
999 | return pc; | |
1000 | } | |
1001 | ||
acd5c798 MK |
1002 | /* Check whether PC points at a code that sets up a new stack frame. |
1003 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1004 | instruction after the sequence that sets up the frame or LIMIT, |
1005 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1006 | |
1007 | static CORE_ADDR | |
37bdc87e | 1008 | i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit, |
acd5c798 MK |
1009 | struct i386_frame_cache *cache) |
1010 | { | |
37bdc87e | 1011 | struct i386_insn *insn; |
63c0089f | 1012 | gdb_byte op; |
26604a34 | 1013 | int skip = 0; |
acd5c798 | 1014 | |
37bdc87e MK |
1015 | if (limit <= pc) |
1016 | return limit; | |
acd5c798 | 1017 | |
8defab1a | 1018 | target_read_memory (pc, &op, 1); |
acd5c798 | 1019 | |
c906108c | 1020 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1021 | { |
acd5c798 MK |
1022 | /* Take into account that we've executed the `pushl %ebp' that |
1023 | starts this instruction sequence. */ | |
fd13a04a | 1024 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1025 | cache->sp_offset += 4; |
37bdc87e | 1026 | pc++; |
acd5c798 MK |
1027 | |
1028 | /* If that's all, return now. */ | |
37bdc87e MK |
1029 | if (limit <= pc) |
1030 | return limit; | |
26604a34 | 1031 | |
b4632131 | 1032 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1033 | GCC into the prologue and skip them. At this point in the |
1034 | prologue, code should only touch the scratch registers %eax, | |
1035 | %ecx and %edx, so while the number of posibilities is sheer, | |
1036 | it is limited. | |
5daa5b4e | 1037 | |
26604a34 MK |
1038 | Make sure we only skip these instructions if we later see the |
1039 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1040 | while (pc + skip < limit) |
26604a34 | 1041 | { |
37bdc87e MK |
1042 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1043 | if (insn == NULL) | |
1044 | break; | |
b4632131 | 1045 | |
37bdc87e | 1046 | skip += insn->len; |
26604a34 MK |
1047 | } |
1048 | ||
37bdc87e MK |
1049 | /* If that's all, return now. */ |
1050 | if (limit <= pc + skip) | |
1051 | return limit; | |
1052 | ||
8defab1a | 1053 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1054 | |
26604a34 | 1055 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1056 | switch (op) |
c906108c SS |
1057 | { |
1058 | case 0x8b: | |
37bdc87e MK |
1059 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec) |
1060 | return pc; | |
c906108c SS |
1061 | break; |
1062 | case 0x89: | |
37bdc87e MK |
1063 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5) |
1064 | return pc; | |
c906108c SS |
1065 | break; |
1066 | default: | |
37bdc87e | 1067 | return pc; |
c906108c | 1068 | } |
acd5c798 | 1069 | |
26604a34 MK |
1070 | /* OK, we actually have a frame. We just don't know how large |
1071 | it is yet. Set its size to zero. We'll adjust it if | |
1072 | necessary. We also now commit to skipping the special | |
1073 | instructions mentioned before. */ | |
acd5c798 | 1074 | cache->locals = 0; |
37bdc87e | 1075 | pc += (skip + 2); |
acd5c798 MK |
1076 | |
1077 | /* If that's all, return now. */ | |
37bdc87e MK |
1078 | if (limit <= pc) |
1079 | return limit; | |
acd5c798 | 1080 | |
fc338970 MK |
1081 | /* Check for stack adjustment |
1082 | ||
acd5c798 | 1083 | subl $XXX, %esp |
fc338970 | 1084 | |
fd35795f | 1085 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1086 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1087 | target_read_memory (pc, &op, 1); |
c906108c SS |
1088 | if (op == 0x83) |
1089 | { | |
fd35795f | 1090 | /* `subl' with 8-bit immediate. */ |
37bdc87e | 1091 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 1092 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1093 | return pc; |
acd5c798 | 1094 | |
37bdc87e MK |
1095 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1096 | make sense to be negative). */ | |
1097 | cache->locals = read_memory_integer (pc + 2, 1); | |
1098 | return pc + 3; | |
c906108c SS |
1099 | } |
1100 | else if (op == 0x81) | |
1101 | { | |
fd35795f | 1102 | /* Maybe it is `subl' with a 32-bit immediate. */ |
37bdc87e | 1103 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 1104 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1105 | return pc; |
acd5c798 | 1106 | |
fd35795f | 1107 | /* It is `subl' with a 32-bit immediate. */ |
37bdc87e MK |
1108 | cache->locals = read_memory_integer (pc + 2, 4); |
1109 | return pc + 6; | |
c906108c SS |
1110 | } |
1111 | else | |
1112 | { | |
acd5c798 | 1113 | /* Some instruction other than `subl'. */ |
37bdc87e | 1114 | return pc; |
c906108c SS |
1115 | } |
1116 | } | |
37bdc87e | 1117 | else if (op == 0xc8) /* enter */ |
c906108c | 1118 | { |
acd5c798 MK |
1119 | cache->locals = read_memory_unsigned_integer (pc + 1, 2); |
1120 | return pc + 4; | |
c906108c | 1121 | } |
21d0e8a4 | 1122 | |
acd5c798 | 1123 | return pc; |
21d0e8a4 MK |
1124 | } |
1125 | ||
acd5c798 MK |
1126 | /* Check whether PC points at code that saves registers on the stack. |
1127 | If so, it updates CACHE and returns the address of the first | |
1128 | instruction after the register saves or CURRENT_PC, whichever is | |
1129 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1130 | |
1131 | static CORE_ADDR | |
acd5c798 MK |
1132 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1133 | struct i386_frame_cache *cache) | |
6bff26de | 1134 | { |
99ab4326 | 1135 | CORE_ADDR offset = 0; |
63c0089f | 1136 | gdb_byte op; |
99ab4326 | 1137 | int i; |
c0d1d883 | 1138 | |
99ab4326 MK |
1139 | if (cache->locals > 0) |
1140 | offset -= cache->locals; | |
1141 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1142 | { | |
8defab1a | 1143 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1144 | if (op < 0x50 || op > 0x57) |
1145 | break; | |
0d17c81d | 1146 | |
99ab4326 MK |
1147 | offset -= 4; |
1148 | cache->saved_regs[op - 0x50] = offset; | |
1149 | cache->sp_offset += 4; | |
1150 | pc++; | |
6bff26de MK |
1151 | } |
1152 | ||
acd5c798 | 1153 | return pc; |
22797942 AC |
1154 | } |
1155 | ||
acd5c798 MK |
1156 | /* Do a full analysis of the prologue at PC and update CACHE |
1157 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1158 | address where the analysis stopped. | |
ed84f6c1 | 1159 | |
fc338970 MK |
1160 | We handle these cases: |
1161 | ||
1162 | The startup sequence can be at the start of the function, or the | |
1163 | function can start with a branch to startup code at the end. | |
1164 | ||
1165 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1166 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1167 | once used in the System V compiler). | |
1168 | ||
1169 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1170 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1171 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1172 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1173 | |
1174 | Next, the registers used by this function are pushed. With the | |
1175 | System V compiler they will always be in the order: %edi, %esi, | |
1176 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1177 | restore %eax); however, the code below is willing to see the pushes | |
1178 | in any order, and will handle up to 8 of them. | |
1179 | ||
1180 | If the setup sequence is at the end of the function, then the next | |
1181 | instruction will be a branch back to the start. */ | |
c906108c | 1182 | |
acd5c798 MK |
1183 | static CORE_ADDR |
1184 | i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
1185 | struct i386_frame_cache *cache) | |
c906108c | 1186 | { |
e11481da | 1187 | pc = i386_skip_noop (pc); |
acd5c798 MK |
1188 | pc = i386_follow_jump (pc); |
1189 | pc = i386_analyze_struct_return (pc, current_pc, cache); | |
1190 | pc = i386_skip_probe (pc); | |
92dd43fa | 1191 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
acd5c798 MK |
1192 | pc = i386_analyze_frame_setup (pc, current_pc, cache); |
1193 | return i386_analyze_register_saves (pc, current_pc, cache); | |
c906108c SS |
1194 | } |
1195 | ||
fc338970 | 1196 | /* Return PC of first real instruction. */ |
c906108c | 1197 | |
3a1e71e3 | 1198 | static CORE_ADDR |
6093d2eb | 1199 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1200 | { |
63c0089f | 1201 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1202 | { |
1203 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1204 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1205 | }; |
acd5c798 MK |
1206 | struct i386_frame_cache cache; |
1207 | CORE_ADDR pc; | |
63c0089f | 1208 | gdb_byte op; |
acd5c798 | 1209 | int i; |
c5aa993b | 1210 | |
acd5c798 MK |
1211 | cache.locals = -1; |
1212 | pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache); | |
1213 | if (cache.locals < 0) | |
1214 | return start_pc; | |
c5aa993b | 1215 | |
acd5c798 | 1216 | /* Found valid frame setup. */ |
c906108c | 1217 | |
fc338970 MK |
1218 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1219 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1220 | %ebx: |
1221 | ||
fc338970 MK |
1222 | call 0x0 |
1223 | popl %ebx | |
1224 | movl %ebx,x(%ebp) (optional) | |
1225 | addl y,%ebx | |
1226 | ||
c906108c SS |
1227 | This code is with the rest of the prologue (at the end of the |
1228 | function), so we have to skip it to get to the first real | |
1229 | instruction at the start of the function. */ | |
c5aa993b | 1230 | |
c906108c SS |
1231 | for (i = 0; i < 6; i++) |
1232 | { | |
8defab1a | 1233 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1234 | if (pic_pat[i] != op) |
c906108c SS |
1235 | break; |
1236 | } | |
1237 | if (i == 6) | |
1238 | { | |
acd5c798 MK |
1239 | int delta = 6; |
1240 | ||
8defab1a | 1241 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1242 | |
c5aa993b | 1243 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1244 | { |
acd5c798 MK |
1245 | op = read_memory_unsigned_integer (pc + delta + 1, 1); |
1246 | ||
fc338970 | 1247 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1248 | delta += 3; |
fc338970 | 1249 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1250 | delta += 6; |
fc338970 | 1251 | else /* Unexpected instruction. */ |
acd5c798 MK |
1252 | delta = 0; |
1253 | ||
8defab1a | 1254 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1255 | } |
acd5c798 | 1256 | |
c5aa993b | 1257 | /* addl y,%ebx */ |
acd5c798 | 1258 | if (delta > 0 && op == 0x81 |
d5d6fca5 | 1259 | && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3) |
c906108c | 1260 | { |
acd5c798 | 1261 | pc += delta + 6; |
c906108c SS |
1262 | } |
1263 | } | |
c5aa993b | 1264 | |
e63bbc88 MK |
1265 | /* If the function starts with a branch (to startup code at the end) |
1266 | the last instruction should bring us back to the first | |
1267 | instruction of the real code. */ | |
1268 | if (i386_follow_jump (start_pc) != start_pc) | |
1269 | pc = i386_follow_jump (pc); | |
1270 | ||
1271 | return pc; | |
c906108c SS |
1272 | } |
1273 | ||
4309257c PM |
1274 | /* Check that the code pointed to by PC corresponds to a call to |
1275 | __main, skip it if so. Return PC otherwise. */ | |
1276 | ||
1277 | CORE_ADDR | |
1278 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1279 | { | |
1280 | gdb_byte op; | |
1281 | ||
1282 | target_read_memory (pc, &op, 1); | |
1283 | if (op == 0xe8) | |
1284 | { | |
1285 | gdb_byte buf[4]; | |
1286 | ||
1287 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1288 | { | |
1289 | /* Make sure address is computed correctly as a 32bit | |
1290 | integer even if CORE_ADDR is 64 bit wide. */ | |
1291 | struct minimal_symbol *s; | |
1292 | CORE_ADDR call_dest = pc + 5 + extract_signed_integer (buf, 4); | |
1293 | ||
1294 | call_dest = call_dest & 0xffffffffU; | |
1295 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1296 | if (s != NULL | |
1297 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1298 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1299 | pc += 5; | |
1300 | } | |
1301 | } | |
1302 | ||
1303 | return pc; | |
1304 | } | |
1305 | ||
acd5c798 | 1306 | /* This function is 64-bit safe. */ |
93924b6b | 1307 | |
acd5c798 MK |
1308 | static CORE_ADDR |
1309 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1310 | { |
63c0089f | 1311 | gdb_byte buf[8]; |
acd5c798 | 1312 | |
875f8d0e | 1313 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1314 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1315 | } |
acd5c798 | 1316 | \f |
93924b6b | 1317 | |
acd5c798 | 1318 | /* Normal frames. */ |
c5aa993b | 1319 | |
acd5c798 | 1320 | static struct i386_frame_cache * |
10458914 | 1321 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1322 | { |
acd5c798 | 1323 | struct i386_frame_cache *cache; |
63c0089f | 1324 | gdb_byte buf[4]; |
acd5c798 MK |
1325 | int i; |
1326 | ||
1327 | if (*this_cache) | |
1328 | return *this_cache; | |
1329 | ||
fd13a04a | 1330 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1331 | *this_cache = cache; |
1332 | ||
1333 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1334 | which holds the base address for the current stack frame. | |
1335 | However, for functions that don't need it, the frame pointer is | |
1336 | optional. For these "frameless" functions the frame pointer is | |
1337 | actually the frame pointer of the calling frame. Signal | |
1338 | trampolines are just a special case of a "frameless" function. | |
1339 | They (usually) share their frame pointer with the frame that was | |
1340 | in progress when the signal occurred. */ | |
1341 | ||
10458914 | 1342 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
acd5c798 MK |
1343 | cache->base = extract_unsigned_integer (buf, 4); |
1344 | if (cache->base == 0) | |
1345 | return cache; | |
1346 | ||
1347 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1348 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1349 | |
10458914 | 1350 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1351 | if (cache->pc != 0) |
10458914 | 1352 | i386_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache); |
acd5c798 | 1353 | |
e0c62198 | 1354 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1355 | { |
e0c62198 L |
1356 | /* Saved stack pointer has been saved. */ |
1357 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
92dd43fa MK |
1358 | cache->saved_sp = extract_unsigned_integer(buf, 4); |
1359 | } | |
1360 | ||
acd5c798 MK |
1361 | if (cache->locals < 0) |
1362 | { | |
1363 | /* We didn't find a valid frame, which means that CACHE->base | |
1364 | currently holds the frame pointer for our calling frame. If | |
1365 | we're at the start of a function, or somewhere half-way its | |
1366 | prologue, the function's frame probably hasn't been fully | |
1367 | setup yet. Try to reconstruct the base address for the stack | |
1368 | frame by looking at the stack pointer. For truly "frameless" | |
1369 | functions this might work too. */ | |
1370 | ||
e0c62198 | 1371 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1372 | { |
1373 | /* We're halfway aligning the stack. */ | |
1374 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1375 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1376 | ||
1377 | /* This will be added back below. */ | |
1378 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1379 | } | |
1380 | else | |
1381 | { | |
10458914 | 1382 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
92dd43fa MK |
1383 | cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset; |
1384 | } | |
acd5c798 MK |
1385 | } |
1386 | ||
1387 | /* Now that we have the base address for the stack frame we can | |
1388 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1389 | if (cache->saved_sp == 0) |
1390 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1391 | |
acd5c798 MK |
1392 | /* Adjust all the saved registers such that they contain addresses |
1393 | instead of offsets. */ | |
1394 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1395 | if (cache->saved_regs[i] != -1) |
1396 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1397 | |
1398 | return cache; | |
a7769679 MK |
1399 | } |
1400 | ||
3a1e71e3 | 1401 | static void |
10458914 | 1402 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1403 | struct frame_id *this_id) |
c906108c | 1404 | { |
10458914 | 1405 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1406 | |
1407 | /* This marks the outermost frame. */ | |
1408 | if (cache->base == 0) | |
1409 | return; | |
1410 | ||
3e210248 | 1411 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1412 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1413 | } | |
1414 | ||
10458914 DJ |
1415 | static struct value * |
1416 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1417 | int regnum) | |
acd5c798 | 1418 | { |
10458914 | 1419 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1420 | |
1421 | gdb_assert (regnum >= 0); | |
1422 | ||
1423 | /* The System V ABI says that: | |
1424 | ||
1425 | "The flags register contains the system flags, such as the | |
1426 | direction flag and the carry flag. The direction flag must be | |
1427 | set to the forward (that is, zero) direction before entry and | |
1428 | upon exit from a function. Other user flags have no specified | |
1429 | role in the standard calling sequence and are not preserved." | |
1430 | ||
1431 | To guarantee the "upon exit" part of that statement we fake a | |
1432 | saved flags register that has its direction flag cleared. | |
1433 | ||
1434 | Note that GCC doesn't seem to rely on the fact that the direction | |
1435 | flag is cleared after a function return; it always explicitly | |
1436 | clears the flag before operations where it matters. | |
1437 | ||
1438 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1439 | right thing to do. The way we fake the flags register here makes | |
1440 | it impossible to change it. */ | |
1441 | ||
1442 | if (regnum == I386_EFLAGS_REGNUM) | |
1443 | { | |
10458914 | 1444 | ULONGEST val; |
c5aa993b | 1445 | |
10458914 DJ |
1446 | val = get_frame_register_unsigned (this_frame, regnum); |
1447 | val &= ~(1 << 10); | |
1448 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1449 | } |
1211c4e4 | 1450 | |
acd5c798 | 1451 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1452 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1453 | |
1454 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1455 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1456 | |
fd13a04a | 1457 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1458 | return frame_unwind_got_memory (this_frame, regnum, |
1459 | cache->saved_regs[regnum]); | |
fd13a04a | 1460 | |
10458914 | 1461 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1462 | } |
1463 | ||
1464 | static const struct frame_unwind i386_frame_unwind = | |
1465 | { | |
1466 | NORMAL_FRAME, | |
1467 | i386_frame_this_id, | |
10458914 DJ |
1468 | i386_frame_prev_register, |
1469 | NULL, | |
1470 | default_frame_sniffer | |
acd5c798 | 1471 | }; |
acd5c798 MK |
1472 | \f |
1473 | ||
1474 | /* Signal trampolines. */ | |
1475 | ||
1476 | static struct i386_frame_cache * | |
10458914 | 1477 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 MK |
1478 | { |
1479 | struct i386_frame_cache *cache; | |
10458914 | 1480 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1481 | CORE_ADDR addr; |
63c0089f | 1482 | gdb_byte buf[4]; |
acd5c798 MK |
1483 | |
1484 | if (*this_cache) | |
1485 | return *this_cache; | |
1486 | ||
fd13a04a | 1487 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1488 | |
10458914 | 1489 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 MK |
1490 | cache->base = extract_unsigned_integer (buf, 4) - 4; |
1491 | ||
10458914 | 1492 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1493 | if (tdep->sc_reg_offset) |
1494 | { | |
1495 | int i; | |
1496 | ||
1497 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1498 | ||
1499 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1500 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1501 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1502 | } |
1503 | else | |
1504 | { | |
fd13a04a AC |
1505 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1506 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1507 | } |
acd5c798 MK |
1508 | |
1509 | *this_cache = cache; | |
1510 | return cache; | |
1511 | } | |
1512 | ||
1513 | static void | |
10458914 | 1514 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1515 | struct frame_id *this_id) |
1516 | { | |
1517 | struct i386_frame_cache *cache = | |
10458914 | 1518 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1519 | |
3e210248 | 1520 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1521 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1522 | } |
1523 | ||
10458914 DJ |
1524 | static struct value * |
1525 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1526 | void **this_cache, int regnum) | |
acd5c798 MK |
1527 | { |
1528 | /* Make sure we've initialized the cache. */ | |
10458914 | 1529 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1530 | |
10458914 | 1531 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1532 | } |
c0d1d883 | 1533 | |
10458914 DJ |
1534 | static int |
1535 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1536 | struct frame_info *this_frame, | |
1537 | void **this_prologue_cache) | |
acd5c798 | 1538 | { |
10458914 | 1539 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1540 | |
911bc6ee MK |
1541 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1542 | handler. */ | |
1543 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1544 | return 0; |
1c3545ae | 1545 | |
911bc6ee MK |
1546 | if (tdep->sigtramp_p != NULL) |
1547 | { | |
10458914 DJ |
1548 | if (tdep->sigtramp_p (this_frame)) |
1549 | return 1; | |
911bc6ee MK |
1550 | } |
1551 | ||
1552 | if (tdep->sigtramp_start != 0) | |
1553 | { | |
10458914 | 1554 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1555 | |
1556 | gdb_assert (tdep->sigtramp_end != 0); | |
1557 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1558 | return 1; |
911bc6ee | 1559 | } |
acd5c798 | 1560 | |
10458914 | 1561 | return 0; |
acd5c798 | 1562 | } |
10458914 DJ |
1563 | |
1564 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1565 | { | |
1566 | SIGTRAMP_FRAME, | |
1567 | i386_sigtramp_frame_this_id, | |
1568 | i386_sigtramp_frame_prev_register, | |
1569 | NULL, | |
1570 | i386_sigtramp_frame_sniffer | |
1571 | }; | |
acd5c798 MK |
1572 | \f |
1573 | ||
1574 | static CORE_ADDR | |
10458914 | 1575 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1576 | { |
10458914 | 1577 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1578 | |
1579 | return cache->base; | |
1580 | } | |
1581 | ||
1582 | static const struct frame_base i386_frame_base = | |
1583 | { | |
1584 | &i386_frame_unwind, | |
1585 | i386_frame_base_address, | |
1586 | i386_frame_base_address, | |
1587 | i386_frame_base_address | |
1588 | }; | |
1589 | ||
acd5c798 | 1590 | static struct frame_id |
10458914 | 1591 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1592 | { |
acd5c798 MK |
1593 | CORE_ADDR fp; |
1594 | ||
10458914 | 1595 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1596 | |
3e210248 | 1597 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1598 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1599 | } |
fc338970 | 1600 | \f |
c906108c | 1601 | |
fc338970 MK |
1602 | /* Figure out where the longjmp will land. Slurp the args out of the |
1603 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1604 | structure from which we extract the address that we will land at. |
28bcfd30 | 1605 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1606 | success. */ |
c906108c | 1607 | |
8201327c | 1608 | static int |
60ade65d | 1609 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1610 | { |
436675d3 | 1611 | gdb_byte buf[4]; |
c906108c | 1612 | CORE_ADDR sp, jb_addr; |
20a6ec49 MD |
1613 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1614 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
c906108c | 1615 | |
8201327c MK |
1616 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1617 | longjmp will land. */ | |
1618 | if (jb_pc_offset == -1) | |
c906108c SS |
1619 | return 0; |
1620 | ||
436675d3 PA |
1621 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
1622 | sp = extract_unsigned_integer (buf, 4); | |
1623 | if (target_read_memory (sp + 4, buf, 4)) | |
c906108c SS |
1624 | return 0; |
1625 | ||
436675d3 PA |
1626 | jb_addr = extract_unsigned_integer (buf, 4); |
1627 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) | |
8201327c | 1628 | return 0; |
c906108c | 1629 | |
436675d3 | 1630 | *pc = extract_unsigned_integer (buf, 4); |
c906108c SS |
1631 | return 1; |
1632 | } | |
fc338970 | 1633 | \f |
c906108c | 1634 | |
7ccc1c74 JM |
1635 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1636 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1637 | unions containing such types must be 16-byte-aligned; other | |
1638 | arguments are 4-byte-aligned. */ | |
1639 | ||
1640 | static int | |
1641 | i386_16_byte_align_p (struct type *type) | |
1642 | { | |
1643 | type = check_typedef (type); | |
1644 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1645 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1646 | && TYPE_LENGTH (type) == 16) | |
1647 | return 1; | |
1648 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1649 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1650 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1651 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1652 | { | |
1653 | int i; | |
1654 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1655 | { | |
1656 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1657 | return 1; | |
1658 | } | |
1659 | } | |
1660 | return 0; | |
1661 | } | |
1662 | ||
3a1e71e3 | 1663 | static CORE_ADDR |
7d9b040b | 1664 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1665 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1666 | struct value **args, CORE_ADDR sp, int struct_return, | |
1667 | CORE_ADDR struct_addr) | |
22f8ba57 | 1668 | { |
63c0089f | 1669 | gdb_byte buf[4]; |
acd5c798 | 1670 | int i; |
7ccc1c74 JM |
1671 | int write_pass; |
1672 | int args_space = 0; | |
acd5c798 | 1673 | |
7ccc1c74 JM |
1674 | /* Determine the total space required for arguments and struct |
1675 | return address in a first pass (allowing for 16-byte-aligned | |
1676 | arguments), then push arguments in a second pass. */ | |
1677 | ||
1678 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1679 | { |
7ccc1c74 JM |
1680 | int args_space_used = 0; |
1681 | int have_16_byte_aligned_arg = 0; | |
1682 | ||
1683 | if (struct_return) | |
1684 | { | |
1685 | if (write_pass) | |
1686 | { | |
1687 | /* Push value address. */ | |
1688 | store_unsigned_integer (buf, 4, struct_addr); | |
1689 | write_memory (sp, buf, 4); | |
1690 | args_space_used += 4; | |
1691 | } | |
1692 | else | |
1693 | args_space += 4; | |
1694 | } | |
1695 | ||
1696 | for (i = 0; i < nargs; i++) | |
1697 | { | |
1698 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1699 | |
7ccc1c74 JM |
1700 | if (write_pass) |
1701 | { | |
1702 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1703 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1704 | |
7ccc1c74 JM |
1705 | write_memory (sp + args_space_used, |
1706 | value_contents_all (args[i]), len); | |
1707 | /* The System V ABI says that: | |
acd5c798 | 1708 | |
7ccc1c74 JM |
1709 | "An argument's size is increased, if necessary, to make it a |
1710 | multiple of [32-bit] words. This may require tail padding, | |
1711 | depending on the size of the argument." | |
22f8ba57 | 1712 | |
7ccc1c74 JM |
1713 | This makes sure the stack stays word-aligned. */ |
1714 | args_space_used += align_up (len, 4); | |
1715 | } | |
1716 | else | |
1717 | { | |
1718 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1719 | { | |
1720 | args_space = align_up (args_space, 16); | |
1721 | have_16_byte_aligned_arg = 1; | |
1722 | } | |
1723 | args_space += align_up (len, 4); | |
1724 | } | |
1725 | } | |
1726 | ||
1727 | if (!write_pass) | |
1728 | { | |
1729 | if (have_16_byte_aligned_arg) | |
1730 | args_space = align_up (args_space, 16); | |
1731 | sp -= args_space; | |
1732 | } | |
22f8ba57 MK |
1733 | } |
1734 | ||
acd5c798 MK |
1735 | /* Store return address. */ |
1736 | sp -= 4; | |
6a65450a | 1737 | store_unsigned_integer (buf, 4, bp_addr); |
acd5c798 MK |
1738 | write_memory (sp, buf, 4); |
1739 | ||
1740 | /* Finally, update the stack pointer... */ | |
1741 | store_unsigned_integer (buf, 4, sp); | |
1742 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); | |
1743 | ||
1744 | /* ...and fake a frame pointer. */ | |
1745 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1746 | ||
3e210248 AC |
1747 | /* MarkK wrote: This "+ 8" is all over the place: |
1748 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1749 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1750 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1751 | definition of the stack address of a frame. Otherwise frame id |
1752 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1753 | stack address *before* the function call as a frame's CFA. On |
1754 | the i386, when %ebp is used as a frame pointer, the offset | |
1755 | between the contents %ebp and the CFA as defined by GCC. */ | |
1756 | return sp + 8; | |
22f8ba57 MK |
1757 | } |
1758 | ||
1a309862 MK |
1759 | /* These registers are used for returning integers (and on some |
1760 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1761 | size and alignment match an integer type). */ |
acd5c798 MK |
1762 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1763 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1764 | |
c5e656c1 MK |
1765 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1766 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1767 | |
3a1e71e3 | 1768 | static void |
c5e656c1 | 1769 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1770 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1771 | { |
c5e656c1 | 1772 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1773 | int len = TYPE_LENGTH (type); |
63c0089f | 1774 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1775 | |
1e8d0a7b | 1776 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1777 | { |
5716833c | 1778 | if (tdep->st0_regnum < 0) |
1a309862 | 1779 | { |
8a3fe4f8 | 1780 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1781 | memset (valbuf, 0, len); |
ef9dff19 | 1782 | return; |
1a309862 MK |
1783 | } |
1784 | ||
c6ba6f0d MK |
1785 | /* Floating-point return values can be found in %st(0). Convert |
1786 | its contents to the desired type. This is probably not | |
1787 | exactly how it would happen on the target itself, but it is | |
1788 | the best we can do. */ | |
acd5c798 | 1789 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
00f8375e | 1790 | convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type); |
c906108c SS |
1791 | } |
1792 | else | |
c5aa993b | 1793 | { |
875f8d0e UW |
1794 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1795 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1796 | |
1797 | if (len <= low_size) | |
00f8375e | 1798 | { |
0818c12a | 1799 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1800 | memcpy (valbuf, buf, len); |
1801 | } | |
d4f3574e SS |
1802 | else if (len <= (low_size + high_size)) |
1803 | { | |
0818c12a | 1804 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1805 | memcpy (valbuf, buf, low_size); |
0818c12a | 1806 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1807 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1808 | } |
1809 | else | |
8e65ff28 | 1810 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1811 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1812 | } |
1813 | } | |
1814 | ||
c5e656c1 MK |
1815 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1816 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1817 | |
3a1e71e3 | 1818 | static void |
c5e656c1 | 1819 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1820 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1821 | { |
c5e656c1 | 1822 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1823 | int len = TYPE_LENGTH (type); |
1824 | ||
1e8d0a7b | 1825 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1826 | { |
3d7f4f49 | 1827 | ULONGEST fstat; |
63c0089f | 1828 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1829 | |
5716833c | 1830 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1831 | { |
8a3fe4f8 | 1832 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1833 | return; |
1834 | } | |
1835 | ||
635b0cc1 MK |
1836 | /* Returning floating-point values is a bit tricky. Apart from |
1837 | storing the return value in %st(0), we have to simulate the | |
1838 | state of the FPU at function return point. */ | |
1839 | ||
c6ba6f0d MK |
1840 | /* Convert the value found in VALBUF to the extended |
1841 | floating-point format used by the FPU. This is probably | |
1842 | not exactly how it would happen on the target itself, but | |
1843 | it is the best we can do. */ | |
1844 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
acd5c798 | 1845 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1846 | |
635b0cc1 MK |
1847 | /* Set the top of the floating-point register stack to 7. The |
1848 | actual value doesn't really matter, but 7 is what a normal | |
1849 | function return would end up with if the program started out | |
1850 | with a freshly initialized FPU. */ | |
20a6ec49 | 1851 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1852 | fstat |= (7 << 11); |
20a6ec49 | 1853 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1854 | |
635b0cc1 MK |
1855 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1856 | the floating-point register stack to 7, the appropriate value | |
1857 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1858 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1859 | } |
1860 | else | |
1861 | { | |
875f8d0e UW |
1862 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1863 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1864 | |
1865 | if (len <= low_size) | |
3d7f4f49 | 1866 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1867 | else if (len <= (low_size + high_size)) |
1868 | { | |
3d7f4f49 MK |
1869 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1870 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1871 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1872 | } |
1873 | else | |
8e65ff28 | 1874 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1875 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1876 | } |
1877 | } | |
fc338970 | 1878 | \f |
ef9dff19 | 1879 | |
8201327c MK |
1880 | /* This is the variable that is set with "set struct-convention", and |
1881 | its legitimate values. */ | |
1882 | static const char default_struct_convention[] = "default"; | |
1883 | static const char pcc_struct_convention[] = "pcc"; | |
1884 | static const char reg_struct_convention[] = "reg"; | |
1885 | static const char *valid_conventions[] = | |
1886 | { | |
1887 | default_struct_convention, | |
1888 | pcc_struct_convention, | |
1889 | reg_struct_convention, | |
1890 | NULL | |
1891 | }; | |
1892 | static const char *struct_convention = default_struct_convention; | |
1893 | ||
0e4377e1 JB |
1894 | /* Return non-zero if TYPE, which is assumed to be a structure, |
1895 | a union type, or an array type, should be returned in registers | |
1896 | for architecture GDBARCH. */ | |
c5e656c1 | 1897 | |
8201327c | 1898 | static int |
c5e656c1 | 1899 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 1900 | { |
c5e656c1 MK |
1901 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1902 | enum type_code code = TYPE_CODE (type); | |
1903 | int len = TYPE_LENGTH (type); | |
8201327c | 1904 | |
0e4377e1 JB |
1905 | gdb_assert (code == TYPE_CODE_STRUCT |
1906 | || code == TYPE_CODE_UNION | |
1907 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
1908 | |
1909 | if (struct_convention == pcc_struct_convention | |
1910 | || (struct_convention == default_struct_convention | |
1911 | && tdep->struct_return == pcc_struct_return)) | |
1912 | return 0; | |
1913 | ||
9edde48e MK |
1914 | /* Structures consisting of a single `float', `double' or 'long |
1915 | double' member are returned in %st(0). */ | |
1916 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
1917 | { | |
1918 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1919 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1920 | return (len == 4 || len == 8 || len == 12); | |
1921 | } | |
1922 | ||
c5e656c1 MK |
1923 | return (len == 1 || len == 2 || len == 4 || len == 8); |
1924 | } | |
1925 | ||
1926 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
1927 | should be returned. If it is supposed to be returned in registers, | |
1928 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
1929 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
1930 | from WRITEBUF into REGCACHE. */ | |
1931 | ||
1932 | static enum return_value_convention | |
c055b101 CV |
1933 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1934 | struct type *type, struct regcache *regcache, | |
1935 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
1936 | { |
1937 | enum type_code code = TYPE_CODE (type); | |
1938 | ||
5daa78cc TJB |
1939 | if (((code == TYPE_CODE_STRUCT |
1940 | || code == TYPE_CODE_UNION | |
1941 | || code == TYPE_CODE_ARRAY) | |
1942 | && !i386_reg_struct_return_p (gdbarch, type)) | |
1943 | /* 128-bit decimal float uses the struct return convention. */ | |
1944 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
1945 | { |
1946 | /* The System V ABI says that: | |
1947 | ||
1948 | "A function that returns a structure or union also sets %eax | |
1949 | to the value of the original address of the caller's area | |
1950 | before it returns. Thus when the caller receives control | |
1951 | again, the address of the returned object resides in register | |
1952 | %eax and can be used to access the object." | |
1953 | ||
1954 | So the ABI guarantees that we can always find the return | |
1955 | value just after the function has returned. */ | |
1956 | ||
0e4377e1 JB |
1957 | /* Note that the ABI doesn't mention functions returning arrays, |
1958 | which is something possible in certain languages such as Ada. | |
1959 | In this case, the value is returned as if it was wrapped in | |
1960 | a record, so the convention applied to records also applies | |
1961 | to arrays. */ | |
1962 | ||
31db7b6c MK |
1963 | if (readbuf) |
1964 | { | |
1965 | ULONGEST addr; | |
1966 | ||
1967 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
1968 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1969 | } | |
1970 | ||
1971 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
1972 | } | |
c5e656c1 MK |
1973 | |
1974 | /* This special case is for structures consisting of a single | |
9edde48e MK |
1975 | `float', `double' or 'long double' member. These structures are |
1976 | returned in %st(0). For these structures, we call ourselves | |
1977 | recursively, changing TYPE into the type of the first member of | |
1978 | the structure. Since that should work for all structures that | |
1979 | have only one member, we don't bother to check the member's type | |
1980 | here. */ | |
c5e656c1 MK |
1981 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
1982 | { | |
1983 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
1984 | return i386_return_value (gdbarch, func_type, type, regcache, |
1985 | readbuf, writebuf); | |
c5e656c1 MK |
1986 | } |
1987 | ||
1988 | if (readbuf) | |
1989 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
1990 | if (writebuf) | |
1991 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 1992 | |
c5e656c1 | 1993 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
1994 | } |
1995 | \f | |
1996 | ||
5ae96ec1 MK |
1997 | /* Type for %eflags. */ |
1998 | struct type *i386_eflags_type; | |
1999 | ||
794ac428 | 2000 | /* Type for %mxcsr. */ |
878d9193 | 2001 | struct type *i386_mxcsr_type; |
5ae96ec1 MK |
2002 | |
2003 | /* Construct types for ISA-specific registers. */ | |
2004 | static void | |
2005 | i386_init_types (void) | |
2006 | { | |
2007 | struct type *type; | |
2008 | ||
2009 | type = init_flags_type ("builtin_type_i386_eflags", 4); | |
2010 | append_flags_type_flag (type, 0, "CF"); | |
2011 | append_flags_type_flag (type, 1, NULL); | |
2012 | append_flags_type_flag (type, 2, "PF"); | |
2013 | append_flags_type_flag (type, 4, "AF"); | |
2014 | append_flags_type_flag (type, 6, "ZF"); | |
2015 | append_flags_type_flag (type, 7, "SF"); | |
2016 | append_flags_type_flag (type, 8, "TF"); | |
2017 | append_flags_type_flag (type, 9, "IF"); | |
2018 | append_flags_type_flag (type, 10, "DF"); | |
2019 | append_flags_type_flag (type, 11, "OF"); | |
2020 | append_flags_type_flag (type, 14, "NT"); | |
2021 | append_flags_type_flag (type, 16, "RF"); | |
2022 | append_flags_type_flag (type, 17, "VM"); | |
2023 | append_flags_type_flag (type, 18, "AC"); | |
2024 | append_flags_type_flag (type, 19, "VIF"); | |
2025 | append_flags_type_flag (type, 20, "VIP"); | |
2026 | append_flags_type_flag (type, 21, "ID"); | |
2027 | i386_eflags_type = type; | |
21b4b2f2 | 2028 | |
878d9193 MK |
2029 | type = init_flags_type ("builtin_type_i386_mxcsr", 4); |
2030 | append_flags_type_flag (type, 0, "IE"); | |
2031 | append_flags_type_flag (type, 1, "DE"); | |
2032 | append_flags_type_flag (type, 2, "ZE"); | |
2033 | append_flags_type_flag (type, 3, "OE"); | |
2034 | append_flags_type_flag (type, 4, "UE"); | |
2035 | append_flags_type_flag (type, 5, "PE"); | |
2036 | append_flags_type_flag (type, 6, "DAZ"); | |
2037 | append_flags_type_flag (type, 7, "IM"); | |
2038 | append_flags_type_flag (type, 8, "DM"); | |
2039 | append_flags_type_flag (type, 9, "ZM"); | |
2040 | append_flags_type_flag (type, 10, "OM"); | |
2041 | append_flags_type_flag (type, 11, "UM"); | |
2042 | append_flags_type_flag (type, 12, "PM"); | |
2043 | append_flags_type_flag (type, 15, "FZ"); | |
2044 | i386_mxcsr_type = type; | |
21b4b2f2 JB |
2045 | } |
2046 | ||
794ac428 UW |
2047 | /* Construct vector type for MMX registers. */ |
2048 | struct type * | |
2049 | i386_mmx_type (struct gdbarch *gdbarch) | |
2050 | { | |
2051 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2052 | ||
2053 | if (!tdep->i386_mmx_type) | |
2054 | { | |
2055 | /* The type we're building is this: */ | |
2056 | #if 0 | |
2057 | union __gdb_builtin_type_vec64i | |
2058 | { | |
2059 | int64_t uint64; | |
2060 | int32_t v2_int32[2]; | |
2061 | int16_t v4_int16[4]; | |
2062 | int8_t v8_int8[8]; | |
2063 | }; | |
2064 | #endif | |
2065 | ||
2066 | struct type *t; | |
2067 | ||
2068 | t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
2069 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
2070 | append_composite_type_field (t, "v2_int32", | |
2071 | init_vector_type (builtin_type_int32, 2)); | |
2072 | append_composite_type_field (t, "v4_int16", | |
2073 | init_vector_type (builtin_type_int16, 4)); | |
2074 | append_composite_type_field (t, "v8_int8", | |
2075 | init_vector_type (builtin_type_int8, 8)); | |
2076 | ||
876cecd0 | 2077 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2078 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2079 | tdep->i386_mmx_type = t; | |
2080 | } | |
2081 | ||
2082 | return tdep->i386_mmx_type; | |
2083 | } | |
2084 | ||
2085 | struct type * | |
2086 | i386_sse_type (struct gdbarch *gdbarch) | |
2087 | { | |
2088 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2089 | ||
2090 | if (!tdep->i386_sse_type) | |
2091 | { | |
2092 | /* The type we're building is this: */ | |
2093 | #if 0 | |
2094 | union __gdb_builtin_type_vec128i | |
2095 | { | |
2096 | int128_t uint128; | |
2097 | int64_t v2_int64[2]; | |
2098 | int32_t v4_int32[4]; | |
2099 | int16_t v8_int16[8]; | |
2100 | int8_t v16_int8[16]; | |
2101 | double v2_double[2]; | |
2102 | float v4_float[4]; | |
2103 | }; | |
2104 | #endif | |
2105 | ||
2106 | struct type *t; | |
2107 | ||
2108 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
2109 | append_composite_type_field (t, "v4_float", | |
0dfff4cb UW |
2110 | init_vector_type (builtin_type (gdbarch) |
2111 | ->builtin_float, 4)); | |
794ac428 | 2112 | append_composite_type_field (t, "v2_double", |
0dfff4cb UW |
2113 | init_vector_type (builtin_type (gdbarch) |
2114 | ->builtin_double, 2)); | |
794ac428 UW |
2115 | append_composite_type_field (t, "v16_int8", |
2116 | init_vector_type (builtin_type_int8, 16)); | |
2117 | append_composite_type_field (t, "v8_int16", | |
2118 | init_vector_type (builtin_type_int16, 8)); | |
2119 | append_composite_type_field (t, "v4_int32", | |
2120 | init_vector_type (builtin_type_int32, 4)); | |
2121 | append_composite_type_field (t, "v2_int64", | |
2122 | init_vector_type (builtin_type_int64, 2)); | |
2123 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
2124 | ||
876cecd0 | 2125 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2126 | TYPE_NAME (t) = "builtin_type_vec128i"; |
2127 | tdep->i386_sse_type = t; | |
2128 | } | |
2129 | ||
2130 | return tdep->i386_sse_type; | |
2131 | } | |
2132 | ||
d7a0d72c MK |
2133 | /* Return the GDB type object for the "standard" data type of data in |
2134 | register REGNUM. Perhaps %esi and %edi should go here, but | |
2135 | potentially they could be used for things other than address. */ | |
2136 | ||
3a1e71e3 | 2137 | static struct type * |
4e259f09 | 2138 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2139 | { |
ab533587 | 2140 | if (regnum == I386_EIP_REGNUM) |
0dfff4cb | 2141 | return builtin_type (gdbarch)->builtin_func_ptr; |
ab533587 | 2142 | |
5ae96ec1 MK |
2143 | if (regnum == I386_EFLAGS_REGNUM) |
2144 | return i386_eflags_type; | |
2145 | ||
ab533587 | 2146 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) |
0dfff4cb | 2147 | return builtin_type (gdbarch)->builtin_data_ptr; |
d7a0d72c | 2148 | |
20a6ec49 | 2149 | if (i386_fp_regnum_p (gdbarch, regnum)) |
c6ba6f0d | 2150 | return builtin_type_i387_ext; |
d7a0d72c | 2151 | |
878d9193 | 2152 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
794ac428 | 2153 | return i386_mmx_type (gdbarch); |
878d9193 | 2154 | |
5716833c | 2155 | if (i386_sse_regnum_p (gdbarch, regnum)) |
794ac428 | 2156 | return i386_sse_type (gdbarch); |
d7a0d72c | 2157 | |
20a6ec49 | 2158 | if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch))) |
878d9193 MK |
2159 | return i386_mxcsr_type; |
2160 | ||
0dfff4cb | 2161 | return builtin_type (gdbarch)->builtin_int; |
d7a0d72c MK |
2162 | } |
2163 | ||
28fc6740 | 2164 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2165 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2166 | |
2167 | static int | |
c86c27af | 2168 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2169 | { |
5716833c MK |
2170 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2171 | int mmxreg, fpreg; | |
28fc6740 AC |
2172 | ULONGEST fstat; |
2173 | int tos; | |
c86c27af | 2174 | |
5716833c | 2175 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2176 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2177 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2178 | fpreg = (mmxreg + tos) % 8; |
2179 | ||
20a6ec49 | 2180 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2181 | } |
2182 | ||
2183 | static void | |
2184 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2185 | int regnum, gdb_byte *buf) |
28fc6740 | 2186 | { |
5716833c | 2187 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2188 | { |
63c0089f | 2189 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2190 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2191 | ||
28fc6740 | 2192 | /* Extract (always little endian). */ |
c86c27af | 2193 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2194 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2195 | } |
2196 | else | |
2197 | regcache_raw_read (regcache, regnum, buf); | |
2198 | } | |
2199 | ||
2200 | static void | |
2201 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2202 | int regnum, const gdb_byte *buf) |
28fc6740 | 2203 | { |
5716833c | 2204 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2205 | { |
63c0089f | 2206 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2207 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2208 | ||
28fc6740 AC |
2209 | /* Read ... */ |
2210 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2211 | /* ... Modify ... (always little endian). */ | |
f837910f | 2212 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2213 | /* ... Write. */ |
2214 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2215 | } | |
2216 | else | |
2217 | regcache_raw_write (regcache, regnum, buf); | |
2218 | } | |
ff2e87ac AC |
2219 | \f |
2220 | ||
ff2e87ac AC |
2221 | /* Return the register number of the register allocated by GCC after |
2222 | REGNUM, or -1 if there is no such register. */ | |
2223 | ||
2224 | static int | |
2225 | i386_next_regnum (int regnum) | |
2226 | { | |
2227 | /* GCC allocates the registers in the order: | |
2228 | ||
2229 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2230 | ||
2231 | Since storing a variable in %esp doesn't make any sense we return | |
2232 | -1 for %ebp and for %esp itself. */ | |
2233 | static int next_regnum[] = | |
2234 | { | |
2235 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2236 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2237 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2238 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2239 | -1, -1, /* Slots for %esp and %ebp. */ | |
2240 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2241 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2242 | }; | |
2243 | ||
de5b9bb9 | 2244 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2245 | return next_regnum[regnum]; |
28fc6740 | 2246 | |
ff2e87ac AC |
2247 | return -1; |
2248 | } | |
2249 | ||
2250 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2251 | needs any special handling. */ | |
d7a0d72c | 2252 | |
3a1e71e3 | 2253 | static int |
0abe36f5 | 2254 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2255 | { |
de5b9bb9 MK |
2256 | int len = TYPE_LENGTH (type); |
2257 | ||
ff2e87ac AC |
2258 | /* Values may be spread across multiple registers. Most debugging |
2259 | formats aren't expressive enough to specify the locations, so | |
2260 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2261 | have a length that is a multiple of the word size, since GCC |
2262 | doesn't seem to put any other types into registers. */ | |
2263 | if (len > 4 && len % 4 == 0) | |
2264 | { | |
2265 | int last_regnum = regnum; | |
2266 | ||
2267 | while (len > 4) | |
2268 | { | |
2269 | last_regnum = i386_next_regnum (last_regnum); | |
2270 | len -= 4; | |
2271 | } | |
2272 | ||
2273 | if (last_regnum != -1) | |
2274 | return 1; | |
2275 | } | |
ff2e87ac | 2276 | |
0abe36f5 | 2277 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2278 | } |
2279 | ||
ff2e87ac AC |
2280 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2281 | return its contents in TO. */ | |
ac27f131 | 2282 | |
3a1e71e3 | 2283 | static void |
ff2e87ac | 2284 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2285 | struct type *type, gdb_byte *to) |
ac27f131 | 2286 | { |
20a6ec49 | 2287 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2288 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2289 | |
ff2e87ac AC |
2290 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2291 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2292 | |
20a6ec49 | 2293 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2294 | { |
d532c08f MK |
2295 | i387_register_to_value (frame, regnum, type, to); |
2296 | return; | |
8d7f6b4a | 2297 | } |
ff2e87ac | 2298 | |
fd35795f | 2299 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2300 | |
2301 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2302 | |
de5b9bb9 MK |
2303 | while (len > 0) |
2304 | { | |
2305 | gdb_assert (regnum != -1); | |
20a6ec49 | 2306 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2307 | |
42835c2b | 2308 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2309 | regnum = i386_next_regnum (regnum); |
2310 | len -= 4; | |
42835c2b | 2311 | to += 4; |
de5b9bb9 | 2312 | } |
ac27f131 MK |
2313 | } |
2314 | ||
ff2e87ac AC |
2315 | /* Write the contents FROM of a value of type TYPE into register |
2316 | REGNUM in frame FRAME. */ | |
ac27f131 | 2317 | |
3a1e71e3 | 2318 | static void |
ff2e87ac | 2319 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2320 | struct type *type, const gdb_byte *from) |
ac27f131 | 2321 | { |
de5b9bb9 | 2322 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2323 | |
20a6ec49 | 2324 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2325 | { |
d532c08f MK |
2326 | i387_value_to_register (frame, regnum, type, from); |
2327 | return; | |
2328 | } | |
3d261580 | 2329 | |
fd35795f | 2330 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2331 | |
2332 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2333 | |
de5b9bb9 MK |
2334 | while (len > 0) |
2335 | { | |
2336 | gdb_assert (regnum != -1); | |
875f8d0e | 2337 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2338 | |
42835c2b | 2339 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2340 | regnum = i386_next_regnum (regnum); |
2341 | len -= 4; | |
42835c2b | 2342 | from += 4; |
de5b9bb9 | 2343 | } |
ac27f131 | 2344 | } |
ff2e87ac | 2345 | \f |
7fdafb5a MK |
2346 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2347 | in the general-purpose register set REGSET to register cache | |
2348 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2349 | |
20187ed5 | 2350 | void |
473f17b0 MK |
2351 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2352 | int regnum, const void *gregs, size_t len) | |
2353 | { | |
9ea75c57 | 2354 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2355 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2356 | int i; |
2357 | ||
2358 | gdb_assert (len == tdep->sizeof_gregset); | |
2359 | ||
2360 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2361 | { | |
2362 | if ((regnum == i || regnum == -1) | |
2363 | && tdep->gregset_reg_offset[i] != -1) | |
2364 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2365 | } | |
2366 | } | |
2367 | ||
7fdafb5a MK |
2368 | /* Collect register REGNUM from the register cache REGCACHE and store |
2369 | it in the buffer specified by GREGS and LEN as described by the | |
2370 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2371 | all registers in REGSET. */ | |
2372 | ||
2373 | void | |
2374 | i386_collect_gregset (const struct regset *regset, | |
2375 | const struct regcache *regcache, | |
2376 | int regnum, void *gregs, size_t len) | |
2377 | { | |
2378 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2379 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2380 | int i; |
2381 | ||
2382 | gdb_assert (len == tdep->sizeof_gregset); | |
2383 | ||
2384 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2385 | { | |
2386 | if ((regnum == i || regnum == -1) | |
2387 | && tdep->gregset_reg_offset[i] != -1) | |
2388 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2389 | } | |
2390 | } | |
2391 | ||
2392 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2393 | in the floating-point register set REGSET to register cache | |
2394 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2395 | |
2396 | static void | |
2397 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2398 | int regnum, const void *fpregs, size_t len) | |
2399 | { | |
9ea75c57 | 2400 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2401 | |
66a72d25 MK |
2402 | if (len == I387_SIZEOF_FXSAVE) |
2403 | { | |
2404 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2405 | return; | |
2406 | } | |
2407 | ||
473f17b0 MK |
2408 | gdb_assert (len == tdep->sizeof_fpregset); |
2409 | i387_supply_fsave (regcache, regnum, fpregs); | |
2410 | } | |
8446b36a | 2411 | |
2f305df1 MK |
2412 | /* Collect register REGNUM from the register cache REGCACHE and store |
2413 | it in the buffer specified by FPREGS and LEN as described by the | |
2414 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2415 | all registers in REGSET. */ | |
7fdafb5a MK |
2416 | |
2417 | static void | |
2418 | i386_collect_fpregset (const struct regset *regset, | |
2419 | const struct regcache *regcache, | |
2420 | int regnum, void *fpregs, size_t len) | |
2421 | { | |
2422 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2423 | ||
2424 | if (len == I387_SIZEOF_FXSAVE) | |
2425 | { | |
2426 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2427 | return; | |
2428 | } | |
2429 | ||
2430 | gdb_assert (len == tdep->sizeof_fpregset); | |
2431 | i387_collect_fsave (regcache, regnum, fpregs); | |
2432 | } | |
2433 | ||
8446b36a MK |
2434 | /* Return the appropriate register set for the core section identified |
2435 | by SECT_NAME and SECT_SIZE. */ | |
2436 | ||
2437 | const struct regset * | |
2438 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2439 | const char *sect_name, size_t sect_size) | |
2440 | { | |
2441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2442 | ||
2443 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2444 | { | |
2445 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2446 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2447 | i386_collect_gregset); | |
8446b36a MK |
2448 | return tdep->gregset; |
2449 | } | |
2450 | ||
66a72d25 MK |
2451 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2452 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2453 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2454 | { |
2455 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2456 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2457 | i386_collect_fpregset); | |
8446b36a MK |
2458 | return tdep->fpregset; |
2459 | } | |
2460 | ||
2461 | return NULL; | |
2462 | } | |
473f17b0 | 2463 | \f |
fc338970 | 2464 | |
fc338970 | 2465 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2466 | |
2467 | CORE_ADDR | |
1cce71eb | 2468 | i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name) |
c906108c | 2469 | { |
fc338970 | 2470 | if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */ |
c906108c | 2471 | { |
c5aa993b | 2472 | unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4); |
c906108c | 2473 | struct minimal_symbol *indsym = |
fc338970 | 2474 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2475 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2476 | |
c5aa993b | 2477 | if (symname) |
c906108c | 2478 | { |
c5aa993b JM |
2479 | if (strncmp (symname, "__imp_", 6) == 0 |
2480 | || strncmp (symname, "_imp_", 5) == 0) | |
c906108c SS |
2481 | return name ? 1 : read_memory_unsigned_integer (indirect, 4); |
2482 | } | |
2483 | } | |
fc338970 | 2484 | return 0; /* Not a trampoline. */ |
c906108c | 2485 | } |
fc338970 MK |
2486 | \f |
2487 | ||
10458914 DJ |
2488 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2489 | routine. */ | |
8201327c | 2490 | |
4bd207ef | 2491 | int |
10458914 | 2492 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2493 | { |
10458914 | 2494 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2495 | char *name; |
2496 | ||
2497 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2498 | return (name && strcmp ("_sigtramp", name) == 0); |
2499 | } | |
2500 | \f | |
2501 | ||
fc338970 MK |
2502 | /* We have two flavours of disassembly. The machinery on this page |
2503 | deals with switching between those. */ | |
c906108c SS |
2504 | |
2505 | static int | |
a89aa300 | 2506 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2507 | { |
5e3397bb MK |
2508 | gdb_assert (disassembly_flavor == att_flavor |
2509 | || disassembly_flavor == intel_flavor); | |
2510 | ||
2511 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2512 | constified, cast to prevent a compiler warning. */ | |
2513 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2514 | |
2515 | return print_insn_i386 (pc, info); | |
7a292a7a | 2516 | } |
fc338970 | 2517 | \f |
3ce1502b | 2518 | |
8201327c MK |
2519 | /* There are a few i386 architecture variants that differ only |
2520 | slightly from the generic i386 target. For now, we don't give them | |
2521 | their own source file, but include them here. As a consequence, | |
2522 | they'll always be included. */ | |
3ce1502b | 2523 | |
8201327c | 2524 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2525 | |
10458914 DJ |
2526 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2527 | routine. */ | |
911bc6ee | 2528 | |
8201327c | 2529 | static int |
10458914 | 2530 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2531 | { |
10458914 | 2532 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2533 | char *name; |
2534 | ||
acd5c798 MK |
2535 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2536 | currently unknown. */ | |
911bc6ee | 2537 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2538 | return (name && (strcmp ("_sigreturn", name) == 0 |
2539 | || strcmp ("_sigacthandler", name) == 0 | |
2540 | || strcmp ("sigvechandler", name) == 0)); | |
2541 | } | |
d2a7c97a | 2542 | |
10458914 DJ |
2543 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2544 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2545 | |
3a1e71e3 | 2546 | static CORE_ADDR |
10458914 | 2547 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2548 | { |
63c0089f | 2549 | gdb_byte buf[4]; |
acd5c798 | 2550 | CORE_ADDR sp; |
3ce1502b | 2551 | |
10458914 | 2552 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 | 2553 | sp = extract_unsigned_integer (buf, 4); |
21d0e8a4 | 2554 | |
acd5c798 | 2555 | return read_memory_unsigned_integer (sp + 8, 4); |
8201327c MK |
2556 | } |
2557 | \f | |
3ce1502b | 2558 | |
8201327c | 2559 | /* Generic ELF. */ |
d2a7c97a | 2560 | |
8201327c MK |
2561 | void |
2562 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2563 | { | |
c4fc7f1b MK |
2564 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2565 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2566 | } |
3ce1502b | 2567 | |
8201327c | 2568 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2569 | |
8201327c MK |
2570 | void |
2571 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2572 | { | |
2573 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2574 | |
8201327c MK |
2575 | /* System V Release 4 uses ELF. */ |
2576 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2577 | |
dfe01d39 | 2578 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2579 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2580 | ||
911bc6ee | 2581 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2582 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2583 | tdep->sc_pc_offset = 36 + 14 * 4; |
2584 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2585 | |
8201327c | 2586 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2587 | } |
2588 | ||
8201327c | 2589 | /* DJGPP. */ |
3ce1502b | 2590 | |
3a1e71e3 | 2591 | static void |
8201327c | 2592 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2593 | { |
8201327c | 2594 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2595 | |
911bc6ee MK |
2596 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2597 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2598 | |
8201327c | 2599 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2600 | |
2601 | /* DJGPP does not support the SSE registers. */ | |
2602 | tdep->num_xmm_regs = 0; | |
2603 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS); | |
3d22076f EZ |
2604 | |
2605 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2606 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2607 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2608 | set_gdbarch_sdb_reg_to_regnum. */ | |
2609 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2610 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2611 | } |
8201327c | 2612 | \f |
2acceee2 | 2613 | |
38c968cf AC |
2614 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2615 | and "sse". */ | |
2616 | ||
2617 | static struct reggroup *i386_sse_reggroup; | |
2618 | static struct reggroup *i386_mmx_reggroup; | |
2619 | ||
2620 | static void | |
2621 | i386_init_reggroups (void) | |
2622 | { | |
2623 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2624 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2625 | } | |
2626 | ||
2627 | static void | |
2628 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2629 | { | |
2630 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2631 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2632 | reggroup_add (gdbarch, general_reggroup); | |
2633 | reggroup_add (gdbarch, float_reggroup); | |
2634 | reggroup_add (gdbarch, all_reggroup); | |
2635 | reggroup_add (gdbarch, save_reggroup); | |
2636 | reggroup_add (gdbarch, restore_reggroup); | |
2637 | reggroup_add (gdbarch, vector_reggroup); | |
2638 | reggroup_add (gdbarch, system_reggroup); | |
2639 | } | |
2640 | ||
2641 | int | |
2642 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2643 | struct reggroup *group) | |
2644 | { | |
5716833c MK |
2645 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2646 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2647 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2648 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2649 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2650 | |
38c968cf AC |
2651 | if (group == i386_mmx_reggroup) |
2652 | return mmx_regnum_p; | |
2653 | if (group == i386_sse_reggroup) | |
2654 | return sse_regnum_p; | |
2655 | if (group == vector_reggroup) | |
2656 | return (mmx_regnum_p || sse_regnum_p); | |
2657 | if (group == float_reggroup) | |
2658 | return fp_regnum_p; | |
2659 | if (group == general_reggroup) | |
2660 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2661 | |
38c968cf AC |
2662 | return default_register_reggroup_p (gdbarch, regnum, group); |
2663 | } | |
38c968cf | 2664 | \f |
acd5c798 | 2665 | |
f837910f MK |
2666 | /* Get the ARGIth function argument for the current function. */ |
2667 | ||
42c466d7 | 2668 | static CORE_ADDR |
143985b7 AF |
2669 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2670 | struct type *type) | |
2671 | { | |
f837910f MK |
2672 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
2673 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4); | |
143985b7 AF |
2674 | } |
2675 | ||
514f746b AR |
2676 | static void |
2677 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2678 | { | |
2679 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2680 | ||
2681 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2682 | adjust the PC in the regcache. */ | |
2683 | current_pc += 1; | |
2684 | regcache_write_pc (regcache, current_pc); | |
2685 | } | |
2686 | ||
2687 | ||
7ad10968 HZ |
2688 | #define PREFIX_REPZ 0x01 |
2689 | #define PREFIX_REPNZ 0x02 | |
2690 | #define PREFIX_LOCK 0x04 | |
2691 | #define PREFIX_DATA 0x08 | |
2692 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2693 | |
7ad10968 HZ |
2694 | /* operand size */ |
2695 | enum | |
2696 | { | |
2697 | OT_BYTE = 0, | |
2698 | OT_WORD, | |
2699 | OT_LONG, | |
2700 | }; | |
473f17b0 | 2701 | |
7ad10968 HZ |
2702 | /* i386 arith/logic operations */ |
2703 | enum | |
2704 | { | |
2705 | OP_ADDL, | |
2706 | OP_ORL, | |
2707 | OP_ADCL, | |
2708 | OP_SBBL, | |
2709 | OP_ANDL, | |
2710 | OP_SUBL, | |
2711 | OP_XORL, | |
2712 | OP_CMPL, | |
2713 | }; | |
5716833c | 2714 | |
7ad10968 HZ |
2715 | struct i386_record_s |
2716 | { | |
2717 | struct regcache *regcache; | |
2718 | CORE_ADDR addr; | |
2719 | int aflag; | |
2720 | int dflag; | |
2721 | int override; | |
2722 | uint8_t modrm; | |
2723 | uint8_t mod, reg, rm; | |
2724 | int ot; | |
2725 | }; | |
5716833c | 2726 | |
7ad10968 HZ |
2727 | /* Parse "modrm" part in current memory address that irp->addr point to |
2728 | Return -1 if something wrong. */ | |
5716833c | 2729 | |
7ad10968 HZ |
2730 | static int |
2731 | i386_record_modrm (struct i386_record_s *irp) | |
2732 | { | |
2733 | if (target_read_memory (irp->addr, &irp->modrm, 1)) | |
2734 | { | |
2735 | if (record_debug) | |
2736 | printf_unfiltered (_("Process record: error reading memory at " | |
2737 | "addr 0x%s len = 1.\n"), | |
2738 | paddr_nz (irp->addr)); | |
2739 | return -1; | |
2740 | } | |
2741 | irp->addr++; | |
2742 | irp->mod = (irp->modrm >> 6) & 3; | |
2743 | irp->reg = (irp->modrm >> 3) & 7; | |
2744 | irp->rm = irp->modrm & 7; | |
5716833c | 2745 | |
7ad10968 HZ |
2746 | return 0; |
2747 | } | |
d2a7c97a | 2748 | |
7ad10968 HZ |
2749 | /* Get the memory address that current instruction write to and set it to |
2750 | the argument "addr". | |
2751 | Return -1 if something wrong. */ | |
8201327c | 2752 | |
7ad10968 HZ |
2753 | static int |
2754 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr) | |
2755 | { | |
2756 | uint8_t tmpu8; | |
2757 | uint16_t tmpu16; | |
2758 | uint32_t tmpu32; | |
21d0e8a4 | 2759 | |
7ad10968 HZ |
2760 | *addr = 0; |
2761 | if (irp->aflag) | |
2762 | { | |
2763 | /* 32 bits */ | |
2764 | int havesib = 0; | |
2765 | uint8_t scale = 0; | |
2766 | uint8_t index = 0; | |
2767 | uint8_t base = irp->rm; | |
896fb97d | 2768 | |
7ad10968 HZ |
2769 | if (base == 4) |
2770 | { | |
2771 | havesib = 1; | |
2772 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2773 | { | |
2774 | if (record_debug) | |
2775 | printf_unfiltered (_("Process record: error reading memory " | |
2776 | "at addr 0x%s len = 1.\n"), | |
2777 | paddr_nz (irp->addr)); | |
2778 | return -1; | |
2779 | } | |
2780 | irp->addr++; | |
2781 | scale = (tmpu8 >> 6) & 3; | |
2782 | index = ((tmpu8 >> 3) & 7); | |
2783 | base = (tmpu8 & 7); | |
2784 | } | |
21d0e8a4 | 2785 | |
7ad10968 HZ |
2786 | switch (irp->mod) |
2787 | { | |
2788 | case 0: | |
2789 | if ((base & 7) == 5) | |
2790 | { | |
2791 | base = 0xff; | |
2792 | if (target_read_memory (irp->addr, (gdb_byte *) addr, 4)) | |
2793 | { | |
2794 | if (record_debug) | |
2795 | printf_unfiltered (_("Process record: error reading " | |
2796 | "memory at addr 0x%s len = 4.\n"), | |
2797 | paddr_nz (irp->addr)); | |
2798 | return -1; | |
2799 | } | |
2800 | irp->addr += 4; | |
2801 | } | |
2802 | else | |
2803 | { | |
2804 | *addr = 0; | |
2805 | } | |
2806 | break; | |
2807 | case 1: | |
2808 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2809 | { | |
2810 | if (record_debug) | |
2811 | printf_unfiltered (_("Process record: error reading memory " | |
2812 | "at addr 0x%s len = 1.\n"), | |
2813 | paddr_nz (irp->addr)); | |
2814 | return -1; | |
2815 | } | |
2816 | irp->addr++; | |
2817 | *addr = (int8_t) tmpu8; | |
2818 | break; | |
2819 | case 2: | |
2820 | if (target_read_memory (irp->addr, (gdb_byte *) addr, 4)) | |
2821 | { | |
2822 | if (record_debug) | |
2823 | printf_unfiltered (_("Process record: error reading memory " | |
2824 | "at addr 0x%s len = 4.\n"), | |
2825 | paddr_nz (irp->addr)); | |
2826 | return -1; | |
2827 | } | |
2828 | irp->addr += 4; | |
2829 | break; | |
2830 | } | |
356a6b3e | 2831 | |
7ad10968 HZ |
2832 | if (base != 0xff) |
2833 | { | |
2834 | regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32); | |
2835 | *addr += tmpu32; | |
2836 | } | |
c4fc7f1b | 2837 | |
7ad10968 HZ |
2838 | /* XXX: index == 4 is always invalid */ |
2839 | if (havesib && (index != 4 || scale != 0)) | |
2840 | { | |
2841 | regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32); | |
2842 | *addr += tmpu32 << scale; | |
2843 | } | |
2844 | } | |
2845 | else | |
2846 | { | |
2847 | /* 16 bits */ | |
2848 | switch (irp->mod) | |
2849 | { | |
2850 | case 0: | |
2851 | if (irp->rm == 6) | |
2852 | { | |
2853 | if (target_read_memory | |
2854 | (irp->addr, (gdb_byte *) & tmpu16, 2)) | |
2855 | { | |
2856 | if (record_debug) | |
2857 | printf_unfiltered (_("Process record: error reading " | |
2858 | "memory at addr 0x%s len = 2.\n"), | |
2859 | paddr_nz (irp->addr)); | |
2860 | return -1; | |
2861 | } | |
2862 | irp->addr += 2; | |
2863 | *addr = (int16_t) tmpu16; | |
2864 | irp->rm = 0; | |
2865 | goto no_rm; | |
2866 | } | |
2867 | else | |
2868 | { | |
2869 | *addr = 0; | |
2870 | } | |
2871 | break; | |
2872 | case 1: | |
2873 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2874 | { | |
2875 | if (record_debug) | |
2876 | printf_unfiltered (_("Process record: error reading memory " | |
2877 | "at addr 0x%s len = 1.\n"), | |
2878 | paddr_nz (irp->addr)); | |
2879 | return -1; | |
2880 | } | |
2881 | irp->addr++; | |
2882 | *addr = (int8_t) tmpu8; | |
2883 | break; | |
2884 | case 2: | |
2885 | if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2)) | |
2886 | { | |
2887 | if (record_debug) | |
2888 | printf_unfiltered (_("Process record: error reading memory " | |
2889 | "at addr 0x%s len = 2.\n"), | |
2890 | paddr_nz (irp->addr)); | |
2891 | return -1; | |
2892 | } | |
2893 | irp->addr += 2; | |
2894 | *addr = (int16_t) tmpu16; | |
2895 | break; | |
2896 | } | |
c4fc7f1b | 2897 | |
7ad10968 HZ |
2898 | switch (irp->rm) |
2899 | { | |
2900 | case 0: | |
2901 | regcache_raw_read (irp->regcache, I386_EBX_REGNUM, | |
2902 | (gdb_byte *) & tmpu32); | |
2903 | *addr += tmpu32; | |
2904 | regcache_raw_read (irp->regcache, I386_ESI_REGNUM, | |
2905 | (gdb_byte *) & tmpu32); | |
2906 | *addr += tmpu32; | |
2907 | break; | |
2908 | case 1: | |
2909 | regcache_raw_read (irp->regcache, I386_EBX_REGNUM, | |
2910 | (gdb_byte *) & tmpu32); | |
2911 | *addr += tmpu32; | |
2912 | regcache_raw_read (irp->regcache, I386_EDI_REGNUM, | |
2913 | (gdb_byte *) & tmpu32); | |
2914 | *addr += tmpu32; | |
2915 | break; | |
2916 | case 2: | |
2917 | regcache_raw_read (irp->regcache, I386_EBP_REGNUM, | |
2918 | (gdb_byte *) & tmpu32); | |
2919 | *addr += tmpu32; | |
2920 | regcache_raw_read (irp->regcache, I386_ESI_REGNUM, | |
2921 | (gdb_byte *) & tmpu32); | |
2922 | *addr += tmpu32; | |
2923 | break; | |
2924 | case 3: | |
2925 | regcache_raw_read (irp->regcache, I386_EBP_REGNUM, | |
2926 | (gdb_byte *) & tmpu32); | |
2927 | *addr += tmpu32; | |
2928 | regcache_raw_read (irp->regcache, I386_EDI_REGNUM, | |
2929 | (gdb_byte *) & tmpu32); | |
2930 | *addr += tmpu32; | |
2931 | break; | |
2932 | case 4: | |
2933 | regcache_raw_read (irp->regcache, I386_ESI_REGNUM, | |
2934 | (gdb_byte *) & tmpu32); | |
2935 | *addr += tmpu32; | |
2936 | break; | |
2937 | case 5: | |
2938 | regcache_raw_read (irp->regcache, I386_EDI_REGNUM, | |
2939 | (gdb_byte *) & tmpu32); | |
2940 | *addr += tmpu32; | |
2941 | break; | |
2942 | case 6: | |
2943 | regcache_raw_read (irp->regcache, I386_EBP_REGNUM, | |
2944 | (gdb_byte *) & tmpu32); | |
2945 | *addr += tmpu32; | |
2946 | break; | |
2947 | case 7: | |
2948 | regcache_raw_read (irp->regcache, I386_EBX_REGNUM, | |
2949 | (gdb_byte *) & tmpu32); | |
2950 | *addr += tmpu32; | |
2951 | break; | |
2952 | } | |
2953 | *addr &= 0xffff; | |
2954 | } | |
c4fc7f1b | 2955 | |
7ad10968 HZ |
2956 | no_rm: |
2957 | return 0; | |
2958 | } | |
c4fc7f1b | 2959 | |
7ad10968 HZ |
2960 | /* Record the value of the memory that willbe changed in current instruction |
2961 | to "record_arch_list". | |
2962 | Return -1 if something wrong. */ | |
356a6b3e | 2963 | |
7ad10968 HZ |
2964 | static int |
2965 | i386_record_lea_modrm (struct i386_record_s *irp) | |
2966 | { | |
2967 | uint32_t addr; | |
356a6b3e | 2968 | |
7ad10968 HZ |
2969 | if (irp->override) |
2970 | { | |
2971 | if (record_debug) | |
2972 | printf_unfiltered (_("Process record ignores the memory change " | |
2973 | "of instruction at address 0x%s because it " | |
2974 | "can't get the value of the segment register.\n"), | |
2975 | paddr_nz (irp->addr)); | |
2976 | return 0; | |
2977 | } | |
61113f8b | 2978 | |
7ad10968 HZ |
2979 | if (i386_record_lea_modrm_addr (irp, &addr)) |
2980 | return -1; | |
96297dab | 2981 | |
7ad10968 HZ |
2982 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
2983 | return -1; | |
a62cc96e | 2984 | |
7ad10968 HZ |
2985 | return 0; |
2986 | } | |
b6197528 | 2987 | |
7ad10968 HZ |
2988 | /* Parse the current instruction and record the values of the registers and |
2989 | memory that will be changed in current instruction to "record_arch_list". | |
2990 | Return -1 if something wrong. */ | |
8201327c | 2991 | |
a6b808b4 | 2992 | int |
7ad10968 HZ |
2993 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
2994 | CORE_ADDR addr) | |
2995 | { | |
2996 | int prefixes = 0; | |
2997 | uint8_t tmpu8; | |
2998 | uint16_t tmpu16; | |
2999 | uint32_t tmpu32; | |
3000 | uint32_t opcode; | |
3001 | struct i386_record_s ir; | |
3002 | ||
8408d274 | 3003 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 HZ |
3004 | ir.regcache = regcache; |
3005 | ir.addr = addr; | |
3006 | ir.aflag = 1; | |
3007 | ir.dflag = 1; | |
3008 | ||
3009 | if (record_debug > 1) | |
3010 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
3011 | "addr = 0x%s\n", | |
3012 | paddr_nz (ir.addr)); | |
3013 | ||
3014 | /* prefixes */ | |
3015 | while (1) | |
3016 | { | |
3017 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3018 | { | |
3019 | if (record_debug) | |
3020 | printf_unfiltered (_("Process record: error reading memory at " | |
3021 | "addr 0x%s len = 1.\n"), | |
3022 | paddr_nz (ir.addr)); | |
3023 | return -1; | |
3024 | } | |
3025 | ir.addr++; | |
3026 | switch (tmpu8) | |
3027 | { | |
3028 | case 0xf3: | |
3029 | prefixes |= PREFIX_REPZ; | |
3030 | break; | |
3031 | case 0xf2: | |
3032 | prefixes |= PREFIX_REPNZ; | |
3033 | break; | |
3034 | case 0xf0: | |
3035 | prefixes |= PREFIX_LOCK; | |
3036 | break; | |
3037 | case 0x2e: | |
3038 | ir.override = I386_CS_REGNUM; | |
3039 | break; | |
3040 | case 0x36: | |
3041 | ir.override = I386_SS_REGNUM; | |
3042 | break; | |
3043 | case 0x3e: | |
3044 | ir.override = I386_DS_REGNUM; | |
3045 | break; | |
3046 | case 0x26: | |
3047 | ir.override = I386_ES_REGNUM; | |
3048 | break; | |
3049 | case 0x64: | |
3050 | ir.override = I386_FS_REGNUM; | |
3051 | break; | |
3052 | case 0x65: | |
3053 | ir.override = I386_GS_REGNUM; | |
3054 | break; | |
3055 | case 0x66: | |
3056 | prefixes |= PREFIX_DATA; | |
3057 | break; | |
3058 | case 0x67: | |
3059 | prefixes |= PREFIX_ADDR; | |
3060 | break; | |
3061 | default: | |
3062 | goto out_prefixes; | |
3063 | break; | |
3064 | } | |
3065 | } | |
3066 | out_prefixes: | |
3067 | if (prefixes & PREFIX_DATA) | |
3068 | ir.dflag ^= 1; | |
3069 | if (prefixes & PREFIX_ADDR) | |
3070 | ir.aflag ^= 1; | |
3071 | ||
3072 | /* now check op code */ | |
3073 | opcode = (uint32_t) tmpu8; | |
3074 | reswitch: | |
3075 | switch (opcode) | |
3076 | { | |
3077 | case 0x0f: | |
3078 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3079 | { | |
3080 | if (record_debug) | |
3081 | printf_unfiltered (_("Process record: error reading memory at " | |
3082 | "addr 0x%s len = 1.\n"), | |
3083 | paddr_nz (ir.addr)); | |
3084 | return -1; | |
3085 | } | |
3086 | ir.addr++; | |
3087 | opcode = (uint16_t) tmpu8 | 0x0f00; | |
3088 | goto reswitch; | |
3089 | break; | |
93924b6b | 3090 | |
7ad10968 HZ |
3091 | /* arith & logic */ |
3092 | case 0x00: | |
3093 | case 0x01: | |
3094 | case 0x02: | |
3095 | case 0x03: | |
3096 | case 0x04: | |
3097 | case 0x05: | |
3098 | case 0x08: | |
3099 | case 0x09: | |
3100 | case 0x0a: | |
3101 | case 0x0b: | |
3102 | case 0x0c: | |
3103 | case 0x0d: | |
3104 | case 0x10: | |
3105 | case 0x11: | |
3106 | case 0x12: | |
3107 | case 0x13: | |
3108 | case 0x14: | |
3109 | case 0x15: | |
3110 | case 0x18: | |
3111 | case 0x19: | |
3112 | case 0x1a: | |
3113 | case 0x1b: | |
3114 | case 0x1c: | |
3115 | case 0x1d: | |
3116 | case 0x20: | |
3117 | case 0x21: | |
3118 | case 0x22: | |
3119 | case 0x23: | |
3120 | case 0x24: | |
3121 | case 0x25: | |
3122 | case 0x28: | |
3123 | case 0x29: | |
3124 | case 0x2a: | |
3125 | case 0x2b: | |
3126 | case 0x2c: | |
3127 | case 0x2d: | |
3128 | case 0x30: | |
3129 | case 0x31: | |
3130 | case 0x32: | |
3131 | case 0x33: | |
3132 | case 0x34: | |
3133 | case 0x35: | |
3134 | case 0x38: | |
3135 | case 0x39: | |
3136 | case 0x3a: | |
3137 | case 0x3b: | |
3138 | case 0x3c: | |
3139 | case 0x3d: | |
3140 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3141 | { | |
3142 | if ((opcode & 1) == 0) | |
3143 | ir.ot = OT_BYTE; | |
3144 | else | |
3145 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3146 | |
7ad10968 HZ |
3147 | switch ((opcode >> 1) & 3) |
3148 | { | |
3149 | /* OP Ev, Gv */ | |
3150 | case 0: | |
3151 | if (i386_record_modrm (&ir)) | |
3152 | return -1; | |
3153 | if (ir.mod != 3) | |
3154 | { | |
3155 | if (i386_record_lea_modrm (&ir)) | |
3156 | return -1; | |
3157 | } | |
3158 | else | |
3159 | { | |
3160 | if (ir.ot == OT_BYTE) | |
3161 | ir.rm &= 0x3; | |
3162 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3163 | return -1; | |
3164 | } | |
3165 | break; | |
3166 | /* OP Gv, Ev */ | |
3167 | case 1: | |
3168 | if (i386_record_modrm (&ir)) | |
3169 | return -1; | |
3170 | if (ir.ot == OT_BYTE) | |
3171 | ir.reg &= 0x3; | |
3172 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3173 | return -1; | |
3174 | break; | |
3175 | /* OP A, Iv */ | |
3176 | case 2: | |
3177 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3178 | return -1; | |
3179 | break; | |
3180 | } | |
3181 | } | |
3182 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3183 | return -1; | |
3184 | break; | |
42fdc8df | 3185 | |
7ad10968 HZ |
3186 | /* GRP1 */ |
3187 | case 0x80: | |
3188 | case 0x81: | |
3189 | case 0x82: | |
3190 | case 0x83: | |
3191 | if (i386_record_modrm (&ir)) | |
3192 | return -1; | |
8201327c | 3193 | |
7ad10968 HZ |
3194 | if (ir.reg != OP_CMPL) |
3195 | { | |
3196 | if ((opcode & 1) == 0) | |
3197 | ir.ot = OT_BYTE; | |
3198 | else | |
3199 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3200 | |
7ad10968 HZ |
3201 | if (ir.mod != 3) |
3202 | { | |
3203 | if (i386_record_lea_modrm (&ir)) | |
3204 | return -1; | |
3205 | } | |
3206 | else | |
3207 | { | |
3208 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3209 | return -1; | |
3210 | } | |
3211 | } | |
3212 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3213 | return -1; | |
3214 | break; | |
5e3397bb | 3215 | |
7ad10968 HZ |
3216 | /* inv */ |
3217 | case 0x40: | |
3218 | case 0x41: | |
3219 | case 0x42: | |
3220 | case 0x43: | |
3221 | case 0x44: | |
3222 | case 0x45: | |
3223 | case 0x46: | |
3224 | case 0x47: | |
3225 | /* dec */ | |
3226 | case 0x48: | |
3227 | case 0x49: | |
3228 | case 0x4a: | |
3229 | case 0x4b: | |
3230 | case 0x4c: | |
3231 | case 0x4d: | |
3232 | case 0x4e: | |
3233 | case 0x4f: | |
3234 | if (record_arch_list_add_reg (ir.regcache, opcode & 7)) | |
3235 | return -1; | |
3236 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3237 | return -1; | |
3238 | break; | |
acd5c798 | 3239 | |
7ad10968 HZ |
3240 | /* GRP3 */ |
3241 | case 0xf6: | |
3242 | case 0xf7: | |
3243 | if ((opcode & 1) == 0) | |
3244 | ir.ot = OT_BYTE; | |
3245 | else | |
3246 | ir.ot = ir.dflag + OT_WORD; | |
3247 | if (i386_record_modrm (&ir)) | |
3248 | return -1; | |
acd5c798 | 3249 | |
7ad10968 HZ |
3250 | switch (ir.reg) |
3251 | { | |
3252 | /* test */ | |
3253 | case 0: | |
3254 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3255 | return -1; | |
3256 | break; | |
3257 | /* not */ | |
3258 | case 2: | |
3259 | if (ir.mod != 3) | |
3260 | { | |
3261 | if (i386_record_lea_modrm (&ir)) | |
3262 | return -1; | |
3263 | } | |
3264 | else | |
3265 | { | |
3266 | if (ir.ot == OT_BYTE) | |
3267 | ir.rm &= 0x3; | |
3268 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3269 | return -1; | |
3270 | } | |
3271 | break; | |
3272 | /* neg */ | |
3273 | case 3: | |
3274 | if (ir.mod != 3) | |
3275 | { | |
3276 | if (i386_record_lea_modrm (&ir)) | |
3277 | return -1; | |
3278 | } | |
3279 | else | |
3280 | { | |
3281 | if (ir.ot == OT_BYTE) | |
3282 | ir.rm &= 0x3; | |
3283 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3284 | return -1; | |
3285 | } | |
3286 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3287 | return -1; | |
3288 | break; | |
3289 | /* mul */ | |
3290 | case 4: | |
3291 | /* imul */ | |
3292 | case 5: | |
3293 | /* div */ | |
3294 | case 6: | |
3295 | /* idiv */ | |
3296 | case 7: | |
3297 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3298 | return -1; | |
3299 | if (ir.ot != OT_BYTE) | |
3300 | { | |
3301 | if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) | |
3302 | return -1; | |
3303 | } | |
3304 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3305 | return -1; | |
3306 | break; | |
3307 | default: | |
3308 | ir.addr -= 2; | |
3309 | opcode = opcode << 8 | ir.modrm; | |
3310 | goto no_support; | |
3311 | break; | |
3312 | } | |
3313 | break; | |
3314 | ||
3315 | /* GRP4 */ | |
3316 | case 0xfe: | |
3317 | /* GRP5 */ | |
3318 | case 0xff: | |
3319 | if ((opcode & 1) == 0) | |
3320 | ir.ot = OT_BYTE; | |
3321 | else | |
3322 | ir.ot = ir.dflag + OT_WORD; | |
3323 | if (i386_record_modrm (&ir)) | |
3324 | return -1; | |
3325 | if (ir.reg >= 2 && opcode == 0xfe) | |
3326 | { | |
3327 | ir.addr -= 2; | |
3328 | opcode = opcode << 8 | ir.modrm; | |
3329 | goto no_support; | |
3330 | } | |
3331 | ||
3332 | switch (ir.reg) | |
3333 | { | |
3334 | /* inc */ | |
3335 | case 0: | |
3336 | /* dec */ | |
3337 | case 1: | |
3338 | if (ir.mod != 3) | |
3339 | { | |
3340 | if (i386_record_lea_modrm (&ir)) | |
3341 | return -1; | |
3342 | } | |
3343 | else | |
3344 | { | |
3345 | if (ir.ot == OT_BYTE) | |
3346 | ir.rm &= 0x3; | |
3347 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3348 | return -1; | |
3349 | } | |
3350 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3351 | return -1; | |
3352 | break; | |
3353 | /* call */ | |
3354 | case 2: | |
3355 | /* push */ | |
3356 | case 6: | |
3357 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3358 | return -1; | |
3359 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
3360 | (gdb_byte *) & tmpu32); | |
3361 | if (record_arch_list_add_mem | |
3362 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) | |
3363 | return -1; | |
3364 | break; | |
3365 | /* lcall */ | |
3366 | case 3: | |
3367 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3368 | return -1; | |
3369 | if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) | |
3370 | return -1; | |
3371 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
3372 | (gdb_byte *) & tmpu32); | |
3373 | if (record_arch_list_add_mem | |
3374 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2)))) | |
3375 | return -1; | |
3376 | break; | |
3377 | /* jmp */ | |
3378 | case 4: | |
3379 | /* ljmp */ | |
3380 | case 5: | |
3381 | break; | |
3382 | default: | |
3383 | ir.addr -= 2; | |
3384 | opcode = opcode << 8 | ir.modrm; | |
3385 | goto no_support; | |
3386 | break; | |
3387 | } | |
3388 | break; | |
3389 | ||
3390 | /* test */ | |
3391 | case 0x84: | |
3392 | case 0x85: | |
3393 | case 0xa8: | |
3394 | case 0xa9: | |
3395 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3396 | return -1; | |
3397 | break; | |
3398 | ||
3399 | /* CWDE/CBW */ | |
3400 | case 0x98: | |
3401 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3402 | return -1; | |
3403 | break; | |
3404 | ||
3405 | /* CDQ/CWD */ | |
3406 | case 0x99: | |
3407 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3408 | return -1; | |
3409 | if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) | |
3410 | return -1; | |
3411 | break; | |
3412 | ||
3413 | /* imul */ | |
3414 | case 0x0faf: | |
3415 | case 0x69: | |
3416 | case 0x6b: | |
3417 | ir.ot = ir.dflag + OT_WORD; | |
3418 | if (i386_record_modrm (&ir)) | |
3419 | return -1; | |
3420 | if (ir.ot == OT_BYTE) | |
3421 | ir.reg &= 0x3; | |
3422 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3423 | return -1; | |
3424 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3425 | return -1; | |
3426 | break; | |
3427 | ||
3428 | /* xadd */ | |
3429 | case 0x0fc0: | |
3430 | case 0x0fc1: | |
3431 | if ((opcode & 1) == 0) | |
3432 | ir.ot = OT_BYTE; | |
3433 | else | |
3434 | ir.ot = ir.dflag + OT_WORD; | |
3435 | if (i386_record_modrm (&ir)) | |
3436 | return -1; | |
3437 | if (ir.mod == 3) | |
3438 | { | |
3439 | if (ir.ot == OT_BYTE) | |
3440 | ir.reg &= 0x3; | |
3441 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3442 | return -1; | |
3443 | if (ir.ot == OT_BYTE) | |
3444 | ir.rm &= 0x3; | |
3445 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3446 | return -1; | |
3447 | } | |
3448 | else | |
3449 | { | |
3450 | if (i386_record_lea_modrm (&ir)) | |
3451 | return -1; | |
3452 | if (ir.ot == OT_BYTE) | |
3453 | ir.reg &= 0x3; | |
3454 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3455 | return -1; | |
3456 | } | |
3457 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3458 | return -1; | |
3459 | break; | |
3460 | ||
3461 | /* cmpxchg */ | |
3462 | case 0x0fb0: | |
3463 | case 0x0fb1: | |
3464 | if ((opcode & 1) == 0) | |
3465 | ir.ot = OT_BYTE; | |
3466 | else | |
3467 | ir.ot = ir.dflag + OT_WORD; | |
3468 | if (i386_record_modrm (&ir)) | |
3469 | return -1; | |
3470 | if (ir.mod == 3) | |
3471 | { | |
3472 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3473 | return -1; | |
3474 | if (ir.ot == OT_BYTE) | |
3475 | ir.reg &= 0x3; | |
3476 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3477 | return -1; | |
3478 | } | |
3479 | else | |
3480 | { | |
3481 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3482 | return -1; | |
3483 | if (i386_record_lea_modrm (&ir)) | |
3484 | return -1; | |
3485 | } | |
3486 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3487 | return -1; | |
3488 | break; | |
3489 | ||
3490 | /* cmpxchg8b */ | |
3491 | case 0x0fc7: | |
3492 | if (i386_record_modrm (&ir)) | |
3493 | return -1; | |
3494 | if (ir.mod == 3) | |
3495 | { | |
3496 | ir.addr -= 2; | |
3497 | opcode = opcode << 8 | ir.modrm; | |
3498 | goto no_support; | |
3499 | } | |
3500 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3501 | return -1; | |
3502 | if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) | |
3503 | return -1; | |
3504 | if (i386_record_lea_modrm (&ir)) | |
3505 | return -1; | |
3506 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3507 | return -1; | |
3508 | break; | |
3509 | ||
3510 | /* push */ | |
3511 | case 0x50: | |
3512 | case 0x51: | |
3513 | case 0x52: | |
3514 | case 0x53: | |
3515 | case 0x54: | |
3516 | case 0x55: | |
3517 | case 0x56: | |
3518 | case 0x57: | |
3519 | case 0x68: | |
3520 | case 0x6a: | |
3521 | /* push es */ | |
3522 | case 0x06: | |
3523 | /* push cs */ | |
3524 | case 0x0e: | |
3525 | /* push ss */ | |
3526 | case 0x16: | |
3527 | /* push ds */ | |
3528 | case 0x1e: | |
3529 | /* push fs */ | |
3530 | case 0x0fa0: | |
3531 | /* push gs */ | |
3532 | case 0x0fa8: | |
3533 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3534 | return -1; | |
3535 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
3536 | (gdb_byte *) & tmpu32); | |
3537 | if (record_arch_list_add_mem | |
3538 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) | |
3539 | return -1; | |
3540 | break; | |
3541 | ||
3542 | /* pop */ | |
3543 | case 0x58: | |
3544 | case 0x59: | |
3545 | case 0x5a: | |
3546 | case 0x5b: | |
3547 | case 0x5c: | |
3548 | case 0x5d: | |
3549 | case 0x5e: | |
3550 | case 0x5f: | |
3551 | ir.ot = ir.dflag + OT_WORD; | |
3552 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3553 | return -1; | |
3554 | if (ir.ot == OT_BYTE) | |
3555 | opcode &= 0x3; | |
3556 | if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) | |
3557 | return -1; | |
3558 | break; | |
3559 | ||
3560 | /* pusha */ | |
3561 | case 0x60: | |
3562 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3563 | return -1; | |
3564 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
3565 | (gdb_byte *) & tmpu32); | |
3566 | if (record_arch_list_add_mem | |
3567 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4)))) | |
3568 | return -1; | |
3569 | break; | |
3570 | ||
3571 | /* popa */ | |
3572 | case 0x61: | |
3573 | for (tmpu8 = I386_EAX_REGNUM; tmpu8 <= I386_EDI_REGNUM; tmpu8++) | |
3574 | { | |
3575 | if (record_arch_list_add_reg (ir.regcache, tmpu8)) | |
3576 | return -1; | |
3577 | } | |
3578 | break; | |
3579 | ||
3580 | /* pop */ | |
3581 | case 0x8f: | |
3582 | ir.ot = ir.dflag + OT_WORD; | |
3583 | if (i386_record_modrm (&ir)) | |
3584 | return -1; | |
3585 | if (ir.mod == 3) | |
3586 | { | |
3587 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3588 | return -1; | |
3589 | } | |
3590 | else | |
3591 | { | |
3592 | if (i386_record_lea_modrm (&ir)) | |
3593 | return -1; | |
3594 | } | |
3595 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3596 | return -1; | |
3597 | break; | |
3598 | ||
3599 | /* enter */ | |
3600 | case 0xc8: | |
3601 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3602 | return -1; | |
3603 | if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM)) | |
3604 | return -1; | |
3605 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
3606 | (gdb_byte *) & tmpu32); | |
3607 | if (record_arch_list_add_mem | |
3608 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) | |
3609 | return -1; | |
3610 | break; | |
3611 | ||
3612 | /* leave */ | |
3613 | case 0xc9: | |
3614 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3615 | return -1; | |
3616 | if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM)) | |
3617 | return -1; | |
3618 | break; | |
3619 | ||
3620 | /* pop es */ | |
3621 | case 0x07: | |
3622 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3623 | return -1; | |
3624 | if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM)) | |
3625 | return -1; | |
3626 | break; | |
3627 | ||
3628 | /* pop ss */ | |
3629 | case 0x17: | |
3630 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3631 | return -1; | |
3632 | if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM)) | |
3633 | return -1; | |
3634 | break; | |
3635 | ||
3636 | /* pop ds */ | |
3637 | case 0x1f: | |
3638 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3639 | return -1; | |
3640 | if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM)) | |
3641 | return -1; | |
3642 | break; | |
3643 | ||
3644 | /* pop fs */ | |
3645 | case 0x0fa1: | |
3646 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3647 | return -1; | |
3648 | if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM)) | |
3649 | return -1; | |
3650 | break; | |
3651 | ||
3652 | /* pop gs */ | |
3653 | case 0x0fa9: | |
3654 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
3655 | return -1; | |
3656 | if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM)) | |
3657 | return -1; | |
3658 | break; | |
3659 | ||
3660 | /* mov */ | |
3661 | case 0x88: | |
3662 | case 0x89: | |
3663 | case 0xc6: | |
3664 | case 0xc7: | |
3665 | if ((opcode & 1) == 0) | |
3666 | ir.ot = OT_BYTE; | |
3667 | else | |
3668 | ir.ot = ir.dflag + OT_WORD; | |
3669 | ||
3670 | if (i386_record_modrm (&ir)) | |
3671 | return -1; | |
3672 | ||
3673 | if (ir.mod != 3) | |
3674 | { | |
3675 | if (i386_record_lea_modrm (&ir)) | |
3676 | return -1; | |
3677 | } | |
3678 | else | |
3679 | { | |
3680 | if (ir.ot == OT_BYTE) | |
3681 | ir.rm &= 0x3; | |
3682 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3683 | return -1; | |
3684 | } | |
3685 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3686 | return -1; | |
3687 | break; | |
3688 | /* mov */ | |
3689 | case 0x8a: | |
3690 | case 0x8b: | |
3691 | if ((opcode & 1) == 0) | |
3692 | ir.ot = OT_BYTE; | |
3693 | else | |
3694 | ir.ot = ir.dflag + OT_WORD; | |
3695 | ||
3696 | if (i386_record_modrm (&ir)) | |
3697 | return -1; | |
3698 | ||
3699 | if (ir.ot == OT_BYTE) | |
3700 | ir.reg &= 0x3; | |
3701 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3702 | return -1; | |
3703 | ||
3704 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3705 | return -1; | |
3706 | break; | |
3707 | ||
3708 | /* mov seg */ | |
3709 | case 0x8e: | |
3710 | if (i386_record_modrm (&ir)) | |
3711 | return -1; | |
3712 | ||
3713 | switch (ir.reg) | |
3714 | { | |
3715 | case 0: | |
3716 | tmpu8 = I386_ES_REGNUM; | |
3717 | break; | |
3718 | case 2: | |
3719 | tmpu8 = I386_SS_REGNUM; | |
3720 | break; | |
3721 | case 3: | |
3722 | tmpu8 = I386_DS_REGNUM; | |
3723 | break; | |
3724 | case 4: | |
3725 | tmpu8 = I386_FS_REGNUM; | |
3726 | break; | |
3727 | case 5: | |
3728 | tmpu8 = I386_GS_REGNUM; | |
3729 | break; | |
3730 | default: | |
3731 | ir.addr -= 2; | |
3732 | opcode = opcode << 8 | ir.modrm; | |
3733 | goto no_support; | |
3734 | break; | |
3735 | } | |
3736 | if (record_arch_list_add_reg (ir.regcache, tmpu8)) | |
3737 | return -1; | |
3738 | ||
3739 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3740 | return -1; | |
3741 | break; | |
3742 | ||
3743 | /* mov seg */ | |
3744 | case 0x8c: | |
3745 | if (i386_record_modrm (&ir)) | |
3746 | return -1; | |
3747 | if (ir.reg > 5) | |
3748 | { | |
3749 | ir.addr -= 2; | |
3750 | opcode = opcode << 8 | ir.modrm; | |
3751 | goto no_support; | |
3752 | } | |
3753 | ||
3754 | if (ir.mod == 3) | |
3755 | { | |
3756 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3757 | return -1; | |
3758 | } | |
3759 | else | |
3760 | { | |
3761 | ir.ot = OT_WORD; | |
3762 | if (i386_record_lea_modrm (&ir)) | |
3763 | return -1; | |
3764 | } | |
3765 | ||
3766 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
3767 | return -1; | |
3768 | break; | |
3769 | ||
3770 | /* movzbS */ | |
3771 | case 0x0fb6: | |
3772 | /* movzwS */ | |
3773 | case 0x0fb7: | |
3774 | /* movsbS */ | |
3775 | case 0x0fbe: | |
3776 | /* movswS */ | |
3777 | case 0x0fbf: | |
3778 | if (i386_record_modrm (&ir)) | |
3779 | return -1; | |
3780 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3781 | return -1; | |
3782 | break; | |
3783 | ||
3784 | /* lea */ | |
3785 | case 0x8d: | |
3786 | if (i386_record_modrm (&ir)) | |
3787 | return -1; | |
3788 | if (ir.mod == 3) | |
3789 | { | |
3790 | ir.addr -= 2; | |
3791 | opcode = opcode << 8 | ir.modrm; | |
3792 | goto no_support; | |
3793 | } | |
3794 | ||
3795 | ir.ot = ir.dflag; | |
3796 | if (ir.ot == OT_BYTE) | |
3797 | ir.reg &= 0x3; | |
3798 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3799 | return -1; | |
3800 | break; | |
3801 | ||
3802 | /* mov EAX */ | |
3803 | case 0xa0: | |
3804 | case 0xa1: | |
3805 | /* xlat */ | |
3806 | case 0xd7: | |
3807 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3808 | return -1; | |
3809 | break; | |
3810 | ||
3811 | /* mov EAX */ | |
3812 | case 0xa2: | |
3813 | case 0xa3: | |
3814 | { | |
3815 | uint32_t addr; | |
3816 | ||
3817 | if (ir.override) | |
3818 | { | |
3819 | if (record_debug) | |
3820 | printf_unfiltered (_("Process record ignores the memory change " | |
3821 | "of instruction at address 0x%s because " | |
3822 | "it can't get the value of the segment " | |
3823 | "register.\n"), | |
3824 | paddr_nz (ir.addr)); | |
3825 | } | |
3826 | else | |
3827 | { | |
3828 | if ((opcode & 1) == 0) | |
3829 | ir.ot = OT_BYTE; | |
3830 | else | |
3831 | ir.ot = ir.dflag + OT_WORD; | |
3832 | if (ir.aflag) | |
3833 | { | |
3834 | if (target_read_memory | |
3835 | (ir.addr, (gdb_byte *) & addr, 4)) | |
3836 | { | |
3837 | if (record_debug) | |
3838 | printf_unfiltered (_("Process record: error reading " | |
3839 | "memory at addr 0x%s len = 4.\n"), | |
3840 | paddr_nz (ir.addr)); | |
3841 | return -1; | |
3842 | } | |
3843 | ir.addr += 4; | |
3844 | } | |
3845 | else | |
3846 | { | |
3847 | if (target_read_memory | |
3848 | (ir.addr, (gdb_byte *) & tmpu16, 4)) | |
3849 | { | |
3850 | if (record_debug) | |
3851 | printf_unfiltered (_("Process record: error reading " | |
3852 | "memory at addr 0x%s len = 4.\n"), | |
3853 | paddr_nz (ir.addr)); | |
3854 | return -1; | |
3855 | } | |
3856 | ir.addr += 2; | |
3857 | addr = tmpu16; | |
3858 | } | |
3859 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) | |
3860 | return -1; | |
3861 | } | |
3862 | } | |
3863 | break; | |
3864 | ||
3865 | /* mov R, Ib */ | |
3866 | case 0xb0: | |
3867 | case 0xb1: | |
3868 | case 0xb2: | |
3869 | case 0xb3: | |
3870 | case 0xb4: | |
3871 | case 0xb5: | |
3872 | case 0xb6: | |
3873 | case 0xb7: | |
3874 | if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3)) | |
3875 | return -1; | |
3876 | break; | |
3877 | ||
3878 | /* mov R, Iv */ | |
3879 | case 0xb8: | |
3880 | case 0xb9: | |
3881 | case 0xba: | |
3882 | case 0xbb: | |
3883 | case 0xbc: | |
3884 | case 0xbd: | |
3885 | case 0xbe: | |
3886 | case 0xbf: | |
3887 | if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) | |
3888 | return -1; | |
3889 | break; | |
3890 | ||
3891 | /* xchg R, EAX */ | |
3892 | case 0x91: | |
3893 | case 0x92: | |
3894 | case 0x93: | |
3895 | case 0x94: | |
3896 | case 0x95: | |
3897 | case 0x96: | |
3898 | case 0x97: | |
3899 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
3900 | return -1; | |
3901 | if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) | |
3902 | return -1; | |
3903 | break; | |
3904 | ||
3905 | /* xchg Ev, Gv */ | |
3906 | case 0x86: | |
3907 | case 0x87: | |
3908 | if ((opcode & 1) == 0) | |
3909 | ir.ot = OT_BYTE; | |
3910 | else | |
3911 | ir.ot = ir.dflag + OT_WORD; | |
3912 | ||
3913 | if (i386_record_modrm (&ir)) | |
3914 | return -1; | |
3915 | ||
3916 | if (ir.mod == 3) | |
3917 | { | |
3918 | if (ir.ot == OT_BYTE) | |
3919 | ir.rm &= 0x3; | |
3920 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
3921 | return -1; | |
3922 | } | |
3923 | else | |
3924 | { | |
3925 | if (i386_record_lea_modrm (&ir)) | |
3926 | return -1; | |
3927 | } | |
3928 | ||
3929 | if (ir.ot == OT_BYTE) | |
3930 | ir.reg &= 0x3; | |
3931 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3932 | return -1; | |
3933 | break; | |
3934 | ||
3935 | /* les Gv */ | |
3936 | case 0xc4: | |
3937 | /* lds Gv */ | |
3938 | case 0xc5: | |
3939 | /* lss Gv */ | |
3940 | case 0x0fb2: | |
3941 | /* lfs Gv */ | |
3942 | case 0x0fb4: | |
3943 | /* lgs Gv */ | |
3944 | case 0x0fb5: | |
3945 | if (i386_record_modrm (&ir)) | |
3946 | return -1; | |
3947 | if (ir.mod == 3) | |
3948 | { | |
3949 | if (opcode > 0xff) | |
3950 | ir.addr -= 3; | |
3951 | else | |
3952 | ir.addr -= 2; | |
3953 | opcode = opcode << 8 | ir.modrm; | |
3954 | goto no_support; | |
3955 | } | |
3956 | ||
3957 | switch (opcode) | |
3958 | { | |
3959 | /* les Gv */ | |
3960 | case 0xc4: | |
3961 | tmpu8 = I386_ES_REGNUM; | |
3962 | break; | |
3963 | /* lds Gv */ | |
3964 | case 0xc5: | |
3965 | tmpu8 = I386_DS_REGNUM; | |
3966 | break; | |
3967 | /* lss Gv */ | |
3968 | case 0x0fb2: | |
3969 | tmpu8 = I386_SS_REGNUM; | |
3970 | break; | |
3971 | /* lfs Gv */ | |
3972 | case 0x0fb4: | |
3973 | tmpu8 = I386_FS_REGNUM; | |
3974 | break; | |
3975 | /* lgs Gv */ | |
3976 | case 0x0fb5: | |
3977 | tmpu8 = I386_GS_REGNUM; | |
3978 | break; | |
3979 | } | |
3980 | if (record_arch_list_add_reg (ir.regcache, tmpu8)) | |
3981 | return -1; | |
3982 | ||
3983 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
3984 | return -1; | |
3985 | break; | |
3986 | ||
3987 | /* shifts */ | |
3988 | case 0xc0: | |
3989 | case 0xc1: | |
3990 | case 0xd0: | |
3991 | case 0xd1: | |
3992 | case 0xd2: | |
3993 | case 0xd3: | |
3994 | if ((opcode & 1) == 0) | |
3995 | ir.ot = OT_BYTE; | |
3996 | else | |
3997 | ir.ot = ir.dflag + OT_WORD; | |
3998 | ||
3999 | if (i386_record_modrm (&ir)) | |
4000 | return -1; | |
4001 | ||
4002 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) | |
4003 | { | |
4004 | if (i386_record_lea_modrm (&ir)) | |
4005 | return -1; | |
4006 | } | |
4007 | else | |
4008 | { | |
4009 | if (ir.ot == OT_BYTE) | |
4010 | ir.rm &= 0x3; | |
4011 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4012 | return -1; | |
4013 | } | |
4014 | ||
4015 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4016 | return -1; | |
4017 | break; | |
4018 | ||
4019 | case 0x0fa4: | |
4020 | case 0x0fa5: | |
4021 | case 0x0fac: | |
4022 | case 0x0fad: | |
4023 | if (i386_record_modrm (&ir)) | |
4024 | return -1; | |
4025 | if (ir.mod == 3) | |
4026 | { | |
4027 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4028 | return -1; | |
4029 | } | |
4030 | else | |
4031 | { | |
4032 | if (i386_record_lea_modrm (&ir)) | |
4033 | return -1; | |
4034 | } | |
4035 | break; | |
4036 | ||
4037 | /* floats */ | |
4038 | /* It just record the memory change of instrcution. */ | |
4039 | case 0xd8: | |
4040 | case 0xd9: | |
4041 | case 0xda: | |
4042 | case 0xdb: | |
4043 | case 0xdc: | |
4044 | case 0xdd: | |
4045 | case 0xde: | |
4046 | case 0xdf: | |
4047 | if (i386_record_modrm (&ir)) | |
4048 | return -1; | |
4049 | ir.reg |= ((opcode & 7) << 3); | |
4050 | if (ir.mod != 3) | |
4051 | { | |
4052 | /* memory */ | |
4053 | uint32_t addr; | |
4054 | ||
4055 | if (i386_record_lea_modrm_addr (&ir, &addr)) | |
4056 | return -1; | |
4057 | switch (ir.reg) | |
4058 | { | |
4059 | case 0x00: | |
4060 | case 0x01: | |
4061 | case 0x02: | |
4062 | case 0x03: | |
4063 | case 0x04: | |
4064 | case 0x05: | |
4065 | case 0x06: | |
4066 | case 0x07: | |
4067 | case 0x10: | |
4068 | case 0x11: | |
4069 | case 0x12: | |
4070 | case 0x13: | |
4071 | case 0x14: | |
4072 | case 0x15: | |
4073 | case 0x16: | |
4074 | case 0x17: | |
4075 | case 0x20: | |
4076 | case 0x21: | |
4077 | case 0x22: | |
4078 | case 0x23: | |
4079 | case 0x24: | |
4080 | case 0x25: | |
4081 | case 0x26: | |
4082 | case 0x27: | |
4083 | case 0x30: | |
4084 | case 0x31: | |
4085 | case 0x32: | |
4086 | case 0x33: | |
4087 | case 0x34: | |
4088 | case 0x35: | |
4089 | case 0x36: | |
4090 | case 0x37: | |
4091 | break; | |
4092 | case 0x08: | |
4093 | case 0x0a: | |
4094 | case 0x0b: | |
4095 | case 0x18: | |
4096 | case 0x19: | |
4097 | case 0x1a: | |
4098 | case 0x1b: | |
4099 | case 0x28: | |
4100 | case 0x29: | |
4101 | case 0x2a: | |
4102 | case 0x2b: | |
4103 | case 0x38: | |
4104 | case 0x39: | |
4105 | case 0x3a: | |
4106 | case 0x3b: | |
4107 | switch (ir.reg & 7) | |
4108 | { | |
4109 | case 0: | |
4110 | break; | |
4111 | case 1: | |
4112 | switch (ir.reg >> 4) | |
4113 | { | |
4114 | case 0: | |
4115 | if (record_arch_list_add_mem (addr, 4)) | |
4116 | return -1; | |
4117 | break; | |
4118 | case 2: | |
4119 | if (record_arch_list_add_mem (addr, 8)) | |
4120 | return -1; | |
4121 | break; | |
4122 | case 3: | |
4123 | default: | |
4124 | if (record_arch_list_add_mem (addr, 2)) | |
4125 | return -1; | |
4126 | break; | |
4127 | } | |
4128 | break; | |
4129 | default: | |
4130 | switch (ir.reg >> 4) | |
4131 | { | |
4132 | case 0: | |
4133 | case 1: | |
4134 | if (record_arch_list_add_mem (addr, 4)) | |
4135 | return -1; | |
4136 | break; | |
4137 | case 2: | |
4138 | if (record_arch_list_add_mem (addr, 8)) | |
4139 | return -1; | |
4140 | break; | |
4141 | case 3: | |
4142 | default: | |
4143 | if (record_arch_list_add_mem (addr, 2)) | |
4144 | return -1; | |
4145 | break; | |
4146 | } | |
4147 | break; | |
4148 | } | |
4149 | break; | |
4150 | case 0x0c: | |
4151 | case 0x0d: | |
4152 | case 0x1d: | |
4153 | case 0x2c: | |
4154 | case 0x3c: | |
4155 | case 0x3d: | |
4156 | break; | |
4157 | case 0x0e: | |
4158 | if (ir.dflag) | |
4159 | { | |
4160 | if (record_arch_list_add_mem (addr, 28)) | |
4161 | return -1; | |
4162 | } | |
4163 | else | |
4164 | { | |
4165 | if (record_arch_list_add_mem (addr, 14)) | |
4166 | return -1; | |
4167 | } | |
4168 | break; | |
4169 | case 0x0f: | |
4170 | case 0x2f: | |
4171 | if (record_arch_list_add_mem (addr, 2)) | |
4172 | return -1; | |
4173 | break; | |
4174 | case 0x1f: | |
4175 | case 0x3e: | |
4176 | if (record_arch_list_add_mem (addr, 10)) | |
4177 | return -1; | |
4178 | break; | |
4179 | case 0x2e: | |
4180 | if (ir.dflag) | |
4181 | { | |
4182 | if (record_arch_list_add_mem (addr, 28)) | |
4183 | return -1; | |
4184 | addr += 28; | |
4185 | } | |
4186 | else | |
4187 | { | |
4188 | if (record_arch_list_add_mem (addr, 14)) | |
4189 | return -1; | |
4190 | addr += 14; | |
4191 | } | |
4192 | if (record_arch_list_add_mem (addr, 80)) | |
4193 | return -1; | |
4194 | break; | |
4195 | case 0x3f: | |
4196 | if (record_arch_list_add_mem (addr, 8)) | |
4197 | return -1; | |
4198 | break; | |
4199 | default: | |
4200 | ir.addr -= 2; | |
4201 | opcode = opcode << 8 | ir.modrm; | |
4202 | goto no_support; | |
4203 | break; | |
4204 | } | |
4205 | } | |
4206 | break; | |
4207 | ||
4208 | /* string ops */ | |
4209 | /* movsS */ | |
4210 | case 0xa4: | |
4211 | case 0xa5: | |
4212 | /* stosS */ | |
4213 | case 0xaa: | |
4214 | case 0xab: | |
4215 | /* insS */ | |
4216 | case 0x6c: | |
4217 | case 0x6d: | |
4218 | { | |
4219 | uint32_t addr; | |
4220 | ||
4221 | if ((opcode & 1) == 0) | |
4222 | ir.ot = OT_BYTE; | |
4223 | else | |
4224 | ir.ot = ir.dflag + OT_WORD; | |
4225 | if (opcode == 0xa4 || opcode == 0xa5) | |
4226 | { | |
4227 | if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) | |
4228 | return -1; | |
4229 | } | |
4230 | if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) | |
4231 | return -1; | |
4232 | ||
4233 | regcache_raw_read (ir.regcache, I386_EDI_REGNUM, | |
4234 | (gdb_byte *) & addr); | |
4235 | if (!ir.aflag) | |
4236 | { | |
4237 | addr &= 0xffff; | |
4238 | /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */ | |
4239 | if (record_debug) | |
4240 | printf_unfiltered (_("Process record ignores the memory change " | |
4241 | "of instruction at address 0x%s because " | |
4242 | "it can't get the value of the segment " | |
4243 | "register.\n"), | |
4244 | paddr_nz (ir.addr)); | |
4245 | } | |
4246 | ||
4247 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4248 | { | |
4249 | uint32_t count; | |
4250 | ||
4251 | regcache_raw_read (ir.regcache, I386_ECX_REGNUM, | |
4252 | (gdb_byte *) & count); | |
4253 | if (!ir.aflag) | |
4254 | count &= 0xffff; | |
4255 | ||
4256 | regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM, | |
4257 | (gdb_byte *) & tmpu32); | |
4258 | if ((tmpu32 >> 10) & 0x1) | |
4259 | addr -= (count - 1) * (1 << ir.ot); | |
4260 | ||
4261 | if (ir.aflag) | |
4262 | { | |
4263 | if (record_arch_list_add_mem (addr, count * (1 << ir.ot))) | |
4264 | return -1; | |
4265 | } | |
4266 | ||
4267 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4268 | return -1; | |
4269 | } | |
4270 | else | |
4271 | { | |
4272 | if (ir.aflag) | |
4273 | { | |
4274 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) | |
4275 | return -1; | |
4276 | } | |
4277 | } | |
4278 | } | |
4279 | break; | |
4280 | ||
4281 | /* lodsS */ | |
4282 | case 0xac: | |
4283 | case 0xad: | |
4284 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4285 | return -1; | |
4286 | if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) | |
4287 | return -1; | |
4288 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4289 | { | |
4290 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4291 | return -1; | |
4292 | } | |
4293 | break; | |
4294 | ||
4295 | /* outsS */ | |
4296 | case 0x6e: | |
4297 | case 0x6f: | |
4298 | if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) | |
4299 | return -1; | |
4300 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4301 | { | |
4302 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4303 | return -1; | |
4304 | } | |
4305 | break; | |
4306 | ||
4307 | /* scasS */ | |
4308 | case 0xae: | |
4309 | case 0xaf: | |
4310 | if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) | |
4311 | return -1; | |
4312 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4313 | { | |
4314 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4315 | return -1; | |
4316 | } | |
4317 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4318 | return -1; | |
4319 | break; | |
4320 | ||
4321 | /* cmpsS */ | |
4322 | case 0xa6: | |
4323 | case 0xa7: | |
4324 | if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) | |
4325 | return -1; | |
4326 | if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) | |
4327 | return -1; | |
4328 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4329 | { | |
4330 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4331 | return -1; | |
4332 | } | |
4333 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4334 | return -1; | |
4335 | break; | |
4336 | ||
4337 | /* port I/O */ | |
4338 | case 0xe4: | |
4339 | case 0xe5: | |
4340 | case 0xec: | |
4341 | case 0xed: | |
4342 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4343 | return -1; | |
4344 | break; | |
4345 | ||
4346 | case 0xe6: | |
4347 | case 0xe7: | |
4348 | case 0xee: | |
4349 | case 0xef: | |
4350 | break; | |
4351 | ||
4352 | /* control */ | |
4353 | /* ret im */ | |
4354 | case 0xc2: | |
4355 | /* ret */ | |
4356 | case 0xc3: | |
4357 | /* lret im */ | |
4358 | case 0xca: | |
4359 | /* lret */ | |
4360 | case 0xcb: | |
4361 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4362 | return -1; | |
4363 | if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) | |
4364 | return -1; | |
4365 | break; | |
4366 | ||
4367 | /* iret */ | |
4368 | case 0xcf: | |
4369 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4370 | return -1; | |
4371 | if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) | |
4372 | return -1; | |
4373 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4374 | return -1; | |
4375 | break; | |
4376 | ||
4377 | /* call im */ | |
4378 | case 0xe8: | |
4379 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4380 | return -1; | |
4381 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
4382 | (gdb_byte *) & tmpu32); | |
4383 | if (record_arch_list_add_mem | |
4384 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) | |
4385 | return -1; | |
4386 | break; | |
4387 | ||
4388 | /* lcall im */ | |
4389 | case 0x9a: | |
4390 | if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) | |
4391 | return -1; | |
4392 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4393 | return -1; | |
4394 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
4395 | (gdb_byte *) & tmpu32); | |
4396 | if (record_arch_list_add_mem | |
4397 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2)))) | |
4398 | return -1; | |
4399 | break; | |
4400 | ||
4401 | /* jmp im */ | |
4402 | case 0xe9: | |
4403 | /* ljmp im */ | |
4404 | case 0xea: | |
4405 | /* jmp Jb */ | |
4406 | case 0xeb: | |
4407 | /* jcc Jb */ | |
4408 | case 0x70: | |
4409 | case 0x71: | |
4410 | case 0x72: | |
4411 | case 0x73: | |
4412 | case 0x74: | |
4413 | case 0x75: | |
4414 | case 0x76: | |
4415 | case 0x77: | |
4416 | case 0x78: | |
4417 | case 0x79: | |
4418 | case 0x7a: | |
4419 | case 0x7b: | |
4420 | case 0x7c: | |
4421 | case 0x7d: | |
4422 | case 0x7e: | |
4423 | case 0x7f: | |
4424 | /* jcc Jv */ | |
4425 | case 0x0f80: | |
4426 | case 0x0f81: | |
4427 | case 0x0f82: | |
4428 | case 0x0f83: | |
4429 | case 0x0f84: | |
4430 | case 0x0f85: | |
4431 | case 0x0f86: | |
4432 | case 0x0f87: | |
4433 | case 0x0f88: | |
4434 | case 0x0f89: | |
4435 | case 0x0f8a: | |
4436 | case 0x0f8b: | |
4437 | case 0x0f8c: | |
4438 | case 0x0f8d: | |
4439 | case 0x0f8e: | |
4440 | case 0x0f8f: | |
4441 | break; | |
4442 | ||
4443 | /* setcc Gv */ | |
4444 | case 0x0f90: | |
4445 | case 0x0f91: | |
4446 | case 0x0f92: | |
4447 | case 0x0f93: | |
4448 | case 0x0f94: | |
4449 | case 0x0f95: | |
4450 | case 0x0f96: | |
4451 | case 0x0f97: | |
4452 | case 0x0f98: | |
4453 | case 0x0f99: | |
4454 | case 0x0f9a: | |
4455 | case 0x0f9b: | |
4456 | case 0x0f9c: | |
4457 | case 0x0f9d: | |
4458 | case 0x0f9e: | |
4459 | case 0x0f9f: | |
4460 | ir.ot = OT_BYTE; | |
4461 | if (i386_record_modrm (&ir)) | |
4462 | return -1; | |
4463 | if (ir.mod == 3) | |
4464 | { | |
4465 | if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3)) | |
4466 | return -1; | |
4467 | } | |
4468 | else | |
4469 | { | |
4470 | if (i386_record_lea_modrm (&ir)) | |
4471 | return -1; | |
4472 | } | |
4473 | break; | |
4474 | ||
4475 | /* cmov Gv, Ev */ | |
4476 | case 0x0f40: | |
4477 | case 0x0f41: | |
4478 | case 0x0f42: | |
4479 | case 0x0f43: | |
4480 | case 0x0f44: | |
4481 | case 0x0f45: | |
4482 | case 0x0f46: | |
4483 | case 0x0f47: | |
4484 | case 0x0f48: | |
4485 | case 0x0f49: | |
4486 | case 0x0f4a: | |
4487 | case 0x0f4b: | |
4488 | case 0x0f4c: | |
4489 | case 0x0f4d: | |
4490 | case 0x0f4e: | |
4491 | case 0x0f4f: | |
4492 | if (i386_record_modrm (&ir)) | |
4493 | return -1; | |
4494 | if (ir.dflag == OT_BYTE) | |
4495 | ir.reg &= 0x3; | |
4496 | if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3)) | |
4497 | return -1; | |
4498 | break; | |
4499 | ||
4500 | /* flags */ | |
4501 | /* pushf */ | |
4502 | case 0x9c: | |
4503 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4504 | return -1; | |
4505 | regcache_raw_read (ir.regcache, I386_ESP_REGNUM, | |
4506 | (gdb_byte *) & tmpu32); | |
4507 | if (record_arch_list_add_mem | |
4508 | ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) | |
4509 | return -1; | |
4510 | break; | |
4511 | ||
4512 | /* popf */ | |
4513 | case 0x9d: | |
4514 | if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) | |
4515 | return -1; | |
4516 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4517 | return -1; | |
4518 | break; | |
4519 | ||
4520 | /* sahf */ | |
4521 | case 0x9e: | |
4522 | /* cmc */ | |
4523 | case 0xf5: | |
4524 | /* clc */ | |
4525 | case 0xf8: | |
4526 | /* stc */ | |
4527 | case 0xf9: | |
4528 | /* cld */ | |
4529 | case 0xfc: | |
4530 | /* std */ | |
4531 | case 0xfd: | |
4532 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4533 | return -1; | |
4534 | break; | |
4535 | ||
4536 | /* lahf */ | |
4537 | case 0x9f: | |
4538 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4539 | return -1; | |
4540 | break; | |
4541 | ||
4542 | /* bit operations */ | |
4543 | /* bt/bts/btr/btc Gv, im */ | |
4544 | case 0x0fba: | |
4545 | /* bts */ | |
4546 | case 0x0fab: | |
4547 | /* btr */ | |
4548 | case 0x0fb3: | |
4549 | /* btc */ | |
4550 | case 0x0fbb: | |
4551 | ir.ot = ir.dflag + OT_WORD; | |
4552 | if (i386_record_modrm (&ir)) | |
4553 | return -1; | |
4554 | if (ir.reg < 4) | |
4555 | { | |
4556 | ir.addr -= 3; | |
4557 | opcode = opcode << 8 | ir.modrm; | |
4558 | goto no_support; | |
4559 | } | |
4560 | ir.reg -= 4; | |
4561 | if (ir.reg != 0) | |
4562 | { | |
4563 | if (ir.mod != 3) | |
4564 | { | |
4565 | if (i386_record_lea_modrm (&ir)) | |
4566 | return -1; | |
4567 | } | |
4568 | else | |
4569 | { | |
4570 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4571 | return -1; | |
4572 | } | |
4573 | } | |
4574 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4575 | return -1; | |
4576 | break; | |
4577 | ||
4578 | /* bt Gv, Ev */ | |
4579 | case 0x0fa3: | |
4580 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4581 | return -1; | |
4582 | break; | |
4583 | ||
4584 | /* bsf */ | |
4585 | case 0x0fbc: | |
4586 | /* bsr */ | |
4587 | case 0x0fbd: | |
4588 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
4589 | return -1; | |
4590 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4591 | return -1; | |
4592 | break; | |
4593 | ||
4594 | /* bcd */ | |
4595 | /* daa */ | |
4596 | case 0x27: | |
4597 | /* das */ | |
4598 | case 0x2f: | |
4599 | /* aaa */ | |
4600 | case 0x37: | |
4601 | /* aas */ | |
4602 | case 0x3f: | |
4603 | /* aam */ | |
4604 | case 0xd4: | |
4605 | /* aad */ | |
4606 | case 0xd5: | |
4607 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4608 | return -1; | |
4609 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4610 | return -1; | |
4611 | break; | |
4612 | ||
4613 | /* misc */ | |
4614 | /* nop */ | |
4615 | case 0x90: | |
4616 | if (prefixes & PREFIX_LOCK) | |
4617 | { | |
4618 | ir.addr -= 1; | |
4619 | goto no_support; | |
4620 | } | |
4621 | break; | |
4622 | ||
4623 | /* fwait */ | |
4624 | /* XXX */ | |
4625 | case 0x9b: | |
4626 | printf_unfiltered (_("Process record doesn't support instruction " | |
4627 | "fwait.\n")); | |
4628 | ir.addr -= 1; | |
4629 | goto no_support; | |
4630 | break; | |
4631 | ||
4632 | /* int3 */ | |
4633 | /* XXX */ | |
4634 | case 0xcc: | |
4635 | printf_unfiltered (_("Process record doesn't support instruction " | |
4636 | "int3.\n")); | |
4637 | ir.addr -= 1; | |
4638 | goto no_support; | |
4639 | break; | |
4640 | ||
4641 | /* int */ | |
4642 | /* XXX */ | |
4643 | case 0xcd: | |
4644 | { | |
4645 | int ret; | |
4646 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
4647 | { | |
4648 | if (record_debug) | |
4649 | printf_unfiltered (_("Process record: error reading memory " | |
4650 | "at addr 0x%s len = 1.\n"), | |
4651 | paddr_nz (ir.addr)); | |
4652 | return -1; | |
4653 | } | |
4654 | ir.addr++; | |
4655 | if (tmpu8 != 0x80 | |
4656 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) | |
4657 | { | |
4658 | printf_unfiltered (_("Process record doesn't support " | |
4659 | "instruction int 0x%02x.\n"), | |
4660 | tmpu8); | |
4661 | ir.addr -= 2; | |
4662 | goto no_support; | |
4663 | } | |
4664 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
4665 | if (ret) | |
4666 | return ret; | |
4667 | } | |
4668 | break; | |
4669 | ||
4670 | /* into */ | |
4671 | /* XXX */ | |
4672 | case 0xce: | |
4673 | printf_unfiltered (_("Process record doesn't support " | |
4674 | "instruction into.\n")); | |
4675 | ir.addr -= 1; | |
4676 | goto no_support; | |
4677 | break; | |
4678 | ||
4679 | /* cli */ | |
4680 | case 0xfa: | |
4681 | /* sti */ | |
4682 | case 0xfb: | |
4683 | break; | |
4684 | ||
4685 | /* bound */ | |
4686 | case 0x62: | |
4687 | printf_unfiltered (_("Process record doesn't support " | |
4688 | "instruction bound.\n")); | |
4689 | ir.addr -= 1; | |
4690 | goto no_support; | |
4691 | break; | |
4692 | ||
4693 | /* bswap reg */ | |
4694 | case 0x0fc8: | |
4695 | case 0x0fc9: | |
4696 | case 0x0fca: | |
4697 | case 0x0fcb: | |
4698 | case 0x0fcc: | |
4699 | case 0x0fcd: | |
4700 | case 0x0fce: | |
4701 | case 0x0fcf: | |
4702 | if (record_arch_list_add_reg (ir.regcache, opcode & 7)) | |
4703 | return -1; | |
4704 | break; | |
4705 | ||
4706 | /* salc */ | |
4707 | case 0xd6: | |
4708 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4709 | return -1; | |
4710 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4711 | return -1; | |
4712 | break; | |
4713 | ||
4714 | /* loopnz */ | |
4715 | case 0xe0: | |
4716 | /* loopz */ | |
4717 | case 0xe1: | |
4718 | /* loop */ | |
4719 | case 0xe2: | |
4720 | /* jecxz */ | |
4721 | case 0xe3: | |
4722 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4723 | return -1; | |
4724 | break; | |
4725 | ||
4726 | /* wrmsr */ | |
4727 | case 0x0f30: | |
4728 | printf_unfiltered (_("Process record doesn't support " | |
4729 | "instruction wrmsr.\n")); | |
4730 | ir.addr -= 2; | |
4731 | goto no_support; | |
4732 | break; | |
4733 | ||
4734 | /* rdmsr */ | |
4735 | case 0x0f32: | |
4736 | printf_unfiltered (_("Process record doesn't support " | |
4737 | "instruction rdmsr.\n")); | |
4738 | ir.addr -= 2; | |
4739 | goto no_support; | |
4740 | break; | |
4741 | ||
4742 | /* rdtsc */ | |
4743 | case 0x0f31: | |
4744 | printf_unfiltered (_("Process record doesn't support " | |
4745 | "instruction rdtsc.\n")); | |
4746 | ir.addr -= 2; | |
4747 | goto no_support; | |
4748 | break; | |
4749 | ||
4750 | /* sysenter */ | |
4751 | case 0x0f34: | |
4752 | { | |
4753 | int ret; | |
4754 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) | |
4755 | { | |
4756 | printf_unfiltered (_("Process record doesn't support " | |
4757 | "instruction sysenter.\n")); | |
4758 | ir.addr -= 2; | |
4759 | goto no_support; | |
4760 | } | |
4761 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
4762 | if (ret) | |
4763 | return ret; | |
4764 | } | |
4765 | break; | |
4766 | ||
4767 | /* sysexit */ | |
4768 | case 0x0f35: | |
4769 | printf_unfiltered (_("Process record doesn't support " | |
4770 | "instruction sysexit.\n")); | |
4771 | ir.addr -= 2; | |
4772 | goto no_support; | |
4773 | break; | |
4774 | ||
4775 | /* cpuid */ | |
4776 | case 0x0fa2: | |
4777 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4778 | return -1; | |
4779 | if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) | |
4780 | return -1; | |
4781 | if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) | |
4782 | return -1; | |
4783 | if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM)) | |
4784 | return -1; | |
4785 | break; | |
4786 | ||
4787 | /* hlt */ | |
4788 | case 0xf4: | |
4789 | printf_unfiltered (_("Process record doesn't support " | |
4790 | "instruction hlt.\n")); | |
4791 | ir.addr -= 1; | |
4792 | goto no_support; | |
4793 | break; | |
4794 | ||
4795 | case 0x0f00: | |
4796 | if (i386_record_modrm (&ir)) | |
4797 | return -1; | |
4798 | switch (ir.reg) | |
4799 | { | |
4800 | /* sldt */ | |
4801 | case 0: | |
4802 | /* str */ | |
4803 | case 1: | |
4804 | if (ir.mod == 3) | |
4805 | { | |
4806 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4807 | return -1; | |
4808 | } | |
4809 | else | |
4810 | { | |
4811 | ir.ot = OT_WORD; | |
4812 | if (i386_record_lea_modrm (&ir)) | |
4813 | return -1; | |
4814 | } | |
4815 | break; | |
4816 | /* lldt */ | |
4817 | case 2: | |
4818 | /* ltr */ | |
4819 | case 3: | |
4820 | break; | |
4821 | /* verr */ | |
4822 | case 4: | |
4823 | /* verw */ | |
4824 | case 5: | |
4825 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4826 | return -1; | |
4827 | break; | |
4828 | default: | |
4829 | ir.addr -= 3; | |
4830 | opcode = opcode << 8 | ir.modrm; | |
4831 | goto no_support; | |
4832 | break; | |
4833 | } | |
4834 | break; | |
4835 | ||
4836 | case 0x0f01: | |
4837 | if (i386_record_modrm (&ir)) | |
4838 | return -1; | |
4839 | switch (ir.reg) | |
4840 | { | |
4841 | /* sgdt */ | |
4842 | case 0: | |
4843 | { | |
4844 | uint32_t addr; | |
4845 | ||
4846 | if (ir.mod == 3) | |
4847 | { | |
4848 | ir.addr -= 3; | |
4849 | opcode = opcode << 8 | ir.modrm; | |
4850 | goto no_support; | |
4851 | } | |
4852 | ||
4853 | if (ir.override) | |
4854 | { | |
4855 | if (record_debug) | |
4856 | printf_unfiltered (_("Process record ignores the memory " | |
4857 | "change of instruction at " | |
4858 | "address 0x%s because it can't get " | |
4859 | "the value of the segment " | |
4860 | "register.\n"), | |
4861 | paddr_nz (ir.addr)); | |
4862 | } | |
4863 | else | |
4864 | { | |
4865 | if (i386_record_lea_modrm_addr (&ir, &addr)) | |
4866 | return -1; | |
4867 | if (record_arch_list_add_mem (addr, 2)) | |
4868 | return -1; | |
4869 | addr += 2; | |
4870 | if (record_arch_list_add_mem (addr, 4)) | |
4871 | return -1; | |
4872 | } | |
4873 | } | |
4874 | break; | |
4875 | case 1: | |
4876 | if (ir.mod == 3) | |
4877 | { | |
4878 | switch (ir.rm) | |
4879 | { | |
4880 | /* monitor */ | |
4881 | case 0: | |
4882 | break; | |
4883 | /* mwait */ | |
4884 | case 1: | |
4885 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4886 | return -1; | |
4887 | break; | |
4888 | default: | |
4889 | ir.addr -= 3; | |
4890 | opcode = opcode << 8 | ir.modrm; | |
4891 | goto no_support; | |
4892 | break; | |
4893 | } | |
4894 | } | |
4895 | else | |
4896 | { | |
4897 | /* sidt */ | |
4898 | if (ir.override) | |
4899 | { | |
4900 | if (record_debug) | |
4901 | printf_unfiltered (_("Process record ignores the memory " | |
4902 | "change of instruction at " | |
4903 | "address 0x%s because it can't get " | |
4904 | "the value of the segment " | |
4905 | "register.\n"), | |
4906 | paddr_nz (ir.addr)); | |
4907 | } | |
4908 | else | |
4909 | { | |
4910 | uint32_t addr; | |
4911 | ||
4912 | if (i386_record_lea_modrm_addr (&ir, &addr)) | |
4913 | return -1; | |
4914 | if (record_arch_list_add_mem (addr, 2)) | |
4915 | return -1; | |
4916 | addr += 2; | |
4917 | if (record_arch_list_add_mem (addr, 4)) | |
4918 | return -1; | |
4919 | } | |
4920 | } | |
4921 | break; | |
4922 | /* lgdt */ | |
4923 | case 2: | |
4924 | /* lidt */ | |
4925 | case 3: | |
4926 | /* invlpg */ | |
4927 | case 7: | |
4928 | default: | |
4929 | if (ir.mod == 3) | |
4930 | { | |
4931 | ir.addr -= 3; | |
4932 | opcode = opcode << 8 | ir.modrm; | |
4933 | goto no_support; | |
4934 | } | |
4935 | break; | |
4936 | /* smsw */ | |
4937 | case 4: | |
4938 | if (ir.mod == 3) | |
4939 | { | |
4940 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4941 | return -1; | |
4942 | } | |
4943 | else | |
4944 | { | |
4945 | ir.ot = OT_WORD; | |
4946 | if (i386_record_lea_modrm (&ir)) | |
4947 | return -1; | |
4948 | } | |
4949 | break; | |
4950 | /* lmsw */ | |
4951 | case 6: | |
4952 | break; | |
4953 | } | |
4954 | break; | |
4955 | ||
4956 | /* invd */ | |
4957 | case 0x0f08: | |
4958 | /* wbinvd */ | |
4959 | case 0x0f09: | |
4960 | break; | |
4961 | ||
4962 | /* arpl */ | |
4963 | case 0x63: | |
4964 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
4965 | if (i386_record_modrm (&ir)) | |
4966 | return -1; | |
4967 | if (ir.mod != 3) | |
4968 | { | |
4969 | if (i386_record_lea_modrm (&ir)) | |
4970 | return -1; | |
4971 | } | |
4972 | else | |
4973 | { | |
4974 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4975 | return -1; | |
4976 | } | |
4977 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4978 | return -1; | |
4979 | break; | |
4980 | ||
4981 | /* lar */ | |
4982 | case 0x0f02: | |
4983 | /* lsl */ | |
4984 | case 0x0f03: | |
4985 | if (i386_record_modrm (&ir)) | |
4986 | return -1; | |
4987 | if (record_arch_list_add_reg (ir.regcache, ir.reg)) | |
4988 | return -1; | |
4989 | if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) | |
4990 | return -1; | |
4991 | break; | |
4992 | ||
4993 | case 0x0f18: | |
4994 | break; | |
4995 | ||
4996 | /* nop (multi byte) */ | |
4997 | case 0x0f19: | |
4998 | case 0x0f1a: | |
4999 | case 0x0f1b: | |
5000 | case 0x0f1c: | |
5001 | case 0x0f1d: | |
5002 | case 0x0f1e: | |
5003 | case 0x0f1f: | |
5004 | break; | |
5005 | ||
5006 | /* mov reg, crN */ | |
5007 | case 0x0f20: | |
5008 | /* mov crN, reg */ | |
5009 | case 0x0f22: | |
5010 | if (i386_record_modrm (&ir)) | |
5011 | return -1; | |
5012 | if ((ir.modrm & 0xc0) != 0xc0) | |
5013 | { | |
5014 | ir.addr -= 2; | |
5015 | opcode = opcode << 8 | ir.modrm; | |
5016 | goto no_support; | |
5017 | } | |
5018 | switch (ir.reg) | |
5019 | { | |
5020 | case 0: | |
5021 | case 2: | |
5022 | case 3: | |
5023 | case 4: | |
5024 | case 8: | |
5025 | if (opcode & 2) | |
5026 | { | |
5027 | } | |
5028 | else | |
5029 | { | |
5030 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
5031 | return -1; | |
5032 | } | |
5033 | break; | |
5034 | default: | |
5035 | ir.addr -= 2; | |
5036 | opcode = opcode << 8 | ir.modrm; | |
5037 | goto no_support; | |
5038 | break; | |
5039 | } | |
5040 | break; | |
5041 | ||
5042 | /* mov reg, drN */ | |
5043 | case 0x0f21: | |
5044 | /* mov drN, reg */ | |
5045 | case 0x0f23: | |
5046 | if (i386_record_modrm (&ir)) | |
5047 | return -1; | |
5048 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5049 | || ir.reg == 5 || ir.reg >= 8) | |
5050 | { | |
5051 | ir.addr -= 2; | |
5052 | opcode = opcode << 8 | ir.modrm; | |
5053 | goto no_support; | |
5054 | } | |
5055 | if (opcode & 2) | |
5056 | { | |
5057 | } | |
5058 | else | |
5059 | { | |
5060 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
5061 | return -1; | |
5062 | } | |
5063 | break; | |
5064 | ||
5065 | /* clts */ | |
5066 | case 0x0f06: | |
5067 | break; | |
5068 | ||
5069 | /* MMX/SSE/SSE2/PNI support */ | |
5070 | /* XXX */ | |
5071 | ||
5072 | default: | |
5073 | if (opcode > 0xff) | |
5074 | ir.addr -= 2; | |
5075 | else | |
5076 | ir.addr -= 1; | |
5077 | goto no_support; | |
5078 | break; | |
5079 | } | |
5080 | ||
5081 | /* In the future, Maybe still need to deal with need_dasm */ | |
5082 | if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM)) | |
5083 | return -1; | |
5084 | if (record_arch_list_add_end ()) | |
5085 | return -1; | |
5086 | ||
5087 | return 0; | |
5088 | ||
5089 | no_support: | |
5090 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " | |
5091 | "at address 0x%s.\n"), | |
5092 | (unsigned int) (opcode), paddr_nz (ir.addr)); | |
5093 | return -1; | |
5094 | } | |
5095 | ||
5096 | \f | |
5097 | static struct gdbarch * | |
5098 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5099 | { | |
5100 | struct gdbarch_tdep *tdep; | |
5101 | struct gdbarch *gdbarch; | |
5102 | ||
5103 | /* If there is already a candidate, use it. */ | |
5104 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5105 | if (arches != NULL) | |
5106 | return arches->gdbarch; | |
5107 | ||
5108 | /* Allocate space for the new architecture. */ | |
5109 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5110 | gdbarch = gdbarch_alloc (&info, tdep); | |
5111 | ||
5112 | /* General-purpose registers. */ | |
5113 | tdep->gregset = NULL; | |
5114 | tdep->gregset_reg_offset = NULL; | |
5115 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5116 | tdep->sizeof_gregset = 0; | |
5117 | ||
5118 | /* Floating-point registers. */ | |
5119 | tdep->fpregset = NULL; | |
5120 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5121 | ||
5122 | /* The default settings include the FPU registers, the MMX registers | |
5123 | and the SSE registers. This can be overridden for a specific ABI | |
5124 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5125 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5126 | will show up in the output of "info all-registers". Ideally we | |
5127 | should try to autodetect whether they are available, such that we | |
5128 | can prevent "info all-registers" from displaying registers that | |
5129 | aren't available. | |
5130 | ||
5131 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5132 | [the SSE registers] always (even when they don't exist) or never | |
5133 | showing them to the user (even when they do exist), I prefer the | |
5134 | former over the latter. */ | |
5135 | ||
5136 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5137 | ||
5138 | /* The MMX registers are implemented as pseudo-registers. Put off | |
5139 | calculating the register number for %mm0 until we know the number | |
5140 | of raw registers. */ | |
5141 | tdep->mm0_regnum = 0; | |
5142 | ||
5143 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
5144 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5145 | ||
5146 | tdep->jb_pc_offset = -1; | |
5147 | tdep->struct_return = pcc_struct_return; | |
5148 | tdep->sigtramp_start = 0; | |
5149 | tdep->sigtramp_end = 0; | |
5150 | tdep->sigtramp_p = i386_sigtramp_p; | |
5151 | tdep->sigcontext_addr = NULL; | |
5152 | tdep->sc_reg_offset = NULL; | |
5153 | tdep->sc_pc_offset = -1; | |
5154 | tdep->sc_sp_offset = -1; | |
5155 | ||
5156 | /* The format used for `long double' on almost all i386 targets is | |
5157 | the i387 extended floating-point format. In fact, of all targets | |
5158 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5159 | on having a `long double' that's not `long' at all. */ | |
5160 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5161 | ||
5162 | /* Although the i387 extended floating-point has only 80 significant | |
5163 | bits, a `long double' actually takes up 96, probably to enforce | |
5164 | alignment. */ | |
5165 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5166 | ||
5167 | /* The default ABI includes general-purpose registers, | |
5168 | floating-point registers, and the SSE registers. */ | |
5169 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5170 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
5171 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
5172 | ||
5173 | /* Register numbers of various important registers. */ | |
5174 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5175 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5176 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5177 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5178 | ||
5179 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5180 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5181 | differ in how they number %ebp, %esp, %eflags, and the | |
5182 | floating-point registers, and are implemented by the arrays | |
5183 | dbx_register_map[] and svr4_dbx_register_map in | |
5184 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5185 | gcc/config/i386.c, which it designates as the "default" register | |
5186 | map used in 64bit mode. This last register numbering scheme is | |
5187 | implemented in dbx64_register_map, and is used for AMD64; see | |
5188 | amd64-tdep.c. | |
5189 | ||
5190 | Currently, each GCC i386 target always uses the same register | |
5191 | numbering scheme across all its supported debugging formats | |
5192 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5193 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5194 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5195 | respective config header in a manner independent of the requested | |
5196 | output debugging format. | |
5197 | ||
5198 | This does not match the arrangement below, which presumes that | |
5199 | the SDB and stabs numbering schemes differ from the DWARF and | |
5200 | DWARF 2 ones. The reason for this arrangement is that it is | |
5201 | likely to get the numbering scheme for the target's | |
5202 | default/native debug format right. For targets where GCC is the | |
5203 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5204 | targets where the native toolchain uses a different numbering | |
5205 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5206 | the defaults below will have to be overridden, like | |
5207 | i386_elf_init_abi() does. */ | |
5208 | ||
5209 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5210 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5211 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5212 | ||
5213 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5214 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5215 | ||
5216 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5217 | be in use on any of the supported i386 targets. */ | |
5218 | ||
5219 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5220 | ||
5221 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5222 | ||
5223 | /* Call dummy code. */ | |
5224 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5225 | ||
5226 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5227 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5228 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5229 | ||
5230 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5231 | ||
5232 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5233 | ||
5234 | /* Stack grows downward. */ | |
5235 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5236 | ||
5237 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5238 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5239 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5240 | ||
5241 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5242 | ||
5243 | /* Wire in the MMX registers. */ | |
5244 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); | |
5245 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); | |
5246 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5247 | ||
5248 | set_gdbarch_print_insn (gdbarch, i386_print_insn); | |
5249 | ||
5250 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5251 | ||
5252 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5253 | ||
5254 | /* Add the i386 register groups. */ | |
5255 | i386_add_reggroups (gdbarch); | |
5256 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
38c968cf | 5257 | |
143985b7 AF |
5258 | /* Helper for function argument information. */ |
5259 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5260 | ||
6405b0a6 | 5261 | /* Hook in the DWARF CFI frame unwinder. */ |
10458914 | 5262 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5263 | |
acd5c798 | 5264 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5265 | |
3ce1502b | 5266 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 5267 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5268 | |
10458914 DJ |
5269 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5270 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5271 | |
8446b36a MK |
5272 | /* If we have a register mapping, enable the generic core file |
5273 | support, unless it has already been enabled. */ | |
5274 | if (tdep->gregset_reg_offset | |
5275 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5276 | set_gdbarch_regset_from_core_section (gdbarch, | |
5277 | i386_regset_from_core_section); | |
5278 | ||
5716833c MK |
5279 | /* Unless support for MMX has been disabled, make %mm0 the first |
5280 | pseudo-register. */ | |
5281 | if (tdep->mm0_regnum == 0) | |
5282 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
5283 | ||
514f746b AR |
5284 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5285 | i386_skip_permanent_breakpoint); | |
5286 | ||
a62cc96e AC |
5287 | return gdbarch; |
5288 | } | |
5289 | ||
8201327c MK |
5290 | static enum gdb_osabi |
5291 | i386_coff_osabi_sniffer (bfd *abfd) | |
5292 | { | |
762c5349 MK |
5293 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5294 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5295 | return GDB_OSABI_GO32; |
5296 | ||
5297 | return GDB_OSABI_UNKNOWN; | |
5298 | } | |
8201327c MK |
5299 | \f |
5300 | ||
28e9e0f0 MK |
5301 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5302 | void _initialize_i386_tdep (void); | |
5303 | ||
c906108c | 5304 | void |
fba45db2 | 5305 | _initialize_i386_tdep (void) |
c906108c | 5306 | { |
a62cc96e AC |
5307 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5308 | ||
fc338970 | 5309 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5310 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5311 | &disassembly_flavor, _("\ | |
5312 | Set the disassembly flavor."), _("\ | |
5313 | Show the disassembly flavor."), _("\ | |
5314 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5315 | NULL, | |
5316 | NULL, /* FIXME: i18n: */ | |
5317 | &setlist, &showlist); | |
8201327c MK |
5318 | |
5319 | /* Add the variable that controls the convention for returning | |
5320 | structs. */ | |
7ab04401 AC |
5321 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5322 | &struct_convention, _("\ | |
5323 | Set the convention for returning small structs."), _("\ | |
5324 | Show the convention for returning small structs."), _("\ | |
5325 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5326 | is \"default\"."), | |
5327 | NULL, | |
5328 | NULL, /* FIXME: i18n: */ | |
5329 | &setlist, &showlist); | |
8201327c MK |
5330 | |
5331 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5332 | i386_coff_osabi_sniffer); | |
8201327c | 5333 | |
05816f70 | 5334 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5335 | i386_svr4_init_abi); |
05816f70 | 5336 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 5337 | i386_go32_init_abi); |
38c968cf | 5338 | |
5ae96ec1 | 5339 | /* Initialize the i386-specific register groups & types. */ |
38c968cf | 5340 | i386_init_reggroups (); |
5ae96ec1 | 5341 | i386_init_types(); |
c906108c | 5342 | } |