Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
28e7fd62 | 3 | Copyright (C) 1988-2013 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 | 54 | #include "record.h" |
d02ed0bb | 55 | #include "record-full.h" |
7ad10968 HZ |
56 | #include <stdint.h> |
57 | ||
90884b2b | 58 | #include "features/i386/i386.c" |
c131fcee | 59 | #include "features/i386/i386-avx.c" |
3a13a53b | 60 | #include "features/i386/i386-mmx.c" |
90884b2b | 61 | |
6710bf39 SS |
62 | #include "ax.h" |
63 | #include "ax-gdb.h" | |
64 | ||
55aa24fb SDJ |
65 | #include "stap-probe.h" |
66 | #include "user-regs.h" | |
67 | #include "cli/cli-utils.h" | |
68 | #include "expression.h" | |
69 | #include "parser-defs.h" | |
70 | #include <ctype.h> | |
71 | ||
c4fc7f1b | 72 | /* Register names. */ |
c40e1eab | 73 | |
90884b2b | 74 | static const char *i386_register_names[] = |
fc633446 MK |
75 | { |
76 | "eax", "ecx", "edx", "ebx", | |
77 | "esp", "ebp", "esi", "edi", | |
78 | "eip", "eflags", "cs", "ss", | |
79 | "ds", "es", "fs", "gs", | |
80 | "st0", "st1", "st2", "st3", | |
81 | "st4", "st5", "st6", "st7", | |
82 | "fctrl", "fstat", "ftag", "fiseg", | |
83 | "fioff", "foseg", "fooff", "fop", | |
84 | "xmm0", "xmm1", "xmm2", "xmm3", | |
85 | "xmm4", "xmm5", "xmm6", "xmm7", | |
86 | "mxcsr" | |
87 | }; | |
88 | ||
c131fcee L |
89 | static const char *i386_ymm_names[] = |
90 | { | |
91 | "ymm0", "ymm1", "ymm2", "ymm3", | |
92 | "ymm4", "ymm5", "ymm6", "ymm7", | |
93 | }; | |
94 | ||
95 | static const char *i386_ymmh_names[] = | |
96 | { | |
97 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
98 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
99 | }; | |
100 | ||
c4fc7f1b | 101 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 102 | |
90884b2b | 103 | static const char *i386_mmx_names[] = |
28fc6740 AC |
104 | { |
105 | "mm0", "mm1", "mm2", "mm3", | |
106 | "mm4", "mm5", "mm6", "mm7" | |
107 | }; | |
c40e1eab | 108 | |
1ba53b71 L |
109 | /* Register names for byte pseudo-registers. */ |
110 | ||
111 | static const char *i386_byte_names[] = | |
112 | { | |
113 | "al", "cl", "dl", "bl", | |
114 | "ah", "ch", "dh", "bh" | |
115 | }; | |
116 | ||
117 | /* Register names for word pseudo-registers. */ | |
118 | ||
119 | static const char *i386_word_names[] = | |
120 | { | |
121 | "ax", "cx", "dx", "bx", | |
9cad29ac | 122 | "", "bp", "si", "di" |
1ba53b71 L |
123 | }; |
124 | ||
125 | /* MMX register? */ | |
c40e1eab | 126 | |
28fc6740 | 127 | static int |
5716833c | 128 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 129 | { |
1ba53b71 L |
130 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
131 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
132 | |
133 | if (mm0_regnum < 0) | |
134 | return 0; | |
135 | ||
1ba53b71 L |
136 | regnum -= mm0_regnum; |
137 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
138 | } | |
139 | ||
140 | /* Byte register? */ | |
141 | ||
142 | int | |
143 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
144 | { | |
145 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
146 | ||
147 | regnum -= tdep->al_regnum; | |
148 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
149 | } | |
150 | ||
151 | /* Word register? */ | |
152 | ||
153 | int | |
154 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
155 | { | |
156 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
157 | ||
158 | regnum -= tdep->ax_regnum; | |
159 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
160 | } | |
161 | ||
162 | /* Dword register? */ | |
163 | ||
164 | int | |
165 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
166 | { | |
167 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
168 | int eax_regnum = tdep->eax_regnum; | |
169 | ||
170 | if (eax_regnum < 0) | |
171 | return 0; | |
172 | ||
173 | regnum -= eax_regnum; | |
174 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
175 | } |
176 | ||
9191d390 | 177 | static int |
c131fcee L |
178 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
179 | { | |
180 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
181 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
182 | ||
183 | if (ymm0h_regnum < 0) | |
184 | return 0; | |
185 | ||
186 | regnum -= ymm0h_regnum; | |
187 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
188 | } | |
189 | ||
190 | /* AVX register? */ | |
191 | ||
192 | int | |
193 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
194 | { | |
195 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
196 | int ymm0_regnum = tdep->ymm0_regnum; | |
197 | ||
198 | if (ymm0_regnum < 0) | |
199 | return 0; | |
200 | ||
201 | regnum -= ymm0_regnum; | |
202 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
203 | } | |
204 | ||
5716833c | 205 | /* SSE register? */ |
23a34459 | 206 | |
c131fcee L |
207 | int |
208 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 209 | { |
5716833c | 210 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 211 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 212 | |
c131fcee | 213 | if (num_xmm_regs == 0) |
5716833c MK |
214 | return 0; |
215 | ||
c131fcee L |
216 | regnum -= I387_XMM0_REGNUM (tdep); |
217 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
218 | } |
219 | ||
5716833c MK |
220 | static int |
221 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 222 | { |
5716833c MK |
223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
224 | ||
20a6ec49 | 225 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
226 | return 0; |
227 | ||
20a6ec49 | 228 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
229 | } |
230 | ||
5716833c | 231 | /* FP register? */ |
23a34459 AC |
232 | |
233 | int | |
20a6ec49 | 234 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 235 | { |
20a6ec49 MD |
236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
237 | ||
238 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
239 | return 0; |
240 | ||
20a6ec49 MD |
241 | return (I387_ST0_REGNUM (tdep) <= regnum |
242 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
243 | } |
244 | ||
245 | int | |
20a6ec49 | 246 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 247 | { |
20a6ec49 MD |
248 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
249 | ||
250 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
251 | return 0; |
252 | ||
20a6ec49 MD |
253 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
254 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
255 | } |
256 | ||
c131fcee L |
257 | /* Return the name of register REGNUM, or the empty string if it is |
258 | an anonymous register. */ | |
259 | ||
260 | static const char * | |
261 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
262 | { | |
263 | /* Hide the upper YMM registers. */ | |
264 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
265 | return ""; | |
266 | ||
267 | return tdesc_register_name (gdbarch, regnum); | |
268 | } | |
269 | ||
30b0e2d8 | 270 | /* Return the name of register REGNUM. */ |
fc633446 | 271 | |
1ba53b71 | 272 | const char * |
90884b2b | 273 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 274 | { |
1ba53b71 L |
275 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
276 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
277 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
278 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
279 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
280 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
281 | return i386_byte_names[regnum - tdep->al_regnum]; | |
282 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
283 | return i386_word_names[regnum - tdep->ax_regnum]; | |
284 | ||
285 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
286 | } |
287 | ||
c4fc7f1b | 288 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
289 | number used by GDB. */ |
290 | ||
8201327c | 291 | static int |
d3f73121 | 292 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 293 | { |
20a6ec49 MD |
294 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
295 | ||
c4fc7f1b MK |
296 | /* This implements what GCC calls the "default" register map |
297 | (dbx_register_map[]). */ | |
298 | ||
85540d8c MK |
299 | if (reg >= 0 && reg <= 7) |
300 | { | |
9872ad24 JB |
301 | /* General-purpose registers. The debug info calls %ebp |
302 | register 4, and %esp register 5. */ | |
303 | if (reg == 4) | |
304 | return 5; | |
305 | else if (reg == 5) | |
306 | return 4; | |
307 | else return reg; | |
85540d8c MK |
308 | } |
309 | else if (reg >= 12 && reg <= 19) | |
310 | { | |
311 | /* Floating-point registers. */ | |
20a6ec49 | 312 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
313 | } |
314 | else if (reg >= 21 && reg <= 28) | |
315 | { | |
316 | /* SSE registers. */ | |
c131fcee L |
317 | int ymm0_regnum = tdep->ymm0_regnum; |
318 | ||
319 | if (ymm0_regnum >= 0 | |
320 | && i386_xmm_regnum_p (gdbarch, reg)) | |
321 | return reg - 21 + ymm0_regnum; | |
322 | else | |
323 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
324 | } |
325 | else if (reg >= 29 && reg <= 36) | |
326 | { | |
327 | /* MMX registers. */ | |
20a6ec49 | 328 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
329 | } |
330 | ||
331 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 332 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
333 | } |
334 | ||
c4fc7f1b MK |
335 | /* Convert SVR4 register number REG to the appropriate register number |
336 | used by GDB. */ | |
85540d8c | 337 | |
8201327c | 338 | static int |
d3f73121 | 339 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 340 | { |
20a6ec49 MD |
341 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
342 | ||
c4fc7f1b MK |
343 | /* This implements the GCC register map that tries to be compatible |
344 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
345 | ||
346 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
347 | numbers the floating point registers differently. */ |
348 | if (reg >= 0 && reg <= 9) | |
349 | { | |
acd5c798 | 350 | /* General-purpose registers. */ |
85540d8c MK |
351 | return reg; |
352 | } | |
353 | else if (reg >= 11 && reg <= 18) | |
354 | { | |
355 | /* Floating-point registers. */ | |
20a6ec49 | 356 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 357 | } |
c6f4c129 | 358 | else if (reg >= 21 && reg <= 36) |
85540d8c | 359 | { |
c4fc7f1b | 360 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 361 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
362 | } |
363 | ||
c6f4c129 JB |
364 | switch (reg) |
365 | { | |
20a6ec49 MD |
366 | case 37: return I387_FCTRL_REGNUM (tdep); |
367 | case 38: return I387_FSTAT_REGNUM (tdep); | |
368 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
369 | case 40: return I386_ES_REGNUM; |
370 | case 41: return I386_CS_REGNUM; | |
371 | case 42: return I386_SS_REGNUM; | |
372 | case 43: return I386_DS_REGNUM; | |
373 | case 44: return I386_FS_REGNUM; | |
374 | case 45: return I386_GS_REGNUM; | |
375 | } | |
376 | ||
85540d8c | 377 | /* This will hopefully provoke a warning. */ |
d3f73121 | 378 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 379 | } |
5716833c | 380 | |
fc338970 | 381 | \f |
917317f4 | 382 | |
fc338970 MK |
383 | /* This is the variable that is set with "set disassembly-flavor", and |
384 | its legitimate values. */ | |
53904c9e AC |
385 | static const char att_flavor[] = "att"; |
386 | static const char intel_flavor[] = "intel"; | |
40478521 | 387 | static const char *const valid_flavors[] = |
c5aa993b | 388 | { |
c906108c SS |
389 | att_flavor, |
390 | intel_flavor, | |
391 | NULL | |
392 | }; | |
53904c9e | 393 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 394 | \f |
c906108c | 395 | |
acd5c798 MK |
396 | /* Use the program counter to determine the contents and size of a |
397 | breakpoint instruction. Return a pointer to a string of bytes that | |
398 | encode a breakpoint instruction, store the length of the string in | |
399 | *LEN and optionally adjust *PC to point to the correct memory | |
400 | location for inserting the breakpoint. | |
c906108c | 401 | |
acd5c798 MK |
402 | On the i386 we have a single breakpoint that fits in a single byte |
403 | and can be inserted anywhere. | |
c906108c | 404 | |
acd5c798 | 405 | This function is 64-bit safe. */ |
63c0089f MK |
406 | |
407 | static const gdb_byte * | |
67d57894 | 408 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 409 | { |
63c0089f MK |
410 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
411 | ||
acd5c798 MK |
412 | *len = sizeof (break_insn); |
413 | return break_insn; | |
c906108c | 414 | } |
237fc4c9 PA |
415 | \f |
416 | /* Displaced instruction handling. */ | |
417 | ||
1903f0e6 DE |
418 | /* Skip the legacy instruction prefixes in INSN. |
419 | Not all prefixes are valid for any particular insn | |
420 | but we needn't care, the insn will fault if it's invalid. | |
421 | The result is a pointer to the first opcode byte, | |
422 | or NULL if we run off the end of the buffer. */ | |
423 | ||
424 | static gdb_byte * | |
425 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
426 | { | |
427 | gdb_byte *end = insn + max_len; | |
428 | ||
429 | while (insn < end) | |
430 | { | |
431 | switch (*insn) | |
432 | { | |
433 | case DATA_PREFIX_OPCODE: | |
434 | case ADDR_PREFIX_OPCODE: | |
435 | case CS_PREFIX_OPCODE: | |
436 | case DS_PREFIX_OPCODE: | |
437 | case ES_PREFIX_OPCODE: | |
438 | case FS_PREFIX_OPCODE: | |
439 | case GS_PREFIX_OPCODE: | |
440 | case SS_PREFIX_OPCODE: | |
441 | case LOCK_PREFIX_OPCODE: | |
442 | case REPE_PREFIX_OPCODE: | |
443 | case REPNE_PREFIX_OPCODE: | |
444 | ++insn; | |
445 | continue; | |
446 | default: | |
447 | return insn; | |
448 | } | |
449 | } | |
450 | ||
451 | return NULL; | |
452 | } | |
237fc4c9 PA |
453 | |
454 | static int | |
1903f0e6 | 455 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 456 | { |
1777feb0 | 457 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
458 | if (insn[0] == 0xea) |
459 | return 1; | |
460 | ||
461 | if (insn[0] == 0xff) | |
462 | { | |
1777feb0 | 463 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
464 | if ((insn[1] & 0x38) == 0x20) |
465 | return 1; | |
466 | ||
1777feb0 | 467 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
468 | if ((insn[1] & 0x38) == 0x28) |
469 | return 1; | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int | |
1903f0e6 | 476 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 477 | { |
1777feb0 | 478 | /* call far, absolute. */ |
237fc4c9 PA |
479 | if (insn[0] == 0x9a) |
480 | return 1; | |
481 | ||
482 | if (insn[0] == 0xff) | |
483 | { | |
1777feb0 | 484 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
485 | if ((insn[1] & 0x38) == 0x10) |
486 | return 1; | |
487 | ||
1777feb0 | 488 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
489 | if ((insn[1] & 0x38) == 0x18) |
490 | return 1; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
496 | static int | |
1903f0e6 | 497 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
498 | { |
499 | switch (insn[0]) | |
500 | { | |
1777feb0 | 501 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 502 | case 0xc3: /* ret near */ |
1777feb0 | 503 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
504 | case 0xcb: /* ret far */ |
505 | case 0xcf: /* iret */ | |
506 | return 1; | |
507 | ||
508 | default: | |
509 | return 0; | |
510 | } | |
511 | } | |
512 | ||
513 | static int | |
1903f0e6 | 514 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
515 | { |
516 | if (i386_absolute_call_p (insn)) | |
517 | return 1; | |
518 | ||
1777feb0 | 519 | /* call near, relative. */ |
237fc4c9 PA |
520 | if (insn[0] == 0xe8) |
521 | return 1; | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
237fc4c9 PA |
526 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
527 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 528 | |
237fc4c9 | 529 | static int |
b55078be | 530 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 531 | { |
9a7f938f JK |
532 | /* Is it 'int $0x80'? */ |
533 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
534 | /* Or is it 'sysenter'? */ | |
535 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
536 | /* Or is it 'syscall'? */ | |
537 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
538 | { |
539 | *lengthp = 2; | |
540 | return 1; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
b55078be DE |
546 | /* Some kernels may run one past a syscall insn, so we have to cope. |
547 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
548 | ||
549 | struct displaced_step_closure * | |
550 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
551 | CORE_ADDR from, CORE_ADDR to, | |
552 | struct regcache *regs) | |
553 | { | |
554 | size_t len = gdbarch_max_insn_length (gdbarch); | |
555 | gdb_byte *buf = xmalloc (len); | |
556 | ||
557 | read_memory (from, buf, len); | |
558 | ||
559 | /* GDB may get control back after the insn after the syscall. | |
560 | Presumably this is a kernel bug. | |
561 | If this is a syscall, make sure there's a nop afterwards. */ | |
562 | { | |
563 | int syscall_length; | |
564 | gdb_byte *insn; | |
565 | ||
566 | insn = i386_skip_prefixes (buf, len); | |
567 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
568 | insn[syscall_length] = NOP_OPCODE; | |
569 | } | |
570 | ||
571 | write_memory (to, buf, len); | |
572 | ||
573 | if (debug_displaced) | |
574 | { | |
575 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
576 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
577 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
578 | } | |
579 | ||
580 | return (struct displaced_step_closure *) buf; | |
581 | } | |
582 | ||
237fc4c9 PA |
583 | /* Fix up the state of registers and memory after having single-stepped |
584 | a displaced instruction. */ | |
1903f0e6 | 585 | |
237fc4c9 PA |
586 | void |
587 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
588 | struct displaced_step_closure *closure, | |
589 | CORE_ADDR from, CORE_ADDR to, | |
590 | struct regcache *regs) | |
591 | { | |
e17a4113 UW |
592 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
593 | ||
237fc4c9 PA |
594 | /* The offset we applied to the instruction's address. |
595 | This could well be negative (when viewed as a signed 32-bit | |
596 | value), but ULONGEST won't reflect that, so take care when | |
597 | applying it. */ | |
598 | ULONGEST insn_offset = to - from; | |
599 | ||
600 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
601 | copy of the instruction. */ | |
602 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
603 | /* The start of the insn, needed in case we see some prefixes. */ |
604 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
605 | |
606 | if (debug_displaced) | |
607 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 608 | "displaced: fixup (%s, %s), " |
237fc4c9 | 609 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
610 | paddress (gdbarch, from), paddress (gdbarch, to), |
611 | insn[0], insn[1]); | |
237fc4c9 PA |
612 | |
613 | /* The list of issues to contend with here is taken from | |
614 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
615 | Yay for Free Software! */ | |
616 | ||
617 | /* Relocate the %eip, if necessary. */ | |
618 | ||
1903f0e6 DE |
619 | /* The instruction recognizers we use assume any leading prefixes |
620 | have been skipped. */ | |
621 | { | |
622 | /* This is the size of the buffer in closure. */ | |
623 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
624 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
625 | /* If there are too many prefixes, just ignore the insn. | |
626 | It will fault when run. */ | |
627 | if (opcode != NULL) | |
628 | insn = opcode; | |
629 | } | |
630 | ||
237fc4c9 PA |
631 | /* Except in the case of absolute or indirect jump or call |
632 | instructions, or a return instruction, the new eip is relative to | |
633 | the displaced instruction; make it relative. Well, signal | |
634 | handler returns don't need relocation either, but we use the | |
635 | value of %eip to recognize those; see below. */ | |
636 | if (! i386_absolute_jmp_p (insn) | |
637 | && ! i386_absolute_call_p (insn) | |
638 | && ! i386_ret_p (insn)) | |
639 | { | |
640 | ULONGEST orig_eip; | |
b55078be | 641 | int insn_len; |
237fc4c9 PA |
642 | |
643 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
644 | ||
645 | /* A signal trampoline system call changes the %eip, resuming | |
646 | execution of the main program after the signal handler has | |
647 | returned. That makes them like 'return' instructions; we | |
648 | shouldn't relocate %eip. | |
649 | ||
650 | But most system calls don't, and we do need to relocate %eip. | |
651 | ||
652 | Our heuristic for distinguishing these cases: if stepping | |
653 | over the system call instruction left control directly after | |
654 | the instruction, the we relocate --- control almost certainly | |
655 | doesn't belong in the displaced copy. Otherwise, we assume | |
656 | the instruction has put control where it belongs, and leave | |
657 | it unrelocated. Goodness help us if there are PC-relative | |
658 | system calls. */ | |
659 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
660 | && orig_eip != to + (insn - insn_start) + insn_len |
661 | /* GDB can get control back after the insn after the syscall. | |
662 | Presumably this is a kernel bug. | |
663 | i386_displaced_step_copy_insn ensures its a nop, | |
664 | we add one to the length for it. */ | |
665 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
666 | { |
667 | if (debug_displaced) | |
668 | fprintf_unfiltered (gdb_stdlog, | |
669 | "displaced: syscall changed %%eip; " | |
670 | "not relocating\n"); | |
671 | } | |
672 | else | |
673 | { | |
674 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
675 | ||
1903f0e6 DE |
676 | /* If we just stepped over a breakpoint insn, we don't backup |
677 | the pc on purpose; this is to match behaviour without | |
678 | stepping. */ | |
237fc4c9 PA |
679 | |
680 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
681 | ||
682 | if (debug_displaced) | |
683 | fprintf_unfiltered (gdb_stdlog, | |
684 | "displaced: " | |
5af949e3 UW |
685 | "relocated %%eip from %s to %s\n", |
686 | paddress (gdbarch, orig_eip), | |
687 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
688 | } |
689 | } | |
690 | ||
691 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
692 | pushed value, and should be cleared. We'll leave this for later, | |
693 | since GDB already messes up the TF flag when stepping over a | |
694 | pushfl. */ | |
695 | ||
696 | /* If the instruction was a call, the return address now atop the | |
697 | stack is the address following the copied instruction. We need | |
698 | to make it the address following the original instruction. */ | |
699 | if (i386_call_p (insn)) | |
700 | { | |
701 | ULONGEST esp; | |
702 | ULONGEST retaddr; | |
703 | const ULONGEST retaddr_len = 4; | |
704 | ||
705 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 706 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 707 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 708 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
709 | |
710 | if (debug_displaced) | |
711 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
712 | "displaced: relocated return addr at %s to %s\n", |
713 | paddress (gdbarch, esp), | |
714 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
715 | } |
716 | } | |
dde08ee1 PA |
717 | |
718 | static void | |
719 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
720 | { | |
721 | target_write_memory (*to, buf, len); | |
722 | *to += len; | |
723 | } | |
724 | ||
725 | static void | |
726 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
727 | CORE_ADDR *to, CORE_ADDR oldloc) | |
728 | { | |
729 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
730 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
731 | int offset = 0, rel32, newrel; | |
732 | int insn_length; | |
733 | gdb_byte *insn = buf; | |
734 | ||
735 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
736 | ||
737 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
738 | I386_MAX_INSN_LEN, oldloc); | |
739 | ||
740 | /* Get past the prefixes. */ | |
741 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
742 | ||
743 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
744 | the address pushed being the location where the original call in | |
745 | the user program would return to. */ | |
746 | if (insn[0] == 0xe8) | |
747 | { | |
748 | gdb_byte push_buf[16]; | |
749 | unsigned int ret_addr; | |
750 | ||
751 | /* Where "ret" in the original code will return to. */ | |
752 | ret_addr = oldloc + insn_length; | |
1777feb0 | 753 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 754 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
755 | /* Push the push. */ |
756 | append_insns (to, 5, push_buf); | |
757 | ||
758 | /* Convert the relative call to a relative jump. */ | |
759 | insn[0] = 0xe9; | |
760 | ||
761 | /* Adjust the destination offset. */ | |
762 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
763 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
764 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
765 | ||
766 | if (debug_displaced) | |
767 | fprintf_unfiltered (gdb_stdlog, | |
768 | "Adjusted insn rel32=%s at %s to" | |
769 | " rel32=%s at %s\n", | |
770 | hex_string (rel32), paddress (gdbarch, oldloc), | |
771 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
772 | |
773 | /* Write the adjusted jump into its displaced location. */ | |
774 | append_insns (to, 5, insn); | |
775 | return; | |
776 | } | |
777 | ||
778 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
779 | handled above. */ | |
780 | if (insn[0] == 0xe9) | |
781 | offset = 1; | |
782 | /* Adjust conditional jumps. */ | |
783 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
784 | offset = 2; | |
785 | ||
786 | if (offset) | |
787 | { | |
788 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
789 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 790 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
791 | if (debug_displaced) |
792 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
793 | "Adjusted insn rel32=%s at %s to" |
794 | " rel32=%s at %s\n", | |
dde08ee1 PA |
795 | hex_string (rel32), paddress (gdbarch, oldloc), |
796 | hex_string (newrel), paddress (gdbarch, *to)); | |
797 | } | |
798 | ||
799 | /* Write the adjusted instructions into their displaced | |
800 | location. */ | |
801 | append_insns (to, insn_length, buf); | |
802 | } | |
803 | ||
fc338970 | 804 | \f |
acd5c798 MK |
805 | #ifdef I386_REGNO_TO_SYMMETRY |
806 | #error "The Sequent Symmetry is no longer supported." | |
807 | #endif | |
c906108c | 808 | |
acd5c798 MK |
809 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
810 | and %esp "belong" to the calling function. Therefore these | |
811 | registers should be saved if they're going to be modified. */ | |
c906108c | 812 | |
acd5c798 MK |
813 | /* The maximum number of saved registers. This should include all |
814 | registers mentioned above, and %eip. */ | |
a3386186 | 815 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
816 | |
817 | struct i386_frame_cache | |
c906108c | 818 | { |
acd5c798 MK |
819 | /* Base address. */ |
820 | CORE_ADDR base; | |
8fbca658 | 821 | int base_p; |
772562f8 | 822 | LONGEST sp_offset; |
acd5c798 MK |
823 | CORE_ADDR pc; |
824 | ||
fd13a04a AC |
825 | /* Saved registers. */ |
826 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 827 | CORE_ADDR saved_sp; |
e0c62198 | 828 | int saved_sp_reg; |
acd5c798 MK |
829 | int pc_in_eax; |
830 | ||
831 | /* Stack space reserved for local variables. */ | |
832 | long locals; | |
833 | }; | |
834 | ||
835 | /* Allocate and initialize a frame cache. */ | |
836 | ||
837 | static struct i386_frame_cache * | |
fd13a04a | 838 | i386_alloc_frame_cache (void) |
acd5c798 MK |
839 | { |
840 | struct i386_frame_cache *cache; | |
841 | int i; | |
842 | ||
843 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
844 | ||
845 | /* Base address. */ | |
8fbca658 | 846 | cache->base_p = 0; |
acd5c798 MK |
847 | cache->base = 0; |
848 | cache->sp_offset = -4; | |
849 | cache->pc = 0; | |
850 | ||
fd13a04a AC |
851 | /* Saved registers. We initialize these to -1 since zero is a valid |
852 | offset (that's where %ebp is supposed to be stored). */ | |
853 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
854 | cache->saved_regs[i] = -1; | |
acd5c798 | 855 | cache->saved_sp = 0; |
e0c62198 | 856 | cache->saved_sp_reg = -1; |
acd5c798 MK |
857 | cache->pc_in_eax = 0; |
858 | ||
859 | /* Frameless until proven otherwise. */ | |
860 | cache->locals = -1; | |
861 | ||
862 | return cache; | |
863 | } | |
c906108c | 864 | |
acd5c798 MK |
865 | /* If the instruction at PC is a jump, return the address of its |
866 | target. Otherwise, return PC. */ | |
c906108c | 867 | |
acd5c798 | 868 | static CORE_ADDR |
e17a4113 | 869 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 870 | { |
e17a4113 | 871 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 872 | gdb_byte op; |
acd5c798 MK |
873 | long delta = 0; |
874 | int data16 = 0; | |
c906108c | 875 | |
3dcabaa8 MS |
876 | if (target_read_memory (pc, &op, 1)) |
877 | return pc; | |
878 | ||
acd5c798 | 879 | if (op == 0x66) |
c906108c | 880 | { |
c906108c | 881 | data16 = 1; |
e17a4113 | 882 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
883 | } |
884 | ||
acd5c798 | 885 | switch (op) |
c906108c SS |
886 | { |
887 | case 0xe9: | |
fc338970 | 888 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
889 | if (data16) |
890 | { | |
e17a4113 | 891 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 892 | |
fc338970 MK |
893 | /* Include the size of the jmp instruction (including the |
894 | 0x66 prefix). */ | |
acd5c798 | 895 | delta += 4; |
c906108c SS |
896 | } |
897 | else | |
898 | { | |
e17a4113 | 899 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 900 | |
acd5c798 MK |
901 | /* Include the size of the jmp instruction. */ |
902 | delta += 5; | |
c906108c SS |
903 | } |
904 | break; | |
905 | case 0xeb: | |
fc338970 | 906 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 907 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 908 | |
acd5c798 | 909 | delta += data16 + 2; |
c906108c SS |
910 | break; |
911 | } | |
c906108c | 912 | |
acd5c798 MK |
913 | return pc + delta; |
914 | } | |
fc338970 | 915 | |
acd5c798 MK |
916 | /* Check whether PC points at a prologue for a function returning a |
917 | structure or union. If so, it updates CACHE and returns the | |
918 | address of the first instruction after the code sequence that | |
919 | removes the "hidden" argument from the stack or CURRENT_PC, | |
920 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 921 | |
acd5c798 MK |
922 | static CORE_ADDR |
923 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
924 | struct i386_frame_cache *cache) | |
c906108c | 925 | { |
acd5c798 MK |
926 | /* Functions that return a structure or union start with: |
927 | ||
928 | popl %eax 0x58 | |
929 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
930 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
931 | ||
932 | (the System V compiler puts out the second `xchg' instruction, | |
933 | and the assembler doesn't try to optimize it, so the 'sib' form | |
934 | gets generated). This sequence is used to get the address of the | |
935 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
936 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
937 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
938 | gdb_byte buf[4]; | |
939 | gdb_byte op; | |
c906108c | 940 | |
acd5c798 MK |
941 | if (current_pc <= pc) |
942 | return pc; | |
943 | ||
3dcabaa8 MS |
944 | if (target_read_memory (pc, &op, 1)) |
945 | return pc; | |
c906108c | 946 | |
acd5c798 MK |
947 | if (op != 0x58) /* popl %eax */ |
948 | return pc; | |
c906108c | 949 | |
3dcabaa8 MS |
950 | if (target_read_memory (pc + 1, buf, 4)) |
951 | return pc; | |
952 | ||
acd5c798 MK |
953 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
954 | return pc; | |
c906108c | 955 | |
acd5c798 | 956 | if (current_pc == pc) |
c906108c | 957 | { |
acd5c798 MK |
958 | cache->sp_offset += 4; |
959 | return current_pc; | |
c906108c SS |
960 | } |
961 | ||
acd5c798 | 962 | if (current_pc == pc + 1) |
c906108c | 963 | { |
acd5c798 MK |
964 | cache->pc_in_eax = 1; |
965 | return current_pc; | |
966 | } | |
967 | ||
968 | if (buf[1] == proto1[1]) | |
969 | return pc + 4; | |
970 | else | |
971 | return pc + 5; | |
972 | } | |
973 | ||
974 | static CORE_ADDR | |
975 | i386_skip_probe (CORE_ADDR pc) | |
976 | { | |
977 | /* A function may start with | |
fc338970 | 978 | |
acd5c798 MK |
979 | pushl constant |
980 | call _probe | |
981 | addl $4, %esp | |
fc338970 | 982 | |
acd5c798 MK |
983 | followed by |
984 | ||
985 | pushl %ebp | |
fc338970 | 986 | |
acd5c798 | 987 | etc. */ |
63c0089f MK |
988 | gdb_byte buf[8]; |
989 | gdb_byte op; | |
fc338970 | 990 | |
3dcabaa8 MS |
991 | if (target_read_memory (pc, &op, 1)) |
992 | return pc; | |
acd5c798 MK |
993 | |
994 | if (op == 0x68 || op == 0x6a) | |
995 | { | |
996 | int delta; | |
c906108c | 997 | |
acd5c798 MK |
998 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
999 | four-byte operand, depending on the opcode. */ | |
c906108c | 1000 | if (op == 0x68) |
acd5c798 | 1001 | delta = 5; |
c906108c | 1002 | else |
acd5c798 | 1003 | delta = 2; |
c906108c | 1004 | |
acd5c798 MK |
1005 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1006 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1007 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1008 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1009 | pc += delta + sizeof (buf); |
c906108c SS |
1010 | } |
1011 | ||
acd5c798 MK |
1012 | return pc; |
1013 | } | |
1014 | ||
92dd43fa MK |
1015 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1016 | stack pointer. Check whether PC points to such code, and update | |
1017 | CACHE accordingly. Return the first instruction after the code | |
1018 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1019 | recognize the code, return PC. */ | |
1020 | ||
1021 | static CORE_ADDR | |
1022 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1023 | struct i386_frame_cache *cache) | |
1024 | { | |
e0c62198 L |
1025 | /* There are 2 code sequences to re-align stack before the frame |
1026 | gets set up: | |
1027 | ||
1028 | 1. Use a caller-saved saved register: | |
1029 | ||
1030 | leal 4(%esp), %reg | |
1031 | andl $-XXX, %esp | |
1032 | pushl -4(%reg) | |
1033 | ||
1034 | 2. Use a callee-saved saved register: | |
1035 | ||
1036 | pushl %reg | |
1037 | leal 8(%esp), %reg | |
1038 | andl $-XXX, %esp | |
1039 | pushl -4(%reg) | |
1040 | ||
1041 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1042 | ||
1043 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1044 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1045 | */ | |
1046 | ||
1047 | gdb_byte buf[14]; | |
1048 | int reg; | |
1049 | int offset, offset_and; | |
1050 | static int regnums[8] = { | |
1051 | I386_EAX_REGNUM, /* %eax */ | |
1052 | I386_ECX_REGNUM, /* %ecx */ | |
1053 | I386_EDX_REGNUM, /* %edx */ | |
1054 | I386_EBX_REGNUM, /* %ebx */ | |
1055 | I386_ESP_REGNUM, /* %esp */ | |
1056 | I386_EBP_REGNUM, /* %ebp */ | |
1057 | I386_ESI_REGNUM, /* %esi */ | |
1058 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1059 | }; |
92dd43fa | 1060 | |
e0c62198 L |
1061 | if (target_read_memory (pc, buf, sizeof buf)) |
1062 | return pc; | |
1063 | ||
1064 | /* Check caller-saved saved register. The first instruction has | |
1065 | to be "leal 4(%esp), %reg". */ | |
1066 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1067 | { | |
1068 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1069 | if ((buf[1] & 0xc7) != 0x44) | |
1070 | return pc; | |
1071 | ||
1072 | /* REG has register number. */ | |
1073 | reg = (buf[1] >> 3) & 7; | |
1074 | offset = 4; | |
1075 | } | |
1076 | else | |
1077 | { | |
1078 | /* Check callee-saved saved register. The first instruction | |
1079 | has to be "pushl %reg". */ | |
1080 | if ((buf[0] & 0xf8) != 0x50) | |
1081 | return pc; | |
1082 | ||
1083 | /* Get register. */ | |
1084 | reg = buf[0] & 0x7; | |
1085 | ||
1086 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1087 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1088 | return pc; | |
1089 | ||
1090 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1091 | if ((buf[2] & 0xc7) != 0x44) | |
1092 | return pc; | |
1093 | ||
1094 | /* REG has register number. Registers in pushl and leal have to | |
1095 | be the same. */ | |
1096 | if (reg != ((buf[2] >> 3) & 7)) | |
1097 | return pc; | |
1098 | ||
1099 | offset = 5; | |
1100 | } | |
1101 | ||
1102 | /* Rigister can't be %esp nor %ebp. */ | |
1103 | if (reg == 4 || reg == 5) | |
1104 | return pc; | |
1105 | ||
1106 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1107 | if (buf[offset + 1] != 0xe4 | |
1108 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1109 | return pc; | |
1110 | ||
1111 | offset_and = offset; | |
1112 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1113 | ||
1114 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1115 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1116 | if (buf[offset] != 0xff | |
1117 | || buf[offset + 2] != 0xfc | |
1118 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1119 | return pc; | |
1120 | ||
1121 | /* R/M has register. Registers in leal and pushl have to be the | |
1122 | same. */ | |
1123 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1124 | return pc; |
1125 | ||
e0c62198 L |
1126 | if (current_pc > pc + offset_and) |
1127 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1128 | |
e0c62198 | 1129 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1130 | } |
1131 | ||
37bdc87e | 1132 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1133 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1134 | |
1135 | /* Instruction description. */ | |
1136 | struct i386_insn | |
1137 | { | |
1138 | size_t len; | |
237fc4c9 PA |
1139 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1140 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1141 | }; |
1142 | ||
a3fcb948 | 1143 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1144 | |
a3fcb948 JG |
1145 | static int |
1146 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1147 | { |
63c0089f | 1148 | gdb_byte op; |
37bdc87e | 1149 | |
3dcabaa8 | 1150 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1151 | return 0; |
37bdc87e | 1152 | |
a3fcb948 | 1153 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1154 | { |
a3fcb948 JG |
1155 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1156 | int insn_matched = 1; | |
1157 | size_t i; | |
37bdc87e | 1158 | |
a3fcb948 JG |
1159 | gdb_assert (pattern.len > 1); |
1160 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1161 | |
a3fcb948 JG |
1162 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1163 | return 0; | |
613e8135 | 1164 | |
a3fcb948 JG |
1165 | for (i = 1; i < pattern.len; i++) |
1166 | { | |
1167 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1168 | insn_matched = 0; | |
37bdc87e | 1169 | } |
a3fcb948 JG |
1170 | return insn_matched; |
1171 | } | |
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1176 | the first instruction description that matches. Otherwise, return | |
1177 | NULL. */ | |
1178 | ||
1179 | static struct i386_insn * | |
1180 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1181 | { | |
1182 | struct i386_insn *pattern; | |
1183 | ||
1184 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1185 | { | |
1186 | if (i386_match_pattern (pc, *pattern)) | |
1187 | return pattern; | |
37bdc87e MK |
1188 | } |
1189 | ||
1190 | return NULL; | |
1191 | } | |
1192 | ||
a3fcb948 JG |
1193 | /* Return whether PC points inside a sequence of instructions that |
1194 | matches INSN_PATTERNS. */ | |
1195 | ||
1196 | static int | |
1197 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1198 | { | |
1199 | CORE_ADDR current_pc; | |
1200 | int ix, i; | |
a3fcb948 JG |
1201 | struct i386_insn *insn; |
1202 | ||
1203 | insn = i386_match_insn (pc, insn_patterns); | |
1204 | if (insn == NULL) | |
1205 | return 0; | |
1206 | ||
8bbdd3f4 | 1207 | current_pc = pc; |
a3fcb948 JG |
1208 | ix = insn - insn_patterns; |
1209 | for (i = ix - 1; i >= 0; i--) | |
1210 | { | |
8bbdd3f4 MK |
1211 | current_pc -= insn_patterns[i].len; |
1212 | ||
a3fcb948 JG |
1213 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1214 | return 0; | |
a3fcb948 JG |
1215 | } |
1216 | ||
1217 | current_pc = pc + insn->len; | |
1218 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1219 | { | |
1220 | if (!i386_match_pattern (current_pc, *insn)) | |
1221 | return 0; | |
1222 | ||
1223 | current_pc += insn->len; | |
1224 | } | |
1225 | ||
1226 | return 1; | |
1227 | } | |
1228 | ||
37bdc87e MK |
1229 | /* Some special instructions that might be migrated by GCC into the |
1230 | part of the prologue that sets up the new stack frame. Because the | |
1231 | stack frame hasn't been setup yet, no registers have been saved | |
1232 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1233 | touched. */ | |
1234 | ||
1235 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1236 | { | |
1777feb0 | 1237 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1238 | |
1239 | ??? Should we handle 16-bit operand-sizes here? */ | |
1240 | ||
1241 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1242 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1243 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1244 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1245 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1246 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1247 | { 5, { 0xb8 }, { 0xfe } }, | |
1248 | /* `movl imm32, %edx' */ | |
1249 | { 5, { 0xba }, { 0xff } }, | |
1250 | ||
1251 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1252 | encoding for `mov m32, %eax'. | |
1253 | ||
1254 | ??? Should we handle SIB adressing here? | |
1255 | ??? Should we handle 16-bit operand-sizes here? */ | |
1256 | ||
1257 | /* `movl m32, %eax' */ | |
1258 | { 5, { 0xa1 }, { 0xff } }, | |
1259 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1260 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1261 | /* `movl m32, %edx' */ | |
1262 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1263 | ||
1264 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1265 | Because of the symmetry, there are actually two ways to encode | |
1266 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1267 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1268 | ||
1269 | /* `subl %eax, %eax' */ | |
1270 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1271 | /* `subl %ecx, %ecx' */ | |
1272 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1273 | /* `subl %edx, %edx' */ | |
1274 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1275 | /* `xorl %eax, %eax' */ | |
1276 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1277 | /* `xorl %ecx, %ecx' */ | |
1278 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1279 | /* `xorl %edx, %edx' */ | |
1280 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1281 | { 0 } | |
1282 | }; | |
1283 | ||
e11481da PM |
1284 | |
1285 | /* Check whether PC points to a no-op instruction. */ | |
1286 | static CORE_ADDR | |
1287 | i386_skip_noop (CORE_ADDR pc) | |
1288 | { | |
1289 | gdb_byte op; | |
1290 | int check = 1; | |
1291 | ||
3dcabaa8 MS |
1292 | if (target_read_memory (pc, &op, 1)) |
1293 | return pc; | |
e11481da PM |
1294 | |
1295 | while (check) | |
1296 | { | |
1297 | check = 0; | |
1298 | /* Ignore `nop' instruction. */ | |
1299 | if (op == 0x90) | |
1300 | { | |
1301 | pc += 1; | |
3dcabaa8 MS |
1302 | if (target_read_memory (pc, &op, 1)) |
1303 | return pc; | |
e11481da PM |
1304 | check = 1; |
1305 | } | |
1306 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1307 | Microsoft system dlls often start with | |
1308 | a `mov %edi,%edi' instruction. | |
1309 | The 5 bytes before the function start are | |
1310 | filled with `nop' instructions. | |
1311 | This pattern can be used for hot-patching: | |
1312 | The `mov %edi, %edi' instruction can be replaced by a | |
1313 | near jump to the location of the 5 `nop' instructions | |
1314 | which can be replaced by a 32-bit jump to anywhere | |
1315 | in the 32-bit address space. */ | |
1316 | ||
1317 | else if (op == 0x8b) | |
1318 | { | |
3dcabaa8 MS |
1319 | if (target_read_memory (pc + 1, &op, 1)) |
1320 | return pc; | |
1321 | ||
e11481da PM |
1322 | if (op == 0xff) |
1323 | { | |
1324 | pc += 2; | |
3dcabaa8 MS |
1325 | if (target_read_memory (pc, &op, 1)) |
1326 | return pc; | |
1327 | ||
e11481da PM |
1328 | check = 1; |
1329 | } | |
1330 | } | |
1331 | } | |
1332 | return pc; | |
1333 | } | |
1334 | ||
acd5c798 MK |
1335 | /* Check whether PC points at a code that sets up a new stack frame. |
1336 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1337 | instruction after the sequence that sets up the frame or LIMIT, |
1338 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1339 | |
1340 | static CORE_ADDR | |
e17a4113 UW |
1341 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1342 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1343 | struct i386_frame_cache *cache) |
1344 | { | |
e17a4113 | 1345 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1346 | struct i386_insn *insn; |
63c0089f | 1347 | gdb_byte op; |
26604a34 | 1348 | int skip = 0; |
acd5c798 | 1349 | |
37bdc87e MK |
1350 | if (limit <= pc) |
1351 | return limit; | |
acd5c798 | 1352 | |
3dcabaa8 MS |
1353 | if (target_read_memory (pc, &op, 1)) |
1354 | return pc; | |
acd5c798 | 1355 | |
c906108c | 1356 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1357 | { |
acd5c798 MK |
1358 | /* Take into account that we've executed the `pushl %ebp' that |
1359 | starts this instruction sequence. */ | |
fd13a04a | 1360 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1361 | cache->sp_offset += 4; |
37bdc87e | 1362 | pc++; |
acd5c798 MK |
1363 | |
1364 | /* If that's all, return now. */ | |
37bdc87e MK |
1365 | if (limit <= pc) |
1366 | return limit; | |
26604a34 | 1367 | |
b4632131 | 1368 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1369 | GCC into the prologue and skip them. At this point in the |
1370 | prologue, code should only touch the scratch registers %eax, | |
1371 | %ecx and %edx, so while the number of posibilities is sheer, | |
1372 | it is limited. | |
5daa5b4e | 1373 | |
26604a34 MK |
1374 | Make sure we only skip these instructions if we later see the |
1375 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1376 | while (pc + skip < limit) |
26604a34 | 1377 | { |
37bdc87e MK |
1378 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1379 | if (insn == NULL) | |
1380 | break; | |
b4632131 | 1381 | |
37bdc87e | 1382 | skip += insn->len; |
26604a34 MK |
1383 | } |
1384 | ||
37bdc87e MK |
1385 | /* If that's all, return now. */ |
1386 | if (limit <= pc + skip) | |
1387 | return limit; | |
1388 | ||
3dcabaa8 MS |
1389 | if (target_read_memory (pc + skip, &op, 1)) |
1390 | return pc + skip; | |
37bdc87e | 1391 | |
30f8135b YQ |
1392 | /* The i386 prologue looks like |
1393 | ||
1394 | push %ebp | |
1395 | mov %esp,%ebp | |
1396 | sub $0x10,%esp | |
1397 | ||
1398 | and a different prologue can be generated for atom. | |
1399 | ||
1400 | push %ebp | |
1401 | lea (%esp),%ebp | |
1402 | lea -0x10(%esp),%esp | |
1403 | ||
1404 | We handle both of them here. */ | |
1405 | ||
acd5c798 | 1406 | switch (op) |
c906108c | 1407 | { |
30f8135b | 1408 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1409 | case 0x8b: |
e17a4113 UW |
1410 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1411 | != 0xec) | |
37bdc87e | 1412 | return pc; |
30f8135b | 1413 | pc += (skip + 2); |
c906108c SS |
1414 | break; |
1415 | case 0x89: | |
e17a4113 UW |
1416 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1417 | != 0xe5) | |
37bdc87e | 1418 | return pc; |
30f8135b YQ |
1419 | pc += (skip + 2); |
1420 | break; | |
1421 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
1422 | if (read_memory_unsigned_integer (pc + skip + 1, 2, byte_order) | |
1423 | != 0x242c) | |
1424 | return pc; | |
1425 | pc += (skip + 3); | |
c906108c SS |
1426 | break; |
1427 | default: | |
37bdc87e | 1428 | return pc; |
c906108c | 1429 | } |
acd5c798 | 1430 | |
26604a34 MK |
1431 | /* OK, we actually have a frame. We just don't know how large |
1432 | it is yet. Set its size to zero. We'll adjust it if | |
1433 | necessary. We also now commit to skipping the special | |
1434 | instructions mentioned before. */ | |
acd5c798 MK |
1435 | cache->locals = 0; |
1436 | ||
1437 | /* If that's all, return now. */ | |
37bdc87e MK |
1438 | if (limit <= pc) |
1439 | return limit; | |
acd5c798 | 1440 | |
fc338970 MK |
1441 | /* Check for stack adjustment |
1442 | ||
acd5c798 | 1443 | subl $XXX, %esp |
30f8135b YQ |
1444 | or |
1445 | lea -XXX(%esp),%esp | |
fc338970 | 1446 | |
fd35795f | 1447 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1448 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1449 | if (target_read_memory (pc, &op, 1)) |
1450 | return pc; | |
c906108c SS |
1451 | if (op == 0x83) |
1452 | { | |
fd35795f | 1453 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1454 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1455 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1456 | return pc; |
acd5c798 | 1457 | |
37bdc87e MK |
1458 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1459 | make sense to be negative). */ | |
e17a4113 | 1460 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1461 | return pc + 3; |
c906108c SS |
1462 | } |
1463 | else if (op == 0x81) | |
1464 | { | |
fd35795f | 1465 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1466 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1467 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1468 | return pc; |
acd5c798 | 1469 | |
fd35795f | 1470 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1471 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1472 | return pc + 6; |
c906108c | 1473 | } |
30f8135b YQ |
1474 | else if (op == 0x8d) |
1475 | { | |
1476 | /* The ModR/M byte is 0x64. */ | |
1477 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0x64) | |
1478 | return pc; | |
1479 | /* 'lea' with 8-bit displacement. */ | |
1480 | cache->locals = -1 * read_memory_integer (pc + 3, 1, byte_order); | |
1481 | return pc + 4; | |
1482 | } | |
c906108c SS |
1483 | else |
1484 | { | |
30f8135b | 1485 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1486 | return pc; |
c906108c SS |
1487 | } |
1488 | } | |
37bdc87e | 1489 | else if (op == 0xc8) /* enter */ |
c906108c | 1490 | { |
e17a4113 | 1491 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1492 | return pc + 4; |
c906108c | 1493 | } |
21d0e8a4 | 1494 | |
acd5c798 | 1495 | return pc; |
21d0e8a4 MK |
1496 | } |
1497 | ||
acd5c798 MK |
1498 | /* Check whether PC points at code that saves registers on the stack. |
1499 | If so, it updates CACHE and returns the address of the first | |
1500 | instruction after the register saves or CURRENT_PC, whichever is | |
1501 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1502 | |
1503 | static CORE_ADDR | |
acd5c798 MK |
1504 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1505 | struct i386_frame_cache *cache) | |
6bff26de | 1506 | { |
99ab4326 | 1507 | CORE_ADDR offset = 0; |
63c0089f | 1508 | gdb_byte op; |
99ab4326 | 1509 | int i; |
c0d1d883 | 1510 | |
99ab4326 MK |
1511 | if (cache->locals > 0) |
1512 | offset -= cache->locals; | |
1513 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1514 | { | |
3dcabaa8 MS |
1515 | if (target_read_memory (pc, &op, 1)) |
1516 | return pc; | |
99ab4326 MK |
1517 | if (op < 0x50 || op > 0x57) |
1518 | break; | |
0d17c81d | 1519 | |
99ab4326 MK |
1520 | offset -= 4; |
1521 | cache->saved_regs[op - 0x50] = offset; | |
1522 | cache->sp_offset += 4; | |
1523 | pc++; | |
6bff26de MK |
1524 | } |
1525 | ||
acd5c798 | 1526 | return pc; |
22797942 AC |
1527 | } |
1528 | ||
acd5c798 MK |
1529 | /* Do a full analysis of the prologue at PC and update CACHE |
1530 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1531 | address where the analysis stopped. | |
ed84f6c1 | 1532 | |
fc338970 MK |
1533 | We handle these cases: |
1534 | ||
1535 | The startup sequence can be at the start of the function, or the | |
1536 | function can start with a branch to startup code at the end. | |
1537 | ||
1538 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1539 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1540 | once used in the System V compiler). | |
1541 | ||
1542 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1543 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1544 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1545 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1546 | |
1547 | Next, the registers used by this function are pushed. With the | |
1548 | System V compiler they will always be in the order: %edi, %esi, | |
1549 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1550 | restore %eax); however, the code below is willing to see the pushes | |
1551 | in any order, and will handle up to 8 of them. | |
1552 | ||
1553 | If the setup sequence is at the end of the function, then the next | |
1554 | instruction will be a branch back to the start. */ | |
c906108c | 1555 | |
acd5c798 | 1556 | static CORE_ADDR |
e17a4113 UW |
1557 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1558 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1559 | struct i386_frame_cache *cache) |
c906108c | 1560 | { |
e11481da | 1561 | pc = i386_skip_noop (pc); |
e17a4113 | 1562 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1563 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1564 | pc = i386_skip_probe (pc); | |
92dd43fa | 1565 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1566 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1567 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1568 | } |
1569 | ||
fc338970 | 1570 | /* Return PC of first real instruction. */ |
c906108c | 1571 | |
3a1e71e3 | 1572 | static CORE_ADDR |
6093d2eb | 1573 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1574 | { |
e17a4113 UW |
1575 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1576 | ||
63c0089f | 1577 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1578 | { |
1579 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1580 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1581 | }; |
acd5c798 MK |
1582 | struct i386_frame_cache cache; |
1583 | CORE_ADDR pc; | |
63c0089f | 1584 | gdb_byte op; |
acd5c798 | 1585 | int i; |
56bf0743 | 1586 | CORE_ADDR func_addr; |
4e879fc2 | 1587 | |
56bf0743 KB |
1588 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1589 | { | |
1590 | CORE_ADDR post_prologue_pc | |
1591 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1592 | struct symtab *s = find_pc_symtab (func_addr); | |
1593 | ||
1594 | /* Clang always emits a line note before the prologue and another | |
1595 | one after. We trust clang to emit usable line notes. */ | |
1596 | if (post_prologue_pc | |
1597 | && (s != NULL | |
1598 | && s->producer != NULL | |
1599 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) | |
1600 | return max (start_pc, post_prologue_pc); | |
1601 | } | |
1602 | ||
e0f33b1f | 1603 | cache.locals = -1; |
e17a4113 | 1604 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1605 | if (cache.locals < 0) |
1606 | return start_pc; | |
c5aa993b | 1607 | |
acd5c798 | 1608 | /* Found valid frame setup. */ |
c906108c | 1609 | |
fc338970 MK |
1610 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1611 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1612 | %ebx: |
1613 | ||
fc338970 MK |
1614 | call 0x0 |
1615 | popl %ebx | |
1616 | movl %ebx,x(%ebp) (optional) | |
1617 | addl y,%ebx | |
1618 | ||
c906108c SS |
1619 | This code is with the rest of the prologue (at the end of the |
1620 | function), so we have to skip it to get to the first real | |
1621 | instruction at the start of the function. */ | |
c5aa993b | 1622 | |
c906108c SS |
1623 | for (i = 0; i < 6; i++) |
1624 | { | |
3dcabaa8 MS |
1625 | if (target_read_memory (pc + i, &op, 1)) |
1626 | return pc; | |
1627 | ||
c5aa993b | 1628 | if (pic_pat[i] != op) |
c906108c SS |
1629 | break; |
1630 | } | |
1631 | if (i == 6) | |
1632 | { | |
acd5c798 MK |
1633 | int delta = 6; |
1634 | ||
3dcabaa8 MS |
1635 | if (target_read_memory (pc + delta, &op, 1)) |
1636 | return pc; | |
c906108c | 1637 | |
c5aa993b | 1638 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1639 | { |
e17a4113 | 1640 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1641 | |
fc338970 | 1642 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1643 | delta += 3; |
fc338970 | 1644 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1645 | delta += 6; |
fc338970 | 1646 | else /* Unexpected instruction. */ |
acd5c798 MK |
1647 | delta = 0; |
1648 | ||
3dcabaa8 MS |
1649 | if (target_read_memory (pc + delta, &op, 1)) |
1650 | return pc; | |
c906108c | 1651 | } |
acd5c798 | 1652 | |
c5aa993b | 1653 | /* addl y,%ebx */ |
acd5c798 | 1654 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1655 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1656 | == 0xc3) | |
c906108c | 1657 | { |
acd5c798 | 1658 | pc += delta + 6; |
c906108c SS |
1659 | } |
1660 | } | |
c5aa993b | 1661 | |
e63bbc88 MK |
1662 | /* If the function starts with a branch (to startup code at the end) |
1663 | the last instruction should bring us back to the first | |
1664 | instruction of the real code. */ | |
e17a4113 UW |
1665 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1666 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1667 | |
1668 | return pc; | |
c906108c SS |
1669 | } |
1670 | ||
4309257c PM |
1671 | /* Check that the code pointed to by PC corresponds to a call to |
1672 | __main, skip it if so. Return PC otherwise. */ | |
1673 | ||
1674 | CORE_ADDR | |
1675 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1676 | { | |
e17a4113 | 1677 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1678 | gdb_byte op; |
1679 | ||
3dcabaa8 MS |
1680 | if (target_read_memory (pc, &op, 1)) |
1681 | return pc; | |
4309257c PM |
1682 | if (op == 0xe8) |
1683 | { | |
1684 | gdb_byte buf[4]; | |
1685 | ||
1686 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1687 | { | |
1688 | /* Make sure address is computed correctly as a 32bit | |
1689 | integer even if CORE_ADDR is 64 bit wide. */ | |
1690 | struct minimal_symbol *s; | |
e17a4113 | 1691 | CORE_ADDR call_dest; |
4309257c | 1692 | |
e17a4113 | 1693 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1694 | call_dest = call_dest & 0xffffffffU; |
1695 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1696 | if (s != NULL | |
1697 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1698 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1699 | pc += 5; | |
1700 | } | |
1701 | } | |
1702 | ||
1703 | return pc; | |
1704 | } | |
1705 | ||
acd5c798 | 1706 | /* This function is 64-bit safe. */ |
93924b6b | 1707 | |
acd5c798 MK |
1708 | static CORE_ADDR |
1709 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1710 | { |
63c0089f | 1711 | gdb_byte buf[8]; |
acd5c798 | 1712 | |
875f8d0e | 1713 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1714 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1715 | } |
acd5c798 | 1716 | \f |
93924b6b | 1717 | |
acd5c798 | 1718 | /* Normal frames. */ |
c5aa993b | 1719 | |
8fbca658 PA |
1720 | static void |
1721 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1722 | struct i386_frame_cache *cache) | |
a7769679 | 1723 | { |
e17a4113 UW |
1724 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1725 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1726 | gdb_byte buf[4]; |
acd5c798 MK |
1727 | int i; |
1728 | ||
8fbca658 | 1729 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1730 | |
1731 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1732 | which holds the base address for the current stack frame. | |
1733 | However, for functions that don't need it, the frame pointer is | |
1734 | optional. For these "frameless" functions the frame pointer is | |
1735 | actually the frame pointer of the calling frame. Signal | |
1736 | trampolines are just a special case of a "frameless" function. | |
1737 | They (usually) share their frame pointer with the frame that was | |
1738 | in progress when the signal occurred. */ | |
1739 | ||
10458914 | 1740 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1741 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1742 | if (cache->base == 0) |
620fa63a PA |
1743 | { |
1744 | cache->base_p = 1; | |
1745 | return; | |
1746 | } | |
acd5c798 MK |
1747 | |
1748 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1749 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1750 | |
acd5c798 | 1751 | if (cache->pc != 0) |
e17a4113 UW |
1752 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1753 | cache); | |
acd5c798 MK |
1754 | |
1755 | if (cache->locals < 0) | |
1756 | { | |
1757 | /* We didn't find a valid frame, which means that CACHE->base | |
1758 | currently holds the frame pointer for our calling frame. If | |
1759 | we're at the start of a function, or somewhere half-way its | |
1760 | prologue, the function's frame probably hasn't been fully | |
1761 | setup yet. Try to reconstruct the base address for the stack | |
1762 | frame by looking at the stack pointer. For truly "frameless" | |
1763 | functions this might work too. */ | |
1764 | ||
e0c62198 | 1765 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1766 | { |
8fbca658 PA |
1767 | /* Saved stack pointer has been saved. */ |
1768 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1769 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1770 | ||
92dd43fa MK |
1771 | /* We're halfway aligning the stack. */ |
1772 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1773 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1774 | ||
1775 | /* This will be added back below. */ | |
1776 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1777 | } | |
7618e12b DJ |
1778 | else if (cache->pc != 0 |
1779 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1780 | { |
7618e12b DJ |
1781 | /* We're in a known function, but did not find a frame |
1782 | setup. Assume that the function does not use %ebp. | |
1783 | Alternatively, we may have jumped to an invalid | |
1784 | address; in that case there is definitely no new | |
1785 | frame in %ebp. */ | |
10458914 | 1786 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1787 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1788 | + cache->sp_offset; | |
92dd43fa | 1789 | } |
7618e12b DJ |
1790 | else |
1791 | /* We're in an unknown function. We could not find the start | |
1792 | of the function to analyze the prologue; our best option is | |
1793 | to assume a typical frame layout with the caller's %ebp | |
1794 | saved. */ | |
1795 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1796 | } |
1797 | ||
8fbca658 PA |
1798 | if (cache->saved_sp_reg != -1) |
1799 | { | |
1800 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1801 | register may be unavailable). */ | |
1802 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
1803 | && deprecated_frame_register_read (this_frame, |
1804 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
1805 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
1806 | } | |
acd5c798 MK |
1807 | /* Now that we have the base address for the stack frame we can |
1808 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1809 | else if (cache->saved_sp == 0) |
92dd43fa | 1810 | cache->saved_sp = cache->base + 8; |
a7769679 | 1811 | |
acd5c798 MK |
1812 | /* Adjust all the saved registers such that they contain addresses |
1813 | instead of offsets. */ | |
1814 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1815 | if (cache->saved_regs[i] != -1) |
1816 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1817 | |
8fbca658 PA |
1818 | cache->base_p = 1; |
1819 | } | |
1820 | ||
1821 | static struct i386_frame_cache * | |
1822 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1823 | { | |
1824 | volatile struct gdb_exception ex; | |
1825 | struct i386_frame_cache *cache; | |
1826 | ||
1827 | if (*this_cache) | |
1828 | return *this_cache; | |
1829 | ||
1830 | cache = i386_alloc_frame_cache (); | |
1831 | *this_cache = cache; | |
1832 | ||
1833 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1834 | { | |
1835 | i386_frame_cache_1 (this_frame, cache); | |
1836 | } | |
1837 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1838 | throw_exception (ex); | |
1839 | ||
acd5c798 | 1840 | return cache; |
a7769679 MK |
1841 | } |
1842 | ||
3a1e71e3 | 1843 | static void |
10458914 | 1844 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1845 | struct frame_id *this_id) |
c906108c | 1846 | { |
10458914 | 1847 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1848 | |
1849 | /* This marks the outermost frame. */ | |
1850 | if (cache->base == 0) | |
1851 | return; | |
1852 | ||
3e210248 | 1853 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1854 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1855 | } | |
1856 | ||
8fbca658 PA |
1857 | static enum unwind_stop_reason |
1858 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1859 | void **this_cache) | |
1860 | { | |
1861 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1862 | ||
1863 | if (!cache->base_p) | |
1864 | return UNWIND_UNAVAILABLE; | |
1865 | ||
1866 | /* This marks the outermost frame. */ | |
1867 | if (cache->base == 0) | |
1868 | return UNWIND_OUTERMOST; | |
1869 | ||
1870 | return UNWIND_NO_REASON; | |
1871 | } | |
1872 | ||
10458914 DJ |
1873 | static struct value * |
1874 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1875 | int regnum) | |
acd5c798 | 1876 | { |
10458914 | 1877 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1878 | |
1879 | gdb_assert (regnum >= 0); | |
1880 | ||
1881 | /* The System V ABI says that: | |
1882 | ||
1883 | "The flags register contains the system flags, such as the | |
1884 | direction flag and the carry flag. The direction flag must be | |
1885 | set to the forward (that is, zero) direction before entry and | |
1886 | upon exit from a function. Other user flags have no specified | |
1887 | role in the standard calling sequence and are not preserved." | |
1888 | ||
1889 | To guarantee the "upon exit" part of that statement we fake a | |
1890 | saved flags register that has its direction flag cleared. | |
1891 | ||
1892 | Note that GCC doesn't seem to rely on the fact that the direction | |
1893 | flag is cleared after a function return; it always explicitly | |
1894 | clears the flag before operations where it matters. | |
1895 | ||
1896 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1897 | right thing to do. The way we fake the flags register here makes | |
1898 | it impossible to change it. */ | |
1899 | ||
1900 | if (regnum == I386_EFLAGS_REGNUM) | |
1901 | { | |
10458914 | 1902 | ULONGEST val; |
c5aa993b | 1903 | |
10458914 DJ |
1904 | val = get_frame_register_unsigned (this_frame, regnum); |
1905 | val &= ~(1 << 10); | |
1906 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1907 | } |
1211c4e4 | 1908 | |
acd5c798 | 1909 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1910 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1911 | |
fcf250e2 UW |
1912 | if (regnum == I386_ESP_REGNUM |
1913 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1914 | { |
1915 | /* If the SP has been saved, but we don't know where, then this | |
1916 | means that SAVED_SP_REG register was found unavailable back | |
1917 | when we built the cache. */ | |
fcf250e2 | 1918 | if (cache->saved_sp == 0) |
8fbca658 PA |
1919 | return frame_unwind_got_register (this_frame, regnum, |
1920 | cache->saved_sp_reg); | |
1921 | else | |
1922 | return frame_unwind_got_constant (this_frame, regnum, | |
1923 | cache->saved_sp); | |
1924 | } | |
acd5c798 | 1925 | |
fd13a04a | 1926 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1927 | return frame_unwind_got_memory (this_frame, regnum, |
1928 | cache->saved_regs[regnum]); | |
fd13a04a | 1929 | |
10458914 | 1930 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1931 | } |
1932 | ||
1933 | static const struct frame_unwind i386_frame_unwind = | |
1934 | { | |
1935 | NORMAL_FRAME, | |
8fbca658 | 1936 | i386_frame_unwind_stop_reason, |
acd5c798 | 1937 | i386_frame_this_id, |
10458914 DJ |
1938 | i386_frame_prev_register, |
1939 | NULL, | |
1940 | default_frame_sniffer | |
acd5c798 | 1941 | }; |
06da04c6 MS |
1942 | |
1943 | /* Normal frames, but in a function epilogue. */ | |
1944 | ||
1945 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1946 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1947 | the function's stack frame. */ | |
1948 | ||
1949 | static int | |
1950 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1951 | { | |
1952 | gdb_byte insn; | |
e0d00bc7 JK |
1953 | struct symtab *symtab; |
1954 | ||
1955 | symtab = find_pc_symtab (pc); | |
1956 | if (symtab && symtab->epilogue_unwind_valid) | |
1957 | return 0; | |
06da04c6 MS |
1958 | |
1959 | if (target_read_memory (pc, &insn, 1)) | |
1960 | return 0; /* Can't read memory at pc. */ | |
1961 | ||
1962 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1963 | return 0; | |
1964 | ||
1965 | return 1; | |
1966 | } | |
1967 | ||
1968 | static int | |
1969 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1970 | struct frame_info *this_frame, | |
1971 | void **this_prologue_cache) | |
1972 | { | |
1973 | if (frame_relative_level (this_frame) == 0) | |
1974 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1975 | get_frame_pc (this_frame)); | |
1976 | else | |
1977 | return 0; | |
1978 | } | |
1979 | ||
1980 | static struct i386_frame_cache * | |
1981 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1982 | { | |
8fbca658 | 1983 | volatile struct gdb_exception ex; |
06da04c6 | 1984 | struct i386_frame_cache *cache; |
0d6c2135 | 1985 | CORE_ADDR sp; |
06da04c6 MS |
1986 | |
1987 | if (*this_cache) | |
1988 | return *this_cache; | |
1989 | ||
1990 | cache = i386_alloc_frame_cache (); | |
1991 | *this_cache = cache; | |
1992 | ||
8fbca658 PA |
1993 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1994 | { | |
0d6c2135 | 1995 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1996 | |
0d6c2135 MK |
1997 | /* At this point the stack looks as if we just entered the |
1998 | function, with the return address at the top of the | |
1999 | stack. */ | |
2000 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2001 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2002 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2003 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2004 | |
8fbca658 PA |
2005 | cache->base_p = 1; |
2006 | } | |
2007 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2008 | throw_exception (ex); | |
06da04c6 MS |
2009 | |
2010 | return cache; | |
2011 | } | |
2012 | ||
8fbca658 PA |
2013 | static enum unwind_stop_reason |
2014 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2015 | void **this_cache) | |
2016 | { | |
0d6c2135 MK |
2017 | struct i386_frame_cache *cache = |
2018 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2019 | |
2020 | if (!cache->base_p) | |
2021 | return UNWIND_UNAVAILABLE; | |
2022 | ||
2023 | return UNWIND_NO_REASON; | |
2024 | } | |
2025 | ||
06da04c6 MS |
2026 | static void |
2027 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2028 | void **this_cache, | |
2029 | struct frame_id *this_id) | |
2030 | { | |
0d6c2135 MK |
2031 | struct i386_frame_cache *cache = |
2032 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2033 | |
8fbca658 PA |
2034 | if (!cache->base_p) |
2035 | return; | |
2036 | ||
06da04c6 MS |
2037 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
2038 | } | |
2039 | ||
0d6c2135 MK |
2040 | static struct value * |
2041 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2042 | void **this_cache, int regnum) | |
2043 | { | |
2044 | /* Make sure we've initialized the cache. */ | |
2045 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2046 | ||
2047 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2048 | } | |
2049 | ||
06da04c6 MS |
2050 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2051 | { | |
2052 | NORMAL_FRAME, | |
8fbca658 | 2053 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2054 | i386_epilogue_frame_this_id, |
0d6c2135 | 2055 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2056 | NULL, |
2057 | i386_epilogue_frame_sniffer | |
2058 | }; | |
acd5c798 MK |
2059 | \f |
2060 | ||
a3fcb948 JG |
2061 | /* Stack-based trampolines. */ |
2062 | ||
2063 | /* These trampolines are used on cross x86 targets, when taking the | |
2064 | address of a nested function. When executing these trampolines, | |
2065 | no stack frame is set up, so we are in a similar situation as in | |
2066 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2067 | ||
2068 | /* Static chain passed in register. */ | |
2069 | ||
2070 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2071 | { | |
2072 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2073 | { 5, { 0xb8 }, { 0xfe } }, | |
2074 | ||
2075 | /* `jmp imm32' */ | |
2076 | { 5, { 0xe9 }, { 0xff } }, | |
2077 | ||
2078 | {0} | |
2079 | }; | |
2080 | ||
2081 | /* Static chain passed on stack (when regparm=3). */ | |
2082 | ||
2083 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2084 | { | |
2085 | /* `push imm32' */ | |
2086 | { 5, { 0x68 }, { 0xff } }, | |
2087 | ||
2088 | /* `jmp imm32' */ | |
2089 | { 5, { 0xe9 }, { 0xff } }, | |
2090 | ||
2091 | {0} | |
2092 | }; | |
2093 | ||
2094 | /* Return whether PC points inside a stack trampoline. */ | |
2095 | ||
2096 | static int | |
2097 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2098 | { | |
2099 | gdb_byte insn; | |
2c02bd72 | 2100 | const char *name; |
a3fcb948 JG |
2101 | |
2102 | /* A stack trampoline is detected if no name is associated | |
2103 | to the current pc and if it points inside a trampoline | |
2104 | sequence. */ | |
2105 | ||
2106 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2107 | if (name) | |
2108 | return 0; | |
2109 | ||
2110 | if (target_read_memory (pc, &insn, 1)) | |
2111 | return 0; | |
2112 | ||
2113 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2114 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2115 | return 0; | |
2116 | ||
2117 | return 1; | |
2118 | } | |
2119 | ||
2120 | static int | |
2121 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2122 | struct frame_info *this_frame, |
2123 | void **this_cache) | |
a3fcb948 JG |
2124 | { |
2125 | if (frame_relative_level (this_frame) == 0) | |
2126 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2127 | get_frame_pc (this_frame)); | |
2128 | else | |
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2133 | { | |
2134 | NORMAL_FRAME, | |
2135 | i386_epilogue_frame_unwind_stop_reason, | |
2136 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2137 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2138 | NULL, |
2139 | i386_stack_tramp_frame_sniffer | |
2140 | }; | |
2141 | \f | |
6710bf39 SS |
2142 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2143 | ||
2144 | static void | |
2145 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2146 | struct agent_expr *ax, struct axs_value *value, | |
2147 | CORE_ADDR scope) | |
2148 | { | |
2149 | /* The following sequence assumes the traditional use of the base | |
2150 | register. */ | |
2151 | ax_reg (ax, I386_EBP_REGNUM); | |
2152 | ax_const_l (ax, 4); | |
2153 | ax_simple (ax, aop_add); | |
2154 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2155 | value->kind = axs_lvalue_memory; | |
2156 | } | |
2157 | \f | |
a3fcb948 | 2158 | |
acd5c798 MK |
2159 | /* Signal trampolines. */ |
2160 | ||
2161 | static struct i386_frame_cache * | |
10458914 | 2162 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2163 | { |
e17a4113 UW |
2164 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2165 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2166 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2167 | volatile struct gdb_exception ex; |
acd5c798 | 2168 | struct i386_frame_cache *cache; |
acd5c798 | 2169 | CORE_ADDR addr; |
63c0089f | 2170 | gdb_byte buf[4]; |
acd5c798 MK |
2171 | |
2172 | if (*this_cache) | |
2173 | return *this_cache; | |
2174 | ||
fd13a04a | 2175 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2176 | |
8fbca658 | 2177 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2178 | { |
8fbca658 PA |
2179 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2180 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2181 | |
8fbca658 PA |
2182 | addr = tdep->sigcontext_addr (this_frame); |
2183 | if (tdep->sc_reg_offset) | |
2184 | { | |
2185 | int i; | |
a3386186 | 2186 | |
8fbca658 PA |
2187 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2188 | ||
2189 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2190 | if (tdep->sc_reg_offset[i] != -1) | |
2191 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2192 | } | |
2193 | else | |
2194 | { | |
2195 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2196 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2197 | } | |
2198 | ||
2199 | cache->base_p = 1; | |
a3386186 | 2200 | } |
8fbca658 PA |
2201 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2202 | throw_exception (ex); | |
acd5c798 MK |
2203 | |
2204 | *this_cache = cache; | |
2205 | return cache; | |
2206 | } | |
2207 | ||
8fbca658 PA |
2208 | static enum unwind_stop_reason |
2209 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2210 | void **this_cache) | |
2211 | { | |
2212 | struct i386_frame_cache *cache = | |
2213 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2214 | ||
2215 | if (!cache->base_p) | |
2216 | return UNWIND_UNAVAILABLE; | |
2217 | ||
2218 | return UNWIND_NO_REASON; | |
2219 | } | |
2220 | ||
acd5c798 | 2221 | static void |
10458914 | 2222 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2223 | struct frame_id *this_id) |
2224 | { | |
2225 | struct i386_frame_cache *cache = | |
10458914 | 2226 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2227 | |
8fbca658 PA |
2228 | if (!cache->base_p) |
2229 | return; | |
2230 | ||
3e210248 | 2231 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2232 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2233 | } |
2234 | ||
10458914 DJ |
2235 | static struct value * |
2236 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2237 | void **this_cache, int regnum) | |
acd5c798 MK |
2238 | { |
2239 | /* Make sure we've initialized the cache. */ | |
10458914 | 2240 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2241 | |
10458914 | 2242 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2243 | } |
c0d1d883 | 2244 | |
10458914 DJ |
2245 | static int |
2246 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2247 | struct frame_info *this_frame, | |
2248 | void **this_prologue_cache) | |
acd5c798 | 2249 | { |
10458914 | 2250 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2251 | |
911bc6ee MK |
2252 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2253 | handler. */ | |
2254 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2255 | return 0; |
1c3545ae | 2256 | |
911bc6ee MK |
2257 | if (tdep->sigtramp_p != NULL) |
2258 | { | |
10458914 DJ |
2259 | if (tdep->sigtramp_p (this_frame)) |
2260 | return 1; | |
911bc6ee MK |
2261 | } |
2262 | ||
2263 | if (tdep->sigtramp_start != 0) | |
2264 | { | |
10458914 | 2265 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2266 | |
2267 | gdb_assert (tdep->sigtramp_end != 0); | |
2268 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2269 | return 1; |
911bc6ee | 2270 | } |
acd5c798 | 2271 | |
10458914 | 2272 | return 0; |
acd5c798 | 2273 | } |
10458914 DJ |
2274 | |
2275 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2276 | { | |
2277 | SIGTRAMP_FRAME, | |
8fbca658 | 2278 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2279 | i386_sigtramp_frame_this_id, |
2280 | i386_sigtramp_frame_prev_register, | |
2281 | NULL, | |
2282 | i386_sigtramp_frame_sniffer | |
2283 | }; | |
acd5c798 MK |
2284 | \f |
2285 | ||
2286 | static CORE_ADDR | |
10458914 | 2287 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2288 | { |
10458914 | 2289 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2290 | |
2291 | return cache->base; | |
2292 | } | |
2293 | ||
2294 | static const struct frame_base i386_frame_base = | |
2295 | { | |
2296 | &i386_frame_unwind, | |
2297 | i386_frame_base_address, | |
2298 | i386_frame_base_address, | |
2299 | i386_frame_base_address | |
2300 | }; | |
2301 | ||
acd5c798 | 2302 | static struct frame_id |
10458914 | 2303 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2304 | { |
acd5c798 MK |
2305 | CORE_ADDR fp; |
2306 | ||
10458914 | 2307 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2308 | |
3e210248 | 2309 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2310 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2311 | } |
e04e5beb JM |
2312 | |
2313 | /* _Decimal128 function return values need 16-byte alignment on the | |
2314 | stack. */ | |
2315 | ||
2316 | static CORE_ADDR | |
2317 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2318 | { | |
2319 | return sp & -(CORE_ADDR)16; | |
2320 | } | |
fc338970 | 2321 | \f |
c906108c | 2322 | |
fc338970 MK |
2323 | /* Figure out where the longjmp will land. Slurp the args out of the |
2324 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2325 | structure from which we extract the address that we will land at. |
28bcfd30 | 2326 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2327 | success. */ |
c906108c | 2328 | |
8201327c | 2329 | static int |
60ade65d | 2330 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2331 | { |
436675d3 | 2332 | gdb_byte buf[4]; |
c906108c | 2333 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2334 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2335 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2336 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2337 | |
8201327c MK |
2338 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2339 | longjmp will land. */ | |
2340 | if (jb_pc_offset == -1) | |
c906108c SS |
2341 | return 0; |
2342 | ||
436675d3 | 2343 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2344 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2345 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2346 | return 0; |
2347 | ||
e17a4113 | 2348 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2349 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2350 | return 0; |
c906108c | 2351 | |
e17a4113 | 2352 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2353 | return 1; |
2354 | } | |
fc338970 | 2355 | \f |
c906108c | 2356 | |
7ccc1c74 JM |
2357 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2358 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2359 | unions containing such types must be 16-byte-aligned; other | |
2360 | arguments are 4-byte-aligned. */ | |
2361 | ||
2362 | static int | |
2363 | i386_16_byte_align_p (struct type *type) | |
2364 | { | |
2365 | type = check_typedef (type); | |
2366 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2367 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2368 | && TYPE_LENGTH (type) == 16) | |
2369 | return 1; | |
2370 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2371 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2372 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2373 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2374 | { | |
2375 | int i; | |
2376 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2377 | { | |
2378 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2379 | return 1; | |
2380 | } | |
2381 | } | |
2382 | return 0; | |
2383 | } | |
2384 | ||
a9b8d892 JK |
2385 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2386 | ||
2387 | static CORE_ADDR | |
2388 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2389 | struct value **args, int nargs, struct type *value_type, | |
2390 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2391 | struct regcache *regcache) | |
2392 | { | |
2393 | /* Use 0xcc breakpoint - 1 byte. */ | |
2394 | *bp_addr = sp - 1; | |
2395 | *real_pc = funaddr; | |
2396 | ||
2397 | /* Keep the stack aligned. */ | |
2398 | return sp - 16; | |
2399 | } | |
2400 | ||
3a1e71e3 | 2401 | static CORE_ADDR |
7d9b040b | 2402 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2403 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2404 | struct value **args, CORE_ADDR sp, int struct_return, | |
2405 | CORE_ADDR struct_addr) | |
22f8ba57 | 2406 | { |
e17a4113 | 2407 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2408 | gdb_byte buf[4]; |
acd5c798 | 2409 | int i; |
7ccc1c74 JM |
2410 | int write_pass; |
2411 | int args_space = 0; | |
acd5c798 | 2412 | |
7ccc1c74 JM |
2413 | /* Determine the total space required for arguments and struct |
2414 | return address in a first pass (allowing for 16-byte-aligned | |
2415 | arguments), then push arguments in a second pass. */ | |
2416 | ||
2417 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2418 | { |
7ccc1c74 | 2419 | int args_space_used = 0; |
7ccc1c74 JM |
2420 | |
2421 | if (struct_return) | |
2422 | { | |
2423 | if (write_pass) | |
2424 | { | |
2425 | /* Push value address. */ | |
e17a4113 | 2426 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2427 | write_memory (sp, buf, 4); |
2428 | args_space_used += 4; | |
2429 | } | |
2430 | else | |
2431 | args_space += 4; | |
2432 | } | |
2433 | ||
2434 | for (i = 0; i < nargs; i++) | |
2435 | { | |
2436 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2437 | |
7ccc1c74 JM |
2438 | if (write_pass) |
2439 | { | |
2440 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2441 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2442 | |
7ccc1c74 JM |
2443 | write_memory (sp + args_space_used, |
2444 | value_contents_all (args[i]), len); | |
2445 | /* The System V ABI says that: | |
acd5c798 | 2446 | |
7ccc1c74 JM |
2447 | "An argument's size is increased, if necessary, to make it a |
2448 | multiple of [32-bit] words. This may require tail padding, | |
2449 | depending on the size of the argument." | |
22f8ba57 | 2450 | |
7ccc1c74 JM |
2451 | This makes sure the stack stays word-aligned. */ |
2452 | args_space_used += align_up (len, 4); | |
2453 | } | |
2454 | else | |
2455 | { | |
2456 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2457 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2458 | args_space += align_up (len, 4); |
2459 | } | |
2460 | } | |
2461 | ||
2462 | if (!write_pass) | |
2463 | { | |
7ccc1c74 | 2464 | sp -= args_space; |
284c5a60 MK |
2465 | |
2466 | /* The original System V ABI only requires word alignment, | |
2467 | but modern incarnations need 16-byte alignment in order | |
2468 | to support SSE. Since wasting a few bytes here isn't | |
2469 | harmful we unconditionally enforce 16-byte alignment. */ | |
2470 | sp &= ~0xf; | |
7ccc1c74 | 2471 | } |
22f8ba57 MK |
2472 | } |
2473 | ||
acd5c798 MK |
2474 | /* Store return address. */ |
2475 | sp -= 4; | |
e17a4113 | 2476 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2477 | write_memory (sp, buf, 4); |
2478 | ||
2479 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2480 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2481 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2482 | ||
2483 | /* ...and fake a frame pointer. */ | |
2484 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2485 | ||
3e210248 AC |
2486 | /* MarkK wrote: This "+ 8" is all over the place: |
2487 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2488 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2489 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2490 | definition of the stack address of a frame. Otherwise frame id |
2491 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2492 | stack address *before* the function call as a frame's CFA. On |
2493 | the i386, when %ebp is used as a frame pointer, the offset | |
2494 | between the contents %ebp and the CFA as defined by GCC. */ | |
2495 | return sp + 8; | |
22f8ba57 MK |
2496 | } |
2497 | ||
1a309862 MK |
2498 | /* These registers are used for returning integers (and on some |
2499 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2500 | size and alignment match an integer type). */ |
acd5c798 MK |
2501 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2502 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2503 | |
c5e656c1 MK |
2504 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2505 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2506 | |
3a1e71e3 | 2507 | static void |
c5e656c1 | 2508 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2509 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2510 | { |
c5e656c1 | 2511 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2512 | int len = TYPE_LENGTH (type); |
63c0089f | 2513 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2514 | |
1e8d0a7b | 2515 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2516 | { |
5716833c | 2517 | if (tdep->st0_regnum < 0) |
1a309862 | 2518 | { |
8a3fe4f8 | 2519 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2520 | memset (valbuf, 0, len); |
ef9dff19 | 2521 | return; |
1a309862 MK |
2522 | } |
2523 | ||
c6ba6f0d MK |
2524 | /* Floating-point return values can be found in %st(0). Convert |
2525 | its contents to the desired type. This is probably not | |
2526 | exactly how it would happen on the target itself, but it is | |
2527 | the best we can do. */ | |
acd5c798 | 2528 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2529 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2530 | } |
2531 | else | |
c5aa993b | 2532 | { |
875f8d0e UW |
2533 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2534 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2535 | |
2536 | if (len <= low_size) | |
00f8375e | 2537 | { |
0818c12a | 2538 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2539 | memcpy (valbuf, buf, len); |
2540 | } | |
d4f3574e SS |
2541 | else if (len <= (low_size + high_size)) |
2542 | { | |
0818c12a | 2543 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2544 | memcpy (valbuf, buf, low_size); |
0818c12a | 2545 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2546 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2547 | } |
2548 | else | |
8e65ff28 | 2549 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2550 | _("Cannot extract return value of %d bytes long."), |
2551 | len); | |
c906108c SS |
2552 | } |
2553 | } | |
2554 | ||
c5e656c1 MK |
2555 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2556 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2557 | |
3a1e71e3 | 2558 | static void |
c5e656c1 | 2559 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2560 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2561 | { |
c5e656c1 | 2562 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2563 | int len = TYPE_LENGTH (type); |
2564 | ||
1e8d0a7b | 2565 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2566 | { |
3d7f4f49 | 2567 | ULONGEST fstat; |
63c0089f | 2568 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2569 | |
5716833c | 2570 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2571 | { |
8a3fe4f8 | 2572 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2573 | return; |
2574 | } | |
2575 | ||
635b0cc1 MK |
2576 | /* Returning floating-point values is a bit tricky. Apart from |
2577 | storing the return value in %st(0), we have to simulate the | |
2578 | state of the FPU at function return point. */ | |
2579 | ||
c6ba6f0d MK |
2580 | /* Convert the value found in VALBUF to the extended |
2581 | floating-point format used by the FPU. This is probably | |
2582 | not exactly how it would happen on the target itself, but | |
2583 | it is the best we can do. */ | |
27067745 | 2584 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2585 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2586 | |
635b0cc1 MK |
2587 | /* Set the top of the floating-point register stack to 7. The |
2588 | actual value doesn't really matter, but 7 is what a normal | |
2589 | function return would end up with if the program started out | |
2590 | with a freshly initialized FPU. */ | |
20a6ec49 | 2591 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2592 | fstat |= (7 << 11); |
20a6ec49 | 2593 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2594 | |
635b0cc1 MK |
2595 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2596 | the floating-point register stack to 7, the appropriate value | |
2597 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2598 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2599 | } |
2600 | else | |
2601 | { | |
875f8d0e UW |
2602 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2603 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2604 | |
2605 | if (len <= low_size) | |
3d7f4f49 | 2606 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2607 | else if (len <= (low_size + high_size)) |
2608 | { | |
3d7f4f49 MK |
2609 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2610 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2611 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2612 | } |
2613 | else | |
8e65ff28 | 2614 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2615 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2616 | } |
2617 | } | |
fc338970 | 2618 | \f |
ef9dff19 | 2619 | |
8201327c MK |
2620 | /* This is the variable that is set with "set struct-convention", and |
2621 | its legitimate values. */ | |
2622 | static const char default_struct_convention[] = "default"; | |
2623 | static const char pcc_struct_convention[] = "pcc"; | |
2624 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2625 | static const char *const valid_conventions[] = |
8201327c MK |
2626 | { |
2627 | default_struct_convention, | |
2628 | pcc_struct_convention, | |
2629 | reg_struct_convention, | |
2630 | NULL | |
2631 | }; | |
2632 | static const char *struct_convention = default_struct_convention; | |
2633 | ||
0e4377e1 JB |
2634 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2635 | a union type, or an array type, should be returned in registers | |
2636 | for architecture GDBARCH. */ | |
c5e656c1 | 2637 | |
8201327c | 2638 | static int |
c5e656c1 | 2639 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2640 | { |
c5e656c1 MK |
2641 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2642 | enum type_code code = TYPE_CODE (type); | |
2643 | int len = TYPE_LENGTH (type); | |
8201327c | 2644 | |
0e4377e1 JB |
2645 | gdb_assert (code == TYPE_CODE_STRUCT |
2646 | || code == TYPE_CODE_UNION | |
2647 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2648 | |
2649 | if (struct_convention == pcc_struct_convention | |
2650 | || (struct_convention == default_struct_convention | |
2651 | && tdep->struct_return == pcc_struct_return)) | |
2652 | return 0; | |
2653 | ||
9edde48e MK |
2654 | /* Structures consisting of a single `float', `double' or 'long |
2655 | double' member are returned in %st(0). */ | |
2656 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2657 | { | |
2658 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2659 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2660 | return (len == 4 || len == 8 || len == 12); | |
2661 | } | |
2662 | ||
c5e656c1 MK |
2663 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2664 | } | |
2665 | ||
2666 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2667 | should be returned. If it is supposed to be returned in registers, | |
2668 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2669 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2670 | from WRITEBUF into REGCACHE. */ | |
2671 | ||
2672 | static enum return_value_convention | |
6a3a010b | 2673 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2674 | struct type *type, struct regcache *regcache, |
2675 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2676 | { |
2677 | enum type_code code = TYPE_CODE (type); | |
2678 | ||
5daa78cc TJB |
2679 | if (((code == TYPE_CODE_STRUCT |
2680 | || code == TYPE_CODE_UNION | |
2681 | || code == TYPE_CODE_ARRAY) | |
2682 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2683 | /* Complex double and long double uses the struct return covention. */ |
2684 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2685 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2686 | /* 128-bit decimal float uses the struct return convention. */ |
2687 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2688 | { |
2689 | /* The System V ABI says that: | |
2690 | ||
2691 | "A function that returns a structure or union also sets %eax | |
2692 | to the value of the original address of the caller's area | |
2693 | before it returns. Thus when the caller receives control | |
2694 | again, the address of the returned object resides in register | |
2695 | %eax and can be used to access the object." | |
2696 | ||
2697 | So the ABI guarantees that we can always find the return | |
2698 | value just after the function has returned. */ | |
2699 | ||
0e4377e1 JB |
2700 | /* Note that the ABI doesn't mention functions returning arrays, |
2701 | which is something possible in certain languages such as Ada. | |
2702 | In this case, the value is returned as if it was wrapped in | |
2703 | a record, so the convention applied to records also applies | |
2704 | to arrays. */ | |
2705 | ||
31db7b6c MK |
2706 | if (readbuf) |
2707 | { | |
2708 | ULONGEST addr; | |
2709 | ||
2710 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2711 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2712 | } | |
2713 | ||
2714 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2715 | } | |
c5e656c1 MK |
2716 | |
2717 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2718 | `float', `double' or 'long double' member. These structures are |
2719 | returned in %st(0). For these structures, we call ourselves | |
2720 | recursively, changing TYPE into the type of the first member of | |
2721 | the structure. Since that should work for all structures that | |
2722 | have only one member, we don't bother to check the member's type | |
2723 | here. */ | |
c5e656c1 MK |
2724 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2725 | { | |
2726 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2727 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2728 | readbuf, writebuf); |
c5e656c1 MK |
2729 | } |
2730 | ||
2731 | if (readbuf) | |
2732 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2733 | if (writebuf) | |
2734 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2735 | |
c5e656c1 | 2736 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2737 | } |
2738 | \f | |
2739 | ||
27067745 UW |
2740 | struct type * |
2741 | i387_ext_type (struct gdbarch *gdbarch) | |
2742 | { | |
2743 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2744 | ||
2745 | if (!tdep->i387_ext_type) | |
90884b2b L |
2746 | { |
2747 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2748 | gdb_assert (tdep->i387_ext_type != NULL); | |
2749 | } | |
27067745 UW |
2750 | |
2751 | return tdep->i387_ext_type; | |
2752 | } | |
2753 | ||
c131fcee L |
2754 | /* Construct vector type for pseudo YMM registers. We can't use |
2755 | tdesc_find_type since YMM isn't described in target description. */ | |
2756 | ||
2757 | static struct type * | |
2758 | i386_ymm_type (struct gdbarch *gdbarch) | |
2759 | { | |
2760 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2761 | ||
2762 | if (!tdep->i386_ymm_type) | |
2763 | { | |
2764 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2765 | ||
2766 | /* The type we're building is this: */ | |
2767 | #if 0 | |
2768 | union __gdb_builtin_type_vec256i | |
2769 | { | |
2770 | int128_t uint128[2]; | |
2771 | int64_t v2_int64[4]; | |
2772 | int32_t v4_int32[8]; | |
2773 | int16_t v8_int16[16]; | |
2774 | int8_t v16_int8[32]; | |
2775 | double v2_double[4]; | |
2776 | float v4_float[8]; | |
2777 | }; | |
2778 | #endif | |
2779 | ||
2780 | struct type *t; | |
2781 | ||
2782 | t = arch_composite_type (gdbarch, | |
2783 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2784 | append_composite_type_field (t, "v8_float", | |
2785 | init_vector_type (bt->builtin_float, 8)); | |
2786 | append_composite_type_field (t, "v4_double", | |
2787 | init_vector_type (bt->builtin_double, 4)); | |
2788 | append_composite_type_field (t, "v32_int8", | |
2789 | init_vector_type (bt->builtin_int8, 32)); | |
2790 | append_composite_type_field (t, "v16_int16", | |
2791 | init_vector_type (bt->builtin_int16, 16)); | |
2792 | append_composite_type_field (t, "v8_int32", | |
2793 | init_vector_type (bt->builtin_int32, 8)); | |
2794 | append_composite_type_field (t, "v4_int64", | |
2795 | init_vector_type (bt->builtin_int64, 4)); | |
2796 | append_composite_type_field (t, "v2_int128", | |
2797 | init_vector_type (bt->builtin_int128, 2)); | |
2798 | ||
2799 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2800 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2801 | tdep->i386_ymm_type = t; |
2802 | } | |
2803 | ||
2804 | return tdep->i386_ymm_type; | |
2805 | } | |
2806 | ||
794ac428 | 2807 | /* Construct vector type for MMX registers. */ |
90884b2b | 2808 | static struct type * |
794ac428 UW |
2809 | i386_mmx_type (struct gdbarch *gdbarch) |
2810 | { | |
2811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2812 | ||
2813 | if (!tdep->i386_mmx_type) | |
2814 | { | |
df4df182 UW |
2815 | const struct builtin_type *bt = builtin_type (gdbarch); |
2816 | ||
794ac428 UW |
2817 | /* The type we're building is this: */ |
2818 | #if 0 | |
2819 | union __gdb_builtin_type_vec64i | |
2820 | { | |
2821 | int64_t uint64; | |
2822 | int32_t v2_int32[2]; | |
2823 | int16_t v4_int16[4]; | |
2824 | int8_t v8_int8[8]; | |
2825 | }; | |
2826 | #endif | |
2827 | ||
2828 | struct type *t; | |
2829 | ||
e9bb382b UW |
2830 | t = arch_composite_type (gdbarch, |
2831 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2832 | |
2833 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2834 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2835 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2836 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2837 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2838 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2839 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2840 | |
876cecd0 | 2841 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2842 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2843 | tdep->i386_mmx_type = t; | |
2844 | } | |
2845 | ||
2846 | return tdep->i386_mmx_type; | |
2847 | } | |
2848 | ||
d7a0d72c | 2849 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2850 | register REGNUM. */ |
d7a0d72c | 2851 | |
fff4548b | 2852 | struct type * |
90884b2b | 2853 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2854 | { |
1ba53b71 L |
2855 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2856 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2857 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2858 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2859 | else |
2860 | { | |
2861 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2862 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2863 | return bt->builtin_int8; | |
2864 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2865 | return bt->builtin_int16; | |
2866 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2867 | return bt->builtin_int32; | |
2868 | } | |
2869 | ||
2870 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2871 | } |
2872 | ||
28fc6740 | 2873 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2874 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2875 | |
2876 | static int | |
c86c27af | 2877 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2878 | { |
5716833c MK |
2879 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2880 | int mmxreg, fpreg; | |
28fc6740 AC |
2881 | ULONGEST fstat; |
2882 | int tos; | |
c86c27af | 2883 | |
5716833c | 2884 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2885 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2886 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2887 | fpreg = (mmxreg + tos) % 8; |
2888 | ||
20a6ec49 | 2889 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2890 | } |
2891 | ||
3543a589 TT |
2892 | /* A helper function for us by i386_pseudo_register_read_value and |
2893 | amd64_pseudo_register_read_value. It does all the work but reads | |
2894 | the data into an already-allocated value. */ | |
2895 | ||
2896 | void | |
2897 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
2898 | struct regcache *regcache, | |
2899 | int regnum, | |
2900 | struct value *result_value) | |
28fc6740 | 2901 | { |
1ba53b71 | 2902 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2903 | enum register_status status; |
3543a589 | 2904 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 2905 | |
5716833c | 2906 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2907 | { |
c86c27af MK |
2908 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2909 | ||
28fc6740 | 2910 | /* Extract (always little endian). */ |
05d1431c PA |
2911 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2912 | if (status != REG_VALID) | |
3543a589 TT |
2913 | mark_value_bytes_unavailable (result_value, 0, |
2914 | TYPE_LENGTH (value_type (result_value))); | |
2915 | else | |
2916 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2917 | } |
2918 | else | |
1ba53b71 L |
2919 | { |
2920 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2921 | ||
c131fcee L |
2922 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2923 | { | |
2924 | regnum -= tdep->ymm0_regnum; | |
2925 | ||
1777feb0 | 2926 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2927 | status = regcache_raw_read (regcache, |
2928 | I387_XMM0_REGNUM (tdep) + regnum, | |
2929 | raw_buf); | |
2930 | if (status != REG_VALID) | |
3543a589 TT |
2931 | mark_value_bytes_unavailable (result_value, 0, 16); |
2932 | else | |
2933 | memcpy (buf, raw_buf, 16); | |
c131fcee | 2934 | /* Read upper 128bits. */ |
05d1431c PA |
2935 | status = regcache_raw_read (regcache, |
2936 | tdep->ymm0h_regnum + regnum, | |
2937 | raw_buf); | |
2938 | if (status != REG_VALID) | |
3543a589 TT |
2939 | mark_value_bytes_unavailable (result_value, 16, 32); |
2940 | else | |
2941 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
2942 | } |
2943 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2944 | { |
2945 | int gpnum = regnum - tdep->ax_regnum; | |
2946 | ||
2947 | /* Extract (always little endian). */ | |
05d1431c PA |
2948 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2949 | if (status != REG_VALID) | |
3543a589 TT |
2950 | mark_value_bytes_unavailable (result_value, 0, |
2951 | TYPE_LENGTH (value_type (result_value))); | |
2952 | else | |
2953 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
2954 | } |
2955 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2956 | { | |
2957 | /* Check byte pseudo registers last since this function will | |
2958 | be called from amd64_pseudo_register_read, which handles | |
2959 | byte pseudo registers differently. */ | |
2960 | int gpnum = regnum - tdep->al_regnum; | |
2961 | ||
2962 | /* Extract (always little endian). We read both lower and | |
2963 | upper registers. */ | |
05d1431c PA |
2964 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2965 | if (status != REG_VALID) | |
3543a589 TT |
2966 | mark_value_bytes_unavailable (result_value, 0, |
2967 | TYPE_LENGTH (value_type (result_value))); | |
2968 | else if (gpnum >= 4) | |
1ba53b71 L |
2969 | memcpy (buf, raw_buf + 1, 1); |
2970 | else | |
2971 | memcpy (buf, raw_buf, 1); | |
2972 | } | |
2973 | else | |
2974 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2975 | } | |
3543a589 TT |
2976 | } |
2977 | ||
2978 | static struct value * | |
2979 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
2980 | struct regcache *regcache, | |
2981 | int regnum) | |
2982 | { | |
2983 | struct value *result; | |
2984 | ||
2985 | result = allocate_value (register_type (gdbarch, regnum)); | |
2986 | VALUE_LVAL (result) = lval_register; | |
2987 | VALUE_REGNUM (result) = regnum; | |
2988 | ||
2989 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 2990 | |
3543a589 | 2991 | return result; |
28fc6740 AC |
2992 | } |
2993 | ||
1ba53b71 | 2994 | void |
28fc6740 | 2995 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2996 | int regnum, const gdb_byte *buf) |
28fc6740 | 2997 | { |
1ba53b71 L |
2998 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2999 | ||
5716833c | 3000 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3001 | { |
c86c27af MK |
3002 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3003 | ||
28fc6740 | 3004 | /* Read ... */ |
1ba53b71 | 3005 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3006 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3007 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3008 | /* ... Write. */ |
1ba53b71 | 3009 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3010 | } |
3011 | else | |
1ba53b71 L |
3012 | { |
3013 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3014 | ||
c131fcee L |
3015 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
3016 | { | |
3017 | regnum -= tdep->ymm0_regnum; | |
3018 | ||
3019 | /* ... Write lower 128bits. */ | |
3020 | regcache_raw_write (regcache, | |
3021 | I387_XMM0_REGNUM (tdep) + regnum, | |
3022 | buf); | |
3023 | /* ... Write upper 128bits. */ | |
3024 | regcache_raw_write (regcache, | |
3025 | tdep->ymm0h_regnum + regnum, | |
3026 | buf + 16); | |
3027 | } | |
3028 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
3029 | { |
3030 | int gpnum = regnum - tdep->ax_regnum; | |
3031 | ||
3032 | /* Read ... */ | |
3033 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3034 | /* ... Modify ... (always little endian). */ | |
3035 | memcpy (raw_buf, buf, 2); | |
3036 | /* ... Write. */ | |
3037 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3038 | } | |
3039 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3040 | { | |
3041 | /* Check byte pseudo registers last since this function will | |
3042 | be called from amd64_pseudo_register_read, which handles | |
3043 | byte pseudo registers differently. */ | |
3044 | int gpnum = regnum - tdep->al_regnum; | |
3045 | ||
3046 | /* Read ... We read both lower and upper registers. */ | |
3047 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3048 | /* ... Modify ... (always little endian). */ | |
3049 | if (gpnum >= 4) | |
3050 | memcpy (raw_buf + 1, buf, 1); | |
3051 | else | |
3052 | memcpy (raw_buf, buf, 1); | |
3053 | /* ... Write. */ | |
3054 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3055 | } | |
3056 | else | |
3057 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3058 | } | |
28fc6740 | 3059 | } |
ff2e87ac AC |
3060 | \f |
3061 | ||
ff2e87ac AC |
3062 | /* Return the register number of the register allocated by GCC after |
3063 | REGNUM, or -1 if there is no such register. */ | |
3064 | ||
3065 | static int | |
3066 | i386_next_regnum (int regnum) | |
3067 | { | |
3068 | /* GCC allocates the registers in the order: | |
3069 | ||
3070 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3071 | ||
3072 | Since storing a variable in %esp doesn't make any sense we return | |
3073 | -1 for %ebp and for %esp itself. */ | |
3074 | static int next_regnum[] = | |
3075 | { | |
3076 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3077 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3078 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3079 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3080 | -1, -1, /* Slots for %esp and %ebp. */ | |
3081 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3082 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3083 | }; | |
3084 | ||
de5b9bb9 | 3085 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3086 | return next_regnum[regnum]; |
28fc6740 | 3087 | |
ff2e87ac AC |
3088 | return -1; |
3089 | } | |
3090 | ||
3091 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3092 | needs any special handling. */ | |
d7a0d72c | 3093 | |
3a1e71e3 | 3094 | static int |
1777feb0 MS |
3095 | i386_convert_register_p (struct gdbarch *gdbarch, |
3096 | int regnum, struct type *type) | |
d7a0d72c | 3097 | { |
de5b9bb9 MK |
3098 | int len = TYPE_LENGTH (type); |
3099 | ||
ff2e87ac AC |
3100 | /* Values may be spread across multiple registers. Most debugging |
3101 | formats aren't expressive enough to specify the locations, so | |
3102 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3103 | have a length that is a multiple of the word size, since GCC |
3104 | doesn't seem to put any other types into registers. */ | |
3105 | if (len > 4 && len % 4 == 0) | |
3106 | { | |
3107 | int last_regnum = regnum; | |
3108 | ||
3109 | while (len > 4) | |
3110 | { | |
3111 | last_regnum = i386_next_regnum (last_regnum); | |
3112 | len -= 4; | |
3113 | } | |
3114 | ||
3115 | if (last_regnum != -1) | |
3116 | return 1; | |
3117 | } | |
ff2e87ac | 3118 | |
0abe36f5 | 3119 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3120 | } |
3121 | ||
ff2e87ac AC |
3122 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3123 | return its contents in TO. */ | |
ac27f131 | 3124 | |
8dccd430 | 3125 | static int |
ff2e87ac | 3126 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3127 | struct type *type, gdb_byte *to, |
3128 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3129 | { |
20a6ec49 | 3130 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3131 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3132 | |
20a6ec49 | 3133 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3134 | return i387_register_to_value (frame, regnum, type, to, |
3135 | optimizedp, unavailablep); | |
ff2e87ac | 3136 | |
fd35795f | 3137 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3138 | |
3139 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3140 | |
de5b9bb9 MK |
3141 | while (len > 0) |
3142 | { | |
3143 | gdb_assert (regnum != -1); | |
20a6ec49 | 3144 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3145 | |
8dccd430 PA |
3146 | if (!get_frame_register_bytes (frame, regnum, 0, |
3147 | register_size (gdbarch, regnum), | |
3148 | to, optimizedp, unavailablep)) | |
3149 | return 0; | |
3150 | ||
de5b9bb9 MK |
3151 | regnum = i386_next_regnum (regnum); |
3152 | len -= 4; | |
42835c2b | 3153 | to += 4; |
de5b9bb9 | 3154 | } |
8dccd430 PA |
3155 | |
3156 | *optimizedp = *unavailablep = 0; | |
3157 | return 1; | |
ac27f131 MK |
3158 | } |
3159 | ||
ff2e87ac AC |
3160 | /* Write the contents FROM of a value of type TYPE into register |
3161 | REGNUM in frame FRAME. */ | |
ac27f131 | 3162 | |
3a1e71e3 | 3163 | static void |
ff2e87ac | 3164 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3165 | struct type *type, const gdb_byte *from) |
ac27f131 | 3166 | { |
de5b9bb9 | 3167 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3168 | |
20a6ec49 | 3169 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3170 | { |
d532c08f MK |
3171 | i387_value_to_register (frame, regnum, type, from); |
3172 | return; | |
3173 | } | |
3d261580 | 3174 | |
fd35795f | 3175 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3176 | |
3177 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3178 | |
de5b9bb9 MK |
3179 | while (len > 0) |
3180 | { | |
3181 | gdb_assert (regnum != -1); | |
875f8d0e | 3182 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3183 | |
42835c2b | 3184 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3185 | regnum = i386_next_regnum (regnum); |
3186 | len -= 4; | |
42835c2b | 3187 | from += 4; |
de5b9bb9 | 3188 | } |
ac27f131 | 3189 | } |
ff2e87ac | 3190 | \f |
7fdafb5a MK |
3191 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3192 | in the general-purpose register set REGSET to register cache | |
3193 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3194 | |
20187ed5 | 3195 | void |
473f17b0 MK |
3196 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3197 | int regnum, const void *gregs, size_t len) | |
3198 | { | |
9ea75c57 | 3199 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3200 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3201 | int i; |
3202 | ||
3203 | gdb_assert (len == tdep->sizeof_gregset); | |
3204 | ||
3205 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3206 | { | |
3207 | if ((regnum == i || regnum == -1) | |
3208 | && tdep->gregset_reg_offset[i] != -1) | |
3209 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3210 | } | |
3211 | } | |
3212 | ||
7fdafb5a MK |
3213 | /* Collect register REGNUM from the register cache REGCACHE and store |
3214 | it in the buffer specified by GREGS and LEN as described by the | |
3215 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3216 | all registers in REGSET. */ | |
3217 | ||
3218 | void | |
3219 | i386_collect_gregset (const struct regset *regset, | |
3220 | const struct regcache *regcache, | |
3221 | int regnum, void *gregs, size_t len) | |
3222 | { | |
3223 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3224 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3225 | int i; |
3226 | ||
3227 | gdb_assert (len == tdep->sizeof_gregset); | |
3228 | ||
3229 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3230 | { | |
3231 | if ((regnum == i || regnum == -1) | |
3232 | && tdep->gregset_reg_offset[i] != -1) | |
3233 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3238 | in the floating-point register set REGSET to register cache | |
3239 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3240 | |
3241 | static void | |
3242 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3243 | int regnum, const void *fpregs, size_t len) | |
3244 | { | |
9ea75c57 | 3245 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3246 | |
66a72d25 MK |
3247 | if (len == I387_SIZEOF_FXSAVE) |
3248 | { | |
3249 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3250 | return; | |
3251 | } | |
3252 | ||
473f17b0 MK |
3253 | gdb_assert (len == tdep->sizeof_fpregset); |
3254 | i387_supply_fsave (regcache, regnum, fpregs); | |
3255 | } | |
8446b36a | 3256 | |
2f305df1 MK |
3257 | /* Collect register REGNUM from the register cache REGCACHE and store |
3258 | it in the buffer specified by FPREGS and LEN as described by the | |
3259 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3260 | all registers in REGSET. */ | |
7fdafb5a MK |
3261 | |
3262 | static void | |
3263 | i386_collect_fpregset (const struct regset *regset, | |
3264 | const struct regcache *regcache, | |
3265 | int regnum, void *fpregs, size_t len) | |
3266 | { | |
3267 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3268 | ||
3269 | if (len == I387_SIZEOF_FXSAVE) | |
3270 | { | |
3271 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3272 | return; | |
3273 | } | |
3274 | ||
3275 | gdb_assert (len == tdep->sizeof_fpregset); | |
3276 | i387_collect_fsave (regcache, regnum, fpregs); | |
3277 | } | |
3278 | ||
c131fcee L |
3279 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3280 | ||
3281 | static void | |
3282 | i386_supply_xstateregset (const struct regset *regset, | |
3283 | struct regcache *regcache, int regnum, | |
3284 | const void *xstateregs, size_t len) | |
3285 | { | |
c131fcee L |
3286 | i387_supply_xsave (regcache, regnum, xstateregs); |
3287 | } | |
3288 | ||
3289 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3290 | ||
3291 | static void | |
3292 | i386_collect_xstateregset (const struct regset *regset, | |
3293 | const struct regcache *regcache, | |
3294 | int regnum, void *xstateregs, size_t len) | |
3295 | { | |
c131fcee L |
3296 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3297 | } | |
3298 | ||
8446b36a MK |
3299 | /* Return the appropriate register set for the core section identified |
3300 | by SECT_NAME and SECT_SIZE. */ | |
3301 | ||
3302 | const struct regset * | |
3303 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3304 | const char *sect_name, size_t sect_size) | |
3305 | { | |
3306 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3307 | ||
3308 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3309 | { | |
3310 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3311 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3312 | i386_collect_gregset); | |
8446b36a MK |
3313 | return tdep->gregset; |
3314 | } | |
3315 | ||
66a72d25 MK |
3316 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3317 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3318 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3319 | { |
3320 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3321 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3322 | i386_collect_fpregset); | |
8446b36a MK |
3323 | return tdep->fpregset; |
3324 | } | |
3325 | ||
c131fcee L |
3326 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3327 | { | |
3328 | if (tdep->xstateregset == NULL) | |
3329 | tdep->xstateregset = regset_alloc (gdbarch, | |
3330 | i386_supply_xstateregset, | |
3331 | i386_collect_xstateregset); | |
3332 | ||
3333 | return tdep->xstateregset; | |
3334 | } | |
3335 | ||
8446b36a MK |
3336 | return NULL; |
3337 | } | |
473f17b0 | 3338 | \f |
fc338970 | 3339 | |
fc338970 | 3340 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3341 | |
3342 | CORE_ADDR | |
e17a4113 UW |
3343 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3344 | CORE_ADDR pc, char *name) | |
c906108c | 3345 | { |
e17a4113 UW |
3346 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3347 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3348 | ||
3349 | /* jmp *(dest) */ | |
3350 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3351 | { |
e17a4113 UW |
3352 | unsigned long indirect = |
3353 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3354 | struct minimal_symbol *indsym = |
fc338970 | 3355 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
0d5cff50 | 3356 | const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3357 | |
c5aa993b | 3358 | if (symname) |
c906108c | 3359 | { |
c5aa993b JM |
3360 | if (strncmp (symname, "__imp_", 6) == 0 |
3361 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3362 | return name ? 1 : |
3363 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3364 | } |
3365 | } | |
fc338970 | 3366 | return 0; /* Not a trampoline. */ |
c906108c | 3367 | } |
fc338970 MK |
3368 | \f |
3369 | ||
10458914 DJ |
3370 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3371 | routine. */ | |
8201327c | 3372 | |
4bd207ef | 3373 | int |
10458914 | 3374 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3375 | { |
10458914 | 3376 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3377 | const char *name; |
911bc6ee MK |
3378 | |
3379 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3380 | return (name && strcmp ("_sigtramp", name) == 0); |
3381 | } | |
3382 | \f | |
3383 | ||
fc338970 MK |
3384 | /* We have two flavours of disassembly. The machinery on this page |
3385 | deals with switching between those. */ | |
c906108c SS |
3386 | |
3387 | static int | |
a89aa300 | 3388 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3389 | { |
5e3397bb MK |
3390 | gdb_assert (disassembly_flavor == att_flavor |
3391 | || disassembly_flavor == intel_flavor); | |
3392 | ||
3393 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3394 | constified, cast to prevent a compiler warning. */ | |
3395 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3396 | |
3397 | return print_insn_i386 (pc, info); | |
7a292a7a | 3398 | } |
fc338970 | 3399 | \f |
3ce1502b | 3400 | |
8201327c MK |
3401 | /* There are a few i386 architecture variants that differ only |
3402 | slightly from the generic i386 target. For now, we don't give them | |
3403 | their own source file, but include them here. As a consequence, | |
3404 | they'll always be included. */ | |
3ce1502b | 3405 | |
8201327c | 3406 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3407 | |
10458914 DJ |
3408 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3409 | routine. */ | |
911bc6ee | 3410 | |
8201327c | 3411 | static int |
10458914 | 3412 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3413 | { |
10458914 | 3414 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3415 | const char *name; |
911bc6ee | 3416 | |
05b4bd79 | 3417 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3418 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3419 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
3420 | || strcmp ("sigvechandler", name) == 0)); |
3421 | } | |
d2a7c97a | 3422 | |
10458914 DJ |
3423 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3424 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3425 | |
3a1e71e3 | 3426 | static CORE_ADDR |
10458914 | 3427 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3428 | { |
e17a4113 UW |
3429 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3430 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3431 | gdb_byte buf[4]; |
acd5c798 | 3432 | CORE_ADDR sp; |
3ce1502b | 3433 | |
10458914 | 3434 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3435 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3436 | |
e17a4113 | 3437 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3438 | } |
55aa24fb SDJ |
3439 | |
3440 | \f | |
3441 | ||
3442 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3443 | gdbarch.h. */ | |
3444 | ||
3445 | int | |
3446 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3447 | { | |
3448 | return (*s == '$' /* Literal number. */ | |
3449 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3450 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3451 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3452 | } | |
3453 | ||
3454 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in | |
3455 | gdbarch.h. */ | |
3456 | ||
3457 | int | |
3458 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
3459 | struct stap_parse_info *p) | |
3460 | { | |
55aa24fb SDJ |
3461 | /* In order to parse special tokens, we use a state-machine that go |
3462 | through every known token and try to get a match. */ | |
3463 | enum | |
3464 | { | |
3465 | TRIPLET, | |
3466 | THREE_ARG_DISPLACEMENT, | |
3467 | DONE | |
3468 | } current_state; | |
3469 | ||
3470 | current_state = TRIPLET; | |
3471 | ||
3472 | /* The special tokens to be parsed here are: | |
3473 | ||
3474 | - `register base + (register index * size) + offset', as represented | |
3475 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
3476 | ||
3477 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
3478 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
3479 | ||
3480 | while (current_state != DONE) | |
3481 | { | |
3482 | const char *s = p->arg; | |
3483 | ||
3484 | switch (current_state) | |
3485 | { | |
3486 | case TRIPLET: | |
3487 | { | |
3488 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3489 | { | |
3490 | int got_minus[3]; | |
3491 | int i; | |
3492 | long displacements[3]; | |
3493 | const char *start; | |
3494 | char *regname; | |
3495 | int len; | |
3496 | struct stoken str; | |
3497 | ||
3498 | got_minus[0] = 0; | |
3499 | if (*s == '+') | |
3500 | ++s; | |
3501 | else if (*s == '-') | |
3502 | { | |
3503 | ++s; | |
3504 | got_minus[0] = 1; | |
3505 | } | |
3506 | ||
3507 | displacements[0] = strtol (s, (char **) &s, 10); | |
3508 | ||
3509 | if (*s != '+' && *s != '-') | |
3510 | { | |
3511 | /* We are not dealing with a triplet. */ | |
3512 | break; | |
3513 | } | |
3514 | ||
3515 | got_minus[1] = 0; | |
3516 | if (*s == '+') | |
3517 | ++s; | |
3518 | else | |
3519 | { | |
3520 | ++s; | |
3521 | got_minus[1] = 1; | |
3522 | } | |
3523 | ||
3524 | displacements[1] = strtol (s, (char **) &s, 10); | |
3525 | ||
3526 | if (*s != '+' && *s != '-') | |
3527 | { | |
3528 | /* We are not dealing with a triplet. */ | |
3529 | break; | |
3530 | } | |
3531 | ||
3532 | got_minus[2] = 0; | |
3533 | if (*s == '+') | |
3534 | ++s; | |
3535 | else | |
3536 | { | |
3537 | ++s; | |
3538 | got_minus[2] = 1; | |
3539 | } | |
3540 | ||
3541 | displacements[2] = strtol (s, (char **) &s, 10); | |
3542 | ||
3543 | if (*s != '(' || s[1] != '%') | |
3544 | break; | |
3545 | ||
3546 | s += 2; | |
3547 | start = s; | |
3548 | ||
3549 | while (isalnum (*s)) | |
3550 | ++s; | |
3551 | ||
3552 | if (*s++ != ')') | |
3553 | break; | |
3554 | ||
3555 | len = s - start; | |
3556 | regname = alloca (len + 1); | |
3557 | ||
3558 | strncpy (regname, start, len); | |
3559 | regname[len] = '\0'; | |
3560 | ||
3561 | if (user_reg_map_name_to_regnum (gdbarch, | |
3562 | regname, len) == -1) | |
3563 | error (_("Invalid register name `%s' " | |
3564 | "on expression `%s'."), | |
3565 | regname, p->saved_arg); | |
3566 | ||
3567 | for (i = 0; i < 3; i++) | |
3568 | { | |
3569 | write_exp_elt_opcode (OP_LONG); | |
3570 | write_exp_elt_type | |
3571 | (builtin_type (gdbarch)->builtin_long); | |
3572 | write_exp_elt_longcst (displacements[i]); | |
3573 | write_exp_elt_opcode (OP_LONG); | |
3574 | if (got_minus[i]) | |
3575 | write_exp_elt_opcode (UNOP_NEG); | |
3576 | } | |
3577 | ||
3578 | write_exp_elt_opcode (OP_REGISTER); | |
3579 | str.ptr = regname; | |
3580 | str.length = len; | |
3581 | write_exp_string (str); | |
3582 | write_exp_elt_opcode (OP_REGISTER); | |
3583 | ||
3584 | write_exp_elt_opcode (UNOP_CAST); | |
3585 | write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr); | |
3586 | write_exp_elt_opcode (UNOP_CAST); | |
3587 | ||
3588 | write_exp_elt_opcode (BINOP_ADD); | |
3589 | write_exp_elt_opcode (BINOP_ADD); | |
3590 | write_exp_elt_opcode (BINOP_ADD); | |
3591 | ||
3592 | write_exp_elt_opcode (UNOP_CAST); | |
3593 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3594 | write_exp_elt_opcode (UNOP_CAST); | |
3595 | ||
3596 | write_exp_elt_opcode (UNOP_IND); | |
3597 | ||
3598 | p->arg = s; | |
3599 | ||
3600 | return 1; | |
3601 | } | |
3602 | break; | |
3603 | } | |
3604 | case THREE_ARG_DISPLACEMENT: | |
3605 | { | |
3606 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
3607 | { | |
3608 | int offset_minus = 0; | |
3609 | long offset = 0; | |
3610 | int size_minus = 0; | |
3611 | long size = 0; | |
3612 | const char *start; | |
3613 | char *base; | |
3614 | int len_base; | |
3615 | char *index; | |
3616 | int len_index; | |
3617 | struct stoken base_token, index_token; | |
3618 | ||
3619 | if (*s == '+') | |
3620 | ++s; | |
3621 | else if (*s == '-') | |
3622 | { | |
3623 | ++s; | |
3624 | offset_minus = 1; | |
3625 | } | |
3626 | ||
3627 | if (offset_minus && !isdigit (*s)) | |
3628 | break; | |
3629 | ||
3630 | if (isdigit (*s)) | |
3631 | offset = strtol (s, (char **) &s, 10); | |
3632 | ||
3633 | if (*s != '(' || s[1] != '%') | |
3634 | break; | |
3635 | ||
3636 | s += 2; | |
3637 | start = s; | |
3638 | ||
3639 | while (isalnum (*s)) | |
3640 | ++s; | |
3641 | ||
3642 | if (*s != ',' || s[1] != '%') | |
3643 | break; | |
3644 | ||
3645 | len_base = s - start; | |
3646 | base = alloca (len_base + 1); | |
3647 | strncpy (base, start, len_base); | |
3648 | base[len_base] = '\0'; | |
3649 | ||
3650 | if (user_reg_map_name_to_regnum (gdbarch, | |
3651 | base, len_base) == -1) | |
3652 | error (_("Invalid register name `%s' " | |
3653 | "on expression `%s'."), | |
3654 | base, p->saved_arg); | |
3655 | ||
3656 | s += 2; | |
3657 | start = s; | |
3658 | ||
3659 | while (isalnum (*s)) | |
3660 | ++s; | |
3661 | ||
3662 | len_index = s - start; | |
3663 | index = alloca (len_index + 1); | |
3664 | strncpy (index, start, len_index); | |
3665 | index[len_index] = '\0'; | |
3666 | ||
3667 | if (user_reg_map_name_to_regnum (gdbarch, | |
3668 | index, len_index) == -1) | |
3669 | error (_("Invalid register name `%s' " | |
3670 | "on expression `%s'."), | |
3671 | index, p->saved_arg); | |
3672 | ||
3673 | if (*s != ',' && *s != ')') | |
3674 | break; | |
3675 | ||
3676 | if (*s == ',') | |
3677 | { | |
3678 | ++s; | |
3679 | if (*s == '+') | |
3680 | ++s; | |
3681 | else if (*s == '-') | |
3682 | { | |
3683 | ++s; | |
3684 | size_minus = 1; | |
3685 | } | |
3686 | ||
3687 | size = strtol (s, (char **) &s, 10); | |
3688 | ||
3689 | if (*s != ')') | |
3690 | break; | |
3691 | } | |
3692 | ||
3693 | ++s; | |
3694 | ||
3695 | if (offset) | |
3696 | { | |
3697 | write_exp_elt_opcode (OP_LONG); | |
3698 | write_exp_elt_type | |
3699 | (builtin_type (gdbarch)->builtin_long); | |
3700 | write_exp_elt_longcst (offset); | |
3701 | write_exp_elt_opcode (OP_LONG); | |
3702 | if (offset_minus) | |
3703 | write_exp_elt_opcode (UNOP_NEG); | |
3704 | } | |
3705 | ||
3706 | write_exp_elt_opcode (OP_REGISTER); | |
3707 | base_token.ptr = base; | |
3708 | base_token.length = len_base; | |
3709 | write_exp_string (base_token); | |
3710 | write_exp_elt_opcode (OP_REGISTER); | |
3711 | ||
3712 | if (offset) | |
3713 | write_exp_elt_opcode (BINOP_ADD); | |
3714 | ||
3715 | write_exp_elt_opcode (OP_REGISTER); | |
3716 | index_token.ptr = index; | |
3717 | index_token.length = len_index; | |
3718 | write_exp_string (index_token); | |
3719 | write_exp_elt_opcode (OP_REGISTER); | |
3720 | ||
3721 | if (size) | |
3722 | { | |
3723 | write_exp_elt_opcode (OP_LONG); | |
3724 | write_exp_elt_type | |
3725 | (builtin_type (gdbarch)->builtin_long); | |
3726 | write_exp_elt_longcst (size); | |
3727 | write_exp_elt_opcode (OP_LONG); | |
3728 | if (size_minus) | |
3729 | write_exp_elt_opcode (UNOP_NEG); | |
3730 | write_exp_elt_opcode (BINOP_MUL); | |
3731 | } | |
3732 | ||
3733 | write_exp_elt_opcode (BINOP_ADD); | |
3734 | ||
3735 | write_exp_elt_opcode (UNOP_CAST); | |
3736 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3737 | write_exp_elt_opcode (UNOP_CAST); | |
3738 | ||
3739 | write_exp_elt_opcode (UNOP_IND); | |
3740 | ||
3741 | p->arg = s; | |
3742 | ||
3743 | return 1; | |
3744 | } | |
3745 | break; | |
3746 | } | |
3747 | } | |
3748 | ||
3749 | /* Advancing to the next state. */ | |
3750 | ++current_state; | |
3751 | } | |
3752 | ||
3753 | return 0; | |
3754 | } | |
3755 | ||
8201327c | 3756 | \f |
3ce1502b | 3757 | |
8201327c | 3758 | /* Generic ELF. */ |
d2a7c97a | 3759 | |
8201327c MK |
3760 | void |
3761 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3762 | { | |
c4fc7f1b MK |
3763 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3764 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
3765 | |
3766 | /* Registering SystemTap handlers. */ | |
3767 | set_gdbarch_stap_integer_prefix (gdbarch, "$"); | |
3768 | set_gdbarch_stap_register_prefix (gdbarch, "%"); | |
3769 | set_gdbarch_stap_register_indirection_prefix (gdbarch, "("); | |
3770 | set_gdbarch_stap_register_indirection_suffix (gdbarch, ")"); | |
3771 | set_gdbarch_stap_is_single_operand (gdbarch, | |
3772 | i386_stap_is_single_operand); | |
3773 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3774 | i386_stap_parse_special_token); | |
8201327c | 3775 | } |
3ce1502b | 3776 | |
8201327c | 3777 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3778 | |
8201327c MK |
3779 | void |
3780 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3781 | { | |
3782 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3783 | |
8201327c MK |
3784 | /* System V Release 4 uses ELF. */ |
3785 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3786 | |
dfe01d39 | 3787 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3788 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3789 | ||
911bc6ee | 3790 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3791 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3792 | tdep->sc_pc_offset = 36 + 14 * 4; |
3793 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3794 | |
8201327c | 3795 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3796 | } |
3797 | ||
8201327c | 3798 | /* DJGPP. */ |
3ce1502b | 3799 | |
3a1e71e3 | 3800 | static void |
8201327c | 3801 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3802 | { |
8201327c | 3803 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3804 | |
911bc6ee MK |
3805 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3806 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3807 | |
8201327c | 3808 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3809 | |
3810 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3811 | if (! tdesc_has_registers (info.target_desc)) |
3812 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3813 | |
3814 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3815 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3816 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3817 | set_gdbarch_sdb_reg_to_regnum. */ | |
3818 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3819 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3820 | |
3821 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3822 | } |
8201327c | 3823 | \f |
2acceee2 | 3824 | |
38c968cf AC |
3825 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3826 | and "sse". */ | |
3827 | ||
3828 | static struct reggroup *i386_sse_reggroup; | |
3829 | static struct reggroup *i386_mmx_reggroup; | |
3830 | ||
3831 | static void | |
3832 | i386_init_reggroups (void) | |
3833 | { | |
3834 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3835 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3836 | } | |
3837 | ||
3838 | static void | |
3839 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3840 | { | |
3841 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3842 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3843 | reggroup_add (gdbarch, general_reggroup); | |
3844 | reggroup_add (gdbarch, float_reggroup); | |
3845 | reggroup_add (gdbarch, all_reggroup); | |
3846 | reggroup_add (gdbarch, save_reggroup); | |
3847 | reggroup_add (gdbarch, restore_reggroup); | |
3848 | reggroup_add (gdbarch, vector_reggroup); | |
3849 | reggroup_add (gdbarch, system_reggroup); | |
3850 | } | |
3851 | ||
3852 | int | |
3853 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3854 | struct reggroup *group) | |
3855 | { | |
c131fcee L |
3856 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3857 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3858 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3859 | |
1ba53b71 L |
3860 | /* Don't include pseudo registers, except for MMX, in any register |
3861 | groups. */ | |
c131fcee | 3862 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3863 | return 0; |
3864 | ||
c131fcee | 3865 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3866 | return 0; |
3867 | ||
c131fcee | 3868 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3869 | return 0; |
3870 | ||
3871 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3872 | if (group == i386_mmx_reggroup) |
3873 | return mmx_regnum_p; | |
1ba53b71 | 3874 | |
c131fcee L |
3875 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3876 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3877 | if (group == i386_sse_reggroup) |
c131fcee L |
3878 | return xmm_regnum_p || mxcsr_regnum_p; |
3879 | ||
3880 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3881 | if (group == vector_reggroup) |
c131fcee L |
3882 | return (mmx_regnum_p |
3883 | || ymm_regnum_p | |
3884 | || mxcsr_regnum_p | |
3885 | || (xmm_regnum_p | |
3886 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3887 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3888 | |
3889 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3890 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3891 | if (group == float_reggroup) |
3892 | return fp_regnum_p; | |
1ba53b71 | 3893 | |
c131fcee L |
3894 | /* For "info reg all", don't include upper YMM registers nor XMM |
3895 | registers when AVX is supported. */ | |
3896 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3897 | if (group == all_reggroup | |
3898 | && ((xmm_regnum_p | |
3899 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3900 | || ymmh_regnum_p)) | |
3901 | return 0; | |
3902 | ||
38c968cf | 3903 | if (group == general_reggroup) |
1ba53b71 L |
3904 | return (!fp_regnum_p |
3905 | && !mmx_regnum_p | |
c131fcee L |
3906 | && !mxcsr_regnum_p |
3907 | && !xmm_regnum_p | |
3908 | && !ymm_regnum_p | |
3909 | && !ymmh_regnum_p); | |
acd5c798 | 3910 | |
38c968cf AC |
3911 | return default_register_reggroup_p (gdbarch, regnum, group); |
3912 | } | |
38c968cf | 3913 | \f |
acd5c798 | 3914 | |
f837910f MK |
3915 | /* Get the ARGIth function argument for the current function. */ |
3916 | ||
42c466d7 | 3917 | static CORE_ADDR |
143985b7 AF |
3918 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3919 | struct type *type) | |
3920 | { | |
e17a4113 UW |
3921 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3922 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 3923 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3924 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3925 | } |
3926 | ||
514f746b AR |
3927 | static void |
3928 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3929 | { | |
3930 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3931 | ||
3932 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3933 | adjust the PC in the regcache. */ | |
3934 | current_pc += 1; | |
3935 | regcache_write_pc (regcache, current_pc); | |
3936 | } | |
3937 | ||
3938 | ||
7ad10968 HZ |
3939 | #define PREFIX_REPZ 0x01 |
3940 | #define PREFIX_REPNZ 0x02 | |
3941 | #define PREFIX_LOCK 0x04 | |
3942 | #define PREFIX_DATA 0x08 | |
3943 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3944 | |
7ad10968 HZ |
3945 | /* operand size */ |
3946 | enum | |
3947 | { | |
3948 | OT_BYTE = 0, | |
3949 | OT_WORD, | |
3950 | OT_LONG, | |
cf648174 | 3951 | OT_QUAD, |
a3c4230a | 3952 | OT_DQUAD, |
7ad10968 | 3953 | }; |
473f17b0 | 3954 | |
7ad10968 HZ |
3955 | /* i386 arith/logic operations */ |
3956 | enum | |
3957 | { | |
3958 | OP_ADDL, | |
3959 | OP_ORL, | |
3960 | OP_ADCL, | |
3961 | OP_SBBL, | |
3962 | OP_ANDL, | |
3963 | OP_SUBL, | |
3964 | OP_XORL, | |
3965 | OP_CMPL, | |
3966 | }; | |
5716833c | 3967 | |
7ad10968 HZ |
3968 | struct i386_record_s |
3969 | { | |
cf648174 | 3970 | struct gdbarch *gdbarch; |
7ad10968 | 3971 | struct regcache *regcache; |
df61f520 | 3972 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3973 | CORE_ADDR addr; |
3974 | int aflag; | |
3975 | int dflag; | |
3976 | int override; | |
3977 | uint8_t modrm; | |
3978 | uint8_t mod, reg, rm; | |
3979 | int ot; | |
cf648174 HZ |
3980 | uint8_t rex_x; |
3981 | uint8_t rex_b; | |
3982 | int rip_offset; | |
3983 | int popl_esp_hack; | |
3984 | const int *regmap; | |
7ad10968 | 3985 | }; |
5716833c | 3986 | |
99c1624c PA |
3987 | /* Parse the "modrm" part of the memory address irp->addr points at. |
3988 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 3989 | |
7ad10968 HZ |
3990 | static int |
3991 | i386_record_modrm (struct i386_record_s *irp) | |
3992 | { | |
cf648174 | 3993 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3994 | |
4ffa4fc7 PA |
3995 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
3996 | return -1; | |
3997 | ||
7ad10968 HZ |
3998 | irp->addr++; |
3999 | irp->mod = (irp->modrm >> 6) & 3; | |
4000 | irp->reg = (irp->modrm >> 3) & 7; | |
4001 | irp->rm = irp->modrm & 7; | |
5716833c | 4002 | |
7ad10968 HZ |
4003 | return 0; |
4004 | } | |
d2a7c97a | 4005 | |
99c1624c PA |
4006 | /* Extract the memory address that the current instruction writes to, |
4007 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4008 | |
7ad10968 | 4009 | static int |
cf648174 | 4010 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4011 | { |
cf648174 | 4012 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4013 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4014 | gdb_byte buf[4]; | |
4015 | ULONGEST offset64; | |
21d0e8a4 | 4016 | |
7ad10968 HZ |
4017 | *addr = 0; |
4018 | if (irp->aflag) | |
4019 | { | |
4020 | /* 32 bits */ | |
4021 | int havesib = 0; | |
4022 | uint8_t scale = 0; | |
648d0c8b | 4023 | uint8_t byte; |
7ad10968 HZ |
4024 | uint8_t index = 0; |
4025 | uint8_t base = irp->rm; | |
896fb97d | 4026 | |
7ad10968 HZ |
4027 | if (base == 4) |
4028 | { | |
4029 | havesib = 1; | |
4ffa4fc7 PA |
4030 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4031 | return -1; | |
7ad10968 | 4032 | irp->addr++; |
648d0c8b MS |
4033 | scale = (byte >> 6) & 3; |
4034 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4035 | base = (byte & 7); | |
7ad10968 | 4036 | } |
cf648174 | 4037 | base |= irp->rex_b; |
21d0e8a4 | 4038 | |
7ad10968 HZ |
4039 | switch (irp->mod) |
4040 | { | |
4041 | case 0: | |
4042 | if ((base & 7) == 5) | |
4043 | { | |
4044 | base = 0xff; | |
4ffa4fc7 PA |
4045 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4046 | return -1; | |
7ad10968 | 4047 | irp->addr += 4; |
60a1502a | 4048 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4049 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4050 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4051 | } |
7ad10968 HZ |
4052 | break; |
4053 | case 1: | |
4ffa4fc7 PA |
4054 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4055 | return -1; | |
7ad10968 | 4056 | irp->addr++; |
60a1502a | 4057 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4058 | break; |
4059 | case 2: | |
4ffa4fc7 PA |
4060 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4061 | return -1; | |
60a1502a | 4062 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4063 | irp->addr += 4; |
4064 | break; | |
4065 | } | |
356a6b3e | 4066 | |
60a1502a | 4067 | offset64 = 0; |
7ad10968 | 4068 | if (base != 0xff) |
cf648174 HZ |
4069 | { |
4070 | if (base == 4 && irp->popl_esp_hack) | |
4071 | *addr += irp->popl_esp_hack; | |
4072 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4073 | &offset64); |
7ad10968 | 4074 | } |
cf648174 HZ |
4075 | if (irp->aflag == 2) |
4076 | { | |
60a1502a | 4077 | *addr += offset64; |
cf648174 HZ |
4078 | } |
4079 | else | |
60a1502a | 4080 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4081 | |
7ad10968 HZ |
4082 | if (havesib && (index != 4 || scale != 0)) |
4083 | { | |
cf648174 | 4084 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4085 | &offset64); |
cf648174 | 4086 | if (irp->aflag == 2) |
60a1502a | 4087 | *addr += offset64 << scale; |
cf648174 | 4088 | else |
60a1502a | 4089 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
4090 | } |
4091 | } | |
4092 | else | |
4093 | { | |
4094 | /* 16 bits */ | |
4095 | switch (irp->mod) | |
4096 | { | |
4097 | case 0: | |
4098 | if (irp->rm == 6) | |
4099 | { | |
4ffa4fc7 PA |
4100 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4101 | return -1; | |
7ad10968 | 4102 | irp->addr += 2; |
60a1502a | 4103 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4104 | irp->rm = 0; |
4105 | goto no_rm; | |
4106 | } | |
7ad10968 HZ |
4107 | break; |
4108 | case 1: | |
4ffa4fc7 PA |
4109 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4110 | return -1; | |
7ad10968 | 4111 | irp->addr++; |
60a1502a | 4112 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4113 | break; |
4114 | case 2: | |
4ffa4fc7 PA |
4115 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4116 | return -1; | |
7ad10968 | 4117 | irp->addr += 2; |
60a1502a | 4118 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4119 | break; |
4120 | } | |
c4fc7f1b | 4121 | |
7ad10968 HZ |
4122 | switch (irp->rm) |
4123 | { | |
4124 | case 0: | |
cf648174 HZ |
4125 | regcache_raw_read_unsigned (irp->regcache, |
4126 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4127 | &offset64); |
4128 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4129 | regcache_raw_read_unsigned (irp->regcache, |
4130 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4131 | &offset64); |
4132 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4133 | break; |
4134 | case 1: | |
cf648174 HZ |
4135 | regcache_raw_read_unsigned (irp->regcache, |
4136 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4137 | &offset64); |
4138 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4139 | regcache_raw_read_unsigned (irp->regcache, |
4140 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4141 | &offset64); |
4142 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4143 | break; |
4144 | case 2: | |
cf648174 HZ |
4145 | regcache_raw_read_unsigned (irp->regcache, |
4146 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4147 | &offset64); |
4148 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4149 | regcache_raw_read_unsigned (irp->regcache, |
4150 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4151 | &offset64); |
4152 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4153 | break; |
4154 | case 3: | |
cf648174 HZ |
4155 | regcache_raw_read_unsigned (irp->regcache, |
4156 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4157 | &offset64); |
4158 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4159 | regcache_raw_read_unsigned (irp->regcache, |
4160 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4161 | &offset64); |
4162 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4163 | break; |
4164 | case 4: | |
cf648174 HZ |
4165 | regcache_raw_read_unsigned (irp->regcache, |
4166 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4167 | &offset64); |
4168 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4169 | break; |
4170 | case 5: | |
cf648174 HZ |
4171 | regcache_raw_read_unsigned (irp->regcache, |
4172 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4173 | &offset64); |
4174 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4175 | break; |
4176 | case 6: | |
cf648174 HZ |
4177 | regcache_raw_read_unsigned (irp->regcache, |
4178 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4179 | &offset64); |
4180 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4181 | break; |
4182 | case 7: | |
cf648174 HZ |
4183 | regcache_raw_read_unsigned (irp->regcache, |
4184 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4185 | &offset64); |
4186 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4187 | break; |
4188 | } | |
4189 | *addr &= 0xffff; | |
4190 | } | |
c4fc7f1b | 4191 | |
01fe1b41 | 4192 | no_rm: |
7ad10968 HZ |
4193 | return 0; |
4194 | } | |
c4fc7f1b | 4195 | |
99c1624c PA |
4196 | /* Record the address and contents of the memory that will be changed |
4197 | by the current instruction. Return -1 if something goes wrong, 0 | |
4198 | otherwise. */ | |
356a6b3e | 4199 | |
7ad10968 HZ |
4200 | static int |
4201 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4202 | { | |
cf648174 HZ |
4203 | struct gdbarch *gdbarch = irp->gdbarch; |
4204 | uint64_t addr; | |
356a6b3e | 4205 | |
d7877f7e | 4206 | if (irp->override >= 0) |
7ad10968 | 4207 | { |
25ea693b | 4208 | if (record_full_memory_query) |
bb08c432 HZ |
4209 | { |
4210 | int q; | |
4211 | ||
4212 | target_terminal_ours (); | |
4213 | q = yquery (_("\ | |
4214 | Process record ignores the memory change of instruction at address %s\n\ | |
4215 | because it can't get the value of the segment register.\n\ | |
4216 | Do you want to stop the program?"), | |
4217 | paddress (gdbarch, irp->orig_addr)); | |
4218 | target_terminal_inferior (); | |
4219 | if (q) | |
4220 | return -1; | |
4221 | } | |
4222 | ||
7ad10968 HZ |
4223 | return 0; |
4224 | } | |
61113f8b | 4225 | |
7ad10968 HZ |
4226 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4227 | return -1; | |
96297dab | 4228 | |
25ea693b | 4229 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4230 | return -1; |
a62cc96e | 4231 | |
7ad10968 HZ |
4232 | return 0; |
4233 | } | |
b6197528 | 4234 | |
99c1624c PA |
4235 | /* Record the effects of a push operation. Return -1 if something |
4236 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4237 | |
4238 | static int | |
4239 | i386_record_push (struct i386_record_s *irp, int size) | |
4240 | { | |
648d0c8b | 4241 | ULONGEST addr; |
cf648174 | 4242 | |
25ea693b MM |
4243 | if (record_full_arch_list_add_reg (irp->regcache, |
4244 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4245 | return -1; |
4246 | regcache_raw_read_unsigned (irp->regcache, | |
4247 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4248 | &addr); |
25ea693b | 4249 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4250 | return -1; |
4251 | ||
4252 | return 0; | |
4253 | } | |
4254 | ||
0289bdd7 MS |
4255 | |
4256 | /* Defines contents to record. */ | |
4257 | #define I386_SAVE_FPU_REGS 0xfffd | |
4258 | #define I386_SAVE_FPU_ENV 0xfffe | |
4259 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4260 | ||
99c1624c PA |
4261 | /* Record the values of the floating point registers which will be |
4262 | changed by the current instruction. Returns -1 if something is | |
4263 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4264 | |
4265 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4266 | struct i386_record_s *ir, | |
4267 | uint32_t iregnum) | |
4268 | { | |
4269 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4270 | int i; | |
4271 | ||
4272 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4273 | happen. Currently we store st0-st7 registers, but we need not store all | |
4274 | registers all the time, in future we use ftag register and record only | |
4275 | those who are not marked as an empty. */ | |
4276 | ||
4277 | if (I386_SAVE_FPU_REGS == iregnum) | |
4278 | { | |
4279 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4280 | { | |
25ea693b | 4281 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4282 | return -1; |
4283 | } | |
4284 | } | |
4285 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4286 | { | |
4287 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4288 | { | |
25ea693b | 4289 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4290 | return -1; |
4291 | } | |
4292 | } | |
4293 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4294 | { | |
4295 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4296 | { | |
25ea693b | 4297 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4298 | return -1; |
4299 | } | |
4300 | } | |
4301 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4302 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4303 | { | |
25ea693b | 4304 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4305 | return -1; |
4306 | } | |
4307 | else | |
4308 | { | |
4309 | /* Parameter error. */ | |
4310 | return -1; | |
4311 | } | |
4312 | if(I386_SAVE_FPU_ENV != iregnum) | |
4313 | { | |
4314 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4315 | { | |
25ea693b | 4316 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4317 | return -1; |
4318 | } | |
4319 | } | |
4320 | return 0; | |
4321 | } | |
4322 | ||
99c1624c PA |
4323 | /* Parse the current instruction, and record the values of the |
4324 | registers and memory that will be changed by the current | |
4325 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4326 | |
25ea693b MM |
4327 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
4328 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 4329 | |
a6b808b4 | 4330 | int |
7ad10968 | 4331 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4332 | CORE_ADDR input_addr) |
7ad10968 | 4333 | { |
60a1502a | 4334 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4335 | int prefixes = 0; |
580879fc | 4336 | int regnum = 0; |
425b824a | 4337 | uint32_t opcode; |
f4644a3f | 4338 | uint8_t opcode8; |
648d0c8b | 4339 | ULONGEST addr; |
60a1502a | 4340 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4341 | struct i386_record_s ir; |
0289bdd7 | 4342 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4343 | uint8_t rex_w = -1; |
4344 | uint8_t rex_r = 0; | |
7ad10968 | 4345 | |
8408d274 | 4346 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4347 | ir.regcache = regcache; |
648d0c8b MS |
4348 | ir.addr = input_addr; |
4349 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4350 | ir.aflag = 1; |
4351 | ir.dflag = 1; | |
cf648174 HZ |
4352 | ir.override = -1; |
4353 | ir.popl_esp_hack = 0; | |
a3c4230a | 4354 | ir.regmap = tdep->record_regmap; |
cf648174 | 4355 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4356 | |
4357 | if (record_debug > 1) | |
4358 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4359 | "addr = %s\n", |
4360 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4361 | |
4362 | /* prefixes */ | |
4363 | while (1) | |
4364 | { | |
4ffa4fc7 PA |
4365 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4366 | return -1; | |
7ad10968 | 4367 | ir.addr++; |
425b824a | 4368 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4369 | { |
01fe1b41 | 4370 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4371 | prefixes |= PREFIX_REPZ; |
4372 | break; | |
01fe1b41 | 4373 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4374 | prefixes |= PREFIX_REPNZ; |
4375 | break; | |
01fe1b41 | 4376 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4377 | prefixes |= PREFIX_LOCK; |
4378 | break; | |
01fe1b41 | 4379 | case CS_PREFIX_OPCODE: |
cf648174 | 4380 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4381 | break; |
01fe1b41 | 4382 | case SS_PREFIX_OPCODE: |
cf648174 | 4383 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4384 | break; |
01fe1b41 | 4385 | case DS_PREFIX_OPCODE: |
cf648174 | 4386 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4387 | break; |
01fe1b41 | 4388 | case ES_PREFIX_OPCODE: |
cf648174 | 4389 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4390 | break; |
01fe1b41 | 4391 | case FS_PREFIX_OPCODE: |
cf648174 | 4392 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4393 | break; |
01fe1b41 | 4394 | case GS_PREFIX_OPCODE: |
cf648174 | 4395 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4396 | break; |
01fe1b41 | 4397 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4398 | prefixes |= PREFIX_DATA; |
4399 | break; | |
01fe1b41 | 4400 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4401 | prefixes |= PREFIX_ADDR; |
4402 | break; | |
d691bec7 MS |
4403 | case 0x40: /* i386 inc %eax */ |
4404 | case 0x41: /* i386 inc %ecx */ | |
4405 | case 0x42: /* i386 inc %edx */ | |
4406 | case 0x43: /* i386 inc %ebx */ | |
4407 | case 0x44: /* i386 inc %esp */ | |
4408 | case 0x45: /* i386 inc %ebp */ | |
4409 | case 0x46: /* i386 inc %esi */ | |
4410 | case 0x47: /* i386 inc %edi */ | |
4411 | case 0x48: /* i386 dec %eax */ | |
4412 | case 0x49: /* i386 dec %ecx */ | |
4413 | case 0x4a: /* i386 dec %edx */ | |
4414 | case 0x4b: /* i386 dec %ebx */ | |
4415 | case 0x4c: /* i386 dec %esp */ | |
4416 | case 0x4d: /* i386 dec %ebp */ | |
4417 | case 0x4e: /* i386 dec %esi */ | |
4418 | case 0x4f: /* i386 dec %edi */ | |
4419 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4420 | { |
4421 | /* REX */ | |
425b824a MS |
4422 | rex_w = (opcode8 >> 3) & 1; |
4423 | rex_r = (opcode8 & 0x4) << 1; | |
4424 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4425 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4426 | } |
d691bec7 MS |
4427 | else /* 32 bit target */ |
4428 | goto out_prefixes; | |
cf648174 | 4429 | break; |
7ad10968 HZ |
4430 | default: |
4431 | goto out_prefixes; | |
4432 | break; | |
4433 | } | |
4434 | } | |
01fe1b41 | 4435 | out_prefixes: |
cf648174 HZ |
4436 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4437 | { | |
4438 | ir.dflag = 2; | |
4439 | } | |
4440 | else | |
4441 | { | |
4442 | if (prefixes & PREFIX_DATA) | |
4443 | ir.dflag ^= 1; | |
4444 | } | |
7ad10968 HZ |
4445 | if (prefixes & PREFIX_ADDR) |
4446 | ir.aflag ^= 1; | |
cf648174 HZ |
4447 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4448 | ir.aflag = 2; | |
7ad10968 | 4449 | |
1777feb0 | 4450 | /* Now check op code. */ |
425b824a | 4451 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4452 | reswitch: |
7ad10968 HZ |
4453 | switch (opcode) |
4454 | { | |
4455 | case 0x0f: | |
4ffa4fc7 PA |
4456 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4457 | return -1; | |
7ad10968 | 4458 | ir.addr++; |
a3c4230a | 4459 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4460 | goto reswitch; |
4461 | break; | |
93924b6b | 4462 | |
a38bba38 | 4463 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4464 | case 0x01: |
4465 | case 0x02: | |
4466 | case 0x03: | |
4467 | case 0x04: | |
4468 | case 0x05: | |
4469 | case 0x08: | |
4470 | case 0x09: | |
4471 | case 0x0a: | |
4472 | case 0x0b: | |
4473 | case 0x0c: | |
4474 | case 0x0d: | |
4475 | case 0x10: | |
4476 | case 0x11: | |
4477 | case 0x12: | |
4478 | case 0x13: | |
4479 | case 0x14: | |
4480 | case 0x15: | |
4481 | case 0x18: | |
4482 | case 0x19: | |
4483 | case 0x1a: | |
4484 | case 0x1b: | |
4485 | case 0x1c: | |
4486 | case 0x1d: | |
4487 | case 0x20: | |
4488 | case 0x21: | |
4489 | case 0x22: | |
4490 | case 0x23: | |
4491 | case 0x24: | |
4492 | case 0x25: | |
4493 | case 0x28: | |
4494 | case 0x29: | |
4495 | case 0x2a: | |
4496 | case 0x2b: | |
4497 | case 0x2c: | |
4498 | case 0x2d: | |
4499 | case 0x30: | |
4500 | case 0x31: | |
4501 | case 0x32: | |
4502 | case 0x33: | |
4503 | case 0x34: | |
4504 | case 0x35: | |
4505 | case 0x38: | |
4506 | case 0x39: | |
4507 | case 0x3a: | |
4508 | case 0x3b: | |
4509 | case 0x3c: | |
4510 | case 0x3d: | |
4511 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4512 | { | |
4513 | if ((opcode & 1) == 0) | |
4514 | ir.ot = OT_BYTE; | |
4515 | else | |
4516 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4517 | |
7ad10968 HZ |
4518 | switch ((opcode >> 1) & 3) |
4519 | { | |
a38bba38 | 4520 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4521 | if (i386_record_modrm (&ir)) |
4522 | return -1; | |
4523 | if (ir.mod != 3) | |
4524 | { | |
4525 | if (i386_record_lea_modrm (&ir)) | |
4526 | return -1; | |
4527 | } | |
4528 | else | |
4529 | { | |
cf648174 HZ |
4530 | ir.rm |= ir.rex_b; |
4531 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4532 | ir.rm &= 0x3; |
25ea693b | 4533 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4534 | } |
4535 | break; | |
a38bba38 | 4536 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4537 | if (i386_record_modrm (&ir)) |
4538 | return -1; | |
cf648174 HZ |
4539 | ir.reg |= rex_r; |
4540 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4541 | ir.reg &= 0x3; |
25ea693b | 4542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4543 | break; |
a38bba38 | 4544 | case 2: /* OP A, Iv */ |
25ea693b | 4545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4546 | break; |
4547 | } | |
4548 | } | |
25ea693b | 4549 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4550 | break; |
42fdc8df | 4551 | |
a38bba38 | 4552 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4553 | case 0x81: |
4554 | case 0x82: | |
4555 | case 0x83: | |
4556 | if (i386_record_modrm (&ir)) | |
4557 | return -1; | |
8201327c | 4558 | |
7ad10968 HZ |
4559 | if (ir.reg != OP_CMPL) |
4560 | { | |
4561 | if ((opcode & 1) == 0) | |
4562 | ir.ot = OT_BYTE; | |
4563 | else | |
4564 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4565 | |
7ad10968 HZ |
4566 | if (ir.mod != 3) |
4567 | { | |
cf648174 HZ |
4568 | if (opcode == 0x83) |
4569 | ir.rip_offset = 1; | |
4570 | else | |
4571 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4572 | if (i386_record_lea_modrm (&ir)) |
4573 | return -1; | |
4574 | } | |
4575 | else | |
25ea693b | 4576 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4577 | } |
25ea693b | 4578 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4579 | break; |
5e3397bb | 4580 | |
a38bba38 | 4581 | case 0x40: /* inc */ |
7ad10968 HZ |
4582 | case 0x41: |
4583 | case 0x42: | |
4584 | case 0x43: | |
4585 | case 0x44: | |
4586 | case 0x45: | |
4587 | case 0x46: | |
4588 | case 0x47: | |
a38bba38 MS |
4589 | |
4590 | case 0x48: /* dec */ | |
7ad10968 HZ |
4591 | case 0x49: |
4592 | case 0x4a: | |
4593 | case 0x4b: | |
4594 | case 0x4c: | |
4595 | case 0x4d: | |
4596 | case 0x4e: | |
4597 | case 0x4f: | |
a38bba38 | 4598 | |
25ea693b MM |
4599 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
4600 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4601 | break; |
acd5c798 | 4602 | |
a38bba38 | 4603 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4604 | case 0xf7: |
4605 | if ((opcode & 1) == 0) | |
4606 | ir.ot = OT_BYTE; | |
4607 | else | |
4608 | ir.ot = ir.dflag + OT_WORD; | |
4609 | if (i386_record_modrm (&ir)) | |
4610 | return -1; | |
acd5c798 | 4611 | |
cf648174 HZ |
4612 | if (ir.mod != 3 && ir.reg == 0) |
4613 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4614 | ||
7ad10968 HZ |
4615 | switch (ir.reg) |
4616 | { | |
a38bba38 | 4617 | case 0: /* test */ |
25ea693b | 4618 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4619 | break; |
a38bba38 MS |
4620 | case 2: /* not */ |
4621 | case 3: /* neg */ | |
7ad10968 HZ |
4622 | if (ir.mod != 3) |
4623 | { | |
4624 | if (i386_record_lea_modrm (&ir)) | |
4625 | return -1; | |
4626 | } | |
4627 | else | |
4628 | { | |
cf648174 HZ |
4629 | ir.rm |= ir.rex_b; |
4630 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4631 | ir.rm &= 0x3; |
25ea693b | 4632 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4633 | } |
a38bba38 | 4634 | if (ir.reg == 3) /* neg */ |
25ea693b | 4635 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4636 | break; |
a38bba38 MS |
4637 | case 4: /* mul */ |
4638 | case 5: /* imul */ | |
4639 | case 6: /* div */ | |
4640 | case 7: /* idiv */ | |
25ea693b | 4641 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4642 | if (ir.ot != OT_BYTE) |
25ea693b MM |
4643 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4644 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4645 | break; |
4646 | default: | |
4647 | ir.addr -= 2; | |
4648 | opcode = opcode << 8 | ir.modrm; | |
4649 | goto no_support; | |
4650 | break; | |
4651 | } | |
4652 | break; | |
4653 | ||
a38bba38 MS |
4654 | case 0xfe: /* GRP4 */ |
4655 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4656 | if (i386_record_modrm (&ir)) |
4657 | return -1; | |
4658 | if (ir.reg >= 2 && opcode == 0xfe) | |
4659 | { | |
4660 | ir.addr -= 2; | |
4661 | opcode = opcode << 8 | ir.modrm; | |
4662 | goto no_support; | |
4663 | } | |
7ad10968 HZ |
4664 | switch (ir.reg) |
4665 | { | |
a38bba38 MS |
4666 | case 0: /* inc */ |
4667 | case 1: /* dec */ | |
cf648174 HZ |
4668 | if ((opcode & 1) == 0) |
4669 | ir.ot = OT_BYTE; | |
4670 | else | |
4671 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4672 | if (ir.mod != 3) |
4673 | { | |
4674 | if (i386_record_lea_modrm (&ir)) | |
4675 | return -1; | |
4676 | } | |
4677 | else | |
4678 | { | |
cf648174 HZ |
4679 | ir.rm |= ir.rex_b; |
4680 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4681 | ir.rm &= 0x3; |
25ea693b | 4682 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4683 | } |
25ea693b | 4684 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4685 | break; |
a38bba38 | 4686 | case 2: /* call */ |
cf648174 HZ |
4687 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4688 | ir.dflag = 2; | |
4689 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4690 | return -1; |
25ea693b | 4691 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4692 | break; |
a38bba38 | 4693 | case 3: /* lcall */ |
25ea693b | 4694 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 4695 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 4696 | return -1; |
25ea693b | 4697 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4698 | break; |
a38bba38 MS |
4699 | case 4: /* jmp */ |
4700 | case 5: /* ljmp */ | |
25ea693b | 4701 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 4702 | break; |
a38bba38 | 4703 | case 6: /* push */ |
cf648174 HZ |
4704 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4705 | ir.dflag = 2; | |
4706 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4707 | return -1; | |
7ad10968 HZ |
4708 | break; |
4709 | default: | |
4710 | ir.addr -= 2; | |
4711 | opcode = opcode << 8 | ir.modrm; | |
4712 | goto no_support; | |
4713 | break; | |
4714 | } | |
4715 | break; | |
4716 | ||
a38bba38 | 4717 | case 0x84: /* test */ |
7ad10968 HZ |
4718 | case 0x85: |
4719 | case 0xa8: | |
4720 | case 0xa9: | |
25ea693b | 4721 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4722 | break; |
4723 | ||
a38bba38 | 4724 | case 0x98: /* CWDE/CBW */ |
25ea693b | 4725 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4726 | break; |
4727 | ||
a38bba38 | 4728 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
4729 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4730 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4731 | break; |
4732 | ||
a38bba38 | 4733 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4734 | case 0x69: |
4735 | case 0x6b: | |
4736 | ir.ot = ir.dflag + OT_WORD; | |
4737 | if (i386_record_modrm (&ir)) | |
4738 | return -1; | |
cf648174 HZ |
4739 | if (opcode == 0x69) |
4740 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4741 | else if (opcode == 0x6b) | |
4742 | ir.rip_offset = 1; | |
4743 | ir.reg |= rex_r; | |
4744 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4745 | ir.reg &= 0x3; |
25ea693b MM |
4746 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
4747 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4748 | break; |
4749 | ||
a38bba38 | 4750 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4751 | case 0x0fc1: |
4752 | if ((opcode & 1) == 0) | |
4753 | ir.ot = OT_BYTE; | |
4754 | else | |
4755 | ir.ot = ir.dflag + OT_WORD; | |
4756 | if (i386_record_modrm (&ir)) | |
4757 | return -1; | |
cf648174 | 4758 | ir.reg |= rex_r; |
7ad10968 HZ |
4759 | if (ir.mod == 3) |
4760 | { | |
cf648174 | 4761 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4762 | ir.reg &= 0x3; |
25ea693b | 4763 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 4764 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4765 | ir.rm &= 0x3; |
25ea693b | 4766 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4767 | } |
4768 | else | |
4769 | { | |
4770 | if (i386_record_lea_modrm (&ir)) | |
4771 | return -1; | |
cf648174 | 4772 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4773 | ir.reg &= 0x3; |
25ea693b | 4774 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4775 | } |
25ea693b | 4776 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4777 | break; |
4778 | ||
a38bba38 | 4779 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4780 | case 0x0fb1: |
4781 | if ((opcode & 1) == 0) | |
4782 | ir.ot = OT_BYTE; | |
4783 | else | |
4784 | ir.ot = ir.dflag + OT_WORD; | |
4785 | if (i386_record_modrm (&ir)) | |
4786 | return -1; | |
4787 | if (ir.mod == 3) | |
4788 | { | |
cf648174 | 4789 | ir.reg |= rex_r; |
25ea693b | 4790 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 4791 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4792 | ir.reg &= 0x3; |
25ea693b | 4793 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4794 | } |
4795 | else | |
4796 | { | |
25ea693b | 4797 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4798 | if (i386_record_lea_modrm (&ir)) |
4799 | return -1; | |
4800 | } | |
25ea693b | 4801 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4802 | break; |
4803 | ||
a38bba38 | 4804 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4805 | if (i386_record_modrm (&ir)) |
4806 | return -1; | |
4807 | if (ir.mod == 3) | |
4808 | { | |
4809 | ir.addr -= 2; | |
4810 | opcode = opcode << 8 | ir.modrm; | |
4811 | goto no_support; | |
4812 | } | |
25ea693b MM |
4813 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4814 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4815 | if (i386_record_lea_modrm (&ir)) |
4816 | return -1; | |
25ea693b | 4817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4818 | break; |
4819 | ||
a38bba38 | 4820 | case 0x50: /* push */ |
7ad10968 HZ |
4821 | case 0x51: |
4822 | case 0x52: | |
4823 | case 0x53: | |
4824 | case 0x54: | |
4825 | case 0x55: | |
4826 | case 0x56: | |
4827 | case 0x57: | |
4828 | case 0x68: | |
4829 | case 0x6a: | |
cf648174 HZ |
4830 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4831 | ir.dflag = 2; | |
4832 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4833 | return -1; | |
4834 | break; | |
4835 | ||
a38bba38 MS |
4836 | case 0x06: /* push es */ |
4837 | case 0x0e: /* push cs */ | |
4838 | case 0x16: /* push ss */ | |
4839 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4840 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4841 | { | |
4842 | ir.addr -= 1; | |
4843 | goto no_support; | |
4844 | } | |
4845 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4846 | return -1; | |
4847 | break; | |
4848 | ||
a38bba38 MS |
4849 | case 0x0fa0: /* push fs */ |
4850 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4851 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4852 | { | |
4853 | ir.addr -= 2; | |
4854 | goto no_support; | |
4855 | } | |
4856 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4857 | return -1; |
cf648174 HZ |
4858 | break; |
4859 | ||
a38bba38 | 4860 | case 0x60: /* pusha */ |
cf648174 HZ |
4861 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4862 | { | |
4863 | ir.addr -= 1; | |
4864 | goto no_support; | |
4865 | } | |
4866 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4867 | return -1; |
4868 | break; | |
4869 | ||
a38bba38 | 4870 | case 0x58: /* pop */ |
7ad10968 HZ |
4871 | case 0x59: |
4872 | case 0x5a: | |
4873 | case 0x5b: | |
4874 | case 0x5c: | |
4875 | case 0x5d: | |
4876 | case 0x5e: | |
4877 | case 0x5f: | |
25ea693b MM |
4878 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4879 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4880 | break; |
4881 | ||
a38bba38 | 4882 | case 0x61: /* popa */ |
cf648174 HZ |
4883 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4884 | { | |
4885 | ir.addr -= 1; | |
4886 | goto no_support; | |
7ad10968 | 4887 | } |
425b824a MS |
4888 | for (regnum = X86_RECORD_REAX_REGNUM; |
4889 | regnum <= X86_RECORD_REDI_REGNUM; | |
4890 | regnum++) | |
25ea693b | 4891 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
4892 | break; |
4893 | ||
a38bba38 | 4894 | case 0x8f: /* pop */ |
cf648174 HZ |
4895 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4896 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4897 | else | |
4898 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4899 | if (i386_record_modrm (&ir)) |
4900 | return -1; | |
4901 | if (ir.mod == 3) | |
25ea693b | 4902 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4903 | else |
4904 | { | |
cf648174 | 4905 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4906 | if (i386_record_lea_modrm (&ir)) |
4907 | return -1; | |
4908 | } | |
25ea693b | 4909 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4910 | break; |
4911 | ||
a38bba38 | 4912 | case 0xc8: /* enter */ |
25ea693b | 4913 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
4914 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4915 | ir.dflag = 2; | |
4916 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4917 | return -1; |
4918 | break; | |
4919 | ||
a38bba38 | 4920 | case 0xc9: /* leave */ |
25ea693b MM |
4921 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4922 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4923 | break; |
4924 | ||
a38bba38 | 4925 | case 0x07: /* pop es */ |
cf648174 HZ |
4926 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4927 | { | |
4928 | ir.addr -= 1; | |
4929 | goto no_support; | |
4930 | } | |
25ea693b MM |
4931 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4932 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4933 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4934 | break; |
4935 | ||
a38bba38 | 4936 | case 0x17: /* pop ss */ |
cf648174 HZ |
4937 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4938 | { | |
4939 | ir.addr -= 1; | |
4940 | goto no_support; | |
4941 | } | |
25ea693b MM |
4942 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4943 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4944 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4945 | break; |
4946 | ||
a38bba38 | 4947 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4948 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4949 | { | |
4950 | ir.addr -= 1; | |
4951 | goto no_support; | |
4952 | } | |
25ea693b MM |
4953 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4954 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4955 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4956 | break; |
4957 | ||
a38bba38 | 4958 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
4959 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4960 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4961 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4962 | break; |
4963 | ||
a38bba38 | 4964 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
4965 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4966 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4967 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4968 | break; |
4969 | ||
a38bba38 | 4970 | case 0x88: /* mov */ |
7ad10968 HZ |
4971 | case 0x89: |
4972 | case 0xc6: | |
4973 | case 0xc7: | |
4974 | if ((opcode & 1) == 0) | |
4975 | ir.ot = OT_BYTE; | |
4976 | else | |
4977 | ir.ot = ir.dflag + OT_WORD; | |
4978 | ||
4979 | if (i386_record_modrm (&ir)) | |
4980 | return -1; | |
4981 | ||
4982 | if (ir.mod != 3) | |
4983 | { | |
cf648174 HZ |
4984 | if (opcode == 0xc6 || opcode == 0xc7) |
4985 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4986 | if (i386_record_lea_modrm (&ir)) |
4987 | return -1; | |
4988 | } | |
4989 | else | |
4990 | { | |
cf648174 HZ |
4991 | if (opcode == 0xc6 || opcode == 0xc7) |
4992 | ir.rm |= ir.rex_b; | |
4993 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4994 | ir.rm &= 0x3; |
25ea693b | 4995 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4996 | } |
7ad10968 | 4997 | break; |
cf648174 | 4998 | |
a38bba38 | 4999 | case 0x8a: /* mov */ |
7ad10968 HZ |
5000 | case 0x8b: |
5001 | if ((opcode & 1) == 0) | |
5002 | ir.ot = OT_BYTE; | |
5003 | else | |
5004 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5005 | if (i386_record_modrm (&ir)) |
5006 | return -1; | |
cf648174 HZ |
5007 | ir.reg |= rex_r; |
5008 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5009 | ir.reg &= 0x3; |
25ea693b | 5010 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5011 | break; |
7ad10968 | 5012 | |
a38bba38 | 5013 | case 0x8c: /* mov seg */ |
cf648174 | 5014 | if (i386_record_modrm (&ir)) |
7ad10968 | 5015 | return -1; |
cf648174 HZ |
5016 | if (ir.reg > 5) |
5017 | { | |
5018 | ir.addr -= 2; | |
5019 | opcode = opcode << 8 | ir.modrm; | |
5020 | goto no_support; | |
5021 | } | |
5022 | ||
5023 | if (ir.mod == 3) | |
25ea693b | 5024 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5025 | else |
5026 | { | |
5027 | ir.ot = OT_WORD; | |
5028 | if (i386_record_lea_modrm (&ir)) | |
5029 | return -1; | |
5030 | } | |
7ad10968 HZ |
5031 | break; |
5032 | ||
a38bba38 | 5033 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5034 | if (i386_record_modrm (&ir)) |
5035 | return -1; | |
7ad10968 HZ |
5036 | switch (ir.reg) |
5037 | { | |
5038 | case 0: | |
425b824a | 5039 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5040 | break; |
5041 | case 2: | |
425b824a | 5042 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5043 | break; |
5044 | case 3: | |
425b824a | 5045 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5046 | break; |
5047 | case 4: | |
425b824a | 5048 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5049 | break; |
5050 | case 5: | |
425b824a | 5051 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5052 | break; |
5053 | default: | |
5054 | ir.addr -= 2; | |
5055 | opcode = opcode << 8 | ir.modrm; | |
5056 | goto no_support; | |
5057 | break; | |
5058 | } | |
25ea693b MM |
5059 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5060 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5061 | break; |
5062 | ||
a38bba38 MS |
5063 | case 0x0fb6: /* movzbS */ |
5064 | case 0x0fb7: /* movzwS */ | |
5065 | case 0x0fbe: /* movsbS */ | |
5066 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5067 | if (i386_record_modrm (&ir)) |
5068 | return -1; | |
25ea693b | 5069 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5070 | break; |
5071 | ||
a38bba38 | 5072 | case 0x8d: /* lea */ |
7ad10968 HZ |
5073 | if (i386_record_modrm (&ir)) |
5074 | return -1; | |
5075 | if (ir.mod == 3) | |
5076 | { | |
5077 | ir.addr -= 2; | |
5078 | opcode = opcode << 8 | ir.modrm; | |
5079 | goto no_support; | |
5080 | } | |
7ad10968 | 5081 | ir.ot = ir.dflag; |
cf648174 HZ |
5082 | ir.reg |= rex_r; |
5083 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5084 | ir.reg &= 0x3; |
25ea693b | 5085 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5086 | break; |
5087 | ||
a38bba38 | 5088 | case 0xa0: /* mov EAX */ |
7ad10968 | 5089 | case 0xa1: |
a38bba38 MS |
5090 | |
5091 | case 0xd7: /* xlat */ | |
25ea693b | 5092 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5093 | break; |
5094 | ||
a38bba38 | 5095 | case 0xa2: /* mov EAX */ |
7ad10968 | 5096 | case 0xa3: |
d7877f7e | 5097 | if (ir.override >= 0) |
cf648174 | 5098 | { |
25ea693b | 5099 | if (record_full_memory_query) |
bb08c432 HZ |
5100 | { |
5101 | int q; | |
5102 | ||
5103 | target_terminal_ours (); | |
5104 | q = yquery (_("\ | |
5105 | Process record ignores the memory change of instruction at address %s\n\ | |
5106 | because it can't get the value of the segment register.\n\ | |
5107 | Do you want to stop the program?"), | |
5108 | paddress (gdbarch, ir.orig_addr)); | |
5109 | target_terminal_inferior (); | |
5110 | if (q) | |
5111 | return -1; | |
5112 | } | |
cf648174 HZ |
5113 | } |
5114 | else | |
5115 | { | |
5116 | if ((opcode & 1) == 0) | |
5117 | ir.ot = OT_BYTE; | |
5118 | else | |
5119 | ir.ot = ir.dflag + OT_WORD; | |
5120 | if (ir.aflag == 2) | |
5121 | { | |
4ffa4fc7 PA |
5122 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5123 | return -1; | |
cf648174 | 5124 | ir.addr += 8; |
60a1502a | 5125 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5126 | } |
5127 | else if (ir.aflag) | |
5128 | { | |
4ffa4fc7 PA |
5129 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5130 | return -1; | |
cf648174 | 5131 | ir.addr += 4; |
60a1502a | 5132 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5133 | } |
5134 | else | |
5135 | { | |
4ffa4fc7 PA |
5136 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5137 | return -1; | |
cf648174 | 5138 | ir.addr += 2; |
60a1502a | 5139 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5140 | } |
25ea693b | 5141 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5142 | return -1; |
5143 | } | |
7ad10968 HZ |
5144 | break; |
5145 | ||
a38bba38 | 5146 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5147 | case 0xb1: |
5148 | case 0xb2: | |
5149 | case 0xb3: | |
5150 | case 0xb4: | |
5151 | case 0xb5: | |
5152 | case 0xb6: | |
5153 | case 0xb7: | |
25ea693b MM |
5154 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5155 | ? ((opcode & 0x7) | ir.rex_b) | |
5156 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5157 | break; |
5158 | ||
a38bba38 | 5159 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5160 | case 0xb9: |
5161 | case 0xba: | |
5162 | case 0xbb: | |
5163 | case 0xbc: | |
5164 | case 0xbd: | |
5165 | case 0xbe: | |
5166 | case 0xbf: | |
25ea693b | 5167 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5168 | break; |
5169 | ||
a38bba38 | 5170 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5171 | case 0x92: |
5172 | case 0x93: | |
5173 | case 0x94: | |
5174 | case 0x95: | |
5175 | case 0x96: | |
5176 | case 0x97: | |
25ea693b MM |
5177 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5178 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5179 | break; |
5180 | ||
a38bba38 | 5181 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5182 | case 0x87: |
5183 | if ((opcode & 1) == 0) | |
5184 | ir.ot = OT_BYTE; | |
5185 | else | |
5186 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5187 | if (i386_record_modrm (&ir)) |
5188 | return -1; | |
7ad10968 HZ |
5189 | if (ir.mod == 3) |
5190 | { | |
86839d38 | 5191 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5192 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5193 | ir.rm &= 0x3; | |
25ea693b | 5194 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5195 | } |
5196 | else | |
5197 | { | |
5198 | if (i386_record_lea_modrm (&ir)) | |
5199 | return -1; | |
5200 | } | |
cf648174 HZ |
5201 | ir.reg |= rex_r; |
5202 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5203 | ir.reg &= 0x3; |
25ea693b | 5204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5205 | break; |
5206 | ||
a38bba38 MS |
5207 | case 0xc4: /* les Gv */ |
5208 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5209 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5210 | { | |
5211 | ir.addr -= 1; | |
5212 | goto no_support; | |
5213 | } | |
d3f323f3 | 5214 | /* FALLTHROUGH */ |
a38bba38 MS |
5215 | case 0x0fb2: /* lss Gv */ |
5216 | case 0x0fb4: /* lfs Gv */ | |
5217 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5218 | if (i386_record_modrm (&ir)) |
5219 | return -1; | |
5220 | if (ir.mod == 3) | |
5221 | { | |
5222 | if (opcode > 0xff) | |
5223 | ir.addr -= 3; | |
5224 | else | |
5225 | ir.addr -= 2; | |
5226 | opcode = opcode << 8 | ir.modrm; | |
5227 | goto no_support; | |
5228 | } | |
7ad10968 HZ |
5229 | switch (opcode) |
5230 | { | |
a38bba38 | 5231 | case 0xc4: /* les Gv */ |
425b824a | 5232 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5233 | break; |
a38bba38 | 5234 | case 0xc5: /* lds Gv */ |
425b824a | 5235 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5236 | break; |
a38bba38 | 5237 | case 0x0fb2: /* lss Gv */ |
425b824a | 5238 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5239 | break; |
a38bba38 | 5240 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5241 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5242 | break; |
a38bba38 | 5243 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5244 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5245 | break; |
5246 | } | |
25ea693b MM |
5247 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5248 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5249 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5250 | break; |
5251 | ||
a38bba38 | 5252 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5253 | case 0xc1: |
5254 | case 0xd0: | |
5255 | case 0xd1: | |
5256 | case 0xd2: | |
5257 | case 0xd3: | |
5258 | if ((opcode & 1) == 0) | |
5259 | ir.ot = OT_BYTE; | |
5260 | else | |
5261 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5262 | if (i386_record_modrm (&ir)) |
5263 | return -1; | |
7ad10968 HZ |
5264 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5265 | { | |
5266 | if (i386_record_lea_modrm (&ir)) | |
5267 | return -1; | |
5268 | } | |
5269 | else | |
5270 | { | |
cf648174 HZ |
5271 | ir.rm |= ir.rex_b; |
5272 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5273 | ir.rm &= 0x3; |
25ea693b | 5274 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5275 | } |
25ea693b | 5276 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5277 | break; |
5278 | ||
5279 | case 0x0fa4: | |
5280 | case 0x0fa5: | |
5281 | case 0x0fac: | |
5282 | case 0x0fad: | |
5283 | if (i386_record_modrm (&ir)) | |
5284 | return -1; | |
5285 | if (ir.mod == 3) | |
5286 | { | |
25ea693b | 5287 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5288 | return -1; |
5289 | } | |
5290 | else | |
5291 | { | |
5292 | if (i386_record_lea_modrm (&ir)) | |
5293 | return -1; | |
5294 | } | |
5295 | break; | |
5296 | ||
a38bba38 | 5297 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5298 | case 0xd9: |
5299 | case 0xda: | |
5300 | case 0xdb: | |
5301 | case 0xdc: | |
5302 | case 0xdd: | |
5303 | case 0xde: | |
5304 | case 0xdf: | |
5305 | if (i386_record_modrm (&ir)) | |
5306 | return -1; | |
5307 | ir.reg |= ((opcode & 7) << 3); | |
5308 | if (ir.mod != 3) | |
5309 | { | |
1777feb0 | 5310 | /* Memory. */ |
955db0c0 | 5311 | uint64_t addr64; |
7ad10968 | 5312 | |
955db0c0 | 5313 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5314 | return -1; |
5315 | switch (ir.reg) | |
5316 | { | |
7ad10968 | 5317 | case 0x02: |
0289bdd7 MS |
5318 | case 0x12: |
5319 | case 0x22: | |
5320 | case 0x32: | |
5321 | /* For fcom, ficom nothing to do. */ | |
5322 | break; | |
7ad10968 | 5323 | case 0x03: |
0289bdd7 MS |
5324 | case 0x13: |
5325 | case 0x23: | |
5326 | case 0x33: | |
5327 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5328 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5329 | return -1; | |
5330 | break; | |
5331 | case 0x00: | |
5332 | case 0x01: | |
7ad10968 HZ |
5333 | case 0x04: |
5334 | case 0x05: | |
5335 | case 0x06: | |
5336 | case 0x07: | |
5337 | case 0x10: | |
5338 | case 0x11: | |
7ad10968 HZ |
5339 | case 0x14: |
5340 | case 0x15: | |
5341 | case 0x16: | |
5342 | case 0x17: | |
5343 | case 0x20: | |
5344 | case 0x21: | |
7ad10968 HZ |
5345 | case 0x24: |
5346 | case 0x25: | |
5347 | case 0x26: | |
5348 | case 0x27: | |
5349 | case 0x30: | |
5350 | case 0x31: | |
7ad10968 HZ |
5351 | case 0x34: |
5352 | case 0x35: | |
5353 | case 0x36: | |
5354 | case 0x37: | |
0289bdd7 MS |
5355 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5356 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5357 | of code, always affects st(0) register. */ | |
5358 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5359 | return -1; | |
7ad10968 HZ |
5360 | break; |
5361 | case 0x08: | |
5362 | case 0x0a: | |
5363 | case 0x0b: | |
5364 | case 0x18: | |
5365 | case 0x19: | |
5366 | case 0x1a: | |
5367 | case 0x1b: | |
0289bdd7 | 5368 | case 0x1d: |
7ad10968 HZ |
5369 | case 0x28: |
5370 | case 0x29: | |
5371 | case 0x2a: | |
5372 | case 0x2b: | |
5373 | case 0x38: | |
5374 | case 0x39: | |
5375 | case 0x3a: | |
5376 | case 0x3b: | |
0289bdd7 MS |
5377 | case 0x3c: |
5378 | case 0x3d: | |
7ad10968 HZ |
5379 | switch (ir.reg & 7) |
5380 | { | |
5381 | case 0: | |
0289bdd7 MS |
5382 | /* Handling fld, fild. */ |
5383 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5384 | return -1; | |
7ad10968 HZ |
5385 | break; |
5386 | case 1: | |
5387 | switch (ir.reg >> 4) | |
5388 | { | |
5389 | case 0: | |
25ea693b | 5390 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5391 | return -1; |
5392 | break; | |
5393 | case 2: | |
25ea693b | 5394 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5395 | return -1; |
5396 | break; | |
5397 | case 3: | |
0289bdd7 | 5398 | break; |
7ad10968 | 5399 | default: |
25ea693b | 5400 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5401 | return -1; |
5402 | break; | |
5403 | } | |
5404 | break; | |
5405 | default: | |
5406 | switch (ir.reg >> 4) | |
5407 | { | |
5408 | case 0: | |
25ea693b | 5409 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5410 | return -1; |
5411 | if (3 == (ir.reg & 7)) | |
5412 | { | |
5413 | /* For fstp m32fp. */ | |
5414 | if (i386_record_floats (gdbarch, &ir, | |
5415 | I386_SAVE_FPU_REGS)) | |
5416 | return -1; | |
5417 | } | |
5418 | break; | |
7ad10968 | 5419 | case 1: |
25ea693b | 5420 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5421 | return -1; |
0289bdd7 MS |
5422 | if ((3 == (ir.reg & 7)) |
5423 | || (5 == (ir.reg & 7)) | |
5424 | || (7 == (ir.reg & 7))) | |
5425 | { | |
5426 | /* For fstp insn. */ | |
5427 | if (i386_record_floats (gdbarch, &ir, | |
5428 | I386_SAVE_FPU_REGS)) | |
5429 | return -1; | |
5430 | } | |
7ad10968 HZ |
5431 | break; |
5432 | case 2: | |
25ea693b | 5433 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5434 | return -1; |
0289bdd7 MS |
5435 | if (3 == (ir.reg & 7)) |
5436 | { | |
5437 | /* For fstp m64fp. */ | |
5438 | if (i386_record_floats (gdbarch, &ir, | |
5439 | I386_SAVE_FPU_REGS)) | |
5440 | return -1; | |
5441 | } | |
7ad10968 HZ |
5442 | break; |
5443 | case 3: | |
0289bdd7 MS |
5444 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5445 | { | |
5446 | /* For fistp, fbld, fild, fbstp. */ | |
5447 | if (i386_record_floats (gdbarch, &ir, | |
5448 | I386_SAVE_FPU_REGS)) | |
5449 | return -1; | |
5450 | } | |
5451 | /* Fall through */ | |
7ad10968 | 5452 | default: |
25ea693b | 5453 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5454 | return -1; |
5455 | break; | |
5456 | } | |
5457 | break; | |
5458 | } | |
5459 | break; | |
5460 | case 0x0c: | |
0289bdd7 MS |
5461 | /* Insn fldenv. */ |
5462 | if (i386_record_floats (gdbarch, &ir, | |
5463 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5464 | return -1; | |
5465 | break; | |
7ad10968 | 5466 | case 0x0d: |
0289bdd7 MS |
5467 | /* Insn fldcw. */ |
5468 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5469 | return -1; | |
5470 | break; | |
7ad10968 | 5471 | case 0x2c: |
0289bdd7 MS |
5472 | /* Insn frstor. */ |
5473 | if (i386_record_floats (gdbarch, &ir, | |
5474 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5475 | return -1; | |
7ad10968 HZ |
5476 | break; |
5477 | case 0x0e: | |
5478 | if (ir.dflag) | |
5479 | { | |
25ea693b | 5480 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5481 | return -1; |
5482 | } | |
5483 | else | |
5484 | { | |
25ea693b | 5485 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5486 | return -1; |
5487 | } | |
5488 | break; | |
5489 | case 0x0f: | |
5490 | case 0x2f: | |
25ea693b | 5491 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5492 | return -1; |
0289bdd7 MS |
5493 | /* Insn fstp, fbstp. */ |
5494 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5495 | return -1; | |
7ad10968 HZ |
5496 | break; |
5497 | case 0x1f: | |
5498 | case 0x3e: | |
25ea693b | 5499 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5500 | return -1; |
5501 | break; | |
5502 | case 0x2e: | |
5503 | if (ir.dflag) | |
5504 | { | |
25ea693b | 5505 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5506 | return -1; |
955db0c0 | 5507 | addr64 += 28; |
7ad10968 HZ |
5508 | } |
5509 | else | |
5510 | { | |
25ea693b | 5511 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5512 | return -1; |
955db0c0 | 5513 | addr64 += 14; |
7ad10968 | 5514 | } |
25ea693b | 5515 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5516 | return -1; |
0289bdd7 MS |
5517 | /* Insn fsave. */ |
5518 | if (i386_record_floats (gdbarch, &ir, | |
5519 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5520 | return -1; | |
7ad10968 HZ |
5521 | break; |
5522 | case 0x3f: | |
25ea693b | 5523 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5524 | return -1; |
0289bdd7 MS |
5525 | /* Insn fistp. */ |
5526 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5527 | return -1; | |
7ad10968 HZ |
5528 | break; |
5529 | default: | |
5530 | ir.addr -= 2; | |
5531 | opcode = opcode << 8 | ir.modrm; | |
5532 | goto no_support; | |
5533 | break; | |
5534 | } | |
5535 | } | |
0289bdd7 MS |
5536 | /* Opcode is an extension of modR/M byte. */ |
5537 | else | |
5538 | { | |
5539 | switch (opcode) | |
5540 | { | |
5541 | case 0xd8: | |
5542 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5543 | return -1; | |
5544 | break; | |
5545 | case 0xd9: | |
5546 | if (0x0c == (ir.modrm >> 4)) | |
5547 | { | |
5548 | if ((ir.modrm & 0x0f) <= 7) | |
5549 | { | |
5550 | if (i386_record_floats (gdbarch, &ir, | |
5551 | I386_SAVE_FPU_REGS)) | |
5552 | return -1; | |
5553 | } | |
5554 | else | |
5555 | { | |
5556 | if (i386_record_floats (gdbarch, &ir, | |
5557 | I387_ST0_REGNUM (tdep))) | |
5558 | return -1; | |
5559 | /* If only st(0) is changing, then we have already | |
5560 | recorded. */ | |
5561 | if ((ir.modrm & 0x0f) - 0x08) | |
5562 | { | |
5563 | if (i386_record_floats (gdbarch, &ir, | |
5564 | I387_ST0_REGNUM (tdep) + | |
5565 | ((ir.modrm & 0x0f) - 0x08))) | |
5566 | return -1; | |
5567 | } | |
5568 | } | |
5569 | } | |
5570 | else | |
5571 | { | |
5572 | switch (ir.modrm) | |
5573 | { | |
5574 | case 0xe0: | |
5575 | case 0xe1: | |
5576 | case 0xf0: | |
5577 | case 0xf5: | |
5578 | case 0xf8: | |
5579 | case 0xfa: | |
5580 | case 0xfc: | |
5581 | case 0xfe: | |
5582 | case 0xff: | |
5583 | if (i386_record_floats (gdbarch, &ir, | |
5584 | I387_ST0_REGNUM (tdep))) | |
5585 | return -1; | |
5586 | break; | |
5587 | case 0xf1: | |
5588 | case 0xf2: | |
5589 | case 0xf3: | |
5590 | case 0xf4: | |
5591 | case 0xf6: | |
5592 | case 0xf7: | |
5593 | case 0xe8: | |
5594 | case 0xe9: | |
5595 | case 0xea: | |
5596 | case 0xeb: | |
5597 | case 0xec: | |
5598 | case 0xed: | |
5599 | case 0xee: | |
5600 | case 0xf9: | |
5601 | case 0xfb: | |
5602 | if (i386_record_floats (gdbarch, &ir, | |
5603 | I386_SAVE_FPU_REGS)) | |
5604 | return -1; | |
5605 | break; | |
5606 | case 0xfd: | |
5607 | if (i386_record_floats (gdbarch, &ir, | |
5608 | I387_ST0_REGNUM (tdep))) | |
5609 | return -1; | |
5610 | if (i386_record_floats (gdbarch, &ir, | |
5611 | I387_ST0_REGNUM (tdep) + 1)) | |
5612 | return -1; | |
5613 | break; | |
5614 | } | |
5615 | } | |
5616 | break; | |
5617 | case 0xda: | |
5618 | if (0xe9 == ir.modrm) | |
5619 | { | |
5620 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5621 | return -1; | |
5622 | } | |
5623 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5624 | { | |
5625 | if (i386_record_floats (gdbarch, &ir, | |
5626 | I387_ST0_REGNUM (tdep))) | |
5627 | return -1; | |
5628 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5629 | { | |
5630 | if (i386_record_floats (gdbarch, &ir, | |
5631 | I387_ST0_REGNUM (tdep) + | |
5632 | (ir.modrm & 0x0f))) | |
5633 | return -1; | |
5634 | } | |
5635 | else if ((ir.modrm & 0x0f) - 0x08) | |
5636 | { | |
5637 | if (i386_record_floats (gdbarch, &ir, | |
5638 | I387_ST0_REGNUM (tdep) + | |
5639 | ((ir.modrm & 0x0f) - 0x08))) | |
5640 | return -1; | |
5641 | } | |
5642 | } | |
5643 | break; | |
5644 | case 0xdb: | |
5645 | if (0xe3 == ir.modrm) | |
5646 | { | |
5647 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5648 | return -1; | |
5649 | } | |
5650 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5651 | { | |
5652 | if (i386_record_floats (gdbarch, &ir, | |
5653 | I387_ST0_REGNUM (tdep))) | |
5654 | return -1; | |
5655 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5656 | { | |
5657 | if (i386_record_floats (gdbarch, &ir, | |
5658 | I387_ST0_REGNUM (tdep) + | |
5659 | (ir.modrm & 0x0f))) | |
5660 | return -1; | |
5661 | } | |
5662 | else if ((ir.modrm & 0x0f) - 0x08) | |
5663 | { | |
5664 | if (i386_record_floats (gdbarch, &ir, | |
5665 | I387_ST0_REGNUM (tdep) + | |
5666 | ((ir.modrm & 0x0f) - 0x08))) | |
5667 | return -1; | |
5668 | } | |
5669 | } | |
5670 | break; | |
5671 | case 0xdc: | |
5672 | if ((0x0c == ir.modrm >> 4) | |
5673 | || (0x0d == ir.modrm >> 4) | |
5674 | || (0x0f == ir.modrm >> 4)) | |
5675 | { | |
5676 | if ((ir.modrm & 0x0f) <= 7) | |
5677 | { | |
5678 | if (i386_record_floats (gdbarch, &ir, | |
5679 | I387_ST0_REGNUM (tdep) + | |
5680 | (ir.modrm & 0x0f))) | |
5681 | return -1; | |
5682 | } | |
5683 | else | |
5684 | { | |
5685 | if (i386_record_floats (gdbarch, &ir, | |
5686 | I387_ST0_REGNUM (tdep) + | |
5687 | ((ir.modrm & 0x0f) - 0x08))) | |
5688 | return -1; | |
5689 | } | |
5690 | } | |
5691 | break; | |
5692 | case 0xdd: | |
5693 | if (0x0c == ir.modrm >> 4) | |
5694 | { | |
5695 | if (i386_record_floats (gdbarch, &ir, | |
5696 | I387_FTAG_REGNUM (tdep))) | |
5697 | return -1; | |
5698 | } | |
5699 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5700 | { | |
5701 | if ((ir.modrm & 0x0f) <= 7) | |
5702 | { | |
5703 | if (i386_record_floats (gdbarch, &ir, | |
5704 | I387_ST0_REGNUM (tdep) + | |
5705 | (ir.modrm & 0x0f))) | |
5706 | return -1; | |
5707 | } | |
5708 | else | |
5709 | { | |
5710 | if (i386_record_floats (gdbarch, &ir, | |
5711 | I386_SAVE_FPU_REGS)) | |
5712 | return -1; | |
5713 | } | |
5714 | } | |
5715 | break; | |
5716 | case 0xde: | |
5717 | if ((0x0c == ir.modrm >> 4) | |
5718 | || (0x0e == ir.modrm >> 4) | |
5719 | || (0x0f == ir.modrm >> 4) | |
5720 | || (0xd9 == ir.modrm)) | |
5721 | { | |
5722 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5723 | return -1; | |
5724 | } | |
5725 | break; | |
5726 | case 0xdf: | |
5727 | if (0xe0 == ir.modrm) | |
5728 | { | |
25ea693b MM |
5729 | if (record_full_arch_list_add_reg (ir.regcache, |
5730 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
5731 | return -1; |
5732 | } | |
5733 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5734 | { | |
5735 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5736 | return -1; | |
5737 | } | |
5738 | break; | |
5739 | } | |
5740 | } | |
7ad10968 | 5741 | break; |
7ad10968 | 5742 | /* string ops */ |
a38bba38 | 5743 | case 0xa4: /* movsS */ |
7ad10968 | 5744 | case 0xa5: |
a38bba38 | 5745 | case 0xaa: /* stosS */ |
7ad10968 | 5746 | case 0xab: |
a38bba38 | 5747 | case 0x6c: /* insS */ |
7ad10968 | 5748 | case 0x6d: |
cf648174 | 5749 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5750 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5751 | &addr); |
5752 | if (addr) | |
cf648174 | 5753 | { |
77d7dc92 HZ |
5754 | ULONGEST es, ds; |
5755 | ||
5756 | if ((opcode & 1) == 0) | |
5757 | ir.ot = OT_BYTE; | |
5758 | else | |
5759 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5760 | regcache_raw_read_unsigned (ir.regcache, |
5761 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5762 | &addr); |
77d7dc92 | 5763 | |
d7877f7e HZ |
5764 | regcache_raw_read_unsigned (ir.regcache, |
5765 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5766 | &es); | |
5767 | regcache_raw_read_unsigned (ir.regcache, | |
5768 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5769 | &ds); | |
5770 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5771 | { |
5772 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 5773 | if (record_full_memory_query) |
bb08c432 HZ |
5774 | { |
5775 | int q; | |
5776 | ||
5777 | target_terminal_ours (); | |
5778 | q = yquery (_("\ | |
5779 | Process record ignores the memory change of instruction at address %s\n\ | |
5780 | because it can't get the value of the segment register.\n\ | |
5781 | Do you want to stop the program?"), | |
5782 | paddress (gdbarch, ir.orig_addr)); | |
5783 | target_terminal_inferior (); | |
5784 | if (q) | |
5785 | return -1; | |
5786 | } | |
df61f520 HZ |
5787 | } |
5788 | else | |
5789 | { | |
25ea693b | 5790 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5791 | return -1; |
77d7dc92 HZ |
5792 | } |
5793 | ||
5794 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 5795 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 5796 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
5797 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
5798 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5799 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 5800 | } |
cf648174 | 5801 | break; |
7ad10968 | 5802 | |
a38bba38 | 5803 | case 0xa6: /* cmpsS */ |
cf648174 | 5804 | case 0xa7: |
25ea693b MM |
5805 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
5806 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 5807 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
5808 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5809 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5810 | break; |
5811 | ||
a38bba38 | 5812 | case 0xac: /* lodsS */ |
7ad10968 | 5813 | case 0xad: |
25ea693b MM |
5814 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5815 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5816 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
5817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5818 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5819 | break; |
5820 | ||
a38bba38 | 5821 | case 0xae: /* scasS */ |
7ad10968 | 5822 | case 0xaf: |
25ea693b | 5823 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5824 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
5825 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5826 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5827 | break; |
5828 | ||
a38bba38 | 5829 | case 0x6e: /* outsS */ |
cf648174 | 5830 | case 0x6f: |
25ea693b | 5831 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 5832 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
5833 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5834 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5835 | break; |
5836 | ||
a38bba38 | 5837 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5838 | case 0xe5: |
5839 | case 0xec: | |
5840 | case 0xed: | |
25ea693b MM |
5841 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5842 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5843 | break; |
5844 | ||
5845 | case 0xe6: | |
5846 | case 0xe7: | |
5847 | case 0xee: | |
5848 | case 0xef: | |
5849 | break; | |
5850 | ||
5851 | /* control */ | |
a38bba38 MS |
5852 | case 0xc2: /* ret im */ |
5853 | case 0xc3: /* ret */ | |
25ea693b MM |
5854 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5855 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
5856 | break; |
5857 | ||
a38bba38 MS |
5858 | case 0xca: /* lret im */ |
5859 | case 0xcb: /* lret */ | |
5860 | case 0xcf: /* iret */ | |
25ea693b MM |
5861 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5862 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5863 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5864 | break; |
5865 | ||
a38bba38 | 5866 | case 0xe8: /* call im */ |
cf648174 HZ |
5867 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5868 | ir.dflag = 2; | |
5869 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5870 | return -1; | |
7ad10968 HZ |
5871 | break; |
5872 | ||
a38bba38 | 5873 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5874 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5875 | { | |
5876 | ir.addr -= 1; | |
5877 | goto no_support; | |
5878 | } | |
25ea693b | 5879 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
5880 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5881 | return -1; | |
7ad10968 HZ |
5882 | break; |
5883 | ||
a38bba38 MS |
5884 | case 0xe9: /* jmp im */ |
5885 | case 0xea: /* ljmp im */ | |
5886 | case 0xeb: /* jmp Jb */ | |
5887 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5888 | case 0x71: |
5889 | case 0x72: | |
5890 | case 0x73: | |
5891 | case 0x74: | |
5892 | case 0x75: | |
5893 | case 0x76: | |
5894 | case 0x77: | |
5895 | case 0x78: | |
5896 | case 0x79: | |
5897 | case 0x7a: | |
5898 | case 0x7b: | |
5899 | case 0x7c: | |
5900 | case 0x7d: | |
5901 | case 0x7e: | |
5902 | case 0x7f: | |
a38bba38 | 5903 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5904 | case 0x0f81: |
5905 | case 0x0f82: | |
5906 | case 0x0f83: | |
5907 | case 0x0f84: | |
5908 | case 0x0f85: | |
5909 | case 0x0f86: | |
5910 | case 0x0f87: | |
5911 | case 0x0f88: | |
5912 | case 0x0f89: | |
5913 | case 0x0f8a: | |
5914 | case 0x0f8b: | |
5915 | case 0x0f8c: | |
5916 | case 0x0f8d: | |
5917 | case 0x0f8e: | |
5918 | case 0x0f8f: | |
5919 | break; | |
5920 | ||
a38bba38 | 5921 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5922 | case 0x0f91: |
5923 | case 0x0f92: | |
5924 | case 0x0f93: | |
5925 | case 0x0f94: | |
5926 | case 0x0f95: | |
5927 | case 0x0f96: | |
5928 | case 0x0f97: | |
5929 | case 0x0f98: | |
5930 | case 0x0f99: | |
5931 | case 0x0f9a: | |
5932 | case 0x0f9b: | |
5933 | case 0x0f9c: | |
5934 | case 0x0f9d: | |
5935 | case 0x0f9e: | |
5936 | case 0x0f9f: | |
25ea693b | 5937 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5938 | ir.ot = OT_BYTE; |
5939 | if (i386_record_modrm (&ir)) | |
5940 | return -1; | |
5941 | if (ir.mod == 3) | |
25ea693b MM |
5942 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5943 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5944 | else |
5945 | { | |
5946 | if (i386_record_lea_modrm (&ir)) | |
5947 | return -1; | |
5948 | } | |
5949 | break; | |
5950 | ||
a38bba38 | 5951 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5952 | case 0x0f41: |
5953 | case 0x0f42: | |
5954 | case 0x0f43: | |
5955 | case 0x0f44: | |
5956 | case 0x0f45: | |
5957 | case 0x0f46: | |
5958 | case 0x0f47: | |
5959 | case 0x0f48: | |
5960 | case 0x0f49: | |
5961 | case 0x0f4a: | |
5962 | case 0x0f4b: | |
5963 | case 0x0f4c: | |
5964 | case 0x0f4d: | |
5965 | case 0x0f4e: | |
5966 | case 0x0f4f: | |
5967 | if (i386_record_modrm (&ir)) | |
5968 | return -1; | |
cf648174 | 5969 | ir.reg |= rex_r; |
7ad10968 HZ |
5970 | if (ir.dflag == OT_BYTE) |
5971 | ir.reg &= 0x3; | |
25ea693b | 5972 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5973 | break; |
5974 | ||
5975 | /* flags */ | |
a38bba38 | 5976 | case 0x9c: /* pushf */ |
25ea693b | 5977 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
5978 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5979 | ir.dflag = 2; | |
5980 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5981 | return -1; | |
7ad10968 HZ |
5982 | break; |
5983 | ||
a38bba38 | 5984 | case 0x9d: /* popf */ |
25ea693b MM |
5985 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5986 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5987 | break; |
5988 | ||
a38bba38 | 5989 | case 0x9e: /* sahf */ |
cf648174 HZ |
5990 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5991 | { | |
5992 | ir.addr -= 1; | |
5993 | goto no_support; | |
5994 | } | |
d3f323f3 | 5995 | /* FALLTHROUGH */ |
a38bba38 MS |
5996 | case 0xf5: /* cmc */ |
5997 | case 0xf8: /* clc */ | |
5998 | case 0xf9: /* stc */ | |
5999 | case 0xfc: /* cld */ | |
6000 | case 0xfd: /* std */ | |
25ea693b | 6001 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6002 | break; |
6003 | ||
a38bba38 | 6004 | case 0x9f: /* lahf */ |
cf648174 HZ |
6005 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6006 | { | |
6007 | ir.addr -= 1; | |
6008 | goto no_support; | |
6009 | } | |
25ea693b MM |
6010 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6011 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6012 | break; |
6013 | ||
6014 | /* bit operations */ | |
a38bba38 | 6015 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6016 | ir.ot = ir.dflag + OT_WORD; |
6017 | if (i386_record_modrm (&ir)) | |
6018 | return -1; | |
6019 | if (ir.reg < 4) | |
6020 | { | |
cf648174 | 6021 | ir.addr -= 2; |
7ad10968 HZ |
6022 | opcode = opcode << 8 | ir.modrm; |
6023 | goto no_support; | |
6024 | } | |
cf648174 | 6025 | if (ir.reg != 4) |
7ad10968 | 6026 | { |
cf648174 | 6027 | if (ir.mod == 3) |
25ea693b | 6028 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6029 | else |
6030 | { | |
cf648174 | 6031 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6032 | return -1; |
6033 | } | |
6034 | } | |
25ea693b | 6035 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6036 | break; |
6037 | ||
a38bba38 | 6038 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6039 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6040 | break; |
6041 | ||
a38bba38 MS |
6042 | case 0x0fab: /* bts */ |
6043 | case 0x0fb3: /* btr */ | |
6044 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6045 | ir.ot = ir.dflag + OT_WORD; |
6046 | if (i386_record_modrm (&ir)) | |
6047 | return -1; | |
6048 | if (ir.mod == 3) | |
25ea693b | 6049 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6050 | else |
6051 | { | |
955db0c0 MS |
6052 | uint64_t addr64; |
6053 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6054 | return -1; |
6055 | regcache_raw_read_unsigned (ir.regcache, | |
6056 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6057 | &addr); |
cf648174 HZ |
6058 | switch (ir.dflag) |
6059 | { | |
6060 | case 0: | |
648d0c8b | 6061 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6062 | break; |
6063 | case 1: | |
648d0c8b | 6064 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6065 | break; |
6066 | case 2: | |
648d0c8b | 6067 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6068 | break; |
6069 | } | |
25ea693b | 6070 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6071 | return -1; |
6072 | if (i386_record_lea_modrm (&ir)) | |
6073 | return -1; | |
6074 | } | |
25ea693b | 6075 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6076 | break; |
6077 | ||
a38bba38 MS |
6078 | case 0x0fbc: /* bsf */ |
6079 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6080 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6081 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6082 | break; |
6083 | ||
6084 | /* bcd */ | |
a38bba38 MS |
6085 | case 0x27: /* daa */ |
6086 | case 0x2f: /* das */ | |
6087 | case 0x37: /* aaa */ | |
6088 | case 0x3f: /* aas */ | |
6089 | case 0xd4: /* aam */ | |
6090 | case 0xd5: /* aad */ | |
cf648174 HZ |
6091 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6092 | { | |
6093 | ir.addr -= 1; | |
6094 | goto no_support; | |
6095 | } | |
25ea693b MM |
6096 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6097 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6098 | break; |
6099 | ||
6100 | /* misc */ | |
a38bba38 | 6101 | case 0x90: /* nop */ |
7ad10968 HZ |
6102 | if (prefixes & PREFIX_LOCK) |
6103 | { | |
6104 | ir.addr -= 1; | |
6105 | goto no_support; | |
6106 | } | |
6107 | break; | |
6108 | ||
a38bba38 | 6109 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6110 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6111 | return -1; | |
425b824a | 6112 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6113 | ir.addr++; |
6114 | goto reswitch; | |
7ad10968 HZ |
6115 | break; |
6116 | ||
7ad10968 | 6117 | /* XXX */ |
a38bba38 | 6118 | case 0xcc: /* int3 */ |
a3c4230a | 6119 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6120 | "int3.\n")); |
6121 | ir.addr -= 1; | |
6122 | goto no_support; | |
6123 | break; | |
6124 | ||
7ad10968 | 6125 | /* XXX */ |
a38bba38 | 6126 | case 0xcd: /* int */ |
7ad10968 HZ |
6127 | { |
6128 | int ret; | |
425b824a | 6129 | uint8_t interrupt; |
4ffa4fc7 PA |
6130 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6131 | return -1; | |
7ad10968 | 6132 | ir.addr++; |
425b824a | 6133 | if (interrupt != 0x80 |
a3c4230a | 6134 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6135 | { |
a3c4230a | 6136 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6137 | "instruction int 0x%02x.\n"), |
425b824a | 6138 | interrupt); |
7ad10968 HZ |
6139 | ir.addr -= 2; |
6140 | goto no_support; | |
6141 | } | |
a3c4230a | 6142 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6143 | if (ret) |
6144 | return ret; | |
6145 | } | |
6146 | break; | |
6147 | ||
7ad10968 | 6148 | /* XXX */ |
a38bba38 | 6149 | case 0xce: /* into */ |
a3c4230a | 6150 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6151 | "instruction into.\n")); |
6152 | ir.addr -= 1; | |
6153 | goto no_support; | |
6154 | break; | |
6155 | ||
a38bba38 MS |
6156 | case 0xfa: /* cli */ |
6157 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6158 | break; |
6159 | ||
a38bba38 | 6160 | case 0x62: /* bound */ |
a3c4230a | 6161 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6162 | "instruction bound.\n")); |
6163 | ir.addr -= 1; | |
6164 | goto no_support; | |
6165 | break; | |
6166 | ||
a38bba38 | 6167 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6168 | case 0x0fc9: |
6169 | case 0x0fca: | |
6170 | case 0x0fcb: | |
6171 | case 0x0fcc: | |
6172 | case 0x0fcd: | |
6173 | case 0x0fce: | |
6174 | case 0x0fcf: | |
25ea693b | 6175 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6176 | break; |
6177 | ||
a38bba38 | 6178 | case 0xd6: /* salc */ |
cf648174 HZ |
6179 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6180 | { | |
6181 | ir.addr -= 1; | |
6182 | goto no_support; | |
6183 | } | |
25ea693b MM |
6184 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6185 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6186 | break; |
6187 | ||
a38bba38 MS |
6188 | case 0xe0: /* loopnz */ |
6189 | case 0xe1: /* loopz */ | |
6190 | case 0xe2: /* loop */ | |
6191 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6192 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6193 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6194 | break; |
6195 | ||
a38bba38 | 6196 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6197 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6198 | "instruction wrmsr.\n")); |
6199 | ir.addr -= 2; | |
6200 | goto no_support; | |
6201 | break; | |
6202 | ||
a38bba38 | 6203 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6204 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6205 | "instruction rdmsr.\n")); |
6206 | ir.addr -= 2; | |
6207 | goto no_support; | |
6208 | break; | |
6209 | ||
a38bba38 | 6210 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6211 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6212 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6213 | break; |
6214 | ||
a38bba38 | 6215 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6216 | { |
6217 | int ret; | |
cf648174 HZ |
6218 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6219 | { | |
6220 | ir.addr -= 2; | |
6221 | goto no_support; | |
6222 | } | |
a3c4230a | 6223 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6224 | { |
a3c4230a | 6225 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6226 | "instruction sysenter.\n")); |
6227 | ir.addr -= 2; | |
6228 | goto no_support; | |
6229 | } | |
a3c4230a | 6230 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6231 | if (ret) |
6232 | return ret; | |
6233 | } | |
6234 | break; | |
6235 | ||
a38bba38 | 6236 | case 0x0f35: /* sysexit */ |
a3c4230a | 6237 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6238 | "instruction sysexit.\n")); |
6239 | ir.addr -= 2; | |
6240 | goto no_support; | |
6241 | break; | |
6242 | ||
a38bba38 | 6243 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6244 | { |
6245 | int ret; | |
a3c4230a | 6246 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6247 | { |
a3c4230a | 6248 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6249 | "instruction syscall.\n")); |
6250 | ir.addr -= 2; | |
6251 | goto no_support; | |
6252 | } | |
a3c4230a | 6253 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6254 | if (ret) |
6255 | return ret; | |
6256 | } | |
6257 | break; | |
6258 | ||
a38bba38 | 6259 | case 0x0f07: /* sysret */ |
a3c4230a | 6260 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6261 | "instruction sysret.\n")); |
6262 | ir.addr -= 2; | |
6263 | goto no_support; | |
6264 | break; | |
6265 | ||
a38bba38 | 6266 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6267 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6268 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6269 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6270 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6271 | break; |
6272 | ||
a38bba38 | 6273 | case 0xf4: /* hlt */ |
a3c4230a | 6274 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6275 | "instruction hlt.\n")); |
6276 | ir.addr -= 1; | |
6277 | goto no_support; | |
6278 | break; | |
6279 | ||
6280 | case 0x0f00: | |
6281 | if (i386_record_modrm (&ir)) | |
6282 | return -1; | |
6283 | switch (ir.reg) | |
6284 | { | |
a38bba38 MS |
6285 | case 0: /* sldt */ |
6286 | case 1: /* str */ | |
7ad10968 | 6287 | if (ir.mod == 3) |
25ea693b | 6288 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6289 | else |
6290 | { | |
6291 | ir.ot = OT_WORD; | |
6292 | if (i386_record_lea_modrm (&ir)) | |
6293 | return -1; | |
6294 | } | |
6295 | break; | |
a38bba38 MS |
6296 | case 2: /* lldt */ |
6297 | case 3: /* ltr */ | |
7ad10968 | 6298 | break; |
a38bba38 MS |
6299 | case 4: /* verr */ |
6300 | case 5: /* verw */ | |
25ea693b | 6301 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6302 | break; |
6303 | default: | |
6304 | ir.addr -= 3; | |
6305 | opcode = opcode << 8 | ir.modrm; | |
6306 | goto no_support; | |
6307 | break; | |
6308 | } | |
6309 | break; | |
6310 | ||
6311 | case 0x0f01: | |
6312 | if (i386_record_modrm (&ir)) | |
6313 | return -1; | |
6314 | switch (ir.reg) | |
6315 | { | |
a38bba38 | 6316 | case 0: /* sgdt */ |
7ad10968 | 6317 | { |
955db0c0 | 6318 | uint64_t addr64; |
7ad10968 HZ |
6319 | |
6320 | if (ir.mod == 3) | |
6321 | { | |
6322 | ir.addr -= 3; | |
6323 | opcode = opcode << 8 | ir.modrm; | |
6324 | goto no_support; | |
6325 | } | |
d7877f7e | 6326 | if (ir.override >= 0) |
7ad10968 | 6327 | { |
25ea693b | 6328 | if (record_full_memory_query) |
bb08c432 HZ |
6329 | { |
6330 | int q; | |
6331 | ||
6332 | target_terminal_ours (); | |
6333 | q = yquery (_("\ | |
6334 | Process record ignores the memory change of instruction at address %s\n\ | |
6335 | because it can't get the value of the segment register.\n\ | |
6336 | Do you want to stop the program?"), | |
6337 | paddress (gdbarch, ir.orig_addr)); | |
6338 | target_terminal_inferior (); | |
6339 | if (q) | |
6340 | return -1; | |
6341 | } | |
7ad10968 HZ |
6342 | } |
6343 | else | |
6344 | { | |
955db0c0 | 6345 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6346 | return -1; |
25ea693b | 6347 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6348 | return -1; |
955db0c0 | 6349 | addr64 += 2; |
cf648174 HZ |
6350 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6351 | { | |
25ea693b | 6352 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6353 | return -1; |
6354 | } | |
6355 | else | |
6356 | { | |
25ea693b | 6357 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6358 | return -1; |
6359 | } | |
7ad10968 HZ |
6360 | } |
6361 | } | |
6362 | break; | |
6363 | case 1: | |
6364 | if (ir.mod == 3) | |
6365 | { | |
6366 | switch (ir.rm) | |
6367 | { | |
a38bba38 | 6368 | case 0: /* monitor */ |
7ad10968 | 6369 | break; |
a38bba38 | 6370 | case 1: /* mwait */ |
25ea693b | 6371 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6372 | break; |
6373 | default: | |
6374 | ir.addr -= 3; | |
6375 | opcode = opcode << 8 | ir.modrm; | |
6376 | goto no_support; | |
6377 | break; | |
6378 | } | |
6379 | } | |
6380 | else | |
6381 | { | |
6382 | /* sidt */ | |
d7877f7e | 6383 | if (ir.override >= 0) |
7ad10968 | 6384 | { |
25ea693b | 6385 | if (record_full_memory_query) |
bb08c432 HZ |
6386 | { |
6387 | int q; | |
6388 | ||
6389 | target_terminal_ours (); | |
6390 | q = yquery (_("\ | |
6391 | Process record ignores the memory change of instruction at address %s\n\ | |
6392 | because it can't get the value of the segment register.\n\ | |
6393 | Do you want to stop the program?"), | |
6394 | paddress (gdbarch, ir.orig_addr)); | |
6395 | target_terminal_inferior (); | |
6396 | if (q) | |
6397 | return -1; | |
6398 | } | |
7ad10968 HZ |
6399 | } |
6400 | else | |
6401 | { | |
955db0c0 | 6402 | uint64_t addr64; |
7ad10968 | 6403 | |
955db0c0 | 6404 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6405 | return -1; |
25ea693b | 6406 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6407 | return -1; |
955db0c0 | 6408 | addr64 += 2; |
cf648174 HZ |
6409 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6410 | { | |
25ea693b | 6411 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6412 | return -1; |
6413 | } | |
6414 | else | |
6415 | { | |
25ea693b | 6416 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6417 | return -1; |
6418 | } | |
7ad10968 HZ |
6419 | } |
6420 | } | |
6421 | break; | |
a38bba38 | 6422 | case 2: /* lgdt */ |
3800e645 MS |
6423 | if (ir.mod == 3) |
6424 | { | |
6425 | /* xgetbv */ | |
6426 | if (ir.rm == 0) | |
6427 | { | |
25ea693b MM |
6428 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6429 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
6430 | break; |
6431 | } | |
6432 | /* xsetbv */ | |
6433 | else if (ir.rm == 1) | |
6434 | break; | |
6435 | } | |
a38bba38 | 6436 | case 3: /* lidt */ |
7ad10968 HZ |
6437 | if (ir.mod == 3) |
6438 | { | |
6439 | ir.addr -= 3; | |
6440 | opcode = opcode << 8 | ir.modrm; | |
6441 | goto no_support; | |
6442 | } | |
6443 | break; | |
a38bba38 | 6444 | case 4: /* smsw */ |
7ad10968 HZ |
6445 | if (ir.mod == 3) |
6446 | { | |
25ea693b | 6447 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6448 | return -1; |
6449 | } | |
6450 | else | |
6451 | { | |
6452 | ir.ot = OT_WORD; | |
6453 | if (i386_record_lea_modrm (&ir)) | |
6454 | return -1; | |
6455 | } | |
25ea693b | 6456 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6457 | break; |
a38bba38 | 6458 | case 6: /* lmsw */ |
25ea693b | 6459 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 6460 | break; |
a38bba38 | 6461 | case 7: /* invlpg */ |
cf648174 HZ |
6462 | if (ir.mod == 3) |
6463 | { | |
6464 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 6465 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
6466 | else |
6467 | { | |
6468 | ir.addr -= 3; | |
6469 | opcode = opcode << 8 | ir.modrm; | |
6470 | goto no_support; | |
6471 | } | |
6472 | } | |
6473 | else | |
25ea693b | 6474 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6475 | break; |
6476 | default: | |
6477 | ir.addr -= 3; | |
6478 | opcode = opcode << 8 | ir.modrm; | |
6479 | goto no_support; | |
7ad10968 HZ |
6480 | break; |
6481 | } | |
6482 | break; | |
6483 | ||
a38bba38 MS |
6484 | case 0x0f08: /* invd */ |
6485 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6486 | break; |
6487 | ||
a38bba38 | 6488 | case 0x63: /* arpl */ |
7ad10968 HZ |
6489 | if (i386_record_modrm (&ir)) |
6490 | return -1; | |
cf648174 HZ |
6491 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6492 | { | |
25ea693b MM |
6493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
6494 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 6495 | } |
7ad10968 | 6496 | else |
cf648174 HZ |
6497 | { |
6498 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6499 | if (i386_record_lea_modrm (&ir)) | |
6500 | return -1; | |
6501 | } | |
6502 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 6503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6504 | break; |
6505 | ||
a38bba38 MS |
6506 | case 0x0f02: /* lar */ |
6507 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6508 | if (i386_record_modrm (&ir)) |
6509 | return -1; | |
25ea693b MM |
6510 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6511 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6512 | break; |
6513 | ||
6514 | case 0x0f18: | |
cf648174 HZ |
6515 | if (i386_record_modrm (&ir)) |
6516 | return -1; | |
6517 | if (ir.mod == 3 && ir.reg == 3) | |
6518 | { | |
6519 | ir.addr -= 3; | |
6520 | opcode = opcode << 8 | ir.modrm; | |
6521 | goto no_support; | |
6522 | } | |
7ad10968 HZ |
6523 | break; |
6524 | ||
7ad10968 HZ |
6525 | case 0x0f19: |
6526 | case 0x0f1a: | |
6527 | case 0x0f1b: | |
6528 | case 0x0f1c: | |
6529 | case 0x0f1d: | |
6530 | case 0x0f1e: | |
6531 | case 0x0f1f: | |
a38bba38 | 6532 | /* nop (multi byte) */ |
7ad10968 HZ |
6533 | break; |
6534 | ||
a38bba38 MS |
6535 | case 0x0f20: /* mov reg, crN */ |
6536 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6537 | if (i386_record_modrm (&ir)) |
6538 | return -1; | |
6539 | if ((ir.modrm & 0xc0) != 0xc0) | |
6540 | { | |
cf648174 | 6541 | ir.addr -= 3; |
7ad10968 HZ |
6542 | opcode = opcode << 8 | ir.modrm; |
6543 | goto no_support; | |
6544 | } | |
6545 | switch (ir.reg) | |
6546 | { | |
6547 | case 0: | |
6548 | case 2: | |
6549 | case 3: | |
6550 | case 4: | |
6551 | case 8: | |
6552 | if (opcode & 2) | |
25ea693b | 6553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6554 | else |
25ea693b | 6555 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6556 | break; |
6557 | default: | |
cf648174 | 6558 | ir.addr -= 3; |
7ad10968 HZ |
6559 | opcode = opcode << 8 | ir.modrm; |
6560 | goto no_support; | |
6561 | break; | |
6562 | } | |
6563 | break; | |
6564 | ||
a38bba38 MS |
6565 | case 0x0f21: /* mov reg, drN */ |
6566 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6567 | if (i386_record_modrm (&ir)) |
6568 | return -1; | |
6569 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6570 | || ir.reg == 5 || ir.reg >= 8) | |
6571 | { | |
cf648174 | 6572 | ir.addr -= 3; |
7ad10968 HZ |
6573 | opcode = opcode << 8 | ir.modrm; |
6574 | goto no_support; | |
6575 | } | |
6576 | if (opcode & 2) | |
25ea693b | 6577 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6578 | else |
25ea693b | 6579 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6580 | break; |
6581 | ||
a38bba38 | 6582 | case 0x0f06: /* clts */ |
25ea693b | 6583 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6584 | break; |
6585 | ||
a3c4230a HZ |
6586 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6587 | ||
6588 | case 0x0f0d: /* 3DNow! prefetch */ | |
6589 | break; | |
6590 | ||
6591 | case 0x0f0e: /* 3DNow! femms */ | |
6592 | case 0x0f77: /* emms */ | |
6593 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6594 | goto no_support; | |
25ea693b | 6595 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
6596 | break; |
6597 | ||
6598 | case 0x0f0f: /* 3DNow! data */ | |
6599 | if (i386_record_modrm (&ir)) | |
6600 | return -1; | |
4ffa4fc7 PA |
6601 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6602 | return -1; | |
a3c4230a HZ |
6603 | ir.addr++; |
6604 | switch (opcode8) | |
6605 | { | |
6606 | case 0x0c: /* 3DNow! pi2fw */ | |
6607 | case 0x0d: /* 3DNow! pi2fd */ | |
6608 | case 0x1c: /* 3DNow! pf2iw */ | |
6609 | case 0x1d: /* 3DNow! pf2id */ | |
6610 | case 0x8a: /* 3DNow! pfnacc */ | |
6611 | case 0x8e: /* 3DNow! pfpnacc */ | |
6612 | case 0x90: /* 3DNow! pfcmpge */ | |
6613 | case 0x94: /* 3DNow! pfmin */ | |
6614 | case 0x96: /* 3DNow! pfrcp */ | |
6615 | case 0x97: /* 3DNow! pfrsqrt */ | |
6616 | case 0x9a: /* 3DNow! pfsub */ | |
6617 | case 0x9e: /* 3DNow! pfadd */ | |
6618 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6619 | case 0xa4: /* 3DNow! pfmax */ | |
6620 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6621 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6622 | case 0xaa: /* 3DNow! pfsubr */ | |
6623 | case 0xae: /* 3DNow! pfacc */ | |
6624 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6625 | case 0xb4: /* 3DNow! pfmul */ | |
6626 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6627 | case 0xb7: /* 3DNow! pmulhrw */ | |
6628 | case 0xbb: /* 3DNow! pswapd */ | |
6629 | case 0xbf: /* 3DNow! pavgusb */ | |
6630 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6631 | goto no_support_3dnow_data; | |
25ea693b | 6632 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
6633 | break; |
6634 | ||
6635 | default: | |
6636 | no_support_3dnow_data: | |
6637 | opcode = (opcode << 8) | opcode8; | |
6638 | goto no_support; | |
6639 | break; | |
6640 | } | |
6641 | break; | |
6642 | ||
6643 | case 0x0faa: /* rsm */ | |
25ea693b MM |
6644 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6645 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6646 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6647 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6648 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6649 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6650 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6651 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6652 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
6653 | break; |
6654 | ||
6655 | case 0x0fae: | |
6656 | if (i386_record_modrm (&ir)) | |
6657 | return -1; | |
6658 | switch(ir.reg) | |
6659 | { | |
6660 | case 0: /* fxsave */ | |
6661 | { | |
6662 | uint64_t tmpu64; | |
6663 | ||
25ea693b | 6664 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
6665 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
6666 | return -1; | |
25ea693b | 6667 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
6668 | return -1; |
6669 | } | |
6670 | break; | |
6671 | ||
6672 | case 1: /* fxrstor */ | |
6673 | { | |
6674 | int i; | |
6675 | ||
25ea693b | 6676 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
6677 | |
6678 | for (i = I387_MM0_REGNUM (tdep); | |
6679 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 6680 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6681 | |
6682 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6683 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 6684 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6685 | |
6686 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
6687 | record_full_arch_list_add_reg (ir.regcache, |
6688 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
6689 | |
6690 | for (i = I387_ST0_REGNUM (tdep); | |
6691 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 6692 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6693 | |
6694 | for (i = I387_FCTRL_REGNUM (tdep); | |
6695 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 6696 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
6697 | } |
6698 | break; | |
6699 | ||
6700 | case 2: /* ldmxcsr */ | |
6701 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6702 | goto no_support; | |
25ea693b | 6703 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
6704 | break; |
6705 | ||
6706 | case 3: /* stmxcsr */ | |
6707 | ir.ot = OT_LONG; | |
6708 | if (i386_record_lea_modrm (&ir)) | |
6709 | return -1; | |
6710 | break; | |
6711 | ||
6712 | case 5: /* lfence */ | |
6713 | case 6: /* mfence */ | |
6714 | case 7: /* sfence clflush */ | |
6715 | break; | |
6716 | ||
6717 | default: | |
6718 | opcode = (opcode << 8) | ir.modrm; | |
6719 | goto no_support; | |
6720 | break; | |
6721 | } | |
6722 | break; | |
6723 | ||
6724 | case 0x0fc3: /* movnti */ | |
6725 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6726 | if (i386_record_modrm (&ir)) | |
6727 | return -1; | |
6728 | if (ir.mod == 3) | |
6729 | goto no_support; | |
6730 | ir.reg |= rex_r; | |
6731 | if (i386_record_lea_modrm (&ir)) | |
6732 | return -1; | |
6733 | break; | |
6734 | ||
6735 | /* Add prefix to opcode. */ | |
6736 | case 0x0f10: | |
6737 | case 0x0f11: | |
6738 | case 0x0f12: | |
6739 | case 0x0f13: | |
6740 | case 0x0f14: | |
6741 | case 0x0f15: | |
6742 | case 0x0f16: | |
6743 | case 0x0f17: | |
6744 | case 0x0f28: | |
6745 | case 0x0f29: | |
6746 | case 0x0f2a: | |
6747 | case 0x0f2b: | |
6748 | case 0x0f2c: | |
6749 | case 0x0f2d: | |
6750 | case 0x0f2e: | |
6751 | case 0x0f2f: | |
6752 | case 0x0f38: | |
6753 | case 0x0f39: | |
6754 | case 0x0f3a: | |
6755 | case 0x0f50: | |
6756 | case 0x0f51: | |
6757 | case 0x0f52: | |
6758 | case 0x0f53: | |
6759 | case 0x0f54: | |
6760 | case 0x0f55: | |
6761 | case 0x0f56: | |
6762 | case 0x0f57: | |
6763 | case 0x0f58: | |
6764 | case 0x0f59: | |
6765 | case 0x0f5a: | |
6766 | case 0x0f5b: | |
6767 | case 0x0f5c: | |
6768 | case 0x0f5d: | |
6769 | case 0x0f5e: | |
6770 | case 0x0f5f: | |
6771 | case 0x0f60: | |
6772 | case 0x0f61: | |
6773 | case 0x0f62: | |
6774 | case 0x0f63: | |
6775 | case 0x0f64: | |
6776 | case 0x0f65: | |
6777 | case 0x0f66: | |
6778 | case 0x0f67: | |
6779 | case 0x0f68: | |
6780 | case 0x0f69: | |
6781 | case 0x0f6a: | |
6782 | case 0x0f6b: | |
6783 | case 0x0f6c: | |
6784 | case 0x0f6d: | |
6785 | case 0x0f6e: | |
6786 | case 0x0f6f: | |
6787 | case 0x0f70: | |
6788 | case 0x0f71: | |
6789 | case 0x0f72: | |
6790 | case 0x0f73: | |
6791 | case 0x0f74: | |
6792 | case 0x0f75: | |
6793 | case 0x0f76: | |
6794 | case 0x0f7c: | |
6795 | case 0x0f7d: | |
6796 | case 0x0f7e: | |
6797 | case 0x0f7f: | |
6798 | case 0x0fb8: | |
6799 | case 0x0fc2: | |
6800 | case 0x0fc4: | |
6801 | case 0x0fc5: | |
6802 | case 0x0fc6: | |
6803 | case 0x0fd0: | |
6804 | case 0x0fd1: | |
6805 | case 0x0fd2: | |
6806 | case 0x0fd3: | |
6807 | case 0x0fd4: | |
6808 | case 0x0fd5: | |
6809 | case 0x0fd6: | |
6810 | case 0x0fd7: | |
6811 | case 0x0fd8: | |
6812 | case 0x0fd9: | |
6813 | case 0x0fda: | |
6814 | case 0x0fdb: | |
6815 | case 0x0fdc: | |
6816 | case 0x0fdd: | |
6817 | case 0x0fde: | |
6818 | case 0x0fdf: | |
6819 | case 0x0fe0: | |
6820 | case 0x0fe1: | |
6821 | case 0x0fe2: | |
6822 | case 0x0fe3: | |
6823 | case 0x0fe4: | |
6824 | case 0x0fe5: | |
6825 | case 0x0fe6: | |
6826 | case 0x0fe7: | |
6827 | case 0x0fe8: | |
6828 | case 0x0fe9: | |
6829 | case 0x0fea: | |
6830 | case 0x0feb: | |
6831 | case 0x0fec: | |
6832 | case 0x0fed: | |
6833 | case 0x0fee: | |
6834 | case 0x0fef: | |
6835 | case 0x0ff0: | |
6836 | case 0x0ff1: | |
6837 | case 0x0ff2: | |
6838 | case 0x0ff3: | |
6839 | case 0x0ff4: | |
6840 | case 0x0ff5: | |
6841 | case 0x0ff6: | |
6842 | case 0x0ff7: | |
6843 | case 0x0ff8: | |
6844 | case 0x0ff9: | |
6845 | case 0x0ffa: | |
6846 | case 0x0ffb: | |
6847 | case 0x0ffc: | |
6848 | case 0x0ffd: | |
6849 | case 0x0ffe: | |
6850 | switch (prefixes) | |
6851 | { | |
6852 | case PREFIX_REPNZ: | |
6853 | opcode |= 0xf20000; | |
6854 | break; | |
6855 | case PREFIX_DATA: | |
6856 | opcode |= 0x660000; | |
6857 | break; | |
6858 | case PREFIX_REPZ: | |
6859 | opcode |= 0xf30000; | |
6860 | break; | |
6861 | } | |
6862 | reswitch_prefix_add: | |
6863 | switch (opcode) | |
6864 | { | |
6865 | case 0x0f38: | |
6866 | case 0x660f38: | |
6867 | case 0xf20f38: | |
6868 | case 0x0f3a: | |
6869 | case 0x660f3a: | |
4ffa4fc7 PA |
6870 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6871 | return -1; | |
a3c4230a HZ |
6872 | ir.addr++; |
6873 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6874 | goto reswitch_prefix_add; | |
6875 | break; | |
6876 | ||
6877 | case 0x0f10: /* movups */ | |
6878 | case 0x660f10: /* movupd */ | |
6879 | case 0xf30f10: /* movss */ | |
6880 | case 0xf20f10: /* movsd */ | |
6881 | case 0x0f12: /* movlps */ | |
6882 | case 0x660f12: /* movlpd */ | |
6883 | case 0xf30f12: /* movsldup */ | |
6884 | case 0xf20f12: /* movddup */ | |
6885 | case 0x0f14: /* unpcklps */ | |
6886 | case 0x660f14: /* unpcklpd */ | |
6887 | case 0x0f15: /* unpckhps */ | |
6888 | case 0x660f15: /* unpckhpd */ | |
6889 | case 0x0f16: /* movhps */ | |
6890 | case 0x660f16: /* movhpd */ | |
6891 | case 0xf30f16: /* movshdup */ | |
6892 | case 0x0f28: /* movaps */ | |
6893 | case 0x660f28: /* movapd */ | |
6894 | case 0x0f2a: /* cvtpi2ps */ | |
6895 | case 0x660f2a: /* cvtpi2pd */ | |
6896 | case 0xf30f2a: /* cvtsi2ss */ | |
6897 | case 0xf20f2a: /* cvtsi2sd */ | |
6898 | case 0x0f2c: /* cvttps2pi */ | |
6899 | case 0x660f2c: /* cvttpd2pi */ | |
6900 | case 0x0f2d: /* cvtps2pi */ | |
6901 | case 0x660f2d: /* cvtpd2pi */ | |
6902 | case 0x660f3800: /* pshufb */ | |
6903 | case 0x660f3801: /* phaddw */ | |
6904 | case 0x660f3802: /* phaddd */ | |
6905 | case 0x660f3803: /* phaddsw */ | |
6906 | case 0x660f3804: /* pmaddubsw */ | |
6907 | case 0x660f3805: /* phsubw */ | |
6908 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6909 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6910 | case 0x660f3808: /* psignb */ |
6911 | case 0x660f3809: /* psignw */ | |
6912 | case 0x660f380a: /* psignd */ | |
6913 | case 0x660f380b: /* pmulhrsw */ | |
6914 | case 0x660f3810: /* pblendvb */ | |
6915 | case 0x660f3814: /* blendvps */ | |
6916 | case 0x660f3815: /* blendvpd */ | |
6917 | case 0x660f381c: /* pabsb */ | |
6918 | case 0x660f381d: /* pabsw */ | |
6919 | case 0x660f381e: /* pabsd */ | |
6920 | case 0x660f3820: /* pmovsxbw */ | |
6921 | case 0x660f3821: /* pmovsxbd */ | |
6922 | case 0x660f3822: /* pmovsxbq */ | |
6923 | case 0x660f3823: /* pmovsxwd */ | |
6924 | case 0x660f3824: /* pmovsxwq */ | |
6925 | case 0x660f3825: /* pmovsxdq */ | |
6926 | case 0x660f3828: /* pmuldq */ | |
6927 | case 0x660f3829: /* pcmpeqq */ | |
6928 | case 0x660f382a: /* movntdqa */ | |
6929 | case 0x660f3a08: /* roundps */ | |
6930 | case 0x660f3a09: /* roundpd */ | |
6931 | case 0x660f3a0a: /* roundss */ | |
6932 | case 0x660f3a0b: /* roundsd */ | |
6933 | case 0x660f3a0c: /* blendps */ | |
6934 | case 0x660f3a0d: /* blendpd */ | |
6935 | case 0x660f3a0e: /* pblendw */ | |
6936 | case 0x660f3a0f: /* palignr */ | |
6937 | case 0x660f3a20: /* pinsrb */ | |
6938 | case 0x660f3a21: /* insertps */ | |
6939 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6940 | case 0x660f3a40: /* dpps */ | |
6941 | case 0x660f3a41: /* dppd */ | |
6942 | case 0x660f3a42: /* mpsadbw */ | |
6943 | case 0x660f3a60: /* pcmpestrm */ | |
6944 | case 0x660f3a61: /* pcmpestri */ | |
6945 | case 0x660f3a62: /* pcmpistrm */ | |
6946 | case 0x660f3a63: /* pcmpistri */ | |
6947 | case 0x0f51: /* sqrtps */ | |
6948 | case 0x660f51: /* sqrtpd */ | |
6949 | case 0xf20f51: /* sqrtsd */ | |
6950 | case 0xf30f51: /* sqrtss */ | |
6951 | case 0x0f52: /* rsqrtps */ | |
6952 | case 0xf30f52: /* rsqrtss */ | |
6953 | case 0x0f53: /* rcpps */ | |
6954 | case 0xf30f53: /* rcpss */ | |
6955 | case 0x0f54: /* andps */ | |
6956 | case 0x660f54: /* andpd */ | |
6957 | case 0x0f55: /* andnps */ | |
6958 | case 0x660f55: /* andnpd */ | |
6959 | case 0x0f56: /* orps */ | |
6960 | case 0x660f56: /* orpd */ | |
6961 | case 0x0f57: /* xorps */ | |
6962 | case 0x660f57: /* xorpd */ | |
6963 | case 0x0f58: /* addps */ | |
6964 | case 0x660f58: /* addpd */ | |
6965 | case 0xf20f58: /* addsd */ | |
6966 | case 0xf30f58: /* addss */ | |
6967 | case 0x0f59: /* mulps */ | |
6968 | case 0x660f59: /* mulpd */ | |
6969 | case 0xf20f59: /* mulsd */ | |
6970 | case 0xf30f59: /* mulss */ | |
6971 | case 0x0f5a: /* cvtps2pd */ | |
6972 | case 0x660f5a: /* cvtpd2ps */ | |
6973 | case 0xf20f5a: /* cvtsd2ss */ | |
6974 | case 0xf30f5a: /* cvtss2sd */ | |
6975 | case 0x0f5b: /* cvtdq2ps */ | |
6976 | case 0x660f5b: /* cvtps2dq */ | |
6977 | case 0xf30f5b: /* cvttps2dq */ | |
6978 | case 0x0f5c: /* subps */ | |
6979 | case 0x660f5c: /* subpd */ | |
6980 | case 0xf20f5c: /* subsd */ | |
6981 | case 0xf30f5c: /* subss */ | |
6982 | case 0x0f5d: /* minps */ | |
6983 | case 0x660f5d: /* minpd */ | |
6984 | case 0xf20f5d: /* minsd */ | |
6985 | case 0xf30f5d: /* minss */ | |
6986 | case 0x0f5e: /* divps */ | |
6987 | case 0x660f5e: /* divpd */ | |
6988 | case 0xf20f5e: /* divsd */ | |
6989 | case 0xf30f5e: /* divss */ | |
6990 | case 0x0f5f: /* maxps */ | |
6991 | case 0x660f5f: /* maxpd */ | |
6992 | case 0xf20f5f: /* maxsd */ | |
6993 | case 0xf30f5f: /* maxss */ | |
6994 | case 0x660f60: /* punpcklbw */ | |
6995 | case 0x660f61: /* punpcklwd */ | |
6996 | case 0x660f62: /* punpckldq */ | |
6997 | case 0x660f63: /* packsswb */ | |
6998 | case 0x660f64: /* pcmpgtb */ | |
6999 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7000 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7001 | case 0x660f67: /* packuswb */ |
7002 | case 0x660f68: /* punpckhbw */ | |
7003 | case 0x660f69: /* punpckhwd */ | |
7004 | case 0x660f6a: /* punpckhdq */ | |
7005 | case 0x660f6b: /* packssdw */ | |
7006 | case 0x660f6c: /* punpcklqdq */ | |
7007 | case 0x660f6d: /* punpckhqdq */ | |
7008 | case 0x660f6e: /* movd */ | |
7009 | case 0x660f6f: /* movdqa */ | |
7010 | case 0xf30f6f: /* movdqu */ | |
7011 | case 0x660f70: /* pshufd */ | |
7012 | case 0xf20f70: /* pshuflw */ | |
7013 | case 0xf30f70: /* pshufhw */ | |
7014 | case 0x660f74: /* pcmpeqb */ | |
7015 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7016 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7017 | case 0x660f7c: /* haddpd */ |
7018 | case 0xf20f7c: /* haddps */ | |
7019 | case 0x660f7d: /* hsubpd */ | |
7020 | case 0xf20f7d: /* hsubps */ | |
7021 | case 0xf30f7e: /* movq */ | |
7022 | case 0x0fc2: /* cmpps */ | |
7023 | case 0x660fc2: /* cmppd */ | |
7024 | case 0xf20fc2: /* cmpsd */ | |
7025 | case 0xf30fc2: /* cmpss */ | |
7026 | case 0x660fc4: /* pinsrw */ | |
7027 | case 0x0fc6: /* shufps */ | |
7028 | case 0x660fc6: /* shufpd */ | |
7029 | case 0x660fd0: /* addsubpd */ | |
7030 | case 0xf20fd0: /* addsubps */ | |
7031 | case 0x660fd1: /* psrlw */ | |
7032 | case 0x660fd2: /* psrld */ | |
7033 | case 0x660fd3: /* psrlq */ | |
7034 | case 0x660fd4: /* paddq */ | |
7035 | case 0x660fd5: /* pmullw */ | |
7036 | case 0xf30fd6: /* movq2dq */ | |
7037 | case 0x660fd8: /* psubusb */ | |
7038 | case 0x660fd9: /* psubusw */ | |
7039 | case 0x660fda: /* pminub */ | |
7040 | case 0x660fdb: /* pand */ | |
7041 | case 0x660fdc: /* paddusb */ | |
7042 | case 0x660fdd: /* paddusw */ | |
7043 | case 0x660fde: /* pmaxub */ | |
7044 | case 0x660fdf: /* pandn */ | |
7045 | case 0x660fe0: /* pavgb */ | |
7046 | case 0x660fe1: /* psraw */ | |
7047 | case 0x660fe2: /* psrad */ | |
7048 | case 0x660fe3: /* pavgw */ | |
7049 | case 0x660fe4: /* pmulhuw */ | |
7050 | case 0x660fe5: /* pmulhw */ | |
7051 | case 0x660fe6: /* cvttpd2dq */ | |
7052 | case 0xf20fe6: /* cvtpd2dq */ | |
7053 | case 0xf30fe6: /* cvtdq2pd */ | |
7054 | case 0x660fe8: /* psubsb */ | |
7055 | case 0x660fe9: /* psubsw */ | |
7056 | case 0x660fea: /* pminsw */ | |
7057 | case 0x660feb: /* por */ | |
7058 | case 0x660fec: /* paddsb */ | |
7059 | case 0x660fed: /* paddsw */ | |
7060 | case 0x660fee: /* pmaxsw */ | |
7061 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7062 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7063 | case 0x660ff1: /* psllw */ |
7064 | case 0x660ff2: /* pslld */ | |
7065 | case 0x660ff3: /* psllq */ | |
7066 | case 0x660ff4: /* pmuludq */ | |
7067 | case 0x660ff5: /* pmaddwd */ | |
7068 | case 0x660ff6: /* psadbw */ | |
7069 | case 0x660ff8: /* psubb */ | |
7070 | case 0x660ff9: /* psubw */ | |
56d2815c | 7071 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7072 | case 0x660ffb: /* psubq */ |
7073 | case 0x660ffc: /* paddb */ | |
7074 | case 0x660ffd: /* paddw */ | |
56d2815c | 7075 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7076 | if (i386_record_modrm (&ir)) |
7077 | return -1; | |
7078 | ir.reg |= rex_r; | |
c131fcee | 7079 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7080 | goto no_support; |
25ea693b MM |
7081 | record_full_arch_list_add_reg (ir.regcache, |
7082 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7083 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7084 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7085 | break; |
7086 | ||
7087 | case 0x0f11: /* movups */ | |
7088 | case 0x660f11: /* movupd */ | |
7089 | case 0xf30f11: /* movss */ | |
7090 | case 0xf20f11: /* movsd */ | |
7091 | case 0x0f13: /* movlps */ | |
7092 | case 0x660f13: /* movlpd */ | |
7093 | case 0x0f17: /* movhps */ | |
7094 | case 0x660f17: /* movhpd */ | |
7095 | case 0x0f29: /* movaps */ | |
7096 | case 0x660f29: /* movapd */ | |
7097 | case 0x660f3a14: /* pextrb */ | |
7098 | case 0x660f3a15: /* pextrw */ | |
7099 | case 0x660f3a16: /* pextrd pextrq */ | |
7100 | case 0x660f3a17: /* extractps */ | |
7101 | case 0x660f7f: /* movdqa */ | |
7102 | case 0xf30f7f: /* movdqu */ | |
7103 | if (i386_record_modrm (&ir)) | |
7104 | return -1; | |
7105 | if (ir.mod == 3) | |
7106 | { | |
7107 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7108 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7109 | goto no_support; | |
7110 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7111 | if (!i386_xmm_regnum_p (gdbarch, |
7112 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7113 | goto no_support; |
25ea693b MM |
7114 | record_full_arch_list_add_reg (ir.regcache, |
7115 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7116 | } |
7117 | else | |
7118 | { | |
7119 | switch (opcode) | |
7120 | { | |
7121 | case 0x660f3a14: | |
7122 | ir.ot = OT_BYTE; | |
7123 | break; | |
7124 | case 0x660f3a15: | |
7125 | ir.ot = OT_WORD; | |
7126 | break; | |
7127 | case 0x660f3a16: | |
7128 | ir.ot = OT_LONG; | |
7129 | break; | |
7130 | case 0x660f3a17: | |
7131 | ir.ot = OT_QUAD; | |
7132 | break; | |
7133 | default: | |
7134 | ir.ot = OT_DQUAD; | |
7135 | break; | |
7136 | } | |
7137 | if (i386_record_lea_modrm (&ir)) | |
7138 | return -1; | |
7139 | } | |
7140 | break; | |
7141 | ||
7142 | case 0x0f2b: /* movntps */ | |
7143 | case 0x660f2b: /* movntpd */ | |
7144 | case 0x0fe7: /* movntq */ | |
7145 | case 0x660fe7: /* movntdq */ | |
7146 | if (ir.mod == 3) | |
7147 | goto no_support; | |
7148 | if (opcode == 0x0fe7) | |
7149 | ir.ot = OT_QUAD; | |
7150 | else | |
7151 | ir.ot = OT_DQUAD; | |
7152 | if (i386_record_lea_modrm (&ir)) | |
7153 | return -1; | |
7154 | break; | |
7155 | ||
7156 | case 0xf30f2c: /* cvttss2si */ | |
7157 | case 0xf20f2c: /* cvttsd2si */ | |
7158 | case 0xf30f2d: /* cvtss2si */ | |
7159 | case 0xf20f2d: /* cvtsd2si */ | |
7160 | case 0xf20f38f0: /* crc32 */ | |
7161 | case 0xf20f38f1: /* crc32 */ | |
7162 | case 0x0f50: /* movmskps */ | |
7163 | case 0x660f50: /* movmskpd */ | |
7164 | case 0x0fc5: /* pextrw */ | |
7165 | case 0x660fc5: /* pextrw */ | |
7166 | case 0x0fd7: /* pmovmskb */ | |
7167 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7168 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7169 | break; |
7170 | ||
7171 | case 0x0f3800: /* pshufb */ | |
7172 | case 0x0f3801: /* phaddw */ | |
7173 | case 0x0f3802: /* phaddd */ | |
7174 | case 0x0f3803: /* phaddsw */ | |
7175 | case 0x0f3804: /* pmaddubsw */ | |
7176 | case 0x0f3805: /* phsubw */ | |
7177 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7178 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7179 | case 0x0f3808: /* psignb */ |
7180 | case 0x0f3809: /* psignw */ | |
7181 | case 0x0f380a: /* psignd */ | |
7182 | case 0x0f380b: /* pmulhrsw */ | |
7183 | case 0x0f381c: /* pabsb */ | |
7184 | case 0x0f381d: /* pabsw */ | |
7185 | case 0x0f381e: /* pabsd */ | |
7186 | case 0x0f382b: /* packusdw */ | |
7187 | case 0x0f3830: /* pmovzxbw */ | |
7188 | case 0x0f3831: /* pmovzxbd */ | |
7189 | case 0x0f3832: /* pmovzxbq */ | |
7190 | case 0x0f3833: /* pmovzxwd */ | |
7191 | case 0x0f3834: /* pmovzxwq */ | |
7192 | case 0x0f3835: /* pmovzxdq */ | |
7193 | case 0x0f3837: /* pcmpgtq */ | |
7194 | case 0x0f3838: /* pminsb */ | |
7195 | case 0x0f3839: /* pminsd */ | |
7196 | case 0x0f383a: /* pminuw */ | |
7197 | case 0x0f383b: /* pminud */ | |
7198 | case 0x0f383c: /* pmaxsb */ | |
7199 | case 0x0f383d: /* pmaxsd */ | |
7200 | case 0x0f383e: /* pmaxuw */ | |
7201 | case 0x0f383f: /* pmaxud */ | |
7202 | case 0x0f3840: /* pmulld */ | |
7203 | case 0x0f3841: /* phminposuw */ | |
7204 | case 0x0f3a0f: /* palignr */ | |
7205 | case 0x0f60: /* punpcklbw */ | |
7206 | case 0x0f61: /* punpcklwd */ | |
7207 | case 0x0f62: /* punpckldq */ | |
7208 | case 0x0f63: /* packsswb */ | |
7209 | case 0x0f64: /* pcmpgtb */ | |
7210 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7211 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7212 | case 0x0f67: /* packuswb */ |
7213 | case 0x0f68: /* punpckhbw */ | |
7214 | case 0x0f69: /* punpckhwd */ | |
7215 | case 0x0f6a: /* punpckhdq */ | |
7216 | case 0x0f6b: /* packssdw */ | |
7217 | case 0x0f6e: /* movd */ | |
7218 | case 0x0f6f: /* movq */ | |
7219 | case 0x0f70: /* pshufw */ | |
7220 | case 0x0f74: /* pcmpeqb */ | |
7221 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7222 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7223 | case 0x0fc4: /* pinsrw */ |
7224 | case 0x0fd1: /* psrlw */ | |
7225 | case 0x0fd2: /* psrld */ | |
7226 | case 0x0fd3: /* psrlq */ | |
7227 | case 0x0fd4: /* paddq */ | |
7228 | case 0x0fd5: /* pmullw */ | |
7229 | case 0xf20fd6: /* movdq2q */ | |
7230 | case 0x0fd8: /* psubusb */ | |
7231 | case 0x0fd9: /* psubusw */ | |
7232 | case 0x0fda: /* pminub */ | |
7233 | case 0x0fdb: /* pand */ | |
7234 | case 0x0fdc: /* paddusb */ | |
7235 | case 0x0fdd: /* paddusw */ | |
7236 | case 0x0fde: /* pmaxub */ | |
7237 | case 0x0fdf: /* pandn */ | |
7238 | case 0x0fe0: /* pavgb */ | |
7239 | case 0x0fe1: /* psraw */ | |
7240 | case 0x0fe2: /* psrad */ | |
7241 | case 0x0fe3: /* pavgw */ | |
7242 | case 0x0fe4: /* pmulhuw */ | |
7243 | case 0x0fe5: /* pmulhw */ | |
7244 | case 0x0fe8: /* psubsb */ | |
7245 | case 0x0fe9: /* psubsw */ | |
7246 | case 0x0fea: /* pminsw */ | |
7247 | case 0x0feb: /* por */ | |
7248 | case 0x0fec: /* paddsb */ | |
7249 | case 0x0fed: /* paddsw */ | |
7250 | case 0x0fee: /* pmaxsw */ | |
7251 | case 0x0fef: /* pxor */ | |
7252 | case 0x0ff1: /* psllw */ | |
7253 | case 0x0ff2: /* pslld */ | |
7254 | case 0x0ff3: /* psllq */ | |
7255 | case 0x0ff4: /* pmuludq */ | |
7256 | case 0x0ff5: /* pmaddwd */ | |
7257 | case 0x0ff6: /* psadbw */ | |
7258 | case 0x0ff8: /* psubb */ | |
7259 | case 0x0ff9: /* psubw */ | |
56d2815c | 7260 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7261 | case 0x0ffb: /* psubq */ |
7262 | case 0x0ffc: /* paddb */ | |
7263 | case 0x0ffd: /* paddw */ | |
56d2815c | 7264 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7265 | if (i386_record_modrm (&ir)) |
7266 | return -1; | |
7267 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7268 | goto no_support; | |
25ea693b MM |
7269 | record_full_arch_list_add_reg (ir.regcache, |
7270 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7271 | break; |
7272 | ||
7273 | case 0x0f71: /* psllw */ | |
7274 | case 0x0f72: /* pslld */ | |
7275 | case 0x0f73: /* psllq */ | |
7276 | if (i386_record_modrm (&ir)) | |
7277 | return -1; | |
7278 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7279 | goto no_support; | |
25ea693b MM |
7280 | record_full_arch_list_add_reg (ir.regcache, |
7281 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7282 | break; |
7283 | ||
7284 | case 0x660f71: /* psllw */ | |
7285 | case 0x660f72: /* pslld */ | |
7286 | case 0x660f73: /* psllq */ | |
7287 | if (i386_record_modrm (&ir)) | |
7288 | return -1; | |
7289 | ir.rm |= ir.rex_b; | |
c131fcee | 7290 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7291 | goto no_support; |
25ea693b MM |
7292 | record_full_arch_list_add_reg (ir.regcache, |
7293 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7294 | break; |
7295 | ||
7296 | case 0x0f7e: /* movd */ | |
7297 | case 0x660f7e: /* movd */ | |
7298 | if (i386_record_modrm (&ir)) | |
7299 | return -1; | |
7300 | if (ir.mod == 3) | |
25ea693b | 7301 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7302 | else |
7303 | { | |
7304 | if (ir.dflag == 2) | |
7305 | ir.ot = OT_QUAD; | |
7306 | else | |
7307 | ir.ot = OT_LONG; | |
7308 | if (i386_record_lea_modrm (&ir)) | |
7309 | return -1; | |
7310 | } | |
7311 | break; | |
7312 | ||
7313 | case 0x0f7f: /* movq */ | |
7314 | if (i386_record_modrm (&ir)) | |
7315 | return -1; | |
7316 | if (ir.mod == 3) | |
7317 | { | |
7318 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7319 | goto no_support; | |
25ea693b MM |
7320 | record_full_arch_list_add_reg (ir.regcache, |
7321 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7322 | } |
7323 | else | |
7324 | { | |
7325 | ir.ot = OT_QUAD; | |
7326 | if (i386_record_lea_modrm (&ir)) | |
7327 | return -1; | |
7328 | } | |
7329 | break; | |
7330 | ||
7331 | case 0xf30fb8: /* popcnt */ | |
7332 | if (i386_record_modrm (&ir)) | |
7333 | return -1; | |
25ea693b MM |
7334 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7335 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
7336 | break; |
7337 | ||
7338 | case 0x660fd6: /* movq */ | |
7339 | if (i386_record_modrm (&ir)) | |
7340 | return -1; | |
7341 | if (ir.mod == 3) | |
7342 | { | |
7343 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7344 | if (!i386_xmm_regnum_p (gdbarch, |
7345 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7346 | goto no_support; |
25ea693b MM |
7347 | record_full_arch_list_add_reg (ir.regcache, |
7348 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7349 | } |
7350 | else | |
7351 | { | |
7352 | ir.ot = OT_QUAD; | |
7353 | if (i386_record_lea_modrm (&ir)) | |
7354 | return -1; | |
7355 | } | |
7356 | break; | |
7357 | ||
7358 | case 0x660f3817: /* ptest */ | |
7359 | case 0x0f2e: /* ucomiss */ | |
7360 | case 0x660f2e: /* ucomisd */ | |
7361 | case 0x0f2f: /* comiss */ | |
7362 | case 0x660f2f: /* comisd */ | |
25ea693b | 7363 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7364 | break; |
7365 | ||
7366 | case 0x0ff7: /* maskmovq */ | |
7367 | regcache_raw_read_unsigned (ir.regcache, | |
7368 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7369 | &addr); | |
25ea693b | 7370 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
7371 | return -1; |
7372 | break; | |
7373 | ||
7374 | case 0x660ff7: /* maskmovdqu */ | |
7375 | regcache_raw_read_unsigned (ir.regcache, | |
7376 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7377 | &addr); | |
25ea693b | 7378 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
7379 | return -1; |
7380 | break; | |
7381 | ||
7382 | default: | |
7383 | goto no_support; | |
7384 | break; | |
7385 | } | |
7386 | break; | |
7ad10968 HZ |
7387 | |
7388 | default: | |
7ad10968 HZ |
7389 | goto no_support; |
7390 | break; | |
7391 | } | |
7392 | ||
cf648174 | 7393 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
7394 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
7395 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
7396 | return -1; |
7397 | ||
7398 | return 0; | |
7399 | ||
01fe1b41 | 7400 | no_support: |
a3c4230a HZ |
7401 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7402 | "at address %s.\n"), | |
7403 | (unsigned int) (opcode), | |
7404 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7405 | return -1; |
7406 | } | |
7407 | ||
cf648174 HZ |
7408 | static const int i386_record_regmap[] = |
7409 | { | |
7410 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7411 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7412 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7413 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7414 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7415 | }; | |
7416 | ||
7a697b8d | 7417 | /* Check that the given address appears suitable for a fast |
405f8e94 | 7418 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
7419 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
7420 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
7421 | middle of the tracepoint jump. On x86, it may be possible to use |
7422 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
7423 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
7424 | of instruction to replace, and 0 if not, plus an explanatory |
7425 | string. */ | |
7426 | ||
7427 | static int | |
7428 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7429 | CORE_ADDR addr, int *isize, char **msg) | |
7430 | { | |
7431 | int len, jumplen; | |
7432 | static struct ui_file *gdb_null = NULL; | |
7433 | ||
405f8e94 SS |
7434 | /* Ask the target for the minimum instruction length supported. */ |
7435 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
7436 | ||
7437 | if (jumplen < 0) | |
7438 | { | |
7439 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
7440 | operation, assume that fast tracepoints will always be implemented | |
7441 | using 4-byte relative jumps on both x86 and x86-64. */ | |
7442 | jumplen = 5; | |
7443 | } | |
7444 | else if (jumplen == 0) | |
7445 | { | |
7446 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
7447 | returns zero, then the IPA has not loaded yet. In this case, | |
7448 | we optimistically assume that truncated 2-byte relative jumps | |
7449 | will be available on x86, and compensate later if this assumption | |
7450 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
7451 | jumps will always be used. */ | |
7452 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
7453 | } | |
7a697b8d SS |
7454 | |
7455 | /* Dummy file descriptor for the disassembler. */ | |
7456 | if (!gdb_null) | |
7457 | gdb_null = ui_file_new (); | |
7458 | ||
7459 | /* Check for fit. */ | |
7460 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
7461 | if (isize) |
7462 | *isize = len; | |
7463 | ||
7a697b8d SS |
7464 | if (len < jumplen) |
7465 | { | |
7466 | /* Return a bit of target-specific detail to add to the caller's | |
7467 | generic failure message. */ | |
7468 | if (msg) | |
1777feb0 MS |
7469 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7470 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7471 | len, jumplen); |
7472 | return 0; | |
7473 | } | |
405f8e94 SS |
7474 | else |
7475 | { | |
7476 | if (msg) | |
7477 | *msg = NULL; | |
7478 | return 1; | |
7479 | } | |
7a697b8d SS |
7480 | } |
7481 | ||
90884b2b L |
7482 | static int |
7483 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7484 | struct tdesc_arch_data *tdesc_data) | |
7485 | { | |
7486 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7487 | const struct tdesc_feature *feature_core; |
7488 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7489 | int i, num_regs, valid_p; |
7490 | ||
7491 | if (! tdesc_has_registers (tdesc)) | |
7492 | return 0; | |
7493 | ||
7494 | /* Get core registers. */ | |
7495 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7496 | if (feature_core == NULL) |
7497 | return 0; | |
90884b2b L |
7498 | |
7499 | /* Get SSE registers. */ | |
c131fcee | 7500 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7501 | |
c131fcee L |
7502 | /* Try AVX registers. */ |
7503 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7504 | ||
90884b2b L |
7505 | valid_p = 1; |
7506 | ||
c131fcee L |
7507 | /* The XCR0 bits. */ |
7508 | if (feature_avx) | |
7509 | { | |
3a13a53b L |
7510 | /* AVX register description requires SSE register description. */ |
7511 | if (!feature_sse) | |
7512 | return 0; | |
7513 | ||
c131fcee L |
7514 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7515 | ||
7516 | /* It may have been set by OSABI initialization function. */ | |
7517 | if (tdep->num_ymm_regs == 0) | |
7518 | { | |
7519 | tdep->ymmh_register_names = i386_ymmh_names; | |
7520 | tdep->num_ymm_regs = 8; | |
7521 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7522 | } | |
7523 | ||
7524 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7525 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7526 | tdep->ymm0h_regnum + i, | |
7527 | tdep->ymmh_register_names[i]); | |
7528 | } | |
3a13a53b | 7529 | else if (feature_sse) |
c131fcee | 7530 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7531 | else |
7532 | { | |
7533 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7534 | tdep->num_xmm_regs = 0; | |
7535 | } | |
c131fcee | 7536 | |
90884b2b L |
7537 | num_regs = tdep->num_core_regs; |
7538 | for (i = 0; i < num_regs; i++) | |
7539 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7540 | tdep->register_names[i]); | |
7541 | ||
3a13a53b L |
7542 | if (feature_sse) |
7543 | { | |
7544 | /* Need to include %mxcsr, so add one. */ | |
7545 | num_regs += tdep->num_xmm_regs + 1; | |
7546 | for (; i < num_regs; i++) | |
7547 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7548 | tdep->register_names[i]); | |
7549 | } | |
90884b2b L |
7550 | |
7551 | return valid_p; | |
7552 | } | |
7553 | ||
7ad10968 HZ |
7554 | \f |
7555 | static struct gdbarch * | |
7556 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7557 | { | |
7558 | struct gdbarch_tdep *tdep; | |
7559 | struct gdbarch *gdbarch; | |
90884b2b L |
7560 | struct tdesc_arch_data *tdesc_data; |
7561 | const struct target_desc *tdesc; | |
1ba53b71 | 7562 | int mm0_regnum; |
c131fcee | 7563 | int ymm0_regnum; |
7ad10968 HZ |
7564 | |
7565 | /* If there is already a candidate, use it. */ | |
7566 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7567 | if (arches != NULL) | |
7568 | return arches->gdbarch; | |
7569 | ||
7570 | /* Allocate space for the new architecture. */ | |
7571 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7572 | gdbarch = gdbarch_alloc (&info, tdep); | |
7573 | ||
7574 | /* General-purpose registers. */ | |
7575 | tdep->gregset = NULL; | |
7576 | tdep->gregset_reg_offset = NULL; | |
7577 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7578 | tdep->sizeof_gregset = 0; | |
7579 | ||
7580 | /* Floating-point registers. */ | |
7581 | tdep->fpregset = NULL; | |
7582 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7583 | ||
c131fcee L |
7584 | tdep->xstateregset = NULL; |
7585 | ||
7ad10968 HZ |
7586 | /* The default settings include the FPU registers, the MMX registers |
7587 | and the SSE registers. This can be overridden for a specific ABI | |
7588 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7589 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7590 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7591 | |
7592 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7593 | ||
7ad10968 HZ |
7594 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7595 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7596 | ||
7597 | tdep->jb_pc_offset = -1; | |
7598 | tdep->struct_return = pcc_struct_return; | |
7599 | tdep->sigtramp_start = 0; | |
7600 | tdep->sigtramp_end = 0; | |
7601 | tdep->sigtramp_p = i386_sigtramp_p; | |
7602 | tdep->sigcontext_addr = NULL; | |
7603 | tdep->sc_reg_offset = NULL; | |
7604 | tdep->sc_pc_offset = -1; | |
7605 | tdep->sc_sp_offset = -1; | |
7606 | ||
c131fcee L |
7607 | tdep->xsave_xcr0_offset = -1; |
7608 | ||
cf648174 HZ |
7609 | tdep->record_regmap = i386_record_regmap; |
7610 | ||
205c306f DM |
7611 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7612 | ||
7ad10968 HZ |
7613 | /* The format used for `long double' on almost all i386 targets is |
7614 | the i387 extended floating-point format. In fact, of all targets | |
7615 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7616 | on having a `long double' that's not `long' at all. */ | |
7617 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7618 | ||
7619 | /* Although the i387 extended floating-point has only 80 significant | |
7620 | bits, a `long double' actually takes up 96, probably to enforce | |
7621 | alignment. */ | |
7622 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7623 | ||
7ad10968 HZ |
7624 | /* Register numbers of various important registers. */ |
7625 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7626 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7627 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7628 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7629 | ||
7630 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7631 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7632 | differ in how they number %ebp, %esp, %eflags, and the | |
7633 | floating-point registers, and are implemented by the arrays | |
7634 | dbx_register_map[] and svr4_dbx_register_map in | |
7635 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7636 | gcc/config/i386.c, which it designates as the "default" register | |
7637 | map used in 64bit mode. This last register numbering scheme is | |
7638 | implemented in dbx64_register_map, and is used for AMD64; see | |
7639 | amd64-tdep.c. | |
7640 | ||
7641 | Currently, each GCC i386 target always uses the same register | |
7642 | numbering scheme across all its supported debugging formats | |
7643 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7644 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7645 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7646 | respective config header in a manner independent of the requested | |
7647 | output debugging format. | |
7648 | ||
7649 | This does not match the arrangement below, which presumes that | |
7650 | the SDB and stabs numbering schemes differ from the DWARF and | |
7651 | DWARF 2 ones. The reason for this arrangement is that it is | |
7652 | likely to get the numbering scheme for the target's | |
7653 | default/native debug format right. For targets where GCC is the | |
7654 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7655 | targets where the native toolchain uses a different numbering | |
7656 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7657 | the defaults below will have to be overridden, like | |
7658 | i386_elf_init_abi() does. */ | |
7659 | ||
7660 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7661 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7662 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7663 | ||
7664 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7665 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7666 | ||
7667 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7668 | be in use on any of the supported i386 targets. */ | |
7669 | ||
7670 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7671 | ||
7672 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7673 | ||
7674 | /* Call dummy code. */ | |
a9b8d892 JK |
7675 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
7676 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 7677 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 7678 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7679 | |
7680 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7681 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7682 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7683 | ||
7684 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7685 | ||
7686 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7687 | ||
7688 | /* Stack grows downward. */ | |
7689 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7690 | ||
7691 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7692 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7693 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7694 | ||
7695 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7696 | ||
7ad10968 HZ |
7697 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7698 | ||
7699 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7700 | ||
7701 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7702 | ||
7703 | /* Add the i386 register groups. */ | |
7704 | i386_add_reggroups (gdbarch); | |
90884b2b | 7705 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7706 | |
143985b7 AF |
7707 | /* Helper for function argument information. */ |
7708 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7709 | ||
06da04c6 | 7710 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7711 | appended to the list first, so that it supercedes the DWARF |
7712 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7713 | currently fails). */ |
7714 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7715 | ||
7716 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7717 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7718 | CFI info will be used if it is available. */ |
10458914 | 7719 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7720 | |
acd5c798 | 7721 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7722 | |
1ba53b71 | 7723 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7724 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7725 | i386_pseudo_register_read_value); | |
90884b2b L |
7726 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7727 | ||
7728 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7729 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7730 | ||
c131fcee L |
7731 | /* Override the normal target description method to make the AVX |
7732 | upper halves anonymous. */ | |
7733 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7734 | ||
7735 | /* Even though the default ABI only includes general-purpose registers, | |
7736 | floating-point registers and the SSE registers, we have to leave a | |
7737 | gap for the upper AVX registers. */ | |
7738 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7739 | |
7740 | /* Get the x86 target description from INFO. */ | |
7741 | tdesc = info.target_desc; | |
7742 | if (! tdesc_has_registers (tdesc)) | |
7743 | tdesc = tdesc_i386; | |
7744 | tdep->tdesc = tdesc; | |
7745 | ||
7746 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7747 | tdep->register_names = i386_register_names; | |
7748 | ||
c131fcee L |
7749 | /* No upper YMM registers. */ |
7750 | tdep->ymmh_register_names = NULL; | |
7751 | tdep->ymm0h_regnum = -1; | |
7752 | ||
1ba53b71 L |
7753 | tdep->num_byte_regs = 8; |
7754 | tdep->num_word_regs = 8; | |
7755 | tdep->num_dword_regs = 0; | |
7756 | tdep->num_mmx_regs = 8; | |
c131fcee | 7757 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7758 | |
90884b2b L |
7759 | tdesc_data = tdesc_data_alloc (); |
7760 | ||
dde08ee1 PA |
7761 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7762 | ||
6710bf39 SS |
7763 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7764 | ||
3ce1502b | 7765 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7766 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7767 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7768 | |
c131fcee L |
7769 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7770 | { | |
7771 | tdesc_data_cleanup (tdesc_data); | |
7772 | xfree (tdep); | |
7773 | gdbarch_free (gdbarch); | |
7774 | return NULL; | |
7775 | } | |
7776 | ||
1ba53b71 L |
7777 | /* Wire in pseudo registers. Number of pseudo registers may be |
7778 | changed. */ | |
7779 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7780 | + tdep->num_word_regs | |
7781 | + tdep->num_dword_regs | |
c131fcee L |
7782 | + tdep->num_mmx_regs |
7783 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7784 | |
90884b2b L |
7785 | /* Target description may be changed. */ |
7786 | tdesc = tdep->tdesc; | |
7787 | ||
90884b2b L |
7788 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7789 | ||
7790 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7791 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7792 | ||
1ba53b71 L |
7793 | /* Make %al the first pseudo-register. */ |
7794 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7795 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7796 | ||
c131fcee | 7797 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7798 | if (tdep->num_dword_regs) |
7799 | { | |
1c6272a6 | 7800 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7801 | tdep->eax_regnum = ymm0_regnum; |
7802 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7803 | } |
7804 | else | |
7805 | tdep->eax_regnum = -1; | |
7806 | ||
c131fcee L |
7807 | mm0_regnum = ymm0_regnum; |
7808 | if (tdep->num_ymm_regs) | |
7809 | { | |
1c6272a6 | 7810 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7811 | tdep->ymm0_regnum = ymm0_regnum; |
7812 | mm0_regnum += tdep->num_ymm_regs; | |
7813 | } | |
7814 | else | |
7815 | tdep->ymm0_regnum = -1; | |
7816 | ||
1ba53b71 L |
7817 | if (tdep->num_mmx_regs != 0) |
7818 | { | |
1c6272a6 | 7819 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7820 | tdep->mm0_regnum = mm0_regnum; |
7821 | } | |
7822 | else | |
7823 | tdep->mm0_regnum = -1; | |
7824 | ||
06da04c6 | 7825 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7826 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7827 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7828 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7829 | |
8446b36a MK |
7830 | /* If we have a register mapping, enable the generic core file |
7831 | support, unless it has already been enabled. */ | |
7832 | if (tdep->gregset_reg_offset | |
7833 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7834 | set_gdbarch_regset_from_core_section (gdbarch, | |
7835 | i386_regset_from_core_section); | |
7836 | ||
514f746b AR |
7837 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7838 | i386_skip_permanent_breakpoint); | |
7839 | ||
7a697b8d SS |
7840 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7841 | i386_fast_tracepoint_valid_at); | |
7842 | ||
a62cc96e AC |
7843 | return gdbarch; |
7844 | } | |
7845 | ||
8201327c MK |
7846 | static enum gdb_osabi |
7847 | i386_coff_osabi_sniffer (bfd *abfd) | |
7848 | { | |
762c5349 MK |
7849 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7850 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7851 | return GDB_OSABI_GO32; |
7852 | ||
7853 | return GDB_OSABI_UNKNOWN; | |
7854 | } | |
8201327c MK |
7855 | \f |
7856 | ||
28e9e0f0 MK |
7857 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7858 | void _initialize_i386_tdep (void); | |
7859 | ||
c906108c | 7860 | void |
fba45db2 | 7861 | _initialize_i386_tdep (void) |
c906108c | 7862 | { |
a62cc96e AC |
7863 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7864 | ||
fc338970 | 7865 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7866 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7867 | &disassembly_flavor, _("\ | |
7868 | Set the disassembly flavor."), _("\ | |
7869 | Show the disassembly flavor."), _("\ | |
7870 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7871 | NULL, | |
7872 | NULL, /* FIXME: i18n: */ | |
7873 | &setlist, &showlist); | |
8201327c MK |
7874 | |
7875 | /* Add the variable that controls the convention for returning | |
7876 | structs. */ | |
7ab04401 AC |
7877 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7878 | &struct_convention, _("\ | |
7879 | Set the convention for returning small structs."), _("\ | |
7880 | Show the convention for returning small structs."), _("\ | |
7881 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7882 | is \"default\"."), | |
7883 | NULL, | |
7884 | NULL, /* FIXME: i18n: */ | |
7885 | &setlist, &showlist); | |
8201327c MK |
7886 | |
7887 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7888 | i386_coff_osabi_sniffer); | |
8201327c | 7889 | |
05816f70 | 7890 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7891 | i386_svr4_init_abi); |
05816f70 | 7892 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7893 | i386_go32_init_abi); |
38c968cf | 7894 | |
209bd28e | 7895 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7896 | i386_init_reggroups (); |
90884b2b L |
7897 | |
7898 | /* Initialize the standard target descriptions. */ | |
7899 | initialize_tdesc_i386 (); | |
3a13a53b | 7900 | initialize_tdesc_i386_mmx (); |
c131fcee | 7901 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7902 | |
7903 | /* Tell remote stub that we support XML target description. */ | |
7904 | register_remote_support_xml ("i386"); | |
c906108c | 7905 | } |