Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
32d0add0 | 3 | Copyright (C) 1988-2015 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
45741a9c | 31 | #include "infrun.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
df7e5265 | 49 | #include "x86-xstate.h" |
d2a7c97a | 50 | |
7ad10968 | 51 | #include "record.h" |
d02ed0bb | 52 | #include "record-full.h" |
7ad10968 HZ |
53 | #include <stdint.h> |
54 | ||
90884b2b | 55 | #include "features/i386/i386.c" |
c131fcee | 56 | #include "features/i386/i386-avx.c" |
1dbcd68c | 57 | #include "features/i386/i386-mpx.c" |
01f9f808 | 58 | #include "features/i386/i386-avx512.c" |
3a13a53b | 59 | #include "features/i386/i386-mmx.c" |
90884b2b | 60 | |
6710bf39 SS |
61 | #include "ax.h" |
62 | #include "ax-gdb.h" | |
63 | ||
55aa24fb SDJ |
64 | #include "stap-probe.h" |
65 | #include "user-regs.h" | |
66 | #include "cli/cli-utils.h" | |
67 | #include "expression.h" | |
68 | #include "parser-defs.h" | |
69 | #include <ctype.h> | |
70 | ||
c4fc7f1b | 71 | /* Register names. */ |
c40e1eab | 72 | |
90884b2b | 73 | static const char *i386_register_names[] = |
fc633446 MK |
74 | { |
75 | "eax", "ecx", "edx", "ebx", | |
76 | "esp", "ebp", "esi", "edi", | |
77 | "eip", "eflags", "cs", "ss", | |
78 | "ds", "es", "fs", "gs", | |
79 | "st0", "st1", "st2", "st3", | |
80 | "st4", "st5", "st6", "st7", | |
81 | "fctrl", "fstat", "ftag", "fiseg", | |
82 | "fioff", "foseg", "fooff", "fop", | |
83 | "xmm0", "xmm1", "xmm2", "xmm3", | |
84 | "xmm4", "xmm5", "xmm6", "xmm7", | |
85 | "mxcsr" | |
86 | }; | |
87 | ||
01f9f808 MS |
88 | static const char *i386_zmm_names[] = |
89 | { | |
90 | "zmm0", "zmm1", "zmm2", "zmm3", | |
91 | "zmm4", "zmm5", "zmm6", "zmm7" | |
92 | }; | |
93 | ||
94 | static const char *i386_zmmh_names[] = | |
95 | { | |
96 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
97 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
98 | }; | |
99 | ||
100 | static const char *i386_k_names[] = | |
101 | { | |
102 | "k0", "k1", "k2", "k3", | |
103 | "k4", "k5", "k6", "k7" | |
104 | }; | |
105 | ||
c131fcee L |
106 | static const char *i386_ymm_names[] = |
107 | { | |
108 | "ymm0", "ymm1", "ymm2", "ymm3", | |
109 | "ymm4", "ymm5", "ymm6", "ymm7", | |
110 | }; | |
111 | ||
112 | static const char *i386_ymmh_names[] = | |
113 | { | |
114 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
115 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
116 | }; | |
117 | ||
1dbcd68c WT |
118 | static const char *i386_mpx_names[] = |
119 | { | |
120 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
121 | }; | |
122 | ||
123 | /* Register names for MPX pseudo-registers. */ | |
124 | ||
125 | static const char *i386_bnd_names[] = | |
126 | { | |
127 | "bnd0", "bnd1", "bnd2", "bnd3" | |
128 | }; | |
129 | ||
c4fc7f1b | 130 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 131 | |
90884b2b | 132 | static const char *i386_mmx_names[] = |
28fc6740 AC |
133 | { |
134 | "mm0", "mm1", "mm2", "mm3", | |
135 | "mm4", "mm5", "mm6", "mm7" | |
136 | }; | |
c40e1eab | 137 | |
1ba53b71 L |
138 | /* Register names for byte pseudo-registers. */ |
139 | ||
140 | static const char *i386_byte_names[] = | |
141 | { | |
142 | "al", "cl", "dl", "bl", | |
143 | "ah", "ch", "dh", "bh" | |
144 | }; | |
145 | ||
146 | /* Register names for word pseudo-registers. */ | |
147 | ||
148 | static const char *i386_word_names[] = | |
149 | { | |
150 | "ax", "cx", "dx", "bx", | |
9cad29ac | 151 | "", "bp", "si", "di" |
1ba53b71 L |
152 | }; |
153 | ||
01f9f808 MS |
154 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
155 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
156 | we have 16 upper ZMM regs that have to be handled differently. */ | |
157 | ||
158 | const int num_lower_zmm_regs = 16; | |
159 | ||
1ba53b71 | 160 | /* MMX register? */ |
c40e1eab | 161 | |
28fc6740 | 162 | static int |
5716833c | 163 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 164 | { |
1ba53b71 L |
165 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
166 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
167 | |
168 | if (mm0_regnum < 0) | |
169 | return 0; | |
170 | ||
1ba53b71 L |
171 | regnum -= mm0_regnum; |
172 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
173 | } | |
174 | ||
175 | /* Byte register? */ | |
176 | ||
177 | int | |
178 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
179 | { | |
180 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
181 | ||
182 | regnum -= tdep->al_regnum; | |
183 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
184 | } | |
185 | ||
186 | /* Word register? */ | |
187 | ||
188 | int | |
189 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
190 | { | |
191 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
192 | ||
193 | regnum -= tdep->ax_regnum; | |
194 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
195 | } | |
196 | ||
197 | /* Dword register? */ | |
198 | ||
199 | int | |
200 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
201 | { | |
202 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
203 | int eax_regnum = tdep->eax_regnum; | |
204 | ||
205 | if (eax_regnum < 0) | |
206 | return 0; | |
207 | ||
208 | regnum -= eax_regnum; | |
209 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
210 | } |
211 | ||
01f9f808 MS |
212 | /* AVX512 register? */ |
213 | ||
214 | int | |
215 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
216 | { | |
217 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
218 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
219 | ||
220 | if (zmm0h_regnum < 0) | |
221 | return 0; | |
222 | ||
223 | regnum -= zmm0h_regnum; | |
224 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
225 | } | |
226 | ||
227 | int | |
228 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
229 | { | |
230 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
231 | int zmm0_regnum = tdep->zmm0_regnum; | |
232 | ||
233 | if (zmm0_regnum < 0) | |
234 | return 0; | |
235 | ||
236 | regnum -= zmm0_regnum; | |
237 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
238 | } | |
239 | ||
240 | int | |
241 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
242 | { | |
243 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
244 | int k0_regnum = tdep->k0_regnum; | |
245 | ||
246 | if (k0_regnum < 0) | |
247 | return 0; | |
248 | ||
249 | regnum -= k0_regnum; | |
250 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
251 | } | |
252 | ||
9191d390 | 253 | static int |
c131fcee L |
254 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
255 | { | |
256 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
257 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
258 | ||
259 | if (ymm0h_regnum < 0) | |
260 | return 0; | |
261 | ||
262 | regnum -= ymm0h_regnum; | |
263 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
264 | } | |
265 | ||
266 | /* AVX register? */ | |
267 | ||
268 | int | |
269 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
270 | { | |
271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
272 | int ymm0_regnum = tdep->ymm0_regnum; | |
273 | ||
274 | if (ymm0_regnum < 0) | |
275 | return 0; | |
276 | ||
277 | regnum -= ymm0_regnum; | |
278 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
279 | } | |
280 | ||
01f9f808 MS |
281 | static int |
282 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
283 | { | |
284 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
285 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
286 | ||
287 | if (ymm16h_regnum < 0) | |
288 | return 0; | |
289 | ||
290 | regnum -= ymm16h_regnum; | |
291 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
292 | } | |
293 | ||
294 | int | |
295 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
296 | { | |
297 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
298 | int ymm16_regnum = tdep->ymm16_regnum; | |
299 | ||
300 | if (ymm16_regnum < 0) | |
301 | return 0; | |
302 | ||
303 | regnum -= ymm16_regnum; | |
304 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
305 | } | |
306 | ||
1dbcd68c WT |
307 | /* BND register? */ |
308 | ||
309 | int | |
310 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
311 | { | |
312 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
313 | int bnd0_regnum = tdep->bnd0_regnum; | |
314 | ||
315 | if (bnd0_regnum < 0) | |
316 | return 0; | |
317 | ||
318 | regnum -= bnd0_regnum; | |
319 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
320 | } | |
321 | ||
5716833c | 322 | /* SSE register? */ |
23a34459 | 323 | |
c131fcee L |
324 | int |
325 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 326 | { |
5716833c | 327 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 328 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 329 | |
c131fcee | 330 | if (num_xmm_regs == 0) |
5716833c MK |
331 | return 0; |
332 | ||
c131fcee L |
333 | regnum -= I387_XMM0_REGNUM (tdep); |
334 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
335 | } |
336 | ||
01f9f808 MS |
337 | /* XMM_512 register? */ |
338 | ||
339 | int | |
340 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
341 | { | |
342 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
343 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
344 | ||
345 | if (num_xmm_avx512_regs == 0) | |
346 | return 0; | |
347 | ||
348 | regnum -= I387_XMM16_REGNUM (tdep); | |
349 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
350 | } | |
351 | ||
5716833c MK |
352 | static int |
353 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 354 | { |
5716833c MK |
355 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
356 | ||
20a6ec49 | 357 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
358 | return 0; |
359 | ||
20a6ec49 | 360 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
361 | } |
362 | ||
5716833c | 363 | /* FP register? */ |
23a34459 AC |
364 | |
365 | int | |
20a6ec49 | 366 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 367 | { |
20a6ec49 MD |
368 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
369 | ||
370 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
371 | return 0; |
372 | ||
20a6ec49 MD |
373 | return (I387_ST0_REGNUM (tdep) <= regnum |
374 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
375 | } |
376 | ||
377 | int | |
20a6ec49 | 378 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 379 | { |
20a6ec49 MD |
380 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
381 | ||
382 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
383 | return 0; |
384 | ||
20a6ec49 MD |
385 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
386 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
387 | } |
388 | ||
1dbcd68c WT |
389 | /* BNDr (raw) register? */ |
390 | ||
391 | static int | |
392 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
393 | { | |
394 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
395 | ||
396 | if (I387_BND0R_REGNUM (tdep) < 0) | |
397 | return 0; | |
398 | ||
399 | regnum -= tdep->bnd0r_regnum; | |
400 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
401 | } | |
402 | ||
403 | /* BND control register? */ | |
404 | ||
405 | static int | |
406 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
407 | { | |
408 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
409 | ||
410 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
411 | return 0; | |
412 | ||
413 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
414 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
415 | } | |
416 | ||
c131fcee L |
417 | /* Return the name of register REGNUM, or the empty string if it is |
418 | an anonymous register. */ | |
419 | ||
420 | static const char * | |
421 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
422 | { | |
423 | /* Hide the upper YMM registers. */ | |
424 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
425 | return ""; | |
426 | ||
01f9f808 MS |
427 | /* Hide the upper YMM16-31 registers. */ |
428 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
429 | return ""; | |
430 | ||
431 | /* Hide the upper ZMM registers. */ | |
432 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
433 | return ""; | |
434 | ||
c131fcee L |
435 | return tdesc_register_name (gdbarch, regnum); |
436 | } | |
437 | ||
30b0e2d8 | 438 | /* Return the name of register REGNUM. */ |
fc633446 | 439 | |
1ba53b71 | 440 | const char * |
90884b2b | 441 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 442 | { |
1ba53b71 | 443 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
444 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
445 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
446 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
447 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
448 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
449 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
450 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
451 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
452 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
453 | return i386_byte_names[regnum - tdep->al_regnum]; | |
454 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
455 | return i386_word_names[regnum - tdep->ax_regnum]; | |
456 | ||
457 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
458 | } |
459 | ||
c4fc7f1b | 460 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
461 | number used by GDB. */ |
462 | ||
8201327c | 463 | static int |
d3f73121 | 464 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 465 | { |
20a6ec49 MD |
466 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
467 | ||
c4fc7f1b MK |
468 | /* This implements what GCC calls the "default" register map |
469 | (dbx_register_map[]). */ | |
470 | ||
85540d8c MK |
471 | if (reg >= 0 && reg <= 7) |
472 | { | |
9872ad24 JB |
473 | /* General-purpose registers. The debug info calls %ebp |
474 | register 4, and %esp register 5. */ | |
475 | if (reg == 4) | |
476 | return 5; | |
477 | else if (reg == 5) | |
478 | return 4; | |
479 | else return reg; | |
85540d8c MK |
480 | } |
481 | else if (reg >= 12 && reg <= 19) | |
482 | { | |
483 | /* Floating-point registers. */ | |
20a6ec49 | 484 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
485 | } |
486 | else if (reg >= 21 && reg <= 28) | |
487 | { | |
488 | /* SSE registers. */ | |
c131fcee L |
489 | int ymm0_regnum = tdep->ymm0_regnum; |
490 | ||
491 | if (ymm0_regnum >= 0 | |
492 | && i386_xmm_regnum_p (gdbarch, reg)) | |
493 | return reg - 21 + ymm0_regnum; | |
494 | else | |
495 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
496 | } |
497 | else if (reg >= 29 && reg <= 36) | |
498 | { | |
499 | /* MMX registers. */ | |
20a6ec49 | 500 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
501 | } |
502 | ||
503 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 504 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
505 | } |
506 | ||
c4fc7f1b MK |
507 | /* Convert SVR4 register number REG to the appropriate register number |
508 | used by GDB. */ | |
85540d8c | 509 | |
8201327c | 510 | static int |
d3f73121 | 511 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 512 | { |
20a6ec49 MD |
513 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
514 | ||
c4fc7f1b MK |
515 | /* This implements the GCC register map that tries to be compatible |
516 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
517 | ||
518 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
519 | numbers the floating point registers differently. */ |
520 | if (reg >= 0 && reg <= 9) | |
521 | { | |
acd5c798 | 522 | /* General-purpose registers. */ |
85540d8c MK |
523 | return reg; |
524 | } | |
525 | else if (reg >= 11 && reg <= 18) | |
526 | { | |
527 | /* Floating-point registers. */ | |
20a6ec49 | 528 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 529 | } |
c6f4c129 | 530 | else if (reg >= 21 && reg <= 36) |
85540d8c | 531 | { |
c4fc7f1b | 532 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 533 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
534 | } |
535 | ||
c6f4c129 JB |
536 | switch (reg) |
537 | { | |
20a6ec49 MD |
538 | case 37: return I387_FCTRL_REGNUM (tdep); |
539 | case 38: return I387_FSTAT_REGNUM (tdep); | |
540 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
541 | case 40: return I386_ES_REGNUM; |
542 | case 41: return I386_CS_REGNUM; | |
543 | case 42: return I386_SS_REGNUM; | |
544 | case 43: return I386_DS_REGNUM; | |
545 | case 44: return I386_FS_REGNUM; | |
546 | case 45: return I386_GS_REGNUM; | |
547 | } | |
548 | ||
85540d8c | 549 | /* This will hopefully provoke a warning. */ |
d3f73121 | 550 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 551 | } |
5716833c | 552 | |
fc338970 | 553 | \f |
917317f4 | 554 | |
fc338970 MK |
555 | /* This is the variable that is set with "set disassembly-flavor", and |
556 | its legitimate values. */ | |
53904c9e AC |
557 | static const char att_flavor[] = "att"; |
558 | static const char intel_flavor[] = "intel"; | |
40478521 | 559 | static const char *const valid_flavors[] = |
c5aa993b | 560 | { |
c906108c SS |
561 | att_flavor, |
562 | intel_flavor, | |
563 | NULL | |
564 | }; | |
53904c9e | 565 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 566 | \f |
c906108c | 567 | |
acd5c798 MK |
568 | /* Use the program counter to determine the contents and size of a |
569 | breakpoint instruction. Return a pointer to a string of bytes that | |
570 | encode a breakpoint instruction, store the length of the string in | |
571 | *LEN and optionally adjust *PC to point to the correct memory | |
572 | location for inserting the breakpoint. | |
c906108c | 573 | |
acd5c798 MK |
574 | On the i386 we have a single breakpoint that fits in a single byte |
575 | and can be inserted anywhere. | |
c906108c | 576 | |
acd5c798 | 577 | This function is 64-bit safe. */ |
63c0089f MK |
578 | |
579 | static const gdb_byte * | |
67d57894 | 580 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 581 | { |
63c0089f MK |
582 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
583 | ||
acd5c798 MK |
584 | *len = sizeof (break_insn); |
585 | return break_insn; | |
c906108c | 586 | } |
237fc4c9 PA |
587 | \f |
588 | /* Displaced instruction handling. */ | |
589 | ||
1903f0e6 DE |
590 | /* Skip the legacy instruction prefixes in INSN. |
591 | Not all prefixes are valid for any particular insn | |
592 | but we needn't care, the insn will fault if it's invalid. | |
593 | The result is a pointer to the first opcode byte, | |
594 | or NULL if we run off the end of the buffer. */ | |
595 | ||
596 | static gdb_byte * | |
597 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
598 | { | |
599 | gdb_byte *end = insn + max_len; | |
600 | ||
601 | while (insn < end) | |
602 | { | |
603 | switch (*insn) | |
604 | { | |
605 | case DATA_PREFIX_OPCODE: | |
606 | case ADDR_PREFIX_OPCODE: | |
607 | case CS_PREFIX_OPCODE: | |
608 | case DS_PREFIX_OPCODE: | |
609 | case ES_PREFIX_OPCODE: | |
610 | case FS_PREFIX_OPCODE: | |
611 | case GS_PREFIX_OPCODE: | |
612 | case SS_PREFIX_OPCODE: | |
613 | case LOCK_PREFIX_OPCODE: | |
614 | case REPE_PREFIX_OPCODE: | |
615 | case REPNE_PREFIX_OPCODE: | |
616 | ++insn; | |
617 | continue; | |
618 | default: | |
619 | return insn; | |
620 | } | |
621 | } | |
622 | ||
623 | return NULL; | |
624 | } | |
237fc4c9 PA |
625 | |
626 | static int | |
1903f0e6 | 627 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 628 | { |
1777feb0 | 629 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
630 | if (insn[0] == 0xea) |
631 | return 1; | |
632 | ||
633 | if (insn[0] == 0xff) | |
634 | { | |
1777feb0 | 635 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
636 | if ((insn[1] & 0x38) == 0x20) |
637 | return 1; | |
638 | ||
1777feb0 | 639 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
640 | if ((insn[1] & 0x38) == 0x28) |
641 | return 1; | |
642 | } | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
c2170eef MM |
647 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
648 | ||
649 | static int | |
650 | i386_jmp_p (const gdb_byte *insn) | |
651 | { | |
652 | /* jump short, relative. */ | |
653 | if (insn[0] == 0xeb) | |
654 | return 1; | |
655 | ||
656 | /* jump near, relative. */ | |
657 | if (insn[0] == 0xe9) | |
658 | return 1; | |
659 | ||
660 | return i386_absolute_jmp_p (insn); | |
661 | } | |
662 | ||
237fc4c9 | 663 | static int |
1903f0e6 | 664 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 665 | { |
1777feb0 | 666 | /* call far, absolute. */ |
237fc4c9 PA |
667 | if (insn[0] == 0x9a) |
668 | return 1; | |
669 | ||
670 | if (insn[0] == 0xff) | |
671 | { | |
1777feb0 | 672 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
673 | if ((insn[1] & 0x38) == 0x10) |
674 | return 1; | |
675 | ||
1777feb0 | 676 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
677 | if ((insn[1] & 0x38) == 0x18) |
678 | return 1; | |
679 | } | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | static int | |
1903f0e6 | 685 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
686 | { |
687 | switch (insn[0]) | |
688 | { | |
1777feb0 | 689 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 690 | case 0xc3: /* ret near */ |
1777feb0 | 691 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
692 | case 0xcb: /* ret far */ |
693 | case 0xcf: /* iret */ | |
694 | return 1; | |
695 | ||
696 | default: | |
697 | return 0; | |
698 | } | |
699 | } | |
700 | ||
701 | static int | |
1903f0e6 | 702 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
703 | { |
704 | if (i386_absolute_call_p (insn)) | |
705 | return 1; | |
706 | ||
1777feb0 | 707 | /* call near, relative. */ |
237fc4c9 PA |
708 | if (insn[0] == 0xe8) |
709 | return 1; | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
237fc4c9 PA |
714 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
715 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 716 | |
237fc4c9 | 717 | static int |
b55078be | 718 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 719 | { |
9a7f938f JK |
720 | /* Is it 'int $0x80'? */ |
721 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
722 | /* Or is it 'sysenter'? */ | |
723 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
724 | /* Or is it 'syscall'? */ | |
725 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
726 | { |
727 | *lengthp = 2; | |
728 | return 1; | |
729 | } | |
730 | ||
731 | return 0; | |
732 | } | |
733 | ||
c2170eef MM |
734 | /* The gdbarch insn_is_call method. */ |
735 | ||
736 | static int | |
737 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
738 | { | |
739 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
740 | ||
741 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
742 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
743 | ||
744 | return i386_call_p (insn); | |
745 | } | |
746 | ||
747 | /* The gdbarch insn_is_ret method. */ | |
748 | ||
749 | static int | |
750 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
751 | { | |
752 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
753 | ||
754 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
755 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
756 | ||
757 | return i386_ret_p (insn); | |
758 | } | |
759 | ||
760 | /* The gdbarch insn_is_jump method. */ | |
761 | ||
762 | static int | |
763 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
764 | { | |
765 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
766 | ||
767 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
768 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
769 | ||
770 | return i386_jmp_p (insn); | |
771 | } | |
772 | ||
b55078be DE |
773 | /* Some kernels may run one past a syscall insn, so we have to cope. |
774 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
775 | ||
776 | struct displaced_step_closure * | |
777 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
778 | CORE_ADDR from, CORE_ADDR to, | |
779 | struct regcache *regs) | |
780 | { | |
781 | size_t len = gdbarch_max_insn_length (gdbarch); | |
782 | gdb_byte *buf = xmalloc (len); | |
783 | ||
784 | read_memory (from, buf, len); | |
785 | ||
786 | /* GDB may get control back after the insn after the syscall. | |
787 | Presumably this is a kernel bug. | |
788 | If this is a syscall, make sure there's a nop afterwards. */ | |
789 | { | |
790 | int syscall_length; | |
791 | gdb_byte *insn; | |
792 | ||
793 | insn = i386_skip_prefixes (buf, len); | |
794 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
795 | insn[syscall_length] = NOP_OPCODE; | |
796 | } | |
797 | ||
798 | write_memory (to, buf, len); | |
799 | ||
800 | if (debug_displaced) | |
801 | { | |
802 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
803 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
804 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
805 | } | |
806 | ||
807 | return (struct displaced_step_closure *) buf; | |
808 | } | |
809 | ||
237fc4c9 PA |
810 | /* Fix up the state of registers and memory after having single-stepped |
811 | a displaced instruction. */ | |
1903f0e6 | 812 | |
237fc4c9 PA |
813 | void |
814 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
815 | struct displaced_step_closure *closure, | |
816 | CORE_ADDR from, CORE_ADDR to, | |
817 | struct regcache *regs) | |
818 | { | |
e17a4113 UW |
819 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
820 | ||
237fc4c9 PA |
821 | /* The offset we applied to the instruction's address. |
822 | This could well be negative (when viewed as a signed 32-bit | |
823 | value), but ULONGEST won't reflect that, so take care when | |
824 | applying it. */ | |
825 | ULONGEST insn_offset = to - from; | |
826 | ||
827 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
828 | copy of the instruction. */ | |
829 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
830 | /* The start of the insn, needed in case we see some prefixes. */ |
831 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
832 | |
833 | if (debug_displaced) | |
834 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 835 | "displaced: fixup (%s, %s), " |
237fc4c9 | 836 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
837 | paddress (gdbarch, from), paddress (gdbarch, to), |
838 | insn[0], insn[1]); | |
237fc4c9 PA |
839 | |
840 | /* The list of issues to contend with here is taken from | |
841 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
842 | Yay for Free Software! */ | |
843 | ||
844 | /* Relocate the %eip, if necessary. */ | |
845 | ||
1903f0e6 DE |
846 | /* The instruction recognizers we use assume any leading prefixes |
847 | have been skipped. */ | |
848 | { | |
849 | /* This is the size of the buffer in closure. */ | |
850 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
851 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
852 | /* If there are too many prefixes, just ignore the insn. | |
853 | It will fault when run. */ | |
854 | if (opcode != NULL) | |
855 | insn = opcode; | |
856 | } | |
857 | ||
237fc4c9 PA |
858 | /* Except in the case of absolute or indirect jump or call |
859 | instructions, or a return instruction, the new eip is relative to | |
860 | the displaced instruction; make it relative. Well, signal | |
861 | handler returns don't need relocation either, but we use the | |
862 | value of %eip to recognize those; see below. */ | |
863 | if (! i386_absolute_jmp_p (insn) | |
864 | && ! i386_absolute_call_p (insn) | |
865 | && ! i386_ret_p (insn)) | |
866 | { | |
867 | ULONGEST orig_eip; | |
b55078be | 868 | int insn_len; |
237fc4c9 PA |
869 | |
870 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
871 | ||
872 | /* A signal trampoline system call changes the %eip, resuming | |
873 | execution of the main program after the signal handler has | |
874 | returned. That makes them like 'return' instructions; we | |
875 | shouldn't relocate %eip. | |
876 | ||
877 | But most system calls don't, and we do need to relocate %eip. | |
878 | ||
879 | Our heuristic for distinguishing these cases: if stepping | |
880 | over the system call instruction left control directly after | |
881 | the instruction, the we relocate --- control almost certainly | |
882 | doesn't belong in the displaced copy. Otherwise, we assume | |
883 | the instruction has put control where it belongs, and leave | |
884 | it unrelocated. Goodness help us if there are PC-relative | |
885 | system calls. */ | |
886 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
887 | && orig_eip != to + (insn - insn_start) + insn_len |
888 | /* GDB can get control back after the insn after the syscall. | |
889 | Presumably this is a kernel bug. | |
890 | i386_displaced_step_copy_insn ensures its a nop, | |
891 | we add one to the length for it. */ | |
892 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
893 | { |
894 | if (debug_displaced) | |
895 | fprintf_unfiltered (gdb_stdlog, | |
896 | "displaced: syscall changed %%eip; " | |
897 | "not relocating\n"); | |
898 | } | |
899 | else | |
900 | { | |
901 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
902 | ||
1903f0e6 DE |
903 | /* If we just stepped over a breakpoint insn, we don't backup |
904 | the pc on purpose; this is to match behaviour without | |
905 | stepping. */ | |
237fc4c9 PA |
906 | |
907 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
908 | ||
909 | if (debug_displaced) | |
910 | fprintf_unfiltered (gdb_stdlog, | |
911 | "displaced: " | |
5af949e3 UW |
912 | "relocated %%eip from %s to %s\n", |
913 | paddress (gdbarch, orig_eip), | |
914 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
915 | } |
916 | } | |
917 | ||
918 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
919 | pushed value, and should be cleared. We'll leave this for later, | |
920 | since GDB already messes up the TF flag when stepping over a | |
921 | pushfl. */ | |
922 | ||
923 | /* If the instruction was a call, the return address now atop the | |
924 | stack is the address following the copied instruction. We need | |
925 | to make it the address following the original instruction. */ | |
926 | if (i386_call_p (insn)) | |
927 | { | |
928 | ULONGEST esp; | |
929 | ULONGEST retaddr; | |
930 | const ULONGEST retaddr_len = 4; | |
931 | ||
932 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 933 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 934 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 935 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
936 | |
937 | if (debug_displaced) | |
938 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
939 | "displaced: relocated return addr at %s to %s\n", |
940 | paddress (gdbarch, esp), | |
941 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
942 | } |
943 | } | |
dde08ee1 PA |
944 | |
945 | static void | |
946 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
947 | { | |
948 | target_write_memory (*to, buf, len); | |
949 | *to += len; | |
950 | } | |
951 | ||
952 | static void | |
953 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
954 | CORE_ADDR *to, CORE_ADDR oldloc) | |
955 | { | |
956 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
957 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
958 | int offset = 0, rel32, newrel; | |
959 | int insn_length; | |
960 | gdb_byte *insn = buf; | |
961 | ||
962 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
963 | ||
964 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
965 | I386_MAX_INSN_LEN, oldloc); | |
966 | ||
967 | /* Get past the prefixes. */ | |
968 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
969 | ||
970 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
971 | the address pushed being the location where the original call in | |
972 | the user program would return to. */ | |
973 | if (insn[0] == 0xe8) | |
974 | { | |
975 | gdb_byte push_buf[16]; | |
976 | unsigned int ret_addr; | |
977 | ||
978 | /* Where "ret" in the original code will return to. */ | |
979 | ret_addr = oldloc + insn_length; | |
1777feb0 | 980 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 981 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
982 | /* Push the push. */ |
983 | append_insns (to, 5, push_buf); | |
984 | ||
985 | /* Convert the relative call to a relative jump. */ | |
986 | insn[0] = 0xe9; | |
987 | ||
988 | /* Adjust the destination offset. */ | |
989 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
990 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
991 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
992 | ||
993 | if (debug_displaced) | |
994 | fprintf_unfiltered (gdb_stdlog, | |
995 | "Adjusted insn rel32=%s at %s to" | |
996 | " rel32=%s at %s\n", | |
997 | hex_string (rel32), paddress (gdbarch, oldloc), | |
998 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
999 | |
1000 | /* Write the adjusted jump into its displaced location. */ | |
1001 | append_insns (to, 5, insn); | |
1002 | return; | |
1003 | } | |
1004 | ||
1005 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1006 | handled above. */ | |
1007 | if (insn[0] == 0xe9) | |
1008 | offset = 1; | |
1009 | /* Adjust conditional jumps. */ | |
1010 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1011 | offset = 2; | |
1012 | ||
1013 | if (offset) | |
1014 | { | |
1015 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1016 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1017 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1018 | if (debug_displaced) |
1019 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1020 | "Adjusted insn rel32=%s at %s to" |
1021 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1022 | hex_string (rel32), paddress (gdbarch, oldloc), |
1023 | hex_string (newrel), paddress (gdbarch, *to)); | |
1024 | } | |
1025 | ||
1026 | /* Write the adjusted instructions into their displaced | |
1027 | location. */ | |
1028 | append_insns (to, insn_length, buf); | |
1029 | } | |
1030 | ||
fc338970 | 1031 | \f |
acd5c798 MK |
1032 | #ifdef I386_REGNO_TO_SYMMETRY |
1033 | #error "The Sequent Symmetry is no longer supported." | |
1034 | #endif | |
c906108c | 1035 | |
acd5c798 MK |
1036 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1037 | and %esp "belong" to the calling function. Therefore these | |
1038 | registers should be saved if they're going to be modified. */ | |
c906108c | 1039 | |
acd5c798 MK |
1040 | /* The maximum number of saved registers. This should include all |
1041 | registers mentioned above, and %eip. */ | |
a3386186 | 1042 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1043 | |
1044 | struct i386_frame_cache | |
c906108c | 1045 | { |
acd5c798 MK |
1046 | /* Base address. */ |
1047 | CORE_ADDR base; | |
8fbca658 | 1048 | int base_p; |
772562f8 | 1049 | LONGEST sp_offset; |
acd5c798 MK |
1050 | CORE_ADDR pc; |
1051 | ||
fd13a04a AC |
1052 | /* Saved registers. */ |
1053 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1054 | CORE_ADDR saved_sp; |
e0c62198 | 1055 | int saved_sp_reg; |
acd5c798 MK |
1056 | int pc_in_eax; |
1057 | ||
1058 | /* Stack space reserved for local variables. */ | |
1059 | long locals; | |
1060 | }; | |
1061 | ||
1062 | /* Allocate and initialize a frame cache. */ | |
1063 | ||
1064 | static struct i386_frame_cache * | |
fd13a04a | 1065 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1066 | { |
1067 | struct i386_frame_cache *cache; | |
1068 | int i; | |
1069 | ||
1070 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1071 | ||
1072 | /* Base address. */ | |
8fbca658 | 1073 | cache->base_p = 0; |
acd5c798 MK |
1074 | cache->base = 0; |
1075 | cache->sp_offset = -4; | |
1076 | cache->pc = 0; | |
1077 | ||
fd13a04a AC |
1078 | /* Saved registers. We initialize these to -1 since zero is a valid |
1079 | offset (that's where %ebp is supposed to be stored). */ | |
1080 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1081 | cache->saved_regs[i] = -1; | |
acd5c798 | 1082 | cache->saved_sp = 0; |
e0c62198 | 1083 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1084 | cache->pc_in_eax = 0; |
1085 | ||
1086 | /* Frameless until proven otherwise. */ | |
1087 | cache->locals = -1; | |
1088 | ||
1089 | return cache; | |
1090 | } | |
c906108c | 1091 | |
acd5c798 MK |
1092 | /* If the instruction at PC is a jump, return the address of its |
1093 | target. Otherwise, return PC. */ | |
c906108c | 1094 | |
acd5c798 | 1095 | static CORE_ADDR |
e17a4113 | 1096 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1097 | { |
e17a4113 | 1098 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1099 | gdb_byte op; |
acd5c798 MK |
1100 | long delta = 0; |
1101 | int data16 = 0; | |
c906108c | 1102 | |
0865b04a | 1103 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1104 | return pc; |
1105 | ||
acd5c798 | 1106 | if (op == 0x66) |
c906108c | 1107 | { |
c906108c | 1108 | data16 = 1; |
0865b04a YQ |
1109 | |
1110 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1111 | } |
1112 | ||
acd5c798 | 1113 | switch (op) |
c906108c SS |
1114 | { |
1115 | case 0xe9: | |
fc338970 | 1116 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1117 | if (data16) |
1118 | { | |
e17a4113 | 1119 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1120 | |
fc338970 MK |
1121 | /* Include the size of the jmp instruction (including the |
1122 | 0x66 prefix). */ | |
acd5c798 | 1123 | delta += 4; |
c906108c SS |
1124 | } |
1125 | else | |
1126 | { | |
e17a4113 | 1127 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1128 | |
acd5c798 MK |
1129 | /* Include the size of the jmp instruction. */ |
1130 | delta += 5; | |
c906108c SS |
1131 | } |
1132 | break; | |
1133 | case 0xeb: | |
fc338970 | 1134 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1135 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1136 | |
acd5c798 | 1137 | delta += data16 + 2; |
c906108c SS |
1138 | break; |
1139 | } | |
c906108c | 1140 | |
acd5c798 MK |
1141 | return pc + delta; |
1142 | } | |
fc338970 | 1143 | |
acd5c798 MK |
1144 | /* Check whether PC points at a prologue for a function returning a |
1145 | structure or union. If so, it updates CACHE and returns the | |
1146 | address of the first instruction after the code sequence that | |
1147 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1148 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1149 | |
acd5c798 MK |
1150 | static CORE_ADDR |
1151 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1152 | struct i386_frame_cache *cache) | |
c906108c | 1153 | { |
acd5c798 MK |
1154 | /* Functions that return a structure or union start with: |
1155 | ||
1156 | popl %eax 0x58 | |
1157 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1158 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1159 | ||
1160 | (the System V compiler puts out the second `xchg' instruction, | |
1161 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1162 | gets generated). This sequence is used to get the address of the | |
1163 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1164 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1165 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1166 | gdb_byte buf[4]; | |
1167 | gdb_byte op; | |
c906108c | 1168 | |
acd5c798 MK |
1169 | if (current_pc <= pc) |
1170 | return pc; | |
1171 | ||
0865b04a | 1172 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1173 | return pc; |
c906108c | 1174 | |
acd5c798 MK |
1175 | if (op != 0x58) /* popl %eax */ |
1176 | return pc; | |
c906108c | 1177 | |
0865b04a | 1178 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1179 | return pc; |
1180 | ||
acd5c798 MK |
1181 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1182 | return pc; | |
c906108c | 1183 | |
acd5c798 | 1184 | if (current_pc == pc) |
c906108c | 1185 | { |
acd5c798 MK |
1186 | cache->sp_offset += 4; |
1187 | return current_pc; | |
c906108c SS |
1188 | } |
1189 | ||
acd5c798 | 1190 | if (current_pc == pc + 1) |
c906108c | 1191 | { |
acd5c798 MK |
1192 | cache->pc_in_eax = 1; |
1193 | return current_pc; | |
1194 | } | |
1195 | ||
1196 | if (buf[1] == proto1[1]) | |
1197 | return pc + 4; | |
1198 | else | |
1199 | return pc + 5; | |
1200 | } | |
1201 | ||
1202 | static CORE_ADDR | |
1203 | i386_skip_probe (CORE_ADDR pc) | |
1204 | { | |
1205 | /* A function may start with | |
fc338970 | 1206 | |
acd5c798 MK |
1207 | pushl constant |
1208 | call _probe | |
1209 | addl $4, %esp | |
fc338970 | 1210 | |
acd5c798 MK |
1211 | followed by |
1212 | ||
1213 | pushl %ebp | |
fc338970 | 1214 | |
acd5c798 | 1215 | etc. */ |
63c0089f MK |
1216 | gdb_byte buf[8]; |
1217 | gdb_byte op; | |
fc338970 | 1218 | |
0865b04a | 1219 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1220 | return pc; |
acd5c798 MK |
1221 | |
1222 | if (op == 0x68 || op == 0x6a) | |
1223 | { | |
1224 | int delta; | |
c906108c | 1225 | |
acd5c798 MK |
1226 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1227 | four-byte operand, depending on the opcode. */ | |
c906108c | 1228 | if (op == 0x68) |
acd5c798 | 1229 | delta = 5; |
c906108c | 1230 | else |
acd5c798 | 1231 | delta = 2; |
c906108c | 1232 | |
acd5c798 MK |
1233 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1234 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1235 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1236 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1237 | pc += delta + sizeof (buf); |
c906108c SS |
1238 | } |
1239 | ||
acd5c798 MK |
1240 | return pc; |
1241 | } | |
1242 | ||
92dd43fa MK |
1243 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1244 | stack pointer. Check whether PC points to such code, and update | |
1245 | CACHE accordingly. Return the first instruction after the code | |
1246 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1247 | recognize the code, return PC. */ | |
1248 | ||
1249 | static CORE_ADDR | |
1250 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1251 | struct i386_frame_cache *cache) | |
1252 | { | |
e0c62198 L |
1253 | /* There are 2 code sequences to re-align stack before the frame |
1254 | gets set up: | |
1255 | ||
1256 | 1. Use a caller-saved saved register: | |
1257 | ||
1258 | leal 4(%esp), %reg | |
1259 | andl $-XXX, %esp | |
1260 | pushl -4(%reg) | |
1261 | ||
1262 | 2. Use a callee-saved saved register: | |
1263 | ||
1264 | pushl %reg | |
1265 | leal 8(%esp), %reg | |
1266 | andl $-XXX, %esp | |
1267 | pushl -4(%reg) | |
1268 | ||
1269 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1270 | ||
1271 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1272 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1273 | */ | |
1274 | ||
1275 | gdb_byte buf[14]; | |
1276 | int reg; | |
1277 | int offset, offset_and; | |
1278 | static int regnums[8] = { | |
1279 | I386_EAX_REGNUM, /* %eax */ | |
1280 | I386_ECX_REGNUM, /* %ecx */ | |
1281 | I386_EDX_REGNUM, /* %edx */ | |
1282 | I386_EBX_REGNUM, /* %ebx */ | |
1283 | I386_ESP_REGNUM, /* %esp */ | |
1284 | I386_EBP_REGNUM, /* %ebp */ | |
1285 | I386_ESI_REGNUM, /* %esi */ | |
1286 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1287 | }; |
92dd43fa | 1288 | |
0865b04a | 1289 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1290 | return pc; |
1291 | ||
1292 | /* Check caller-saved saved register. The first instruction has | |
1293 | to be "leal 4(%esp), %reg". */ | |
1294 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1295 | { | |
1296 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1297 | if ((buf[1] & 0xc7) != 0x44) | |
1298 | return pc; | |
1299 | ||
1300 | /* REG has register number. */ | |
1301 | reg = (buf[1] >> 3) & 7; | |
1302 | offset = 4; | |
1303 | } | |
1304 | else | |
1305 | { | |
1306 | /* Check callee-saved saved register. The first instruction | |
1307 | has to be "pushl %reg". */ | |
1308 | if ((buf[0] & 0xf8) != 0x50) | |
1309 | return pc; | |
1310 | ||
1311 | /* Get register. */ | |
1312 | reg = buf[0] & 0x7; | |
1313 | ||
1314 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1315 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1316 | return pc; | |
1317 | ||
1318 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1319 | if ((buf[2] & 0xc7) != 0x44) | |
1320 | return pc; | |
1321 | ||
1322 | /* REG has register number. Registers in pushl and leal have to | |
1323 | be the same. */ | |
1324 | if (reg != ((buf[2] >> 3) & 7)) | |
1325 | return pc; | |
1326 | ||
1327 | offset = 5; | |
1328 | } | |
1329 | ||
1330 | /* Rigister can't be %esp nor %ebp. */ | |
1331 | if (reg == 4 || reg == 5) | |
1332 | return pc; | |
1333 | ||
1334 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1335 | if (buf[offset + 1] != 0xe4 | |
1336 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1337 | return pc; | |
1338 | ||
1339 | offset_and = offset; | |
1340 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1341 | ||
1342 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1343 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1344 | if (buf[offset] != 0xff | |
1345 | || buf[offset + 2] != 0xfc | |
1346 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1347 | return pc; | |
1348 | ||
1349 | /* R/M has register. Registers in leal and pushl have to be the | |
1350 | same. */ | |
1351 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1352 | return pc; |
1353 | ||
e0c62198 L |
1354 | if (current_pc > pc + offset_and) |
1355 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1356 | |
e0c62198 | 1357 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1358 | } |
1359 | ||
37bdc87e | 1360 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1361 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1362 | |
1363 | /* Instruction description. */ | |
1364 | struct i386_insn | |
1365 | { | |
1366 | size_t len; | |
237fc4c9 PA |
1367 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1368 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1369 | }; |
1370 | ||
a3fcb948 | 1371 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1372 | |
a3fcb948 JG |
1373 | static int |
1374 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1375 | { |
63c0089f | 1376 | gdb_byte op; |
37bdc87e | 1377 | |
0865b04a | 1378 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1379 | return 0; |
37bdc87e | 1380 | |
a3fcb948 | 1381 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1382 | { |
a3fcb948 JG |
1383 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1384 | int insn_matched = 1; | |
1385 | size_t i; | |
37bdc87e | 1386 | |
a3fcb948 JG |
1387 | gdb_assert (pattern.len > 1); |
1388 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1389 | |
0865b04a | 1390 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1391 | return 0; |
613e8135 | 1392 | |
a3fcb948 JG |
1393 | for (i = 1; i < pattern.len; i++) |
1394 | { | |
1395 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1396 | insn_matched = 0; | |
37bdc87e | 1397 | } |
a3fcb948 JG |
1398 | return insn_matched; |
1399 | } | |
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1404 | the first instruction description that matches. Otherwise, return | |
1405 | NULL. */ | |
1406 | ||
1407 | static struct i386_insn * | |
1408 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1409 | { | |
1410 | struct i386_insn *pattern; | |
1411 | ||
1412 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1413 | { | |
1414 | if (i386_match_pattern (pc, *pattern)) | |
1415 | return pattern; | |
37bdc87e MK |
1416 | } |
1417 | ||
1418 | return NULL; | |
1419 | } | |
1420 | ||
a3fcb948 JG |
1421 | /* Return whether PC points inside a sequence of instructions that |
1422 | matches INSN_PATTERNS. */ | |
1423 | ||
1424 | static int | |
1425 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1426 | { | |
1427 | CORE_ADDR current_pc; | |
1428 | int ix, i; | |
a3fcb948 JG |
1429 | struct i386_insn *insn; |
1430 | ||
1431 | insn = i386_match_insn (pc, insn_patterns); | |
1432 | if (insn == NULL) | |
1433 | return 0; | |
1434 | ||
8bbdd3f4 | 1435 | current_pc = pc; |
a3fcb948 JG |
1436 | ix = insn - insn_patterns; |
1437 | for (i = ix - 1; i >= 0; i--) | |
1438 | { | |
8bbdd3f4 MK |
1439 | current_pc -= insn_patterns[i].len; |
1440 | ||
a3fcb948 JG |
1441 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1442 | return 0; | |
a3fcb948 JG |
1443 | } |
1444 | ||
1445 | current_pc = pc + insn->len; | |
1446 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1447 | { | |
1448 | if (!i386_match_pattern (current_pc, *insn)) | |
1449 | return 0; | |
1450 | ||
1451 | current_pc += insn->len; | |
1452 | } | |
1453 | ||
1454 | return 1; | |
1455 | } | |
1456 | ||
37bdc87e MK |
1457 | /* Some special instructions that might be migrated by GCC into the |
1458 | part of the prologue that sets up the new stack frame. Because the | |
1459 | stack frame hasn't been setup yet, no registers have been saved | |
1460 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1461 | touched. */ | |
1462 | ||
1463 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1464 | { | |
1777feb0 | 1465 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1466 | |
1467 | ??? Should we handle 16-bit operand-sizes here? */ | |
1468 | ||
1469 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1470 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1471 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1472 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1473 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1474 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1475 | { 5, { 0xb8 }, { 0xfe } }, | |
1476 | /* `movl imm32, %edx' */ | |
1477 | { 5, { 0xba }, { 0xff } }, | |
1478 | ||
1479 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1480 | encoding for `mov m32, %eax'. | |
1481 | ||
1482 | ??? Should we handle SIB adressing here? | |
1483 | ??? Should we handle 16-bit operand-sizes here? */ | |
1484 | ||
1485 | /* `movl m32, %eax' */ | |
1486 | { 5, { 0xa1 }, { 0xff } }, | |
1487 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1488 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1489 | /* `movl m32, %edx' */ | |
1490 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1491 | ||
1492 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1493 | Because of the symmetry, there are actually two ways to encode | |
1494 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1495 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1496 | ||
1497 | /* `subl %eax, %eax' */ | |
1498 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1499 | /* `subl %ecx, %ecx' */ | |
1500 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1501 | /* `subl %edx, %edx' */ | |
1502 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1503 | /* `xorl %eax, %eax' */ | |
1504 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1505 | /* `xorl %ecx, %ecx' */ | |
1506 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1507 | /* `xorl %edx, %edx' */ | |
1508 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1509 | { 0 } | |
1510 | }; | |
1511 | ||
e11481da PM |
1512 | |
1513 | /* Check whether PC points to a no-op instruction. */ | |
1514 | static CORE_ADDR | |
1515 | i386_skip_noop (CORE_ADDR pc) | |
1516 | { | |
1517 | gdb_byte op; | |
1518 | int check = 1; | |
1519 | ||
0865b04a | 1520 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1521 | return pc; |
e11481da PM |
1522 | |
1523 | while (check) | |
1524 | { | |
1525 | check = 0; | |
1526 | /* Ignore `nop' instruction. */ | |
1527 | if (op == 0x90) | |
1528 | { | |
1529 | pc += 1; | |
0865b04a | 1530 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1531 | return pc; |
e11481da PM |
1532 | check = 1; |
1533 | } | |
1534 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1535 | Microsoft system dlls often start with | |
1536 | a `mov %edi,%edi' instruction. | |
1537 | The 5 bytes before the function start are | |
1538 | filled with `nop' instructions. | |
1539 | This pattern can be used for hot-patching: | |
1540 | The `mov %edi, %edi' instruction can be replaced by a | |
1541 | near jump to the location of the 5 `nop' instructions | |
1542 | which can be replaced by a 32-bit jump to anywhere | |
1543 | in the 32-bit address space. */ | |
1544 | ||
1545 | else if (op == 0x8b) | |
1546 | { | |
0865b04a | 1547 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1548 | return pc; |
1549 | ||
e11481da PM |
1550 | if (op == 0xff) |
1551 | { | |
1552 | pc += 2; | |
0865b04a | 1553 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1554 | return pc; |
1555 | ||
e11481da PM |
1556 | check = 1; |
1557 | } | |
1558 | } | |
1559 | } | |
1560 | return pc; | |
1561 | } | |
1562 | ||
acd5c798 MK |
1563 | /* Check whether PC points at a code that sets up a new stack frame. |
1564 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1565 | instruction after the sequence that sets up the frame or LIMIT, |
1566 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1567 | |
1568 | static CORE_ADDR | |
e17a4113 UW |
1569 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1570 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1571 | struct i386_frame_cache *cache) |
1572 | { | |
e17a4113 | 1573 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1574 | struct i386_insn *insn; |
63c0089f | 1575 | gdb_byte op; |
26604a34 | 1576 | int skip = 0; |
acd5c798 | 1577 | |
37bdc87e MK |
1578 | if (limit <= pc) |
1579 | return limit; | |
acd5c798 | 1580 | |
0865b04a | 1581 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1582 | return pc; |
acd5c798 | 1583 | |
c906108c | 1584 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1585 | { |
acd5c798 MK |
1586 | /* Take into account that we've executed the `pushl %ebp' that |
1587 | starts this instruction sequence. */ | |
fd13a04a | 1588 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1589 | cache->sp_offset += 4; |
37bdc87e | 1590 | pc++; |
acd5c798 MK |
1591 | |
1592 | /* If that's all, return now. */ | |
37bdc87e MK |
1593 | if (limit <= pc) |
1594 | return limit; | |
26604a34 | 1595 | |
b4632131 | 1596 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1597 | GCC into the prologue and skip them. At this point in the |
1598 | prologue, code should only touch the scratch registers %eax, | |
1599 | %ecx and %edx, so while the number of posibilities is sheer, | |
1600 | it is limited. | |
5daa5b4e | 1601 | |
26604a34 MK |
1602 | Make sure we only skip these instructions if we later see the |
1603 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1604 | while (pc + skip < limit) |
26604a34 | 1605 | { |
37bdc87e MK |
1606 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1607 | if (insn == NULL) | |
1608 | break; | |
b4632131 | 1609 | |
37bdc87e | 1610 | skip += insn->len; |
26604a34 MK |
1611 | } |
1612 | ||
37bdc87e MK |
1613 | /* If that's all, return now. */ |
1614 | if (limit <= pc + skip) | |
1615 | return limit; | |
1616 | ||
0865b04a | 1617 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1618 | return pc + skip; |
37bdc87e | 1619 | |
30f8135b YQ |
1620 | /* The i386 prologue looks like |
1621 | ||
1622 | push %ebp | |
1623 | mov %esp,%ebp | |
1624 | sub $0x10,%esp | |
1625 | ||
1626 | and a different prologue can be generated for atom. | |
1627 | ||
1628 | push %ebp | |
1629 | lea (%esp),%ebp | |
1630 | lea -0x10(%esp),%esp | |
1631 | ||
1632 | We handle both of them here. */ | |
1633 | ||
acd5c798 | 1634 | switch (op) |
c906108c | 1635 | { |
30f8135b | 1636 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1637 | case 0x8b: |
0865b04a | 1638 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1639 | != 0xec) |
37bdc87e | 1640 | return pc; |
30f8135b | 1641 | pc += (skip + 2); |
c906108c SS |
1642 | break; |
1643 | case 0x89: | |
0865b04a | 1644 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1645 | != 0xe5) |
37bdc87e | 1646 | return pc; |
30f8135b YQ |
1647 | pc += (skip + 2); |
1648 | break; | |
1649 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1650 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1651 | != 0x242c) |
1652 | return pc; | |
1653 | pc += (skip + 3); | |
c906108c SS |
1654 | break; |
1655 | default: | |
37bdc87e | 1656 | return pc; |
c906108c | 1657 | } |
acd5c798 | 1658 | |
26604a34 MK |
1659 | /* OK, we actually have a frame. We just don't know how large |
1660 | it is yet. Set its size to zero. We'll adjust it if | |
1661 | necessary. We also now commit to skipping the special | |
1662 | instructions mentioned before. */ | |
acd5c798 MK |
1663 | cache->locals = 0; |
1664 | ||
1665 | /* If that's all, return now. */ | |
37bdc87e MK |
1666 | if (limit <= pc) |
1667 | return limit; | |
acd5c798 | 1668 | |
fc338970 MK |
1669 | /* Check for stack adjustment |
1670 | ||
acd5c798 | 1671 | subl $XXX, %esp |
30f8135b YQ |
1672 | or |
1673 | lea -XXX(%esp),%esp | |
fc338970 | 1674 | |
fd35795f | 1675 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1676 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1677 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1678 | return pc; |
c906108c SS |
1679 | if (op == 0x83) |
1680 | { | |
fd35795f | 1681 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1682 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1683 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1684 | return pc; |
acd5c798 | 1685 | |
37bdc87e MK |
1686 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1687 | make sense to be negative). */ | |
0865b04a | 1688 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1689 | return pc + 3; |
c906108c SS |
1690 | } |
1691 | else if (op == 0x81) | |
1692 | { | |
fd35795f | 1693 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1694 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1695 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1696 | return pc; |
acd5c798 | 1697 | |
fd35795f | 1698 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1699 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1700 | return pc + 6; |
c906108c | 1701 | } |
30f8135b YQ |
1702 | else if (op == 0x8d) |
1703 | { | |
1704 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1705 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1706 | return pc; |
1707 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1708 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1709 | return pc + 4; |
1710 | } | |
c906108c SS |
1711 | else |
1712 | { | |
30f8135b | 1713 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1714 | return pc; |
c906108c SS |
1715 | } |
1716 | } | |
37bdc87e | 1717 | else if (op == 0xc8) /* enter */ |
c906108c | 1718 | { |
0865b04a | 1719 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1720 | return pc + 4; |
c906108c | 1721 | } |
21d0e8a4 | 1722 | |
acd5c798 | 1723 | return pc; |
21d0e8a4 MK |
1724 | } |
1725 | ||
acd5c798 MK |
1726 | /* Check whether PC points at code that saves registers on the stack. |
1727 | If so, it updates CACHE and returns the address of the first | |
1728 | instruction after the register saves or CURRENT_PC, whichever is | |
1729 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1730 | |
1731 | static CORE_ADDR | |
acd5c798 MK |
1732 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1733 | struct i386_frame_cache *cache) | |
6bff26de | 1734 | { |
99ab4326 | 1735 | CORE_ADDR offset = 0; |
63c0089f | 1736 | gdb_byte op; |
99ab4326 | 1737 | int i; |
c0d1d883 | 1738 | |
99ab4326 MK |
1739 | if (cache->locals > 0) |
1740 | offset -= cache->locals; | |
1741 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1742 | { | |
0865b04a | 1743 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1744 | return pc; |
99ab4326 MK |
1745 | if (op < 0x50 || op > 0x57) |
1746 | break; | |
0d17c81d | 1747 | |
99ab4326 MK |
1748 | offset -= 4; |
1749 | cache->saved_regs[op - 0x50] = offset; | |
1750 | cache->sp_offset += 4; | |
1751 | pc++; | |
6bff26de MK |
1752 | } |
1753 | ||
acd5c798 | 1754 | return pc; |
22797942 AC |
1755 | } |
1756 | ||
acd5c798 MK |
1757 | /* Do a full analysis of the prologue at PC and update CACHE |
1758 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1759 | address where the analysis stopped. | |
ed84f6c1 | 1760 | |
fc338970 MK |
1761 | We handle these cases: |
1762 | ||
1763 | The startup sequence can be at the start of the function, or the | |
1764 | function can start with a branch to startup code at the end. | |
1765 | ||
1766 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1767 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1768 | once used in the System V compiler). | |
1769 | ||
1770 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1771 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1772 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1773 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1774 | |
1775 | Next, the registers used by this function are pushed. With the | |
1776 | System V compiler they will always be in the order: %edi, %esi, | |
1777 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1778 | restore %eax); however, the code below is willing to see the pushes | |
1779 | in any order, and will handle up to 8 of them. | |
1780 | ||
1781 | If the setup sequence is at the end of the function, then the next | |
1782 | instruction will be a branch back to the start. */ | |
c906108c | 1783 | |
acd5c798 | 1784 | static CORE_ADDR |
e17a4113 UW |
1785 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1786 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1787 | struct i386_frame_cache *cache) |
c906108c | 1788 | { |
e11481da | 1789 | pc = i386_skip_noop (pc); |
e17a4113 | 1790 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1791 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1792 | pc = i386_skip_probe (pc); | |
92dd43fa | 1793 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1794 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1795 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1796 | } |
1797 | ||
fc338970 | 1798 | /* Return PC of first real instruction. */ |
c906108c | 1799 | |
3a1e71e3 | 1800 | static CORE_ADDR |
6093d2eb | 1801 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1802 | { |
e17a4113 UW |
1803 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1804 | ||
63c0089f | 1805 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1806 | { |
1807 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1808 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1809 | }; |
acd5c798 MK |
1810 | struct i386_frame_cache cache; |
1811 | CORE_ADDR pc; | |
63c0089f | 1812 | gdb_byte op; |
acd5c798 | 1813 | int i; |
56bf0743 | 1814 | CORE_ADDR func_addr; |
4e879fc2 | 1815 | |
56bf0743 KB |
1816 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1817 | { | |
1818 | CORE_ADDR post_prologue_pc | |
1819 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1820 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
1821 | |
1822 | /* Clang always emits a line note before the prologue and another | |
1823 | one after. We trust clang to emit usable line notes. */ | |
1824 | if (post_prologue_pc | |
43f3e411 DE |
1825 | && (cust != NULL |
1826 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 1827 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
56bf0743 KB |
1828 | return max (start_pc, post_prologue_pc); |
1829 | } | |
1830 | ||
e0f33b1f | 1831 | cache.locals = -1; |
e17a4113 | 1832 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1833 | if (cache.locals < 0) |
1834 | return start_pc; | |
c5aa993b | 1835 | |
acd5c798 | 1836 | /* Found valid frame setup. */ |
c906108c | 1837 | |
fc338970 MK |
1838 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1839 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1840 | %ebx: |
1841 | ||
fc338970 MK |
1842 | call 0x0 |
1843 | popl %ebx | |
1844 | movl %ebx,x(%ebp) (optional) | |
1845 | addl y,%ebx | |
1846 | ||
c906108c SS |
1847 | This code is with the rest of the prologue (at the end of the |
1848 | function), so we have to skip it to get to the first real | |
1849 | instruction at the start of the function. */ | |
c5aa993b | 1850 | |
c906108c SS |
1851 | for (i = 0; i < 6; i++) |
1852 | { | |
0865b04a | 1853 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1854 | return pc; |
1855 | ||
c5aa993b | 1856 | if (pic_pat[i] != op) |
c906108c SS |
1857 | break; |
1858 | } | |
1859 | if (i == 6) | |
1860 | { | |
acd5c798 MK |
1861 | int delta = 6; |
1862 | ||
0865b04a | 1863 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1864 | return pc; |
c906108c | 1865 | |
c5aa993b | 1866 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1867 | { |
0865b04a | 1868 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1869 | |
fc338970 | 1870 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1871 | delta += 3; |
fc338970 | 1872 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1873 | delta += 6; |
fc338970 | 1874 | else /* Unexpected instruction. */ |
acd5c798 MK |
1875 | delta = 0; |
1876 | ||
0865b04a | 1877 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1878 | return pc; |
c906108c | 1879 | } |
acd5c798 | 1880 | |
c5aa993b | 1881 | /* addl y,%ebx */ |
acd5c798 | 1882 | if (delta > 0 && op == 0x81 |
0865b04a | 1883 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1884 | == 0xc3) |
c906108c | 1885 | { |
acd5c798 | 1886 | pc += delta + 6; |
c906108c SS |
1887 | } |
1888 | } | |
c5aa993b | 1889 | |
e63bbc88 MK |
1890 | /* If the function starts with a branch (to startup code at the end) |
1891 | the last instruction should bring us back to the first | |
1892 | instruction of the real code. */ | |
e17a4113 UW |
1893 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1894 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1895 | |
1896 | return pc; | |
c906108c SS |
1897 | } |
1898 | ||
4309257c PM |
1899 | /* Check that the code pointed to by PC corresponds to a call to |
1900 | __main, skip it if so. Return PC otherwise. */ | |
1901 | ||
1902 | CORE_ADDR | |
1903 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1904 | { | |
e17a4113 | 1905 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1906 | gdb_byte op; |
1907 | ||
0865b04a | 1908 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1909 | return pc; |
4309257c PM |
1910 | if (op == 0xe8) |
1911 | { | |
1912 | gdb_byte buf[4]; | |
1913 | ||
0865b04a | 1914 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1915 | { |
1916 | /* Make sure address is computed correctly as a 32bit | |
1917 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1918 | struct bound_minimal_symbol s; |
e17a4113 | 1919 | CORE_ADDR call_dest; |
4309257c | 1920 | |
e17a4113 | 1921 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1922 | call_dest = call_dest & 0xffffffffU; |
1923 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1924 | if (s.minsym != NULL |
efd66ac6 TT |
1925 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1926 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1927 | pc += 5; |
1928 | } | |
1929 | } | |
1930 | ||
1931 | return pc; | |
1932 | } | |
1933 | ||
acd5c798 | 1934 | /* This function is 64-bit safe. */ |
93924b6b | 1935 | |
acd5c798 MK |
1936 | static CORE_ADDR |
1937 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1938 | { |
63c0089f | 1939 | gdb_byte buf[8]; |
acd5c798 | 1940 | |
875f8d0e | 1941 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1942 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1943 | } |
acd5c798 | 1944 | \f |
93924b6b | 1945 | |
acd5c798 | 1946 | /* Normal frames. */ |
c5aa993b | 1947 | |
8fbca658 PA |
1948 | static void |
1949 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1950 | struct i386_frame_cache *cache) | |
a7769679 | 1951 | { |
e17a4113 UW |
1952 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1953 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1954 | gdb_byte buf[4]; |
acd5c798 MK |
1955 | int i; |
1956 | ||
8fbca658 | 1957 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1958 | |
1959 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1960 | which holds the base address for the current stack frame. | |
1961 | However, for functions that don't need it, the frame pointer is | |
1962 | optional. For these "frameless" functions the frame pointer is | |
1963 | actually the frame pointer of the calling frame. Signal | |
1964 | trampolines are just a special case of a "frameless" function. | |
1965 | They (usually) share their frame pointer with the frame that was | |
1966 | in progress when the signal occurred. */ | |
1967 | ||
10458914 | 1968 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1969 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1970 | if (cache->base == 0) |
620fa63a PA |
1971 | { |
1972 | cache->base_p = 1; | |
1973 | return; | |
1974 | } | |
acd5c798 MK |
1975 | |
1976 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1977 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1978 | |
acd5c798 | 1979 | if (cache->pc != 0) |
e17a4113 UW |
1980 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1981 | cache); | |
acd5c798 MK |
1982 | |
1983 | if (cache->locals < 0) | |
1984 | { | |
1985 | /* We didn't find a valid frame, which means that CACHE->base | |
1986 | currently holds the frame pointer for our calling frame. If | |
1987 | we're at the start of a function, or somewhere half-way its | |
1988 | prologue, the function's frame probably hasn't been fully | |
1989 | setup yet. Try to reconstruct the base address for the stack | |
1990 | frame by looking at the stack pointer. For truly "frameless" | |
1991 | functions this might work too. */ | |
1992 | ||
e0c62198 | 1993 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1994 | { |
8fbca658 PA |
1995 | /* Saved stack pointer has been saved. */ |
1996 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1997 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1998 | ||
92dd43fa MK |
1999 | /* We're halfway aligning the stack. */ |
2000 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2001 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2002 | ||
2003 | /* This will be added back below. */ | |
2004 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2005 | } | |
7618e12b | 2006 | else if (cache->pc != 0 |
0865b04a | 2007 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2008 | { |
7618e12b DJ |
2009 | /* We're in a known function, but did not find a frame |
2010 | setup. Assume that the function does not use %ebp. | |
2011 | Alternatively, we may have jumped to an invalid | |
2012 | address; in that case there is definitely no new | |
2013 | frame in %ebp. */ | |
10458914 | 2014 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2015 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2016 | + cache->sp_offset; | |
92dd43fa | 2017 | } |
7618e12b DJ |
2018 | else |
2019 | /* We're in an unknown function. We could not find the start | |
2020 | of the function to analyze the prologue; our best option is | |
2021 | to assume a typical frame layout with the caller's %ebp | |
2022 | saved. */ | |
2023 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2024 | } |
2025 | ||
8fbca658 PA |
2026 | if (cache->saved_sp_reg != -1) |
2027 | { | |
2028 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2029 | register may be unavailable). */ | |
2030 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2031 | && deprecated_frame_register_read (this_frame, |
2032 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2033 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2034 | } | |
acd5c798 MK |
2035 | /* Now that we have the base address for the stack frame we can |
2036 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2037 | else if (cache->saved_sp == 0) |
92dd43fa | 2038 | cache->saved_sp = cache->base + 8; |
a7769679 | 2039 | |
acd5c798 MK |
2040 | /* Adjust all the saved registers such that they contain addresses |
2041 | instead of offsets. */ | |
2042 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2043 | if (cache->saved_regs[i] != -1) |
2044 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2045 | |
8fbca658 PA |
2046 | cache->base_p = 1; |
2047 | } | |
2048 | ||
2049 | static struct i386_frame_cache * | |
2050 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2051 | { | |
8fbca658 PA |
2052 | struct i386_frame_cache *cache; |
2053 | ||
2054 | if (*this_cache) | |
2055 | return *this_cache; | |
2056 | ||
2057 | cache = i386_alloc_frame_cache (); | |
2058 | *this_cache = cache; | |
2059 | ||
492d29ea | 2060 | TRY |
8fbca658 PA |
2061 | { |
2062 | i386_frame_cache_1 (this_frame, cache); | |
2063 | } | |
492d29ea | 2064 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2065 | { |
2066 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2067 | throw_exception (ex); | |
2068 | } | |
492d29ea | 2069 | END_CATCH |
8fbca658 | 2070 | |
acd5c798 | 2071 | return cache; |
a7769679 MK |
2072 | } |
2073 | ||
3a1e71e3 | 2074 | static void |
10458914 | 2075 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2076 | struct frame_id *this_id) |
c906108c | 2077 | { |
10458914 | 2078 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2079 | |
5ce0145d PA |
2080 | if (!cache->base_p) |
2081 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2082 | else if (cache->base == 0) | |
2083 | { | |
2084 | /* This marks the outermost frame. */ | |
2085 | } | |
2086 | else | |
2087 | { | |
2088 | /* See the end of i386_push_dummy_call. */ | |
2089 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2090 | } | |
acd5c798 MK |
2091 | } |
2092 | ||
8fbca658 PA |
2093 | static enum unwind_stop_reason |
2094 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2095 | void **this_cache) | |
2096 | { | |
2097 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2098 | ||
2099 | if (!cache->base_p) | |
2100 | return UNWIND_UNAVAILABLE; | |
2101 | ||
2102 | /* This marks the outermost frame. */ | |
2103 | if (cache->base == 0) | |
2104 | return UNWIND_OUTERMOST; | |
2105 | ||
2106 | return UNWIND_NO_REASON; | |
2107 | } | |
2108 | ||
10458914 DJ |
2109 | static struct value * |
2110 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2111 | int regnum) | |
acd5c798 | 2112 | { |
10458914 | 2113 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2114 | |
2115 | gdb_assert (regnum >= 0); | |
2116 | ||
2117 | /* The System V ABI says that: | |
2118 | ||
2119 | "The flags register contains the system flags, such as the | |
2120 | direction flag and the carry flag. The direction flag must be | |
2121 | set to the forward (that is, zero) direction before entry and | |
2122 | upon exit from a function. Other user flags have no specified | |
2123 | role in the standard calling sequence and are not preserved." | |
2124 | ||
2125 | To guarantee the "upon exit" part of that statement we fake a | |
2126 | saved flags register that has its direction flag cleared. | |
2127 | ||
2128 | Note that GCC doesn't seem to rely on the fact that the direction | |
2129 | flag is cleared after a function return; it always explicitly | |
2130 | clears the flag before operations where it matters. | |
2131 | ||
2132 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2133 | right thing to do. The way we fake the flags register here makes | |
2134 | it impossible to change it. */ | |
2135 | ||
2136 | if (regnum == I386_EFLAGS_REGNUM) | |
2137 | { | |
10458914 | 2138 | ULONGEST val; |
c5aa993b | 2139 | |
10458914 DJ |
2140 | val = get_frame_register_unsigned (this_frame, regnum); |
2141 | val &= ~(1 << 10); | |
2142 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2143 | } |
1211c4e4 | 2144 | |
acd5c798 | 2145 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2146 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2147 | |
fcf250e2 UW |
2148 | if (regnum == I386_ESP_REGNUM |
2149 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2150 | { |
2151 | /* If the SP has been saved, but we don't know where, then this | |
2152 | means that SAVED_SP_REG register was found unavailable back | |
2153 | when we built the cache. */ | |
fcf250e2 | 2154 | if (cache->saved_sp == 0) |
8fbca658 PA |
2155 | return frame_unwind_got_register (this_frame, regnum, |
2156 | cache->saved_sp_reg); | |
2157 | else | |
2158 | return frame_unwind_got_constant (this_frame, regnum, | |
2159 | cache->saved_sp); | |
2160 | } | |
acd5c798 | 2161 | |
fd13a04a | 2162 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2163 | return frame_unwind_got_memory (this_frame, regnum, |
2164 | cache->saved_regs[regnum]); | |
fd13a04a | 2165 | |
10458914 | 2166 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2167 | } |
2168 | ||
2169 | static const struct frame_unwind i386_frame_unwind = | |
2170 | { | |
2171 | NORMAL_FRAME, | |
8fbca658 | 2172 | i386_frame_unwind_stop_reason, |
acd5c798 | 2173 | i386_frame_this_id, |
10458914 DJ |
2174 | i386_frame_prev_register, |
2175 | NULL, | |
2176 | default_frame_sniffer | |
acd5c798 | 2177 | }; |
06da04c6 MS |
2178 | |
2179 | /* Normal frames, but in a function epilogue. */ | |
2180 | ||
c9cf6e20 MG |
2181 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2182 | ||
2183 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2184 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2185 | the function's stack frame. */ | |
2186 | ||
2187 | static int | |
c9cf6e20 | 2188 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2189 | { |
2190 | gdb_byte insn; | |
43f3e411 | 2191 | struct compunit_symtab *cust; |
e0d00bc7 | 2192 | |
43f3e411 DE |
2193 | cust = find_pc_compunit_symtab (pc); |
2194 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2195 | return 0; |
06da04c6 MS |
2196 | |
2197 | if (target_read_memory (pc, &insn, 1)) | |
2198 | return 0; /* Can't read memory at pc. */ | |
2199 | ||
2200 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2201 | return 0; | |
2202 | ||
2203 | return 1; | |
2204 | } | |
2205 | ||
2206 | static int | |
2207 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2208 | struct frame_info *this_frame, | |
2209 | void **this_prologue_cache) | |
2210 | { | |
2211 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2212 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2213 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2214 | else |
2215 | return 0; | |
2216 | } | |
2217 | ||
2218 | static struct i386_frame_cache * | |
2219 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2220 | { | |
06da04c6 | 2221 | struct i386_frame_cache *cache; |
0d6c2135 | 2222 | CORE_ADDR sp; |
06da04c6 MS |
2223 | |
2224 | if (*this_cache) | |
2225 | return *this_cache; | |
2226 | ||
2227 | cache = i386_alloc_frame_cache (); | |
2228 | *this_cache = cache; | |
2229 | ||
492d29ea | 2230 | TRY |
8fbca658 | 2231 | { |
0d6c2135 | 2232 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2233 | |
0d6c2135 MK |
2234 | /* At this point the stack looks as if we just entered the |
2235 | function, with the return address at the top of the | |
2236 | stack. */ | |
2237 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2238 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2239 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2240 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2241 | |
8fbca658 PA |
2242 | cache->base_p = 1; |
2243 | } | |
492d29ea | 2244 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2245 | { |
2246 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2247 | throw_exception (ex); | |
2248 | } | |
492d29ea | 2249 | END_CATCH |
06da04c6 MS |
2250 | |
2251 | return cache; | |
2252 | } | |
2253 | ||
8fbca658 PA |
2254 | static enum unwind_stop_reason |
2255 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2256 | void **this_cache) | |
2257 | { | |
0d6c2135 MK |
2258 | struct i386_frame_cache *cache = |
2259 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2260 | |
2261 | if (!cache->base_p) | |
2262 | return UNWIND_UNAVAILABLE; | |
2263 | ||
2264 | return UNWIND_NO_REASON; | |
2265 | } | |
2266 | ||
06da04c6 MS |
2267 | static void |
2268 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2269 | void **this_cache, | |
2270 | struct frame_id *this_id) | |
2271 | { | |
0d6c2135 MK |
2272 | struct i386_frame_cache *cache = |
2273 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2274 | |
8fbca658 | 2275 | if (!cache->base_p) |
5ce0145d PA |
2276 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2277 | else | |
2278 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2279 | } |
2280 | ||
0d6c2135 MK |
2281 | static struct value * |
2282 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2283 | void **this_cache, int regnum) | |
2284 | { | |
2285 | /* Make sure we've initialized the cache. */ | |
2286 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2287 | ||
2288 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2289 | } | |
2290 | ||
06da04c6 MS |
2291 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2292 | { | |
2293 | NORMAL_FRAME, | |
8fbca658 | 2294 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2295 | i386_epilogue_frame_this_id, |
0d6c2135 | 2296 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2297 | NULL, |
2298 | i386_epilogue_frame_sniffer | |
2299 | }; | |
acd5c798 MK |
2300 | \f |
2301 | ||
a3fcb948 JG |
2302 | /* Stack-based trampolines. */ |
2303 | ||
2304 | /* These trampolines are used on cross x86 targets, when taking the | |
2305 | address of a nested function. When executing these trampolines, | |
2306 | no stack frame is set up, so we are in a similar situation as in | |
2307 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2308 | ||
2309 | /* Static chain passed in register. */ | |
2310 | ||
2311 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2312 | { | |
2313 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2314 | { 5, { 0xb8 }, { 0xfe } }, | |
2315 | ||
2316 | /* `jmp imm32' */ | |
2317 | { 5, { 0xe9 }, { 0xff } }, | |
2318 | ||
2319 | {0} | |
2320 | }; | |
2321 | ||
2322 | /* Static chain passed on stack (when regparm=3). */ | |
2323 | ||
2324 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2325 | { | |
2326 | /* `push imm32' */ | |
2327 | { 5, { 0x68 }, { 0xff } }, | |
2328 | ||
2329 | /* `jmp imm32' */ | |
2330 | { 5, { 0xe9 }, { 0xff } }, | |
2331 | ||
2332 | {0} | |
2333 | }; | |
2334 | ||
2335 | /* Return whether PC points inside a stack trampoline. */ | |
2336 | ||
2337 | static int | |
6df81a63 | 2338 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2339 | { |
2340 | gdb_byte insn; | |
2c02bd72 | 2341 | const char *name; |
a3fcb948 JG |
2342 | |
2343 | /* A stack trampoline is detected if no name is associated | |
2344 | to the current pc and if it points inside a trampoline | |
2345 | sequence. */ | |
2346 | ||
2347 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2348 | if (name) | |
2349 | return 0; | |
2350 | ||
2351 | if (target_read_memory (pc, &insn, 1)) | |
2352 | return 0; | |
2353 | ||
2354 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2355 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2356 | return 0; | |
2357 | ||
2358 | return 1; | |
2359 | } | |
2360 | ||
2361 | static int | |
2362 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2363 | struct frame_info *this_frame, |
2364 | void **this_cache) | |
a3fcb948 JG |
2365 | { |
2366 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2367 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2368 | else |
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2373 | { | |
2374 | NORMAL_FRAME, | |
2375 | i386_epilogue_frame_unwind_stop_reason, | |
2376 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2377 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2378 | NULL, |
2379 | i386_stack_tramp_frame_sniffer | |
2380 | }; | |
2381 | \f | |
6710bf39 SS |
2382 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2383 | ||
2384 | static void | |
2385 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2386 | struct agent_expr *ax, struct axs_value *value, | |
2387 | CORE_ADDR scope) | |
2388 | { | |
2389 | /* The following sequence assumes the traditional use of the base | |
2390 | register. */ | |
2391 | ax_reg (ax, I386_EBP_REGNUM); | |
2392 | ax_const_l (ax, 4); | |
2393 | ax_simple (ax, aop_add); | |
2394 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2395 | value->kind = axs_lvalue_memory; | |
2396 | } | |
2397 | \f | |
a3fcb948 | 2398 | |
acd5c798 MK |
2399 | /* Signal trampolines. */ |
2400 | ||
2401 | static struct i386_frame_cache * | |
10458914 | 2402 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2403 | { |
e17a4113 UW |
2404 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2405 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2406 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2407 | struct i386_frame_cache *cache; |
acd5c798 | 2408 | CORE_ADDR addr; |
63c0089f | 2409 | gdb_byte buf[4]; |
acd5c798 MK |
2410 | |
2411 | if (*this_cache) | |
2412 | return *this_cache; | |
2413 | ||
fd13a04a | 2414 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2415 | |
492d29ea | 2416 | TRY |
a3386186 | 2417 | { |
8fbca658 PA |
2418 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2419 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2420 | |
8fbca658 PA |
2421 | addr = tdep->sigcontext_addr (this_frame); |
2422 | if (tdep->sc_reg_offset) | |
2423 | { | |
2424 | int i; | |
a3386186 | 2425 | |
8fbca658 PA |
2426 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2427 | ||
2428 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2429 | if (tdep->sc_reg_offset[i] != -1) | |
2430 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2431 | } | |
2432 | else | |
2433 | { | |
2434 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2435 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2436 | } | |
2437 | ||
2438 | cache->base_p = 1; | |
a3386186 | 2439 | } |
492d29ea | 2440 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2441 | { |
2442 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2443 | throw_exception (ex); | |
2444 | } | |
492d29ea | 2445 | END_CATCH |
acd5c798 MK |
2446 | |
2447 | *this_cache = cache; | |
2448 | return cache; | |
2449 | } | |
2450 | ||
8fbca658 PA |
2451 | static enum unwind_stop_reason |
2452 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2453 | void **this_cache) | |
2454 | { | |
2455 | struct i386_frame_cache *cache = | |
2456 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2457 | ||
2458 | if (!cache->base_p) | |
2459 | return UNWIND_UNAVAILABLE; | |
2460 | ||
2461 | return UNWIND_NO_REASON; | |
2462 | } | |
2463 | ||
acd5c798 | 2464 | static void |
10458914 | 2465 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2466 | struct frame_id *this_id) |
2467 | { | |
2468 | struct i386_frame_cache *cache = | |
10458914 | 2469 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2470 | |
8fbca658 | 2471 | if (!cache->base_p) |
5ce0145d PA |
2472 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2473 | else | |
2474 | { | |
2475 | /* See the end of i386_push_dummy_call. */ | |
2476 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2477 | } | |
acd5c798 MK |
2478 | } |
2479 | ||
10458914 DJ |
2480 | static struct value * |
2481 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2482 | void **this_cache, int regnum) | |
acd5c798 MK |
2483 | { |
2484 | /* Make sure we've initialized the cache. */ | |
10458914 | 2485 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2486 | |
10458914 | 2487 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2488 | } |
c0d1d883 | 2489 | |
10458914 DJ |
2490 | static int |
2491 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2492 | struct frame_info *this_frame, | |
2493 | void **this_prologue_cache) | |
acd5c798 | 2494 | { |
10458914 | 2495 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2496 | |
911bc6ee MK |
2497 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2498 | handler. */ | |
2499 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2500 | return 0; |
1c3545ae | 2501 | |
911bc6ee MK |
2502 | if (tdep->sigtramp_p != NULL) |
2503 | { | |
10458914 DJ |
2504 | if (tdep->sigtramp_p (this_frame)) |
2505 | return 1; | |
911bc6ee MK |
2506 | } |
2507 | ||
2508 | if (tdep->sigtramp_start != 0) | |
2509 | { | |
10458914 | 2510 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2511 | |
2512 | gdb_assert (tdep->sigtramp_end != 0); | |
2513 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2514 | return 1; |
911bc6ee | 2515 | } |
acd5c798 | 2516 | |
10458914 | 2517 | return 0; |
acd5c798 | 2518 | } |
10458914 DJ |
2519 | |
2520 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2521 | { | |
2522 | SIGTRAMP_FRAME, | |
8fbca658 | 2523 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2524 | i386_sigtramp_frame_this_id, |
2525 | i386_sigtramp_frame_prev_register, | |
2526 | NULL, | |
2527 | i386_sigtramp_frame_sniffer | |
2528 | }; | |
acd5c798 MK |
2529 | \f |
2530 | ||
2531 | static CORE_ADDR | |
10458914 | 2532 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2533 | { |
10458914 | 2534 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2535 | |
2536 | return cache->base; | |
2537 | } | |
2538 | ||
2539 | static const struct frame_base i386_frame_base = | |
2540 | { | |
2541 | &i386_frame_unwind, | |
2542 | i386_frame_base_address, | |
2543 | i386_frame_base_address, | |
2544 | i386_frame_base_address | |
2545 | }; | |
2546 | ||
acd5c798 | 2547 | static struct frame_id |
10458914 | 2548 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2549 | { |
acd5c798 MK |
2550 | CORE_ADDR fp; |
2551 | ||
10458914 | 2552 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2553 | |
3e210248 | 2554 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2555 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2556 | } |
e04e5beb JM |
2557 | |
2558 | /* _Decimal128 function return values need 16-byte alignment on the | |
2559 | stack. */ | |
2560 | ||
2561 | static CORE_ADDR | |
2562 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2563 | { | |
2564 | return sp & -(CORE_ADDR)16; | |
2565 | } | |
fc338970 | 2566 | \f |
c906108c | 2567 | |
fc338970 MK |
2568 | /* Figure out where the longjmp will land. Slurp the args out of the |
2569 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2570 | structure from which we extract the address that we will land at. |
28bcfd30 | 2571 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2572 | success. */ |
c906108c | 2573 | |
8201327c | 2574 | static int |
60ade65d | 2575 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2576 | { |
436675d3 | 2577 | gdb_byte buf[4]; |
c906108c | 2578 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2579 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2580 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2581 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2582 | |
8201327c MK |
2583 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2584 | longjmp will land. */ | |
2585 | if (jb_pc_offset == -1) | |
c906108c SS |
2586 | return 0; |
2587 | ||
436675d3 | 2588 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2589 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2590 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2591 | return 0; |
2592 | ||
e17a4113 | 2593 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2594 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2595 | return 0; |
c906108c | 2596 | |
e17a4113 | 2597 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2598 | return 1; |
2599 | } | |
fc338970 | 2600 | \f |
c906108c | 2601 | |
7ccc1c74 JM |
2602 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2603 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2604 | unions containing such types must be 16-byte-aligned; other | |
2605 | arguments are 4-byte-aligned. */ | |
2606 | ||
2607 | static int | |
2608 | i386_16_byte_align_p (struct type *type) | |
2609 | { | |
2610 | type = check_typedef (type); | |
2611 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2612 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2613 | && TYPE_LENGTH (type) == 16) | |
2614 | return 1; | |
2615 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2616 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2617 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2618 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2619 | { | |
2620 | int i; | |
2621 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2622 | { | |
2623 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2624 | return 1; | |
2625 | } | |
2626 | } | |
2627 | return 0; | |
2628 | } | |
2629 | ||
a9b8d892 JK |
2630 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2631 | ||
2632 | static CORE_ADDR | |
2633 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2634 | struct value **args, int nargs, struct type *value_type, | |
2635 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2636 | struct regcache *regcache) | |
2637 | { | |
2638 | /* Use 0xcc breakpoint - 1 byte. */ | |
2639 | *bp_addr = sp - 1; | |
2640 | *real_pc = funaddr; | |
2641 | ||
2642 | /* Keep the stack aligned. */ | |
2643 | return sp - 16; | |
2644 | } | |
2645 | ||
3a1e71e3 | 2646 | static CORE_ADDR |
7d9b040b | 2647 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2648 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2649 | struct value **args, CORE_ADDR sp, int struct_return, | |
2650 | CORE_ADDR struct_addr) | |
22f8ba57 | 2651 | { |
e17a4113 | 2652 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2653 | gdb_byte buf[4]; |
acd5c798 | 2654 | int i; |
7ccc1c74 JM |
2655 | int write_pass; |
2656 | int args_space = 0; | |
acd5c798 | 2657 | |
7ccc1c74 JM |
2658 | /* Determine the total space required for arguments and struct |
2659 | return address in a first pass (allowing for 16-byte-aligned | |
2660 | arguments), then push arguments in a second pass. */ | |
2661 | ||
2662 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2663 | { |
7ccc1c74 | 2664 | int args_space_used = 0; |
7ccc1c74 JM |
2665 | |
2666 | if (struct_return) | |
2667 | { | |
2668 | if (write_pass) | |
2669 | { | |
2670 | /* Push value address. */ | |
e17a4113 | 2671 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2672 | write_memory (sp, buf, 4); |
2673 | args_space_used += 4; | |
2674 | } | |
2675 | else | |
2676 | args_space += 4; | |
2677 | } | |
2678 | ||
2679 | for (i = 0; i < nargs; i++) | |
2680 | { | |
2681 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2682 | |
7ccc1c74 JM |
2683 | if (write_pass) |
2684 | { | |
2685 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2686 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2687 | |
7ccc1c74 JM |
2688 | write_memory (sp + args_space_used, |
2689 | value_contents_all (args[i]), len); | |
2690 | /* The System V ABI says that: | |
acd5c798 | 2691 | |
7ccc1c74 JM |
2692 | "An argument's size is increased, if necessary, to make it a |
2693 | multiple of [32-bit] words. This may require tail padding, | |
2694 | depending on the size of the argument." | |
22f8ba57 | 2695 | |
7ccc1c74 JM |
2696 | This makes sure the stack stays word-aligned. */ |
2697 | args_space_used += align_up (len, 4); | |
2698 | } | |
2699 | else | |
2700 | { | |
2701 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2702 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2703 | args_space += align_up (len, 4); |
2704 | } | |
2705 | } | |
2706 | ||
2707 | if (!write_pass) | |
2708 | { | |
7ccc1c74 | 2709 | sp -= args_space; |
284c5a60 MK |
2710 | |
2711 | /* The original System V ABI only requires word alignment, | |
2712 | but modern incarnations need 16-byte alignment in order | |
2713 | to support SSE. Since wasting a few bytes here isn't | |
2714 | harmful we unconditionally enforce 16-byte alignment. */ | |
2715 | sp &= ~0xf; | |
7ccc1c74 | 2716 | } |
22f8ba57 MK |
2717 | } |
2718 | ||
acd5c798 MK |
2719 | /* Store return address. */ |
2720 | sp -= 4; | |
e17a4113 | 2721 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2722 | write_memory (sp, buf, 4); |
2723 | ||
2724 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2725 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2726 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2727 | ||
2728 | /* ...and fake a frame pointer. */ | |
2729 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2730 | ||
3e210248 AC |
2731 | /* MarkK wrote: This "+ 8" is all over the place: |
2732 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2733 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2734 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2735 | definition of the stack address of a frame. Otherwise frame id |
2736 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2737 | stack address *before* the function call as a frame's CFA. On |
2738 | the i386, when %ebp is used as a frame pointer, the offset | |
2739 | between the contents %ebp and the CFA as defined by GCC. */ | |
2740 | return sp + 8; | |
22f8ba57 MK |
2741 | } |
2742 | ||
1a309862 MK |
2743 | /* These registers are used for returning integers (and on some |
2744 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2745 | size and alignment match an integer type). */ |
acd5c798 MK |
2746 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2747 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2748 | |
c5e656c1 MK |
2749 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2750 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2751 | |
3a1e71e3 | 2752 | static void |
c5e656c1 | 2753 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2754 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2755 | { |
c5e656c1 | 2756 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2757 | int len = TYPE_LENGTH (type); |
63c0089f | 2758 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2759 | |
1e8d0a7b | 2760 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2761 | { |
5716833c | 2762 | if (tdep->st0_regnum < 0) |
1a309862 | 2763 | { |
8a3fe4f8 | 2764 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2765 | memset (valbuf, 0, len); |
ef9dff19 | 2766 | return; |
1a309862 MK |
2767 | } |
2768 | ||
c6ba6f0d MK |
2769 | /* Floating-point return values can be found in %st(0). Convert |
2770 | its contents to the desired type. This is probably not | |
2771 | exactly how it would happen on the target itself, but it is | |
2772 | the best we can do. */ | |
acd5c798 | 2773 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2774 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2775 | } |
2776 | else | |
c5aa993b | 2777 | { |
875f8d0e UW |
2778 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2779 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2780 | |
2781 | if (len <= low_size) | |
00f8375e | 2782 | { |
0818c12a | 2783 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2784 | memcpy (valbuf, buf, len); |
2785 | } | |
d4f3574e SS |
2786 | else if (len <= (low_size + high_size)) |
2787 | { | |
0818c12a | 2788 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2789 | memcpy (valbuf, buf, low_size); |
0818c12a | 2790 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2791 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2792 | } |
2793 | else | |
8e65ff28 | 2794 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2795 | _("Cannot extract return value of %d bytes long."), |
2796 | len); | |
c906108c SS |
2797 | } |
2798 | } | |
2799 | ||
c5e656c1 MK |
2800 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2801 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2802 | |
3a1e71e3 | 2803 | static void |
c5e656c1 | 2804 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2805 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2806 | { |
c5e656c1 | 2807 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2808 | int len = TYPE_LENGTH (type); |
2809 | ||
1e8d0a7b | 2810 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2811 | { |
3d7f4f49 | 2812 | ULONGEST fstat; |
63c0089f | 2813 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2814 | |
5716833c | 2815 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2816 | { |
8a3fe4f8 | 2817 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2818 | return; |
2819 | } | |
2820 | ||
635b0cc1 MK |
2821 | /* Returning floating-point values is a bit tricky. Apart from |
2822 | storing the return value in %st(0), we have to simulate the | |
2823 | state of the FPU at function return point. */ | |
2824 | ||
c6ba6f0d MK |
2825 | /* Convert the value found in VALBUF to the extended |
2826 | floating-point format used by the FPU. This is probably | |
2827 | not exactly how it would happen on the target itself, but | |
2828 | it is the best we can do. */ | |
27067745 | 2829 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2830 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2831 | |
635b0cc1 MK |
2832 | /* Set the top of the floating-point register stack to 7. The |
2833 | actual value doesn't really matter, but 7 is what a normal | |
2834 | function return would end up with if the program started out | |
2835 | with a freshly initialized FPU. */ | |
20a6ec49 | 2836 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2837 | fstat |= (7 << 11); |
20a6ec49 | 2838 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2839 | |
635b0cc1 MK |
2840 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2841 | the floating-point register stack to 7, the appropriate value | |
2842 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2843 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2844 | } |
2845 | else | |
2846 | { | |
875f8d0e UW |
2847 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2848 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2849 | |
2850 | if (len <= low_size) | |
3d7f4f49 | 2851 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2852 | else if (len <= (low_size + high_size)) |
2853 | { | |
3d7f4f49 MK |
2854 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2855 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2856 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2857 | } |
2858 | else | |
8e65ff28 | 2859 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2860 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2861 | } |
2862 | } | |
fc338970 | 2863 | \f |
ef9dff19 | 2864 | |
8201327c MK |
2865 | /* This is the variable that is set with "set struct-convention", and |
2866 | its legitimate values. */ | |
2867 | static const char default_struct_convention[] = "default"; | |
2868 | static const char pcc_struct_convention[] = "pcc"; | |
2869 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2870 | static const char *const valid_conventions[] = |
8201327c MK |
2871 | { |
2872 | default_struct_convention, | |
2873 | pcc_struct_convention, | |
2874 | reg_struct_convention, | |
2875 | NULL | |
2876 | }; | |
2877 | static const char *struct_convention = default_struct_convention; | |
2878 | ||
0e4377e1 JB |
2879 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2880 | a union type, or an array type, should be returned in registers | |
2881 | for architecture GDBARCH. */ | |
c5e656c1 | 2882 | |
8201327c | 2883 | static int |
c5e656c1 | 2884 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2885 | { |
c5e656c1 MK |
2886 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2887 | enum type_code code = TYPE_CODE (type); | |
2888 | int len = TYPE_LENGTH (type); | |
8201327c | 2889 | |
0e4377e1 JB |
2890 | gdb_assert (code == TYPE_CODE_STRUCT |
2891 | || code == TYPE_CODE_UNION | |
2892 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2893 | |
2894 | if (struct_convention == pcc_struct_convention | |
2895 | || (struct_convention == default_struct_convention | |
2896 | && tdep->struct_return == pcc_struct_return)) | |
2897 | return 0; | |
2898 | ||
9edde48e MK |
2899 | /* Structures consisting of a single `float', `double' or 'long |
2900 | double' member are returned in %st(0). */ | |
2901 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2902 | { | |
2903 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2904 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2905 | return (len == 4 || len == 8 || len == 12); | |
2906 | } | |
2907 | ||
c5e656c1 MK |
2908 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2909 | } | |
2910 | ||
2911 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2912 | should be returned. If it is supposed to be returned in registers, | |
2913 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2914 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2915 | from WRITEBUF into REGCACHE. */ | |
2916 | ||
2917 | static enum return_value_convention | |
6a3a010b | 2918 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2919 | struct type *type, struct regcache *regcache, |
2920 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2921 | { |
2922 | enum type_code code = TYPE_CODE (type); | |
2923 | ||
5daa78cc TJB |
2924 | if (((code == TYPE_CODE_STRUCT |
2925 | || code == TYPE_CODE_UNION | |
2926 | || code == TYPE_CODE_ARRAY) | |
2927 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2928 | /* Complex double and long double uses the struct return covention. */ |
2929 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2930 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2931 | /* 128-bit decimal float uses the struct return convention. */ |
2932 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2933 | { |
2934 | /* The System V ABI says that: | |
2935 | ||
2936 | "A function that returns a structure or union also sets %eax | |
2937 | to the value of the original address of the caller's area | |
2938 | before it returns. Thus when the caller receives control | |
2939 | again, the address of the returned object resides in register | |
2940 | %eax and can be used to access the object." | |
2941 | ||
2942 | So the ABI guarantees that we can always find the return | |
2943 | value just after the function has returned. */ | |
2944 | ||
0e4377e1 JB |
2945 | /* Note that the ABI doesn't mention functions returning arrays, |
2946 | which is something possible in certain languages such as Ada. | |
2947 | In this case, the value is returned as if it was wrapped in | |
2948 | a record, so the convention applied to records also applies | |
2949 | to arrays. */ | |
2950 | ||
31db7b6c MK |
2951 | if (readbuf) |
2952 | { | |
2953 | ULONGEST addr; | |
2954 | ||
2955 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2956 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2957 | } | |
2958 | ||
2959 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2960 | } | |
c5e656c1 MK |
2961 | |
2962 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2963 | `float', `double' or 'long double' member. These structures are |
2964 | returned in %st(0). For these structures, we call ourselves | |
2965 | recursively, changing TYPE into the type of the first member of | |
2966 | the structure. Since that should work for all structures that | |
2967 | have only one member, we don't bother to check the member's type | |
2968 | here. */ | |
c5e656c1 MK |
2969 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2970 | { | |
2971 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2972 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2973 | readbuf, writebuf); |
c5e656c1 MK |
2974 | } |
2975 | ||
2976 | if (readbuf) | |
2977 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2978 | if (writebuf) | |
2979 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2980 | |
c5e656c1 | 2981 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2982 | } |
2983 | \f | |
2984 | ||
27067745 UW |
2985 | struct type * |
2986 | i387_ext_type (struct gdbarch *gdbarch) | |
2987 | { | |
2988 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2989 | ||
2990 | if (!tdep->i387_ext_type) | |
90884b2b L |
2991 | { |
2992 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2993 | gdb_assert (tdep->i387_ext_type != NULL); | |
2994 | } | |
27067745 UW |
2995 | |
2996 | return tdep->i387_ext_type; | |
2997 | } | |
2998 | ||
1dbcd68c WT |
2999 | /* Construct type for pseudo BND registers. We can't use |
3000 | tdesc_find_type since a complement of one value has to be used | |
3001 | to describe the upper bound. */ | |
3002 | ||
3003 | static struct type * | |
3004 | i386_bnd_type (struct gdbarch *gdbarch) | |
3005 | { | |
3006 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3007 | ||
3008 | ||
3009 | if (!tdep->i386_bnd_type) | |
3010 | { | |
3011 | struct type *t, *bound_t; | |
3012 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3013 | ||
3014 | /* The type we're building is described bellow: */ | |
3015 | #if 0 | |
3016 | struct __bound128 | |
3017 | { | |
3018 | void *lbound; | |
3019 | void *ubound; /* One complement of raw ubound field. */ | |
3020 | }; | |
3021 | #endif | |
3022 | ||
3023 | t = arch_composite_type (gdbarch, | |
3024 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3025 | ||
3026 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3027 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3028 | ||
3029 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3030 | tdep->i386_bnd_type = t; | |
3031 | } | |
3032 | ||
3033 | return tdep->i386_bnd_type; | |
3034 | } | |
3035 | ||
01f9f808 MS |
3036 | /* Construct vector type for pseudo ZMM registers. We can't use |
3037 | tdesc_find_type since ZMM isn't described in target description. */ | |
3038 | ||
3039 | static struct type * | |
3040 | i386_zmm_type (struct gdbarch *gdbarch) | |
3041 | { | |
3042 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3043 | ||
3044 | if (!tdep->i386_zmm_type) | |
3045 | { | |
3046 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3047 | ||
3048 | /* The type we're building is this: */ | |
3049 | #if 0 | |
3050 | union __gdb_builtin_type_vec512i | |
3051 | { | |
3052 | int128_t uint128[4]; | |
3053 | int64_t v4_int64[8]; | |
3054 | int32_t v8_int32[16]; | |
3055 | int16_t v16_int16[32]; | |
3056 | int8_t v32_int8[64]; | |
3057 | double v4_double[8]; | |
3058 | float v8_float[16]; | |
3059 | }; | |
3060 | #endif | |
3061 | ||
3062 | struct type *t; | |
3063 | ||
3064 | t = arch_composite_type (gdbarch, | |
3065 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3066 | append_composite_type_field (t, "v16_float", | |
3067 | init_vector_type (bt->builtin_float, 16)); | |
3068 | append_composite_type_field (t, "v8_double", | |
3069 | init_vector_type (bt->builtin_double, 8)); | |
3070 | append_composite_type_field (t, "v64_int8", | |
3071 | init_vector_type (bt->builtin_int8, 64)); | |
3072 | append_composite_type_field (t, "v32_int16", | |
3073 | init_vector_type (bt->builtin_int16, 32)); | |
3074 | append_composite_type_field (t, "v16_int32", | |
3075 | init_vector_type (bt->builtin_int32, 16)); | |
3076 | append_composite_type_field (t, "v8_int64", | |
3077 | init_vector_type (bt->builtin_int64, 8)); | |
3078 | append_composite_type_field (t, "v4_int128", | |
3079 | init_vector_type (bt->builtin_int128, 4)); | |
3080 | ||
3081 | TYPE_VECTOR (t) = 1; | |
3082 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3083 | tdep->i386_zmm_type = t; | |
3084 | } | |
3085 | ||
3086 | return tdep->i386_zmm_type; | |
3087 | } | |
3088 | ||
c131fcee L |
3089 | /* Construct vector type for pseudo YMM registers. We can't use |
3090 | tdesc_find_type since YMM isn't described in target description. */ | |
3091 | ||
3092 | static struct type * | |
3093 | i386_ymm_type (struct gdbarch *gdbarch) | |
3094 | { | |
3095 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3096 | ||
3097 | if (!tdep->i386_ymm_type) | |
3098 | { | |
3099 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3100 | ||
3101 | /* The type we're building is this: */ | |
3102 | #if 0 | |
3103 | union __gdb_builtin_type_vec256i | |
3104 | { | |
3105 | int128_t uint128[2]; | |
3106 | int64_t v2_int64[4]; | |
3107 | int32_t v4_int32[8]; | |
3108 | int16_t v8_int16[16]; | |
3109 | int8_t v16_int8[32]; | |
3110 | double v2_double[4]; | |
3111 | float v4_float[8]; | |
3112 | }; | |
3113 | #endif | |
3114 | ||
3115 | struct type *t; | |
3116 | ||
3117 | t = arch_composite_type (gdbarch, | |
3118 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3119 | append_composite_type_field (t, "v8_float", | |
3120 | init_vector_type (bt->builtin_float, 8)); | |
3121 | append_composite_type_field (t, "v4_double", | |
3122 | init_vector_type (bt->builtin_double, 4)); | |
3123 | append_composite_type_field (t, "v32_int8", | |
3124 | init_vector_type (bt->builtin_int8, 32)); | |
3125 | append_composite_type_field (t, "v16_int16", | |
3126 | init_vector_type (bt->builtin_int16, 16)); | |
3127 | append_composite_type_field (t, "v8_int32", | |
3128 | init_vector_type (bt->builtin_int32, 8)); | |
3129 | append_composite_type_field (t, "v4_int64", | |
3130 | init_vector_type (bt->builtin_int64, 4)); | |
3131 | append_composite_type_field (t, "v2_int128", | |
3132 | init_vector_type (bt->builtin_int128, 2)); | |
3133 | ||
3134 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3135 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3136 | tdep->i386_ymm_type = t; |
3137 | } | |
3138 | ||
3139 | return tdep->i386_ymm_type; | |
3140 | } | |
3141 | ||
794ac428 | 3142 | /* Construct vector type for MMX registers. */ |
90884b2b | 3143 | static struct type * |
794ac428 UW |
3144 | i386_mmx_type (struct gdbarch *gdbarch) |
3145 | { | |
3146 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3147 | ||
3148 | if (!tdep->i386_mmx_type) | |
3149 | { | |
df4df182 UW |
3150 | const struct builtin_type *bt = builtin_type (gdbarch); |
3151 | ||
794ac428 UW |
3152 | /* The type we're building is this: */ |
3153 | #if 0 | |
3154 | union __gdb_builtin_type_vec64i | |
3155 | { | |
3156 | int64_t uint64; | |
3157 | int32_t v2_int32[2]; | |
3158 | int16_t v4_int16[4]; | |
3159 | int8_t v8_int8[8]; | |
3160 | }; | |
3161 | #endif | |
3162 | ||
3163 | struct type *t; | |
3164 | ||
e9bb382b UW |
3165 | t = arch_composite_type (gdbarch, |
3166 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3167 | |
3168 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3169 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3170 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3171 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3172 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3173 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3174 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3175 | |
876cecd0 | 3176 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3177 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3178 | tdep->i386_mmx_type = t; | |
3179 | } | |
3180 | ||
3181 | return tdep->i386_mmx_type; | |
3182 | } | |
3183 | ||
d7a0d72c | 3184 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3185 | register REGNUM. */ |
d7a0d72c | 3186 | |
fff4548b | 3187 | struct type * |
90884b2b | 3188 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3189 | { |
1dbcd68c WT |
3190 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3191 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3192 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3193 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3194 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3195 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3196 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3197 | return i386_ymm_type (gdbarch); | |
3198 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3199 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3200 | else |
3201 | { | |
3202 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3203 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3204 | return bt->builtin_int8; | |
3205 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3206 | return bt->builtin_int16; | |
3207 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3208 | return bt->builtin_int32; | |
01f9f808 MS |
3209 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3210 | return bt->builtin_int64; | |
1ba53b71 L |
3211 | } |
3212 | ||
3213 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3214 | } |
3215 | ||
28fc6740 | 3216 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3217 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3218 | |
3219 | static int | |
c86c27af | 3220 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3221 | { |
5716833c MK |
3222 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3223 | int mmxreg, fpreg; | |
28fc6740 AC |
3224 | ULONGEST fstat; |
3225 | int tos; | |
c86c27af | 3226 | |
5716833c | 3227 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3228 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3229 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3230 | fpreg = (mmxreg + tos) % 8; |
3231 | ||
20a6ec49 | 3232 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3233 | } |
3234 | ||
3543a589 TT |
3235 | /* A helper function for us by i386_pseudo_register_read_value and |
3236 | amd64_pseudo_register_read_value. It does all the work but reads | |
3237 | the data into an already-allocated value. */ | |
3238 | ||
3239 | void | |
3240 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3241 | struct regcache *regcache, | |
3242 | int regnum, | |
3243 | struct value *result_value) | |
28fc6740 | 3244 | { |
1ba53b71 | 3245 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 3246 | enum register_status status; |
3543a589 | 3247 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3248 | |
5716833c | 3249 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3250 | { |
c86c27af MK |
3251 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3252 | ||
28fc6740 | 3253 | /* Extract (always little endian). */ |
05d1431c PA |
3254 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3255 | if (status != REG_VALID) | |
3543a589 TT |
3256 | mark_value_bytes_unavailable (result_value, 0, |
3257 | TYPE_LENGTH (value_type (result_value))); | |
3258 | else | |
3259 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3260 | } |
3261 | else | |
1ba53b71 L |
3262 | { |
3263 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3264 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3265 | { | |
3266 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3267 | |
1dbcd68c WT |
3268 | /* Extract (always little endian). Read lower 128bits. */ |
3269 | status = regcache_raw_read (regcache, | |
3270 | I387_BND0R_REGNUM (tdep) + regnum, | |
3271 | raw_buf); | |
3272 | if (status != REG_VALID) | |
3273 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3274 | else | |
3275 | { | |
3276 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3277 | LONGEST upper, lower; | |
3278 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3279 | ||
3280 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3281 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3282 | upper = ~upper; | |
3283 | ||
3284 | memcpy (buf, &lower, size); | |
3285 | memcpy (buf + size, &upper, size); | |
3286 | } | |
3287 | } | |
01f9f808 MS |
3288 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3289 | { | |
3290 | regnum -= tdep->k0_regnum; | |
3291 | ||
3292 | /* Extract (always little endian). */ | |
3293 | status = regcache_raw_read (regcache, | |
3294 | tdep->k0_regnum + regnum, | |
3295 | raw_buf); | |
3296 | if (status != REG_VALID) | |
3297 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3298 | else | |
3299 | memcpy (buf, raw_buf, 8); | |
3300 | } | |
3301 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3302 | { | |
3303 | regnum -= tdep->zmm0_regnum; | |
3304 | ||
3305 | if (regnum < num_lower_zmm_regs) | |
3306 | { | |
3307 | /* Extract (always little endian). Read lower 128bits. */ | |
3308 | status = regcache_raw_read (regcache, | |
3309 | I387_XMM0_REGNUM (tdep) + regnum, | |
3310 | raw_buf); | |
3311 | if (status != REG_VALID) | |
3312 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3313 | else | |
3314 | memcpy (buf, raw_buf, 16); | |
3315 | ||
3316 | /* Extract (always little endian). Read upper 128bits. */ | |
3317 | status = regcache_raw_read (regcache, | |
3318 | tdep->ymm0h_regnum + regnum, | |
3319 | raw_buf); | |
3320 | if (status != REG_VALID) | |
3321 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3322 | else | |
3323 | memcpy (buf + 16, raw_buf, 16); | |
3324 | } | |
3325 | else | |
3326 | { | |
3327 | /* Extract (always little endian). Read lower 128bits. */ | |
3328 | status = regcache_raw_read (regcache, | |
3329 | I387_XMM16_REGNUM (tdep) + regnum | |
3330 | - num_lower_zmm_regs, | |
3331 | raw_buf); | |
3332 | if (status != REG_VALID) | |
3333 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3334 | else | |
3335 | memcpy (buf, raw_buf, 16); | |
3336 | ||
3337 | /* Extract (always little endian). Read upper 128bits. */ | |
3338 | status = regcache_raw_read (regcache, | |
3339 | I387_YMM16H_REGNUM (tdep) + regnum | |
3340 | - num_lower_zmm_regs, | |
3341 | raw_buf); | |
3342 | if (status != REG_VALID) | |
3343 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3344 | else | |
3345 | memcpy (buf + 16, raw_buf, 16); | |
3346 | } | |
3347 | ||
3348 | /* Read upper 256bits. */ | |
3349 | status = regcache_raw_read (regcache, | |
3350 | tdep->zmm0h_regnum + regnum, | |
3351 | raw_buf); | |
3352 | if (status != REG_VALID) | |
3353 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3354 | else | |
3355 | memcpy (buf + 32, raw_buf, 32); | |
3356 | } | |
1dbcd68c | 3357 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3358 | { |
3359 | regnum -= tdep->ymm0_regnum; | |
3360 | ||
1777feb0 | 3361 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3362 | status = regcache_raw_read (regcache, |
3363 | I387_XMM0_REGNUM (tdep) + regnum, | |
3364 | raw_buf); | |
3365 | if (status != REG_VALID) | |
3543a589 TT |
3366 | mark_value_bytes_unavailable (result_value, 0, 16); |
3367 | else | |
3368 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3369 | /* Read upper 128bits. */ |
05d1431c PA |
3370 | status = regcache_raw_read (regcache, |
3371 | tdep->ymm0h_regnum + regnum, | |
3372 | raw_buf); | |
3373 | if (status != REG_VALID) | |
3543a589 TT |
3374 | mark_value_bytes_unavailable (result_value, 16, 32); |
3375 | else | |
3376 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3377 | } |
01f9f808 MS |
3378 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3379 | { | |
3380 | regnum -= tdep->ymm16_regnum; | |
3381 | /* Extract (always little endian). Read lower 128bits. */ | |
3382 | status = regcache_raw_read (regcache, | |
3383 | I387_XMM16_REGNUM (tdep) + regnum, | |
3384 | raw_buf); | |
3385 | if (status != REG_VALID) | |
3386 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3387 | else | |
3388 | memcpy (buf, raw_buf, 16); | |
3389 | /* Read upper 128bits. */ | |
3390 | status = regcache_raw_read (regcache, | |
3391 | tdep->ymm16h_regnum + regnum, | |
3392 | raw_buf); | |
3393 | if (status != REG_VALID) | |
3394 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3395 | else | |
3396 | memcpy (buf + 16, raw_buf, 16); | |
3397 | } | |
c131fcee | 3398 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3399 | { |
3400 | int gpnum = regnum - tdep->ax_regnum; | |
3401 | ||
3402 | /* Extract (always little endian). */ | |
05d1431c PA |
3403 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3404 | if (status != REG_VALID) | |
3543a589 TT |
3405 | mark_value_bytes_unavailable (result_value, 0, |
3406 | TYPE_LENGTH (value_type (result_value))); | |
3407 | else | |
3408 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3409 | } |
3410 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3411 | { | |
3412 | /* Check byte pseudo registers last since this function will | |
3413 | be called from amd64_pseudo_register_read, which handles | |
3414 | byte pseudo registers differently. */ | |
3415 | int gpnum = regnum - tdep->al_regnum; | |
3416 | ||
3417 | /* Extract (always little endian). We read both lower and | |
3418 | upper registers. */ | |
05d1431c PA |
3419 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3420 | if (status != REG_VALID) | |
3543a589 TT |
3421 | mark_value_bytes_unavailable (result_value, 0, |
3422 | TYPE_LENGTH (value_type (result_value))); | |
3423 | else if (gpnum >= 4) | |
1ba53b71 L |
3424 | memcpy (buf, raw_buf + 1, 1); |
3425 | else | |
3426 | memcpy (buf, raw_buf, 1); | |
3427 | } | |
3428 | else | |
3429 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3430 | } | |
3543a589 TT |
3431 | } |
3432 | ||
3433 | static struct value * | |
3434 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3435 | struct regcache *regcache, | |
3436 | int regnum) | |
3437 | { | |
3438 | struct value *result; | |
3439 | ||
3440 | result = allocate_value (register_type (gdbarch, regnum)); | |
3441 | VALUE_LVAL (result) = lval_register; | |
3442 | VALUE_REGNUM (result) = regnum; | |
3443 | ||
3444 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3445 | |
3543a589 | 3446 | return result; |
28fc6740 AC |
3447 | } |
3448 | ||
1ba53b71 | 3449 | void |
28fc6740 | 3450 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3451 | int regnum, const gdb_byte *buf) |
28fc6740 | 3452 | { |
1ba53b71 L |
3453 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
3454 | ||
5716833c | 3455 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3456 | { |
c86c27af MK |
3457 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3458 | ||
28fc6740 | 3459 | /* Read ... */ |
1ba53b71 | 3460 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3461 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3462 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3463 | /* ... Write. */ |
1ba53b71 | 3464 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3465 | } |
3466 | else | |
1ba53b71 L |
3467 | { |
3468 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3469 | ||
1dbcd68c WT |
3470 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3471 | { | |
3472 | ULONGEST upper, lower; | |
3473 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3474 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3475 | ||
3476 | /* New values from input value. */ | |
3477 | regnum -= tdep->bnd0_regnum; | |
3478 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3479 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3480 | ||
3481 | /* Fetching register buffer. */ | |
3482 | regcache_raw_read (regcache, | |
3483 | I387_BND0R_REGNUM (tdep) + regnum, | |
3484 | raw_buf); | |
3485 | ||
3486 | upper = ~upper; | |
3487 | ||
3488 | /* Set register bits. */ | |
3489 | memcpy (raw_buf, &lower, 8); | |
3490 | memcpy (raw_buf + 8, &upper, 8); | |
3491 | ||
3492 | ||
3493 | regcache_raw_write (regcache, | |
3494 | I387_BND0R_REGNUM (tdep) + regnum, | |
3495 | raw_buf); | |
3496 | } | |
01f9f808 MS |
3497 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3498 | { | |
3499 | regnum -= tdep->k0_regnum; | |
3500 | ||
3501 | regcache_raw_write (regcache, | |
3502 | tdep->k0_regnum + regnum, | |
3503 | buf); | |
3504 | } | |
3505 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3506 | { | |
3507 | regnum -= tdep->zmm0_regnum; | |
3508 | ||
3509 | if (regnum < num_lower_zmm_regs) | |
3510 | { | |
3511 | /* Write lower 128bits. */ | |
3512 | regcache_raw_write (regcache, | |
3513 | I387_XMM0_REGNUM (tdep) + regnum, | |
3514 | buf); | |
3515 | /* Write upper 128bits. */ | |
3516 | regcache_raw_write (regcache, | |
3517 | I387_YMM0_REGNUM (tdep) + regnum, | |
3518 | buf + 16); | |
3519 | } | |
3520 | else | |
3521 | { | |
3522 | /* Write lower 128bits. */ | |
3523 | regcache_raw_write (regcache, | |
3524 | I387_XMM16_REGNUM (tdep) + regnum | |
3525 | - num_lower_zmm_regs, | |
3526 | buf); | |
3527 | /* Write upper 128bits. */ | |
3528 | regcache_raw_write (regcache, | |
3529 | I387_YMM16H_REGNUM (tdep) + regnum | |
3530 | - num_lower_zmm_regs, | |
3531 | buf + 16); | |
3532 | } | |
3533 | /* Write upper 256bits. */ | |
3534 | regcache_raw_write (regcache, | |
3535 | tdep->zmm0h_regnum + regnum, | |
3536 | buf + 32); | |
3537 | } | |
1dbcd68c | 3538 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3539 | { |
3540 | regnum -= tdep->ymm0_regnum; | |
3541 | ||
3542 | /* ... Write lower 128bits. */ | |
3543 | regcache_raw_write (regcache, | |
3544 | I387_XMM0_REGNUM (tdep) + regnum, | |
3545 | buf); | |
3546 | /* ... Write upper 128bits. */ | |
3547 | regcache_raw_write (regcache, | |
3548 | tdep->ymm0h_regnum + regnum, | |
3549 | buf + 16); | |
3550 | } | |
01f9f808 MS |
3551 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3552 | { | |
3553 | regnum -= tdep->ymm16_regnum; | |
3554 | ||
3555 | /* ... Write lower 128bits. */ | |
3556 | regcache_raw_write (regcache, | |
3557 | I387_XMM16_REGNUM (tdep) + regnum, | |
3558 | buf); | |
3559 | /* ... Write upper 128bits. */ | |
3560 | regcache_raw_write (regcache, | |
3561 | tdep->ymm16h_regnum + regnum, | |
3562 | buf + 16); | |
3563 | } | |
c131fcee | 3564 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3565 | { |
3566 | int gpnum = regnum - tdep->ax_regnum; | |
3567 | ||
3568 | /* Read ... */ | |
3569 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3570 | /* ... Modify ... (always little endian). */ | |
3571 | memcpy (raw_buf, buf, 2); | |
3572 | /* ... Write. */ | |
3573 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3574 | } | |
3575 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3576 | { | |
3577 | /* Check byte pseudo registers last since this function will | |
3578 | be called from amd64_pseudo_register_read, which handles | |
3579 | byte pseudo registers differently. */ | |
3580 | int gpnum = regnum - tdep->al_regnum; | |
3581 | ||
3582 | /* Read ... We read both lower and upper registers. */ | |
3583 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3584 | /* ... Modify ... (always little endian). */ | |
3585 | if (gpnum >= 4) | |
3586 | memcpy (raw_buf + 1, buf, 1); | |
3587 | else | |
3588 | memcpy (raw_buf, buf, 1); | |
3589 | /* ... Write. */ | |
3590 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3591 | } | |
3592 | else | |
3593 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3594 | } | |
28fc6740 | 3595 | } |
ff2e87ac AC |
3596 | \f |
3597 | ||
ff2e87ac AC |
3598 | /* Return the register number of the register allocated by GCC after |
3599 | REGNUM, or -1 if there is no such register. */ | |
3600 | ||
3601 | static int | |
3602 | i386_next_regnum (int regnum) | |
3603 | { | |
3604 | /* GCC allocates the registers in the order: | |
3605 | ||
3606 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3607 | ||
3608 | Since storing a variable in %esp doesn't make any sense we return | |
3609 | -1 for %ebp and for %esp itself. */ | |
3610 | static int next_regnum[] = | |
3611 | { | |
3612 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3613 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3614 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3615 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3616 | -1, -1, /* Slots for %esp and %ebp. */ | |
3617 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3618 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3619 | }; | |
3620 | ||
de5b9bb9 | 3621 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3622 | return next_regnum[regnum]; |
28fc6740 | 3623 | |
ff2e87ac AC |
3624 | return -1; |
3625 | } | |
3626 | ||
3627 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3628 | needs any special handling. */ | |
d7a0d72c | 3629 | |
3a1e71e3 | 3630 | static int |
1777feb0 MS |
3631 | i386_convert_register_p (struct gdbarch *gdbarch, |
3632 | int regnum, struct type *type) | |
d7a0d72c | 3633 | { |
de5b9bb9 MK |
3634 | int len = TYPE_LENGTH (type); |
3635 | ||
ff2e87ac AC |
3636 | /* Values may be spread across multiple registers. Most debugging |
3637 | formats aren't expressive enough to specify the locations, so | |
3638 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3639 | have a length that is a multiple of the word size, since GCC |
3640 | doesn't seem to put any other types into registers. */ | |
3641 | if (len > 4 && len % 4 == 0) | |
3642 | { | |
3643 | int last_regnum = regnum; | |
3644 | ||
3645 | while (len > 4) | |
3646 | { | |
3647 | last_regnum = i386_next_regnum (last_regnum); | |
3648 | len -= 4; | |
3649 | } | |
3650 | ||
3651 | if (last_regnum != -1) | |
3652 | return 1; | |
3653 | } | |
ff2e87ac | 3654 | |
0abe36f5 | 3655 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3656 | } |
3657 | ||
ff2e87ac AC |
3658 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3659 | return its contents in TO. */ | |
ac27f131 | 3660 | |
8dccd430 | 3661 | static int |
ff2e87ac | 3662 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3663 | struct type *type, gdb_byte *to, |
3664 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3665 | { |
20a6ec49 | 3666 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3667 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3668 | |
20a6ec49 | 3669 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3670 | return i387_register_to_value (frame, regnum, type, to, |
3671 | optimizedp, unavailablep); | |
ff2e87ac | 3672 | |
fd35795f | 3673 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3674 | |
3675 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3676 | |
de5b9bb9 MK |
3677 | while (len > 0) |
3678 | { | |
3679 | gdb_assert (regnum != -1); | |
20a6ec49 | 3680 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3681 | |
8dccd430 PA |
3682 | if (!get_frame_register_bytes (frame, regnum, 0, |
3683 | register_size (gdbarch, regnum), | |
3684 | to, optimizedp, unavailablep)) | |
3685 | return 0; | |
3686 | ||
de5b9bb9 MK |
3687 | regnum = i386_next_regnum (regnum); |
3688 | len -= 4; | |
42835c2b | 3689 | to += 4; |
de5b9bb9 | 3690 | } |
8dccd430 PA |
3691 | |
3692 | *optimizedp = *unavailablep = 0; | |
3693 | return 1; | |
ac27f131 MK |
3694 | } |
3695 | ||
ff2e87ac AC |
3696 | /* Write the contents FROM of a value of type TYPE into register |
3697 | REGNUM in frame FRAME. */ | |
ac27f131 | 3698 | |
3a1e71e3 | 3699 | static void |
ff2e87ac | 3700 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3701 | struct type *type, const gdb_byte *from) |
ac27f131 | 3702 | { |
de5b9bb9 | 3703 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3704 | |
20a6ec49 | 3705 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3706 | { |
d532c08f MK |
3707 | i387_value_to_register (frame, regnum, type, from); |
3708 | return; | |
3709 | } | |
3d261580 | 3710 | |
fd35795f | 3711 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3712 | |
3713 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3714 | |
de5b9bb9 MK |
3715 | while (len > 0) |
3716 | { | |
3717 | gdb_assert (regnum != -1); | |
875f8d0e | 3718 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3719 | |
42835c2b | 3720 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3721 | regnum = i386_next_regnum (regnum); |
3722 | len -= 4; | |
42835c2b | 3723 | from += 4; |
de5b9bb9 | 3724 | } |
ac27f131 | 3725 | } |
ff2e87ac | 3726 | \f |
7fdafb5a MK |
3727 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3728 | in the general-purpose register set REGSET to register cache | |
3729 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3730 | |
20187ed5 | 3731 | void |
473f17b0 MK |
3732 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3733 | int regnum, const void *gregs, size_t len) | |
3734 | { | |
09424cff AA |
3735 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3736 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3737 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3738 | int i; |
3739 | ||
1528345d | 3740 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3741 | |
3742 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3743 | { | |
3744 | if ((regnum == i || regnum == -1) | |
3745 | && tdep->gregset_reg_offset[i] != -1) | |
3746 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3747 | } | |
3748 | } | |
3749 | ||
7fdafb5a MK |
3750 | /* Collect register REGNUM from the register cache REGCACHE and store |
3751 | it in the buffer specified by GREGS and LEN as described by the | |
3752 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3753 | all registers in REGSET. */ | |
3754 | ||
ecc37a5a | 3755 | static void |
7fdafb5a MK |
3756 | i386_collect_gregset (const struct regset *regset, |
3757 | const struct regcache *regcache, | |
3758 | int regnum, void *gregs, size_t len) | |
3759 | { | |
09424cff AA |
3760 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3761 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3762 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3763 | int i; |
3764 | ||
1528345d | 3765 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3766 | |
3767 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3768 | { | |
3769 | if ((regnum == i || regnum == -1) | |
3770 | && tdep->gregset_reg_offset[i] != -1) | |
3771 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3772 | } | |
3773 | } | |
3774 | ||
3775 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3776 | in the floating-point register set REGSET to register cache | |
3777 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3778 | |
3779 | static void | |
3780 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3781 | int regnum, const void *fpregs, size_t len) | |
3782 | { | |
09424cff AA |
3783 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3784 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3785 | |
66a72d25 MK |
3786 | if (len == I387_SIZEOF_FXSAVE) |
3787 | { | |
3788 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3789 | return; | |
3790 | } | |
3791 | ||
1528345d | 3792 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3793 | i387_supply_fsave (regcache, regnum, fpregs); |
3794 | } | |
8446b36a | 3795 | |
2f305df1 MK |
3796 | /* Collect register REGNUM from the register cache REGCACHE and store |
3797 | it in the buffer specified by FPREGS and LEN as described by the | |
3798 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3799 | all registers in REGSET. */ | |
7fdafb5a MK |
3800 | |
3801 | static void | |
3802 | i386_collect_fpregset (const struct regset *regset, | |
3803 | const struct regcache *regcache, | |
3804 | int regnum, void *fpregs, size_t len) | |
3805 | { | |
09424cff AA |
3806 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3807 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3808 | |
3809 | if (len == I387_SIZEOF_FXSAVE) | |
3810 | { | |
3811 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3812 | return; | |
3813 | } | |
3814 | ||
1528345d | 3815 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3816 | i387_collect_fsave (regcache, regnum, fpregs); |
3817 | } | |
3818 | ||
ecc37a5a AA |
3819 | /* Register set definitions. */ |
3820 | ||
3821 | const struct regset i386_gregset = | |
3822 | { | |
3823 | NULL, i386_supply_gregset, i386_collect_gregset | |
3824 | }; | |
3825 | ||
8f0435f7 | 3826 | const struct regset i386_fpregset = |
ecc37a5a AA |
3827 | { |
3828 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3829 | }; | |
3830 | ||
490496c3 | 3831 | /* Default iterator over core file register note sections. */ |
8446b36a | 3832 | |
490496c3 AA |
3833 | void |
3834 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3835 | iterate_over_regset_sections_cb *cb, | |
3836 | void *cb_data, | |
3837 | const struct regcache *regcache) | |
8446b36a MK |
3838 | { |
3839 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3840 | ||
490496c3 AA |
3841 | cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data); |
3842 | if (tdep->sizeof_fpregset) | |
3843 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
8446b36a | 3844 | } |
473f17b0 | 3845 | \f |
fc338970 | 3846 | |
fc338970 | 3847 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3848 | |
3849 | CORE_ADDR | |
e17a4113 UW |
3850 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3851 | CORE_ADDR pc, char *name) | |
c906108c | 3852 | { |
e17a4113 UW |
3853 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3854 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3855 | ||
3856 | /* jmp *(dest) */ | |
3857 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3858 | { |
e17a4113 UW |
3859 | unsigned long indirect = |
3860 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3861 | struct minimal_symbol *indsym = |
7cbd4a93 | 3862 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3863 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3864 | |
c5aa993b | 3865 | if (symname) |
c906108c | 3866 | { |
61012eef GB |
3867 | if (startswith (symname, "__imp_") |
3868 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3869 | return name ? 1 : |
3870 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3871 | } |
3872 | } | |
fc338970 | 3873 | return 0; /* Not a trampoline. */ |
c906108c | 3874 | } |
fc338970 MK |
3875 | \f |
3876 | ||
10458914 DJ |
3877 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3878 | routine. */ | |
8201327c | 3879 | |
4bd207ef | 3880 | int |
10458914 | 3881 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3882 | { |
10458914 | 3883 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3884 | const char *name; |
911bc6ee MK |
3885 | |
3886 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3887 | return (name && strcmp ("_sigtramp", name) == 0); |
3888 | } | |
3889 | \f | |
3890 | ||
fc338970 MK |
3891 | /* We have two flavours of disassembly. The machinery on this page |
3892 | deals with switching between those. */ | |
c906108c SS |
3893 | |
3894 | static int | |
a89aa300 | 3895 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3896 | { |
5e3397bb MK |
3897 | gdb_assert (disassembly_flavor == att_flavor |
3898 | || disassembly_flavor == intel_flavor); | |
3899 | ||
3900 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3901 | constified, cast to prevent a compiler warning. */ | |
3902 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3903 | |
3904 | return print_insn_i386 (pc, info); | |
7a292a7a | 3905 | } |
fc338970 | 3906 | \f |
3ce1502b | 3907 | |
8201327c MK |
3908 | /* There are a few i386 architecture variants that differ only |
3909 | slightly from the generic i386 target. For now, we don't give them | |
3910 | their own source file, but include them here. As a consequence, | |
3911 | they'll always be included. */ | |
3ce1502b | 3912 | |
8201327c | 3913 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3914 | |
10458914 DJ |
3915 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3916 | routine. */ | |
911bc6ee | 3917 | |
8201327c | 3918 | static int |
10458914 | 3919 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3920 | { |
10458914 | 3921 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3922 | const char *name; |
911bc6ee | 3923 | |
05b4bd79 | 3924 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3925 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3926 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
3927 | || strcmp ("sigvechandler", name) == 0)); |
3928 | } | |
d2a7c97a | 3929 | |
10458914 DJ |
3930 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3931 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3932 | |
3a1e71e3 | 3933 | static CORE_ADDR |
10458914 | 3934 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3935 | { |
e17a4113 UW |
3936 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3937 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3938 | gdb_byte buf[4]; |
acd5c798 | 3939 | CORE_ADDR sp; |
3ce1502b | 3940 | |
10458914 | 3941 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3942 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3943 | |
e17a4113 | 3944 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3945 | } |
55aa24fb SDJ |
3946 | |
3947 | \f | |
3948 | ||
3949 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3950 | gdbarch.h. */ | |
3951 | ||
3952 | int | |
3953 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3954 | { | |
3955 | return (*s == '$' /* Literal number. */ | |
3956 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3957 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3958 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3959 | } | |
3960 | ||
5acfdbae SDJ |
3961 | /* Helper function for i386_stap_parse_special_token. |
3962 | ||
3963 | This function parses operands of the form `-8+3+1(%rbp)', which | |
3964 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
3965 | ||
3966 | Return 1 if the operand was parsed successfully, zero | |
3967 | otherwise. */ | |
3968 | ||
3969 | static int | |
3970 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
3971 | struct stap_parse_info *p) | |
3972 | { | |
3973 | const char *s = p->arg; | |
3974 | ||
3975 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3976 | { | |
3977 | int got_minus[3]; | |
3978 | int i; | |
3979 | long displacements[3]; | |
3980 | const char *start; | |
3981 | char *regname; | |
3982 | int len; | |
3983 | struct stoken str; | |
3984 | char *endp; | |
3985 | ||
3986 | got_minus[0] = 0; | |
3987 | if (*s == '+') | |
3988 | ++s; | |
3989 | else if (*s == '-') | |
3990 | { | |
3991 | ++s; | |
3992 | got_minus[0] = 1; | |
3993 | } | |
3994 | ||
d7b30f67 SDJ |
3995 | if (!isdigit ((unsigned char) *s)) |
3996 | return 0; | |
3997 | ||
5acfdbae SDJ |
3998 | displacements[0] = strtol (s, &endp, 10); |
3999 | s = endp; | |
4000 | ||
4001 | if (*s != '+' && *s != '-') | |
4002 | { | |
4003 | /* We are not dealing with a triplet. */ | |
4004 | return 0; | |
4005 | } | |
4006 | ||
4007 | got_minus[1] = 0; | |
4008 | if (*s == '+') | |
4009 | ++s; | |
4010 | else | |
4011 | { | |
4012 | ++s; | |
4013 | got_minus[1] = 1; | |
4014 | } | |
4015 | ||
d7b30f67 SDJ |
4016 | if (!isdigit ((unsigned char) *s)) |
4017 | return 0; | |
4018 | ||
5acfdbae SDJ |
4019 | displacements[1] = strtol (s, &endp, 10); |
4020 | s = endp; | |
4021 | ||
4022 | if (*s != '+' && *s != '-') | |
4023 | { | |
4024 | /* We are not dealing with a triplet. */ | |
4025 | return 0; | |
4026 | } | |
4027 | ||
4028 | got_minus[2] = 0; | |
4029 | if (*s == '+') | |
4030 | ++s; | |
4031 | else | |
4032 | { | |
4033 | ++s; | |
4034 | got_minus[2] = 1; | |
4035 | } | |
4036 | ||
d7b30f67 SDJ |
4037 | if (!isdigit ((unsigned char) *s)) |
4038 | return 0; | |
4039 | ||
5acfdbae SDJ |
4040 | displacements[2] = strtol (s, &endp, 10); |
4041 | s = endp; | |
4042 | ||
4043 | if (*s != '(' || s[1] != '%') | |
4044 | return 0; | |
4045 | ||
4046 | s += 2; | |
4047 | start = s; | |
4048 | ||
4049 | while (isalnum (*s)) | |
4050 | ++s; | |
4051 | ||
4052 | if (*s++ != ')') | |
4053 | return 0; | |
4054 | ||
d7b30f67 | 4055 | len = s - start - 1; |
5acfdbae SDJ |
4056 | regname = alloca (len + 1); |
4057 | ||
4058 | strncpy (regname, start, len); | |
4059 | regname[len] = '\0'; | |
4060 | ||
4061 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4062 | error (_("Invalid register name `%s' on expression `%s'."), | |
4063 | regname, p->saved_arg); | |
4064 | ||
4065 | for (i = 0; i < 3; i++) | |
4066 | { | |
410a0ff2 SDJ |
4067 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4068 | write_exp_elt_type | |
4069 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4070 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4071 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4072 | if (got_minus[i]) |
410a0ff2 | 4073 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4074 | } |
4075 | ||
410a0ff2 | 4076 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4077 | str.ptr = regname; |
4078 | str.length = len; | |
410a0ff2 SDJ |
4079 | write_exp_string (&p->pstate, str); |
4080 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4081 | |
410a0ff2 SDJ |
4082 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4083 | write_exp_elt_type (&p->pstate, | |
4084 | builtin_type (gdbarch)->builtin_data_ptr); | |
4085 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4086 | |
410a0ff2 SDJ |
4087 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4088 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4089 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4090 | |
410a0ff2 SDJ |
4091 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4092 | write_exp_elt_type (&p->pstate, | |
4093 | lookup_pointer_type (p->arg_type)); | |
4094 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4095 | |
410a0ff2 | 4096 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4097 | |
4098 | p->arg = s; | |
4099 | ||
4100 | return 1; | |
4101 | } | |
4102 | ||
4103 | return 0; | |
4104 | } | |
4105 | ||
4106 | /* Helper function for i386_stap_parse_special_token. | |
4107 | ||
4108 | This function parses operands of the form `register base + | |
4109 | (register index * size) + offset', as represented in | |
4110 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4111 | ||
4112 | Return 1 if the operand was parsed successfully, zero | |
4113 | otherwise. */ | |
4114 | ||
4115 | static int | |
4116 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4117 | struct stap_parse_info *p) | |
4118 | { | |
4119 | const char *s = p->arg; | |
4120 | ||
4121 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4122 | { | |
4123 | int offset_minus = 0; | |
4124 | long offset = 0; | |
4125 | int size_minus = 0; | |
4126 | long size = 0; | |
4127 | const char *start; | |
4128 | char *base; | |
4129 | int len_base; | |
4130 | char *index; | |
4131 | int len_index; | |
4132 | struct stoken base_token, index_token; | |
4133 | ||
4134 | if (*s == '+') | |
4135 | ++s; | |
4136 | else if (*s == '-') | |
4137 | { | |
4138 | ++s; | |
4139 | offset_minus = 1; | |
4140 | } | |
4141 | ||
4142 | if (offset_minus && !isdigit (*s)) | |
4143 | return 0; | |
4144 | ||
4145 | if (isdigit (*s)) | |
4146 | { | |
4147 | char *endp; | |
4148 | ||
4149 | offset = strtol (s, &endp, 10); | |
4150 | s = endp; | |
4151 | } | |
4152 | ||
4153 | if (*s != '(' || s[1] != '%') | |
4154 | return 0; | |
4155 | ||
4156 | s += 2; | |
4157 | start = s; | |
4158 | ||
4159 | while (isalnum (*s)) | |
4160 | ++s; | |
4161 | ||
4162 | if (*s != ',' || s[1] != '%') | |
4163 | return 0; | |
4164 | ||
4165 | len_base = s - start; | |
4166 | base = alloca (len_base + 1); | |
4167 | strncpy (base, start, len_base); | |
4168 | base[len_base] = '\0'; | |
4169 | ||
4170 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4171 | error (_("Invalid register name `%s' on expression `%s'."), | |
4172 | base, p->saved_arg); | |
4173 | ||
4174 | s += 2; | |
4175 | start = s; | |
4176 | ||
4177 | while (isalnum (*s)) | |
4178 | ++s; | |
4179 | ||
4180 | len_index = s - start; | |
4181 | index = alloca (len_index + 1); | |
4182 | strncpy (index, start, len_index); | |
4183 | index[len_index] = '\0'; | |
4184 | ||
4185 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4186 | error (_("Invalid register name `%s' on expression `%s'."), | |
4187 | index, p->saved_arg); | |
4188 | ||
4189 | if (*s != ',' && *s != ')') | |
4190 | return 0; | |
4191 | ||
4192 | if (*s == ',') | |
4193 | { | |
4194 | char *endp; | |
4195 | ||
4196 | ++s; | |
4197 | if (*s == '+') | |
4198 | ++s; | |
4199 | else if (*s == '-') | |
4200 | { | |
4201 | ++s; | |
4202 | size_minus = 1; | |
4203 | } | |
4204 | ||
4205 | size = strtol (s, &endp, 10); | |
4206 | s = endp; | |
4207 | ||
4208 | if (*s != ')') | |
4209 | return 0; | |
4210 | } | |
4211 | ||
4212 | ++s; | |
4213 | ||
4214 | if (offset) | |
4215 | { | |
410a0ff2 SDJ |
4216 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4217 | write_exp_elt_type (&p->pstate, | |
4218 | builtin_type (gdbarch)->builtin_long); | |
4219 | write_exp_elt_longcst (&p->pstate, offset); | |
4220 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4221 | if (offset_minus) |
410a0ff2 | 4222 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4223 | } |
4224 | ||
410a0ff2 | 4225 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4226 | base_token.ptr = base; |
4227 | base_token.length = len_base; | |
410a0ff2 SDJ |
4228 | write_exp_string (&p->pstate, base_token); |
4229 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4230 | |
4231 | if (offset) | |
410a0ff2 | 4232 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4233 | |
410a0ff2 | 4234 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4235 | index_token.ptr = index; |
4236 | index_token.length = len_index; | |
410a0ff2 SDJ |
4237 | write_exp_string (&p->pstate, index_token); |
4238 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4239 | |
4240 | if (size) | |
4241 | { | |
410a0ff2 SDJ |
4242 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4243 | write_exp_elt_type (&p->pstate, | |
4244 | builtin_type (gdbarch)->builtin_long); | |
4245 | write_exp_elt_longcst (&p->pstate, size); | |
4246 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4247 | if (size_minus) |
410a0ff2 SDJ |
4248 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4249 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4250 | } |
4251 | ||
410a0ff2 | 4252 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4253 | |
410a0ff2 SDJ |
4254 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4255 | write_exp_elt_type (&p->pstate, | |
4256 | lookup_pointer_type (p->arg_type)); | |
4257 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4258 | |
410a0ff2 | 4259 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4260 | |
4261 | p->arg = s; | |
4262 | ||
4263 | return 1; | |
4264 | } | |
4265 | ||
4266 | return 0; | |
4267 | } | |
4268 | ||
55aa24fb SDJ |
4269 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4270 | gdbarch.h. */ | |
4271 | ||
4272 | int | |
4273 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4274 | struct stap_parse_info *p) | |
4275 | { | |
55aa24fb SDJ |
4276 | /* In order to parse special tokens, we use a state-machine that go |
4277 | through every known token and try to get a match. */ | |
4278 | enum | |
4279 | { | |
4280 | TRIPLET, | |
4281 | THREE_ARG_DISPLACEMENT, | |
4282 | DONE | |
570dc176 TT |
4283 | }; |
4284 | int current_state; | |
55aa24fb SDJ |
4285 | |
4286 | current_state = TRIPLET; | |
4287 | ||
4288 | /* The special tokens to be parsed here are: | |
4289 | ||
4290 | - `register base + (register index * size) + offset', as represented | |
4291 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4292 | ||
4293 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4294 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4295 | ||
4296 | while (current_state != DONE) | |
4297 | { | |
55aa24fb SDJ |
4298 | switch (current_state) |
4299 | { | |
4300 | case TRIPLET: | |
5acfdbae SDJ |
4301 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4302 | return 1; | |
4303 | break; | |
4304 | ||
55aa24fb | 4305 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4306 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4307 | return 1; | |
4308 | break; | |
55aa24fb SDJ |
4309 | } |
4310 | ||
4311 | /* Advancing to the next state. */ | |
4312 | ++current_state; | |
4313 | } | |
4314 | ||
4315 | return 0; | |
4316 | } | |
4317 | ||
8201327c | 4318 | \f |
3ce1502b | 4319 | |
ac04f72b TT |
4320 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4321 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4322 | ||
4323 | static const char * | |
4324 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4325 | { | |
4326 | return "(x86_64|i.86)"; | |
4327 | } | |
4328 | ||
4329 | \f | |
4330 | ||
8201327c | 4331 | /* Generic ELF. */ |
d2a7c97a | 4332 | |
8201327c MK |
4333 | void |
4334 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4335 | { | |
05c0465e SDJ |
4336 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4337 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4338 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4339 | NULL }; | |
4340 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4341 | NULL }; | |
4342 | ||
c4fc7f1b MK |
4343 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4344 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4345 | |
4346 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4347 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4348 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4349 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4350 | stap_register_indirection_prefixes); | |
4351 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4352 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4353 | set_gdbarch_stap_is_single_operand (gdbarch, |
4354 | i386_stap_is_single_operand); | |
4355 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4356 | i386_stap_parse_special_token); | |
ac04f72b TT |
4357 | |
4358 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
8201327c | 4359 | } |
3ce1502b | 4360 | |
8201327c | 4361 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4362 | |
8201327c MK |
4363 | void |
4364 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4365 | { | |
4366 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4367 | |
8201327c MK |
4368 | /* System V Release 4 uses ELF. */ |
4369 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4370 | |
dfe01d39 | 4371 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4372 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4373 | ||
911bc6ee | 4374 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4375 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4376 | tdep->sc_pc_offset = 36 + 14 * 4; |
4377 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4378 | |
8201327c | 4379 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4380 | } |
4381 | ||
8201327c | 4382 | /* DJGPP. */ |
3ce1502b | 4383 | |
3a1e71e3 | 4384 | static void |
8201327c | 4385 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 4386 | { |
8201327c | 4387 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 4388 | |
911bc6ee MK |
4389 | /* DJGPP doesn't have any special frames for signal handlers. */ |
4390 | tdep->sigtramp_p = NULL; | |
3ce1502b | 4391 | |
8201327c | 4392 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
4393 | |
4394 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
4395 | if (! tdesc_has_registers (info.target_desc)) |
4396 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
4397 | |
4398 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
4399 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
4400 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
4401 | set_gdbarch_sdb_reg_to_regnum. */ | |
4402 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
4403 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
4404 | |
4405 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
ac04f72b TT |
4406 | |
4407 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
3ce1502b | 4408 | } |
8201327c | 4409 | \f |
2acceee2 | 4410 | |
38c968cf AC |
4411 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4412 | and "sse". */ | |
4413 | ||
4414 | static struct reggroup *i386_sse_reggroup; | |
4415 | static struct reggroup *i386_mmx_reggroup; | |
4416 | ||
4417 | static void | |
4418 | i386_init_reggroups (void) | |
4419 | { | |
4420 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4421 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4422 | } | |
4423 | ||
4424 | static void | |
4425 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4426 | { | |
4427 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4428 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4429 | reggroup_add (gdbarch, general_reggroup); | |
4430 | reggroup_add (gdbarch, float_reggroup); | |
4431 | reggroup_add (gdbarch, all_reggroup); | |
4432 | reggroup_add (gdbarch, save_reggroup); | |
4433 | reggroup_add (gdbarch, restore_reggroup); | |
4434 | reggroup_add (gdbarch, vector_reggroup); | |
4435 | reggroup_add (gdbarch, system_reggroup); | |
4436 | } | |
4437 | ||
4438 | int | |
4439 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4440 | struct reggroup *group) | |
4441 | { | |
c131fcee L |
4442 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4443 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4444 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4445 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4446 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
4447 | avx512_p, avx_p, sse_p; | |
acd5c798 | 4448 | |
1ba53b71 L |
4449 | /* Don't include pseudo registers, except for MMX, in any register |
4450 | groups. */ | |
c131fcee | 4451 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4452 | return 0; |
4453 | ||
c131fcee | 4454 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4455 | return 0; |
4456 | ||
c131fcee | 4457 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4458 | return 0; |
4459 | ||
4460 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4461 | if (group == i386_mmx_reggroup) |
4462 | return mmx_regnum_p; | |
1ba53b71 | 4463 | |
c131fcee | 4464 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4465 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4466 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4467 | if (group == i386_sse_reggroup) |
01f9f808 | 4468 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4469 | |
4470 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4471 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4472 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4473 | ||
df7e5265 GB |
4474 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) |
4475 | == X86_XSTATE_AVX512_MASK); | |
4476 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4477 | == X86_XSTATE_AVX_MASK) && !avx512_p; | |
4478 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4479 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; | |
01f9f808 | 4480 | |
38c968cf | 4481 | if (group == vector_reggroup) |
c131fcee | 4482 | return (mmx_regnum_p |
01f9f808 MS |
4483 | || (zmm_regnum_p && avx512_p) |
4484 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4485 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4486 | || mxcsr_regnum_p); | |
1ba53b71 L |
4487 | |
4488 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4489 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4490 | if (group == float_reggroup) |
4491 | return fp_regnum_p; | |
1ba53b71 | 4492 | |
c131fcee L |
4493 | /* For "info reg all", don't include upper YMM registers nor XMM |
4494 | registers when AVX is supported. */ | |
4495 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4496 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4497 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4498 | if (group == all_reggroup |
01f9f808 MS |
4499 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4500 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4501 | || ymmh_regnum_p | |
4502 | || ymmh_avx512_regnum_p | |
4503 | || zmmh_regnum_p)) | |
c131fcee L |
4504 | return 0; |
4505 | ||
1dbcd68c WT |
4506 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4507 | if (group == all_reggroup | |
df7e5265 | 4508 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4509 | return bnd_regnum_p; |
4510 | ||
4511 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4512 | if (group == all_reggroup | |
df7e5265 | 4513 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4514 | return 0; |
4515 | ||
4516 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4517 | if (group == all_reggroup | |
df7e5265 | 4518 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4519 | return mpx_ctrl_regnum_p; |
4520 | ||
38c968cf | 4521 | if (group == general_reggroup) |
1ba53b71 L |
4522 | return (!fp_regnum_p |
4523 | && !mmx_regnum_p | |
c131fcee L |
4524 | && !mxcsr_regnum_p |
4525 | && !xmm_regnum_p | |
01f9f808 | 4526 | && !xmm_avx512_regnum_p |
c131fcee | 4527 | && !ymm_regnum_p |
1dbcd68c | 4528 | && !ymmh_regnum_p |
01f9f808 MS |
4529 | && !ymm_avx512_regnum_p |
4530 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4531 | && !bndr_regnum_p |
4532 | && !bnd_regnum_p | |
01f9f808 MS |
4533 | && !mpx_ctrl_regnum_p |
4534 | && !zmm_regnum_p | |
4535 | && !zmmh_regnum_p); | |
acd5c798 | 4536 | |
38c968cf AC |
4537 | return default_register_reggroup_p (gdbarch, regnum, group); |
4538 | } | |
38c968cf | 4539 | \f |
acd5c798 | 4540 | |
f837910f MK |
4541 | /* Get the ARGIth function argument for the current function. */ |
4542 | ||
42c466d7 | 4543 | static CORE_ADDR |
143985b7 AF |
4544 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4545 | struct type *type) | |
4546 | { | |
e17a4113 UW |
4547 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4548 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4549 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4550 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4551 | } |
4552 | ||
7ad10968 HZ |
4553 | #define PREFIX_REPZ 0x01 |
4554 | #define PREFIX_REPNZ 0x02 | |
4555 | #define PREFIX_LOCK 0x04 | |
4556 | #define PREFIX_DATA 0x08 | |
4557 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4558 | |
7ad10968 HZ |
4559 | /* operand size */ |
4560 | enum | |
4561 | { | |
4562 | OT_BYTE = 0, | |
4563 | OT_WORD, | |
4564 | OT_LONG, | |
cf648174 | 4565 | OT_QUAD, |
a3c4230a | 4566 | OT_DQUAD, |
7ad10968 | 4567 | }; |
473f17b0 | 4568 | |
7ad10968 HZ |
4569 | /* i386 arith/logic operations */ |
4570 | enum | |
4571 | { | |
4572 | OP_ADDL, | |
4573 | OP_ORL, | |
4574 | OP_ADCL, | |
4575 | OP_SBBL, | |
4576 | OP_ANDL, | |
4577 | OP_SUBL, | |
4578 | OP_XORL, | |
4579 | OP_CMPL, | |
4580 | }; | |
5716833c | 4581 | |
7ad10968 HZ |
4582 | struct i386_record_s |
4583 | { | |
cf648174 | 4584 | struct gdbarch *gdbarch; |
7ad10968 | 4585 | struct regcache *regcache; |
df61f520 | 4586 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4587 | CORE_ADDR addr; |
4588 | int aflag; | |
4589 | int dflag; | |
4590 | int override; | |
4591 | uint8_t modrm; | |
4592 | uint8_t mod, reg, rm; | |
4593 | int ot; | |
cf648174 HZ |
4594 | uint8_t rex_x; |
4595 | uint8_t rex_b; | |
4596 | int rip_offset; | |
4597 | int popl_esp_hack; | |
4598 | const int *regmap; | |
7ad10968 | 4599 | }; |
5716833c | 4600 | |
99c1624c PA |
4601 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4602 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4603 | |
7ad10968 HZ |
4604 | static int |
4605 | i386_record_modrm (struct i386_record_s *irp) | |
4606 | { | |
cf648174 | 4607 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4608 | |
4ffa4fc7 PA |
4609 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4610 | return -1; | |
4611 | ||
7ad10968 HZ |
4612 | irp->addr++; |
4613 | irp->mod = (irp->modrm >> 6) & 3; | |
4614 | irp->reg = (irp->modrm >> 3) & 7; | |
4615 | irp->rm = irp->modrm & 7; | |
5716833c | 4616 | |
7ad10968 HZ |
4617 | return 0; |
4618 | } | |
d2a7c97a | 4619 | |
99c1624c PA |
4620 | /* Extract the memory address that the current instruction writes to, |
4621 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4622 | |
7ad10968 | 4623 | static int |
cf648174 | 4624 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4625 | { |
cf648174 | 4626 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4627 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4628 | gdb_byte buf[4]; | |
4629 | ULONGEST offset64; | |
21d0e8a4 | 4630 | |
7ad10968 | 4631 | *addr = 0; |
1e87984a | 4632 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4633 | { |
1e87984a | 4634 | /* 32/64 bits */ |
7ad10968 HZ |
4635 | int havesib = 0; |
4636 | uint8_t scale = 0; | |
648d0c8b | 4637 | uint8_t byte; |
7ad10968 HZ |
4638 | uint8_t index = 0; |
4639 | uint8_t base = irp->rm; | |
896fb97d | 4640 | |
7ad10968 HZ |
4641 | if (base == 4) |
4642 | { | |
4643 | havesib = 1; | |
4ffa4fc7 PA |
4644 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4645 | return -1; | |
7ad10968 | 4646 | irp->addr++; |
648d0c8b MS |
4647 | scale = (byte >> 6) & 3; |
4648 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4649 | base = (byte & 7); | |
7ad10968 | 4650 | } |
cf648174 | 4651 | base |= irp->rex_b; |
21d0e8a4 | 4652 | |
7ad10968 HZ |
4653 | switch (irp->mod) |
4654 | { | |
4655 | case 0: | |
4656 | if ((base & 7) == 5) | |
4657 | { | |
4658 | base = 0xff; | |
4ffa4fc7 PA |
4659 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4660 | return -1; | |
7ad10968 | 4661 | irp->addr += 4; |
60a1502a | 4662 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4663 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4664 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4665 | } |
7ad10968 HZ |
4666 | break; |
4667 | case 1: | |
4ffa4fc7 PA |
4668 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4669 | return -1; | |
7ad10968 | 4670 | irp->addr++; |
60a1502a | 4671 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4672 | break; |
4673 | case 2: | |
4ffa4fc7 PA |
4674 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4675 | return -1; | |
60a1502a | 4676 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4677 | irp->addr += 4; |
4678 | break; | |
4679 | } | |
356a6b3e | 4680 | |
60a1502a | 4681 | offset64 = 0; |
7ad10968 | 4682 | if (base != 0xff) |
cf648174 HZ |
4683 | { |
4684 | if (base == 4 && irp->popl_esp_hack) | |
4685 | *addr += irp->popl_esp_hack; | |
4686 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4687 | &offset64); |
7ad10968 | 4688 | } |
cf648174 HZ |
4689 | if (irp->aflag == 2) |
4690 | { | |
60a1502a | 4691 | *addr += offset64; |
cf648174 HZ |
4692 | } |
4693 | else | |
60a1502a | 4694 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4695 | |
7ad10968 HZ |
4696 | if (havesib && (index != 4 || scale != 0)) |
4697 | { | |
cf648174 | 4698 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4699 | &offset64); |
cf648174 | 4700 | if (irp->aflag == 2) |
60a1502a | 4701 | *addr += offset64 << scale; |
cf648174 | 4702 | else |
60a1502a | 4703 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4704 | } |
e85596e0 L |
4705 | |
4706 | if (!irp->aflag) | |
4707 | { | |
4708 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4709 | address from 32-bit to 64-bit. */ | |
4710 | *addr = (uint32_t) *addr; | |
4711 | } | |
7ad10968 HZ |
4712 | } |
4713 | else | |
4714 | { | |
4715 | /* 16 bits */ | |
4716 | switch (irp->mod) | |
4717 | { | |
4718 | case 0: | |
4719 | if (irp->rm == 6) | |
4720 | { | |
4ffa4fc7 PA |
4721 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4722 | return -1; | |
7ad10968 | 4723 | irp->addr += 2; |
60a1502a | 4724 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4725 | irp->rm = 0; |
4726 | goto no_rm; | |
4727 | } | |
7ad10968 HZ |
4728 | break; |
4729 | case 1: | |
4ffa4fc7 PA |
4730 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4731 | return -1; | |
7ad10968 | 4732 | irp->addr++; |
60a1502a | 4733 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4734 | break; |
4735 | case 2: | |
4ffa4fc7 PA |
4736 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4737 | return -1; | |
7ad10968 | 4738 | irp->addr += 2; |
60a1502a | 4739 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4740 | break; |
4741 | } | |
c4fc7f1b | 4742 | |
7ad10968 HZ |
4743 | switch (irp->rm) |
4744 | { | |
4745 | case 0: | |
cf648174 HZ |
4746 | regcache_raw_read_unsigned (irp->regcache, |
4747 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4748 | &offset64); |
4749 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4750 | regcache_raw_read_unsigned (irp->regcache, |
4751 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4752 | &offset64); |
4753 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4754 | break; |
4755 | case 1: | |
cf648174 HZ |
4756 | regcache_raw_read_unsigned (irp->regcache, |
4757 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4758 | &offset64); |
4759 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4760 | regcache_raw_read_unsigned (irp->regcache, |
4761 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4762 | &offset64); |
4763 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4764 | break; |
4765 | case 2: | |
cf648174 HZ |
4766 | regcache_raw_read_unsigned (irp->regcache, |
4767 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4768 | &offset64); |
4769 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4770 | regcache_raw_read_unsigned (irp->regcache, |
4771 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4772 | &offset64); |
4773 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4774 | break; |
4775 | case 3: | |
cf648174 HZ |
4776 | regcache_raw_read_unsigned (irp->regcache, |
4777 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4778 | &offset64); |
4779 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4780 | regcache_raw_read_unsigned (irp->regcache, |
4781 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4782 | &offset64); |
4783 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4784 | break; |
4785 | case 4: | |
cf648174 HZ |
4786 | regcache_raw_read_unsigned (irp->regcache, |
4787 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4788 | &offset64); |
4789 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4790 | break; |
4791 | case 5: | |
cf648174 HZ |
4792 | regcache_raw_read_unsigned (irp->regcache, |
4793 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4794 | &offset64); |
4795 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4796 | break; |
4797 | case 6: | |
cf648174 HZ |
4798 | regcache_raw_read_unsigned (irp->regcache, |
4799 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4800 | &offset64); |
4801 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4802 | break; |
4803 | case 7: | |
cf648174 HZ |
4804 | regcache_raw_read_unsigned (irp->regcache, |
4805 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4806 | &offset64); |
4807 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4808 | break; |
4809 | } | |
4810 | *addr &= 0xffff; | |
4811 | } | |
c4fc7f1b | 4812 | |
01fe1b41 | 4813 | no_rm: |
7ad10968 HZ |
4814 | return 0; |
4815 | } | |
c4fc7f1b | 4816 | |
99c1624c PA |
4817 | /* Record the address and contents of the memory that will be changed |
4818 | by the current instruction. Return -1 if something goes wrong, 0 | |
4819 | otherwise. */ | |
356a6b3e | 4820 | |
7ad10968 HZ |
4821 | static int |
4822 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4823 | { | |
cf648174 HZ |
4824 | struct gdbarch *gdbarch = irp->gdbarch; |
4825 | uint64_t addr; | |
356a6b3e | 4826 | |
d7877f7e | 4827 | if (irp->override >= 0) |
7ad10968 | 4828 | { |
25ea693b | 4829 | if (record_full_memory_query) |
bb08c432 HZ |
4830 | { |
4831 | int q; | |
4832 | ||
4833 | target_terminal_ours (); | |
4834 | q = yquery (_("\ | |
4835 | Process record ignores the memory change of instruction at address %s\n\ | |
4836 | because it can't get the value of the segment register.\n\ | |
4837 | Do you want to stop the program?"), | |
4838 | paddress (gdbarch, irp->orig_addr)); | |
4839 | target_terminal_inferior (); | |
4840 | if (q) | |
4841 | return -1; | |
4842 | } | |
4843 | ||
7ad10968 HZ |
4844 | return 0; |
4845 | } | |
61113f8b | 4846 | |
7ad10968 HZ |
4847 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4848 | return -1; | |
96297dab | 4849 | |
25ea693b | 4850 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4851 | return -1; |
a62cc96e | 4852 | |
7ad10968 HZ |
4853 | return 0; |
4854 | } | |
b6197528 | 4855 | |
99c1624c PA |
4856 | /* Record the effects of a push operation. Return -1 if something |
4857 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4858 | |
4859 | static int | |
4860 | i386_record_push (struct i386_record_s *irp, int size) | |
4861 | { | |
648d0c8b | 4862 | ULONGEST addr; |
cf648174 | 4863 | |
25ea693b MM |
4864 | if (record_full_arch_list_add_reg (irp->regcache, |
4865 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4866 | return -1; |
4867 | regcache_raw_read_unsigned (irp->regcache, | |
4868 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4869 | &addr); |
25ea693b | 4870 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4871 | return -1; |
4872 | ||
4873 | return 0; | |
4874 | } | |
4875 | ||
0289bdd7 MS |
4876 | |
4877 | /* Defines contents to record. */ | |
4878 | #define I386_SAVE_FPU_REGS 0xfffd | |
4879 | #define I386_SAVE_FPU_ENV 0xfffe | |
4880 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4881 | ||
99c1624c PA |
4882 | /* Record the values of the floating point registers which will be |
4883 | changed by the current instruction. Returns -1 if something is | |
4884 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4885 | |
4886 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4887 | struct i386_record_s *ir, | |
4888 | uint32_t iregnum) | |
4889 | { | |
4890 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4891 | int i; | |
4892 | ||
4893 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4894 | happen. Currently we store st0-st7 registers, but we need not store all | |
4895 | registers all the time, in future we use ftag register and record only | |
4896 | those who are not marked as an empty. */ | |
4897 | ||
4898 | if (I386_SAVE_FPU_REGS == iregnum) | |
4899 | { | |
4900 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4901 | { | |
25ea693b | 4902 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4903 | return -1; |
4904 | } | |
4905 | } | |
4906 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4907 | { | |
4908 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4909 | { | |
25ea693b | 4910 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4911 | return -1; |
4912 | } | |
4913 | } | |
4914 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4915 | { | |
4916 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4917 | { | |
25ea693b | 4918 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4919 | return -1; |
4920 | } | |
4921 | } | |
4922 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4923 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4924 | { | |
25ea693b | 4925 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4926 | return -1; |
4927 | } | |
4928 | else | |
4929 | { | |
4930 | /* Parameter error. */ | |
4931 | return -1; | |
4932 | } | |
4933 | if(I386_SAVE_FPU_ENV != iregnum) | |
4934 | { | |
4935 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4936 | { | |
25ea693b | 4937 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4938 | return -1; |
4939 | } | |
4940 | } | |
4941 | return 0; | |
4942 | } | |
4943 | ||
99c1624c PA |
4944 | /* Parse the current instruction, and record the values of the |
4945 | registers and memory that will be changed by the current | |
4946 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4947 | |
25ea693b MM |
4948 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
4949 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 4950 | |
a6b808b4 | 4951 | int |
7ad10968 | 4952 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4953 | CORE_ADDR input_addr) |
7ad10968 | 4954 | { |
60a1502a | 4955 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4956 | int prefixes = 0; |
580879fc | 4957 | int regnum = 0; |
425b824a | 4958 | uint32_t opcode; |
f4644a3f | 4959 | uint8_t opcode8; |
648d0c8b | 4960 | ULONGEST addr; |
60a1502a | 4961 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4962 | struct i386_record_s ir; |
0289bdd7 | 4963 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4964 | uint8_t rex_w = -1; |
4965 | uint8_t rex_r = 0; | |
7ad10968 | 4966 | |
8408d274 | 4967 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4968 | ir.regcache = regcache; |
648d0c8b MS |
4969 | ir.addr = input_addr; |
4970 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4971 | ir.aflag = 1; |
4972 | ir.dflag = 1; | |
cf648174 HZ |
4973 | ir.override = -1; |
4974 | ir.popl_esp_hack = 0; | |
a3c4230a | 4975 | ir.regmap = tdep->record_regmap; |
cf648174 | 4976 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4977 | |
4978 | if (record_debug > 1) | |
4979 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4980 | "addr = %s\n", |
4981 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4982 | |
4983 | /* prefixes */ | |
4984 | while (1) | |
4985 | { | |
4ffa4fc7 PA |
4986 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
4987 | return -1; | |
7ad10968 | 4988 | ir.addr++; |
425b824a | 4989 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4990 | { |
01fe1b41 | 4991 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4992 | prefixes |= PREFIX_REPZ; |
4993 | break; | |
01fe1b41 | 4994 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4995 | prefixes |= PREFIX_REPNZ; |
4996 | break; | |
01fe1b41 | 4997 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4998 | prefixes |= PREFIX_LOCK; |
4999 | break; | |
01fe1b41 | 5000 | case CS_PREFIX_OPCODE: |
cf648174 | 5001 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5002 | break; |
01fe1b41 | 5003 | case SS_PREFIX_OPCODE: |
cf648174 | 5004 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5005 | break; |
01fe1b41 | 5006 | case DS_PREFIX_OPCODE: |
cf648174 | 5007 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5008 | break; |
01fe1b41 | 5009 | case ES_PREFIX_OPCODE: |
cf648174 | 5010 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5011 | break; |
01fe1b41 | 5012 | case FS_PREFIX_OPCODE: |
cf648174 | 5013 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5014 | break; |
01fe1b41 | 5015 | case GS_PREFIX_OPCODE: |
cf648174 | 5016 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5017 | break; |
01fe1b41 | 5018 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5019 | prefixes |= PREFIX_DATA; |
5020 | break; | |
01fe1b41 | 5021 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5022 | prefixes |= PREFIX_ADDR; |
5023 | break; | |
d691bec7 MS |
5024 | case 0x40: /* i386 inc %eax */ |
5025 | case 0x41: /* i386 inc %ecx */ | |
5026 | case 0x42: /* i386 inc %edx */ | |
5027 | case 0x43: /* i386 inc %ebx */ | |
5028 | case 0x44: /* i386 inc %esp */ | |
5029 | case 0x45: /* i386 inc %ebp */ | |
5030 | case 0x46: /* i386 inc %esi */ | |
5031 | case 0x47: /* i386 inc %edi */ | |
5032 | case 0x48: /* i386 dec %eax */ | |
5033 | case 0x49: /* i386 dec %ecx */ | |
5034 | case 0x4a: /* i386 dec %edx */ | |
5035 | case 0x4b: /* i386 dec %ebx */ | |
5036 | case 0x4c: /* i386 dec %esp */ | |
5037 | case 0x4d: /* i386 dec %ebp */ | |
5038 | case 0x4e: /* i386 dec %esi */ | |
5039 | case 0x4f: /* i386 dec %edi */ | |
5040 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5041 | { |
5042 | /* REX */ | |
425b824a MS |
5043 | rex_w = (opcode8 >> 3) & 1; |
5044 | rex_r = (opcode8 & 0x4) << 1; | |
5045 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5046 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5047 | } |
d691bec7 MS |
5048 | else /* 32 bit target */ |
5049 | goto out_prefixes; | |
cf648174 | 5050 | break; |
7ad10968 HZ |
5051 | default: |
5052 | goto out_prefixes; | |
5053 | break; | |
5054 | } | |
5055 | } | |
01fe1b41 | 5056 | out_prefixes: |
cf648174 HZ |
5057 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5058 | { | |
5059 | ir.dflag = 2; | |
5060 | } | |
5061 | else | |
5062 | { | |
5063 | if (prefixes & PREFIX_DATA) | |
5064 | ir.dflag ^= 1; | |
5065 | } | |
7ad10968 HZ |
5066 | if (prefixes & PREFIX_ADDR) |
5067 | ir.aflag ^= 1; | |
cf648174 HZ |
5068 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5069 | ir.aflag = 2; | |
7ad10968 | 5070 | |
1777feb0 | 5071 | /* Now check op code. */ |
425b824a | 5072 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5073 | reswitch: |
7ad10968 HZ |
5074 | switch (opcode) |
5075 | { | |
5076 | case 0x0f: | |
4ffa4fc7 PA |
5077 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5078 | return -1; | |
7ad10968 | 5079 | ir.addr++; |
a3c4230a | 5080 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5081 | goto reswitch; |
5082 | break; | |
93924b6b | 5083 | |
a38bba38 | 5084 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5085 | case 0x01: |
5086 | case 0x02: | |
5087 | case 0x03: | |
5088 | case 0x04: | |
5089 | case 0x05: | |
5090 | case 0x08: | |
5091 | case 0x09: | |
5092 | case 0x0a: | |
5093 | case 0x0b: | |
5094 | case 0x0c: | |
5095 | case 0x0d: | |
5096 | case 0x10: | |
5097 | case 0x11: | |
5098 | case 0x12: | |
5099 | case 0x13: | |
5100 | case 0x14: | |
5101 | case 0x15: | |
5102 | case 0x18: | |
5103 | case 0x19: | |
5104 | case 0x1a: | |
5105 | case 0x1b: | |
5106 | case 0x1c: | |
5107 | case 0x1d: | |
5108 | case 0x20: | |
5109 | case 0x21: | |
5110 | case 0x22: | |
5111 | case 0x23: | |
5112 | case 0x24: | |
5113 | case 0x25: | |
5114 | case 0x28: | |
5115 | case 0x29: | |
5116 | case 0x2a: | |
5117 | case 0x2b: | |
5118 | case 0x2c: | |
5119 | case 0x2d: | |
5120 | case 0x30: | |
5121 | case 0x31: | |
5122 | case 0x32: | |
5123 | case 0x33: | |
5124 | case 0x34: | |
5125 | case 0x35: | |
5126 | case 0x38: | |
5127 | case 0x39: | |
5128 | case 0x3a: | |
5129 | case 0x3b: | |
5130 | case 0x3c: | |
5131 | case 0x3d: | |
5132 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5133 | { | |
5134 | if ((opcode & 1) == 0) | |
5135 | ir.ot = OT_BYTE; | |
5136 | else | |
5137 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5138 | |
7ad10968 HZ |
5139 | switch ((opcode >> 1) & 3) |
5140 | { | |
a38bba38 | 5141 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5142 | if (i386_record_modrm (&ir)) |
5143 | return -1; | |
5144 | if (ir.mod != 3) | |
5145 | { | |
5146 | if (i386_record_lea_modrm (&ir)) | |
5147 | return -1; | |
5148 | } | |
5149 | else | |
5150 | { | |
cf648174 HZ |
5151 | ir.rm |= ir.rex_b; |
5152 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5153 | ir.rm &= 0x3; |
25ea693b | 5154 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5155 | } |
5156 | break; | |
a38bba38 | 5157 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5158 | if (i386_record_modrm (&ir)) |
5159 | return -1; | |
cf648174 HZ |
5160 | ir.reg |= rex_r; |
5161 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5162 | ir.reg &= 0x3; |
25ea693b | 5163 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5164 | break; |
a38bba38 | 5165 | case 2: /* OP A, Iv */ |
25ea693b | 5166 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5167 | break; |
5168 | } | |
5169 | } | |
25ea693b | 5170 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5171 | break; |
42fdc8df | 5172 | |
a38bba38 | 5173 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5174 | case 0x81: |
5175 | case 0x82: | |
5176 | case 0x83: | |
5177 | if (i386_record_modrm (&ir)) | |
5178 | return -1; | |
8201327c | 5179 | |
7ad10968 HZ |
5180 | if (ir.reg != OP_CMPL) |
5181 | { | |
5182 | if ((opcode & 1) == 0) | |
5183 | ir.ot = OT_BYTE; | |
5184 | else | |
5185 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5186 | |
7ad10968 HZ |
5187 | if (ir.mod != 3) |
5188 | { | |
cf648174 HZ |
5189 | if (opcode == 0x83) |
5190 | ir.rip_offset = 1; | |
5191 | else | |
5192 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5193 | if (i386_record_lea_modrm (&ir)) |
5194 | return -1; | |
5195 | } | |
5196 | else | |
25ea693b | 5197 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5198 | } |
25ea693b | 5199 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5200 | break; |
5e3397bb | 5201 | |
a38bba38 | 5202 | case 0x40: /* inc */ |
7ad10968 HZ |
5203 | case 0x41: |
5204 | case 0x42: | |
5205 | case 0x43: | |
5206 | case 0x44: | |
5207 | case 0x45: | |
5208 | case 0x46: | |
5209 | case 0x47: | |
a38bba38 MS |
5210 | |
5211 | case 0x48: /* dec */ | |
7ad10968 HZ |
5212 | case 0x49: |
5213 | case 0x4a: | |
5214 | case 0x4b: | |
5215 | case 0x4c: | |
5216 | case 0x4d: | |
5217 | case 0x4e: | |
5218 | case 0x4f: | |
a38bba38 | 5219 | |
25ea693b MM |
5220 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5221 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5222 | break; |
acd5c798 | 5223 | |
a38bba38 | 5224 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5225 | case 0xf7: |
5226 | if ((opcode & 1) == 0) | |
5227 | ir.ot = OT_BYTE; | |
5228 | else | |
5229 | ir.ot = ir.dflag + OT_WORD; | |
5230 | if (i386_record_modrm (&ir)) | |
5231 | return -1; | |
acd5c798 | 5232 | |
cf648174 HZ |
5233 | if (ir.mod != 3 && ir.reg == 0) |
5234 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5235 | ||
7ad10968 HZ |
5236 | switch (ir.reg) |
5237 | { | |
a38bba38 | 5238 | case 0: /* test */ |
25ea693b | 5239 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5240 | break; |
a38bba38 MS |
5241 | case 2: /* not */ |
5242 | case 3: /* neg */ | |
7ad10968 HZ |
5243 | if (ir.mod != 3) |
5244 | { | |
5245 | if (i386_record_lea_modrm (&ir)) | |
5246 | return -1; | |
5247 | } | |
5248 | else | |
5249 | { | |
cf648174 HZ |
5250 | ir.rm |= ir.rex_b; |
5251 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5252 | ir.rm &= 0x3; |
25ea693b | 5253 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5254 | } |
a38bba38 | 5255 | if (ir.reg == 3) /* neg */ |
25ea693b | 5256 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5257 | break; |
a38bba38 MS |
5258 | case 4: /* mul */ |
5259 | case 5: /* imul */ | |
5260 | case 6: /* div */ | |
5261 | case 7: /* idiv */ | |
25ea693b | 5262 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5263 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5264 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5265 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5266 | break; |
5267 | default: | |
5268 | ir.addr -= 2; | |
5269 | opcode = opcode << 8 | ir.modrm; | |
5270 | goto no_support; | |
5271 | break; | |
5272 | } | |
5273 | break; | |
5274 | ||
a38bba38 MS |
5275 | case 0xfe: /* GRP4 */ |
5276 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5277 | if (i386_record_modrm (&ir)) |
5278 | return -1; | |
5279 | if (ir.reg >= 2 && opcode == 0xfe) | |
5280 | { | |
5281 | ir.addr -= 2; | |
5282 | opcode = opcode << 8 | ir.modrm; | |
5283 | goto no_support; | |
5284 | } | |
7ad10968 HZ |
5285 | switch (ir.reg) |
5286 | { | |
a38bba38 MS |
5287 | case 0: /* inc */ |
5288 | case 1: /* dec */ | |
cf648174 HZ |
5289 | if ((opcode & 1) == 0) |
5290 | ir.ot = OT_BYTE; | |
5291 | else | |
5292 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5293 | if (ir.mod != 3) |
5294 | { | |
5295 | if (i386_record_lea_modrm (&ir)) | |
5296 | return -1; | |
5297 | } | |
5298 | else | |
5299 | { | |
cf648174 HZ |
5300 | ir.rm |= ir.rex_b; |
5301 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5302 | ir.rm &= 0x3; |
25ea693b | 5303 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5304 | } |
25ea693b | 5305 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5306 | break; |
a38bba38 | 5307 | case 2: /* call */ |
cf648174 HZ |
5308 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5309 | ir.dflag = 2; | |
5310 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5311 | return -1; |
25ea693b | 5312 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5313 | break; |
a38bba38 | 5314 | case 3: /* lcall */ |
25ea693b | 5315 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5316 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5317 | return -1; |
25ea693b | 5318 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5319 | break; |
a38bba38 MS |
5320 | case 4: /* jmp */ |
5321 | case 5: /* ljmp */ | |
25ea693b | 5322 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5323 | break; |
a38bba38 | 5324 | case 6: /* push */ |
cf648174 HZ |
5325 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5326 | ir.dflag = 2; | |
5327 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5328 | return -1; | |
7ad10968 HZ |
5329 | break; |
5330 | default: | |
5331 | ir.addr -= 2; | |
5332 | opcode = opcode << 8 | ir.modrm; | |
5333 | goto no_support; | |
5334 | break; | |
5335 | } | |
5336 | break; | |
5337 | ||
a38bba38 | 5338 | case 0x84: /* test */ |
7ad10968 HZ |
5339 | case 0x85: |
5340 | case 0xa8: | |
5341 | case 0xa9: | |
25ea693b | 5342 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5343 | break; |
5344 | ||
a38bba38 | 5345 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5346 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5347 | break; |
5348 | ||
a38bba38 | 5349 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5350 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5351 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5352 | break; |
5353 | ||
a38bba38 | 5354 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5355 | case 0x69: |
5356 | case 0x6b: | |
5357 | ir.ot = ir.dflag + OT_WORD; | |
5358 | if (i386_record_modrm (&ir)) | |
5359 | return -1; | |
cf648174 HZ |
5360 | if (opcode == 0x69) |
5361 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5362 | else if (opcode == 0x6b) | |
5363 | ir.rip_offset = 1; | |
5364 | ir.reg |= rex_r; | |
5365 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5366 | ir.reg &= 0x3; |
25ea693b MM |
5367 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5368 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5369 | break; |
5370 | ||
a38bba38 | 5371 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5372 | case 0x0fc1: |
5373 | if ((opcode & 1) == 0) | |
5374 | ir.ot = OT_BYTE; | |
5375 | else | |
5376 | ir.ot = ir.dflag + OT_WORD; | |
5377 | if (i386_record_modrm (&ir)) | |
5378 | return -1; | |
cf648174 | 5379 | ir.reg |= rex_r; |
7ad10968 HZ |
5380 | if (ir.mod == 3) |
5381 | { | |
cf648174 | 5382 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5383 | ir.reg &= 0x3; |
25ea693b | 5384 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5385 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5386 | ir.rm &= 0x3; |
25ea693b | 5387 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5388 | } |
5389 | else | |
5390 | { | |
5391 | if (i386_record_lea_modrm (&ir)) | |
5392 | return -1; | |
cf648174 | 5393 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5394 | ir.reg &= 0x3; |
25ea693b | 5395 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5396 | } |
25ea693b | 5397 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5398 | break; |
5399 | ||
a38bba38 | 5400 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5401 | case 0x0fb1: |
5402 | if ((opcode & 1) == 0) | |
5403 | ir.ot = OT_BYTE; | |
5404 | else | |
5405 | ir.ot = ir.dflag + OT_WORD; | |
5406 | if (i386_record_modrm (&ir)) | |
5407 | return -1; | |
5408 | if (ir.mod == 3) | |
5409 | { | |
cf648174 | 5410 | ir.reg |= rex_r; |
25ea693b | 5411 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5412 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5413 | ir.reg &= 0x3; |
25ea693b | 5414 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5415 | } |
5416 | else | |
5417 | { | |
25ea693b | 5418 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5419 | if (i386_record_lea_modrm (&ir)) |
5420 | return -1; | |
5421 | } | |
25ea693b | 5422 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5423 | break; |
5424 | ||
a38bba38 | 5425 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
5426 | if (i386_record_modrm (&ir)) |
5427 | return -1; | |
5428 | if (ir.mod == 3) | |
5429 | { | |
5430 | ir.addr -= 2; | |
5431 | opcode = opcode << 8 | ir.modrm; | |
5432 | goto no_support; | |
5433 | } | |
25ea693b MM |
5434 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5435 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5436 | if (i386_record_lea_modrm (&ir)) |
5437 | return -1; | |
25ea693b | 5438 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5439 | break; |
5440 | ||
a38bba38 | 5441 | case 0x50: /* push */ |
7ad10968 HZ |
5442 | case 0x51: |
5443 | case 0x52: | |
5444 | case 0x53: | |
5445 | case 0x54: | |
5446 | case 0x55: | |
5447 | case 0x56: | |
5448 | case 0x57: | |
5449 | case 0x68: | |
5450 | case 0x6a: | |
cf648174 HZ |
5451 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5452 | ir.dflag = 2; | |
5453 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5454 | return -1; | |
5455 | break; | |
5456 | ||
a38bba38 MS |
5457 | case 0x06: /* push es */ |
5458 | case 0x0e: /* push cs */ | |
5459 | case 0x16: /* push ss */ | |
5460 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5461 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5462 | { | |
5463 | ir.addr -= 1; | |
5464 | goto no_support; | |
5465 | } | |
5466 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5467 | return -1; | |
5468 | break; | |
5469 | ||
a38bba38 MS |
5470 | case 0x0fa0: /* push fs */ |
5471 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5472 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5473 | { | |
5474 | ir.addr -= 2; | |
5475 | goto no_support; | |
5476 | } | |
5477 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5478 | return -1; |
cf648174 HZ |
5479 | break; |
5480 | ||
a38bba38 | 5481 | case 0x60: /* pusha */ |
cf648174 HZ |
5482 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5483 | { | |
5484 | ir.addr -= 1; | |
5485 | goto no_support; | |
5486 | } | |
5487 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5488 | return -1; |
5489 | break; | |
5490 | ||
a38bba38 | 5491 | case 0x58: /* pop */ |
7ad10968 HZ |
5492 | case 0x59: |
5493 | case 0x5a: | |
5494 | case 0x5b: | |
5495 | case 0x5c: | |
5496 | case 0x5d: | |
5497 | case 0x5e: | |
5498 | case 0x5f: | |
25ea693b MM |
5499 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5500 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5501 | break; |
5502 | ||
a38bba38 | 5503 | case 0x61: /* popa */ |
cf648174 HZ |
5504 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5505 | { | |
5506 | ir.addr -= 1; | |
5507 | goto no_support; | |
7ad10968 | 5508 | } |
425b824a MS |
5509 | for (regnum = X86_RECORD_REAX_REGNUM; |
5510 | regnum <= X86_RECORD_REDI_REGNUM; | |
5511 | regnum++) | |
25ea693b | 5512 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5513 | break; |
5514 | ||
a38bba38 | 5515 | case 0x8f: /* pop */ |
cf648174 HZ |
5516 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5517 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5518 | else | |
5519 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5520 | if (i386_record_modrm (&ir)) |
5521 | return -1; | |
5522 | if (ir.mod == 3) | |
25ea693b | 5523 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5524 | else |
5525 | { | |
cf648174 | 5526 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5527 | if (i386_record_lea_modrm (&ir)) |
5528 | return -1; | |
5529 | } | |
25ea693b | 5530 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5531 | break; |
5532 | ||
a38bba38 | 5533 | case 0xc8: /* enter */ |
25ea693b | 5534 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5535 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5536 | ir.dflag = 2; | |
5537 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5538 | return -1; |
5539 | break; | |
5540 | ||
a38bba38 | 5541 | case 0xc9: /* leave */ |
25ea693b MM |
5542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5543 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5544 | break; |
5545 | ||
a38bba38 | 5546 | case 0x07: /* pop es */ |
cf648174 HZ |
5547 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5548 | { | |
5549 | ir.addr -= 1; | |
5550 | goto no_support; | |
5551 | } | |
25ea693b MM |
5552 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5554 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5555 | break; |
5556 | ||
a38bba38 | 5557 | case 0x17: /* pop ss */ |
cf648174 HZ |
5558 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5559 | { | |
5560 | ir.addr -= 1; | |
5561 | goto no_support; | |
5562 | } | |
25ea693b MM |
5563 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5564 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5566 | break; |
5567 | ||
a38bba38 | 5568 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5569 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5570 | { | |
5571 | ir.addr -= 1; | |
5572 | goto no_support; | |
5573 | } | |
25ea693b MM |
5574 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5575 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5576 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5577 | break; |
5578 | ||
a38bba38 | 5579 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5580 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5581 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5582 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5583 | break; |
5584 | ||
a38bba38 | 5585 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5586 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5587 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5588 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5589 | break; |
5590 | ||
a38bba38 | 5591 | case 0x88: /* mov */ |
7ad10968 HZ |
5592 | case 0x89: |
5593 | case 0xc6: | |
5594 | case 0xc7: | |
5595 | if ((opcode & 1) == 0) | |
5596 | ir.ot = OT_BYTE; | |
5597 | else | |
5598 | ir.ot = ir.dflag + OT_WORD; | |
5599 | ||
5600 | if (i386_record_modrm (&ir)) | |
5601 | return -1; | |
5602 | ||
5603 | if (ir.mod != 3) | |
5604 | { | |
cf648174 HZ |
5605 | if (opcode == 0xc6 || opcode == 0xc7) |
5606 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5607 | if (i386_record_lea_modrm (&ir)) |
5608 | return -1; | |
5609 | } | |
5610 | else | |
5611 | { | |
cf648174 HZ |
5612 | if (opcode == 0xc6 || opcode == 0xc7) |
5613 | ir.rm |= ir.rex_b; | |
5614 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5615 | ir.rm &= 0x3; |
25ea693b | 5616 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5617 | } |
7ad10968 | 5618 | break; |
cf648174 | 5619 | |
a38bba38 | 5620 | case 0x8a: /* mov */ |
7ad10968 HZ |
5621 | case 0x8b: |
5622 | if ((opcode & 1) == 0) | |
5623 | ir.ot = OT_BYTE; | |
5624 | else | |
5625 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5626 | if (i386_record_modrm (&ir)) |
5627 | return -1; | |
cf648174 HZ |
5628 | ir.reg |= rex_r; |
5629 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5630 | ir.reg &= 0x3; |
25ea693b | 5631 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5632 | break; |
7ad10968 | 5633 | |
a38bba38 | 5634 | case 0x8c: /* mov seg */ |
cf648174 | 5635 | if (i386_record_modrm (&ir)) |
7ad10968 | 5636 | return -1; |
cf648174 HZ |
5637 | if (ir.reg > 5) |
5638 | { | |
5639 | ir.addr -= 2; | |
5640 | opcode = opcode << 8 | ir.modrm; | |
5641 | goto no_support; | |
5642 | } | |
5643 | ||
5644 | if (ir.mod == 3) | |
25ea693b | 5645 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5646 | else |
5647 | { | |
5648 | ir.ot = OT_WORD; | |
5649 | if (i386_record_lea_modrm (&ir)) | |
5650 | return -1; | |
5651 | } | |
7ad10968 HZ |
5652 | break; |
5653 | ||
a38bba38 | 5654 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5655 | if (i386_record_modrm (&ir)) |
5656 | return -1; | |
7ad10968 HZ |
5657 | switch (ir.reg) |
5658 | { | |
5659 | case 0: | |
425b824a | 5660 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5661 | break; |
5662 | case 2: | |
425b824a | 5663 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5664 | break; |
5665 | case 3: | |
425b824a | 5666 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5667 | break; |
5668 | case 4: | |
425b824a | 5669 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5670 | break; |
5671 | case 5: | |
425b824a | 5672 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5673 | break; |
5674 | default: | |
5675 | ir.addr -= 2; | |
5676 | opcode = opcode << 8 | ir.modrm; | |
5677 | goto no_support; | |
5678 | break; | |
5679 | } | |
25ea693b MM |
5680 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5682 | break; |
5683 | ||
a38bba38 MS |
5684 | case 0x0fb6: /* movzbS */ |
5685 | case 0x0fb7: /* movzwS */ | |
5686 | case 0x0fbe: /* movsbS */ | |
5687 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5688 | if (i386_record_modrm (&ir)) |
5689 | return -1; | |
25ea693b | 5690 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5691 | break; |
5692 | ||
a38bba38 | 5693 | case 0x8d: /* lea */ |
7ad10968 HZ |
5694 | if (i386_record_modrm (&ir)) |
5695 | return -1; | |
5696 | if (ir.mod == 3) | |
5697 | { | |
5698 | ir.addr -= 2; | |
5699 | opcode = opcode << 8 | ir.modrm; | |
5700 | goto no_support; | |
5701 | } | |
7ad10968 | 5702 | ir.ot = ir.dflag; |
cf648174 HZ |
5703 | ir.reg |= rex_r; |
5704 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5705 | ir.reg &= 0x3; |
25ea693b | 5706 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5707 | break; |
5708 | ||
a38bba38 | 5709 | case 0xa0: /* mov EAX */ |
7ad10968 | 5710 | case 0xa1: |
a38bba38 MS |
5711 | |
5712 | case 0xd7: /* xlat */ | |
25ea693b | 5713 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5714 | break; |
5715 | ||
a38bba38 | 5716 | case 0xa2: /* mov EAX */ |
7ad10968 | 5717 | case 0xa3: |
d7877f7e | 5718 | if (ir.override >= 0) |
cf648174 | 5719 | { |
25ea693b | 5720 | if (record_full_memory_query) |
bb08c432 HZ |
5721 | { |
5722 | int q; | |
5723 | ||
5724 | target_terminal_ours (); | |
5725 | q = yquery (_("\ | |
5726 | Process record ignores the memory change of instruction at address %s\n\ | |
5727 | because it can't get the value of the segment register.\n\ | |
5728 | Do you want to stop the program?"), | |
5729 | paddress (gdbarch, ir.orig_addr)); | |
5730 | target_terminal_inferior (); | |
5731 | if (q) | |
5732 | return -1; | |
5733 | } | |
cf648174 HZ |
5734 | } |
5735 | else | |
5736 | { | |
5737 | if ((opcode & 1) == 0) | |
5738 | ir.ot = OT_BYTE; | |
5739 | else | |
5740 | ir.ot = ir.dflag + OT_WORD; | |
5741 | if (ir.aflag == 2) | |
5742 | { | |
4ffa4fc7 PA |
5743 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5744 | return -1; | |
cf648174 | 5745 | ir.addr += 8; |
60a1502a | 5746 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5747 | } |
5748 | else if (ir.aflag) | |
5749 | { | |
4ffa4fc7 PA |
5750 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5751 | return -1; | |
cf648174 | 5752 | ir.addr += 4; |
60a1502a | 5753 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5754 | } |
5755 | else | |
5756 | { | |
4ffa4fc7 PA |
5757 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5758 | return -1; | |
cf648174 | 5759 | ir.addr += 2; |
60a1502a | 5760 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5761 | } |
25ea693b | 5762 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5763 | return -1; |
5764 | } | |
7ad10968 HZ |
5765 | break; |
5766 | ||
a38bba38 | 5767 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5768 | case 0xb1: |
5769 | case 0xb2: | |
5770 | case 0xb3: | |
5771 | case 0xb4: | |
5772 | case 0xb5: | |
5773 | case 0xb6: | |
5774 | case 0xb7: | |
25ea693b MM |
5775 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5776 | ? ((opcode & 0x7) | ir.rex_b) | |
5777 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5778 | break; |
5779 | ||
a38bba38 | 5780 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5781 | case 0xb9: |
5782 | case 0xba: | |
5783 | case 0xbb: | |
5784 | case 0xbc: | |
5785 | case 0xbd: | |
5786 | case 0xbe: | |
5787 | case 0xbf: | |
25ea693b | 5788 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5789 | break; |
5790 | ||
a38bba38 | 5791 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5792 | case 0x92: |
5793 | case 0x93: | |
5794 | case 0x94: | |
5795 | case 0x95: | |
5796 | case 0x96: | |
5797 | case 0x97: | |
25ea693b MM |
5798 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5799 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5800 | break; |
5801 | ||
a38bba38 | 5802 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5803 | case 0x87: |
5804 | if ((opcode & 1) == 0) | |
5805 | ir.ot = OT_BYTE; | |
5806 | else | |
5807 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5808 | if (i386_record_modrm (&ir)) |
5809 | return -1; | |
7ad10968 HZ |
5810 | if (ir.mod == 3) |
5811 | { | |
86839d38 | 5812 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5813 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5814 | ir.rm &= 0x3; | |
25ea693b | 5815 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5816 | } |
5817 | else | |
5818 | { | |
5819 | if (i386_record_lea_modrm (&ir)) | |
5820 | return -1; | |
5821 | } | |
cf648174 HZ |
5822 | ir.reg |= rex_r; |
5823 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5824 | ir.reg &= 0x3; |
25ea693b | 5825 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5826 | break; |
5827 | ||
a38bba38 MS |
5828 | case 0xc4: /* les Gv */ |
5829 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5830 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5831 | { | |
5832 | ir.addr -= 1; | |
5833 | goto no_support; | |
5834 | } | |
d3f323f3 | 5835 | /* FALLTHROUGH */ |
a38bba38 MS |
5836 | case 0x0fb2: /* lss Gv */ |
5837 | case 0x0fb4: /* lfs Gv */ | |
5838 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5839 | if (i386_record_modrm (&ir)) |
5840 | return -1; | |
5841 | if (ir.mod == 3) | |
5842 | { | |
5843 | if (opcode > 0xff) | |
5844 | ir.addr -= 3; | |
5845 | else | |
5846 | ir.addr -= 2; | |
5847 | opcode = opcode << 8 | ir.modrm; | |
5848 | goto no_support; | |
5849 | } | |
7ad10968 HZ |
5850 | switch (opcode) |
5851 | { | |
a38bba38 | 5852 | case 0xc4: /* les Gv */ |
425b824a | 5853 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5854 | break; |
a38bba38 | 5855 | case 0xc5: /* lds Gv */ |
425b824a | 5856 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5857 | break; |
a38bba38 | 5858 | case 0x0fb2: /* lss Gv */ |
425b824a | 5859 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5860 | break; |
a38bba38 | 5861 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5862 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5863 | break; |
a38bba38 | 5864 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5865 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5866 | break; |
5867 | } | |
25ea693b MM |
5868 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5869 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5870 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5871 | break; |
5872 | ||
a38bba38 | 5873 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5874 | case 0xc1: |
5875 | case 0xd0: | |
5876 | case 0xd1: | |
5877 | case 0xd2: | |
5878 | case 0xd3: | |
5879 | if ((opcode & 1) == 0) | |
5880 | ir.ot = OT_BYTE; | |
5881 | else | |
5882 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5883 | if (i386_record_modrm (&ir)) |
5884 | return -1; | |
7ad10968 HZ |
5885 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5886 | { | |
5887 | if (i386_record_lea_modrm (&ir)) | |
5888 | return -1; | |
5889 | } | |
5890 | else | |
5891 | { | |
cf648174 HZ |
5892 | ir.rm |= ir.rex_b; |
5893 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5894 | ir.rm &= 0x3; |
25ea693b | 5895 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5896 | } |
25ea693b | 5897 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5898 | break; |
5899 | ||
5900 | case 0x0fa4: | |
5901 | case 0x0fa5: | |
5902 | case 0x0fac: | |
5903 | case 0x0fad: | |
5904 | if (i386_record_modrm (&ir)) | |
5905 | return -1; | |
5906 | if (ir.mod == 3) | |
5907 | { | |
25ea693b | 5908 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5909 | return -1; |
5910 | } | |
5911 | else | |
5912 | { | |
5913 | if (i386_record_lea_modrm (&ir)) | |
5914 | return -1; | |
5915 | } | |
5916 | break; | |
5917 | ||
a38bba38 | 5918 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5919 | case 0xd9: |
5920 | case 0xda: | |
5921 | case 0xdb: | |
5922 | case 0xdc: | |
5923 | case 0xdd: | |
5924 | case 0xde: | |
5925 | case 0xdf: | |
5926 | if (i386_record_modrm (&ir)) | |
5927 | return -1; | |
5928 | ir.reg |= ((opcode & 7) << 3); | |
5929 | if (ir.mod != 3) | |
5930 | { | |
1777feb0 | 5931 | /* Memory. */ |
955db0c0 | 5932 | uint64_t addr64; |
7ad10968 | 5933 | |
955db0c0 | 5934 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5935 | return -1; |
5936 | switch (ir.reg) | |
5937 | { | |
7ad10968 | 5938 | case 0x02: |
0289bdd7 MS |
5939 | case 0x12: |
5940 | case 0x22: | |
5941 | case 0x32: | |
5942 | /* For fcom, ficom nothing to do. */ | |
5943 | break; | |
7ad10968 | 5944 | case 0x03: |
0289bdd7 MS |
5945 | case 0x13: |
5946 | case 0x23: | |
5947 | case 0x33: | |
5948 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5949 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5950 | return -1; | |
5951 | break; | |
5952 | case 0x00: | |
5953 | case 0x01: | |
7ad10968 HZ |
5954 | case 0x04: |
5955 | case 0x05: | |
5956 | case 0x06: | |
5957 | case 0x07: | |
5958 | case 0x10: | |
5959 | case 0x11: | |
7ad10968 HZ |
5960 | case 0x14: |
5961 | case 0x15: | |
5962 | case 0x16: | |
5963 | case 0x17: | |
5964 | case 0x20: | |
5965 | case 0x21: | |
7ad10968 HZ |
5966 | case 0x24: |
5967 | case 0x25: | |
5968 | case 0x26: | |
5969 | case 0x27: | |
5970 | case 0x30: | |
5971 | case 0x31: | |
7ad10968 HZ |
5972 | case 0x34: |
5973 | case 0x35: | |
5974 | case 0x36: | |
5975 | case 0x37: | |
0289bdd7 MS |
5976 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5977 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5978 | of code, always affects st(0) register. */ | |
5979 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5980 | return -1; | |
7ad10968 HZ |
5981 | break; |
5982 | case 0x08: | |
5983 | case 0x0a: | |
5984 | case 0x0b: | |
5985 | case 0x18: | |
5986 | case 0x19: | |
5987 | case 0x1a: | |
5988 | case 0x1b: | |
0289bdd7 | 5989 | case 0x1d: |
7ad10968 HZ |
5990 | case 0x28: |
5991 | case 0x29: | |
5992 | case 0x2a: | |
5993 | case 0x2b: | |
5994 | case 0x38: | |
5995 | case 0x39: | |
5996 | case 0x3a: | |
5997 | case 0x3b: | |
0289bdd7 MS |
5998 | case 0x3c: |
5999 | case 0x3d: | |
7ad10968 HZ |
6000 | switch (ir.reg & 7) |
6001 | { | |
6002 | case 0: | |
0289bdd7 MS |
6003 | /* Handling fld, fild. */ |
6004 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6005 | return -1; | |
7ad10968 HZ |
6006 | break; |
6007 | case 1: | |
6008 | switch (ir.reg >> 4) | |
6009 | { | |
6010 | case 0: | |
25ea693b | 6011 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6012 | return -1; |
6013 | break; | |
6014 | case 2: | |
25ea693b | 6015 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6016 | return -1; |
6017 | break; | |
6018 | case 3: | |
0289bdd7 | 6019 | break; |
7ad10968 | 6020 | default: |
25ea693b | 6021 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6022 | return -1; |
6023 | break; | |
6024 | } | |
6025 | break; | |
6026 | default: | |
6027 | switch (ir.reg >> 4) | |
6028 | { | |
6029 | case 0: | |
25ea693b | 6030 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6031 | return -1; |
6032 | if (3 == (ir.reg & 7)) | |
6033 | { | |
6034 | /* For fstp m32fp. */ | |
6035 | if (i386_record_floats (gdbarch, &ir, | |
6036 | I386_SAVE_FPU_REGS)) | |
6037 | return -1; | |
6038 | } | |
6039 | break; | |
7ad10968 | 6040 | case 1: |
25ea693b | 6041 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6042 | return -1; |
0289bdd7 MS |
6043 | if ((3 == (ir.reg & 7)) |
6044 | || (5 == (ir.reg & 7)) | |
6045 | || (7 == (ir.reg & 7))) | |
6046 | { | |
6047 | /* For fstp insn. */ | |
6048 | if (i386_record_floats (gdbarch, &ir, | |
6049 | I386_SAVE_FPU_REGS)) | |
6050 | return -1; | |
6051 | } | |
7ad10968 HZ |
6052 | break; |
6053 | case 2: | |
25ea693b | 6054 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6055 | return -1; |
0289bdd7 MS |
6056 | if (3 == (ir.reg & 7)) |
6057 | { | |
6058 | /* For fstp m64fp. */ | |
6059 | if (i386_record_floats (gdbarch, &ir, | |
6060 | I386_SAVE_FPU_REGS)) | |
6061 | return -1; | |
6062 | } | |
7ad10968 HZ |
6063 | break; |
6064 | case 3: | |
0289bdd7 MS |
6065 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6066 | { | |
6067 | /* For fistp, fbld, fild, fbstp. */ | |
6068 | if (i386_record_floats (gdbarch, &ir, | |
6069 | I386_SAVE_FPU_REGS)) | |
6070 | return -1; | |
6071 | } | |
6072 | /* Fall through */ | |
7ad10968 | 6073 | default: |
25ea693b | 6074 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6075 | return -1; |
6076 | break; | |
6077 | } | |
6078 | break; | |
6079 | } | |
6080 | break; | |
6081 | case 0x0c: | |
0289bdd7 MS |
6082 | /* Insn fldenv. */ |
6083 | if (i386_record_floats (gdbarch, &ir, | |
6084 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6085 | return -1; | |
6086 | break; | |
7ad10968 | 6087 | case 0x0d: |
0289bdd7 MS |
6088 | /* Insn fldcw. */ |
6089 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6090 | return -1; | |
6091 | break; | |
7ad10968 | 6092 | case 0x2c: |
0289bdd7 MS |
6093 | /* Insn frstor. */ |
6094 | if (i386_record_floats (gdbarch, &ir, | |
6095 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6096 | return -1; | |
7ad10968 HZ |
6097 | break; |
6098 | case 0x0e: | |
6099 | if (ir.dflag) | |
6100 | { | |
25ea693b | 6101 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6102 | return -1; |
6103 | } | |
6104 | else | |
6105 | { | |
25ea693b | 6106 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6107 | return -1; |
6108 | } | |
6109 | break; | |
6110 | case 0x0f: | |
6111 | case 0x2f: | |
25ea693b | 6112 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6113 | return -1; |
0289bdd7 MS |
6114 | /* Insn fstp, fbstp. */ |
6115 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6116 | return -1; | |
7ad10968 HZ |
6117 | break; |
6118 | case 0x1f: | |
6119 | case 0x3e: | |
25ea693b | 6120 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6121 | return -1; |
6122 | break; | |
6123 | case 0x2e: | |
6124 | if (ir.dflag) | |
6125 | { | |
25ea693b | 6126 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6127 | return -1; |
955db0c0 | 6128 | addr64 += 28; |
7ad10968 HZ |
6129 | } |
6130 | else | |
6131 | { | |
25ea693b | 6132 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6133 | return -1; |
955db0c0 | 6134 | addr64 += 14; |
7ad10968 | 6135 | } |
25ea693b | 6136 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6137 | return -1; |
0289bdd7 MS |
6138 | /* Insn fsave. */ |
6139 | if (i386_record_floats (gdbarch, &ir, | |
6140 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6141 | return -1; | |
7ad10968 HZ |
6142 | break; |
6143 | case 0x3f: | |
25ea693b | 6144 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6145 | return -1; |
0289bdd7 MS |
6146 | /* Insn fistp. */ |
6147 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6148 | return -1; | |
7ad10968 HZ |
6149 | break; |
6150 | default: | |
6151 | ir.addr -= 2; | |
6152 | opcode = opcode << 8 | ir.modrm; | |
6153 | goto no_support; | |
6154 | break; | |
6155 | } | |
6156 | } | |
0289bdd7 MS |
6157 | /* Opcode is an extension of modR/M byte. */ |
6158 | else | |
6159 | { | |
6160 | switch (opcode) | |
6161 | { | |
6162 | case 0xd8: | |
6163 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6164 | return -1; | |
6165 | break; | |
6166 | case 0xd9: | |
6167 | if (0x0c == (ir.modrm >> 4)) | |
6168 | { | |
6169 | if ((ir.modrm & 0x0f) <= 7) | |
6170 | { | |
6171 | if (i386_record_floats (gdbarch, &ir, | |
6172 | I386_SAVE_FPU_REGS)) | |
6173 | return -1; | |
6174 | } | |
6175 | else | |
6176 | { | |
6177 | if (i386_record_floats (gdbarch, &ir, | |
6178 | I387_ST0_REGNUM (tdep))) | |
6179 | return -1; | |
6180 | /* If only st(0) is changing, then we have already | |
6181 | recorded. */ | |
6182 | if ((ir.modrm & 0x0f) - 0x08) | |
6183 | { | |
6184 | if (i386_record_floats (gdbarch, &ir, | |
6185 | I387_ST0_REGNUM (tdep) + | |
6186 | ((ir.modrm & 0x0f) - 0x08))) | |
6187 | return -1; | |
6188 | } | |
6189 | } | |
6190 | } | |
6191 | else | |
6192 | { | |
6193 | switch (ir.modrm) | |
6194 | { | |
6195 | case 0xe0: | |
6196 | case 0xe1: | |
6197 | case 0xf0: | |
6198 | case 0xf5: | |
6199 | case 0xf8: | |
6200 | case 0xfa: | |
6201 | case 0xfc: | |
6202 | case 0xfe: | |
6203 | case 0xff: | |
6204 | if (i386_record_floats (gdbarch, &ir, | |
6205 | I387_ST0_REGNUM (tdep))) | |
6206 | return -1; | |
6207 | break; | |
6208 | case 0xf1: | |
6209 | case 0xf2: | |
6210 | case 0xf3: | |
6211 | case 0xf4: | |
6212 | case 0xf6: | |
6213 | case 0xf7: | |
6214 | case 0xe8: | |
6215 | case 0xe9: | |
6216 | case 0xea: | |
6217 | case 0xeb: | |
6218 | case 0xec: | |
6219 | case 0xed: | |
6220 | case 0xee: | |
6221 | case 0xf9: | |
6222 | case 0xfb: | |
6223 | if (i386_record_floats (gdbarch, &ir, | |
6224 | I386_SAVE_FPU_REGS)) | |
6225 | return -1; | |
6226 | break; | |
6227 | case 0xfd: | |
6228 | if (i386_record_floats (gdbarch, &ir, | |
6229 | I387_ST0_REGNUM (tdep))) | |
6230 | return -1; | |
6231 | if (i386_record_floats (gdbarch, &ir, | |
6232 | I387_ST0_REGNUM (tdep) + 1)) | |
6233 | return -1; | |
6234 | break; | |
6235 | } | |
6236 | } | |
6237 | break; | |
6238 | case 0xda: | |
6239 | if (0xe9 == ir.modrm) | |
6240 | { | |
6241 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6242 | return -1; | |
6243 | } | |
6244 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6245 | { | |
6246 | if (i386_record_floats (gdbarch, &ir, | |
6247 | I387_ST0_REGNUM (tdep))) | |
6248 | return -1; | |
6249 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6250 | { | |
6251 | if (i386_record_floats (gdbarch, &ir, | |
6252 | I387_ST0_REGNUM (tdep) + | |
6253 | (ir.modrm & 0x0f))) | |
6254 | return -1; | |
6255 | } | |
6256 | else if ((ir.modrm & 0x0f) - 0x08) | |
6257 | { | |
6258 | if (i386_record_floats (gdbarch, &ir, | |
6259 | I387_ST0_REGNUM (tdep) + | |
6260 | ((ir.modrm & 0x0f) - 0x08))) | |
6261 | return -1; | |
6262 | } | |
6263 | } | |
6264 | break; | |
6265 | case 0xdb: | |
6266 | if (0xe3 == ir.modrm) | |
6267 | { | |
6268 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6269 | return -1; | |
6270 | } | |
6271 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6272 | { | |
6273 | if (i386_record_floats (gdbarch, &ir, | |
6274 | I387_ST0_REGNUM (tdep))) | |
6275 | return -1; | |
6276 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6277 | { | |
6278 | if (i386_record_floats (gdbarch, &ir, | |
6279 | I387_ST0_REGNUM (tdep) + | |
6280 | (ir.modrm & 0x0f))) | |
6281 | return -1; | |
6282 | } | |
6283 | else if ((ir.modrm & 0x0f) - 0x08) | |
6284 | { | |
6285 | if (i386_record_floats (gdbarch, &ir, | |
6286 | I387_ST0_REGNUM (tdep) + | |
6287 | ((ir.modrm & 0x0f) - 0x08))) | |
6288 | return -1; | |
6289 | } | |
6290 | } | |
6291 | break; | |
6292 | case 0xdc: | |
6293 | if ((0x0c == ir.modrm >> 4) | |
6294 | || (0x0d == ir.modrm >> 4) | |
6295 | || (0x0f == ir.modrm >> 4)) | |
6296 | { | |
6297 | if ((ir.modrm & 0x0f) <= 7) | |
6298 | { | |
6299 | if (i386_record_floats (gdbarch, &ir, | |
6300 | I387_ST0_REGNUM (tdep) + | |
6301 | (ir.modrm & 0x0f))) | |
6302 | return -1; | |
6303 | } | |
6304 | else | |
6305 | { | |
6306 | if (i386_record_floats (gdbarch, &ir, | |
6307 | I387_ST0_REGNUM (tdep) + | |
6308 | ((ir.modrm & 0x0f) - 0x08))) | |
6309 | return -1; | |
6310 | } | |
6311 | } | |
6312 | break; | |
6313 | case 0xdd: | |
6314 | if (0x0c == ir.modrm >> 4) | |
6315 | { | |
6316 | if (i386_record_floats (gdbarch, &ir, | |
6317 | I387_FTAG_REGNUM (tdep))) | |
6318 | return -1; | |
6319 | } | |
6320 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6321 | { | |
6322 | if ((ir.modrm & 0x0f) <= 7) | |
6323 | { | |
6324 | if (i386_record_floats (gdbarch, &ir, | |
6325 | I387_ST0_REGNUM (tdep) + | |
6326 | (ir.modrm & 0x0f))) | |
6327 | return -1; | |
6328 | } | |
6329 | else | |
6330 | { | |
6331 | if (i386_record_floats (gdbarch, &ir, | |
6332 | I386_SAVE_FPU_REGS)) | |
6333 | return -1; | |
6334 | } | |
6335 | } | |
6336 | break; | |
6337 | case 0xde: | |
6338 | if ((0x0c == ir.modrm >> 4) | |
6339 | || (0x0e == ir.modrm >> 4) | |
6340 | || (0x0f == ir.modrm >> 4) | |
6341 | || (0xd9 == ir.modrm)) | |
6342 | { | |
6343 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6344 | return -1; | |
6345 | } | |
6346 | break; | |
6347 | case 0xdf: | |
6348 | if (0xe0 == ir.modrm) | |
6349 | { | |
25ea693b MM |
6350 | if (record_full_arch_list_add_reg (ir.regcache, |
6351 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6352 | return -1; |
6353 | } | |
6354 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6355 | { | |
6356 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6357 | return -1; | |
6358 | } | |
6359 | break; | |
6360 | } | |
6361 | } | |
7ad10968 | 6362 | break; |
7ad10968 | 6363 | /* string ops */ |
a38bba38 | 6364 | case 0xa4: /* movsS */ |
7ad10968 | 6365 | case 0xa5: |
a38bba38 | 6366 | case 0xaa: /* stosS */ |
7ad10968 | 6367 | case 0xab: |
a38bba38 | 6368 | case 0x6c: /* insS */ |
7ad10968 | 6369 | case 0x6d: |
cf648174 | 6370 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6371 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6372 | &addr); |
6373 | if (addr) | |
cf648174 | 6374 | { |
77d7dc92 HZ |
6375 | ULONGEST es, ds; |
6376 | ||
6377 | if ((opcode & 1) == 0) | |
6378 | ir.ot = OT_BYTE; | |
6379 | else | |
6380 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6381 | regcache_raw_read_unsigned (ir.regcache, |
6382 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6383 | &addr); |
77d7dc92 | 6384 | |
d7877f7e HZ |
6385 | regcache_raw_read_unsigned (ir.regcache, |
6386 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6387 | &es); | |
6388 | regcache_raw_read_unsigned (ir.regcache, | |
6389 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6390 | &ds); | |
6391 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6392 | { |
6393 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6394 | if (record_full_memory_query) |
bb08c432 HZ |
6395 | { |
6396 | int q; | |
6397 | ||
6398 | target_terminal_ours (); | |
6399 | q = yquery (_("\ | |
6400 | Process record ignores the memory change of instruction at address %s\n\ | |
6401 | because it can't get the value of the segment register.\n\ | |
6402 | Do you want to stop the program?"), | |
6403 | paddress (gdbarch, ir.orig_addr)); | |
6404 | target_terminal_inferior (); | |
6405 | if (q) | |
6406 | return -1; | |
6407 | } | |
df61f520 HZ |
6408 | } |
6409 | else | |
6410 | { | |
25ea693b | 6411 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6412 | return -1; |
77d7dc92 HZ |
6413 | } |
6414 | ||
6415 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6416 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6417 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6418 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6419 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6420 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6421 | } |
cf648174 | 6422 | break; |
7ad10968 | 6423 | |
a38bba38 | 6424 | case 0xa6: /* cmpsS */ |
cf648174 | 6425 | case 0xa7: |
25ea693b MM |
6426 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6427 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6428 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6429 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6430 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6431 | break; |
6432 | ||
a38bba38 | 6433 | case 0xac: /* lodsS */ |
7ad10968 | 6434 | case 0xad: |
25ea693b MM |
6435 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6436 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6437 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6438 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6440 | break; |
6441 | ||
a38bba38 | 6442 | case 0xae: /* scasS */ |
7ad10968 | 6443 | case 0xaf: |
25ea693b | 6444 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6445 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6446 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6447 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6448 | break; |
6449 | ||
a38bba38 | 6450 | case 0x6e: /* outsS */ |
cf648174 | 6451 | case 0x6f: |
25ea693b | 6452 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6453 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6454 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6455 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6456 | break; |
6457 | ||
a38bba38 | 6458 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6459 | case 0xe5: |
6460 | case 0xec: | |
6461 | case 0xed: | |
25ea693b MM |
6462 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6463 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6464 | break; |
6465 | ||
6466 | case 0xe6: | |
6467 | case 0xe7: | |
6468 | case 0xee: | |
6469 | case 0xef: | |
6470 | break; | |
6471 | ||
6472 | /* control */ | |
a38bba38 MS |
6473 | case 0xc2: /* ret im */ |
6474 | case 0xc3: /* ret */ | |
25ea693b MM |
6475 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6476 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6477 | break; |
6478 | ||
a38bba38 MS |
6479 | case 0xca: /* lret im */ |
6480 | case 0xcb: /* lret */ | |
6481 | case 0xcf: /* iret */ | |
25ea693b MM |
6482 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6483 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6484 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6485 | break; |
6486 | ||
a38bba38 | 6487 | case 0xe8: /* call im */ |
cf648174 HZ |
6488 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6489 | ir.dflag = 2; | |
6490 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6491 | return -1; | |
7ad10968 HZ |
6492 | break; |
6493 | ||
a38bba38 | 6494 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6495 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6496 | { | |
6497 | ir.addr -= 1; | |
6498 | goto no_support; | |
6499 | } | |
25ea693b | 6500 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6501 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6502 | return -1; | |
7ad10968 HZ |
6503 | break; |
6504 | ||
a38bba38 MS |
6505 | case 0xe9: /* jmp im */ |
6506 | case 0xea: /* ljmp im */ | |
6507 | case 0xeb: /* jmp Jb */ | |
6508 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6509 | case 0x71: |
6510 | case 0x72: | |
6511 | case 0x73: | |
6512 | case 0x74: | |
6513 | case 0x75: | |
6514 | case 0x76: | |
6515 | case 0x77: | |
6516 | case 0x78: | |
6517 | case 0x79: | |
6518 | case 0x7a: | |
6519 | case 0x7b: | |
6520 | case 0x7c: | |
6521 | case 0x7d: | |
6522 | case 0x7e: | |
6523 | case 0x7f: | |
a38bba38 | 6524 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6525 | case 0x0f81: |
6526 | case 0x0f82: | |
6527 | case 0x0f83: | |
6528 | case 0x0f84: | |
6529 | case 0x0f85: | |
6530 | case 0x0f86: | |
6531 | case 0x0f87: | |
6532 | case 0x0f88: | |
6533 | case 0x0f89: | |
6534 | case 0x0f8a: | |
6535 | case 0x0f8b: | |
6536 | case 0x0f8c: | |
6537 | case 0x0f8d: | |
6538 | case 0x0f8e: | |
6539 | case 0x0f8f: | |
6540 | break; | |
6541 | ||
a38bba38 | 6542 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6543 | case 0x0f91: |
6544 | case 0x0f92: | |
6545 | case 0x0f93: | |
6546 | case 0x0f94: | |
6547 | case 0x0f95: | |
6548 | case 0x0f96: | |
6549 | case 0x0f97: | |
6550 | case 0x0f98: | |
6551 | case 0x0f99: | |
6552 | case 0x0f9a: | |
6553 | case 0x0f9b: | |
6554 | case 0x0f9c: | |
6555 | case 0x0f9d: | |
6556 | case 0x0f9e: | |
6557 | case 0x0f9f: | |
25ea693b | 6558 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6559 | ir.ot = OT_BYTE; |
6560 | if (i386_record_modrm (&ir)) | |
6561 | return -1; | |
6562 | if (ir.mod == 3) | |
25ea693b MM |
6563 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6564 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6565 | else |
6566 | { | |
6567 | if (i386_record_lea_modrm (&ir)) | |
6568 | return -1; | |
6569 | } | |
6570 | break; | |
6571 | ||
a38bba38 | 6572 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6573 | case 0x0f41: |
6574 | case 0x0f42: | |
6575 | case 0x0f43: | |
6576 | case 0x0f44: | |
6577 | case 0x0f45: | |
6578 | case 0x0f46: | |
6579 | case 0x0f47: | |
6580 | case 0x0f48: | |
6581 | case 0x0f49: | |
6582 | case 0x0f4a: | |
6583 | case 0x0f4b: | |
6584 | case 0x0f4c: | |
6585 | case 0x0f4d: | |
6586 | case 0x0f4e: | |
6587 | case 0x0f4f: | |
6588 | if (i386_record_modrm (&ir)) | |
6589 | return -1; | |
cf648174 | 6590 | ir.reg |= rex_r; |
7ad10968 HZ |
6591 | if (ir.dflag == OT_BYTE) |
6592 | ir.reg &= 0x3; | |
25ea693b | 6593 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6594 | break; |
6595 | ||
6596 | /* flags */ | |
a38bba38 | 6597 | case 0x9c: /* pushf */ |
25ea693b | 6598 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6599 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6600 | ir.dflag = 2; | |
6601 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6602 | return -1; | |
7ad10968 HZ |
6603 | break; |
6604 | ||
a38bba38 | 6605 | case 0x9d: /* popf */ |
25ea693b MM |
6606 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6607 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6608 | break; |
6609 | ||
a38bba38 | 6610 | case 0x9e: /* sahf */ |
cf648174 HZ |
6611 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6612 | { | |
6613 | ir.addr -= 1; | |
6614 | goto no_support; | |
6615 | } | |
d3f323f3 | 6616 | /* FALLTHROUGH */ |
a38bba38 MS |
6617 | case 0xf5: /* cmc */ |
6618 | case 0xf8: /* clc */ | |
6619 | case 0xf9: /* stc */ | |
6620 | case 0xfc: /* cld */ | |
6621 | case 0xfd: /* std */ | |
25ea693b | 6622 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6623 | break; |
6624 | ||
a38bba38 | 6625 | case 0x9f: /* lahf */ |
cf648174 HZ |
6626 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6627 | { | |
6628 | ir.addr -= 1; | |
6629 | goto no_support; | |
6630 | } | |
25ea693b MM |
6631 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6632 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6633 | break; |
6634 | ||
6635 | /* bit operations */ | |
a38bba38 | 6636 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6637 | ir.ot = ir.dflag + OT_WORD; |
6638 | if (i386_record_modrm (&ir)) | |
6639 | return -1; | |
6640 | if (ir.reg < 4) | |
6641 | { | |
cf648174 | 6642 | ir.addr -= 2; |
7ad10968 HZ |
6643 | opcode = opcode << 8 | ir.modrm; |
6644 | goto no_support; | |
6645 | } | |
cf648174 | 6646 | if (ir.reg != 4) |
7ad10968 | 6647 | { |
cf648174 | 6648 | if (ir.mod == 3) |
25ea693b | 6649 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6650 | else |
6651 | { | |
cf648174 | 6652 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6653 | return -1; |
6654 | } | |
6655 | } | |
25ea693b | 6656 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6657 | break; |
6658 | ||
a38bba38 | 6659 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6660 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6661 | break; |
6662 | ||
a38bba38 MS |
6663 | case 0x0fab: /* bts */ |
6664 | case 0x0fb3: /* btr */ | |
6665 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6666 | ir.ot = ir.dflag + OT_WORD; |
6667 | if (i386_record_modrm (&ir)) | |
6668 | return -1; | |
6669 | if (ir.mod == 3) | |
25ea693b | 6670 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6671 | else |
6672 | { | |
955db0c0 MS |
6673 | uint64_t addr64; |
6674 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6675 | return -1; |
6676 | regcache_raw_read_unsigned (ir.regcache, | |
6677 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6678 | &addr); |
cf648174 HZ |
6679 | switch (ir.dflag) |
6680 | { | |
6681 | case 0: | |
648d0c8b | 6682 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6683 | break; |
6684 | case 1: | |
648d0c8b | 6685 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6686 | break; |
6687 | case 2: | |
648d0c8b | 6688 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6689 | break; |
6690 | } | |
25ea693b | 6691 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6692 | return -1; |
6693 | if (i386_record_lea_modrm (&ir)) | |
6694 | return -1; | |
6695 | } | |
25ea693b | 6696 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6697 | break; |
6698 | ||
a38bba38 MS |
6699 | case 0x0fbc: /* bsf */ |
6700 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6701 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6702 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6703 | break; |
6704 | ||
6705 | /* bcd */ | |
a38bba38 MS |
6706 | case 0x27: /* daa */ |
6707 | case 0x2f: /* das */ | |
6708 | case 0x37: /* aaa */ | |
6709 | case 0x3f: /* aas */ | |
6710 | case 0xd4: /* aam */ | |
6711 | case 0xd5: /* aad */ | |
cf648174 HZ |
6712 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6713 | { | |
6714 | ir.addr -= 1; | |
6715 | goto no_support; | |
6716 | } | |
25ea693b MM |
6717 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6718 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6719 | break; |
6720 | ||
6721 | /* misc */ | |
a38bba38 | 6722 | case 0x90: /* nop */ |
7ad10968 HZ |
6723 | if (prefixes & PREFIX_LOCK) |
6724 | { | |
6725 | ir.addr -= 1; | |
6726 | goto no_support; | |
6727 | } | |
6728 | break; | |
6729 | ||
a38bba38 | 6730 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6731 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6732 | return -1; | |
425b824a | 6733 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6734 | ir.addr++; |
6735 | goto reswitch; | |
7ad10968 HZ |
6736 | break; |
6737 | ||
7ad10968 | 6738 | /* XXX */ |
a38bba38 | 6739 | case 0xcc: /* int3 */ |
a3c4230a | 6740 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6741 | "int3.\n")); |
6742 | ir.addr -= 1; | |
6743 | goto no_support; | |
6744 | break; | |
6745 | ||
7ad10968 | 6746 | /* XXX */ |
a38bba38 | 6747 | case 0xcd: /* int */ |
7ad10968 HZ |
6748 | { |
6749 | int ret; | |
425b824a | 6750 | uint8_t interrupt; |
4ffa4fc7 PA |
6751 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6752 | return -1; | |
7ad10968 | 6753 | ir.addr++; |
425b824a | 6754 | if (interrupt != 0x80 |
a3c4230a | 6755 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6756 | { |
a3c4230a | 6757 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6758 | "instruction int 0x%02x.\n"), |
425b824a | 6759 | interrupt); |
7ad10968 HZ |
6760 | ir.addr -= 2; |
6761 | goto no_support; | |
6762 | } | |
a3c4230a | 6763 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6764 | if (ret) |
6765 | return ret; | |
6766 | } | |
6767 | break; | |
6768 | ||
7ad10968 | 6769 | /* XXX */ |
a38bba38 | 6770 | case 0xce: /* into */ |
a3c4230a | 6771 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6772 | "instruction into.\n")); |
6773 | ir.addr -= 1; | |
6774 | goto no_support; | |
6775 | break; | |
6776 | ||
a38bba38 MS |
6777 | case 0xfa: /* cli */ |
6778 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6779 | break; |
6780 | ||
a38bba38 | 6781 | case 0x62: /* bound */ |
a3c4230a | 6782 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6783 | "instruction bound.\n")); |
6784 | ir.addr -= 1; | |
6785 | goto no_support; | |
6786 | break; | |
6787 | ||
a38bba38 | 6788 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6789 | case 0x0fc9: |
6790 | case 0x0fca: | |
6791 | case 0x0fcb: | |
6792 | case 0x0fcc: | |
6793 | case 0x0fcd: | |
6794 | case 0x0fce: | |
6795 | case 0x0fcf: | |
25ea693b | 6796 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6797 | break; |
6798 | ||
a38bba38 | 6799 | case 0xd6: /* salc */ |
cf648174 HZ |
6800 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6801 | { | |
6802 | ir.addr -= 1; | |
6803 | goto no_support; | |
6804 | } | |
25ea693b MM |
6805 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6806 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6807 | break; |
6808 | ||
a38bba38 MS |
6809 | case 0xe0: /* loopnz */ |
6810 | case 0xe1: /* loopz */ | |
6811 | case 0xe2: /* loop */ | |
6812 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6813 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6814 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6815 | break; |
6816 | ||
a38bba38 | 6817 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6818 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6819 | "instruction wrmsr.\n")); |
6820 | ir.addr -= 2; | |
6821 | goto no_support; | |
6822 | break; | |
6823 | ||
a38bba38 | 6824 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6825 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6826 | "instruction rdmsr.\n")); |
6827 | ir.addr -= 2; | |
6828 | goto no_support; | |
6829 | break; | |
6830 | ||
a38bba38 | 6831 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6832 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6833 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6834 | break; |
6835 | ||
a38bba38 | 6836 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6837 | { |
6838 | int ret; | |
cf648174 HZ |
6839 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6840 | { | |
6841 | ir.addr -= 2; | |
6842 | goto no_support; | |
6843 | } | |
a3c4230a | 6844 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6845 | { |
a3c4230a | 6846 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6847 | "instruction sysenter.\n")); |
6848 | ir.addr -= 2; | |
6849 | goto no_support; | |
6850 | } | |
a3c4230a | 6851 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6852 | if (ret) |
6853 | return ret; | |
6854 | } | |
6855 | break; | |
6856 | ||
a38bba38 | 6857 | case 0x0f35: /* sysexit */ |
a3c4230a | 6858 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6859 | "instruction sysexit.\n")); |
6860 | ir.addr -= 2; | |
6861 | goto no_support; | |
6862 | break; | |
6863 | ||
a38bba38 | 6864 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6865 | { |
6866 | int ret; | |
a3c4230a | 6867 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6868 | { |
a3c4230a | 6869 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6870 | "instruction syscall.\n")); |
6871 | ir.addr -= 2; | |
6872 | goto no_support; | |
6873 | } | |
a3c4230a | 6874 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6875 | if (ret) |
6876 | return ret; | |
6877 | } | |
6878 | break; | |
6879 | ||
a38bba38 | 6880 | case 0x0f07: /* sysret */ |
a3c4230a | 6881 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6882 | "instruction sysret.\n")); |
6883 | ir.addr -= 2; | |
6884 | goto no_support; | |
6885 | break; | |
6886 | ||
a38bba38 | 6887 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6888 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6889 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6890 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6891 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6892 | break; |
6893 | ||
a38bba38 | 6894 | case 0xf4: /* hlt */ |
a3c4230a | 6895 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6896 | "instruction hlt.\n")); |
6897 | ir.addr -= 1; | |
6898 | goto no_support; | |
6899 | break; | |
6900 | ||
6901 | case 0x0f00: | |
6902 | if (i386_record_modrm (&ir)) | |
6903 | return -1; | |
6904 | switch (ir.reg) | |
6905 | { | |
a38bba38 MS |
6906 | case 0: /* sldt */ |
6907 | case 1: /* str */ | |
7ad10968 | 6908 | if (ir.mod == 3) |
25ea693b | 6909 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6910 | else |
6911 | { | |
6912 | ir.ot = OT_WORD; | |
6913 | if (i386_record_lea_modrm (&ir)) | |
6914 | return -1; | |
6915 | } | |
6916 | break; | |
a38bba38 MS |
6917 | case 2: /* lldt */ |
6918 | case 3: /* ltr */ | |
7ad10968 | 6919 | break; |
a38bba38 MS |
6920 | case 4: /* verr */ |
6921 | case 5: /* verw */ | |
25ea693b | 6922 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6923 | break; |
6924 | default: | |
6925 | ir.addr -= 3; | |
6926 | opcode = opcode << 8 | ir.modrm; | |
6927 | goto no_support; | |
6928 | break; | |
6929 | } | |
6930 | break; | |
6931 | ||
6932 | case 0x0f01: | |
6933 | if (i386_record_modrm (&ir)) | |
6934 | return -1; | |
6935 | switch (ir.reg) | |
6936 | { | |
a38bba38 | 6937 | case 0: /* sgdt */ |
7ad10968 | 6938 | { |
955db0c0 | 6939 | uint64_t addr64; |
7ad10968 HZ |
6940 | |
6941 | if (ir.mod == 3) | |
6942 | { | |
6943 | ir.addr -= 3; | |
6944 | opcode = opcode << 8 | ir.modrm; | |
6945 | goto no_support; | |
6946 | } | |
d7877f7e | 6947 | if (ir.override >= 0) |
7ad10968 | 6948 | { |
25ea693b | 6949 | if (record_full_memory_query) |
bb08c432 HZ |
6950 | { |
6951 | int q; | |
6952 | ||
6953 | target_terminal_ours (); | |
6954 | q = yquery (_("\ | |
6955 | Process record ignores the memory change of instruction at address %s\n\ | |
6956 | because it can't get the value of the segment register.\n\ | |
6957 | Do you want to stop the program?"), | |
6958 | paddress (gdbarch, ir.orig_addr)); | |
6959 | target_terminal_inferior (); | |
6960 | if (q) | |
6961 | return -1; | |
6962 | } | |
7ad10968 HZ |
6963 | } |
6964 | else | |
6965 | { | |
955db0c0 | 6966 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6967 | return -1; |
25ea693b | 6968 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6969 | return -1; |
955db0c0 | 6970 | addr64 += 2; |
cf648174 HZ |
6971 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6972 | { | |
25ea693b | 6973 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6974 | return -1; |
6975 | } | |
6976 | else | |
6977 | { | |
25ea693b | 6978 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6979 | return -1; |
6980 | } | |
7ad10968 HZ |
6981 | } |
6982 | } | |
6983 | break; | |
6984 | case 1: | |
6985 | if (ir.mod == 3) | |
6986 | { | |
6987 | switch (ir.rm) | |
6988 | { | |
a38bba38 | 6989 | case 0: /* monitor */ |
7ad10968 | 6990 | break; |
a38bba38 | 6991 | case 1: /* mwait */ |
25ea693b | 6992 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6993 | break; |
6994 | default: | |
6995 | ir.addr -= 3; | |
6996 | opcode = opcode << 8 | ir.modrm; | |
6997 | goto no_support; | |
6998 | break; | |
6999 | } | |
7000 | } | |
7001 | else | |
7002 | { | |
7003 | /* sidt */ | |
d7877f7e | 7004 | if (ir.override >= 0) |
7ad10968 | 7005 | { |
25ea693b | 7006 | if (record_full_memory_query) |
bb08c432 HZ |
7007 | { |
7008 | int q; | |
7009 | ||
7010 | target_terminal_ours (); | |
7011 | q = yquery (_("\ | |
7012 | Process record ignores the memory change of instruction at address %s\n\ | |
7013 | because it can't get the value of the segment register.\n\ | |
7014 | Do you want to stop the program?"), | |
7015 | paddress (gdbarch, ir.orig_addr)); | |
7016 | target_terminal_inferior (); | |
7017 | if (q) | |
7018 | return -1; | |
7019 | } | |
7ad10968 HZ |
7020 | } |
7021 | else | |
7022 | { | |
955db0c0 | 7023 | uint64_t addr64; |
7ad10968 | 7024 | |
955db0c0 | 7025 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7026 | return -1; |
25ea693b | 7027 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7028 | return -1; |
955db0c0 | 7029 | addr64 += 2; |
cf648174 HZ |
7030 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7031 | { | |
25ea693b | 7032 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7033 | return -1; |
7034 | } | |
7035 | else | |
7036 | { | |
25ea693b | 7037 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7038 | return -1; |
7039 | } | |
7ad10968 HZ |
7040 | } |
7041 | } | |
7042 | break; | |
a38bba38 | 7043 | case 2: /* lgdt */ |
3800e645 MS |
7044 | if (ir.mod == 3) |
7045 | { | |
7046 | /* xgetbv */ | |
7047 | if (ir.rm == 0) | |
7048 | { | |
25ea693b MM |
7049 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7050 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7051 | break; |
7052 | } | |
7053 | /* xsetbv */ | |
7054 | else if (ir.rm == 1) | |
7055 | break; | |
7056 | } | |
a38bba38 | 7057 | case 3: /* lidt */ |
7ad10968 HZ |
7058 | if (ir.mod == 3) |
7059 | { | |
7060 | ir.addr -= 3; | |
7061 | opcode = opcode << 8 | ir.modrm; | |
7062 | goto no_support; | |
7063 | } | |
7064 | break; | |
a38bba38 | 7065 | case 4: /* smsw */ |
7ad10968 HZ |
7066 | if (ir.mod == 3) |
7067 | { | |
25ea693b | 7068 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7069 | return -1; |
7070 | } | |
7071 | else | |
7072 | { | |
7073 | ir.ot = OT_WORD; | |
7074 | if (i386_record_lea_modrm (&ir)) | |
7075 | return -1; | |
7076 | } | |
25ea693b | 7077 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7078 | break; |
a38bba38 | 7079 | case 6: /* lmsw */ |
25ea693b | 7080 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7081 | break; |
a38bba38 | 7082 | case 7: /* invlpg */ |
cf648174 HZ |
7083 | if (ir.mod == 3) |
7084 | { | |
7085 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7086 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7087 | else |
7088 | { | |
7089 | ir.addr -= 3; | |
7090 | opcode = opcode << 8 | ir.modrm; | |
7091 | goto no_support; | |
7092 | } | |
7093 | } | |
7094 | else | |
25ea693b | 7095 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7096 | break; |
7097 | default: | |
7098 | ir.addr -= 3; | |
7099 | opcode = opcode << 8 | ir.modrm; | |
7100 | goto no_support; | |
7ad10968 HZ |
7101 | break; |
7102 | } | |
7103 | break; | |
7104 | ||
a38bba38 MS |
7105 | case 0x0f08: /* invd */ |
7106 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7107 | break; |
7108 | ||
a38bba38 | 7109 | case 0x63: /* arpl */ |
7ad10968 HZ |
7110 | if (i386_record_modrm (&ir)) |
7111 | return -1; | |
cf648174 HZ |
7112 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7113 | { | |
25ea693b MM |
7114 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7115 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7116 | } |
7ad10968 | 7117 | else |
cf648174 HZ |
7118 | { |
7119 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7120 | if (i386_record_lea_modrm (&ir)) | |
7121 | return -1; | |
7122 | } | |
7123 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7124 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7125 | break; |
7126 | ||
a38bba38 MS |
7127 | case 0x0f02: /* lar */ |
7128 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7129 | if (i386_record_modrm (&ir)) |
7130 | return -1; | |
25ea693b MM |
7131 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7132 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7133 | break; |
7134 | ||
7135 | case 0x0f18: | |
cf648174 HZ |
7136 | if (i386_record_modrm (&ir)) |
7137 | return -1; | |
7138 | if (ir.mod == 3 && ir.reg == 3) | |
7139 | { | |
7140 | ir.addr -= 3; | |
7141 | opcode = opcode << 8 | ir.modrm; | |
7142 | goto no_support; | |
7143 | } | |
7ad10968 HZ |
7144 | break; |
7145 | ||
7ad10968 HZ |
7146 | case 0x0f19: |
7147 | case 0x0f1a: | |
7148 | case 0x0f1b: | |
7149 | case 0x0f1c: | |
7150 | case 0x0f1d: | |
7151 | case 0x0f1e: | |
7152 | case 0x0f1f: | |
a38bba38 | 7153 | /* nop (multi byte) */ |
7ad10968 HZ |
7154 | break; |
7155 | ||
a38bba38 MS |
7156 | case 0x0f20: /* mov reg, crN */ |
7157 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7158 | if (i386_record_modrm (&ir)) |
7159 | return -1; | |
7160 | if ((ir.modrm & 0xc0) != 0xc0) | |
7161 | { | |
cf648174 | 7162 | ir.addr -= 3; |
7ad10968 HZ |
7163 | opcode = opcode << 8 | ir.modrm; |
7164 | goto no_support; | |
7165 | } | |
7166 | switch (ir.reg) | |
7167 | { | |
7168 | case 0: | |
7169 | case 2: | |
7170 | case 3: | |
7171 | case 4: | |
7172 | case 8: | |
7173 | if (opcode & 2) | |
25ea693b | 7174 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7175 | else |
25ea693b | 7176 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7177 | break; |
7178 | default: | |
cf648174 | 7179 | ir.addr -= 3; |
7ad10968 HZ |
7180 | opcode = opcode << 8 | ir.modrm; |
7181 | goto no_support; | |
7182 | break; | |
7183 | } | |
7184 | break; | |
7185 | ||
a38bba38 MS |
7186 | case 0x0f21: /* mov reg, drN */ |
7187 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7188 | if (i386_record_modrm (&ir)) |
7189 | return -1; | |
7190 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7191 | || ir.reg == 5 || ir.reg >= 8) | |
7192 | { | |
cf648174 | 7193 | ir.addr -= 3; |
7ad10968 HZ |
7194 | opcode = opcode << 8 | ir.modrm; |
7195 | goto no_support; | |
7196 | } | |
7197 | if (opcode & 2) | |
25ea693b | 7198 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7199 | else |
25ea693b | 7200 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7201 | break; |
7202 | ||
a38bba38 | 7203 | case 0x0f06: /* clts */ |
25ea693b | 7204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7205 | break; |
7206 | ||
a3c4230a HZ |
7207 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7208 | ||
7209 | case 0x0f0d: /* 3DNow! prefetch */ | |
7210 | break; | |
7211 | ||
7212 | case 0x0f0e: /* 3DNow! femms */ | |
7213 | case 0x0f77: /* emms */ | |
7214 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7215 | goto no_support; | |
25ea693b | 7216 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7217 | break; |
7218 | ||
7219 | case 0x0f0f: /* 3DNow! data */ | |
7220 | if (i386_record_modrm (&ir)) | |
7221 | return -1; | |
4ffa4fc7 PA |
7222 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7223 | return -1; | |
a3c4230a HZ |
7224 | ir.addr++; |
7225 | switch (opcode8) | |
7226 | { | |
7227 | case 0x0c: /* 3DNow! pi2fw */ | |
7228 | case 0x0d: /* 3DNow! pi2fd */ | |
7229 | case 0x1c: /* 3DNow! pf2iw */ | |
7230 | case 0x1d: /* 3DNow! pf2id */ | |
7231 | case 0x8a: /* 3DNow! pfnacc */ | |
7232 | case 0x8e: /* 3DNow! pfpnacc */ | |
7233 | case 0x90: /* 3DNow! pfcmpge */ | |
7234 | case 0x94: /* 3DNow! pfmin */ | |
7235 | case 0x96: /* 3DNow! pfrcp */ | |
7236 | case 0x97: /* 3DNow! pfrsqrt */ | |
7237 | case 0x9a: /* 3DNow! pfsub */ | |
7238 | case 0x9e: /* 3DNow! pfadd */ | |
7239 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7240 | case 0xa4: /* 3DNow! pfmax */ | |
7241 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7242 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7243 | case 0xaa: /* 3DNow! pfsubr */ | |
7244 | case 0xae: /* 3DNow! pfacc */ | |
7245 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7246 | case 0xb4: /* 3DNow! pfmul */ | |
7247 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7248 | case 0xb7: /* 3DNow! pmulhrw */ | |
7249 | case 0xbb: /* 3DNow! pswapd */ | |
7250 | case 0xbf: /* 3DNow! pavgusb */ | |
7251 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7252 | goto no_support_3dnow_data; | |
25ea693b | 7253 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7254 | break; |
7255 | ||
7256 | default: | |
7257 | no_support_3dnow_data: | |
7258 | opcode = (opcode << 8) | opcode8; | |
7259 | goto no_support; | |
7260 | break; | |
7261 | } | |
7262 | break; | |
7263 | ||
7264 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7265 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7266 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7267 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7268 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7269 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7270 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7271 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7272 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7273 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7274 | break; |
7275 | ||
7276 | case 0x0fae: | |
7277 | if (i386_record_modrm (&ir)) | |
7278 | return -1; | |
7279 | switch(ir.reg) | |
7280 | { | |
7281 | case 0: /* fxsave */ | |
7282 | { | |
7283 | uint64_t tmpu64; | |
7284 | ||
25ea693b | 7285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7286 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7287 | return -1; | |
25ea693b | 7288 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7289 | return -1; |
7290 | } | |
7291 | break; | |
7292 | ||
7293 | case 1: /* fxrstor */ | |
7294 | { | |
7295 | int i; | |
7296 | ||
25ea693b | 7297 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7298 | |
7299 | for (i = I387_MM0_REGNUM (tdep); | |
7300 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7301 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7302 | |
7303 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7304 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7305 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7306 | |
7307 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7308 | record_full_arch_list_add_reg (ir.regcache, |
7309 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7310 | |
7311 | for (i = I387_ST0_REGNUM (tdep); | |
7312 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7313 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7314 | |
7315 | for (i = I387_FCTRL_REGNUM (tdep); | |
7316 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7317 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7318 | } |
7319 | break; | |
7320 | ||
7321 | case 2: /* ldmxcsr */ | |
7322 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7323 | goto no_support; | |
25ea693b | 7324 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7325 | break; |
7326 | ||
7327 | case 3: /* stmxcsr */ | |
7328 | ir.ot = OT_LONG; | |
7329 | if (i386_record_lea_modrm (&ir)) | |
7330 | return -1; | |
7331 | break; | |
7332 | ||
7333 | case 5: /* lfence */ | |
7334 | case 6: /* mfence */ | |
7335 | case 7: /* sfence clflush */ | |
7336 | break; | |
7337 | ||
7338 | default: | |
7339 | opcode = (opcode << 8) | ir.modrm; | |
7340 | goto no_support; | |
7341 | break; | |
7342 | } | |
7343 | break; | |
7344 | ||
7345 | case 0x0fc3: /* movnti */ | |
7346 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7347 | if (i386_record_modrm (&ir)) | |
7348 | return -1; | |
7349 | if (ir.mod == 3) | |
7350 | goto no_support; | |
7351 | ir.reg |= rex_r; | |
7352 | if (i386_record_lea_modrm (&ir)) | |
7353 | return -1; | |
7354 | break; | |
7355 | ||
7356 | /* Add prefix to opcode. */ | |
7357 | case 0x0f10: | |
7358 | case 0x0f11: | |
7359 | case 0x0f12: | |
7360 | case 0x0f13: | |
7361 | case 0x0f14: | |
7362 | case 0x0f15: | |
7363 | case 0x0f16: | |
7364 | case 0x0f17: | |
7365 | case 0x0f28: | |
7366 | case 0x0f29: | |
7367 | case 0x0f2a: | |
7368 | case 0x0f2b: | |
7369 | case 0x0f2c: | |
7370 | case 0x0f2d: | |
7371 | case 0x0f2e: | |
7372 | case 0x0f2f: | |
7373 | case 0x0f38: | |
7374 | case 0x0f39: | |
7375 | case 0x0f3a: | |
7376 | case 0x0f50: | |
7377 | case 0x0f51: | |
7378 | case 0x0f52: | |
7379 | case 0x0f53: | |
7380 | case 0x0f54: | |
7381 | case 0x0f55: | |
7382 | case 0x0f56: | |
7383 | case 0x0f57: | |
7384 | case 0x0f58: | |
7385 | case 0x0f59: | |
7386 | case 0x0f5a: | |
7387 | case 0x0f5b: | |
7388 | case 0x0f5c: | |
7389 | case 0x0f5d: | |
7390 | case 0x0f5e: | |
7391 | case 0x0f5f: | |
7392 | case 0x0f60: | |
7393 | case 0x0f61: | |
7394 | case 0x0f62: | |
7395 | case 0x0f63: | |
7396 | case 0x0f64: | |
7397 | case 0x0f65: | |
7398 | case 0x0f66: | |
7399 | case 0x0f67: | |
7400 | case 0x0f68: | |
7401 | case 0x0f69: | |
7402 | case 0x0f6a: | |
7403 | case 0x0f6b: | |
7404 | case 0x0f6c: | |
7405 | case 0x0f6d: | |
7406 | case 0x0f6e: | |
7407 | case 0x0f6f: | |
7408 | case 0x0f70: | |
7409 | case 0x0f71: | |
7410 | case 0x0f72: | |
7411 | case 0x0f73: | |
7412 | case 0x0f74: | |
7413 | case 0x0f75: | |
7414 | case 0x0f76: | |
7415 | case 0x0f7c: | |
7416 | case 0x0f7d: | |
7417 | case 0x0f7e: | |
7418 | case 0x0f7f: | |
7419 | case 0x0fb8: | |
7420 | case 0x0fc2: | |
7421 | case 0x0fc4: | |
7422 | case 0x0fc5: | |
7423 | case 0x0fc6: | |
7424 | case 0x0fd0: | |
7425 | case 0x0fd1: | |
7426 | case 0x0fd2: | |
7427 | case 0x0fd3: | |
7428 | case 0x0fd4: | |
7429 | case 0x0fd5: | |
7430 | case 0x0fd6: | |
7431 | case 0x0fd7: | |
7432 | case 0x0fd8: | |
7433 | case 0x0fd9: | |
7434 | case 0x0fda: | |
7435 | case 0x0fdb: | |
7436 | case 0x0fdc: | |
7437 | case 0x0fdd: | |
7438 | case 0x0fde: | |
7439 | case 0x0fdf: | |
7440 | case 0x0fe0: | |
7441 | case 0x0fe1: | |
7442 | case 0x0fe2: | |
7443 | case 0x0fe3: | |
7444 | case 0x0fe4: | |
7445 | case 0x0fe5: | |
7446 | case 0x0fe6: | |
7447 | case 0x0fe7: | |
7448 | case 0x0fe8: | |
7449 | case 0x0fe9: | |
7450 | case 0x0fea: | |
7451 | case 0x0feb: | |
7452 | case 0x0fec: | |
7453 | case 0x0fed: | |
7454 | case 0x0fee: | |
7455 | case 0x0fef: | |
7456 | case 0x0ff0: | |
7457 | case 0x0ff1: | |
7458 | case 0x0ff2: | |
7459 | case 0x0ff3: | |
7460 | case 0x0ff4: | |
7461 | case 0x0ff5: | |
7462 | case 0x0ff6: | |
7463 | case 0x0ff7: | |
7464 | case 0x0ff8: | |
7465 | case 0x0ff9: | |
7466 | case 0x0ffa: | |
7467 | case 0x0ffb: | |
7468 | case 0x0ffc: | |
7469 | case 0x0ffd: | |
7470 | case 0x0ffe: | |
f9fda3f5 L |
7471 | /* Mask out PREFIX_ADDR. */ |
7472 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7473 | { |
7474 | case PREFIX_REPNZ: | |
7475 | opcode |= 0xf20000; | |
7476 | break; | |
7477 | case PREFIX_DATA: | |
7478 | opcode |= 0x660000; | |
7479 | break; | |
7480 | case PREFIX_REPZ: | |
7481 | opcode |= 0xf30000; | |
7482 | break; | |
7483 | } | |
7484 | reswitch_prefix_add: | |
7485 | switch (opcode) | |
7486 | { | |
7487 | case 0x0f38: | |
7488 | case 0x660f38: | |
7489 | case 0xf20f38: | |
7490 | case 0x0f3a: | |
7491 | case 0x660f3a: | |
4ffa4fc7 PA |
7492 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7493 | return -1; | |
a3c4230a HZ |
7494 | ir.addr++; |
7495 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7496 | goto reswitch_prefix_add; | |
7497 | break; | |
7498 | ||
7499 | case 0x0f10: /* movups */ | |
7500 | case 0x660f10: /* movupd */ | |
7501 | case 0xf30f10: /* movss */ | |
7502 | case 0xf20f10: /* movsd */ | |
7503 | case 0x0f12: /* movlps */ | |
7504 | case 0x660f12: /* movlpd */ | |
7505 | case 0xf30f12: /* movsldup */ | |
7506 | case 0xf20f12: /* movddup */ | |
7507 | case 0x0f14: /* unpcklps */ | |
7508 | case 0x660f14: /* unpcklpd */ | |
7509 | case 0x0f15: /* unpckhps */ | |
7510 | case 0x660f15: /* unpckhpd */ | |
7511 | case 0x0f16: /* movhps */ | |
7512 | case 0x660f16: /* movhpd */ | |
7513 | case 0xf30f16: /* movshdup */ | |
7514 | case 0x0f28: /* movaps */ | |
7515 | case 0x660f28: /* movapd */ | |
7516 | case 0x0f2a: /* cvtpi2ps */ | |
7517 | case 0x660f2a: /* cvtpi2pd */ | |
7518 | case 0xf30f2a: /* cvtsi2ss */ | |
7519 | case 0xf20f2a: /* cvtsi2sd */ | |
7520 | case 0x0f2c: /* cvttps2pi */ | |
7521 | case 0x660f2c: /* cvttpd2pi */ | |
7522 | case 0x0f2d: /* cvtps2pi */ | |
7523 | case 0x660f2d: /* cvtpd2pi */ | |
7524 | case 0x660f3800: /* pshufb */ | |
7525 | case 0x660f3801: /* phaddw */ | |
7526 | case 0x660f3802: /* phaddd */ | |
7527 | case 0x660f3803: /* phaddsw */ | |
7528 | case 0x660f3804: /* pmaddubsw */ | |
7529 | case 0x660f3805: /* phsubw */ | |
7530 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7531 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7532 | case 0x660f3808: /* psignb */ |
7533 | case 0x660f3809: /* psignw */ | |
7534 | case 0x660f380a: /* psignd */ | |
7535 | case 0x660f380b: /* pmulhrsw */ | |
7536 | case 0x660f3810: /* pblendvb */ | |
7537 | case 0x660f3814: /* blendvps */ | |
7538 | case 0x660f3815: /* blendvpd */ | |
7539 | case 0x660f381c: /* pabsb */ | |
7540 | case 0x660f381d: /* pabsw */ | |
7541 | case 0x660f381e: /* pabsd */ | |
7542 | case 0x660f3820: /* pmovsxbw */ | |
7543 | case 0x660f3821: /* pmovsxbd */ | |
7544 | case 0x660f3822: /* pmovsxbq */ | |
7545 | case 0x660f3823: /* pmovsxwd */ | |
7546 | case 0x660f3824: /* pmovsxwq */ | |
7547 | case 0x660f3825: /* pmovsxdq */ | |
7548 | case 0x660f3828: /* pmuldq */ | |
7549 | case 0x660f3829: /* pcmpeqq */ | |
7550 | case 0x660f382a: /* movntdqa */ | |
7551 | case 0x660f3a08: /* roundps */ | |
7552 | case 0x660f3a09: /* roundpd */ | |
7553 | case 0x660f3a0a: /* roundss */ | |
7554 | case 0x660f3a0b: /* roundsd */ | |
7555 | case 0x660f3a0c: /* blendps */ | |
7556 | case 0x660f3a0d: /* blendpd */ | |
7557 | case 0x660f3a0e: /* pblendw */ | |
7558 | case 0x660f3a0f: /* palignr */ | |
7559 | case 0x660f3a20: /* pinsrb */ | |
7560 | case 0x660f3a21: /* insertps */ | |
7561 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7562 | case 0x660f3a40: /* dpps */ | |
7563 | case 0x660f3a41: /* dppd */ | |
7564 | case 0x660f3a42: /* mpsadbw */ | |
7565 | case 0x660f3a60: /* pcmpestrm */ | |
7566 | case 0x660f3a61: /* pcmpestri */ | |
7567 | case 0x660f3a62: /* pcmpistrm */ | |
7568 | case 0x660f3a63: /* pcmpistri */ | |
7569 | case 0x0f51: /* sqrtps */ | |
7570 | case 0x660f51: /* sqrtpd */ | |
7571 | case 0xf20f51: /* sqrtsd */ | |
7572 | case 0xf30f51: /* sqrtss */ | |
7573 | case 0x0f52: /* rsqrtps */ | |
7574 | case 0xf30f52: /* rsqrtss */ | |
7575 | case 0x0f53: /* rcpps */ | |
7576 | case 0xf30f53: /* rcpss */ | |
7577 | case 0x0f54: /* andps */ | |
7578 | case 0x660f54: /* andpd */ | |
7579 | case 0x0f55: /* andnps */ | |
7580 | case 0x660f55: /* andnpd */ | |
7581 | case 0x0f56: /* orps */ | |
7582 | case 0x660f56: /* orpd */ | |
7583 | case 0x0f57: /* xorps */ | |
7584 | case 0x660f57: /* xorpd */ | |
7585 | case 0x0f58: /* addps */ | |
7586 | case 0x660f58: /* addpd */ | |
7587 | case 0xf20f58: /* addsd */ | |
7588 | case 0xf30f58: /* addss */ | |
7589 | case 0x0f59: /* mulps */ | |
7590 | case 0x660f59: /* mulpd */ | |
7591 | case 0xf20f59: /* mulsd */ | |
7592 | case 0xf30f59: /* mulss */ | |
7593 | case 0x0f5a: /* cvtps2pd */ | |
7594 | case 0x660f5a: /* cvtpd2ps */ | |
7595 | case 0xf20f5a: /* cvtsd2ss */ | |
7596 | case 0xf30f5a: /* cvtss2sd */ | |
7597 | case 0x0f5b: /* cvtdq2ps */ | |
7598 | case 0x660f5b: /* cvtps2dq */ | |
7599 | case 0xf30f5b: /* cvttps2dq */ | |
7600 | case 0x0f5c: /* subps */ | |
7601 | case 0x660f5c: /* subpd */ | |
7602 | case 0xf20f5c: /* subsd */ | |
7603 | case 0xf30f5c: /* subss */ | |
7604 | case 0x0f5d: /* minps */ | |
7605 | case 0x660f5d: /* minpd */ | |
7606 | case 0xf20f5d: /* minsd */ | |
7607 | case 0xf30f5d: /* minss */ | |
7608 | case 0x0f5e: /* divps */ | |
7609 | case 0x660f5e: /* divpd */ | |
7610 | case 0xf20f5e: /* divsd */ | |
7611 | case 0xf30f5e: /* divss */ | |
7612 | case 0x0f5f: /* maxps */ | |
7613 | case 0x660f5f: /* maxpd */ | |
7614 | case 0xf20f5f: /* maxsd */ | |
7615 | case 0xf30f5f: /* maxss */ | |
7616 | case 0x660f60: /* punpcklbw */ | |
7617 | case 0x660f61: /* punpcklwd */ | |
7618 | case 0x660f62: /* punpckldq */ | |
7619 | case 0x660f63: /* packsswb */ | |
7620 | case 0x660f64: /* pcmpgtb */ | |
7621 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7622 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7623 | case 0x660f67: /* packuswb */ |
7624 | case 0x660f68: /* punpckhbw */ | |
7625 | case 0x660f69: /* punpckhwd */ | |
7626 | case 0x660f6a: /* punpckhdq */ | |
7627 | case 0x660f6b: /* packssdw */ | |
7628 | case 0x660f6c: /* punpcklqdq */ | |
7629 | case 0x660f6d: /* punpckhqdq */ | |
7630 | case 0x660f6e: /* movd */ | |
7631 | case 0x660f6f: /* movdqa */ | |
7632 | case 0xf30f6f: /* movdqu */ | |
7633 | case 0x660f70: /* pshufd */ | |
7634 | case 0xf20f70: /* pshuflw */ | |
7635 | case 0xf30f70: /* pshufhw */ | |
7636 | case 0x660f74: /* pcmpeqb */ | |
7637 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7638 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7639 | case 0x660f7c: /* haddpd */ |
7640 | case 0xf20f7c: /* haddps */ | |
7641 | case 0x660f7d: /* hsubpd */ | |
7642 | case 0xf20f7d: /* hsubps */ | |
7643 | case 0xf30f7e: /* movq */ | |
7644 | case 0x0fc2: /* cmpps */ | |
7645 | case 0x660fc2: /* cmppd */ | |
7646 | case 0xf20fc2: /* cmpsd */ | |
7647 | case 0xf30fc2: /* cmpss */ | |
7648 | case 0x660fc4: /* pinsrw */ | |
7649 | case 0x0fc6: /* shufps */ | |
7650 | case 0x660fc6: /* shufpd */ | |
7651 | case 0x660fd0: /* addsubpd */ | |
7652 | case 0xf20fd0: /* addsubps */ | |
7653 | case 0x660fd1: /* psrlw */ | |
7654 | case 0x660fd2: /* psrld */ | |
7655 | case 0x660fd3: /* psrlq */ | |
7656 | case 0x660fd4: /* paddq */ | |
7657 | case 0x660fd5: /* pmullw */ | |
7658 | case 0xf30fd6: /* movq2dq */ | |
7659 | case 0x660fd8: /* psubusb */ | |
7660 | case 0x660fd9: /* psubusw */ | |
7661 | case 0x660fda: /* pminub */ | |
7662 | case 0x660fdb: /* pand */ | |
7663 | case 0x660fdc: /* paddusb */ | |
7664 | case 0x660fdd: /* paddusw */ | |
7665 | case 0x660fde: /* pmaxub */ | |
7666 | case 0x660fdf: /* pandn */ | |
7667 | case 0x660fe0: /* pavgb */ | |
7668 | case 0x660fe1: /* psraw */ | |
7669 | case 0x660fe2: /* psrad */ | |
7670 | case 0x660fe3: /* pavgw */ | |
7671 | case 0x660fe4: /* pmulhuw */ | |
7672 | case 0x660fe5: /* pmulhw */ | |
7673 | case 0x660fe6: /* cvttpd2dq */ | |
7674 | case 0xf20fe6: /* cvtpd2dq */ | |
7675 | case 0xf30fe6: /* cvtdq2pd */ | |
7676 | case 0x660fe8: /* psubsb */ | |
7677 | case 0x660fe9: /* psubsw */ | |
7678 | case 0x660fea: /* pminsw */ | |
7679 | case 0x660feb: /* por */ | |
7680 | case 0x660fec: /* paddsb */ | |
7681 | case 0x660fed: /* paddsw */ | |
7682 | case 0x660fee: /* pmaxsw */ | |
7683 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7684 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7685 | case 0x660ff1: /* psllw */ |
7686 | case 0x660ff2: /* pslld */ | |
7687 | case 0x660ff3: /* psllq */ | |
7688 | case 0x660ff4: /* pmuludq */ | |
7689 | case 0x660ff5: /* pmaddwd */ | |
7690 | case 0x660ff6: /* psadbw */ | |
7691 | case 0x660ff8: /* psubb */ | |
7692 | case 0x660ff9: /* psubw */ | |
56d2815c | 7693 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7694 | case 0x660ffb: /* psubq */ |
7695 | case 0x660ffc: /* paddb */ | |
7696 | case 0x660ffd: /* paddw */ | |
56d2815c | 7697 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7698 | if (i386_record_modrm (&ir)) |
7699 | return -1; | |
7700 | ir.reg |= rex_r; | |
c131fcee | 7701 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7702 | goto no_support; |
25ea693b MM |
7703 | record_full_arch_list_add_reg (ir.regcache, |
7704 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7705 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7706 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7707 | break; |
7708 | ||
7709 | case 0x0f11: /* movups */ | |
7710 | case 0x660f11: /* movupd */ | |
7711 | case 0xf30f11: /* movss */ | |
7712 | case 0xf20f11: /* movsd */ | |
7713 | case 0x0f13: /* movlps */ | |
7714 | case 0x660f13: /* movlpd */ | |
7715 | case 0x0f17: /* movhps */ | |
7716 | case 0x660f17: /* movhpd */ | |
7717 | case 0x0f29: /* movaps */ | |
7718 | case 0x660f29: /* movapd */ | |
7719 | case 0x660f3a14: /* pextrb */ | |
7720 | case 0x660f3a15: /* pextrw */ | |
7721 | case 0x660f3a16: /* pextrd pextrq */ | |
7722 | case 0x660f3a17: /* extractps */ | |
7723 | case 0x660f7f: /* movdqa */ | |
7724 | case 0xf30f7f: /* movdqu */ | |
7725 | if (i386_record_modrm (&ir)) | |
7726 | return -1; | |
7727 | if (ir.mod == 3) | |
7728 | { | |
7729 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7730 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7731 | goto no_support; | |
7732 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7733 | if (!i386_xmm_regnum_p (gdbarch, |
7734 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7735 | goto no_support; |
25ea693b MM |
7736 | record_full_arch_list_add_reg (ir.regcache, |
7737 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7738 | } |
7739 | else | |
7740 | { | |
7741 | switch (opcode) | |
7742 | { | |
7743 | case 0x660f3a14: | |
7744 | ir.ot = OT_BYTE; | |
7745 | break; | |
7746 | case 0x660f3a15: | |
7747 | ir.ot = OT_WORD; | |
7748 | break; | |
7749 | case 0x660f3a16: | |
7750 | ir.ot = OT_LONG; | |
7751 | break; | |
7752 | case 0x660f3a17: | |
7753 | ir.ot = OT_QUAD; | |
7754 | break; | |
7755 | default: | |
7756 | ir.ot = OT_DQUAD; | |
7757 | break; | |
7758 | } | |
7759 | if (i386_record_lea_modrm (&ir)) | |
7760 | return -1; | |
7761 | } | |
7762 | break; | |
7763 | ||
7764 | case 0x0f2b: /* movntps */ | |
7765 | case 0x660f2b: /* movntpd */ | |
7766 | case 0x0fe7: /* movntq */ | |
7767 | case 0x660fe7: /* movntdq */ | |
7768 | if (ir.mod == 3) | |
7769 | goto no_support; | |
7770 | if (opcode == 0x0fe7) | |
7771 | ir.ot = OT_QUAD; | |
7772 | else | |
7773 | ir.ot = OT_DQUAD; | |
7774 | if (i386_record_lea_modrm (&ir)) | |
7775 | return -1; | |
7776 | break; | |
7777 | ||
7778 | case 0xf30f2c: /* cvttss2si */ | |
7779 | case 0xf20f2c: /* cvttsd2si */ | |
7780 | case 0xf30f2d: /* cvtss2si */ | |
7781 | case 0xf20f2d: /* cvtsd2si */ | |
7782 | case 0xf20f38f0: /* crc32 */ | |
7783 | case 0xf20f38f1: /* crc32 */ | |
7784 | case 0x0f50: /* movmskps */ | |
7785 | case 0x660f50: /* movmskpd */ | |
7786 | case 0x0fc5: /* pextrw */ | |
7787 | case 0x660fc5: /* pextrw */ | |
7788 | case 0x0fd7: /* pmovmskb */ | |
7789 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7790 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7791 | break; |
7792 | ||
7793 | case 0x0f3800: /* pshufb */ | |
7794 | case 0x0f3801: /* phaddw */ | |
7795 | case 0x0f3802: /* phaddd */ | |
7796 | case 0x0f3803: /* phaddsw */ | |
7797 | case 0x0f3804: /* pmaddubsw */ | |
7798 | case 0x0f3805: /* phsubw */ | |
7799 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7800 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7801 | case 0x0f3808: /* psignb */ |
7802 | case 0x0f3809: /* psignw */ | |
7803 | case 0x0f380a: /* psignd */ | |
7804 | case 0x0f380b: /* pmulhrsw */ | |
7805 | case 0x0f381c: /* pabsb */ | |
7806 | case 0x0f381d: /* pabsw */ | |
7807 | case 0x0f381e: /* pabsd */ | |
7808 | case 0x0f382b: /* packusdw */ | |
7809 | case 0x0f3830: /* pmovzxbw */ | |
7810 | case 0x0f3831: /* pmovzxbd */ | |
7811 | case 0x0f3832: /* pmovzxbq */ | |
7812 | case 0x0f3833: /* pmovzxwd */ | |
7813 | case 0x0f3834: /* pmovzxwq */ | |
7814 | case 0x0f3835: /* pmovzxdq */ | |
7815 | case 0x0f3837: /* pcmpgtq */ | |
7816 | case 0x0f3838: /* pminsb */ | |
7817 | case 0x0f3839: /* pminsd */ | |
7818 | case 0x0f383a: /* pminuw */ | |
7819 | case 0x0f383b: /* pminud */ | |
7820 | case 0x0f383c: /* pmaxsb */ | |
7821 | case 0x0f383d: /* pmaxsd */ | |
7822 | case 0x0f383e: /* pmaxuw */ | |
7823 | case 0x0f383f: /* pmaxud */ | |
7824 | case 0x0f3840: /* pmulld */ | |
7825 | case 0x0f3841: /* phminposuw */ | |
7826 | case 0x0f3a0f: /* palignr */ | |
7827 | case 0x0f60: /* punpcklbw */ | |
7828 | case 0x0f61: /* punpcklwd */ | |
7829 | case 0x0f62: /* punpckldq */ | |
7830 | case 0x0f63: /* packsswb */ | |
7831 | case 0x0f64: /* pcmpgtb */ | |
7832 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7833 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7834 | case 0x0f67: /* packuswb */ |
7835 | case 0x0f68: /* punpckhbw */ | |
7836 | case 0x0f69: /* punpckhwd */ | |
7837 | case 0x0f6a: /* punpckhdq */ | |
7838 | case 0x0f6b: /* packssdw */ | |
7839 | case 0x0f6e: /* movd */ | |
7840 | case 0x0f6f: /* movq */ | |
7841 | case 0x0f70: /* pshufw */ | |
7842 | case 0x0f74: /* pcmpeqb */ | |
7843 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7844 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7845 | case 0x0fc4: /* pinsrw */ |
7846 | case 0x0fd1: /* psrlw */ | |
7847 | case 0x0fd2: /* psrld */ | |
7848 | case 0x0fd3: /* psrlq */ | |
7849 | case 0x0fd4: /* paddq */ | |
7850 | case 0x0fd5: /* pmullw */ | |
7851 | case 0xf20fd6: /* movdq2q */ | |
7852 | case 0x0fd8: /* psubusb */ | |
7853 | case 0x0fd9: /* psubusw */ | |
7854 | case 0x0fda: /* pminub */ | |
7855 | case 0x0fdb: /* pand */ | |
7856 | case 0x0fdc: /* paddusb */ | |
7857 | case 0x0fdd: /* paddusw */ | |
7858 | case 0x0fde: /* pmaxub */ | |
7859 | case 0x0fdf: /* pandn */ | |
7860 | case 0x0fe0: /* pavgb */ | |
7861 | case 0x0fe1: /* psraw */ | |
7862 | case 0x0fe2: /* psrad */ | |
7863 | case 0x0fe3: /* pavgw */ | |
7864 | case 0x0fe4: /* pmulhuw */ | |
7865 | case 0x0fe5: /* pmulhw */ | |
7866 | case 0x0fe8: /* psubsb */ | |
7867 | case 0x0fe9: /* psubsw */ | |
7868 | case 0x0fea: /* pminsw */ | |
7869 | case 0x0feb: /* por */ | |
7870 | case 0x0fec: /* paddsb */ | |
7871 | case 0x0fed: /* paddsw */ | |
7872 | case 0x0fee: /* pmaxsw */ | |
7873 | case 0x0fef: /* pxor */ | |
7874 | case 0x0ff1: /* psllw */ | |
7875 | case 0x0ff2: /* pslld */ | |
7876 | case 0x0ff3: /* psllq */ | |
7877 | case 0x0ff4: /* pmuludq */ | |
7878 | case 0x0ff5: /* pmaddwd */ | |
7879 | case 0x0ff6: /* psadbw */ | |
7880 | case 0x0ff8: /* psubb */ | |
7881 | case 0x0ff9: /* psubw */ | |
56d2815c | 7882 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7883 | case 0x0ffb: /* psubq */ |
7884 | case 0x0ffc: /* paddb */ | |
7885 | case 0x0ffd: /* paddw */ | |
56d2815c | 7886 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7887 | if (i386_record_modrm (&ir)) |
7888 | return -1; | |
7889 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7890 | goto no_support; | |
25ea693b MM |
7891 | record_full_arch_list_add_reg (ir.regcache, |
7892 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7893 | break; |
7894 | ||
7895 | case 0x0f71: /* psllw */ | |
7896 | case 0x0f72: /* pslld */ | |
7897 | case 0x0f73: /* psllq */ | |
7898 | if (i386_record_modrm (&ir)) | |
7899 | return -1; | |
7900 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7901 | goto no_support; | |
25ea693b MM |
7902 | record_full_arch_list_add_reg (ir.regcache, |
7903 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7904 | break; |
7905 | ||
7906 | case 0x660f71: /* psllw */ | |
7907 | case 0x660f72: /* pslld */ | |
7908 | case 0x660f73: /* psllq */ | |
7909 | if (i386_record_modrm (&ir)) | |
7910 | return -1; | |
7911 | ir.rm |= ir.rex_b; | |
c131fcee | 7912 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7913 | goto no_support; |
25ea693b MM |
7914 | record_full_arch_list_add_reg (ir.regcache, |
7915 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7916 | break; |
7917 | ||
7918 | case 0x0f7e: /* movd */ | |
7919 | case 0x660f7e: /* movd */ | |
7920 | if (i386_record_modrm (&ir)) | |
7921 | return -1; | |
7922 | if (ir.mod == 3) | |
25ea693b | 7923 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7924 | else |
7925 | { | |
7926 | if (ir.dflag == 2) | |
7927 | ir.ot = OT_QUAD; | |
7928 | else | |
7929 | ir.ot = OT_LONG; | |
7930 | if (i386_record_lea_modrm (&ir)) | |
7931 | return -1; | |
7932 | } | |
7933 | break; | |
7934 | ||
7935 | case 0x0f7f: /* movq */ | |
7936 | if (i386_record_modrm (&ir)) | |
7937 | return -1; | |
7938 | if (ir.mod == 3) | |
7939 | { | |
7940 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7941 | goto no_support; | |
25ea693b MM |
7942 | record_full_arch_list_add_reg (ir.regcache, |
7943 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7944 | } |
7945 | else | |
7946 | { | |
7947 | ir.ot = OT_QUAD; | |
7948 | if (i386_record_lea_modrm (&ir)) | |
7949 | return -1; | |
7950 | } | |
7951 | break; | |
7952 | ||
7953 | case 0xf30fb8: /* popcnt */ | |
7954 | if (i386_record_modrm (&ir)) | |
7955 | return -1; | |
25ea693b MM |
7956 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7957 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
7958 | break; |
7959 | ||
7960 | case 0x660fd6: /* movq */ | |
7961 | if (i386_record_modrm (&ir)) | |
7962 | return -1; | |
7963 | if (ir.mod == 3) | |
7964 | { | |
7965 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7966 | if (!i386_xmm_regnum_p (gdbarch, |
7967 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7968 | goto no_support; |
25ea693b MM |
7969 | record_full_arch_list_add_reg (ir.regcache, |
7970 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7971 | } |
7972 | else | |
7973 | { | |
7974 | ir.ot = OT_QUAD; | |
7975 | if (i386_record_lea_modrm (&ir)) | |
7976 | return -1; | |
7977 | } | |
7978 | break; | |
7979 | ||
7980 | case 0x660f3817: /* ptest */ | |
7981 | case 0x0f2e: /* ucomiss */ | |
7982 | case 0x660f2e: /* ucomisd */ | |
7983 | case 0x0f2f: /* comiss */ | |
7984 | case 0x660f2f: /* comisd */ | |
25ea693b | 7985 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7986 | break; |
7987 | ||
7988 | case 0x0ff7: /* maskmovq */ | |
7989 | regcache_raw_read_unsigned (ir.regcache, | |
7990 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7991 | &addr); | |
25ea693b | 7992 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
7993 | return -1; |
7994 | break; | |
7995 | ||
7996 | case 0x660ff7: /* maskmovdqu */ | |
7997 | regcache_raw_read_unsigned (ir.regcache, | |
7998 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7999 | &addr); | |
25ea693b | 8000 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8001 | return -1; |
8002 | break; | |
8003 | ||
8004 | default: | |
8005 | goto no_support; | |
8006 | break; | |
8007 | } | |
8008 | break; | |
7ad10968 HZ |
8009 | |
8010 | default: | |
7ad10968 HZ |
8011 | goto no_support; |
8012 | break; | |
8013 | } | |
8014 | ||
cf648174 | 8015 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8016 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8017 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8018 | return -1; |
8019 | ||
8020 | return 0; | |
8021 | ||
01fe1b41 | 8022 | no_support: |
a3c4230a HZ |
8023 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8024 | "at address %s.\n"), | |
8025 | (unsigned int) (opcode), | |
8026 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8027 | return -1; |
8028 | } | |
8029 | ||
cf648174 HZ |
8030 | static const int i386_record_regmap[] = |
8031 | { | |
8032 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8033 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8034 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8035 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8036 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8037 | }; | |
8038 | ||
7a697b8d | 8039 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8040 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8041 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8042 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8043 | middle of the tracepoint jump. On x86, it may be possible to use |
8044 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8045 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8046 | of instruction to replace, and 0 if not, plus an explanatory |
8047 | string. */ | |
8048 | ||
8049 | static int | |
8050 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
8051 | CORE_ADDR addr, int *isize, char **msg) | |
8052 | { | |
8053 | int len, jumplen; | |
8054 | static struct ui_file *gdb_null = NULL; | |
8055 | ||
405f8e94 SS |
8056 | /* Ask the target for the minimum instruction length supported. */ |
8057 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8058 | ||
8059 | if (jumplen < 0) | |
8060 | { | |
8061 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8062 | operation, assume that fast tracepoints will always be implemented | |
8063 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8064 | jumplen = 5; | |
8065 | } | |
8066 | else if (jumplen == 0) | |
8067 | { | |
8068 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8069 | returns zero, then the IPA has not loaded yet. In this case, | |
8070 | we optimistically assume that truncated 2-byte relative jumps | |
8071 | will be available on x86, and compensate later if this assumption | |
8072 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8073 | jumps will always be used. */ | |
8074 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8075 | } | |
7a697b8d SS |
8076 | |
8077 | /* Dummy file descriptor for the disassembler. */ | |
8078 | if (!gdb_null) | |
8079 | gdb_null = ui_file_new (); | |
8080 | ||
8081 | /* Check for fit. */ | |
8082 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
8083 | if (isize) |
8084 | *isize = len; | |
8085 | ||
7a697b8d SS |
8086 | if (len < jumplen) |
8087 | { | |
8088 | /* Return a bit of target-specific detail to add to the caller's | |
8089 | generic failure message. */ | |
8090 | if (msg) | |
1777feb0 MS |
8091 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8092 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8093 | len, jumplen); |
8094 | return 0; | |
8095 | } | |
405f8e94 SS |
8096 | else |
8097 | { | |
8098 | if (msg) | |
8099 | *msg = NULL; | |
8100 | return 1; | |
8101 | } | |
7a697b8d SS |
8102 | } |
8103 | ||
90884b2b L |
8104 | static int |
8105 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8106 | struct tdesc_arch_data *tdesc_data) | |
8107 | { | |
8108 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8109 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8110 | |
8111 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
8112 | *feature_avx512; | |
90884b2b L |
8113 | int i, num_regs, valid_p; |
8114 | ||
8115 | if (! tdesc_has_registers (tdesc)) | |
8116 | return 0; | |
8117 | ||
8118 | /* Get core registers. */ | |
8119 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8120 | if (feature_core == NULL) |
8121 | return 0; | |
90884b2b L |
8122 | |
8123 | /* Get SSE registers. */ | |
c131fcee | 8124 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8125 | |
c131fcee L |
8126 | /* Try AVX registers. */ |
8127 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8128 | ||
1dbcd68c WT |
8129 | /* Try MPX registers. */ |
8130 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8131 | ||
01f9f808 MS |
8132 | /* Try AVX512 registers. */ |
8133 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8134 | ||
90884b2b L |
8135 | valid_p = 1; |
8136 | ||
c131fcee | 8137 | /* The XCR0 bits. */ |
01f9f808 MS |
8138 | if (feature_avx512) |
8139 | { | |
8140 | /* AVX512 register description requires AVX register description. */ | |
8141 | if (!feature_avx) | |
8142 | return 0; | |
8143 | ||
df7e5265 | 8144 | tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK; |
01f9f808 MS |
8145 | |
8146 | /* It may have been set by OSABI initialization function. */ | |
8147 | if (tdep->k0_regnum < 0) | |
8148 | { | |
8149 | tdep->k_register_names = i386_k_names; | |
8150 | tdep->k0_regnum = I386_K0_REGNUM; | |
8151 | } | |
8152 | ||
8153 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8154 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8155 | tdep->k0_regnum + i, | |
8156 | i386_k_names[i]); | |
8157 | ||
8158 | if (tdep->num_zmm_regs == 0) | |
8159 | { | |
8160 | tdep->zmmh_register_names = i386_zmmh_names; | |
8161 | tdep->num_zmm_regs = 8; | |
8162 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8163 | } | |
8164 | ||
8165 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8166 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8167 | tdep->zmm0h_regnum + i, | |
8168 | tdep->zmmh_register_names[i]); | |
8169 | ||
8170 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8171 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8172 | tdep->xmm16_regnum + i, | |
8173 | tdep->xmm_avx512_register_names[i]); | |
8174 | ||
8175 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8176 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8177 | tdep->ymm16h_regnum + i, | |
8178 | tdep->ymm16h_register_names[i]); | |
8179 | } | |
c131fcee L |
8180 | if (feature_avx) |
8181 | { | |
3a13a53b L |
8182 | /* AVX register description requires SSE register description. */ |
8183 | if (!feature_sse) | |
8184 | return 0; | |
8185 | ||
01f9f808 | 8186 | if (!feature_avx512) |
df7e5265 | 8187 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8188 | |
8189 | /* It may have been set by OSABI initialization function. */ | |
8190 | if (tdep->num_ymm_regs == 0) | |
8191 | { | |
8192 | tdep->ymmh_register_names = i386_ymmh_names; | |
8193 | tdep->num_ymm_regs = 8; | |
8194 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8195 | } | |
8196 | ||
8197 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8198 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8199 | tdep->ymm0h_regnum + i, | |
8200 | tdep->ymmh_register_names[i]); | |
8201 | } | |
3a13a53b | 8202 | else if (feature_sse) |
df7e5265 | 8203 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8204 | else |
8205 | { | |
df7e5265 | 8206 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8207 | tdep->num_xmm_regs = 0; |
8208 | } | |
c131fcee | 8209 | |
90884b2b L |
8210 | num_regs = tdep->num_core_regs; |
8211 | for (i = 0; i < num_regs; i++) | |
8212 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8213 | tdep->register_names[i]); | |
8214 | ||
3a13a53b L |
8215 | if (feature_sse) |
8216 | { | |
8217 | /* Need to include %mxcsr, so add one. */ | |
8218 | num_regs += tdep->num_xmm_regs + 1; | |
8219 | for (; i < num_regs; i++) | |
8220 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8221 | tdep->register_names[i]); | |
8222 | } | |
90884b2b | 8223 | |
1dbcd68c WT |
8224 | if (feature_mpx) |
8225 | { | |
df7e5265 | 8226 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8227 | |
8228 | if (tdep->bnd0r_regnum < 0) | |
8229 | { | |
8230 | tdep->mpx_register_names = i386_mpx_names; | |
8231 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8232 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8233 | } | |
8234 | ||
8235 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8236 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8237 | I387_BND0R_REGNUM (tdep) + i, | |
8238 | tdep->mpx_register_names[i]); | |
8239 | } | |
8240 | ||
90884b2b L |
8241 | return valid_p; |
8242 | } | |
8243 | ||
7ad10968 HZ |
8244 | \f |
8245 | static struct gdbarch * | |
8246 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8247 | { | |
8248 | struct gdbarch_tdep *tdep; | |
8249 | struct gdbarch *gdbarch; | |
90884b2b L |
8250 | struct tdesc_arch_data *tdesc_data; |
8251 | const struct target_desc *tdesc; | |
1ba53b71 | 8252 | int mm0_regnum; |
c131fcee | 8253 | int ymm0_regnum; |
1dbcd68c WT |
8254 | int bnd0_regnum; |
8255 | int num_bnd_cooked; | |
01f9f808 MS |
8256 | int k0_regnum; |
8257 | int zmm0_regnum; | |
7ad10968 HZ |
8258 | |
8259 | /* If there is already a candidate, use it. */ | |
8260 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8261 | if (arches != NULL) | |
8262 | return arches->gdbarch; | |
8263 | ||
8264 | /* Allocate space for the new architecture. */ | |
fc270c35 | 8265 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8266 | gdbarch = gdbarch_alloc (&info, tdep); |
8267 | ||
8268 | /* General-purpose registers. */ | |
7ad10968 HZ |
8269 | tdep->gregset_reg_offset = NULL; |
8270 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8271 | tdep->sizeof_gregset = 0; | |
8272 | ||
8273 | /* Floating-point registers. */ | |
7ad10968 | 8274 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8275 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8276 | |
8277 | /* The default settings include the FPU registers, the MMX registers | |
8278 | and the SSE registers. This can be overridden for a specific ABI | |
8279 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8280 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8281 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8282 | |
8283 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8284 | ||
7ad10968 HZ |
8285 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8286 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8287 | ||
8288 | tdep->jb_pc_offset = -1; | |
8289 | tdep->struct_return = pcc_struct_return; | |
8290 | tdep->sigtramp_start = 0; | |
8291 | tdep->sigtramp_end = 0; | |
8292 | tdep->sigtramp_p = i386_sigtramp_p; | |
8293 | tdep->sigcontext_addr = NULL; | |
8294 | tdep->sc_reg_offset = NULL; | |
8295 | tdep->sc_pc_offset = -1; | |
8296 | tdep->sc_sp_offset = -1; | |
8297 | ||
c131fcee L |
8298 | tdep->xsave_xcr0_offset = -1; |
8299 | ||
cf648174 HZ |
8300 | tdep->record_regmap = i386_record_regmap; |
8301 | ||
205c306f DM |
8302 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8303 | ||
7ad10968 HZ |
8304 | /* The format used for `long double' on almost all i386 targets is |
8305 | the i387 extended floating-point format. In fact, of all targets | |
8306 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8307 | on having a `long double' that's not `long' at all. */ | |
8308 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8309 | ||
8310 | /* Although the i387 extended floating-point has only 80 significant | |
8311 | bits, a `long double' actually takes up 96, probably to enforce | |
8312 | alignment. */ | |
8313 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8314 | ||
7ad10968 HZ |
8315 | /* Register numbers of various important registers. */ |
8316 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8317 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8318 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8319 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8320 | ||
8321 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8322 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8323 | differ in how they number %ebp, %esp, %eflags, and the | |
8324 | floating-point registers, and are implemented by the arrays | |
8325 | dbx_register_map[] and svr4_dbx_register_map in | |
8326 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8327 | gcc/config/i386.c, which it designates as the "default" register | |
8328 | map used in 64bit mode. This last register numbering scheme is | |
8329 | implemented in dbx64_register_map, and is used for AMD64; see | |
8330 | amd64-tdep.c. | |
8331 | ||
8332 | Currently, each GCC i386 target always uses the same register | |
8333 | numbering scheme across all its supported debugging formats | |
8334 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8335 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8336 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8337 | respective config header in a manner independent of the requested | |
8338 | output debugging format. | |
8339 | ||
8340 | This does not match the arrangement below, which presumes that | |
8341 | the SDB and stabs numbering schemes differ from the DWARF and | |
8342 | DWARF 2 ones. The reason for this arrangement is that it is | |
8343 | likely to get the numbering scheme for the target's | |
8344 | default/native debug format right. For targets where GCC is the | |
8345 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8346 | targets where the native toolchain uses a different numbering | |
8347 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8348 | the defaults below will have to be overridden, like | |
8349 | i386_elf_init_abi() does. */ | |
8350 | ||
8351 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8352 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8353 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8354 | ||
8355 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
8356 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8357 | ||
8358 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8359 | be in use on any of the supported i386 targets. */ | |
8360 | ||
8361 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8362 | ||
8363 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8364 | ||
8365 | /* Call dummy code. */ | |
a9b8d892 JK |
8366 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8367 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8368 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8369 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8370 | |
8371 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8372 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8373 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8374 | ||
8375 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8376 | ||
8377 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8378 | ||
8379 | /* Stack grows downward. */ | |
8380 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8381 | ||
8382 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
8383 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
8384 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8385 | ||
8386 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8387 | ||
7ad10968 HZ |
8388 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8389 | ||
8390 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8391 | ||
8392 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8393 | ||
8394 | /* Add the i386 register groups. */ | |
8395 | i386_add_reggroups (gdbarch); | |
90884b2b | 8396 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8397 | |
143985b7 AF |
8398 | /* Helper for function argument information. */ |
8399 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8400 | ||
06da04c6 | 8401 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8402 | appended to the list first, so that it supercedes the DWARF |
8403 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8404 | currently fails). */ |
8405 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8406 | ||
8407 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8408 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8409 | CFI info will be used if it is available. */ |
10458914 | 8410 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8411 | |
acd5c798 | 8412 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8413 | |
1ba53b71 | 8414 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8415 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8416 | i386_pseudo_register_read_value); | |
90884b2b L |
8417 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
8418 | ||
8419 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8420 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8421 | ||
c131fcee L |
8422 | /* Override the normal target description method to make the AVX |
8423 | upper halves anonymous. */ | |
8424 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8425 | ||
8426 | /* Even though the default ABI only includes general-purpose registers, | |
8427 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 MS |
8428 | gap for the upper AVX, MPX and AVX512 registers. */ |
8429 | set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS); | |
90884b2b | 8430 | |
ac04f72b TT |
8431 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8432 | ||
90884b2b L |
8433 | /* Get the x86 target description from INFO. */ |
8434 | tdesc = info.target_desc; | |
8435 | if (! tdesc_has_registers (tdesc)) | |
8436 | tdesc = tdesc_i386; | |
8437 | tdep->tdesc = tdesc; | |
8438 | ||
8439 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8440 | tdep->register_names = i386_register_names; | |
8441 | ||
c131fcee L |
8442 | /* No upper YMM registers. */ |
8443 | tdep->ymmh_register_names = NULL; | |
8444 | tdep->ymm0h_regnum = -1; | |
8445 | ||
01f9f808 MS |
8446 | /* No upper ZMM registers. */ |
8447 | tdep->zmmh_register_names = NULL; | |
8448 | tdep->zmm0h_regnum = -1; | |
8449 | ||
8450 | /* No high XMM registers. */ | |
8451 | tdep->xmm_avx512_register_names = NULL; | |
8452 | tdep->xmm16_regnum = -1; | |
8453 | ||
8454 | /* No upper YMM16-31 registers. */ | |
8455 | tdep->ymm16h_register_names = NULL; | |
8456 | tdep->ymm16h_regnum = -1; | |
8457 | ||
1ba53b71 L |
8458 | tdep->num_byte_regs = 8; |
8459 | tdep->num_word_regs = 8; | |
8460 | tdep->num_dword_regs = 0; | |
8461 | tdep->num_mmx_regs = 8; | |
c131fcee | 8462 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8463 | |
1dbcd68c WT |
8464 | /* No MPX registers. */ |
8465 | tdep->bnd0r_regnum = -1; | |
8466 | tdep->bndcfgu_regnum = -1; | |
8467 | ||
01f9f808 MS |
8468 | /* No AVX512 registers. */ |
8469 | tdep->k0_regnum = -1; | |
8470 | tdep->num_zmm_regs = 0; | |
8471 | tdep->num_ymm_avx512_regs = 0; | |
8472 | tdep->num_xmm_avx512_regs = 0; | |
8473 | ||
90884b2b L |
8474 | tdesc_data = tdesc_data_alloc (); |
8475 | ||
dde08ee1 PA |
8476 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8477 | ||
6710bf39 SS |
8478 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8479 | ||
c2170eef MM |
8480 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8481 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8482 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8483 | ||
3ce1502b | 8484 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 8485 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 8486 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8487 | |
c131fcee L |
8488 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8489 | { | |
8490 | tdesc_data_cleanup (tdesc_data); | |
8491 | xfree (tdep); | |
8492 | gdbarch_free (gdbarch); | |
8493 | return NULL; | |
8494 | } | |
8495 | ||
1dbcd68c WT |
8496 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8497 | ||
1ba53b71 L |
8498 | /* Wire in pseudo registers. Number of pseudo registers may be |
8499 | changed. */ | |
8500 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8501 | + tdep->num_word_regs | |
8502 | + tdep->num_dword_regs | |
c131fcee | 8503 | + tdep->num_mmx_regs |
1dbcd68c | 8504 | + tdep->num_ymm_regs |
01f9f808 MS |
8505 | + num_bnd_cooked |
8506 | + tdep->num_ymm_avx512_regs | |
8507 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8508 | |
90884b2b L |
8509 | /* Target description may be changed. */ |
8510 | tdesc = tdep->tdesc; | |
8511 | ||
90884b2b L |
8512 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8513 | ||
8514 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8515 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8516 | ||
1ba53b71 L |
8517 | /* Make %al the first pseudo-register. */ |
8518 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8519 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8520 | ||
c131fcee | 8521 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8522 | if (tdep->num_dword_regs) |
8523 | { | |
1c6272a6 | 8524 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8525 | tdep->eax_regnum = ymm0_regnum; |
8526 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8527 | } |
8528 | else | |
8529 | tdep->eax_regnum = -1; | |
8530 | ||
c131fcee L |
8531 | mm0_regnum = ymm0_regnum; |
8532 | if (tdep->num_ymm_regs) | |
8533 | { | |
1c6272a6 | 8534 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8535 | tdep->ymm0_regnum = ymm0_regnum; |
8536 | mm0_regnum += tdep->num_ymm_regs; | |
8537 | } | |
8538 | else | |
8539 | tdep->ymm0_regnum = -1; | |
8540 | ||
01f9f808 MS |
8541 | if (tdep->num_ymm_avx512_regs) |
8542 | { | |
8543 | /* Support YMM16-31 pseudo registers if available. */ | |
8544 | tdep->ymm16_regnum = mm0_regnum; | |
8545 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8546 | } | |
8547 | else | |
8548 | tdep->ymm16_regnum = -1; | |
8549 | ||
8550 | if (tdep->num_zmm_regs) | |
8551 | { | |
8552 | /* Support ZMM pseudo-register if it is available. */ | |
8553 | tdep->zmm0_regnum = mm0_regnum; | |
8554 | mm0_regnum += tdep->num_zmm_regs; | |
8555 | } | |
8556 | else | |
8557 | tdep->zmm0_regnum = -1; | |
8558 | ||
1dbcd68c | 8559 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8560 | if (tdep->num_mmx_regs != 0) |
8561 | { | |
1c6272a6 | 8562 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8563 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8564 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8565 | } |
8566 | else | |
8567 | tdep->mm0_regnum = -1; | |
8568 | ||
1dbcd68c WT |
8569 | if (tdep->bnd0r_regnum > 0) |
8570 | tdep->bnd0_regnum = bnd0_regnum; | |
8571 | else | |
8572 | tdep-> bnd0_regnum = -1; | |
8573 | ||
06da04c6 | 8574 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8575 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8576 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8577 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8578 | |
8446b36a MK |
8579 | /* If we have a register mapping, enable the generic core file |
8580 | support, unless it has already been enabled. */ | |
8581 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8582 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8583 | set_gdbarch_iterate_over_regset_sections |
8584 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8585 | |
7a697b8d SS |
8586 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8587 | i386_fast_tracepoint_valid_at); | |
8588 | ||
a62cc96e AC |
8589 | return gdbarch; |
8590 | } | |
8591 | ||
8201327c MK |
8592 | static enum gdb_osabi |
8593 | i386_coff_osabi_sniffer (bfd *abfd) | |
8594 | { | |
762c5349 MK |
8595 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8596 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8597 | return GDB_OSABI_GO32; |
8598 | ||
8599 | return GDB_OSABI_UNKNOWN; | |
8600 | } | |
8201327c MK |
8601 | \f |
8602 | ||
97de3545 JB |
8603 | /* Return the target description for a specified XSAVE feature mask. */ |
8604 | ||
8605 | const struct target_desc * | |
8606 | i386_target_description (uint64_t xcr0) | |
8607 | { | |
8608 | switch (xcr0 & X86_XSTATE_ALL_MASK) | |
8609 | { | |
8610 | case X86_XSTATE_MPX_AVX512_MASK: | |
8611 | case X86_XSTATE_AVX512_MASK: | |
8612 | return tdesc_i386_avx512; | |
8613 | case X86_XSTATE_MPX_MASK: | |
8614 | return tdesc_i386_mpx; | |
8615 | case X86_XSTATE_AVX_MASK: | |
8616 | return tdesc_i386_avx; | |
8617 | default: | |
8618 | return tdesc_i386; | |
8619 | } | |
8620 | } | |
8621 | ||
29c1c244 WT |
8622 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8623 | ||
8624 | /* Find the bound directory base address. */ | |
8625 | ||
8626 | static unsigned long | |
8627 | i386_mpx_bd_base (void) | |
8628 | { | |
8629 | struct regcache *rcache; | |
8630 | struct gdbarch_tdep *tdep; | |
8631 | ULONGEST ret; | |
8632 | enum register_status regstatus; | |
8633 | struct gdb_exception except; | |
8634 | ||
8635 | rcache = get_current_regcache (); | |
8636 | tdep = gdbarch_tdep (get_regcache_arch (rcache)); | |
8637 | ||
8638 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8639 | ||
8640 | if (regstatus != REG_VALID) | |
8641 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8642 | ||
8643 | return ret & MPX_BASE_MASK; | |
8644 | } | |
8645 | ||
8646 | /* Check if the current target is MPX enabled. */ | |
8647 | ||
8648 | static int | |
8649 | i386_mpx_enabled (void) | |
8650 | { | |
8651 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8652 | const struct target_desc *tdesc = tdep->tdesc; | |
8653 | ||
8654 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8655 | } | |
8656 | ||
8657 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8658 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8659 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8660 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8661 | ||
8662 | /* Find the bound table entry given the pointer location and the base | |
8663 | address of the table. */ | |
8664 | ||
8665 | static CORE_ADDR | |
8666 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8667 | { | |
8668 | CORE_ADDR offset1; | |
8669 | CORE_ADDR offset2; | |
8670 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8671 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8672 | CORE_ADDR bd_entry_addr; | |
8673 | CORE_ADDR bt_addr; | |
8674 | CORE_ADDR bd_entry; | |
8675 | struct gdbarch *gdbarch = get_current_arch (); | |
8676 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8677 | ||
8678 | ||
8679 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8680 | { | |
8681 | mpx_bd_mask = MPX_BD_MASK; | |
8682 | bd_ptr_r_shift = 20; | |
8683 | bd_ptr_l_shift = 3; | |
8684 | bt_select_r_shift = 3; | |
8685 | bt_select_l_shift = 5; | |
8686 | bt_mask = MPX_BT_MASK; | |
8687 | } | |
8688 | else | |
8689 | { | |
8690 | mpx_bd_mask = MPX_BD_MASK_32; | |
8691 | bd_ptr_r_shift = 12; | |
8692 | bd_ptr_l_shift = 2; | |
8693 | bt_select_r_shift = 2; | |
8694 | bt_select_l_shift = 4; | |
8695 | bt_mask = MPX_BT_MASK_32; | |
8696 | } | |
8697 | ||
8698 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8699 | bd_entry_addr = bd_base + offset1; | |
8700 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8701 | ||
8702 | if ((bd_entry & 0x1) == 0) | |
8703 | error (_("Invalid bounds directory entry at %s."), | |
8704 | paddress (get_current_arch (), bd_entry_addr)); | |
8705 | ||
8706 | /* Clearing status bit. */ | |
8707 | bd_entry--; | |
8708 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8709 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8710 | ||
8711 | return bt_addr + offset2; | |
8712 | } | |
8713 | ||
8714 | /* Print routine for the mpx bounds. */ | |
8715 | ||
8716 | static void | |
8717 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8718 | { | |
8719 | struct ui_out *uiout = current_uiout; | |
8720 | long long int size; | |
8721 | struct gdbarch *gdbarch = get_current_arch (); | |
8722 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8723 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8724 | ||
8725 | if (bounds_in_map == 1) | |
8726 | { | |
8727 | ui_out_text (uiout, "Null bounds on map:"); | |
8728 | ui_out_text (uiout, " pointer value = "); | |
8729 | ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]); | |
8730 | ui_out_text (uiout, "."); | |
8731 | ui_out_text (uiout, "\n"); | |
8732 | } | |
8733 | else | |
8734 | { | |
8735 | ui_out_text (uiout, "{lbound = "); | |
8736 | ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]); | |
8737 | ui_out_text (uiout, ", ubound = "); | |
8738 | ||
8739 | /* The upper bound is stored in 1's complement. */ | |
8740 | ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]); | |
8741 | ui_out_text (uiout, "}: pointer value = "); | |
8742 | ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]); | |
8743 | ||
8744 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8745 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8746 | else | |
8747 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8748 | ||
8749 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8750 | -1 represents in this sense full memory access, and there is no need | |
8751 | one to the size. */ | |
8752 | ||
8753 | size = (size > -1 ? size + 1 : size); | |
8754 | ui_out_text (uiout, ", size = "); | |
8755 | ui_out_field_fmt (uiout, "size", "%lld", size); | |
8756 | ||
8757 | ui_out_text (uiout, ", metadata = "); | |
8758 | ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]); | |
8759 | ui_out_text (uiout, "\n"); | |
8760 | } | |
8761 | } | |
8762 | ||
8763 | /* Implement the command "show mpx bound". */ | |
8764 | ||
8765 | static void | |
8766 | i386_mpx_info_bounds (char *args, int from_tty) | |
8767 | { | |
8768 | CORE_ADDR bd_base = 0; | |
8769 | CORE_ADDR addr; | |
8770 | CORE_ADDR bt_entry_addr = 0; | |
8771 | CORE_ADDR bt_entry[4]; | |
8772 | int i; | |
8773 | struct gdbarch *gdbarch = get_current_arch (); | |
8774 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8775 | ||
8776 | if (!i386_mpx_enabled ()) | |
8777 | error (_("Intel(R) Memory Protection Extensions not\ | |
8778 | supported on this target.")); | |
8779 | ||
8780 | if (args == NULL) | |
8781 | error (_("Address of pointer variable expected.")); | |
8782 | ||
8783 | addr = parse_and_eval_address (args); | |
8784 | ||
8785 | bd_base = i386_mpx_bd_base (); | |
8786 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8787 | ||
8788 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8789 | ||
8790 | for (i = 0; i < 4; i++) | |
8791 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
8792 | + i * data_ptr_type->length, | |
8793 | data_ptr_type); | |
8794 | ||
8795 | i386_mpx_print_bounds (bt_entry); | |
8796 | } | |
8797 | ||
8798 | /* Implement the command "set mpx bound". */ | |
8799 | ||
8800 | static void | |
8801 | i386_mpx_set_bounds (char *args, int from_tty) | |
8802 | { | |
8803 | CORE_ADDR bd_base = 0; | |
8804 | CORE_ADDR addr, lower, upper; | |
8805 | CORE_ADDR bt_entry_addr = 0; | |
8806 | CORE_ADDR bt_entry[2]; | |
8807 | const char *input = args; | |
8808 | int i; | |
8809 | struct gdbarch *gdbarch = get_current_arch (); | |
8810 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8811 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8812 | ||
8813 | if (!i386_mpx_enabled ()) | |
8814 | error (_("Intel(R) Memory Protection Extensions not supported\ | |
8815 | on this target.")); | |
8816 | ||
8817 | if (args == NULL) | |
8818 | error (_("Pointer value expected.")); | |
8819 | ||
8820 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8821 | ||
8822 | if (input[0] == ',') | |
8823 | ++input; | |
8824 | if (input[0] == '\0') | |
8825 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8826 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8827 | ||
8828 | if (input[0] == ',') | |
8829 | ++input; | |
8830 | if (input[0] == '\0') | |
8831 | error (_("Wrong number of arguments; Missing upper bound.")); | |
8832 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
8833 | ||
8834 | bd_base = i386_mpx_bd_base (); | |
8835 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8836 | for (i = 0; i < 2; i++) | |
8837 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
8838 | + i * data_ptr_type->length, | |
8839 | data_ptr_type); | |
8840 | bt_entry[0] = (uint64_t) lower; | |
8841 | bt_entry[1] = ~(uint64_t) upper; | |
8842 | ||
8843 | for (i = 0; i < 2; i++) | |
8844 | write_memory_unsigned_integer (bt_entry_addr + i * data_ptr_type->length, | |
8845 | data_ptr_type->length, byte_order, | |
8846 | bt_entry[i]); | |
8847 | } | |
8848 | ||
8849 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
8850 | ||
8851 | /* Helper function for the CLI commands. */ | |
8852 | ||
8853 | static void | |
8854 | set_mpx_cmd (char *args, int from_tty) | |
8855 | { | |
8856 | help_list (mpx_set_cmdlist, "set mpx", all_commands, gdb_stdout); | |
8857 | } | |
8858 | ||
8859 | /* Helper function for the CLI commands. */ | |
8860 | ||
8861 | static void | |
8862 | show_mpx_cmd (char *args, int from_tty) | |
8863 | { | |
8864 | cmd_show_list (mpx_show_cmdlist, from_tty, ""); | |
8865 | } | |
8866 | ||
28e9e0f0 MK |
8867 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
8868 | void _initialize_i386_tdep (void); | |
8869 | ||
c906108c | 8870 | void |
fba45db2 | 8871 | _initialize_i386_tdep (void) |
c906108c | 8872 | { |
a62cc96e AC |
8873 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8874 | ||
fc338970 | 8875 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8876 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8877 | &disassembly_flavor, _("\ | |
8878 | Set the disassembly flavor."), _("\ | |
8879 | Show the disassembly flavor."), _("\ | |
8880 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8881 | NULL, | |
8882 | NULL, /* FIXME: i18n: */ | |
8883 | &setlist, &showlist); | |
8201327c MK |
8884 | |
8885 | /* Add the variable that controls the convention for returning | |
8886 | structs. */ | |
7ab04401 AC |
8887 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
8888 | &struct_convention, _("\ | |
8889 | Set the convention for returning small structs."), _("\ | |
8890 | Show the convention for returning small structs."), _("\ | |
8891 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
8892 | is \"default\"."), | |
8893 | NULL, | |
8894 | NULL, /* FIXME: i18n: */ | |
8895 | &setlist, &showlist); | |
8201327c | 8896 | |
29c1c244 WT |
8897 | /* Add "mpx" prefix for the set commands. */ |
8898 | ||
8899 | add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\ | |
8900 | Set Intel(R) Memory Protection Extensions specific variables."), | |
8901 | &mpx_set_cmdlist, "set tdesc ", | |
8902 | 0 /* allow-unknown */, &setlist); | |
8903 | ||
8904 | /* Add "mpx" prefix for the show commands. */ | |
8905 | ||
8906 | add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\ | |
8907 | Show Intel(R) Memory Protection Extensions specific variables."), | |
8908 | &mpx_show_cmdlist, "show mpx ", | |
8909 | 0 /* allow-unknown */, &showlist); | |
8910 | ||
8911 | /* Add "bound" command for the show mpx commands list. */ | |
8912 | ||
8913 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
8914 | "Show the memory bounds for a given array/pointer storage\ | |
8915 | in the bound table.", | |
8916 | &mpx_show_cmdlist); | |
8917 | ||
8918 | /* Add "bound" command for the set mpx commands list. */ | |
8919 | ||
8920 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
8921 | "Set the memory bounds for a given array/pointer storage\ | |
8922 | in the bound table.", | |
8923 | &mpx_set_cmdlist); | |
8924 | ||
8201327c MK |
8925 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, |
8926 | i386_coff_osabi_sniffer); | |
8201327c | 8927 | |
05816f70 | 8928 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 8929 | i386_svr4_init_abi); |
05816f70 | 8930 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 8931 | i386_go32_init_abi); |
38c968cf | 8932 | |
209bd28e | 8933 | /* Initialize the i386-specific register groups. */ |
38c968cf | 8934 | i386_init_reggroups (); |
90884b2b L |
8935 | |
8936 | /* Initialize the standard target descriptions. */ | |
8937 | initialize_tdesc_i386 (); | |
3a13a53b | 8938 | initialize_tdesc_i386_mmx (); |
c131fcee | 8939 | initialize_tdesc_i386_avx (); |
1dbcd68c | 8940 | initialize_tdesc_i386_mpx (); |
01f9f808 | 8941 | initialize_tdesc_i386_avx512 (); |
c8d5aac9 L |
8942 | |
8943 | /* Tell remote stub that we support XML target description. */ | |
8944 | register_remote_support_xml ("i386"); | |
c906108c | 8945 | } |