Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
90884b2b | 57 | #include "features/i386/i386.c" |
c131fcee | 58 | #include "features/i386/i386-avx.c" |
3a13a53b | 59 | #include "features/i386/i386-mmx.c" |
90884b2b | 60 | |
6710bf39 SS |
61 | #include "ax.h" |
62 | #include "ax-gdb.h" | |
63 | ||
55aa24fb SDJ |
64 | #include "stap-probe.h" |
65 | #include "user-regs.h" | |
66 | #include "cli/cli-utils.h" | |
67 | #include "expression.h" | |
68 | #include "parser-defs.h" | |
69 | #include <ctype.h> | |
70 | ||
c4fc7f1b | 71 | /* Register names. */ |
c40e1eab | 72 | |
90884b2b | 73 | static const char *i386_register_names[] = |
fc633446 MK |
74 | { |
75 | "eax", "ecx", "edx", "ebx", | |
76 | "esp", "ebp", "esi", "edi", | |
77 | "eip", "eflags", "cs", "ss", | |
78 | "ds", "es", "fs", "gs", | |
79 | "st0", "st1", "st2", "st3", | |
80 | "st4", "st5", "st6", "st7", | |
81 | "fctrl", "fstat", "ftag", "fiseg", | |
82 | "fioff", "foseg", "fooff", "fop", | |
83 | "xmm0", "xmm1", "xmm2", "xmm3", | |
84 | "xmm4", "xmm5", "xmm6", "xmm7", | |
85 | "mxcsr" | |
86 | }; | |
87 | ||
c131fcee L |
88 | static const char *i386_ymm_names[] = |
89 | { | |
90 | "ymm0", "ymm1", "ymm2", "ymm3", | |
91 | "ymm4", "ymm5", "ymm6", "ymm7", | |
92 | }; | |
93 | ||
94 | static const char *i386_ymmh_names[] = | |
95 | { | |
96 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
97 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
98 | }; | |
99 | ||
c4fc7f1b | 100 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 101 | |
90884b2b | 102 | static const char *i386_mmx_names[] = |
28fc6740 AC |
103 | { |
104 | "mm0", "mm1", "mm2", "mm3", | |
105 | "mm4", "mm5", "mm6", "mm7" | |
106 | }; | |
c40e1eab | 107 | |
1ba53b71 L |
108 | /* Register names for byte pseudo-registers. */ |
109 | ||
110 | static const char *i386_byte_names[] = | |
111 | { | |
112 | "al", "cl", "dl", "bl", | |
113 | "ah", "ch", "dh", "bh" | |
114 | }; | |
115 | ||
116 | /* Register names for word pseudo-registers. */ | |
117 | ||
118 | static const char *i386_word_names[] = | |
119 | { | |
120 | "ax", "cx", "dx", "bx", | |
9cad29ac | 121 | "", "bp", "si", "di" |
1ba53b71 L |
122 | }; |
123 | ||
124 | /* MMX register? */ | |
c40e1eab | 125 | |
28fc6740 | 126 | static int |
5716833c | 127 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 128 | { |
1ba53b71 L |
129 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
130 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
131 | |
132 | if (mm0_regnum < 0) | |
133 | return 0; | |
134 | ||
1ba53b71 L |
135 | regnum -= mm0_regnum; |
136 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
137 | } | |
138 | ||
139 | /* Byte register? */ | |
140 | ||
141 | int | |
142 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
143 | { | |
144 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
145 | ||
146 | regnum -= tdep->al_regnum; | |
147 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
148 | } | |
149 | ||
150 | /* Word register? */ | |
151 | ||
152 | int | |
153 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
154 | { | |
155 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156 | ||
157 | regnum -= tdep->ax_regnum; | |
158 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
159 | } | |
160 | ||
161 | /* Dword register? */ | |
162 | ||
163 | int | |
164 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
165 | { | |
166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
167 | int eax_regnum = tdep->eax_regnum; | |
168 | ||
169 | if (eax_regnum < 0) | |
170 | return 0; | |
171 | ||
172 | regnum -= eax_regnum; | |
173 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
174 | } |
175 | ||
9191d390 | 176 | static int |
c131fcee L |
177 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
178 | { | |
179 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
180 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
181 | ||
182 | if (ymm0h_regnum < 0) | |
183 | return 0; | |
184 | ||
185 | regnum -= ymm0h_regnum; | |
186 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
187 | } | |
188 | ||
189 | /* AVX register? */ | |
190 | ||
191 | int | |
192 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
193 | { | |
194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
195 | int ymm0_regnum = tdep->ymm0_regnum; | |
196 | ||
197 | if (ymm0_regnum < 0) | |
198 | return 0; | |
199 | ||
200 | regnum -= ymm0_regnum; | |
201 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
202 | } | |
203 | ||
5716833c | 204 | /* SSE register? */ |
23a34459 | 205 | |
c131fcee L |
206 | int |
207 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 208 | { |
5716833c | 209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 210 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 211 | |
c131fcee | 212 | if (num_xmm_regs == 0) |
5716833c MK |
213 | return 0; |
214 | ||
c131fcee L |
215 | regnum -= I387_XMM0_REGNUM (tdep); |
216 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
217 | } |
218 | ||
5716833c MK |
219 | static int |
220 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 221 | { |
5716833c MK |
222 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
223 | ||
20a6ec49 | 224 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
225 | return 0; |
226 | ||
20a6ec49 | 227 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
228 | } |
229 | ||
5716833c | 230 | /* FP register? */ |
23a34459 AC |
231 | |
232 | int | |
20a6ec49 | 233 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 234 | { |
20a6ec49 MD |
235 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
236 | ||
237 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
238 | return 0; |
239 | ||
20a6ec49 MD |
240 | return (I387_ST0_REGNUM (tdep) <= regnum |
241 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
242 | } |
243 | ||
244 | int | |
20a6ec49 | 245 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 246 | { |
20a6ec49 MD |
247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
248 | ||
249 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
250 | return 0; |
251 | ||
20a6ec49 MD |
252 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
253 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
254 | } |
255 | ||
c131fcee L |
256 | /* Return the name of register REGNUM, or the empty string if it is |
257 | an anonymous register. */ | |
258 | ||
259 | static const char * | |
260 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
261 | { | |
262 | /* Hide the upper YMM registers. */ | |
263 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
264 | return ""; | |
265 | ||
266 | return tdesc_register_name (gdbarch, regnum); | |
267 | } | |
268 | ||
30b0e2d8 | 269 | /* Return the name of register REGNUM. */ |
fc633446 | 270 | |
1ba53b71 | 271 | const char * |
90884b2b | 272 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 273 | { |
1ba53b71 L |
274 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
275 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
276 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
277 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
278 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
279 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
280 | return i386_byte_names[regnum - tdep->al_regnum]; | |
281 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
282 | return i386_word_names[regnum - tdep->ax_regnum]; | |
283 | ||
284 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
285 | } |
286 | ||
c4fc7f1b | 287 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
288 | number used by GDB. */ |
289 | ||
8201327c | 290 | static int |
d3f73121 | 291 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 292 | { |
20a6ec49 MD |
293 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
294 | ||
c4fc7f1b MK |
295 | /* This implements what GCC calls the "default" register map |
296 | (dbx_register_map[]). */ | |
297 | ||
85540d8c MK |
298 | if (reg >= 0 && reg <= 7) |
299 | { | |
9872ad24 JB |
300 | /* General-purpose registers. The debug info calls %ebp |
301 | register 4, and %esp register 5. */ | |
302 | if (reg == 4) | |
303 | return 5; | |
304 | else if (reg == 5) | |
305 | return 4; | |
306 | else return reg; | |
85540d8c MK |
307 | } |
308 | else if (reg >= 12 && reg <= 19) | |
309 | { | |
310 | /* Floating-point registers. */ | |
20a6ec49 | 311 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
312 | } |
313 | else if (reg >= 21 && reg <= 28) | |
314 | { | |
315 | /* SSE registers. */ | |
c131fcee L |
316 | int ymm0_regnum = tdep->ymm0_regnum; |
317 | ||
318 | if (ymm0_regnum >= 0 | |
319 | && i386_xmm_regnum_p (gdbarch, reg)) | |
320 | return reg - 21 + ymm0_regnum; | |
321 | else | |
322 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
323 | } |
324 | else if (reg >= 29 && reg <= 36) | |
325 | { | |
326 | /* MMX registers. */ | |
20a6ec49 | 327 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
328 | } |
329 | ||
330 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 331 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
332 | } |
333 | ||
c4fc7f1b MK |
334 | /* Convert SVR4 register number REG to the appropriate register number |
335 | used by GDB. */ | |
85540d8c | 336 | |
8201327c | 337 | static int |
d3f73121 | 338 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 339 | { |
20a6ec49 MD |
340 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
341 | ||
c4fc7f1b MK |
342 | /* This implements the GCC register map that tries to be compatible |
343 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
344 | ||
345 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
346 | numbers the floating point registers differently. */ |
347 | if (reg >= 0 && reg <= 9) | |
348 | { | |
acd5c798 | 349 | /* General-purpose registers. */ |
85540d8c MK |
350 | return reg; |
351 | } | |
352 | else if (reg >= 11 && reg <= 18) | |
353 | { | |
354 | /* Floating-point registers. */ | |
20a6ec49 | 355 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 356 | } |
c6f4c129 | 357 | else if (reg >= 21 && reg <= 36) |
85540d8c | 358 | { |
c4fc7f1b | 359 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 360 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
361 | } |
362 | ||
c6f4c129 JB |
363 | switch (reg) |
364 | { | |
20a6ec49 MD |
365 | case 37: return I387_FCTRL_REGNUM (tdep); |
366 | case 38: return I387_FSTAT_REGNUM (tdep); | |
367 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
368 | case 40: return I386_ES_REGNUM; |
369 | case 41: return I386_CS_REGNUM; | |
370 | case 42: return I386_SS_REGNUM; | |
371 | case 43: return I386_DS_REGNUM; | |
372 | case 44: return I386_FS_REGNUM; | |
373 | case 45: return I386_GS_REGNUM; | |
374 | } | |
375 | ||
85540d8c | 376 | /* This will hopefully provoke a warning. */ |
d3f73121 | 377 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 378 | } |
5716833c | 379 | |
fc338970 | 380 | \f |
917317f4 | 381 | |
fc338970 MK |
382 | /* This is the variable that is set with "set disassembly-flavor", and |
383 | its legitimate values. */ | |
53904c9e AC |
384 | static const char att_flavor[] = "att"; |
385 | static const char intel_flavor[] = "intel"; | |
40478521 | 386 | static const char *const valid_flavors[] = |
c5aa993b | 387 | { |
c906108c SS |
388 | att_flavor, |
389 | intel_flavor, | |
390 | NULL | |
391 | }; | |
53904c9e | 392 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 393 | \f |
c906108c | 394 | |
acd5c798 MK |
395 | /* Use the program counter to determine the contents and size of a |
396 | breakpoint instruction. Return a pointer to a string of bytes that | |
397 | encode a breakpoint instruction, store the length of the string in | |
398 | *LEN and optionally adjust *PC to point to the correct memory | |
399 | location for inserting the breakpoint. | |
c906108c | 400 | |
acd5c798 MK |
401 | On the i386 we have a single breakpoint that fits in a single byte |
402 | and can be inserted anywhere. | |
c906108c | 403 | |
acd5c798 | 404 | This function is 64-bit safe. */ |
63c0089f MK |
405 | |
406 | static const gdb_byte * | |
67d57894 | 407 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 408 | { |
63c0089f MK |
409 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
410 | ||
acd5c798 MK |
411 | *len = sizeof (break_insn); |
412 | return break_insn; | |
c906108c | 413 | } |
237fc4c9 PA |
414 | \f |
415 | /* Displaced instruction handling. */ | |
416 | ||
1903f0e6 DE |
417 | /* Skip the legacy instruction prefixes in INSN. |
418 | Not all prefixes are valid for any particular insn | |
419 | but we needn't care, the insn will fault if it's invalid. | |
420 | The result is a pointer to the first opcode byte, | |
421 | or NULL if we run off the end of the buffer. */ | |
422 | ||
423 | static gdb_byte * | |
424 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
425 | { | |
426 | gdb_byte *end = insn + max_len; | |
427 | ||
428 | while (insn < end) | |
429 | { | |
430 | switch (*insn) | |
431 | { | |
432 | case DATA_PREFIX_OPCODE: | |
433 | case ADDR_PREFIX_OPCODE: | |
434 | case CS_PREFIX_OPCODE: | |
435 | case DS_PREFIX_OPCODE: | |
436 | case ES_PREFIX_OPCODE: | |
437 | case FS_PREFIX_OPCODE: | |
438 | case GS_PREFIX_OPCODE: | |
439 | case SS_PREFIX_OPCODE: | |
440 | case LOCK_PREFIX_OPCODE: | |
441 | case REPE_PREFIX_OPCODE: | |
442 | case REPNE_PREFIX_OPCODE: | |
443 | ++insn; | |
444 | continue; | |
445 | default: | |
446 | return insn; | |
447 | } | |
448 | } | |
449 | ||
450 | return NULL; | |
451 | } | |
237fc4c9 PA |
452 | |
453 | static int | |
1903f0e6 | 454 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 455 | { |
1777feb0 | 456 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
457 | if (insn[0] == 0xea) |
458 | return 1; | |
459 | ||
460 | if (insn[0] == 0xff) | |
461 | { | |
1777feb0 | 462 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
463 | if ((insn[1] & 0x38) == 0x20) |
464 | return 1; | |
465 | ||
1777feb0 | 466 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
467 | if ((insn[1] & 0x38) == 0x28) |
468 | return 1; | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | static int | |
1903f0e6 | 475 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 476 | { |
1777feb0 | 477 | /* call far, absolute. */ |
237fc4c9 PA |
478 | if (insn[0] == 0x9a) |
479 | return 1; | |
480 | ||
481 | if (insn[0] == 0xff) | |
482 | { | |
1777feb0 | 483 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
484 | if ((insn[1] & 0x38) == 0x10) |
485 | return 1; | |
486 | ||
1777feb0 | 487 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
488 | if ((insn[1] & 0x38) == 0x18) |
489 | return 1; | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | static int | |
1903f0e6 | 496 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
497 | { |
498 | switch (insn[0]) | |
499 | { | |
1777feb0 | 500 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 501 | case 0xc3: /* ret near */ |
1777feb0 | 502 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
503 | case 0xcb: /* ret far */ |
504 | case 0xcf: /* iret */ | |
505 | return 1; | |
506 | ||
507 | default: | |
508 | return 0; | |
509 | } | |
510 | } | |
511 | ||
512 | static int | |
1903f0e6 | 513 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
514 | { |
515 | if (i386_absolute_call_p (insn)) | |
516 | return 1; | |
517 | ||
1777feb0 | 518 | /* call near, relative. */ |
237fc4c9 PA |
519 | if (insn[0] == 0xe8) |
520 | return 1; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
237fc4c9 PA |
525 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
526 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 527 | |
237fc4c9 | 528 | static int |
b55078be | 529 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 530 | { |
9a7f938f JK |
531 | /* Is it 'int $0x80'? */ |
532 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
533 | /* Or is it 'sysenter'? */ | |
534 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
535 | /* Or is it 'syscall'? */ | |
536 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
537 | { |
538 | *lengthp = 2; | |
539 | return 1; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
b55078be DE |
545 | /* Some kernels may run one past a syscall insn, so we have to cope. |
546 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
547 | ||
548 | struct displaced_step_closure * | |
549 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
550 | CORE_ADDR from, CORE_ADDR to, | |
551 | struct regcache *regs) | |
552 | { | |
553 | size_t len = gdbarch_max_insn_length (gdbarch); | |
554 | gdb_byte *buf = xmalloc (len); | |
555 | ||
556 | read_memory (from, buf, len); | |
557 | ||
558 | /* GDB may get control back after the insn after the syscall. | |
559 | Presumably this is a kernel bug. | |
560 | If this is a syscall, make sure there's a nop afterwards. */ | |
561 | { | |
562 | int syscall_length; | |
563 | gdb_byte *insn; | |
564 | ||
565 | insn = i386_skip_prefixes (buf, len); | |
566 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
567 | insn[syscall_length] = NOP_OPCODE; | |
568 | } | |
569 | ||
570 | write_memory (to, buf, len); | |
571 | ||
572 | if (debug_displaced) | |
573 | { | |
574 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
575 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
576 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
577 | } | |
578 | ||
579 | return (struct displaced_step_closure *) buf; | |
580 | } | |
581 | ||
237fc4c9 PA |
582 | /* Fix up the state of registers and memory after having single-stepped |
583 | a displaced instruction. */ | |
1903f0e6 | 584 | |
237fc4c9 PA |
585 | void |
586 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
587 | struct displaced_step_closure *closure, | |
588 | CORE_ADDR from, CORE_ADDR to, | |
589 | struct regcache *regs) | |
590 | { | |
e17a4113 UW |
591 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
592 | ||
237fc4c9 PA |
593 | /* The offset we applied to the instruction's address. |
594 | This could well be negative (when viewed as a signed 32-bit | |
595 | value), but ULONGEST won't reflect that, so take care when | |
596 | applying it. */ | |
597 | ULONGEST insn_offset = to - from; | |
598 | ||
599 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
600 | copy of the instruction. */ | |
601 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
602 | /* The start of the insn, needed in case we see some prefixes. */ |
603 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
604 | |
605 | if (debug_displaced) | |
606 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 607 | "displaced: fixup (%s, %s), " |
237fc4c9 | 608 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
609 | paddress (gdbarch, from), paddress (gdbarch, to), |
610 | insn[0], insn[1]); | |
237fc4c9 PA |
611 | |
612 | /* The list of issues to contend with here is taken from | |
613 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
614 | Yay for Free Software! */ | |
615 | ||
616 | /* Relocate the %eip, if necessary. */ | |
617 | ||
1903f0e6 DE |
618 | /* The instruction recognizers we use assume any leading prefixes |
619 | have been skipped. */ | |
620 | { | |
621 | /* This is the size of the buffer in closure. */ | |
622 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
623 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
624 | /* If there are too many prefixes, just ignore the insn. | |
625 | It will fault when run. */ | |
626 | if (opcode != NULL) | |
627 | insn = opcode; | |
628 | } | |
629 | ||
237fc4c9 PA |
630 | /* Except in the case of absolute or indirect jump or call |
631 | instructions, or a return instruction, the new eip is relative to | |
632 | the displaced instruction; make it relative. Well, signal | |
633 | handler returns don't need relocation either, but we use the | |
634 | value of %eip to recognize those; see below. */ | |
635 | if (! i386_absolute_jmp_p (insn) | |
636 | && ! i386_absolute_call_p (insn) | |
637 | && ! i386_ret_p (insn)) | |
638 | { | |
639 | ULONGEST orig_eip; | |
b55078be | 640 | int insn_len; |
237fc4c9 PA |
641 | |
642 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
643 | ||
644 | /* A signal trampoline system call changes the %eip, resuming | |
645 | execution of the main program after the signal handler has | |
646 | returned. That makes them like 'return' instructions; we | |
647 | shouldn't relocate %eip. | |
648 | ||
649 | But most system calls don't, and we do need to relocate %eip. | |
650 | ||
651 | Our heuristic for distinguishing these cases: if stepping | |
652 | over the system call instruction left control directly after | |
653 | the instruction, the we relocate --- control almost certainly | |
654 | doesn't belong in the displaced copy. Otherwise, we assume | |
655 | the instruction has put control where it belongs, and leave | |
656 | it unrelocated. Goodness help us if there are PC-relative | |
657 | system calls. */ | |
658 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
659 | && orig_eip != to + (insn - insn_start) + insn_len |
660 | /* GDB can get control back after the insn after the syscall. | |
661 | Presumably this is a kernel bug. | |
662 | i386_displaced_step_copy_insn ensures its a nop, | |
663 | we add one to the length for it. */ | |
664 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
665 | { |
666 | if (debug_displaced) | |
667 | fprintf_unfiltered (gdb_stdlog, | |
668 | "displaced: syscall changed %%eip; " | |
669 | "not relocating\n"); | |
670 | } | |
671 | else | |
672 | { | |
673 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
674 | ||
1903f0e6 DE |
675 | /* If we just stepped over a breakpoint insn, we don't backup |
676 | the pc on purpose; this is to match behaviour without | |
677 | stepping. */ | |
237fc4c9 PA |
678 | |
679 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
680 | ||
681 | if (debug_displaced) | |
682 | fprintf_unfiltered (gdb_stdlog, | |
683 | "displaced: " | |
5af949e3 UW |
684 | "relocated %%eip from %s to %s\n", |
685 | paddress (gdbarch, orig_eip), | |
686 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
687 | } |
688 | } | |
689 | ||
690 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
691 | pushed value, and should be cleared. We'll leave this for later, | |
692 | since GDB already messes up the TF flag when stepping over a | |
693 | pushfl. */ | |
694 | ||
695 | /* If the instruction was a call, the return address now atop the | |
696 | stack is the address following the copied instruction. We need | |
697 | to make it the address following the original instruction. */ | |
698 | if (i386_call_p (insn)) | |
699 | { | |
700 | ULONGEST esp; | |
701 | ULONGEST retaddr; | |
702 | const ULONGEST retaddr_len = 4; | |
703 | ||
704 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 705 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 706 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 707 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
708 | |
709 | if (debug_displaced) | |
710 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
711 | "displaced: relocated return addr at %s to %s\n", |
712 | paddress (gdbarch, esp), | |
713 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
714 | } |
715 | } | |
dde08ee1 PA |
716 | |
717 | static void | |
718 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
719 | { | |
720 | target_write_memory (*to, buf, len); | |
721 | *to += len; | |
722 | } | |
723 | ||
724 | static void | |
725 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
726 | CORE_ADDR *to, CORE_ADDR oldloc) | |
727 | { | |
728 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
729 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
730 | int offset = 0, rel32, newrel; | |
731 | int insn_length; | |
732 | gdb_byte *insn = buf; | |
733 | ||
734 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
735 | ||
736 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
737 | I386_MAX_INSN_LEN, oldloc); | |
738 | ||
739 | /* Get past the prefixes. */ | |
740 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
741 | ||
742 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
743 | the address pushed being the location where the original call in | |
744 | the user program would return to. */ | |
745 | if (insn[0] == 0xe8) | |
746 | { | |
747 | gdb_byte push_buf[16]; | |
748 | unsigned int ret_addr; | |
749 | ||
750 | /* Where "ret" in the original code will return to. */ | |
751 | ret_addr = oldloc + insn_length; | |
1777feb0 | 752 | push_buf[0] = 0x68; /* pushq $... */ |
dde08ee1 PA |
753 | memcpy (&push_buf[1], &ret_addr, 4); |
754 | /* Push the push. */ | |
755 | append_insns (to, 5, push_buf); | |
756 | ||
757 | /* Convert the relative call to a relative jump. */ | |
758 | insn[0] = 0xe9; | |
759 | ||
760 | /* Adjust the destination offset. */ | |
761 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
762 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
763 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
764 | ||
765 | if (debug_displaced) | |
766 | fprintf_unfiltered (gdb_stdlog, | |
767 | "Adjusted insn rel32=%s at %s to" | |
768 | " rel32=%s at %s\n", | |
769 | hex_string (rel32), paddress (gdbarch, oldloc), | |
770 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
771 | |
772 | /* Write the adjusted jump into its displaced location. */ | |
773 | append_insns (to, 5, insn); | |
774 | return; | |
775 | } | |
776 | ||
777 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
778 | handled above. */ | |
779 | if (insn[0] == 0xe9) | |
780 | offset = 1; | |
781 | /* Adjust conditional jumps. */ | |
782 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
783 | offset = 2; | |
784 | ||
785 | if (offset) | |
786 | { | |
787 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
788 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 789 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
790 | if (debug_displaced) |
791 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
792 | "Adjusted insn rel32=%s at %s to" |
793 | " rel32=%s at %s\n", | |
dde08ee1 PA |
794 | hex_string (rel32), paddress (gdbarch, oldloc), |
795 | hex_string (newrel), paddress (gdbarch, *to)); | |
796 | } | |
797 | ||
798 | /* Write the adjusted instructions into their displaced | |
799 | location. */ | |
800 | append_insns (to, insn_length, buf); | |
801 | } | |
802 | ||
fc338970 | 803 | \f |
acd5c798 MK |
804 | #ifdef I386_REGNO_TO_SYMMETRY |
805 | #error "The Sequent Symmetry is no longer supported." | |
806 | #endif | |
c906108c | 807 | |
acd5c798 MK |
808 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
809 | and %esp "belong" to the calling function. Therefore these | |
810 | registers should be saved if they're going to be modified. */ | |
c906108c | 811 | |
acd5c798 MK |
812 | /* The maximum number of saved registers. This should include all |
813 | registers mentioned above, and %eip. */ | |
a3386186 | 814 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
815 | |
816 | struct i386_frame_cache | |
c906108c | 817 | { |
acd5c798 MK |
818 | /* Base address. */ |
819 | CORE_ADDR base; | |
8fbca658 | 820 | int base_p; |
772562f8 | 821 | LONGEST sp_offset; |
acd5c798 MK |
822 | CORE_ADDR pc; |
823 | ||
fd13a04a AC |
824 | /* Saved registers. */ |
825 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 826 | CORE_ADDR saved_sp; |
e0c62198 | 827 | int saved_sp_reg; |
acd5c798 MK |
828 | int pc_in_eax; |
829 | ||
830 | /* Stack space reserved for local variables. */ | |
831 | long locals; | |
832 | }; | |
833 | ||
834 | /* Allocate and initialize a frame cache. */ | |
835 | ||
836 | static struct i386_frame_cache * | |
fd13a04a | 837 | i386_alloc_frame_cache (void) |
acd5c798 MK |
838 | { |
839 | struct i386_frame_cache *cache; | |
840 | int i; | |
841 | ||
842 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
843 | ||
844 | /* Base address. */ | |
8fbca658 | 845 | cache->base_p = 0; |
acd5c798 MK |
846 | cache->base = 0; |
847 | cache->sp_offset = -4; | |
848 | cache->pc = 0; | |
849 | ||
fd13a04a AC |
850 | /* Saved registers. We initialize these to -1 since zero is a valid |
851 | offset (that's where %ebp is supposed to be stored). */ | |
852 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
853 | cache->saved_regs[i] = -1; | |
acd5c798 | 854 | cache->saved_sp = 0; |
e0c62198 | 855 | cache->saved_sp_reg = -1; |
acd5c798 MK |
856 | cache->pc_in_eax = 0; |
857 | ||
858 | /* Frameless until proven otherwise. */ | |
859 | cache->locals = -1; | |
860 | ||
861 | return cache; | |
862 | } | |
c906108c | 863 | |
acd5c798 MK |
864 | /* If the instruction at PC is a jump, return the address of its |
865 | target. Otherwise, return PC. */ | |
c906108c | 866 | |
acd5c798 | 867 | static CORE_ADDR |
e17a4113 | 868 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 869 | { |
e17a4113 | 870 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 871 | gdb_byte op; |
acd5c798 MK |
872 | long delta = 0; |
873 | int data16 = 0; | |
c906108c | 874 | |
3dcabaa8 MS |
875 | if (target_read_memory (pc, &op, 1)) |
876 | return pc; | |
877 | ||
acd5c798 | 878 | if (op == 0x66) |
c906108c | 879 | { |
c906108c | 880 | data16 = 1; |
e17a4113 | 881 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
882 | } |
883 | ||
acd5c798 | 884 | switch (op) |
c906108c SS |
885 | { |
886 | case 0xe9: | |
fc338970 | 887 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
888 | if (data16) |
889 | { | |
e17a4113 | 890 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 891 | |
fc338970 MK |
892 | /* Include the size of the jmp instruction (including the |
893 | 0x66 prefix). */ | |
acd5c798 | 894 | delta += 4; |
c906108c SS |
895 | } |
896 | else | |
897 | { | |
e17a4113 | 898 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 899 | |
acd5c798 MK |
900 | /* Include the size of the jmp instruction. */ |
901 | delta += 5; | |
c906108c SS |
902 | } |
903 | break; | |
904 | case 0xeb: | |
fc338970 | 905 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 906 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 907 | |
acd5c798 | 908 | delta += data16 + 2; |
c906108c SS |
909 | break; |
910 | } | |
c906108c | 911 | |
acd5c798 MK |
912 | return pc + delta; |
913 | } | |
fc338970 | 914 | |
acd5c798 MK |
915 | /* Check whether PC points at a prologue for a function returning a |
916 | structure or union. If so, it updates CACHE and returns the | |
917 | address of the first instruction after the code sequence that | |
918 | removes the "hidden" argument from the stack or CURRENT_PC, | |
919 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 920 | |
acd5c798 MK |
921 | static CORE_ADDR |
922 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
923 | struct i386_frame_cache *cache) | |
c906108c | 924 | { |
acd5c798 MK |
925 | /* Functions that return a structure or union start with: |
926 | ||
927 | popl %eax 0x58 | |
928 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
929 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
930 | ||
931 | (the System V compiler puts out the second `xchg' instruction, | |
932 | and the assembler doesn't try to optimize it, so the 'sib' form | |
933 | gets generated). This sequence is used to get the address of the | |
934 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
935 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
936 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
937 | gdb_byte buf[4]; | |
938 | gdb_byte op; | |
c906108c | 939 | |
acd5c798 MK |
940 | if (current_pc <= pc) |
941 | return pc; | |
942 | ||
3dcabaa8 MS |
943 | if (target_read_memory (pc, &op, 1)) |
944 | return pc; | |
c906108c | 945 | |
acd5c798 MK |
946 | if (op != 0x58) /* popl %eax */ |
947 | return pc; | |
c906108c | 948 | |
3dcabaa8 MS |
949 | if (target_read_memory (pc + 1, buf, 4)) |
950 | return pc; | |
951 | ||
acd5c798 MK |
952 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
953 | return pc; | |
c906108c | 954 | |
acd5c798 | 955 | if (current_pc == pc) |
c906108c | 956 | { |
acd5c798 MK |
957 | cache->sp_offset += 4; |
958 | return current_pc; | |
c906108c SS |
959 | } |
960 | ||
acd5c798 | 961 | if (current_pc == pc + 1) |
c906108c | 962 | { |
acd5c798 MK |
963 | cache->pc_in_eax = 1; |
964 | return current_pc; | |
965 | } | |
966 | ||
967 | if (buf[1] == proto1[1]) | |
968 | return pc + 4; | |
969 | else | |
970 | return pc + 5; | |
971 | } | |
972 | ||
973 | static CORE_ADDR | |
974 | i386_skip_probe (CORE_ADDR pc) | |
975 | { | |
976 | /* A function may start with | |
fc338970 | 977 | |
acd5c798 MK |
978 | pushl constant |
979 | call _probe | |
980 | addl $4, %esp | |
fc338970 | 981 | |
acd5c798 MK |
982 | followed by |
983 | ||
984 | pushl %ebp | |
fc338970 | 985 | |
acd5c798 | 986 | etc. */ |
63c0089f MK |
987 | gdb_byte buf[8]; |
988 | gdb_byte op; | |
fc338970 | 989 | |
3dcabaa8 MS |
990 | if (target_read_memory (pc, &op, 1)) |
991 | return pc; | |
acd5c798 MK |
992 | |
993 | if (op == 0x68 || op == 0x6a) | |
994 | { | |
995 | int delta; | |
c906108c | 996 | |
acd5c798 MK |
997 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
998 | four-byte operand, depending on the opcode. */ | |
c906108c | 999 | if (op == 0x68) |
acd5c798 | 1000 | delta = 5; |
c906108c | 1001 | else |
acd5c798 | 1002 | delta = 2; |
c906108c | 1003 | |
acd5c798 MK |
1004 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1005 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1006 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1007 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1008 | pc += delta + sizeof (buf); |
c906108c SS |
1009 | } |
1010 | ||
acd5c798 MK |
1011 | return pc; |
1012 | } | |
1013 | ||
92dd43fa MK |
1014 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1015 | stack pointer. Check whether PC points to such code, and update | |
1016 | CACHE accordingly. Return the first instruction after the code | |
1017 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1018 | recognize the code, return PC. */ | |
1019 | ||
1020 | static CORE_ADDR | |
1021 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1022 | struct i386_frame_cache *cache) | |
1023 | { | |
e0c62198 L |
1024 | /* There are 2 code sequences to re-align stack before the frame |
1025 | gets set up: | |
1026 | ||
1027 | 1. Use a caller-saved saved register: | |
1028 | ||
1029 | leal 4(%esp), %reg | |
1030 | andl $-XXX, %esp | |
1031 | pushl -4(%reg) | |
1032 | ||
1033 | 2. Use a callee-saved saved register: | |
1034 | ||
1035 | pushl %reg | |
1036 | leal 8(%esp), %reg | |
1037 | andl $-XXX, %esp | |
1038 | pushl -4(%reg) | |
1039 | ||
1040 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1041 | ||
1042 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1043 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1044 | */ | |
1045 | ||
1046 | gdb_byte buf[14]; | |
1047 | int reg; | |
1048 | int offset, offset_and; | |
1049 | static int regnums[8] = { | |
1050 | I386_EAX_REGNUM, /* %eax */ | |
1051 | I386_ECX_REGNUM, /* %ecx */ | |
1052 | I386_EDX_REGNUM, /* %edx */ | |
1053 | I386_EBX_REGNUM, /* %ebx */ | |
1054 | I386_ESP_REGNUM, /* %esp */ | |
1055 | I386_EBP_REGNUM, /* %ebp */ | |
1056 | I386_ESI_REGNUM, /* %esi */ | |
1057 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1058 | }; |
92dd43fa | 1059 | |
e0c62198 L |
1060 | if (target_read_memory (pc, buf, sizeof buf)) |
1061 | return pc; | |
1062 | ||
1063 | /* Check caller-saved saved register. The first instruction has | |
1064 | to be "leal 4(%esp), %reg". */ | |
1065 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1066 | { | |
1067 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1068 | if ((buf[1] & 0xc7) != 0x44) | |
1069 | return pc; | |
1070 | ||
1071 | /* REG has register number. */ | |
1072 | reg = (buf[1] >> 3) & 7; | |
1073 | offset = 4; | |
1074 | } | |
1075 | else | |
1076 | { | |
1077 | /* Check callee-saved saved register. The first instruction | |
1078 | has to be "pushl %reg". */ | |
1079 | if ((buf[0] & 0xf8) != 0x50) | |
1080 | return pc; | |
1081 | ||
1082 | /* Get register. */ | |
1083 | reg = buf[0] & 0x7; | |
1084 | ||
1085 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1086 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1087 | return pc; | |
1088 | ||
1089 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1090 | if ((buf[2] & 0xc7) != 0x44) | |
1091 | return pc; | |
1092 | ||
1093 | /* REG has register number. Registers in pushl and leal have to | |
1094 | be the same. */ | |
1095 | if (reg != ((buf[2] >> 3) & 7)) | |
1096 | return pc; | |
1097 | ||
1098 | offset = 5; | |
1099 | } | |
1100 | ||
1101 | /* Rigister can't be %esp nor %ebp. */ | |
1102 | if (reg == 4 || reg == 5) | |
1103 | return pc; | |
1104 | ||
1105 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1106 | if (buf[offset + 1] != 0xe4 | |
1107 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1108 | return pc; | |
1109 | ||
1110 | offset_and = offset; | |
1111 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1112 | ||
1113 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1114 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1115 | if (buf[offset] != 0xff | |
1116 | || buf[offset + 2] != 0xfc | |
1117 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1118 | return pc; | |
1119 | ||
1120 | /* R/M has register. Registers in leal and pushl have to be the | |
1121 | same. */ | |
1122 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1123 | return pc; |
1124 | ||
e0c62198 L |
1125 | if (current_pc > pc + offset_and) |
1126 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1127 | |
e0c62198 | 1128 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1129 | } |
1130 | ||
37bdc87e | 1131 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1132 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1133 | |
1134 | /* Instruction description. */ | |
1135 | struct i386_insn | |
1136 | { | |
1137 | size_t len; | |
237fc4c9 PA |
1138 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1139 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1140 | }; |
1141 | ||
a3fcb948 | 1142 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1143 | |
a3fcb948 JG |
1144 | static int |
1145 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1146 | { |
63c0089f | 1147 | gdb_byte op; |
37bdc87e | 1148 | |
3dcabaa8 | 1149 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1150 | return 0; |
37bdc87e | 1151 | |
a3fcb948 | 1152 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1153 | { |
a3fcb948 JG |
1154 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1155 | int insn_matched = 1; | |
1156 | size_t i; | |
37bdc87e | 1157 | |
a3fcb948 JG |
1158 | gdb_assert (pattern.len > 1); |
1159 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1160 | |
a3fcb948 JG |
1161 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1162 | return 0; | |
613e8135 | 1163 | |
a3fcb948 JG |
1164 | for (i = 1; i < pattern.len; i++) |
1165 | { | |
1166 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1167 | insn_matched = 0; | |
37bdc87e | 1168 | } |
a3fcb948 JG |
1169 | return insn_matched; |
1170 | } | |
1171 | return 0; | |
1172 | } | |
1173 | ||
1174 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1175 | the first instruction description that matches. Otherwise, return | |
1176 | NULL. */ | |
1177 | ||
1178 | static struct i386_insn * | |
1179 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1180 | { | |
1181 | struct i386_insn *pattern; | |
1182 | ||
1183 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1184 | { | |
1185 | if (i386_match_pattern (pc, *pattern)) | |
1186 | return pattern; | |
37bdc87e MK |
1187 | } |
1188 | ||
1189 | return NULL; | |
1190 | } | |
1191 | ||
a3fcb948 JG |
1192 | /* Return whether PC points inside a sequence of instructions that |
1193 | matches INSN_PATTERNS. */ | |
1194 | ||
1195 | static int | |
1196 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1197 | { | |
1198 | CORE_ADDR current_pc; | |
1199 | int ix, i; | |
1200 | gdb_byte op; | |
1201 | struct i386_insn *insn; | |
1202 | ||
1203 | insn = i386_match_insn (pc, insn_patterns); | |
1204 | if (insn == NULL) | |
1205 | return 0; | |
1206 | ||
8bbdd3f4 | 1207 | current_pc = pc; |
a3fcb948 JG |
1208 | ix = insn - insn_patterns; |
1209 | for (i = ix - 1; i >= 0; i--) | |
1210 | { | |
8bbdd3f4 MK |
1211 | current_pc -= insn_patterns[i].len; |
1212 | ||
a3fcb948 JG |
1213 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1214 | return 0; | |
a3fcb948 JG |
1215 | } |
1216 | ||
1217 | current_pc = pc + insn->len; | |
1218 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1219 | { | |
1220 | if (!i386_match_pattern (current_pc, *insn)) | |
1221 | return 0; | |
1222 | ||
1223 | current_pc += insn->len; | |
1224 | } | |
1225 | ||
1226 | return 1; | |
1227 | } | |
1228 | ||
37bdc87e MK |
1229 | /* Some special instructions that might be migrated by GCC into the |
1230 | part of the prologue that sets up the new stack frame. Because the | |
1231 | stack frame hasn't been setup yet, no registers have been saved | |
1232 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1233 | touched. */ | |
1234 | ||
1235 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1236 | { | |
1777feb0 | 1237 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1238 | |
1239 | ??? Should we handle 16-bit operand-sizes here? */ | |
1240 | ||
1241 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1242 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1243 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1244 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1245 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1246 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1247 | { 5, { 0xb8 }, { 0xfe } }, | |
1248 | /* `movl imm32, %edx' */ | |
1249 | { 5, { 0xba }, { 0xff } }, | |
1250 | ||
1251 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1252 | encoding for `mov m32, %eax'. | |
1253 | ||
1254 | ??? Should we handle SIB adressing here? | |
1255 | ??? Should we handle 16-bit operand-sizes here? */ | |
1256 | ||
1257 | /* `movl m32, %eax' */ | |
1258 | { 5, { 0xa1 }, { 0xff } }, | |
1259 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1260 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1261 | /* `movl m32, %edx' */ | |
1262 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1263 | ||
1264 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1265 | Because of the symmetry, there are actually two ways to encode | |
1266 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1267 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1268 | ||
1269 | /* `subl %eax, %eax' */ | |
1270 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1271 | /* `subl %ecx, %ecx' */ | |
1272 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1273 | /* `subl %edx, %edx' */ | |
1274 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1275 | /* `xorl %eax, %eax' */ | |
1276 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1277 | /* `xorl %ecx, %ecx' */ | |
1278 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1279 | /* `xorl %edx, %edx' */ | |
1280 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1281 | { 0 } | |
1282 | }; | |
1283 | ||
e11481da PM |
1284 | |
1285 | /* Check whether PC points to a no-op instruction. */ | |
1286 | static CORE_ADDR | |
1287 | i386_skip_noop (CORE_ADDR pc) | |
1288 | { | |
1289 | gdb_byte op; | |
1290 | int check = 1; | |
1291 | ||
3dcabaa8 MS |
1292 | if (target_read_memory (pc, &op, 1)) |
1293 | return pc; | |
e11481da PM |
1294 | |
1295 | while (check) | |
1296 | { | |
1297 | check = 0; | |
1298 | /* Ignore `nop' instruction. */ | |
1299 | if (op == 0x90) | |
1300 | { | |
1301 | pc += 1; | |
3dcabaa8 MS |
1302 | if (target_read_memory (pc, &op, 1)) |
1303 | return pc; | |
e11481da PM |
1304 | check = 1; |
1305 | } | |
1306 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1307 | Microsoft system dlls often start with | |
1308 | a `mov %edi,%edi' instruction. | |
1309 | The 5 bytes before the function start are | |
1310 | filled with `nop' instructions. | |
1311 | This pattern can be used for hot-patching: | |
1312 | The `mov %edi, %edi' instruction can be replaced by a | |
1313 | near jump to the location of the 5 `nop' instructions | |
1314 | which can be replaced by a 32-bit jump to anywhere | |
1315 | in the 32-bit address space. */ | |
1316 | ||
1317 | else if (op == 0x8b) | |
1318 | { | |
3dcabaa8 MS |
1319 | if (target_read_memory (pc + 1, &op, 1)) |
1320 | return pc; | |
1321 | ||
e11481da PM |
1322 | if (op == 0xff) |
1323 | { | |
1324 | pc += 2; | |
3dcabaa8 MS |
1325 | if (target_read_memory (pc, &op, 1)) |
1326 | return pc; | |
1327 | ||
e11481da PM |
1328 | check = 1; |
1329 | } | |
1330 | } | |
1331 | } | |
1332 | return pc; | |
1333 | } | |
1334 | ||
acd5c798 MK |
1335 | /* Check whether PC points at a code that sets up a new stack frame. |
1336 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1337 | instruction after the sequence that sets up the frame or LIMIT, |
1338 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1339 | |
1340 | static CORE_ADDR | |
e17a4113 UW |
1341 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1342 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1343 | struct i386_frame_cache *cache) |
1344 | { | |
e17a4113 | 1345 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1346 | struct i386_insn *insn; |
63c0089f | 1347 | gdb_byte op; |
26604a34 | 1348 | int skip = 0; |
acd5c798 | 1349 | |
37bdc87e MK |
1350 | if (limit <= pc) |
1351 | return limit; | |
acd5c798 | 1352 | |
3dcabaa8 MS |
1353 | if (target_read_memory (pc, &op, 1)) |
1354 | return pc; | |
acd5c798 | 1355 | |
c906108c | 1356 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1357 | { |
acd5c798 MK |
1358 | /* Take into account that we've executed the `pushl %ebp' that |
1359 | starts this instruction sequence. */ | |
fd13a04a | 1360 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1361 | cache->sp_offset += 4; |
37bdc87e | 1362 | pc++; |
acd5c798 MK |
1363 | |
1364 | /* If that's all, return now. */ | |
37bdc87e MK |
1365 | if (limit <= pc) |
1366 | return limit; | |
26604a34 | 1367 | |
b4632131 | 1368 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1369 | GCC into the prologue and skip them. At this point in the |
1370 | prologue, code should only touch the scratch registers %eax, | |
1371 | %ecx and %edx, so while the number of posibilities is sheer, | |
1372 | it is limited. | |
5daa5b4e | 1373 | |
26604a34 MK |
1374 | Make sure we only skip these instructions if we later see the |
1375 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1376 | while (pc + skip < limit) |
26604a34 | 1377 | { |
37bdc87e MK |
1378 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1379 | if (insn == NULL) | |
1380 | break; | |
b4632131 | 1381 | |
37bdc87e | 1382 | skip += insn->len; |
26604a34 MK |
1383 | } |
1384 | ||
37bdc87e MK |
1385 | /* If that's all, return now. */ |
1386 | if (limit <= pc + skip) | |
1387 | return limit; | |
1388 | ||
3dcabaa8 MS |
1389 | if (target_read_memory (pc + skip, &op, 1)) |
1390 | return pc + skip; | |
37bdc87e | 1391 | |
26604a34 | 1392 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1393 | switch (op) |
c906108c SS |
1394 | { |
1395 | case 0x8b: | |
e17a4113 UW |
1396 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1397 | != 0xec) | |
37bdc87e | 1398 | return pc; |
c906108c SS |
1399 | break; |
1400 | case 0x89: | |
e17a4113 UW |
1401 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1402 | != 0xe5) | |
37bdc87e | 1403 | return pc; |
c906108c SS |
1404 | break; |
1405 | default: | |
37bdc87e | 1406 | return pc; |
c906108c | 1407 | } |
acd5c798 | 1408 | |
26604a34 MK |
1409 | /* OK, we actually have a frame. We just don't know how large |
1410 | it is yet. Set its size to zero. We'll adjust it if | |
1411 | necessary. We also now commit to skipping the special | |
1412 | instructions mentioned before. */ | |
acd5c798 | 1413 | cache->locals = 0; |
37bdc87e | 1414 | pc += (skip + 2); |
acd5c798 MK |
1415 | |
1416 | /* If that's all, return now. */ | |
37bdc87e MK |
1417 | if (limit <= pc) |
1418 | return limit; | |
acd5c798 | 1419 | |
fc338970 MK |
1420 | /* Check for stack adjustment |
1421 | ||
acd5c798 | 1422 | subl $XXX, %esp |
fc338970 | 1423 | |
fd35795f | 1424 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1425 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1426 | if (target_read_memory (pc, &op, 1)) |
1427 | return pc; | |
c906108c SS |
1428 | if (op == 0x83) |
1429 | { | |
fd35795f | 1430 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1431 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1432 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1433 | return pc; |
acd5c798 | 1434 | |
37bdc87e MK |
1435 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1436 | make sense to be negative). */ | |
e17a4113 | 1437 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1438 | return pc + 3; |
c906108c SS |
1439 | } |
1440 | else if (op == 0x81) | |
1441 | { | |
fd35795f | 1442 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1443 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1444 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1445 | return pc; |
acd5c798 | 1446 | |
fd35795f | 1447 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1448 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1449 | return pc + 6; |
c906108c SS |
1450 | } |
1451 | else | |
1452 | { | |
acd5c798 | 1453 | /* Some instruction other than `subl'. */ |
37bdc87e | 1454 | return pc; |
c906108c SS |
1455 | } |
1456 | } | |
37bdc87e | 1457 | else if (op == 0xc8) /* enter */ |
c906108c | 1458 | { |
e17a4113 | 1459 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1460 | return pc + 4; |
c906108c | 1461 | } |
21d0e8a4 | 1462 | |
acd5c798 | 1463 | return pc; |
21d0e8a4 MK |
1464 | } |
1465 | ||
acd5c798 MK |
1466 | /* Check whether PC points at code that saves registers on the stack. |
1467 | If so, it updates CACHE and returns the address of the first | |
1468 | instruction after the register saves or CURRENT_PC, whichever is | |
1469 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1470 | |
1471 | static CORE_ADDR | |
acd5c798 MK |
1472 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1473 | struct i386_frame_cache *cache) | |
6bff26de | 1474 | { |
99ab4326 | 1475 | CORE_ADDR offset = 0; |
63c0089f | 1476 | gdb_byte op; |
99ab4326 | 1477 | int i; |
c0d1d883 | 1478 | |
99ab4326 MK |
1479 | if (cache->locals > 0) |
1480 | offset -= cache->locals; | |
1481 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1482 | { | |
3dcabaa8 MS |
1483 | if (target_read_memory (pc, &op, 1)) |
1484 | return pc; | |
99ab4326 MK |
1485 | if (op < 0x50 || op > 0x57) |
1486 | break; | |
0d17c81d | 1487 | |
99ab4326 MK |
1488 | offset -= 4; |
1489 | cache->saved_regs[op - 0x50] = offset; | |
1490 | cache->sp_offset += 4; | |
1491 | pc++; | |
6bff26de MK |
1492 | } |
1493 | ||
acd5c798 | 1494 | return pc; |
22797942 AC |
1495 | } |
1496 | ||
acd5c798 MK |
1497 | /* Do a full analysis of the prologue at PC and update CACHE |
1498 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1499 | address where the analysis stopped. | |
ed84f6c1 | 1500 | |
fc338970 MK |
1501 | We handle these cases: |
1502 | ||
1503 | The startup sequence can be at the start of the function, or the | |
1504 | function can start with a branch to startup code at the end. | |
1505 | ||
1506 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1507 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1508 | once used in the System V compiler). | |
1509 | ||
1510 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1511 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1512 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1513 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1514 | |
1515 | Next, the registers used by this function are pushed. With the | |
1516 | System V compiler they will always be in the order: %edi, %esi, | |
1517 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1518 | restore %eax); however, the code below is willing to see the pushes | |
1519 | in any order, and will handle up to 8 of them. | |
1520 | ||
1521 | If the setup sequence is at the end of the function, then the next | |
1522 | instruction will be a branch back to the start. */ | |
c906108c | 1523 | |
acd5c798 | 1524 | static CORE_ADDR |
e17a4113 UW |
1525 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1526 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1527 | struct i386_frame_cache *cache) |
c906108c | 1528 | { |
e11481da | 1529 | pc = i386_skip_noop (pc); |
e17a4113 | 1530 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1531 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1532 | pc = i386_skip_probe (pc); | |
92dd43fa | 1533 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1534 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1535 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1536 | } |
1537 | ||
fc338970 | 1538 | /* Return PC of first real instruction. */ |
c906108c | 1539 | |
3a1e71e3 | 1540 | static CORE_ADDR |
6093d2eb | 1541 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1542 | { |
e17a4113 UW |
1543 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1544 | ||
63c0089f | 1545 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1546 | { |
1547 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1548 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1549 | }; |
acd5c798 MK |
1550 | struct i386_frame_cache cache; |
1551 | CORE_ADDR pc; | |
63c0089f | 1552 | gdb_byte op; |
acd5c798 | 1553 | int i; |
c5aa993b | 1554 | |
acd5c798 | 1555 | cache.locals = -1; |
e17a4113 | 1556 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1557 | if (cache.locals < 0) |
1558 | return start_pc; | |
c5aa993b | 1559 | |
acd5c798 | 1560 | /* Found valid frame setup. */ |
c906108c | 1561 | |
fc338970 MK |
1562 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1563 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1564 | %ebx: |
1565 | ||
fc338970 MK |
1566 | call 0x0 |
1567 | popl %ebx | |
1568 | movl %ebx,x(%ebp) (optional) | |
1569 | addl y,%ebx | |
1570 | ||
c906108c SS |
1571 | This code is with the rest of the prologue (at the end of the |
1572 | function), so we have to skip it to get to the first real | |
1573 | instruction at the start of the function. */ | |
c5aa993b | 1574 | |
c906108c SS |
1575 | for (i = 0; i < 6; i++) |
1576 | { | |
3dcabaa8 MS |
1577 | if (target_read_memory (pc + i, &op, 1)) |
1578 | return pc; | |
1579 | ||
c5aa993b | 1580 | if (pic_pat[i] != op) |
c906108c SS |
1581 | break; |
1582 | } | |
1583 | if (i == 6) | |
1584 | { | |
acd5c798 MK |
1585 | int delta = 6; |
1586 | ||
3dcabaa8 MS |
1587 | if (target_read_memory (pc + delta, &op, 1)) |
1588 | return pc; | |
c906108c | 1589 | |
c5aa993b | 1590 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1591 | { |
e17a4113 | 1592 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1593 | |
fc338970 | 1594 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1595 | delta += 3; |
fc338970 | 1596 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1597 | delta += 6; |
fc338970 | 1598 | else /* Unexpected instruction. */ |
acd5c798 MK |
1599 | delta = 0; |
1600 | ||
3dcabaa8 MS |
1601 | if (target_read_memory (pc + delta, &op, 1)) |
1602 | return pc; | |
c906108c | 1603 | } |
acd5c798 | 1604 | |
c5aa993b | 1605 | /* addl y,%ebx */ |
acd5c798 | 1606 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1607 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1608 | == 0xc3) | |
c906108c | 1609 | { |
acd5c798 | 1610 | pc += delta + 6; |
c906108c SS |
1611 | } |
1612 | } | |
c5aa993b | 1613 | |
e63bbc88 MK |
1614 | /* If the function starts with a branch (to startup code at the end) |
1615 | the last instruction should bring us back to the first | |
1616 | instruction of the real code. */ | |
e17a4113 UW |
1617 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1618 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1619 | |
1620 | return pc; | |
c906108c SS |
1621 | } |
1622 | ||
4309257c PM |
1623 | /* Check that the code pointed to by PC corresponds to a call to |
1624 | __main, skip it if so. Return PC otherwise. */ | |
1625 | ||
1626 | CORE_ADDR | |
1627 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1628 | { | |
e17a4113 | 1629 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1630 | gdb_byte op; |
1631 | ||
3dcabaa8 MS |
1632 | if (target_read_memory (pc, &op, 1)) |
1633 | return pc; | |
4309257c PM |
1634 | if (op == 0xe8) |
1635 | { | |
1636 | gdb_byte buf[4]; | |
1637 | ||
1638 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1639 | { | |
1640 | /* Make sure address is computed correctly as a 32bit | |
1641 | integer even if CORE_ADDR is 64 bit wide. */ | |
1642 | struct minimal_symbol *s; | |
e17a4113 | 1643 | CORE_ADDR call_dest; |
4309257c | 1644 | |
e17a4113 | 1645 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1646 | call_dest = call_dest & 0xffffffffU; |
1647 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1648 | if (s != NULL | |
1649 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1650 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1651 | pc += 5; | |
1652 | } | |
1653 | } | |
1654 | ||
1655 | return pc; | |
1656 | } | |
1657 | ||
acd5c798 | 1658 | /* This function is 64-bit safe. */ |
93924b6b | 1659 | |
acd5c798 MK |
1660 | static CORE_ADDR |
1661 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1662 | { |
63c0089f | 1663 | gdb_byte buf[8]; |
acd5c798 | 1664 | |
875f8d0e | 1665 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1666 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1667 | } |
acd5c798 | 1668 | \f |
93924b6b | 1669 | |
acd5c798 | 1670 | /* Normal frames. */ |
c5aa993b | 1671 | |
8fbca658 PA |
1672 | static void |
1673 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1674 | struct i386_frame_cache *cache) | |
a7769679 | 1675 | { |
e17a4113 UW |
1676 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1677 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1678 | gdb_byte buf[4]; |
acd5c798 MK |
1679 | int i; |
1680 | ||
8fbca658 | 1681 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1682 | |
1683 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1684 | which holds the base address for the current stack frame. | |
1685 | However, for functions that don't need it, the frame pointer is | |
1686 | optional. For these "frameless" functions the frame pointer is | |
1687 | actually the frame pointer of the calling frame. Signal | |
1688 | trampolines are just a special case of a "frameless" function. | |
1689 | They (usually) share their frame pointer with the frame that was | |
1690 | in progress when the signal occurred. */ | |
1691 | ||
10458914 | 1692 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1693 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1694 | if (cache->base == 0) |
620fa63a PA |
1695 | { |
1696 | cache->base_p = 1; | |
1697 | return; | |
1698 | } | |
acd5c798 MK |
1699 | |
1700 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1701 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1702 | |
acd5c798 | 1703 | if (cache->pc != 0) |
e17a4113 UW |
1704 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1705 | cache); | |
acd5c798 MK |
1706 | |
1707 | if (cache->locals < 0) | |
1708 | { | |
1709 | /* We didn't find a valid frame, which means that CACHE->base | |
1710 | currently holds the frame pointer for our calling frame. If | |
1711 | we're at the start of a function, or somewhere half-way its | |
1712 | prologue, the function's frame probably hasn't been fully | |
1713 | setup yet. Try to reconstruct the base address for the stack | |
1714 | frame by looking at the stack pointer. For truly "frameless" | |
1715 | functions this might work too. */ | |
1716 | ||
e0c62198 | 1717 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1718 | { |
8fbca658 PA |
1719 | /* Saved stack pointer has been saved. */ |
1720 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1721 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1722 | ||
92dd43fa MK |
1723 | /* We're halfway aligning the stack. */ |
1724 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1725 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1726 | ||
1727 | /* This will be added back below. */ | |
1728 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1729 | } | |
7618e12b DJ |
1730 | else if (cache->pc != 0 |
1731 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1732 | { |
7618e12b DJ |
1733 | /* We're in a known function, but did not find a frame |
1734 | setup. Assume that the function does not use %ebp. | |
1735 | Alternatively, we may have jumped to an invalid | |
1736 | address; in that case there is definitely no new | |
1737 | frame in %ebp. */ | |
10458914 | 1738 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1739 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1740 | + cache->sp_offset; | |
92dd43fa | 1741 | } |
7618e12b DJ |
1742 | else |
1743 | /* We're in an unknown function. We could not find the start | |
1744 | of the function to analyze the prologue; our best option is | |
1745 | to assume a typical frame layout with the caller's %ebp | |
1746 | saved. */ | |
1747 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1748 | } |
1749 | ||
8fbca658 PA |
1750 | if (cache->saved_sp_reg != -1) |
1751 | { | |
1752 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1753 | register may be unavailable). */ | |
1754 | if (cache->saved_sp == 0 | |
1755 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) | |
1756 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1757 | } | |
acd5c798 MK |
1758 | /* Now that we have the base address for the stack frame we can |
1759 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1760 | else if (cache->saved_sp == 0) |
92dd43fa | 1761 | cache->saved_sp = cache->base + 8; |
a7769679 | 1762 | |
acd5c798 MK |
1763 | /* Adjust all the saved registers such that they contain addresses |
1764 | instead of offsets. */ | |
1765 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1766 | if (cache->saved_regs[i] != -1) |
1767 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1768 | |
8fbca658 PA |
1769 | cache->base_p = 1; |
1770 | } | |
1771 | ||
1772 | static struct i386_frame_cache * | |
1773 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1774 | { | |
1775 | volatile struct gdb_exception ex; | |
1776 | struct i386_frame_cache *cache; | |
1777 | ||
1778 | if (*this_cache) | |
1779 | return *this_cache; | |
1780 | ||
1781 | cache = i386_alloc_frame_cache (); | |
1782 | *this_cache = cache; | |
1783 | ||
1784 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1785 | { | |
1786 | i386_frame_cache_1 (this_frame, cache); | |
1787 | } | |
1788 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1789 | throw_exception (ex); | |
1790 | ||
acd5c798 | 1791 | return cache; |
a7769679 MK |
1792 | } |
1793 | ||
3a1e71e3 | 1794 | static void |
10458914 | 1795 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1796 | struct frame_id *this_id) |
c906108c | 1797 | { |
10458914 | 1798 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1799 | |
1800 | /* This marks the outermost frame. */ | |
1801 | if (cache->base == 0) | |
1802 | return; | |
1803 | ||
3e210248 | 1804 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1805 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1806 | } | |
1807 | ||
8fbca658 PA |
1808 | static enum unwind_stop_reason |
1809 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1810 | void **this_cache) | |
1811 | { | |
1812 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1813 | ||
1814 | if (!cache->base_p) | |
1815 | return UNWIND_UNAVAILABLE; | |
1816 | ||
1817 | /* This marks the outermost frame. */ | |
1818 | if (cache->base == 0) | |
1819 | return UNWIND_OUTERMOST; | |
1820 | ||
1821 | return UNWIND_NO_REASON; | |
1822 | } | |
1823 | ||
10458914 DJ |
1824 | static struct value * |
1825 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1826 | int regnum) | |
acd5c798 | 1827 | { |
10458914 | 1828 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1829 | |
1830 | gdb_assert (regnum >= 0); | |
1831 | ||
1832 | /* The System V ABI says that: | |
1833 | ||
1834 | "The flags register contains the system flags, such as the | |
1835 | direction flag and the carry flag. The direction flag must be | |
1836 | set to the forward (that is, zero) direction before entry and | |
1837 | upon exit from a function. Other user flags have no specified | |
1838 | role in the standard calling sequence and are not preserved." | |
1839 | ||
1840 | To guarantee the "upon exit" part of that statement we fake a | |
1841 | saved flags register that has its direction flag cleared. | |
1842 | ||
1843 | Note that GCC doesn't seem to rely on the fact that the direction | |
1844 | flag is cleared after a function return; it always explicitly | |
1845 | clears the flag before operations where it matters. | |
1846 | ||
1847 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1848 | right thing to do. The way we fake the flags register here makes | |
1849 | it impossible to change it. */ | |
1850 | ||
1851 | if (regnum == I386_EFLAGS_REGNUM) | |
1852 | { | |
10458914 | 1853 | ULONGEST val; |
c5aa993b | 1854 | |
10458914 DJ |
1855 | val = get_frame_register_unsigned (this_frame, regnum); |
1856 | val &= ~(1 << 10); | |
1857 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1858 | } |
1211c4e4 | 1859 | |
acd5c798 | 1860 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1861 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1862 | |
fcf250e2 UW |
1863 | if (regnum == I386_ESP_REGNUM |
1864 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1865 | { |
1866 | /* If the SP has been saved, but we don't know where, then this | |
1867 | means that SAVED_SP_REG register was found unavailable back | |
1868 | when we built the cache. */ | |
fcf250e2 | 1869 | if (cache->saved_sp == 0) |
8fbca658 PA |
1870 | return frame_unwind_got_register (this_frame, regnum, |
1871 | cache->saved_sp_reg); | |
1872 | else | |
1873 | return frame_unwind_got_constant (this_frame, regnum, | |
1874 | cache->saved_sp); | |
1875 | } | |
acd5c798 | 1876 | |
fd13a04a | 1877 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1878 | return frame_unwind_got_memory (this_frame, regnum, |
1879 | cache->saved_regs[regnum]); | |
fd13a04a | 1880 | |
10458914 | 1881 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1882 | } |
1883 | ||
1884 | static const struct frame_unwind i386_frame_unwind = | |
1885 | { | |
1886 | NORMAL_FRAME, | |
8fbca658 | 1887 | i386_frame_unwind_stop_reason, |
acd5c798 | 1888 | i386_frame_this_id, |
10458914 DJ |
1889 | i386_frame_prev_register, |
1890 | NULL, | |
1891 | default_frame_sniffer | |
acd5c798 | 1892 | }; |
06da04c6 MS |
1893 | |
1894 | /* Normal frames, but in a function epilogue. */ | |
1895 | ||
1896 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1897 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1898 | the function's stack frame. */ | |
1899 | ||
1900 | static int | |
1901 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1902 | { | |
1903 | gdb_byte insn; | |
e0d00bc7 JK |
1904 | struct symtab *symtab; |
1905 | ||
1906 | symtab = find_pc_symtab (pc); | |
1907 | if (symtab && symtab->epilogue_unwind_valid) | |
1908 | return 0; | |
06da04c6 MS |
1909 | |
1910 | if (target_read_memory (pc, &insn, 1)) | |
1911 | return 0; /* Can't read memory at pc. */ | |
1912 | ||
1913 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1914 | return 0; | |
1915 | ||
1916 | return 1; | |
1917 | } | |
1918 | ||
1919 | static int | |
1920 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1921 | struct frame_info *this_frame, | |
1922 | void **this_prologue_cache) | |
1923 | { | |
1924 | if (frame_relative_level (this_frame) == 0) | |
1925 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1926 | get_frame_pc (this_frame)); | |
1927 | else | |
1928 | return 0; | |
1929 | } | |
1930 | ||
1931 | static struct i386_frame_cache * | |
1932 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1933 | { | |
8fbca658 | 1934 | volatile struct gdb_exception ex; |
06da04c6 | 1935 | struct i386_frame_cache *cache; |
0d6c2135 | 1936 | CORE_ADDR sp; |
06da04c6 MS |
1937 | |
1938 | if (*this_cache) | |
1939 | return *this_cache; | |
1940 | ||
1941 | cache = i386_alloc_frame_cache (); | |
1942 | *this_cache = cache; | |
1943 | ||
8fbca658 PA |
1944 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1945 | { | |
0d6c2135 | 1946 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1947 | |
0d6c2135 MK |
1948 | /* At this point the stack looks as if we just entered the |
1949 | function, with the return address at the top of the | |
1950 | stack. */ | |
1951 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
1952 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 1953 | cache->saved_sp = cache->base + 8; |
8fbca658 | 1954 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 1955 | |
8fbca658 PA |
1956 | cache->base_p = 1; |
1957 | } | |
1958 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1959 | throw_exception (ex); | |
06da04c6 MS |
1960 | |
1961 | return cache; | |
1962 | } | |
1963 | ||
8fbca658 PA |
1964 | static enum unwind_stop_reason |
1965 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1966 | void **this_cache) | |
1967 | { | |
0d6c2135 MK |
1968 | struct i386_frame_cache *cache = |
1969 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
1970 | |
1971 | if (!cache->base_p) | |
1972 | return UNWIND_UNAVAILABLE; | |
1973 | ||
1974 | return UNWIND_NO_REASON; | |
1975 | } | |
1976 | ||
06da04c6 MS |
1977 | static void |
1978 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1979 | void **this_cache, | |
1980 | struct frame_id *this_id) | |
1981 | { | |
0d6c2135 MK |
1982 | struct i386_frame_cache *cache = |
1983 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 1984 | |
8fbca658 PA |
1985 | if (!cache->base_p) |
1986 | return; | |
1987 | ||
06da04c6 MS |
1988 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1989 | } | |
1990 | ||
0d6c2135 MK |
1991 | static struct value * |
1992 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
1993 | void **this_cache, int regnum) | |
1994 | { | |
1995 | /* Make sure we've initialized the cache. */ | |
1996 | i386_epilogue_frame_cache (this_frame, this_cache); | |
1997 | ||
1998 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
1999 | } | |
2000 | ||
06da04c6 MS |
2001 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2002 | { | |
2003 | NORMAL_FRAME, | |
8fbca658 | 2004 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2005 | i386_epilogue_frame_this_id, |
0d6c2135 | 2006 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2007 | NULL, |
2008 | i386_epilogue_frame_sniffer | |
2009 | }; | |
acd5c798 MK |
2010 | \f |
2011 | ||
a3fcb948 JG |
2012 | /* Stack-based trampolines. */ |
2013 | ||
2014 | /* These trampolines are used on cross x86 targets, when taking the | |
2015 | address of a nested function. When executing these trampolines, | |
2016 | no stack frame is set up, so we are in a similar situation as in | |
2017 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2018 | ||
2019 | /* Static chain passed in register. */ | |
2020 | ||
2021 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2022 | { | |
2023 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2024 | { 5, { 0xb8 }, { 0xfe } }, | |
2025 | ||
2026 | /* `jmp imm32' */ | |
2027 | { 5, { 0xe9 }, { 0xff } }, | |
2028 | ||
2029 | {0} | |
2030 | }; | |
2031 | ||
2032 | /* Static chain passed on stack (when regparm=3). */ | |
2033 | ||
2034 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2035 | { | |
2036 | /* `push imm32' */ | |
2037 | { 5, { 0x68 }, { 0xff } }, | |
2038 | ||
2039 | /* `jmp imm32' */ | |
2040 | { 5, { 0xe9 }, { 0xff } }, | |
2041 | ||
2042 | {0} | |
2043 | }; | |
2044 | ||
2045 | /* Return whether PC points inside a stack trampoline. */ | |
2046 | ||
2047 | static int | |
2048 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2049 | { | |
2050 | gdb_byte insn; | |
2c02bd72 | 2051 | const char *name; |
a3fcb948 JG |
2052 | |
2053 | /* A stack trampoline is detected if no name is associated | |
2054 | to the current pc and if it points inside a trampoline | |
2055 | sequence. */ | |
2056 | ||
2057 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2058 | if (name) | |
2059 | return 0; | |
2060 | ||
2061 | if (target_read_memory (pc, &insn, 1)) | |
2062 | return 0; | |
2063 | ||
2064 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2065 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2066 | return 0; | |
2067 | ||
2068 | return 1; | |
2069 | } | |
2070 | ||
2071 | static int | |
2072 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2073 | struct frame_info *this_frame, |
2074 | void **this_cache) | |
a3fcb948 JG |
2075 | { |
2076 | if (frame_relative_level (this_frame) == 0) | |
2077 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2078 | get_frame_pc (this_frame)); | |
2079 | else | |
2080 | return 0; | |
2081 | } | |
2082 | ||
2083 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2084 | { | |
2085 | NORMAL_FRAME, | |
2086 | i386_epilogue_frame_unwind_stop_reason, | |
2087 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2088 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2089 | NULL, |
2090 | i386_stack_tramp_frame_sniffer | |
2091 | }; | |
2092 | \f | |
6710bf39 SS |
2093 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2094 | ||
2095 | static void | |
2096 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2097 | struct agent_expr *ax, struct axs_value *value, | |
2098 | CORE_ADDR scope) | |
2099 | { | |
2100 | /* The following sequence assumes the traditional use of the base | |
2101 | register. */ | |
2102 | ax_reg (ax, I386_EBP_REGNUM); | |
2103 | ax_const_l (ax, 4); | |
2104 | ax_simple (ax, aop_add); | |
2105 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2106 | value->kind = axs_lvalue_memory; | |
2107 | } | |
2108 | \f | |
a3fcb948 | 2109 | |
acd5c798 MK |
2110 | /* Signal trampolines. */ |
2111 | ||
2112 | static struct i386_frame_cache * | |
10458914 | 2113 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2114 | { |
e17a4113 UW |
2115 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2116 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2117 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2118 | volatile struct gdb_exception ex; |
acd5c798 | 2119 | struct i386_frame_cache *cache; |
acd5c798 | 2120 | CORE_ADDR addr; |
63c0089f | 2121 | gdb_byte buf[4]; |
acd5c798 MK |
2122 | |
2123 | if (*this_cache) | |
2124 | return *this_cache; | |
2125 | ||
fd13a04a | 2126 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2127 | |
8fbca658 | 2128 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2129 | { |
8fbca658 PA |
2130 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2131 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2132 | |
8fbca658 PA |
2133 | addr = tdep->sigcontext_addr (this_frame); |
2134 | if (tdep->sc_reg_offset) | |
2135 | { | |
2136 | int i; | |
a3386186 | 2137 | |
8fbca658 PA |
2138 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2139 | ||
2140 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2141 | if (tdep->sc_reg_offset[i] != -1) | |
2142 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2143 | } | |
2144 | else | |
2145 | { | |
2146 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2147 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2148 | } | |
2149 | ||
2150 | cache->base_p = 1; | |
a3386186 | 2151 | } |
8fbca658 PA |
2152 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2153 | throw_exception (ex); | |
acd5c798 MK |
2154 | |
2155 | *this_cache = cache; | |
2156 | return cache; | |
2157 | } | |
2158 | ||
8fbca658 PA |
2159 | static enum unwind_stop_reason |
2160 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2161 | void **this_cache) | |
2162 | { | |
2163 | struct i386_frame_cache *cache = | |
2164 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2165 | ||
2166 | if (!cache->base_p) | |
2167 | return UNWIND_UNAVAILABLE; | |
2168 | ||
2169 | return UNWIND_NO_REASON; | |
2170 | } | |
2171 | ||
acd5c798 | 2172 | static void |
10458914 | 2173 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2174 | struct frame_id *this_id) |
2175 | { | |
2176 | struct i386_frame_cache *cache = | |
10458914 | 2177 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2178 | |
8fbca658 PA |
2179 | if (!cache->base_p) |
2180 | return; | |
2181 | ||
3e210248 | 2182 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2183 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2184 | } |
2185 | ||
10458914 DJ |
2186 | static struct value * |
2187 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2188 | void **this_cache, int regnum) | |
acd5c798 MK |
2189 | { |
2190 | /* Make sure we've initialized the cache. */ | |
10458914 | 2191 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2192 | |
10458914 | 2193 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2194 | } |
c0d1d883 | 2195 | |
10458914 DJ |
2196 | static int |
2197 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2198 | struct frame_info *this_frame, | |
2199 | void **this_prologue_cache) | |
acd5c798 | 2200 | { |
10458914 | 2201 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2202 | |
911bc6ee MK |
2203 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2204 | handler. */ | |
2205 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2206 | return 0; |
1c3545ae | 2207 | |
911bc6ee MK |
2208 | if (tdep->sigtramp_p != NULL) |
2209 | { | |
10458914 DJ |
2210 | if (tdep->sigtramp_p (this_frame)) |
2211 | return 1; | |
911bc6ee MK |
2212 | } |
2213 | ||
2214 | if (tdep->sigtramp_start != 0) | |
2215 | { | |
10458914 | 2216 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2217 | |
2218 | gdb_assert (tdep->sigtramp_end != 0); | |
2219 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2220 | return 1; |
911bc6ee | 2221 | } |
acd5c798 | 2222 | |
10458914 | 2223 | return 0; |
acd5c798 | 2224 | } |
10458914 DJ |
2225 | |
2226 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2227 | { | |
2228 | SIGTRAMP_FRAME, | |
8fbca658 | 2229 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2230 | i386_sigtramp_frame_this_id, |
2231 | i386_sigtramp_frame_prev_register, | |
2232 | NULL, | |
2233 | i386_sigtramp_frame_sniffer | |
2234 | }; | |
acd5c798 MK |
2235 | \f |
2236 | ||
2237 | static CORE_ADDR | |
10458914 | 2238 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2239 | { |
10458914 | 2240 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2241 | |
2242 | return cache->base; | |
2243 | } | |
2244 | ||
2245 | static const struct frame_base i386_frame_base = | |
2246 | { | |
2247 | &i386_frame_unwind, | |
2248 | i386_frame_base_address, | |
2249 | i386_frame_base_address, | |
2250 | i386_frame_base_address | |
2251 | }; | |
2252 | ||
acd5c798 | 2253 | static struct frame_id |
10458914 | 2254 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2255 | { |
acd5c798 MK |
2256 | CORE_ADDR fp; |
2257 | ||
10458914 | 2258 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2259 | |
3e210248 | 2260 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2261 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2262 | } |
e04e5beb JM |
2263 | |
2264 | /* _Decimal128 function return values need 16-byte alignment on the | |
2265 | stack. */ | |
2266 | ||
2267 | static CORE_ADDR | |
2268 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2269 | { | |
2270 | return sp & -(CORE_ADDR)16; | |
2271 | } | |
fc338970 | 2272 | \f |
c906108c | 2273 | |
fc338970 MK |
2274 | /* Figure out where the longjmp will land. Slurp the args out of the |
2275 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2276 | structure from which we extract the address that we will land at. |
28bcfd30 | 2277 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2278 | success. */ |
c906108c | 2279 | |
8201327c | 2280 | static int |
60ade65d | 2281 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2282 | { |
436675d3 | 2283 | gdb_byte buf[4]; |
c906108c | 2284 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2285 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2286 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2287 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2288 | |
8201327c MK |
2289 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2290 | longjmp will land. */ | |
2291 | if (jb_pc_offset == -1) | |
c906108c SS |
2292 | return 0; |
2293 | ||
436675d3 | 2294 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2295 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2296 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2297 | return 0; |
2298 | ||
e17a4113 | 2299 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2300 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2301 | return 0; |
c906108c | 2302 | |
e17a4113 | 2303 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2304 | return 1; |
2305 | } | |
fc338970 | 2306 | \f |
c906108c | 2307 | |
7ccc1c74 JM |
2308 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2309 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2310 | unions containing such types must be 16-byte-aligned; other | |
2311 | arguments are 4-byte-aligned. */ | |
2312 | ||
2313 | static int | |
2314 | i386_16_byte_align_p (struct type *type) | |
2315 | { | |
2316 | type = check_typedef (type); | |
2317 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2318 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2319 | && TYPE_LENGTH (type) == 16) | |
2320 | return 1; | |
2321 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2322 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2323 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2324 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2325 | { | |
2326 | int i; | |
2327 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2328 | { | |
2329 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2330 | return 1; | |
2331 | } | |
2332 | } | |
2333 | return 0; | |
2334 | } | |
2335 | ||
3a1e71e3 | 2336 | static CORE_ADDR |
7d9b040b | 2337 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2338 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2339 | struct value **args, CORE_ADDR sp, int struct_return, | |
2340 | CORE_ADDR struct_addr) | |
22f8ba57 | 2341 | { |
e17a4113 | 2342 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2343 | gdb_byte buf[4]; |
acd5c798 | 2344 | int i; |
7ccc1c74 JM |
2345 | int write_pass; |
2346 | int args_space = 0; | |
acd5c798 | 2347 | |
7ccc1c74 JM |
2348 | /* Determine the total space required for arguments and struct |
2349 | return address in a first pass (allowing for 16-byte-aligned | |
2350 | arguments), then push arguments in a second pass. */ | |
2351 | ||
2352 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2353 | { |
7ccc1c74 JM |
2354 | int args_space_used = 0; |
2355 | int have_16_byte_aligned_arg = 0; | |
2356 | ||
2357 | if (struct_return) | |
2358 | { | |
2359 | if (write_pass) | |
2360 | { | |
2361 | /* Push value address. */ | |
e17a4113 | 2362 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2363 | write_memory (sp, buf, 4); |
2364 | args_space_used += 4; | |
2365 | } | |
2366 | else | |
2367 | args_space += 4; | |
2368 | } | |
2369 | ||
2370 | for (i = 0; i < nargs; i++) | |
2371 | { | |
2372 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2373 | |
7ccc1c74 JM |
2374 | if (write_pass) |
2375 | { | |
2376 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2377 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2378 | |
7ccc1c74 JM |
2379 | write_memory (sp + args_space_used, |
2380 | value_contents_all (args[i]), len); | |
2381 | /* The System V ABI says that: | |
acd5c798 | 2382 | |
7ccc1c74 JM |
2383 | "An argument's size is increased, if necessary, to make it a |
2384 | multiple of [32-bit] words. This may require tail padding, | |
2385 | depending on the size of the argument." | |
22f8ba57 | 2386 | |
7ccc1c74 JM |
2387 | This makes sure the stack stays word-aligned. */ |
2388 | args_space_used += align_up (len, 4); | |
2389 | } | |
2390 | else | |
2391 | { | |
2392 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2393 | { | |
2394 | args_space = align_up (args_space, 16); | |
2395 | have_16_byte_aligned_arg = 1; | |
2396 | } | |
2397 | args_space += align_up (len, 4); | |
2398 | } | |
2399 | } | |
2400 | ||
2401 | if (!write_pass) | |
2402 | { | |
2403 | if (have_16_byte_aligned_arg) | |
2404 | args_space = align_up (args_space, 16); | |
2405 | sp -= args_space; | |
2406 | } | |
22f8ba57 MK |
2407 | } |
2408 | ||
acd5c798 MK |
2409 | /* Store return address. */ |
2410 | sp -= 4; | |
e17a4113 | 2411 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2412 | write_memory (sp, buf, 4); |
2413 | ||
2414 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2415 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2416 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2417 | ||
2418 | /* ...and fake a frame pointer. */ | |
2419 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2420 | ||
3e210248 AC |
2421 | /* MarkK wrote: This "+ 8" is all over the place: |
2422 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2423 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2424 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2425 | definition of the stack address of a frame. Otherwise frame id |
2426 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2427 | stack address *before* the function call as a frame's CFA. On |
2428 | the i386, when %ebp is used as a frame pointer, the offset | |
2429 | between the contents %ebp and the CFA as defined by GCC. */ | |
2430 | return sp + 8; | |
22f8ba57 MK |
2431 | } |
2432 | ||
1a309862 MK |
2433 | /* These registers are used for returning integers (and on some |
2434 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2435 | size and alignment match an integer type). */ |
acd5c798 MK |
2436 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2437 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2438 | |
c5e656c1 MK |
2439 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2440 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2441 | |
3a1e71e3 | 2442 | static void |
c5e656c1 | 2443 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2444 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2445 | { |
c5e656c1 | 2446 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2447 | int len = TYPE_LENGTH (type); |
63c0089f | 2448 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2449 | |
1e8d0a7b | 2450 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2451 | { |
5716833c | 2452 | if (tdep->st0_regnum < 0) |
1a309862 | 2453 | { |
8a3fe4f8 | 2454 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2455 | memset (valbuf, 0, len); |
ef9dff19 | 2456 | return; |
1a309862 MK |
2457 | } |
2458 | ||
c6ba6f0d MK |
2459 | /* Floating-point return values can be found in %st(0). Convert |
2460 | its contents to the desired type. This is probably not | |
2461 | exactly how it would happen on the target itself, but it is | |
2462 | the best we can do. */ | |
acd5c798 | 2463 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2464 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2465 | } |
2466 | else | |
c5aa993b | 2467 | { |
875f8d0e UW |
2468 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2469 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2470 | |
2471 | if (len <= low_size) | |
00f8375e | 2472 | { |
0818c12a | 2473 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2474 | memcpy (valbuf, buf, len); |
2475 | } | |
d4f3574e SS |
2476 | else if (len <= (low_size + high_size)) |
2477 | { | |
0818c12a | 2478 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2479 | memcpy (valbuf, buf, low_size); |
0818c12a | 2480 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2481 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2482 | } |
2483 | else | |
8e65ff28 | 2484 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2485 | _("Cannot extract return value of %d bytes long."), |
2486 | len); | |
c906108c SS |
2487 | } |
2488 | } | |
2489 | ||
c5e656c1 MK |
2490 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2491 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2492 | |
3a1e71e3 | 2493 | static void |
c5e656c1 | 2494 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2495 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2496 | { |
c5e656c1 | 2497 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2498 | int len = TYPE_LENGTH (type); |
2499 | ||
1e8d0a7b | 2500 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2501 | { |
3d7f4f49 | 2502 | ULONGEST fstat; |
63c0089f | 2503 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2504 | |
5716833c | 2505 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2506 | { |
8a3fe4f8 | 2507 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2508 | return; |
2509 | } | |
2510 | ||
635b0cc1 MK |
2511 | /* Returning floating-point values is a bit tricky. Apart from |
2512 | storing the return value in %st(0), we have to simulate the | |
2513 | state of the FPU at function return point. */ | |
2514 | ||
c6ba6f0d MK |
2515 | /* Convert the value found in VALBUF to the extended |
2516 | floating-point format used by the FPU. This is probably | |
2517 | not exactly how it would happen on the target itself, but | |
2518 | it is the best we can do. */ | |
27067745 | 2519 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2520 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2521 | |
635b0cc1 MK |
2522 | /* Set the top of the floating-point register stack to 7. The |
2523 | actual value doesn't really matter, but 7 is what a normal | |
2524 | function return would end up with if the program started out | |
2525 | with a freshly initialized FPU. */ | |
20a6ec49 | 2526 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2527 | fstat |= (7 << 11); |
20a6ec49 | 2528 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2529 | |
635b0cc1 MK |
2530 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2531 | the floating-point register stack to 7, the appropriate value | |
2532 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2533 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2534 | } |
2535 | else | |
2536 | { | |
875f8d0e UW |
2537 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2538 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2539 | |
2540 | if (len <= low_size) | |
3d7f4f49 | 2541 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2542 | else if (len <= (low_size + high_size)) |
2543 | { | |
3d7f4f49 MK |
2544 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2545 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2546 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2547 | } |
2548 | else | |
8e65ff28 | 2549 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2550 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2551 | } |
2552 | } | |
fc338970 | 2553 | \f |
ef9dff19 | 2554 | |
8201327c MK |
2555 | /* This is the variable that is set with "set struct-convention", and |
2556 | its legitimate values. */ | |
2557 | static const char default_struct_convention[] = "default"; | |
2558 | static const char pcc_struct_convention[] = "pcc"; | |
2559 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2560 | static const char *const valid_conventions[] = |
8201327c MK |
2561 | { |
2562 | default_struct_convention, | |
2563 | pcc_struct_convention, | |
2564 | reg_struct_convention, | |
2565 | NULL | |
2566 | }; | |
2567 | static const char *struct_convention = default_struct_convention; | |
2568 | ||
0e4377e1 JB |
2569 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2570 | a union type, or an array type, should be returned in registers | |
2571 | for architecture GDBARCH. */ | |
c5e656c1 | 2572 | |
8201327c | 2573 | static int |
c5e656c1 | 2574 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2575 | { |
c5e656c1 MK |
2576 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2577 | enum type_code code = TYPE_CODE (type); | |
2578 | int len = TYPE_LENGTH (type); | |
8201327c | 2579 | |
0e4377e1 JB |
2580 | gdb_assert (code == TYPE_CODE_STRUCT |
2581 | || code == TYPE_CODE_UNION | |
2582 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2583 | |
2584 | if (struct_convention == pcc_struct_convention | |
2585 | || (struct_convention == default_struct_convention | |
2586 | && tdep->struct_return == pcc_struct_return)) | |
2587 | return 0; | |
2588 | ||
9edde48e MK |
2589 | /* Structures consisting of a single `float', `double' or 'long |
2590 | double' member are returned in %st(0). */ | |
2591 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2592 | { | |
2593 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2594 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2595 | return (len == 4 || len == 8 || len == 12); | |
2596 | } | |
2597 | ||
c5e656c1 MK |
2598 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2599 | } | |
2600 | ||
2601 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2602 | should be returned. If it is supposed to be returned in registers, | |
2603 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2604 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2605 | from WRITEBUF into REGCACHE. */ | |
2606 | ||
2607 | static enum return_value_convention | |
c055b101 CV |
2608 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2609 | struct type *type, struct regcache *regcache, | |
2610 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2611 | { |
2612 | enum type_code code = TYPE_CODE (type); | |
2613 | ||
5daa78cc TJB |
2614 | if (((code == TYPE_CODE_STRUCT |
2615 | || code == TYPE_CODE_UNION | |
2616 | || code == TYPE_CODE_ARRAY) | |
2617 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2618 | /* 128-bit decimal float uses the struct return convention. */ | |
2619 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2620 | { |
2621 | /* The System V ABI says that: | |
2622 | ||
2623 | "A function that returns a structure or union also sets %eax | |
2624 | to the value of the original address of the caller's area | |
2625 | before it returns. Thus when the caller receives control | |
2626 | again, the address of the returned object resides in register | |
2627 | %eax and can be used to access the object." | |
2628 | ||
2629 | So the ABI guarantees that we can always find the return | |
2630 | value just after the function has returned. */ | |
2631 | ||
0e4377e1 JB |
2632 | /* Note that the ABI doesn't mention functions returning arrays, |
2633 | which is something possible in certain languages such as Ada. | |
2634 | In this case, the value is returned as if it was wrapped in | |
2635 | a record, so the convention applied to records also applies | |
2636 | to arrays. */ | |
2637 | ||
31db7b6c MK |
2638 | if (readbuf) |
2639 | { | |
2640 | ULONGEST addr; | |
2641 | ||
2642 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2643 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2644 | } | |
2645 | ||
2646 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2647 | } | |
c5e656c1 MK |
2648 | |
2649 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2650 | `float', `double' or 'long double' member. These structures are |
2651 | returned in %st(0). For these structures, we call ourselves | |
2652 | recursively, changing TYPE into the type of the first member of | |
2653 | the structure. Since that should work for all structures that | |
2654 | have only one member, we don't bother to check the member's type | |
2655 | here. */ | |
c5e656c1 MK |
2656 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2657 | { | |
2658 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2659 | return i386_return_value (gdbarch, func_type, type, regcache, |
2660 | readbuf, writebuf); | |
c5e656c1 MK |
2661 | } |
2662 | ||
2663 | if (readbuf) | |
2664 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2665 | if (writebuf) | |
2666 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2667 | |
c5e656c1 | 2668 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2669 | } |
2670 | \f | |
2671 | ||
27067745 UW |
2672 | struct type * |
2673 | i387_ext_type (struct gdbarch *gdbarch) | |
2674 | { | |
2675 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2676 | ||
2677 | if (!tdep->i387_ext_type) | |
90884b2b L |
2678 | { |
2679 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2680 | gdb_assert (tdep->i387_ext_type != NULL); | |
2681 | } | |
27067745 UW |
2682 | |
2683 | return tdep->i387_ext_type; | |
2684 | } | |
2685 | ||
c131fcee L |
2686 | /* Construct vector type for pseudo YMM registers. We can't use |
2687 | tdesc_find_type since YMM isn't described in target description. */ | |
2688 | ||
2689 | static struct type * | |
2690 | i386_ymm_type (struct gdbarch *gdbarch) | |
2691 | { | |
2692 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2693 | ||
2694 | if (!tdep->i386_ymm_type) | |
2695 | { | |
2696 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2697 | ||
2698 | /* The type we're building is this: */ | |
2699 | #if 0 | |
2700 | union __gdb_builtin_type_vec256i | |
2701 | { | |
2702 | int128_t uint128[2]; | |
2703 | int64_t v2_int64[4]; | |
2704 | int32_t v4_int32[8]; | |
2705 | int16_t v8_int16[16]; | |
2706 | int8_t v16_int8[32]; | |
2707 | double v2_double[4]; | |
2708 | float v4_float[8]; | |
2709 | }; | |
2710 | #endif | |
2711 | ||
2712 | struct type *t; | |
2713 | ||
2714 | t = arch_composite_type (gdbarch, | |
2715 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2716 | append_composite_type_field (t, "v8_float", | |
2717 | init_vector_type (bt->builtin_float, 8)); | |
2718 | append_composite_type_field (t, "v4_double", | |
2719 | init_vector_type (bt->builtin_double, 4)); | |
2720 | append_composite_type_field (t, "v32_int8", | |
2721 | init_vector_type (bt->builtin_int8, 32)); | |
2722 | append_composite_type_field (t, "v16_int16", | |
2723 | init_vector_type (bt->builtin_int16, 16)); | |
2724 | append_composite_type_field (t, "v8_int32", | |
2725 | init_vector_type (bt->builtin_int32, 8)); | |
2726 | append_composite_type_field (t, "v4_int64", | |
2727 | init_vector_type (bt->builtin_int64, 4)); | |
2728 | append_composite_type_field (t, "v2_int128", | |
2729 | init_vector_type (bt->builtin_int128, 2)); | |
2730 | ||
2731 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2732 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2733 | tdep->i386_ymm_type = t; |
2734 | } | |
2735 | ||
2736 | return tdep->i386_ymm_type; | |
2737 | } | |
2738 | ||
794ac428 | 2739 | /* Construct vector type for MMX registers. */ |
90884b2b | 2740 | static struct type * |
794ac428 UW |
2741 | i386_mmx_type (struct gdbarch *gdbarch) |
2742 | { | |
2743 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2744 | ||
2745 | if (!tdep->i386_mmx_type) | |
2746 | { | |
df4df182 UW |
2747 | const struct builtin_type *bt = builtin_type (gdbarch); |
2748 | ||
794ac428 UW |
2749 | /* The type we're building is this: */ |
2750 | #if 0 | |
2751 | union __gdb_builtin_type_vec64i | |
2752 | { | |
2753 | int64_t uint64; | |
2754 | int32_t v2_int32[2]; | |
2755 | int16_t v4_int16[4]; | |
2756 | int8_t v8_int8[8]; | |
2757 | }; | |
2758 | #endif | |
2759 | ||
2760 | struct type *t; | |
2761 | ||
e9bb382b UW |
2762 | t = arch_composite_type (gdbarch, |
2763 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2764 | |
2765 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2766 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2767 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2768 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2769 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2770 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2771 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2772 | |
876cecd0 | 2773 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2774 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2775 | tdep->i386_mmx_type = t; | |
2776 | } | |
2777 | ||
2778 | return tdep->i386_mmx_type; | |
2779 | } | |
2780 | ||
d7a0d72c | 2781 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2782 | register REGNUM. */ |
d7a0d72c | 2783 | |
3a1e71e3 | 2784 | static struct type * |
90884b2b | 2785 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2786 | { |
1ba53b71 L |
2787 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2788 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2789 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2790 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2791 | else |
2792 | { | |
2793 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2794 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2795 | return bt->builtin_int8; | |
2796 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2797 | return bt->builtin_int16; | |
2798 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2799 | return bt->builtin_int32; | |
2800 | } | |
2801 | ||
2802 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2803 | } |
2804 | ||
28fc6740 | 2805 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2806 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2807 | |
2808 | static int | |
c86c27af | 2809 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2810 | { |
5716833c MK |
2811 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2812 | int mmxreg, fpreg; | |
28fc6740 AC |
2813 | ULONGEST fstat; |
2814 | int tos; | |
c86c27af | 2815 | |
5716833c | 2816 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2817 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2818 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2819 | fpreg = (mmxreg + tos) % 8; |
2820 | ||
20a6ec49 | 2821 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2822 | } |
2823 | ||
3543a589 TT |
2824 | /* A helper function for us by i386_pseudo_register_read_value and |
2825 | amd64_pseudo_register_read_value. It does all the work but reads | |
2826 | the data into an already-allocated value. */ | |
2827 | ||
2828 | void | |
2829 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
2830 | struct regcache *regcache, | |
2831 | int regnum, | |
2832 | struct value *result_value) | |
28fc6740 | 2833 | { |
1ba53b71 | 2834 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2835 | enum register_status status; |
3543a589 | 2836 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 2837 | |
5716833c | 2838 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2839 | { |
c86c27af MK |
2840 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2841 | ||
28fc6740 | 2842 | /* Extract (always little endian). */ |
05d1431c PA |
2843 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2844 | if (status != REG_VALID) | |
3543a589 TT |
2845 | mark_value_bytes_unavailable (result_value, 0, |
2846 | TYPE_LENGTH (value_type (result_value))); | |
2847 | else | |
2848 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2849 | } |
2850 | else | |
1ba53b71 L |
2851 | { |
2852 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2853 | ||
c131fcee L |
2854 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2855 | { | |
2856 | regnum -= tdep->ymm0_regnum; | |
2857 | ||
1777feb0 | 2858 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2859 | status = regcache_raw_read (regcache, |
2860 | I387_XMM0_REGNUM (tdep) + regnum, | |
2861 | raw_buf); | |
2862 | if (status != REG_VALID) | |
3543a589 TT |
2863 | mark_value_bytes_unavailable (result_value, 0, 16); |
2864 | else | |
2865 | memcpy (buf, raw_buf, 16); | |
c131fcee | 2866 | /* Read upper 128bits. */ |
05d1431c PA |
2867 | status = regcache_raw_read (regcache, |
2868 | tdep->ymm0h_regnum + regnum, | |
2869 | raw_buf); | |
2870 | if (status != REG_VALID) | |
3543a589 TT |
2871 | mark_value_bytes_unavailable (result_value, 16, 32); |
2872 | else | |
2873 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
2874 | } |
2875 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2876 | { |
2877 | int gpnum = regnum - tdep->ax_regnum; | |
2878 | ||
2879 | /* Extract (always little endian). */ | |
05d1431c PA |
2880 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2881 | if (status != REG_VALID) | |
3543a589 TT |
2882 | mark_value_bytes_unavailable (result_value, 0, |
2883 | TYPE_LENGTH (value_type (result_value))); | |
2884 | else | |
2885 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
2886 | } |
2887 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2888 | { | |
2889 | /* Check byte pseudo registers last since this function will | |
2890 | be called from amd64_pseudo_register_read, which handles | |
2891 | byte pseudo registers differently. */ | |
2892 | int gpnum = regnum - tdep->al_regnum; | |
2893 | ||
2894 | /* Extract (always little endian). We read both lower and | |
2895 | upper registers. */ | |
05d1431c PA |
2896 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2897 | if (status != REG_VALID) | |
3543a589 TT |
2898 | mark_value_bytes_unavailable (result_value, 0, |
2899 | TYPE_LENGTH (value_type (result_value))); | |
2900 | else if (gpnum >= 4) | |
1ba53b71 L |
2901 | memcpy (buf, raw_buf + 1, 1); |
2902 | else | |
2903 | memcpy (buf, raw_buf, 1); | |
2904 | } | |
2905 | else | |
2906 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2907 | } | |
3543a589 TT |
2908 | } |
2909 | ||
2910 | static struct value * | |
2911 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
2912 | struct regcache *regcache, | |
2913 | int regnum) | |
2914 | { | |
2915 | struct value *result; | |
2916 | ||
2917 | result = allocate_value (register_type (gdbarch, regnum)); | |
2918 | VALUE_LVAL (result) = lval_register; | |
2919 | VALUE_REGNUM (result) = regnum; | |
2920 | ||
2921 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 2922 | |
3543a589 | 2923 | return result; |
28fc6740 AC |
2924 | } |
2925 | ||
1ba53b71 | 2926 | void |
28fc6740 | 2927 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2928 | int regnum, const gdb_byte *buf) |
28fc6740 | 2929 | { |
1ba53b71 L |
2930 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2931 | ||
5716833c | 2932 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2933 | { |
c86c27af MK |
2934 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2935 | ||
28fc6740 | 2936 | /* Read ... */ |
1ba53b71 | 2937 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2938 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2939 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2940 | /* ... Write. */ |
1ba53b71 | 2941 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2942 | } |
2943 | else | |
1ba53b71 L |
2944 | { |
2945 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2946 | ||
c131fcee L |
2947 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2948 | { | |
2949 | regnum -= tdep->ymm0_regnum; | |
2950 | ||
2951 | /* ... Write lower 128bits. */ | |
2952 | regcache_raw_write (regcache, | |
2953 | I387_XMM0_REGNUM (tdep) + regnum, | |
2954 | buf); | |
2955 | /* ... Write upper 128bits. */ | |
2956 | regcache_raw_write (regcache, | |
2957 | tdep->ymm0h_regnum + regnum, | |
2958 | buf + 16); | |
2959 | } | |
2960 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2961 | { |
2962 | int gpnum = regnum - tdep->ax_regnum; | |
2963 | ||
2964 | /* Read ... */ | |
2965 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2966 | /* ... Modify ... (always little endian). */ | |
2967 | memcpy (raw_buf, buf, 2); | |
2968 | /* ... Write. */ | |
2969 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2970 | } | |
2971 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2972 | { | |
2973 | /* Check byte pseudo registers last since this function will | |
2974 | be called from amd64_pseudo_register_read, which handles | |
2975 | byte pseudo registers differently. */ | |
2976 | int gpnum = regnum - tdep->al_regnum; | |
2977 | ||
2978 | /* Read ... We read both lower and upper registers. */ | |
2979 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2980 | /* ... Modify ... (always little endian). */ | |
2981 | if (gpnum >= 4) | |
2982 | memcpy (raw_buf + 1, buf, 1); | |
2983 | else | |
2984 | memcpy (raw_buf, buf, 1); | |
2985 | /* ... Write. */ | |
2986 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2987 | } | |
2988 | else | |
2989 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2990 | } | |
28fc6740 | 2991 | } |
ff2e87ac AC |
2992 | \f |
2993 | ||
ff2e87ac AC |
2994 | /* Return the register number of the register allocated by GCC after |
2995 | REGNUM, or -1 if there is no such register. */ | |
2996 | ||
2997 | static int | |
2998 | i386_next_regnum (int regnum) | |
2999 | { | |
3000 | /* GCC allocates the registers in the order: | |
3001 | ||
3002 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3003 | ||
3004 | Since storing a variable in %esp doesn't make any sense we return | |
3005 | -1 for %ebp and for %esp itself. */ | |
3006 | static int next_regnum[] = | |
3007 | { | |
3008 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3009 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3010 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3011 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3012 | -1, -1, /* Slots for %esp and %ebp. */ | |
3013 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3014 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3015 | }; | |
3016 | ||
de5b9bb9 | 3017 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3018 | return next_regnum[regnum]; |
28fc6740 | 3019 | |
ff2e87ac AC |
3020 | return -1; |
3021 | } | |
3022 | ||
3023 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3024 | needs any special handling. */ | |
d7a0d72c | 3025 | |
3a1e71e3 | 3026 | static int |
1777feb0 MS |
3027 | i386_convert_register_p (struct gdbarch *gdbarch, |
3028 | int regnum, struct type *type) | |
d7a0d72c | 3029 | { |
de5b9bb9 MK |
3030 | int len = TYPE_LENGTH (type); |
3031 | ||
ff2e87ac AC |
3032 | /* Values may be spread across multiple registers. Most debugging |
3033 | formats aren't expressive enough to specify the locations, so | |
3034 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3035 | have a length that is a multiple of the word size, since GCC |
3036 | doesn't seem to put any other types into registers. */ | |
3037 | if (len > 4 && len % 4 == 0) | |
3038 | { | |
3039 | int last_regnum = regnum; | |
3040 | ||
3041 | while (len > 4) | |
3042 | { | |
3043 | last_regnum = i386_next_regnum (last_regnum); | |
3044 | len -= 4; | |
3045 | } | |
3046 | ||
3047 | if (last_regnum != -1) | |
3048 | return 1; | |
3049 | } | |
ff2e87ac | 3050 | |
0abe36f5 | 3051 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3052 | } |
3053 | ||
ff2e87ac AC |
3054 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3055 | return its contents in TO. */ | |
ac27f131 | 3056 | |
8dccd430 | 3057 | static int |
ff2e87ac | 3058 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3059 | struct type *type, gdb_byte *to, |
3060 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3061 | { |
20a6ec49 | 3062 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3063 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3064 | |
20a6ec49 | 3065 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3066 | return i387_register_to_value (frame, regnum, type, to, |
3067 | optimizedp, unavailablep); | |
ff2e87ac | 3068 | |
fd35795f | 3069 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3070 | |
3071 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3072 | |
de5b9bb9 MK |
3073 | while (len > 0) |
3074 | { | |
3075 | gdb_assert (regnum != -1); | |
20a6ec49 | 3076 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3077 | |
8dccd430 PA |
3078 | if (!get_frame_register_bytes (frame, regnum, 0, |
3079 | register_size (gdbarch, regnum), | |
3080 | to, optimizedp, unavailablep)) | |
3081 | return 0; | |
3082 | ||
de5b9bb9 MK |
3083 | regnum = i386_next_regnum (regnum); |
3084 | len -= 4; | |
42835c2b | 3085 | to += 4; |
de5b9bb9 | 3086 | } |
8dccd430 PA |
3087 | |
3088 | *optimizedp = *unavailablep = 0; | |
3089 | return 1; | |
ac27f131 MK |
3090 | } |
3091 | ||
ff2e87ac AC |
3092 | /* Write the contents FROM of a value of type TYPE into register |
3093 | REGNUM in frame FRAME. */ | |
ac27f131 | 3094 | |
3a1e71e3 | 3095 | static void |
ff2e87ac | 3096 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3097 | struct type *type, const gdb_byte *from) |
ac27f131 | 3098 | { |
de5b9bb9 | 3099 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3100 | |
20a6ec49 | 3101 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3102 | { |
d532c08f MK |
3103 | i387_value_to_register (frame, regnum, type, from); |
3104 | return; | |
3105 | } | |
3d261580 | 3106 | |
fd35795f | 3107 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3108 | |
3109 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3110 | |
de5b9bb9 MK |
3111 | while (len > 0) |
3112 | { | |
3113 | gdb_assert (regnum != -1); | |
875f8d0e | 3114 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3115 | |
42835c2b | 3116 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3117 | regnum = i386_next_regnum (regnum); |
3118 | len -= 4; | |
42835c2b | 3119 | from += 4; |
de5b9bb9 | 3120 | } |
ac27f131 | 3121 | } |
ff2e87ac | 3122 | \f |
7fdafb5a MK |
3123 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3124 | in the general-purpose register set REGSET to register cache | |
3125 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3126 | |
20187ed5 | 3127 | void |
473f17b0 MK |
3128 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3129 | int regnum, const void *gregs, size_t len) | |
3130 | { | |
9ea75c57 | 3131 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3132 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3133 | int i; |
3134 | ||
3135 | gdb_assert (len == tdep->sizeof_gregset); | |
3136 | ||
3137 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3138 | { | |
3139 | if ((regnum == i || regnum == -1) | |
3140 | && tdep->gregset_reg_offset[i] != -1) | |
3141 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3142 | } | |
3143 | } | |
3144 | ||
7fdafb5a MK |
3145 | /* Collect register REGNUM from the register cache REGCACHE and store |
3146 | it in the buffer specified by GREGS and LEN as described by the | |
3147 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3148 | all registers in REGSET. */ | |
3149 | ||
3150 | void | |
3151 | i386_collect_gregset (const struct regset *regset, | |
3152 | const struct regcache *regcache, | |
3153 | int regnum, void *gregs, size_t len) | |
3154 | { | |
3155 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3156 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3157 | int i; |
3158 | ||
3159 | gdb_assert (len == tdep->sizeof_gregset); | |
3160 | ||
3161 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3162 | { | |
3163 | if ((regnum == i || regnum == -1) | |
3164 | && tdep->gregset_reg_offset[i] != -1) | |
3165 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3166 | } | |
3167 | } | |
3168 | ||
3169 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3170 | in the floating-point register set REGSET to register cache | |
3171 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3172 | |
3173 | static void | |
3174 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3175 | int regnum, const void *fpregs, size_t len) | |
3176 | { | |
9ea75c57 | 3177 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3178 | |
66a72d25 MK |
3179 | if (len == I387_SIZEOF_FXSAVE) |
3180 | { | |
3181 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3182 | return; | |
3183 | } | |
3184 | ||
473f17b0 MK |
3185 | gdb_assert (len == tdep->sizeof_fpregset); |
3186 | i387_supply_fsave (regcache, regnum, fpregs); | |
3187 | } | |
8446b36a | 3188 | |
2f305df1 MK |
3189 | /* Collect register REGNUM from the register cache REGCACHE and store |
3190 | it in the buffer specified by FPREGS and LEN as described by the | |
3191 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3192 | all registers in REGSET. */ | |
7fdafb5a MK |
3193 | |
3194 | static void | |
3195 | i386_collect_fpregset (const struct regset *regset, | |
3196 | const struct regcache *regcache, | |
3197 | int regnum, void *fpregs, size_t len) | |
3198 | { | |
3199 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3200 | ||
3201 | if (len == I387_SIZEOF_FXSAVE) | |
3202 | { | |
3203 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3204 | return; | |
3205 | } | |
3206 | ||
3207 | gdb_assert (len == tdep->sizeof_fpregset); | |
3208 | i387_collect_fsave (regcache, regnum, fpregs); | |
3209 | } | |
3210 | ||
c131fcee L |
3211 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3212 | ||
3213 | static void | |
3214 | i386_supply_xstateregset (const struct regset *regset, | |
3215 | struct regcache *regcache, int regnum, | |
3216 | const void *xstateregs, size_t len) | |
3217 | { | |
c131fcee L |
3218 | i387_supply_xsave (regcache, regnum, xstateregs); |
3219 | } | |
3220 | ||
3221 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3222 | ||
3223 | static void | |
3224 | i386_collect_xstateregset (const struct regset *regset, | |
3225 | const struct regcache *regcache, | |
3226 | int regnum, void *xstateregs, size_t len) | |
3227 | { | |
c131fcee L |
3228 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3229 | } | |
3230 | ||
8446b36a MK |
3231 | /* Return the appropriate register set for the core section identified |
3232 | by SECT_NAME and SECT_SIZE. */ | |
3233 | ||
3234 | const struct regset * | |
3235 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3236 | const char *sect_name, size_t sect_size) | |
3237 | { | |
3238 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3239 | ||
3240 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3241 | { | |
3242 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3243 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3244 | i386_collect_gregset); | |
8446b36a MK |
3245 | return tdep->gregset; |
3246 | } | |
3247 | ||
66a72d25 MK |
3248 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3249 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3250 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3251 | { |
3252 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3253 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3254 | i386_collect_fpregset); | |
8446b36a MK |
3255 | return tdep->fpregset; |
3256 | } | |
3257 | ||
c131fcee L |
3258 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3259 | { | |
3260 | if (tdep->xstateregset == NULL) | |
3261 | tdep->xstateregset = regset_alloc (gdbarch, | |
3262 | i386_supply_xstateregset, | |
3263 | i386_collect_xstateregset); | |
3264 | ||
3265 | return tdep->xstateregset; | |
3266 | } | |
3267 | ||
8446b36a MK |
3268 | return NULL; |
3269 | } | |
473f17b0 | 3270 | \f |
fc338970 | 3271 | |
fc338970 | 3272 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3273 | |
3274 | CORE_ADDR | |
e17a4113 UW |
3275 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3276 | CORE_ADDR pc, char *name) | |
c906108c | 3277 | { |
e17a4113 UW |
3278 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3279 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3280 | ||
3281 | /* jmp *(dest) */ | |
3282 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3283 | { |
e17a4113 UW |
3284 | unsigned long indirect = |
3285 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3286 | struct minimal_symbol *indsym = |
fc338970 | 3287 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
0d5cff50 | 3288 | const char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3289 | |
c5aa993b | 3290 | if (symname) |
c906108c | 3291 | { |
c5aa993b JM |
3292 | if (strncmp (symname, "__imp_", 6) == 0 |
3293 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3294 | return name ? 1 : |
3295 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3296 | } |
3297 | } | |
fc338970 | 3298 | return 0; /* Not a trampoline. */ |
c906108c | 3299 | } |
fc338970 MK |
3300 | \f |
3301 | ||
10458914 DJ |
3302 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3303 | routine. */ | |
8201327c | 3304 | |
4bd207ef | 3305 | int |
10458914 | 3306 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3307 | { |
10458914 | 3308 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3309 | const char *name; |
911bc6ee MK |
3310 | |
3311 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3312 | return (name && strcmp ("_sigtramp", name) == 0); |
3313 | } | |
3314 | \f | |
3315 | ||
fc338970 MK |
3316 | /* We have two flavours of disassembly. The machinery on this page |
3317 | deals with switching between those. */ | |
c906108c SS |
3318 | |
3319 | static int | |
a89aa300 | 3320 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3321 | { |
5e3397bb MK |
3322 | gdb_assert (disassembly_flavor == att_flavor |
3323 | || disassembly_flavor == intel_flavor); | |
3324 | ||
3325 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3326 | constified, cast to prevent a compiler warning. */ | |
3327 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3328 | |
3329 | return print_insn_i386 (pc, info); | |
7a292a7a | 3330 | } |
fc338970 | 3331 | \f |
3ce1502b | 3332 | |
8201327c MK |
3333 | /* There are a few i386 architecture variants that differ only |
3334 | slightly from the generic i386 target. For now, we don't give them | |
3335 | their own source file, but include them here. As a consequence, | |
3336 | they'll always be included. */ | |
3ce1502b | 3337 | |
8201327c | 3338 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3339 | |
10458914 DJ |
3340 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3341 | routine. */ | |
911bc6ee | 3342 | |
8201327c | 3343 | static int |
10458914 | 3344 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3345 | { |
10458914 | 3346 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3347 | const char *name; |
911bc6ee | 3348 | |
acd5c798 MK |
3349 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3350 | currently unknown. */ | |
911bc6ee | 3351 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3352 | return (name && (strcmp ("_sigreturn", name) == 0 |
3353 | || strcmp ("_sigacthandler", name) == 0 | |
3354 | || strcmp ("sigvechandler", name) == 0)); | |
3355 | } | |
d2a7c97a | 3356 | |
10458914 DJ |
3357 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3358 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3359 | |
3a1e71e3 | 3360 | static CORE_ADDR |
10458914 | 3361 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3362 | { |
e17a4113 UW |
3363 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3364 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3365 | gdb_byte buf[4]; |
acd5c798 | 3366 | CORE_ADDR sp; |
3ce1502b | 3367 | |
10458914 | 3368 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3369 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3370 | |
e17a4113 | 3371 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3372 | } |
55aa24fb SDJ |
3373 | |
3374 | \f | |
3375 | ||
3376 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3377 | gdbarch.h. */ | |
3378 | ||
3379 | int | |
3380 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3381 | { | |
3382 | return (*s == '$' /* Literal number. */ | |
3383 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3384 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3385 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3386 | } | |
3387 | ||
3388 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in | |
3389 | gdbarch.h. */ | |
3390 | ||
3391 | int | |
3392 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
3393 | struct stap_parse_info *p) | |
3394 | { | |
55aa24fb SDJ |
3395 | /* In order to parse special tokens, we use a state-machine that go |
3396 | through every known token and try to get a match. */ | |
3397 | enum | |
3398 | { | |
3399 | TRIPLET, | |
3400 | THREE_ARG_DISPLACEMENT, | |
3401 | DONE | |
3402 | } current_state; | |
3403 | ||
3404 | current_state = TRIPLET; | |
3405 | ||
3406 | /* The special tokens to be parsed here are: | |
3407 | ||
3408 | - `register base + (register index * size) + offset', as represented | |
3409 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
3410 | ||
3411 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
3412 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
3413 | ||
3414 | while (current_state != DONE) | |
3415 | { | |
3416 | const char *s = p->arg; | |
3417 | ||
3418 | switch (current_state) | |
3419 | { | |
3420 | case TRIPLET: | |
3421 | { | |
3422 | if (isdigit (*s) || *s == '-' || *s == '+') | |
3423 | { | |
3424 | int got_minus[3]; | |
3425 | int i; | |
3426 | long displacements[3]; | |
3427 | const char *start; | |
3428 | char *regname; | |
3429 | int len; | |
3430 | struct stoken str; | |
3431 | ||
3432 | got_minus[0] = 0; | |
3433 | if (*s == '+') | |
3434 | ++s; | |
3435 | else if (*s == '-') | |
3436 | { | |
3437 | ++s; | |
3438 | got_minus[0] = 1; | |
3439 | } | |
3440 | ||
3441 | displacements[0] = strtol (s, (char **) &s, 10); | |
3442 | ||
3443 | if (*s != '+' && *s != '-') | |
3444 | { | |
3445 | /* We are not dealing with a triplet. */ | |
3446 | break; | |
3447 | } | |
3448 | ||
3449 | got_minus[1] = 0; | |
3450 | if (*s == '+') | |
3451 | ++s; | |
3452 | else | |
3453 | { | |
3454 | ++s; | |
3455 | got_minus[1] = 1; | |
3456 | } | |
3457 | ||
3458 | displacements[1] = strtol (s, (char **) &s, 10); | |
3459 | ||
3460 | if (*s != '+' && *s != '-') | |
3461 | { | |
3462 | /* We are not dealing with a triplet. */ | |
3463 | break; | |
3464 | } | |
3465 | ||
3466 | got_minus[2] = 0; | |
3467 | if (*s == '+') | |
3468 | ++s; | |
3469 | else | |
3470 | { | |
3471 | ++s; | |
3472 | got_minus[2] = 1; | |
3473 | } | |
3474 | ||
3475 | displacements[2] = strtol (s, (char **) &s, 10); | |
3476 | ||
3477 | if (*s != '(' || s[1] != '%') | |
3478 | break; | |
3479 | ||
3480 | s += 2; | |
3481 | start = s; | |
3482 | ||
3483 | while (isalnum (*s)) | |
3484 | ++s; | |
3485 | ||
3486 | if (*s++ != ')') | |
3487 | break; | |
3488 | ||
3489 | len = s - start; | |
3490 | regname = alloca (len + 1); | |
3491 | ||
3492 | strncpy (regname, start, len); | |
3493 | regname[len] = '\0'; | |
3494 | ||
3495 | if (user_reg_map_name_to_regnum (gdbarch, | |
3496 | regname, len) == -1) | |
3497 | error (_("Invalid register name `%s' " | |
3498 | "on expression `%s'."), | |
3499 | regname, p->saved_arg); | |
3500 | ||
3501 | for (i = 0; i < 3; i++) | |
3502 | { | |
3503 | write_exp_elt_opcode (OP_LONG); | |
3504 | write_exp_elt_type | |
3505 | (builtin_type (gdbarch)->builtin_long); | |
3506 | write_exp_elt_longcst (displacements[i]); | |
3507 | write_exp_elt_opcode (OP_LONG); | |
3508 | if (got_minus[i]) | |
3509 | write_exp_elt_opcode (UNOP_NEG); | |
3510 | } | |
3511 | ||
3512 | write_exp_elt_opcode (OP_REGISTER); | |
3513 | str.ptr = regname; | |
3514 | str.length = len; | |
3515 | write_exp_string (str); | |
3516 | write_exp_elt_opcode (OP_REGISTER); | |
3517 | ||
3518 | write_exp_elt_opcode (UNOP_CAST); | |
3519 | write_exp_elt_type (builtin_type (gdbarch)->builtin_data_ptr); | |
3520 | write_exp_elt_opcode (UNOP_CAST); | |
3521 | ||
3522 | write_exp_elt_opcode (BINOP_ADD); | |
3523 | write_exp_elt_opcode (BINOP_ADD); | |
3524 | write_exp_elt_opcode (BINOP_ADD); | |
3525 | ||
3526 | write_exp_elt_opcode (UNOP_CAST); | |
3527 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3528 | write_exp_elt_opcode (UNOP_CAST); | |
3529 | ||
3530 | write_exp_elt_opcode (UNOP_IND); | |
3531 | ||
3532 | p->arg = s; | |
3533 | ||
3534 | return 1; | |
3535 | } | |
3536 | break; | |
3537 | } | |
3538 | case THREE_ARG_DISPLACEMENT: | |
3539 | { | |
3540 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
3541 | { | |
3542 | int offset_minus = 0; | |
3543 | long offset = 0; | |
3544 | int size_minus = 0; | |
3545 | long size = 0; | |
3546 | const char *start; | |
3547 | char *base; | |
3548 | int len_base; | |
3549 | char *index; | |
3550 | int len_index; | |
3551 | struct stoken base_token, index_token; | |
3552 | ||
3553 | if (*s == '+') | |
3554 | ++s; | |
3555 | else if (*s == '-') | |
3556 | { | |
3557 | ++s; | |
3558 | offset_minus = 1; | |
3559 | } | |
3560 | ||
3561 | if (offset_minus && !isdigit (*s)) | |
3562 | break; | |
3563 | ||
3564 | if (isdigit (*s)) | |
3565 | offset = strtol (s, (char **) &s, 10); | |
3566 | ||
3567 | if (*s != '(' || s[1] != '%') | |
3568 | break; | |
3569 | ||
3570 | s += 2; | |
3571 | start = s; | |
3572 | ||
3573 | while (isalnum (*s)) | |
3574 | ++s; | |
3575 | ||
3576 | if (*s != ',' || s[1] != '%') | |
3577 | break; | |
3578 | ||
3579 | len_base = s - start; | |
3580 | base = alloca (len_base + 1); | |
3581 | strncpy (base, start, len_base); | |
3582 | base[len_base] = '\0'; | |
3583 | ||
3584 | if (user_reg_map_name_to_regnum (gdbarch, | |
3585 | base, len_base) == -1) | |
3586 | error (_("Invalid register name `%s' " | |
3587 | "on expression `%s'."), | |
3588 | base, p->saved_arg); | |
3589 | ||
3590 | s += 2; | |
3591 | start = s; | |
3592 | ||
3593 | while (isalnum (*s)) | |
3594 | ++s; | |
3595 | ||
3596 | len_index = s - start; | |
3597 | index = alloca (len_index + 1); | |
3598 | strncpy (index, start, len_index); | |
3599 | index[len_index] = '\0'; | |
3600 | ||
3601 | if (user_reg_map_name_to_regnum (gdbarch, | |
3602 | index, len_index) == -1) | |
3603 | error (_("Invalid register name `%s' " | |
3604 | "on expression `%s'."), | |
3605 | index, p->saved_arg); | |
3606 | ||
3607 | if (*s != ',' && *s != ')') | |
3608 | break; | |
3609 | ||
3610 | if (*s == ',') | |
3611 | { | |
3612 | ++s; | |
3613 | if (*s == '+') | |
3614 | ++s; | |
3615 | else if (*s == '-') | |
3616 | { | |
3617 | ++s; | |
3618 | size_minus = 1; | |
3619 | } | |
3620 | ||
3621 | size = strtol (s, (char **) &s, 10); | |
3622 | ||
3623 | if (*s != ')') | |
3624 | break; | |
3625 | } | |
3626 | ||
3627 | ++s; | |
3628 | ||
3629 | if (offset) | |
3630 | { | |
3631 | write_exp_elt_opcode (OP_LONG); | |
3632 | write_exp_elt_type | |
3633 | (builtin_type (gdbarch)->builtin_long); | |
3634 | write_exp_elt_longcst (offset); | |
3635 | write_exp_elt_opcode (OP_LONG); | |
3636 | if (offset_minus) | |
3637 | write_exp_elt_opcode (UNOP_NEG); | |
3638 | } | |
3639 | ||
3640 | write_exp_elt_opcode (OP_REGISTER); | |
3641 | base_token.ptr = base; | |
3642 | base_token.length = len_base; | |
3643 | write_exp_string (base_token); | |
3644 | write_exp_elt_opcode (OP_REGISTER); | |
3645 | ||
3646 | if (offset) | |
3647 | write_exp_elt_opcode (BINOP_ADD); | |
3648 | ||
3649 | write_exp_elt_opcode (OP_REGISTER); | |
3650 | index_token.ptr = index; | |
3651 | index_token.length = len_index; | |
3652 | write_exp_string (index_token); | |
3653 | write_exp_elt_opcode (OP_REGISTER); | |
3654 | ||
3655 | if (size) | |
3656 | { | |
3657 | write_exp_elt_opcode (OP_LONG); | |
3658 | write_exp_elt_type | |
3659 | (builtin_type (gdbarch)->builtin_long); | |
3660 | write_exp_elt_longcst (size); | |
3661 | write_exp_elt_opcode (OP_LONG); | |
3662 | if (size_minus) | |
3663 | write_exp_elt_opcode (UNOP_NEG); | |
3664 | write_exp_elt_opcode (BINOP_MUL); | |
3665 | } | |
3666 | ||
3667 | write_exp_elt_opcode (BINOP_ADD); | |
3668 | ||
3669 | write_exp_elt_opcode (UNOP_CAST); | |
3670 | write_exp_elt_type (lookup_pointer_type (p->arg_type)); | |
3671 | write_exp_elt_opcode (UNOP_CAST); | |
3672 | ||
3673 | write_exp_elt_opcode (UNOP_IND); | |
3674 | ||
3675 | p->arg = s; | |
3676 | ||
3677 | return 1; | |
3678 | } | |
3679 | break; | |
3680 | } | |
3681 | } | |
3682 | ||
3683 | /* Advancing to the next state. */ | |
3684 | ++current_state; | |
3685 | } | |
3686 | ||
3687 | return 0; | |
3688 | } | |
3689 | ||
8201327c | 3690 | \f |
3ce1502b | 3691 | |
8201327c | 3692 | /* Generic ELF. */ |
d2a7c97a | 3693 | |
8201327c MK |
3694 | void |
3695 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3696 | { | |
c4fc7f1b MK |
3697 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3698 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
3699 | |
3700 | /* Registering SystemTap handlers. */ | |
3701 | set_gdbarch_stap_integer_prefix (gdbarch, "$"); | |
3702 | set_gdbarch_stap_register_prefix (gdbarch, "%"); | |
3703 | set_gdbarch_stap_register_indirection_prefix (gdbarch, "("); | |
3704 | set_gdbarch_stap_register_indirection_suffix (gdbarch, ")"); | |
3705 | set_gdbarch_stap_is_single_operand (gdbarch, | |
3706 | i386_stap_is_single_operand); | |
3707 | set_gdbarch_stap_parse_special_token (gdbarch, | |
3708 | i386_stap_parse_special_token); | |
8201327c | 3709 | } |
3ce1502b | 3710 | |
8201327c | 3711 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3712 | |
8201327c MK |
3713 | void |
3714 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3715 | { | |
3716 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3717 | |
8201327c MK |
3718 | /* System V Release 4 uses ELF. */ |
3719 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3720 | |
dfe01d39 | 3721 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3722 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3723 | ||
911bc6ee | 3724 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3725 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3726 | tdep->sc_pc_offset = 36 + 14 * 4; |
3727 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3728 | |
8201327c | 3729 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3730 | } |
3731 | ||
8201327c | 3732 | /* DJGPP. */ |
3ce1502b | 3733 | |
3a1e71e3 | 3734 | static void |
8201327c | 3735 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3736 | { |
8201327c | 3737 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3738 | |
911bc6ee MK |
3739 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3740 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3741 | |
8201327c | 3742 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3743 | |
3744 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3745 | if (! tdesc_has_registers (info.target_desc)) |
3746 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3747 | |
3748 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3749 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3750 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3751 | set_gdbarch_sdb_reg_to_regnum. */ | |
3752 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3753 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3754 | |
3755 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3756 | } |
8201327c | 3757 | \f |
2acceee2 | 3758 | |
38c968cf AC |
3759 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3760 | and "sse". */ | |
3761 | ||
3762 | static struct reggroup *i386_sse_reggroup; | |
3763 | static struct reggroup *i386_mmx_reggroup; | |
3764 | ||
3765 | static void | |
3766 | i386_init_reggroups (void) | |
3767 | { | |
3768 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3769 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3770 | } | |
3771 | ||
3772 | static void | |
3773 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3774 | { | |
3775 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3776 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3777 | reggroup_add (gdbarch, general_reggroup); | |
3778 | reggroup_add (gdbarch, float_reggroup); | |
3779 | reggroup_add (gdbarch, all_reggroup); | |
3780 | reggroup_add (gdbarch, save_reggroup); | |
3781 | reggroup_add (gdbarch, restore_reggroup); | |
3782 | reggroup_add (gdbarch, vector_reggroup); | |
3783 | reggroup_add (gdbarch, system_reggroup); | |
3784 | } | |
3785 | ||
3786 | int | |
3787 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3788 | struct reggroup *group) | |
3789 | { | |
c131fcee L |
3790 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3791 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3792 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3793 | |
1ba53b71 L |
3794 | /* Don't include pseudo registers, except for MMX, in any register |
3795 | groups. */ | |
c131fcee | 3796 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3797 | return 0; |
3798 | ||
c131fcee | 3799 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3800 | return 0; |
3801 | ||
c131fcee | 3802 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3803 | return 0; |
3804 | ||
3805 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3806 | if (group == i386_mmx_reggroup) |
3807 | return mmx_regnum_p; | |
1ba53b71 | 3808 | |
c131fcee L |
3809 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3810 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3811 | if (group == i386_sse_reggroup) |
c131fcee L |
3812 | return xmm_regnum_p || mxcsr_regnum_p; |
3813 | ||
3814 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3815 | if (group == vector_reggroup) |
c131fcee L |
3816 | return (mmx_regnum_p |
3817 | || ymm_regnum_p | |
3818 | || mxcsr_regnum_p | |
3819 | || (xmm_regnum_p | |
3820 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3821 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3822 | |
3823 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3824 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3825 | if (group == float_reggroup) |
3826 | return fp_regnum_p; | |
1ba53b71 | 3827 | |
c131fcee L |
3828 | /* For "info reg all", don't include upper YMM registers nor XMM |
3829 | registers when AVX is supported. */ | |
3830 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3831 | if (group == all_reggroup | |
3832 | && ((xmm_regnum_p | |
3833 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3834 | || ymmh_regnum_p)) | |
3835 | return 0; | |
3836 | ||
38c968cf | 3837 | if (group == general_reggroup) |
1ba53b71 L |
3838 | return (!fp_regnum_p |
3839 | && !mmx_regnum_p | |
c131fcee L |
3840 | && !mxcsr_regnum_p |
3841 | && !xmm_regnum_p | |
3842 | && !ymm_regnum_p | |
3843 | && !ymmh_regnum_p); | |
acd5c798 | 3844 | |
38c968cf AC |
3845 | return default_register_reggroup_p (gdbarch, regnum, group); |
3846 | } | |
38c968cf | 3847 | \f |
acd5c798 | 3848 | |
f837910f MK |
3849 | /* Get the ARGIth function argument for the current function. */ |
3850 | ||
42c466d7 | 3851 | static CORE_ADDR |
143985b7 AF |
3852 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3853 | struct type *type) | |
3854 | { | |
e17a4113 UW |
3855 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3856 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 3857 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3858 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3859 | } |
3860 | ||
514f746b AR |
3861 | static void |
3862 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3863 | { | |
3864 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3865 | ||
3866 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3867 | adjust the PC in the regcache. */ | |
3868 | current_pc += 1; | |
3869 | regcache_write_pc (regcache, current_pc); | |
3870 | } | |
3871 | ||
3872 | ||
7ad10968 HZ |
3873 | #define PREFIX_REPZ 0x01 |
3874 | #define PREFIX_REPNZ 0x02 | |
3875 | #define PREFIX_LOCK 0x04 | |
3876 | #define PREFIX_DATA 0x08 | |
3877 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3878 | |
7ad10968 HZ |
3879 | /* operand size */ |
3880 | enum | |
3881 | { | |
3882 | OT_BYTE = 0, | |
3883 | OT_WORD, | |
3884 | OT_LONG, | |
cf648174 | 3885 | OT_QUAD, |
a3c4230a | 3886 | OT_DQUAD, |
7ad10968 | 3887 | }; |
473f17b0 | 3888 | |
7ad10968 HZ |
3889 | /* i386 arith/logic operations */ |
3890 | enum | |
3891 | { | |
3892 | OP_ADDL, | |
3893 | OP_ORL, | |
3894 | OP_ADCL, | |
3895 | OP_SBBL, | |
3896 | OP_ANDL, | |
3897 | OP_SUBL, | |
3898 | OP_XORL, | |
3899 | OP_CMPL, | |
3900 | }; | |
5716833c | 3901 | |
7ad10968 HZ |
3902 | struct i386_record_s |
3903 | { | |
cf648174 | 3904 | struct gdbarch *gdbarch; |
7ad10968 | 3905 | struct regcache *regcache; |
df61f520 | 3906 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3907 | CORE_ADDR addr; |
3908 | int aflag; | |
3909 | int dflag; | |
3910 | int override; | |
3911 | uint8_t modrm; | |
3912 | uint8_t mod, reg, rm; | |
3913 | int ot; | |
cf648174 HZ |
3914 | uint8_t rex_x; |
3915 | uint8_t rex_b; | |
3916 | int rip_offset; | |
3917 | int popl_esp_hack; | |
3918 | const int *regmap; | |
7ad10968 | 3919 | }; |
5716833c | 3920 | |
7ad10968 | 3921 | /* Parse "modrm" part in current memory address that irp->addr point to |
1777feb0 | 3922 | Return -1 if something wrong. */ |
5716833c | 3923 | |
7ad10968 HZ |
3924 | static int |
3925 | i386_record_modrm (struct i386_record_s *irp) | |
3926 | { | |
cf648174 | 3927 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3928 | |
7ad10968 HZ |
3929 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3930 | { | |
3931 | if (record_debug) | |
3932 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3933 | "addr %s len = 1.\n"), |
3934 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3935 | return -1; |
3936 | } | |
3937 | irp->addr++; | |
3938 | irp->mod = (irp->modrm >> 6) & 3; | |
3939 | irp->reg = (irp->modrm >> 3) & 7; | |
3940 | irp->rm = irp->modrm & 7; | |
5716833c | 3941 | |
7ad10968 HZ |
3942 | return 0; |
3943 | } | |
d2a7c97a | 3944 | |
7ad10968 HZ |
3945 | /* Get the memory address that current instruction write to and set it to |
3946 | the argument "addr". | |
1777feb0 | 3947 | Return -1 if something wrong. */ |
8201327c | 3948 | |
7ad10968 | 3949 | static int |
cf648174 | 3950 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3951 | { |
cf648174 | 3952 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3953 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3954 | gdb_byte buf[4]; | |
3955 | ULONGEST offset64; | |
21d0e8a4 | 3956 | |
7ad10968 HZ |
3957 | *addr = 0; |
3958 | if (irp->aflag) | |
3959 | { | |
3960 | /* 32 bits */ | |
3961 | int havesib = 0; | |
3962 | uint8_t scale = 0; | |
648d0c8b | 3963 | uint8_t byte; |
7ad10968 HZ |
3964 | uint8_t index = 0; |
3965 | uint8_t base = irp->rm; | |
896fb97d | 3966 | |
7ad10968 HZ |
3967 | if (base == 4) |
3968 | { | |
3969 | havesib = 1; | |
648d0c8b | 3970 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3971 | { |
3972 | if (record_debug) | |
3973 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3974 | "at addr %s len = 1.\n"), |
3975 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3976 | return -1; |
3977 | } | |
3978 | irp->addr++; | |
648d0c8b MS |
3979 | scale = (byte >> 6) & 3; |
3980 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3981 | base = (byte & 7); | |
7ad10968 | 3982 | } |
cf648174 | 3983 | base |= irp->rex_b; |
21d0e8a4 | 3984 | |
7ad10968 HZ |
3985 | switch (irp->mod) |
3986 | { | |
3987 | case 0: | |
3988 | if ((base & 7) == 5) | |
3989 | { | |
3990 | base = 0xff; | |
60a1502a | 3991 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3992 | { |
3993 | if (record_debug) | |
3994 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3995 | "memory at addr %s len = 4.\n"), |
3996 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3997 | return -1; |
3998 | } | |
3999 | irp->addr += 4; | |
60a1502a | 4000 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4001 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4002 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4003 | } |
7ad10968 HZ |
4004 | break; |
4005 | case 1: | |
60a1502a | 4006 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
4007 | { |
4008 | if (record_debug) | |
4009 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4010 | "at addr %s len = 1.\n"), |
4011 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
4012 | return -1; |
4013 | } | |
4014 | irp->addr++; | |
60a1502a | 4015 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4016 | break; |
4017 | case 2: | |
60a1502a | 4018 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
4019 | { |
4020 | if (record_debug) | |
4021 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4022 | "at addr %s len = 4.\n"), |
4023 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
4024 | return -1; |
4025 | } | |
60a1502a | 4026 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4027 | irp->addr += 4; |
4028 | break; | |
4029 | } | |
356a6b3e | 4030 | |
60a1502a | 4031 | offset64 = 0; |
7ad10968 | 4032 | if (base != 0xff) |
cf648174 HZ |
4033 | { |
4034 | if (base == 4 && irp->popl_esp_hack) | |
4035 | *addr += irp->popl_esp_hack; | |
4036 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4037 | &offset64); |
7ad10968 | 4038 | } |
cf648174 HZ |
4039 | if (irp->aflag == 2) |
4040 | { | |
60a1502a | 4041 | *addr += offset64; |
cf648174 HZ |
4042 | } |
4043 | else | |
60a1502a | 4044 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4045 | |
7ad10968 HZ |
4046 | if (havesib && (index != 4 || scale != 0)) |
4047 | { | |
cf648174 | 4048 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4049 | &offset64); |
cf648174 | 4050 | if (irp->aflag == 2) |
60a1502a | 4051 | *addr += offset64 << scale; |
cf648174 | 4052 | else |
60a1502a | 4053 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
4054 | } |
4055 | } | |
4056 | else | |
4057 | { | |
4058 | /* 16 bits */ | |
4059 | switch (irp->mod) | |
4060 | { | |
4061 | case 0: | |
4062 | if (irp->rm == 6) | |
4063 | { | |
60a1502a | 4064 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
4065 | { |
4066 | if (record_debug) | |
4067 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
4068 | "memory at addr %s len = 2.\n"), |
4069 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
4070 | return -1; |
4071 | } | |
4072 | irp->addr += 2; | |
60a1502a | 4073 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4074 | irp->rm = 0; |
4075 | goto no_rm; | |
4076 | } | |
7ad10968 HZ |
4077 | break; |
4078 | case 1: | |
60a1502a | 4079 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
4080 | { |
4081 | if (record_debug) | |
4082 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4083 | "at addr %s len = 1.\n"), |
4084 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
4085 | return -1; |
4086 | } | |
4087 | irp->addr++; | |
60a1502a | 4088 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4089 | break; |
4090 | case 2: | |
60a1502a | 4091 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
4092 | { |
4093 | if (record_debug) | |
4094 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4095 | "at addr %s len = 2.\n"), |
4096 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
4097 | return -1; |
4098 | } | |
4099 | irp->addr += 2; | |
60a1502a | 4100 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4101 | break; |
4102 | } | |
c4fc7f1b | 4103 | |
7ad10968 HZ |
4104 | switch (irp->rm) |
4105 | { | |
4106 | case 0: | |
cf648174 HZ |
4107 | regcache_raw_read_unsigned (irp->regcache, |
4108 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4109 | &offset64); |
4110 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4111 | regcache_raw_read_unsigned (irp->regcache, |
4112 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4113 | &offset64); |
4114 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4115 | break; |
4116 | case 1: | |
cf648174 HZ |
4117 | regcache_raw_read_unsigned (irp->regcache, |
4118 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4119 | &offset64); |
4120 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4121 | regcache_raw_read_unsigned (irp->regcache, |
4122 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4123 | &offset64); |
4124 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4125 | break; |
4126 | case 2: | |
cf648174 HZ |
4127 | regcache_raw_read_unsigned (irp->regcache, |
4128 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4129 | &offset64); |
4130 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4131 | regcache_raw_read_unsigned (irp->regcache, |
4132 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4133 | &offset64); |
4134 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4135 | break; |
4136 | case 3: | |
cf648174 HZ |
4137 | regcache_raw_read_unsigned (irp->regcache, |
4138 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4139 | &offset64); |
4140 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4141 | regcache_raw_read_unsigned (irp->regcache, |
4142 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4143 | &offset64); |
4144 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4145 | break; |
4146 | case 4: | |
cf648174 HZ |
4147 | regcache_raw_read_unsigned (irp->regcache, |
4148 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4149 | &offset64); |
4150 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4151 | break; |
4152 | case 5: | |
cf648174 HZ |
4153 | regcache_raw_read_unsigned (irp->regcache, |
4154 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4155 | &offset64); |
4156 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4157 | break; |
4158 | case 6: | |
cf648174 HZ |
4159 | regcache_raw_read_unsigned (irp->regcache, |
4160 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4161 | &offset64); |
4162 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4163 | break; |
4164 | case 7: | |
cf648174 HZ |
4165 | regcache_raw_read_unsigned (irp->regcache, |
4166 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4167 | &offset64); |
4168 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4169 | break; |
4170 | } | |
4171 | *addr &= 0xffff; | |
4172 | } | |
c4fc7f1b | 4173 | |
01fe1b41 | 4174 | no_rm: |
7ad10968 HZ |
4175 | return 0; |
4176 | } | |
c4fc7f1b | 4177 | |
7ad10968 HZ |
4178 | /* Record the value of the memory that willbe changed in current instruction |
4179 | to "record_arch_list". | |
1777feb0 | 4180 | Return -1 if something wrong. */ |
356a6b3e | 4181 | |
7ad10968 HZ |
4182 | static int |
4183 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4184 | { | |
cf648174 HZ |
4185 | struct gdbarch *gdbarch = irp->gdbarch; |
4186 | uint64_t addr; | |
356a6b3e | 4187 | |
d7877f7e | 4188 | if (irp->override >= 0) |
7ad10968 | 4189 | { |
bb08c432 HZ |
4190 | if (record_memory_query) |
4191 | { | |
4192 | int q; | |
4193 | ||
4194 | target_terminal_ours (); | |
4195 | q = yquery (_("\ | |
4196 | Process record ignores the memory change of instruction at address %s\n\ | |
4197 | because it can't get the value of the segment register.\n\ | |
4198 | Do you want to stop the program?"), | |
4199 | paddress (gdbarch, irp->orig_addr)); | |
4200 | target_terminal_inferior (); | |
4201 | if (q) | |
4202 | return -1; | |
4203 | } | |
4204 | ||
7ad10968 HZ |
4205 | return 0; |
4206 | } | |
61113f8b | 4207 | |
7ad10968 HZ |
4208 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4209 | return -1; | |
96297dab | 4210 | |
7ad10968 HZ |
4211 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
4212 | return -1; | |
a62cc96e | 4213 | |
7ad10968 HZ |
4214 | return 0; |
4215 | } | |
b6197528 | 4216 | |
cf648174 | 4217 | /* Record the push operation to "record_arch_list". |
1777feb0 | 4218 | Return -1 if something wrong. */ |
cf648174 HZ |
4219 | |
4220 | static int | |
4221 | i386_record_push (struct i386_record_s *irp, int size) | |
4222 | { | |
648d0c8b | 4223 | ULONGEST addr; |
cf648174 HZ |
4224 | |
4225 | if (record_arch_list_add_reg (irp->regcache, | |
4226 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
4227 | return -1; | |
4228 | regcache_raw_read_unsigned (irp->regcache, | |
4229 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
4230 | &addr); |
4231 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
4232 | return -1; |
4233 | ||
4234 | return 0; | |
4235 | } | |
4236 | ||
0289bdd7 MS |
4237 | |
4238 | /* Defines contents to record. */ | |
4239 | #define I386_SAVE_FPU_REGS 0xfffd | |
4240 | #define I386_SAVE_FPU_ENV 0xfffe | |
4241 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4242 | ||
1777feb0 MS |
4243 | /* Record the value of floating point registers which will be changed |
4244 | by the current instruction to "record_arch_list". Return -1 if | |
4245 | something is wrong. */ | |
0289bdd7 MS |
4246 | |
4247 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4248 | struct i386_record_s *ir, | |
4249 | uint32_t iregnum) | |
4250 | { | |
4251 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4252 | int i; | |
4253 | ||
4254 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4255 | happen. Currently we store st0-st7 registers, but we need not store all | |
4256 | registers all the time, in future we use ftag register and record only | |
4257 | those who are not marked as an empty. */ | |
4258 | ||
4259 | if (I386_SAVE_FPU_REGS == iregnum) | |
4260 | { | |
4261 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4262 | { | |
4263 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4264 | return -1; | |
4265 | } | |
4266 | } | |
4267 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4268 | { | |
4269 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4270 | { | |
4271 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4272 | return -1; | |
4273 | } | |
4274 | } | |
4275 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4276 | { | |
4277 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4278 | { | |
4279 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4280 | return -1; | |
4281 | } | |
4282 | } | |
4283 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4284 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4285 | { | |
4286 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
4287 | return -1; | |
4288 | } | |
4289 | else | |
4290 | { | |
4291 | /* Parameter error. */ | |
4292 | return -1; | |
4293 | } | |
4294 | if(I386_SAVE_FPU_ENV != iregnum) | |
4295 | { | |
4296 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4297 | { | |
4298 | if (record_arch_list_add_reg (ir->regcache, i)) | |
4299 | return -1; | |
4300 | } | |
4301 | } | |
4302 | return 0; | |
4303 | } | |
4304 | ||
7ad10968 HZ |
4305 | /* Parse the current instruction and record the values of the registers and |
4306 | memory that will be changed in current instruction to "record_arch_list". | |
1777feb0 | 4307 | Return -1 if something wrong. */ |
8201327c | 4308 | |
cf648174 HZ |
4309 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
4310 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
4311 | ||
a6b808b4 | 4312 | int |
7ad10968 | 4313 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4314 | CORE_ADDR input_addr) |
7ad10968 | 4315 | { |
60a1502a | 4316 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4317 | int prefixes = 0; |
580879fc | 4318 | int regnum = 0; |
425b824a | 4319 | uint32_t opcode; |
f4644a3f | 4320 | uint8_t opcode8; |
648d0c8b | 4321 | ULONGEST addr; |
60a1502a | 4322 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4323 | struct i386_record_s ir; |
0289bdd7 | 4324 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4325 | int rex = 0; |
4326 | uint8_t rex_w = -1; | |
4327 | uint8_t rex_r = 0; | |
7ad10968 | 4328 | |
8408d274 | 4329 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4330 | ir.regcache = regcache; |
648d0c8b MS |
4331 | ir.addr = input_addr; |
4332 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4333 | ir.aflag = 1; |
4334 | ir.dflag = 1; | |
cf648174 HZ |
4335 | ir.override = -1; |
4336 | ir.popl_esp_hack = 0; | |
a3c4230a | 4337 | ir.regmap = tdep->record_regmap; |
cf648174 | 4338 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4339 | |
4340 | if (record_debug > 1) | |
4341 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4342 | "addr = %s\n", |
4343 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4344 | |
4345 | /* prefixes */ | |
4346 | while (1) | |
4347 | { | |
425b824a | 4348 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4349 | { |
4350 | if (record_debug) | |
4351 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4352 | "addr %s len = 1.\n"), |
4353 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4354 | return -1; |
4355 | } | |
4356 | ir.addr++; | |
425b824a | 4357 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4358 | { |
01fe1b41 | 4359 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4360 | prefixes |= PREFIX_REPZ; |
4361 | break; | |
01fe1b41 | 4362 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4363 | prefixes |= PREFIX_REPNZ; |
4364 | break; | |
01fe1b41 | 4365 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4366 | prefixes |= PREFIX_LOCK; |
4367 | break; | |
01fe1b41 | 4368 | case CS_PREFIX_OPCODE: |
cf648174 | 4369 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4370 | break; |
01fe1b41 | 4371 | case SS_PREFIX_OPCODE: |
cf648174 | 4372 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4373 | break; |
01fe1b41 | 4374 | case DS_PREFIX_OPCODE: |
cf648174 | 4375 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4376 | break; |
01fe1b41 | 4377 | case ES_PREFIX_OPCODE: |
cf648174 | 4378 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4379 | break; |
01fe1b41 | 4380 | case FS_PREFIX_OPCODE: |
cf648174 | 4381 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4382 | break; |
01fe1b41 | 4383 | case GS_PREFIX_OPCODE: |
cf648174 | 4384 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4385 | break; |
01fe1b41 | 4386 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4387 | prefixes |= PREFIX_DATA; |
4388 | break; | |
01fe1b41 | 4389 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4390 | prefixes |= PREFIX_ADDR; |
4391 | break; | |
d691bec7 MS |
4392 | case 0x40: /* i386 inc %eax */ |
4393 | case 0x41: /* i386 inc %ecx */ | |
4394 | case 0x42: /* i386 inc %edx */ | |
4395 | case 0x43: /* i386 inc %ebx */ | |
4396 | case 0x44: /* i386 inc %esp */ | |
4397 | case 0x45: /* i386 inc %ebp */ | |
4398 | case 0x46: /* i386 inc %esi */ | |
4399 | case 0x47: /* i386 inc %edi */ | |
4400 | case 0x48: /* i386 dec %eax */ | |
4401 | case 0x49: /* i386 dec %ecx */ | |
4402 | case 0x4a: /* i386 dec %edx */ | |
4403 | case 0x4b: /* i386 dec %ebx */ | |
4404 | case 0x4c: /* i386 dec %esp */ | |
4405 | case 0x4d: /* i386 dec %ebp */ | |
4406 | case 0x4e: /* i386 dec %esi */ | |
4407 | case 0x4f: /* i386 dec %edi */ | |
4408 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4409 | { |
4410 | /* REX */ | |
4411 | rex = 1; | |
425b824a MS |
4412 | rex_w = (opcode8 >> 3) & 1; |
4413 | rex_r = (opcode8 & 0x4) << 1; | |
4414 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4415 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4416 | } |
d691bec7 MS |
4417 | else /* 32 bit target */ |
4418 | goto out_prefixes; | |
cf648174 | 4419 | break; |
7ad10968 HZ |
4420 | default: |
4421 | goto out_prefixes; | |
4422 | break; | |
4423 | } | |
4424 | } | |
01fe1b41 | 4425 | out_prefixes: |
cf648174 HZ |
4426 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4427 | { | |
4428 | ir.dflag = 2; | |
4429 | } | |
4430 | else | |
4431 | { | |
4432 | if (prefixes & PREFIX_DATA) | |
4433 | ir.dflag ^= 1; | |
4434 | } | |
7ad10968 HZ |
4435 | if (prefixes & PREFIX_ADDR) |
4436 | ir.aflag ^= 1; | |
cf648174 HZ |
4437 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4438 | ir.aflag = 2; | |
7ad10968 | 4439 | |
1777feb0 | 4440 | /* Now check op code. */ |
425b824a | 4441 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4442 | reswitch: |
7ad10968 HZ |
4443 | switch (opcode) |
4444 | { | |
4445 | case 0x0f: | |
425b824a | 4446 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4447 | { |
4448 | if (record_debug) | |
4449 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4450 | "addr %s len = 1.\n"), |
4451 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4452 | return -1; |
4453 | } | |
4454 | ir.addr++; | |
a3c4230a | 4455 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4456 | goto reswitch; |
4457 | break; | |
93924b6b | 4458 | |
a38bba38 | 4459 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4460 | case 0x01: |
4461 | case 0x02: | |
4462 | case 0x03: | |
4463 | case 0x04: | |
4464 | case 0x05: | |
4465 | case 0x08: | |
4466 | case 0x09: | |
4467 | case 0x0a: | |
4468 | case 0x0b: | |
4469 | case 0x0c: | |
4470 | case 0x0d: | |
4471 | case 0x10: | |
4472 | case 0x11: | |
4473 | case 0x12: | |
4474 | case 0x13: | |
4475 | case 0x14: | |
4476 | case 0x15: | |
4477 | case 0x18: | |
4478 | case 0x19: | |
4479 | case 0x1a: | |
4480 | case 0x1b: | |
4481 | case 0x1c: | |
4482 | case 0x1d: | |
4483 | case 0x20: | |
4484 | case 0x21: | |
4485 | case 0x22: | |
4486 | case 0x23: | |
4487 | case 0x24: | |
4488 | case 0x25: | |
4489 | case 0x28: | |
4490 | case 0x29: | |
4491 | case 0x2a: | |
4492 | case 0x2b: | |
4493 | case 0x2c: | |
4494 | case 0x2d: | |
4495 | case 0x30: | |
4496 | case 0x31: | |
4497 | case 0x32: | |
4498 | case 0x33: | |
4499 | case 0x34: | |
4500 | case 0x35: | |
4501 | case 0x38: | |
4502 | case 0x39: | |
4503 | case 0x3a: | |
4504 | case 0x3b: | |
4505 | case 0x3c: | |
4506 | case 0x3d: | |
4507 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4508 | { | |
4509 | if ((opcode & 1) == 0) | |
4510 | ir.ot = OT_BYTE; | |
4511 | else | |
4512 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4513 | |
7ad10968 HZ |
4514 | switch ((opcode >> 1) & 3) |
4515 | { | |
a38bba38 | 4516 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4517 | if (i386_record_modrm (&ir)) |
4518 | return -1; | |
4519 | if (ir.mod != 3) | |
4520 | { | |
4521 | if (i386_record_lea_modrm (&ir)) | |
4522 | return -1; | |
4523 | } | |
4524 | else | |
4525 | { | |
cf648174 HZ |
4526 | ir.rm |= ir.rex_b; |
4527 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4528 | ir.rm &= 0x3; |
cf648174 | 4529 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4530 | } |
4531 | break; | |
a38bba38 | 4532 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4533 | if (i386_record_modrm (&ir)) |
4534 | return -1; | |
cf648174 HZ |
4535 | ir.reg |= rex_r; |
4536 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4537 | ir.reg &= 0x3; |
cf648174 | 4538 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4539 | break; |
a38bba38 | 4540 | case 2: /* OP A, Iv */ |
cf648174 | 4541 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4542 | break; |
4543 | } | |
4544 | } | |
cf648174 | 4545 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4546 | break; |
42fdc8df | 4547 | |
a38bba38 | 4548 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4549 | case 0x81: |
4550 | case 0x82: | |
4551 | case 0x83: | |
4552 | if (i386_record_modrm (&ir)) | |
4553 | return -1; | |
8201327c | 4554 | |
7ad10968 HZ |
4555 | if (ir.reg != OP_CMPL) |
4556 | { | |
4557 | if ((opcode & 1) == 0) | |
4558 | ir.ot = OT_BYTE; | |
4559 | else | |
4560 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4561 | |
7ad10968 HZ |
4562 | if (ir.mod != 3) |
4563 | { | |
cf648174 HZ |
4564 | if (opcode == 0x83) |
4565 | ir.rip_offset = 1; | |
4566 | else | |
4567 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4568 | if (i386_record_lea_modrm (&ir)) |
4569 | return -1; | |
4570 | } | |
4571 | else | |
cf648174 | 4572 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4573 | } |
cf648174 | 4574 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4575 | break; |
5e3397bb | 4576 | |
a38bba38 | 4577 | case 0x40: /* inc */ |
7ad10968 HZ |
4578 | case 0x41: |
4579 | case 0x42: | |
4580 | case 0x43: | |
4581 | case 0x44: | |
4582 | case 0x45: | |
4583 | case 0x46: | |
4584 | case 0x47: | |
a38bba38 MS |
4585 | |
4586 | case 0x48: /* dec */ | |
7ad10968 HZ |
4587 | case 0x49: |
4588 | case 0x4a: | |
4589 | case 0x4b: | |
4590 | case 0x4c: | |
4591 | case 0x4d: | |
4592 | case 0x4e: | |
4593 | case 0x4f: | |
a38bba38 | 4594 | |
cf648174 HZ |
4595 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
4596 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4597 | break; |
acd5c798 | 4598 | |
a38bba38 | 4599 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4600 | case 0xf7: |
4601 | if ((opcode & 1) == 0) | |
4602 | ir.ot = OT_BYTE; | |
4603 | else | |
4604 | ir.ot = ir.dflag + OT_WORD; | |
4605 | if (i386_record_modrm (&ir)) | |
4606 | return -1; | |
acd5c798 | 4607 | |
cf648174 HZ |
4608 | if (ir.mod != 3 && ir.reg == 0) |
4609 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4610 | ||
7ad10968 HZ |
4611 | switch (ir.reg) |
4612 | { | |
a38bba38 | 4613 | case 0: /* test */ |
cf648174 | 4614 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4615 | break; |
a38bba38 MS |
4616 | case 2: /* not */ |
4617 | case 3: /* neg */ | |
7ad10968 HZ |
4618 | if (ir.mod != 3) |
4619 | { | |
4620 | if (i386_record_lea_modrm (&ir)) | |
4621 | return -1; | |
4622 | } | |
4623 | else | |
4624 | { | |
cf648174 HZ |
4625 | ir.rm |= ir.rex_b; |
4626 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4627 | ir.rm &= 0x3; |
cf648174 | 4628 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4629 | } |
a38bba38 | 4630 | if (ir.reg == 3) /* neg */ |
cf648174 | 4631 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4632 | break; |
a38bba38 MS |
4633 | case 4: /* mul */ |
4634 | case 5: /* imul */ | |
4635 | case 6: /* div */ | |
4636 | case 7: /* idiv */ | |
cf648174 | 4637 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4638 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
4639 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4640 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4641 | break; |
4642 | default: | |
4643 | ir.addr -= 2; | |
4644 | opcode = opcode << 8 | ir.modrm; | |
4645 | goto no_support; | |
4646 | break; | |
4647 | } | |
4648 | break; | |
4649 | ||
a38bba38 MS |
4650 | case 0xfe: /* GRP4 */ |
4651 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4652 | if (i386_record_modrm (&ir)) |
4653 | return -1; | |
4654 | if (ir.reg >= 2 && opcode == 0xfe) | |
4655 | { | |
4656 | ir.addr -= 2; | |
4657 | opcode = opcode << 8 | ir.modrm; | |
4658 | goto no_support; | |
4659 | } | |
7ad10968 HZ |
4660 | switch (ir.reg) |
4661 | { | |
a38bba38 MS |
4662 | case 0: /* inc */ |
4663 | case 1: /* dec */ | |
cf648174 HZ |
4664 | if ((opcode & 1) == 0) |
4665 | ir.ot = OT_BYTE; | |
4666 | else | |
4667 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4668 | if (ir.mod != 3) |
4669 | { | |
4670 | if (i386_record_lea_modrm (&ir)) | |
4671 | return -1; | |
4672 | } | |
4673 | else | |
4674 | { | |
cf648174 HZ |
4675 | ir.rm |= ir.rex_b; |
4676 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4677 | ir.rm &= 0x3; |
cf648174 | 4678 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4679 | } |
cf648174 | 4680 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4681 | break; |
a38bba38 | 4682 | case 2: /* call */ |
cf648174 HZ |
4683 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4684 | ir.dflag = 2; | |
4685 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4686 | return -1; |
cf648174 | 4687 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4688 | break; |
a38bba38 | 4689 | case 3: /* lcall */ |
cf648174 HZ |
4690 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4691 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4692 | return -1; |
cf648174 | 4693 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4694 | break; |
a38bba38 MS |
4695 | case 4: /* jmp */ |
4696 | case 5: /* ljmp */ | |
cf648174 HZ |
4697 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4698 | break; | |
a38bba38 | 4699 | case 6: /* push */ |
cf648174 HZ |
4700 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4701 | ir.dflag = 2; | |
4702 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4703 | return -1; | |
7ad10968 HZ |
4704 | break; |
4705 | default: | |
4706 | ir.addr -= 2; | |
4707 | opcode = opcode << 8 | ir.modrm; | |
4708 | goto no_support; | |
4709 | break; | |
4710 | } | |
4711 | break; | |
4712 | ||
a38bba38 | 4713 | case 0x84: /* test */ |
7ad10968 HZ |
4714 | case 0x85: |
4715 | case 0xa8: | |
4716 | case 0xa9: | |
cf648174 | 4717 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4718 | break; |
4719 | ||
a38bba38 | 4720 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4721 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4722 | break; |
4723 | ||
a38bba38 | 4724 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4725 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4726 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4727 | break; |
4728 | ||
a38bba38 | 4729 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4730 | case 0x69: |
4731 | case 0x6b: | |
4732 | ir.ot = ir.dflag + OT_WORD; | |
4733 | if (i386_record_modrm (&ir)) | |
4734 | return -1; | |
cf648174 HZ |
4735 | if (opcode == 0x69) |
4736 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4737 | else if (opcode == 0x6b) | |
4738 | ir.rip_offset = 1; | |
4739 | ir.reg |= rex_r; | |
4740 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4741 | ir.reg &= 0x3; |
cf648174 HZ |
4742 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4743 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4744 | break; |
4745 | ||
a38bba38 | 4746 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4747 | case 0x0fc1: |
4748 | if ((opcode & 1) == 0) | |
4749 | ir.ot = OT_BYTE; | |
4750 | else | |
4751 | ir.ot = ir.dflag + OT_WORD; | |
4752 | if (i386_record_modrm (&ir)) | |
4753 | return -1; | |
cf648174 | 4754 | ir.reg |= rex_r; |
7ad10968 HZ |
4755 | if (ir.mod == 3) |
4756 | { | |
cf648174 | 4757 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4758 | ir.reg &= 0x3; |
cf648174 HZ |
4759 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4760 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4761 | ir.rm &= 0x3; |
cf648174 | 4762 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4763 | } |
4764 | else | |
4765 | { | |
4766 | if (i386_record_lea_modrm (&ir)) | |
4767 | return -1; | |
cf648174 | 4768 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4769 | ir.reg &= 0x3; |
cf648174 | 4770 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4771 | } |
cf648174 | 4772 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4773 | break; |
4774 | ||
a38bba38 | 4775 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4776 | case 0x0fb1: |
4777 | if ((opcode & 1) == 0) | |
4778 | ir.ot = OT_BYTE; | |
4779 | else | |
4780 | ir.ot = ir.dflag + OT_WORD; | |
4781 | if (i386_record_modrm (&ir)) | |
4782 | return -1; | |
4783 | if (ir.mod == 3) | |
4784 | { | |
cf648174 HZ |
4785 | ir.reg |= rex_r; |
4786 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4787 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4788 | ir.reg &= 0x3; |
cf648174 | 4789 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4790 | } |
4791 | else | |
4792 | { | |
cf648174 | 4793 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4794 | if (i386_record_lea_modrm (&ir)) |
4795 | return -1; | |
4796 | } | |
cf648174 | 4797 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4798 | break; |
4799 | ||
a38bba38 | 4800 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4801 | if (i386_record_modrm (&ir)) |
4802 | return -1; | |
4803 | if (ir.mod == 3) | |
4804 | { | |
4805 | ir.addr -= 2; | |
4806 | opcode = opcode << 8 | ir.modrm; | |
4807 | goto no_support; | |
4808 | } | |
cf648174 HZ |
4809 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4810 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4811 | if (i386_record_lea_modrm (&ir)) |
4812 | return -1; | |
cf648174 | 4813 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4814 | break; |
4815 | ||
a38bba38 | 4816 | case 0x50: /* push */ |
7ad10968 HZ |
4817 | case 0x51: |
4818 | case 0x52: | |
4819 | case 0x53: | |
4820 | case 0x54: | |
4821 | case 0x55: | |
4822 | case 0x56: | |
4823 | case 0x57: | |
4824 | case 0x68: | |
4825 | case 0x6a: | |
cf648174 HZ |
4826 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4827 | ir.dflag = 2; | |
4828 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4829 | return -1; | |
4830 | break; | |
4831 | ||
a38bba38 MS |
4832 | case 0x06: /* push es */ |
4833 | case 0x0e: /* push cs */ | |
4834 | case 0x16: /* push ss */ | |
4835 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4836 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4837 | { | |
4838 | ir.addr -= 1; | |
4839 | goto no_support; | |
4840 | } | |
4841 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4842 | return -1; | |
4843 | break; | |
4844 | ||
a38bba38 MS |
4845 | case 0x0fa0: /* push fs */ |
4846 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4847 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4848 | { | |
4849 | ir.addr -= 2; | |
4850 | goto no_support; | |
4851 | } | |
4852 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4853 | return -1; |
cf648174 HZ |
4854 | break; |
4855 | ||
a38bba38 | 4856 | case 0x60: /* pusha */ |
cf648174 HZ |
4857 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4858 | { | |
4859 | ir.addr -= 1; | |
4860 | goto no_support; | |
4861 | } | |
4862 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4863 | return -1; |
4864 | break; | |
4865 | ||
a38bba38 | 4866 | case 0x58: /* pop */ |
7ad10968 HZ |
4867 | case 0x59: |
4868 | case 0x5a: | |
4869 | case 0x5b: | |
4870 | case 0x5c: | |
4871 | case 0x5d: | |
4872 | case 0x5e: | |
4873 | case 0x5f: | |
cf648174 HZ |
4874 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4875 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4876 | break; |
4877 | ||
a38bba38 | 4878 | case 0x61: /* popa */ |
cf648174 HZ |
4879 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4880 | { | |
4881 | ir.addr -= 1; | |
4882 | goto no_support; | |
7ad10968 | 4883 | } |
425b824a MS |
4884 | for (regnum = X86_RECORD_REAX_REGNUM; |
4885 | regnum <= X86_RECORD_REDI_REGNUM; | |
4886 | regnum++) | |
4887 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4888 | break; |
4889 | ||
a38bba38 | 4890 | case 0x8f: /* pop */ |
cf648174 HZ |
4891 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4892 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4893 | else | |
4894 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4895 | if (i386_record_modrm (&ir)) |
4896 | return -1; | |
4897 | if (ir.mod == 3) | |
cf648174 | 4898 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4899 | else |
4900 | { | |
cf648174 | 4901 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4902 | if (i386_record_lea_modrm (&ir)) |
4903 | return -1; | |
4904 | } | |
cf648174 | 4905 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4906 | break; |
4907 | ||
a38bba38 | 4908 | case 0xc8: /* enter */ |
cf648174 HZ |
4909 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4910 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4911 | ir.dflag = 2; | |
4912 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4913 | return -1; |
4914 | break; | |
4915 | ||
a38bba38 | 4916 | case 0xc9: /* leave */ |
cf648174 HZ |
4917 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4918 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4919 | break; |
4920 | ||
a38bba38 | 4921 | case 0x07: /* pop es */ |
cf648174 HZ |
4922 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4923 | { | |
4924 | ir.addr -= 1; | |
4925 | goto no_support; | |
4926 | } | |
4927 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4928 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4929 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4930 | break; |
4931 | ||
a38bba38 | 4932 | case 0x17: /* pop ss */ |
cf648174 HZ |
4933 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4934 | { | |
4935 | ir.addr -= 1; | |
4936 | goto no_support; | |
4937 | } | |
4938 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4939 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4940 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4941 | break; |
4942 | ||
a38bba38 | 4943 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4944 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4945 | { | |
4946 | ir.addr -= 1; | |
4947 | goto no_support; | |
4948 | } | |
4949 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4952 | break; |
4953 | ||
a38bba38 | 4954 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4955 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4956 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4957 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4958 | break; |
4959 | ||
a38bba38 | 4960 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4961 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4962 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4963 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4964 | break; |
4965 | ||
a38bba38 | 4966 | case 0x88: /* mov */ |
7ad10968 HZ |
4967 | case 0x89: |
4968 | case 0xc6: | |
4969 | case 0xc7: | |
4970 | if ((opcode & 1) == 0) | |
4971 | ir.ot = OT_BYTE; | |
4972 | else | |
4973 | ir.ot = ir.dflag + OT_WORD; | |
4974 | ||
4975 | if (i386_record_modrm (&ir)) | |
4976 | return -1; | |
4977 | ||
4978 | if (ir.mod != 3) | |
4979 | { | |
cf648174 HZ |
4980 | if (opcode == 0xc6 || opcode == 0xc7) |
4981 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4982 | if (i386_record_lea_modrm (&ir)) |
4983 | return -1; | |
4984 | } | |
4985 | else | |
4986 | { | |
cf648174 HZ |
4987 | if (opcode == 0xc6 || opcode == 0xc7) |
4988 | ir.rm |= ir.rex_b; | |
4989 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4990 | ir.rm &= 0x3; |
cf648174 | 4991 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4992 | } |
7ad10968 | 4993 | break; |
cf648174 | 4994 | |
a38bba38 | 4995 | case 0x8a: /* mov */ |
7ad10968 HZ |
4996 | case 0x8b: |
4997 | if ((opcode & 1) == 0) | |
4998 | ir.ot = OT_BYTE; | |
4999 | else | |
5000 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5001 | if (i386_record_modrm (&ir)) |
5002 | return -1; | |
cf648174 HZ |
5003 | ir.reg |= rex_r; |
5004 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5005 | ir.reg &= 0x3; |
cf648174 HZ |
5006 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
5007 | break; | |
7ad10968 | 5008 | |
a38bba38 | 5009 | case 0x8c: /* mov seg */ |
cf648174 | 5010 | if (i386_record_modrm (&ir)) |
7ad10968 | 5011 | return -1; |
cf648174 HZ |
5012 | if (ir.reg > 5) |
5013 | { | |
5014 | ir.addr -= 2; | |
5015 | opcode = opcode << 8 | ir.modrm; | |
5016 | goto no_support; | |
5017 | } | |
5018 | ||
5019 | if (ir.mod == 3) | |
5020 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
5021 | else | |
5022 | { | |
5023 | ir.ot = OT_WORD; | |
5024 | if (i386_record_lea_modrm (&ir)) | |
5025 | return -1; | |
5026 | } | |
7ad10968 HZ |
5027 | break; |
5028 | ||
a38bba38 | 5029 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5030 | if (i386_record_modrm (&ir)) |
5031 | return -1; | |
7ad10968 HZ |
5032 | switch (ir.reg) |
5033 | { | |
5034 | case 0: | |
425b824a | 5035 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5036 | break; |
5037 | case 2: | |
425b824a | 5038 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5039 | break; |
5040 | case 3: | |
425b824a | 5041 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5042 | break; |
5043 | case 4: | |
425b824a | 5044 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5045 | break; |
5046 | case 5: | |
425b824a | 5047 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5048 | break; |
5049 | default: | |
5050 | ir.addr -= 2; | |
5051 | opcode = opcode << 8 | ir.modrm; | |
5052 | goto no_support; | |
5053 | break; | |
5054 | } | |
425b824a | 5055 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 5056 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5057 | break; |
5058 | ||
a38bba38 MS |
5059 | case 0x0fb6: /* movzbS */ |
5060 | case 0x0fb7: /* movzwS */ | |
5061 | case 0x0fbe: /* movsbS */ | |
5062 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5063 | if (i386_record_modrm (&ir)) |
5064 | return -1; | |
cf648174 | 5065 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5066 | break; |
5067 | ||
a38bba38 | 5068 | case 0x8d: /* lea */ |
7ad10968 HZ |
5069 | if (i386_record_modrm (&ir)) |
5070 | return -1; | |
5071 | if (ir.mod == 3) | |
5072 | { | |
5073 | ir.addr -= 2; | |
5074 | opcode = opcode << 8 | ir.modrm; | |
5075 | goto no_support; | |
5076 | } | |
7ad10968 | 5077 | ir.ot = ir.dflag; |
cf648174 HZ |
5078 | ir.reg |= rex_r; |
5079 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5080 | ir.reg &= 0x3; |
cf648174 | 5081 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5082 | break; |
5083 | ||
a38bba38 | 5084 | case 0xa0: /* mov EAX */ |
7ad10968 | 5085 | case 0xa1: |
a38bba38 MS |
5086 | |
5087 | case 0xd7: /* xlat */ | |
cf648174 | 5088 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5089 | break; |
5090 | ||
a38bba38 | 5091 | case 0xa2: /* mov EAX */ |
7ad10968 | 5092 | case 0xa3: |
d7877f7e | 5093 | if (ir.override >= 0) |
cf648174 | 5094 | { |
bb08c432 HZ |
5095 | if (record_memory_query) |
5096 | { | |
5097 | int q; | |
5098 | ||
5099 | target_terminal_ours (); | |
5100 | q = yquery (_("\ | |
5101 | Process record ignores the memory change of instruction at address %s\n\ | |
5102 | because it can't get the value of the segment register.\n\ | |
5103 | Do you want to stop the program?"), | |
5104 | paddress (gdbarch, ir.orig_addr)); | |
5105 | target_terminal_inferior (); | |
5106 | if (q) | |
5107 | return -1; | |
5108 | } | |
cf648174 HZ |
5109 | } |
5110 | else | |
5111 | { | |
5112 | if ((opcode & 1) == 0) | |
5113 | ir.ot = OT_BYTE; | |
5114 | else | |
5115 | ir.ot = ir.dflag + OT_WORD; | |
5116 | if (ir.aflag == 2) | |
5117 | { | |
60a1502a | 5118 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
5119 | { |
5120 | if (record_debug) | |
5121 | printf_unfiltered (_("Process record: error reading " | |
5122 | "memory at addr 0x%s len = 8.\n"), | |
5123 | paddress (gdbarch, ir.addr)); | |
5124 | return -1; | |
5125 | } | |
5126 | ir.addr += 8; | |
60a1502a | 5127 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5128 | } |
5129 | else if (ir.aflag) | |
5130 | { | |
60a1502a | 5131 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
5132 | { |
5133 | if (record_debug) | |
5134 | printf_unfiltered (_("Process record: error reading " | |
5135 | "memory at addr 0x%s len = 4.\n"), | |
5136 | paddress (gdbarch, ir.addr)); | |
5137 | return -1; | |
5138 | } | |
5139 | ir.addr += 4; | |
60a1502a | 5140 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5141 | } |
5142 | else | |
5143 | { | |
60a1502a | 5144 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
5145 | { |
5146 | if (record_debug) | |
5147 | printf_unfiltered (_("Process record: error reading " | |
5148 | "memory at addr 0x%s len = 2.\n"), | |
5149 | paddress (gdbarch, ir.addr)); | |
5150 | return -1; | |
5151 | } | |
5152 | ir.addr += 2; | |
60a1502a | 5153 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5154 | } |
648d0c8b | 5155 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5156 | return -1; |
5157 | } | |
7ad10968 HZ |
5158 | break; |
5159 | ||
a38bba38 | 5160 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5161 | case 0xb1: |
5162 | case 0xb2: | |
5163 | case 0xb3: | |
5164 | case 0xb4: | |
5165 | case 0xb5: | |
5166 | case 0xb6: | |
5167 | case 0xb7: | |
cf648174 HZ |
5168 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5169 | ? ((opcode & 0x7) | ir.rex_b) | |
5170 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5171 | break; |
5172 | ||
a38bba38 | 5173 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5174 | case 0xb9: |
5175 | case 0xba: | |
5176 | case 0xbb: | |
5177 | case 0xbc: | |
5178 | case 0xbd: | |
5179 | case 0xbe: | |
5180 | case 0xbf: | |
cf648174 | 5181 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5182 | break; |
5183 | ||
a38bba38 | 5184 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5185 | case 0x92: |
5186 | case 0x93: | |
5187 | case 0x94: | |
5188 | case 0x95: | |
5189 | case 0x96: | |
5190 | case 0x97: | |
cf648174 HZ |
5191 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5192 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5193 | break; |
5194 | ||
a38bba38 | 5195 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5196 | case 0x87: |
5197 | if ((opcode & 1) == 0) | |
5198 | ir.ot = OT_BYTE; | |
5199 | else | |
5200 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5201 | if (i386_record_modrm (&ir)) |
5202 | return -1; | |
7ad10968 HZ |
5203 | if (ir.mod == 3) |
5204 | { | |
86839d38 | 5205 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5206 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5207 | ir.rm &= 0x3; | |
5208 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
5209 | } |
5210 | else | |
5211 | { | |
5212 | if (i386_record_lea_modrm (&ir)) | |
5213 | return -1; | |
5214 | } | |
cf648174 HZ |
5215 | ir.reg |= rex_r; |
5216 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5217 | ir.reg &= 0x3; |
cf648174 | 5218 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5219 | break; |
5220 | ||
a38bba38 MS |
5221 | case 0xc4: /* les Gv */ |
5222 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5223 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5224 | { | |
5225 | ir.addr -= 1; | |
5226 | goto no_support; | |
5227 | } | |
d3f323f3 | 5228 | /* FALLTHROUGH */ |
a38bba38 MS |
5229 | case 0x0fb2: /* lss Gv */ |
5230 | case 0x0fb4: /* lfs Gv */ | |
5231 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5232 | if (i386_record_modrm (&ir)) |
5233 | return -1; | |
5234 | if (ir.mod == 3) | |
5235 | { | |
5236 | if (opcode > 0xff) | |
5237 | ir.addr -= 3; | |
5238 | else | |
5239 | ir.addr -= 2; | |
5240 | opcode = opcode << 8 | ir.modrm; | |
5241 | goto no_support; | |
5242 | } | |
7ad10968 HZ |
5243 | switch (opcode) |
5244 | { | |
a38bba38 | 5245 | case 0xc4: /* les Gv */ |
425b824a | 5246 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5247 | break; |
a38bba38 | 5248 | case 0xc5: /* lds Gv */ |
425b824a | 5249 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5250 | break; |
a38bba38 | 5251 | case 0x0fb2: /* lss Gv */ |
425b824a | 5252 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5253 | break; |
a38bba38 | 5254 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5255 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5256 | break; |
a38bba38 | 5257 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5258 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5259 | break; |
5260 | } | |
425b824a | 5261 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
5262 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5263 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5264 | break; |
5265 | ||
a38bba38 | 5266 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5267 | case 0xc1: |
5268 | case 0xd0: | |
5269 | case 0xd1: | |
5270 | case 0xd2: | |
5271 | case 0xd3: | |
5272 | if ((opcode & 1) == 0) | |
5273 | ir.ot = OT_BYTE; | |
5274 | else | |
5275 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5276 | if (i386_record_modrm (&ir)) |
5277 | return -1; | |
7ad10968 HZ |
5278 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5279 | { | |
5280 | if (i386_record_lea_modrm (&ir)) | |
5281 | return -1; | |
5282 | } | |
5283 | else | |
5284 | { | |
cf648174 HZ |
5285 | ir.rm |= ir.rex_b; |
5286 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5287 | ir.rm &= 0x3; |
cf648174 | 5288 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5289 | } |
cf648174 | 5290 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5291 | break; |
5292 | ||
5293 | case 0x0fa4: | |
5294 | case 0x0fa5: | |
5295 | case 0x0fac: | |
5296 | case 0x0fad: | |
5297 | if (i386_record_modrm (&ir)) | |
5298 | return -1; | |
5299 | if (ir.mod == 3) | |
5300 | { | |
5301 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
5302 | return -1; | |
5303 | } | |
5304 | else | |
5305 | { | |
5306 | if (i386_record_lea_modrm (&ir)) | |
5307 | return -1; | |
5308 | } | |
5309 | break; | |
5310 | ||
a38bba38 | 5311 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5312 | case 0xd9: |
5313 | case 0xda: | |
5314 | case 0xdb: | |
5315 | case 0xdc: | |
5316 | case 0xdd: | |
5317 | case 0xde: | |
5318 | case 0xdf: | |
5319 | if (i386_record_modrm (&ir)) | |
5320 | return -1; | |
5321 | ir.reg |= ((opcode & 7) << 3); | |
5322 | if (ir.mod != 3) | |
5323 | { | |
1777feb0 | 5324 | /* Memory. */ |
955db0c0 | 5325 | uint64_t addr64; |
7ad10968 | 5326 | |
955db0c0 | 5327 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5328 | return -1; |
5329 | switch (ir.reg) | |
5330 | { | |
7ad10968 | 5331 | case 0x02: |
0289bdd7 MS |
5332 | case 0x12: |
5333 | case 0x22: | |
5334 | case 0x32: | |
5335 | /* For fcom, ficom nothing to do. */ | |
5336 | break; | |
7ad10968 | 5337 | case 0x03: |
0289bdd7 MS |
5338 | case 0x13: |
5339 | case 0x23: | |
5340 | case 0x33: | |
5341 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5342 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5343 | return -1; | |
5344 | break; | |
5345 | case 0x00: | |
5346 | case 0x01: | |
7ad10968 HZ |
5347 | case 0x04: |
5348 | case 0x05: | |
5349 | case 0x06: | |
5350 | case 0x07: | |
5351 | case 0x10: | |
5352 | case 0x11: | |
7ad10968 HZ |
5353 | case 0x14: |
5354 | case 0x15: | |
5355 | case 0x16: | |
5356 | case 0x17: | |
5357 | case 0x20: | |
5358 | case 0x21: | |
7ad10968 HZ |
5359 | case 0x24: |
5360 | case 0x25: | |
5361 | case 0x26: | |
5362 | case 0x27: | |
5363 | case 0x30: | |
5364 | case 0x31: | |
7ad10968 HZ |
5365 | case 0x34: |
5366 | case 0x35: | |
5367 | case 0x36: | |
5368 | case 0x37: | |
0289bdd7 MS |
5369 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5370 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5371 | of code, always affects st(0) register. */ | |
5372 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5373 | return -1; | |
7ad10968 HZ |
5374 | break; |
5375 | case 0x08: | |
5376 | case 0x0a: | |
5377 | case 0x0b: | |
5378 | case 0x18: | |
5379 | case 0x19: | |
5380 | case 0x1a: | |
5381 | case 0x1b: | |
0289bdd7 | 5382 | case 0x1d: |
7ad10968 HZ |
5383 | case 0x28: |
5384 | case 0x29: | |
5385 | case 0x2a: | |
5386 | case 0x2b: | |
5387 | case 0x38: | |
5388 | case 0x39: | |
5389 | case 0x3a: | |
5390 | case 0x3b: | |
0289bdd7 MS |
5391 | case 0x3c: |
5392 | case 0x3d: | |
7ad10968 HZ |
5393 | switch (ir.reg & 7) |
5394 | { | |
5395 | case 0: | |
0289bdd7 MS |
5396 | /* Handling fld, fild. */ |
5397 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5398 | return -1; | |
7ad10968 HZ |
5399 | break; |
5400 | case 1: | |
5401 | switch (ir.reg >> 4) | |
5402 | { | |
5403 | case 0: | |
955db0c0 | 5404 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5405 | return -1; |
5406 | break; | |
5407 | case 2: | |
955db0c0 | 5408 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5409 | return -1; |
5410 | break; | |
5411 | case 3: | |
0289bdd7 | 5412 | break; |
7ad10968 | 5413 | default: |
955db0c0 | 5414 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5415 | return -1; |
5416 | break; | |
5417 | } | |
5418 | break; | |
5419 | default: | |
5420 | switch (ir.reg >> 4) | |
5421 | { | |
5422 | case 0: | |
955db0c0 | 5423 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5424 | return -1; |
5425 | if (3 == (ir.reg & 7)) | |
5426 | { | |
5427 | /* For fstp m32fp. */ | |
5428 | if (i386_record_floats (gdbarch, &ir, | |
5429 | I386_SAVE_FPU_REGS)) | |
5430 | return -1; | |
5431 | } | |
5432 | break; | |
7ad10968 | 5433 | case 1: |
955db0c0 | 5434 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5435 | return -1; |
0289bdd7 MS |
5436 | if ((3 == (ir.reg & 7)) |
5437 | || (5 == (ir.reg & 7)) | |
5438 | || (7 == (ir.reg & 7))) | |
5439 | { | |
5440 | /* For fstp insn. */ | |
5441 | if (i386_record_floats (gdbarch, &ir, | |
5442 | I386_SAVE_FPU_REGS)) | |
5443 | return -1; | |
5444 | } | |
7ad10968 HZ |
5445 | break; |
5446 | case 2: | |
955db0c0 | 5447 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5448 | return -1; |
0289bdd7 MS |
5449 | if (3 == (ir.reg & 7)) |
5450 | { | |
5451 | /* For fstp m64fp. */ | |
5452 | if (i386_record_floats (gdbarch, &ir, | |
5453 | I386_SAVE_FPU_REGS)) | |
5454 | return -1; | |
5455 | } | |
7ad10968 HZ |
5456 | break; |
5457 | case 3: | |
0289bdd7 MS |
5458 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5459 | { | |
5460 | /* For fistp, fbld, fild, fbstp. */ | |
5461 | if (i386_record_floats (gdbarch, &ir, | |
5462 | I386_SAVE_FPU_REGS)) | |
5463 | return -1; | |
5464 | } | |
5465 | /* Fall through */ | |
7ad10968 | 5466 | default: |
955db0c0 | 5467 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5468 | return -1; |
5469 | break; | |
5470 | } | |
5471 | break; | |
5472 | } | |
5473 | break; | |
5474 | case 0x0c: | |
0289bdd7 MS |
5475 | /* Insn fldenv. */ |
5476 | if (i386_record_floats (gdbarch, &ir, | |
5477 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5478 | return -1; | |
5479 | break; | |
7ad10968 | 5480 | case 0x0d: |
0289bdd7 MS |
5481 | /* Insn fldcw. */ |
5482 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5483 | return -1; | |
5484 | break; | |
7ad10968 | 5485 | case 0x2c: |
0289bdd7 MS |
5486 | /* Insn frstor. */ |
5487 | if (i386_record_floats (gdbarch, &ir, | |
5488 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5489 | return -1; | |
7ad10968 HZ |
5490 | break; |
5491 | case 0x0e: | |
5492 | if (ir.dflag) | |
5493 | { | |
955db0c0 | 5494 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5495 | return -1; |
5496 | } | |
5497 | else | |
5498 | { | |
955db0c0 | 5499 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5500 | return -1; |
5501 | } | |
5502 | break; | |
5503 | case 0x0f: | |
5504 | case 0x2f: | |
955db0c0 | 5505 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5506 | return -1; |
0289bdd7 MS |
5507 | /* Insn fstp, fbstp. */ |
5508 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5509 | return -1; | |
7ad10968 HZ |
5510 | break; |
5511 | case 0x1f: | |
5512 | case 0x3e: | |
955db0c0 | 5513 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5514 | return -1; |
5515 | break; | |
5516 | case 0x2e: | |
5517 | if (ir.dflag) | |
5518 | { | |
955db0c0 | 5519 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5520 | return -1; |
955db0c0 | 5521 | addr64 += 28; |
7ad10968 HZ |
5522 | } |
5523 | else | |
5524 | { | |
955db0c0 | 5525 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5526 | return -1; |
955db0c0 | 5527 | addr64 += 14; |
7ad10968 | 5528 | } |
955db0c0 | 5529 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5530 | return -1; |
0289bdd7 MS |
5531 | /* Insn fsave. */ |
5532 | if (i386_record_floats (gdbarch, &ir, | |
5533 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5534 | return -1; | |
7ad10968 HZ |
5535 | break; |
5536 | case 0x3f: | |
955db0c0 | 5537 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5538 | return -1; |
0289bdd7 MS |
5539 | /* Insn fistp. */ |
5540 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5541 | return -1; | |
7ad10968 HZ |
5542 | break; |
5543 | default: | |
5544 | ir.addr -= 2; | |
5545 | opcode = opcode << 8 | ir.modrm; | |
5546 | goto no_support; | |
5547 | break; | |
5548 | } | |
5549 | } | |
0289bdd7 MS |
5550 | /* Opcode is an extension of modR/M byte. */ |
5551 | else | |
5552 | { | |
5553 | switch (opcode) | |
5554 | { | |
5555 | case 0xd8: | |
5556 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5557 | return -1; | |
5558 | break; | |
5559 | case 0xd9: | |
5560 | if (0x0c == (ir.modrm >> 4)) | |
5561 | { | |
5562 | if ((ir.modrm & 0x0f) <= 7) | |
5563 | { | |
5564 | if (i386_record_floats (gdbarch, &ir, | |
5565 | I386_SAVE_FPU_REGS)) | |
5566 | return -1; | |
5567 | } | |
5568 | else | |
5569 | { | |
5570 | if (i386_record_floats (gdbarch, &ir, | |
5571 | I387_ST0_REGNUM (tdep))) | |
5572 | return -1; | |
5573 | /* If only st(0) is changing, then we have already | |
5574 | recorded. */ | |
5575 | if ((ir.modrm & 0x0f) - 0x08) | |
5576 | { | |
5577 | if (i386_record_floats (gdbarch, &ir, | |
5578 | I387_ST0_REGNUM (tdep) + | |
5579 | ((ir.modrm & 0x0f) - 0x08))) | |
5580 | return -1; | |
5581 | } | |
5582 | } | |
5583 | } | |
5584 | else | |
5585 | { | |
5586 | switch (ir.modrm) | |
5587 | { | |
5588 | case 0xe0: | |
5589 | case 0xe1: | |
5590 | case 0xf0: | |
5591 | case 0xf5: | |
5592 | case 0xf8: | |
5593 | case 0xfa: | |
5594 | case 0xfc: | |
5595 | case 0xfe: | |
5596 | case 0xff: | |
5597 | if (i386_record_floats (gdbarch, &ir, | |
5598 | I387_ST0_REGNUM (tdep))) | |
5599 | return -1; | |
5600 | break; | |
5601 | case 0xf1: | |
5602 | case 0xf2: | |
5603 | case 0xf3: | |
5604 | case 0xf4: | |
5605 | case 0xf6: | |
5606 | case 0xf7: | |
5607 | case 0xe8: | |
5608 | case 0xe9: | |
5609 | case 0xea: | |
5610 | case 0xeb: | |
5611 | case 0xec: | |
5612 | case 0xed: | |
5613 | case 0xee: | |
5614 | case 0xf9: | |
5615 | case 0xfb: | |
5616 | if (i386_record_floats (gdbarch, &ir, | |
5617 | I386_SAVE_FPU_REGS)) | |
5618 | return -1; | |
5619 | break; | |
5620 | case 0xfd: | |
5621 | if (i386_record_floats (gdbarch, &ir, | |
5622 | I387_ST0_REGNUM (tdep))) | |
5623 | return -1; | |
5624 | if (i386_record_floats (gdbarch, &ir, | |
5625 | I387_ST0_REGNUM (tdep) + 1)) | |
5626 | return -1; | |
5627 | break; | |
5628 | } | |
5629 | } | |
5630 | break; | |
5631 | case 0xda: | |
5632 | if (0xe9 == ir.modrm) | |
5633 | { | |
5634 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5635 | return -1; | |
5636 | } | |
5637 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5638 | { | |
5639 | if (i386_record_floats (gdbarch, &ir, | |
5640 | I387_ST0_REGNUM (tdep))) | |
5641 | return -1; | |
5642 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5643 | { | |
5644 | if (i386_record_floats (gdbarch, &ir, | |
5645 | I387_ST0_REGNUM (tdep) + | |
5646 | (ir.modrm & 0x0f))) | |
5647 | return -1; | |
5648 | } | |
5649 | else if ((ir.modrm & 0x0f) - 0x08) | |
5650 | { | |
5651 | if (i386_record_floats (gdbarch, &ir, | |
5652 | I387_ST0_REGNUM (tdep) + | |
5653 | ((ir.modrm & 0x0f) - 0x08))) | |
5654 | return -1; | |
5655 | } | |
5656 | } | |
5657 | break; | |
5658 | case 0xdb: | |
5659 | if (0xe3 == ir.modrm) | |
5660 | { | |
5661 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5662 | return -1; | |
5663 | } | |
5664 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5665 | { | |
5666 | if (i386_record_floats (gdbarch, &ir, | |
5667 | I387_ST0_REGNUM (tdep))) | |
5668 | return -1; | |
5669 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5670 | { | |
5671 | if (i386_record_floats (gdbarch, &ir, | |
5672 | I387_ST0_REGNUM (tdep) + | |
5673 | (ir.modrm & 0x0f))) | |
5674 | return -1; | |
5675 | } | |
5676 | else if ((ir.modrm & 0x0f) - 0x08) | |
5677 | { | |
5678 | if (i386_record_floats (gdbarch, &ir, | |
5679 | I387_ST0_REGNUM (tdep) + | |
5680 | ((ir.modrm & 0x0f) - 0x08))) | |
5681 | return -1; | |
5682 | } | |
5683 | } | |
5684 | break; | |
5685 | case 0xdc: | |
5686 | if ((0x0c == ir.modrm >> 4) | |
5687 | || (0x0d == ir.modrm >> 4) | |
5688 | || (0x0f == ir.modrm >> 4)) | |
5689 | { | |
5690 | if ((ir.modrm & 0x0f) <= 7) | |
5691 | { | |
5692 | if (i386_record_floats (gdbarch, &ir, | |
5693 | I387_ST0_REGNUM (tdep) + | |
5694 | (ir.modrm & 0x0f))) | |
5695 | return -1; | |
5696 | } | |
5697 | else | |
5698 | { | |
5699 | if (i386_record_floats (gdbarch, &ir, | |
5700 | I387_ST0_REGNUM (tdep) + | |
5701 | ((ir.modrm & 0x0f) - 0x08))) | |
5702 | return -1; | |
5703 | } | |
5704 | } | |
5705 | break; | |
5706 | case 0xdd: | |
5707 | if (0x0c == ir.modrm >> 4) | |
5708 | { | |
5709 | if (i386_record_floats (gdbarch, &ir, | |
5710 | I387_FTAG_REGNUM (tdep))) | |
5711 | return -1; | |
5712 | } | |
5713 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5714 | { | |
5715 | if ((ir.modrm & 0x0f) <= 7) | |
5716 | { | |
5717 | if (i386_record_floats (gdbarch, &ir, | |
5718 | I387_ST0_REGNUM (tdep) + | |
5719 | (ir.modrm & 0x0f))) | |
5720 | return -1; | |
5721 | } | |
5722 | else | |
5723 | { | |
5724 | if (i386_record_floats (gdbarch, &ir, | |
5725 | I386_SAVE_FPU_REGS)) | |
5726 | return -1; | |
5727 | } | |
5728 | } | |
5729 | break; | |
5730 | case 0xde: | |
5731 | if ((0x0c == ir.modrm >> 4) | |
5732 | || (0x0e == ir.modrm >> 4) | |
5733 | || (0x0f == ir.modrm >> 4) | |
5734 | || (0xd9 == ir.modrm)) | |
5735 | { | |
5736 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5737 | return -1; | |
5738 | } | |
5739 | break; | |
5740 | case 0xdf: | |
5741 | if (0xe0 == ir.modrm) | |
5742 | { | |
5743 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5744 | return -1; | |
5745 | } | |
5746 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5747 | { | |
5748 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5749 | return -1; | |
5750 | } | |
5751 | break; | |
5752 | } | |
5753 | } | |
7ad10968 | 5754 | break; |
7ad10968 | 5755 | /* string ops */ |
a38bba38 | 5756 | case 0xa4: /* movsS */ |
7ad10968 | 5757 | case 0xa5: |
a38bba38 | 5758 | case 0xaa: /* stosS */ |
7ad10968 | 5759 | case 0xab: |
a38bba38 | 5760 | case 0x6c: /* insS */ |
7ad10968 | 5761 | case 0x6d: |
cf648174 | 5762 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5763 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5764 | &addr); |
5765 | if (addr) | |
cf648174 | 5766 | { |
77d7dc92 HZ |
5767 | ULONGEST es, ds; |
5768 | ||
5769 | if ((opcode & 1) == 0) | |
5770 | ir.ot = OT_BYTE; | |
5771 | else | |
5772 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5773 | regcache_raw_read_unsigned (ir.regcache, |
5774 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5775 | &addr); |
77d7dc92 | 5776 | |
d7877f7e HZ |
5777 | regcache_raw_read_unsigned (ir.regcache, |
5778 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5779 | &es); | |
5780 | regcache_raw_read_unsigned (ir.regcache, | |
5781 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5782 | &ds); | |
5783 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5784 | { |
5785 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5786 | if (record_memory_query) |
5787 | { | |
5788 | int q; | |
5789 | ||
5790 | target_terminal_ours (); | |
5791 | q = yquery (_("\ | |
5792 | Process record ignores the memory change of instruction at address %s\n\ | |
5793 | because it can't get the value of the segment register.\n\ | |
5794 | Do you want to stop the program?"), | |
5795 | paddress (gdbarch, ir.orig_addr)); | |
5796 | target_terminal_inferior (); | |
5797 | if (q) | |
5798 | return -1; | |
5799 | } | |
df61f520 HZ |
5800 | } |
5801 | else | |
5802 | { | |
648d0c8b | 5803 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5804 | return -1; |
77d7dc92 HZ |
5805 | } |
5806 | ||
5807 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5809 | if (opcode == 0xa4 || opcode == 0xa5) |
5810 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5811 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5812 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5813 | } | |
cf648174 | 5814 | break; |
7ad10968 | 5815 | |
a38bba38 | 5816 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5817 | case 0xa7: |
5818 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5819 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5820 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5821 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5822 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5823 | break; |
5824 | ||
a38bba38 | 5825 | case 0xac: /* lodsS */ |
7ad10968 | 5826 | case 0xad: |
cf648174 HZ |
5827 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5828 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5829 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5830 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5831 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5832 | break; |
5833 | ||
a38bba38 | 5834 | case 0xae: /* scasS */ |
7ad10968 | 5835 | case 0xaf: |
cf648174 | 5836 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5837 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5838 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5839 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5840 | break; |
5841 | ||
a38bba38 | 5842 | case 0x6e: /* outsS */ |
cf648174 HZ |
5843 | case 0x6f: |
5844 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5845 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5846 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5847 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5848 | break; |
5849 | ||
a38bba38 | 5850 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5851 | case 0xe5: |
5852 | case 0xec: | |
5853 | case 0xed: | |
cf648174 HZ |
5854 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5855 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5856 | break; |
5857 | ||
5858 | case 0xe6: | |
5859 | case 0xe7: | |
5860 | case 0xee: | |
5861 | case 0xef: | |
5862 | break; | |
5863 | ||
5864 | /* control */ | |
a38bba38 MS |
5865 | case 0xc2: /* ret im */ |
5866 | case 0xc3: /* ret */ | |
cf648174 HZ |
5867 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5868 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5869 | break; | |
5870 | ||
a38bba38 MS |
5871 | case 0xca: /* lret im */ |
5872 | case 0xcb: /* lret */ | |
5873 | case 0xcf: /* iret */ | |
cf648174 HZ |
5874 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5875 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5876 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5877 | break; |
5878 | ||
a38bba38 | 5879 | case 0xe8: /* call im */ |
cf648174 HZ |
5880 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5881 | ir.dflag = 2; | |
5882 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5883 | return -1; | |
7ad10968 HZ |
5884 | break; |
5885 | ||
a38bba38 | 5886 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5887 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5888 | { | |
5889 | ir.addr -= 1; | |
5890 | goto no_support; | |
5891 | } | |
5892 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5893 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5894 | return -1; | |
7ad10968 HZ |
5895 | break; |
5896 | ||
a38bba38 MS |
5897 | case 0xe9: /* jmp im */ |
5898 | case 0xea: /* ljmp im */ | |
5899 | case 0xeb: /* jmp Jb */ | |
5900 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5901 | case 0x71: |
5902 | case 0x72: | |
5903 | case 0x73: | |
5904 | case 0x74: | |
5905 | case 0x75: | |
5906 | case 0x76: | |
5907 | case 0x77: | |
5908 | case 0x78: | |
5909 | case 0x79: | |
5910 | case 0x7a: | |
5911 | case 0x7b: | |
5912 | case 0x7c: | |
5913 | case 0x7d: | |
5914 | case 0x7e: | |
5915 | case 0x7f: | |
a38bba38 | 5916 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5917 | case 0x0f81: |
5918 | case 0x0f82: | |
5919 | case 0x0f83: | |
5920 | case 0x0f84: | |
5921 | case 0x0f85: | |
5922 | case 0x0f86: | |
5923 | case 0x0f87: | |
5924 | case 0x0f88: | |
5925 | case 0x0f89: | |
5926 | case 0x0f8a: | |
5927 | case 0x0f8b: | |
5928 | case 0x0f8c: | |
5929 | case 0x0f8d: | |
5930 | case 0x0f8e: | |
5931 | case 0x0f8f: | |
5932 | break; | |
5933 | ||
a38bba38 | 5934 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5935 | case 0x0f91: |
5936 | case 0x0f92: | |
5937 | case 0x0f93: | |
5938 | case 0x0f94: | |
5939 | case 0x0f95: | |
5940 | case 0x0f96: | |
5941 | case 0x0f97: | |
5942 | case 0x0f98: | |
5943 | case 0x0f99: | |
5944 | case 0x0f9a: | |
5945 | case 0x0f9b: | |
5946 | case 0x0f9c: | |
5947 | case 0x0f9d: | |
5948 | case 0x0f9e: | |
5949 | case 0x0f9f: | |
cf648174 | 5950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5951 | ir.ot = OT_BYTE; |
5952 | if (i386_record_modrm (&ir)) | |
5953 | return -1; | |
5954 | if (ir.mod == 3) | |
cf648174 HZ |
5955 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5956 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5957 | else |
5958 | { | |
5959 | if (i386_record_lea_modrm (&ir)) | |
5960 | return -1; | |
5961 | } | |
5962 | break; | |
5963 | ||
a38bba38 | 5964 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5965 | case 0x0f41: |
5966 | case 0x0f42: | |
5967 | case 0x0f43: | |
5968 | case 0x0f44: | |
5969 | case 0x0f45: | |
5970 | case 0x0f46: | |
5971 | case 0x0f47: | |
5972 | case 0x0f48: | |
5973 | case 0x0f49: | |
5974 | case 0x0f4a: | |
5975 | case 0x0f4b: | |
5976 | case 0x0f4c: | |
5977 | case 0x0f4d: | |
5978 | case 0x0f4e: | |
5979 | case 0x0f4f: | |
5980 | if (i386_record_modrm (&ir)) | |
5981 | return -1; | |
cf648174 | 5982 | ir.reg |= rex_r; |
7ad10968 HZ |
5983 | if (ir.dflag == OT_BYTE) |
5984 | ir.reg &= 0x3; | |
cf648174 | 5985 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5986 | break; |
5987 | ||
5988 | /* flags */ | |
a38bba38 | 5989 | case 0x9c: /* pushf */ |
cf648174 HZ |
5990 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5991 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5992 | ir.dflag = 2; | |
5993 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5994 | return -1; | |
7ad10968 HZ |
5995 | break; |
5996 | ||
a38bba38 | 5997 | case 0x9d: /* popf */ |
cf648174 HZ |
5998 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5999 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6000 | break; |
6001 | ||
a38bba38 | 6002 | case 0x9e: /* sahf */ |
cf648174 HZ |
6003 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6004 | { | |
6005 | ir.addr -= 1; | |
6006 | goto no_support; | |
6007 | } | |
d3f323f3 | 6008 | /* FALLTHROUGH */ |
a38bba38 MS |
6009 | case 0xf5: /* cmc */ |
6010 | case 0xf8: /* clc */ | |
6011 | case 0xf9: /* stc */ | |
6012 | case 0xfc: /* cld */ | |
6013 | case 0xfd: /* std */ | |
cf648174 | 6014 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6015 | break; |
6016 | ||
a38bba38 | 6017 | case 0x9f: /* lahf */ |
cf648174 HZ |
6018 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6019 | { | |
6020 | ir.addr -= 1; | |
6021 | goto no_support; | |
6022 | } | |
6023 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6024 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6025 | break; |
6026 | ||
6027 | /* bit operations */ | |
a38bba38 | 6028 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6029 | ir.ot = ir.dflag + OT_WORD; |
6030 | if (i386_record_modrm (&ir)) | |
6031 | return -1; | |
6032 | if (ir.reg < 4) | |
6033 | { | |
cf648174 | 6034 | ir.addr -= 2; |
7ad10968 HZ |
6035 | opcode = opcode << 8 | ir.modrm; |
6036 | goto no_support; | |
6037 | } | |
cf648174 | 6038 | if (ir.reg != 4) |
7ad10968 | 6039 | { |
cf648174 HZ |
6040 | if (ir.mod == 3) |
6041 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
6042 | else |
6043 | { | |
cf648174 | 6044 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6045 | return -1; |
6046 | } | |
6047 | } | |
cf648174 | 6048 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6049 | break; |
6050 | ||
a38bba38 | 6051 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
6052 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6053 | break; | |
6054 | ||
a38bba38 MS |
6055 | case 0x0fab: /* bts */ |
6056 | case 0x0fb3: /* btr */ | |
6057 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6058 | ir.ot = ir.dflag + OT_WORD; |
6059 | if (i386_record_modrm (&ir)) | |
6060 | return -1; | |
6061 | if (ir.mod == 3) | |
6062 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6063 | else | |
6064 | { | |
955db0c0 MS |
6065 | uint64_t addr64; |
6066 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6067 | return -1; |
6068 | regcache_raw_read_unsigned (ir.regcache, | |
6069 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6070 | &addr); |
cf648174 HZ |
6071 | switch (ir.dflag) |
6072 | { | |
6073 | case 0: | |
648d0c8b | 6074 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6075 | break; |
6076 | case 1: | |
648d0c8b | 6077 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6078 | break; |
6079 | case 2: | |
648d0c8b | 6080 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6081 | break; |
6082 | } | |
955db0c0 | 6083 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6084 | return -1; |
6085 | if (i386_record_lea_modrm (&ir)) | |
6086 | return -1; | |
6087 | } | |
6088 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6089 | break; |
6090 | ||
a38bba38 MS |
6091 | case 0x0fbc: /* bsf */ |
6092 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
6093 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6094 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6095 | break; |
6096 | ||
6097 | /* bcd */ | |
a38bba38 MS |
6098 | case 0x27: /* daa */ |
6099 | case 0x2f: /* das */ | |
6100 | case 0x37: /* aaa */ | |
6101 | case 0x3f: /* aas */ | |
6102 | case 0xd4: /* aam */ | |
6103 | case 0xd5: /* aad */ | |
cf648174 HZ |
6104 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6105 | { | |
6106 | ir.addr -= 1; | |
6107 | goto no_support; | |
6108 | } | |
6109 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6110 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6111 | break; |
6112 | ||
6113 | /* misc */ | |
a38bba38 | 6114 | case 0x90: /* nop */ |
7ad10968 HZ |
6115 | if (prefixes & PREFIX_LOCK) |
6116 | { | |
6117 | ir.addr -= 1; | |
6118 | goto no_support; | |
6119 | } | |
6120 | break; | |
6121 | ||
a38bba38 | 6122 | case 0x9b: /* fwait */ |
425b824a | 6123 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
6124 | { |
6125 | if (record_debug) | |
6126 | printf_unfiltered (_("Process record: error reading memory at " | |
6127 | "addr 0x%s len = 1.\n"), | |
6128 | paddress (gdbarch, ir.addr)); | |
6129 | return -1; | |
6130 | } | |
425b824a | 6131 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6132 | ir.addr++; |
6133 | goto reswitch; | |
7ad10968 HZ |
6134 | break; |
6135 | ||
7ad10968 | 6136 | /* XXX */ |
a38bba38 | 6137 | case 0xcc: /* int3 */ |
a3c4230a | 6138 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6139 | "int3.\n")); |
6140 | ir.addr -= 1; | |
6141 | goto no_support; | |
6142 | break; | |
6143 | ||
7ad10968 | 6144 | /* XXX */ |
a38bba38 | 6145 | case 0xcd: /* int */ |
7ad10968 HZ |
6146 | { |
6147 | int ret; | |
425b824a MS |
6148 | uint8_t interrupt; |
6149 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
6150 | { |
6151 | if (record_debug) | |
6152 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
6153 | "at addr %s len = 1.\n"), |
6154 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
6155 | return -1; |
6156 | } | |
6157 | ir.addr++; | |
425b824a | 6158 | if (interrupt != 0x80 |
a3c4230a | 6159 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6160 | { |
a3c4230a | 6161 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6162 | "instruction int 0x%02x.\n"), |
425b824a | 6163 | interrupt); |
7ad10968 HZ |
6164 | ir.addr -= 2; |
6165 | goto no_support; | |
6166 | } | |
a3c4230a | 6167 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6168 | if (ret) |
6169 | return ret; | |
6170 | } | |
6171 | break; | |
6172 | ||
7ad10968 | 6173 | /* XXX */ |
a38bba38 | 6174 | case 0xce: /* into */ |
a3c4230a | 6175 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6176 | "instruction into.\n")); |
6177 | ir.addr -= 1; | |
6178 | goto no_support; | |
6179 | break; | |
6180 | ||
a38bba38 MS |
6181 | case 0xfa: /* cli */ |
6182 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6183 | break; |
6184 | ||
a38bba38 | 6185 | case 0x62: /* bound */ |
a3c4230a | 6186 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6187 | "instruction bound.\n")); |
6188 | ir.addr -= 1; | |
6189 | goto no_support; | |
6190 | break; | |
6191 | ||
a38bba38 | 6192 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6193 | case 0x0fc9: |
6194 | case 0x0fca: | |
6195 | case 0x0fcb: | |
6196 | case 0x0fcc: | |
6197 | case 0x0fcd: | |
6198 | case 0x0fce: | |
6199 | case 0x0fcf: | |
cf648174 | 6200 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6201 | break; |
6202 | ||
a38bba38 | 6203 | case 0xd6: /* salc */ |
cf648174 HZ |
6204 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6205 | { | |
6206 | ir.addr -= 1; | |
6207 | goto no_support; | |
6208 | } | |
6209 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6210 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6211 | break; |
6212 | ||
a38bba38 MS |
6213 | case 0xe0: /* loopnz */ |
6214 | case 0xe1: /* loopz */ | |
6215 | case 0xe2: /* loop */ | |
6216 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
6217 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6218 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6219 | break; |
6220 | ||
a38bba38 | 6221 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6222 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6223 | "instruction wrmsr.\n")); |
6224 | ir.addr -= 2; | |
6225 | goto no_support; | |
6226 | break; | |
6227 | ||
a38bba38 | 6228 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6229 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6230 | "instruction rdmsr.\n")); |
6231 | ir.addr -= 2; | |
6232 | goto no_support; | |
6233 | break; | |
6234 | ||
a38bba38 | 6235 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
6236 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6237 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6238 | break; |
6239 | ||
a38bba38 | 6240 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6241 | { |
6242 | int ret; | |
cf648174 HZ |
6243 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6244 | { | |
6245 | ir.addr -= 2; | |
6246 | goto no_support; | |
6247 | } | |
a3c4230a | 6248 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6249 | { |
a3c4230a | 6250 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6251 | "instruction sysenter.\n")); |
6252 | ir.addr -= 2; | |
6253 | goto no_support; | |
6254 | } | |
a3c4230a | 6255 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6256 | if (ret) |
6257 | return ret; | |
6258 | } | |
6259 | break; | |
6260 | ||
a38bba38 | 6261 | case 0x0f35: /* sysexit */ |
a3c4230a | 6262 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6263 | "instruction sysexit.\n")); |
6264 | ir.addr -= 2; | |
6265 | goto no_support; | |
6266 | break; | |
6267 | ||
a38bba38 | 6268 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6269 | { |
6270 | int ret; | |
a3c4230a | 6271 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6272 | { |
a3c4230a | 6273 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6274 | "instruction syscall.\n")); |
6275 | ir.addr -= 2; | |
6276 | goto no_support; | |
6277 | } | |
a3c4230a | 6278 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6279 | if (ret) |
6280 | return ret; | |
6281 | } | |
6282 | break; | |
6283 | ||
a38bba38 | 6284 | case 0x0f07: /* sysret */ |
a3c4230a | 6285 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6286 | "instruction sysret.\n")); |
6287 | ir.addr -= 2; | |
6288 | goto no_support; | |
6289 | break; | |
6290 | ||
a38bba38 | 6291 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
6292 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6293 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6294 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6295 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6296 | break; |
6297 | ||
a38bba38 | 6298 | case 0xf4: /* hlt */ |
a3c4230a | 6299 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6300 | "instruction hlt.\n")); |
6301 | ir.addr -= 1; | |
6302 | goto no_support; | |
6303 | break; | |
6304 | ||
6305 | case 0x0f00: | |
6306 | if (i386_record_modrm (&ir)) | |
6307 | return -1; | |
6308 | switch (ir.reg) | |
6309 | { | |
a38bba38 MS |
6310 | case 0: /* sldt */ |
6311 | case 1: /* str */ | |
7ad10968 | 6312 | if (ir.mod == 3) |
cf648174 | 6313 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6314 | else |
6315 | { | |
6316 | ir.ot = OT_WORD; | |
6317 | if (i386_record_lea_modrm (&ir)) | |
6318 | return -1; | |
6319 | } | |
6320 | break; | |
a38bba38 MS |
6321 | case 2: /* lldt */ |
6322 | case 3: /* ltr */ | |
7ad10968 | 6323 | break; |
a38bba38 MS |
6324 | case 4: /* verr */ |
6325 | case 5: /* verw */ | |
cf648174 | 6326 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6327 | break; |
6328 | default: | |
6329 | ir.addr -= 3; | |
6330 | opcode = opcode << 8 | ir.modrm; | |
6331 | goto no_support; | |
6332 | break; | |
6333 | } | |
6334 | break; | |
6335 | ||
6336 | case 0x0f01: | |
6337 | if (i386_record_modrm (&ir)) | |
6338 | return -1; | |
6339 | switch (ir.reg) | |
6340 | { | |
a38bba38 | 6341 | case 0: /* sgdt */ |
7ad10968 | 6342 | { |
955db0c0 | 6343 | uint64_t addr64; |
7ad10968 HZ |
6344 | |
6345 | if (ir.mod == 3) | |
6346 | { | |
6347 | ir.addr -= 3; | |
6348 | opcode = opcode << 8 | ir.modrm; | |
6349 | goto no_support; | |
6350 | } | |
d7877f7e | 6351 | if (ir.override >= 0) |
7ad10968 | 6352 | { |
bb08c432 HZ |
6353 | if (record_memory_query) |
6354 | { | |
6355 | int q; | |
6356 | ||
6357 | target_terminal_ours (); | |
6358 | q = yquery (_("\ | |
6359 | Process record ignores the memory change of instruction at address %s\n\ | |
6360 | because it can't get the value of the segment register.\n\ | |
6361 | Do you want to stop the program?"), | |
6362 | paddress (gdbarch, ir.orig_addr)); | |
6363 | target_terminal_inferior (); | |
6364 | if (q) | |
6365 | return -1; | |
6366 | } | |
7ad10968 HZ |
6367 | } |
6368 | else | |
6369 | { | |
955db0c0 | 6370 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6371 | return -1; |
955db0c0 | 6372 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6373 | return -1; |
955db0c0 | 6374 | addr64 += 2; |
cf648174 HZ |
6375 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6376 | { | |
955db0c0 | 6377 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6378 | return -1; |
6379 | } | |
6380 | else | |
6381 | { | |
955db0c0 | 6382 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6383 | return -1; |
6384 | } | |
7ad10968 HZ |
6385 | } |
6386 | } | |
6387 | break; | |
6388 | case 1: | |
6389 | if (ir.mod == 3) | |
6390 | { | |
6391 | switch (ir.rm) | |
6392 | { | |
a38bba38 | 6393 | case 0: /* monitor */ |
7ad10968 | 6394 | break; |
a38bba38 | 6395 | case 1: /* mwait */ |
cf648174 | 6396 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6397 | break; |
6398 | default: | |
6399 | ir.addr -= 3; | |
6400 | opcode = opcode << 8 | ir.modrm; | |
6401 | goto no_support; | |
6402 | break; | |
6403 | } | |
6404 | } | |
6405 | else | |
6406 | { | |
6407 | /* sidt */ | |
d7877f7e | 6408 | if (ir.override >= 0) |
7ad10968 | 6409 | { |
bb08c432 HZ |
6410 | if (record_memory_query) |
6411 | { | |
6412 | int q; | |
6413 | ||
6414 | target_terminal_ours (); | |
6415 | q = yquery (_("\ | |
6416 | Process record ignores the memory change of instruction at address %s\n\ | |
6417 | because it can't get the value of the segment register.\n\ | |
6418 | Do you want to stop the program?"), | |
6419 | paddress (gdbarch, ir.orig_addr)); | |
6420 | target_terminal_inferior (); | |
6421 | if (q) | |
6422 | return -1; | |
6423 | } | |
7ad10968 HZ |
6424 | } |
6425 | else | |
6426 | { | |
955db0c0 | 6427 | uint64_t addr64; |
7ad10968 | 6428 | |
955db0c0 | 6429 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6430 | return -1; |
955db0c0 | 6431 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6432 | return -1; |
955db0c0 | 6433 | addr64 += 2; |
cf648174 HZ |
6434 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6435 | { | |
955db0c0 | 6436 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6437 | return -1; |
6438 | } | |
6439 | else | |
6440 | { | |
955db0c0 | 6441 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6442 | return -1; |
6443 | } | |
7ad10968 HZ |
6444 | } |
6445 | } | |
6446 | break; | |
a38bba38 | 6447 | case 2: /* lgdt */ |
3800e645 MS |
6448 | if (ir.mod == 3) |
6449 | { | |
6450 | /* xgetbv */ | |
6451 | if (ir.rm == 0) | |
6452 | { | |
6453 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6454 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6455 | break; | |
6456 | } | |
6457 | /* xsetbv */ | |
6458 | else if (ir.rm == 1) | |
6459 | break; | |
6460 | } | |
a38bba38 | 6461 | case 3: /* lidt */ |
7ad10968 HZ |
6462 | if (ir.mod == 3) |
6463 | { | |
6464 | ir.addr -= 3; | |
6465 | opcode = opcode << 8 | ir.modrm; | |
6466 | goto no_support; | |
6467 | } | |
6468 | break; | |
a38bba38 | 6469 | case 4: /* smsw */ |
7ad10968 HZ |
6470 | if (ir.mod == 3) |
6471 | { | |
cf648174 | 6472 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6473 | return -1; |
6474 | } | |
6475 | else | |
6476 | { | |
6477 | ir.ot = OT_WORD; | |
6478 | if (i386_record_lea_modrm (&ir)) | |
6479 | return -1; | |
6480 | } | |
cf648174 | 6481 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6482 | break; |
a38bba38 | 6483 | case 6: /* lmsw */ |
cf648174 HZ |
6484 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6485 | break; | |
a38bba38 | 6486 | case 7: /* invlpg */ |
cf648174 HZ |
6487 | if (ir.mod == 3) |
6488 | { | |
6489 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
6490 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
6491 | else | |
6492 | { | |
6493 | ir.addr -= 3; | |
6494 | opcode = opcode << 8 | ir.modrm; | |
6495 | goto no_support; | |
6496 | } | |
6497 | } | |
6498 | else | |
6499 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6500 | break; | |
6501 | default: | |
6502 | ir.addr -= 3; | |
6503 | opcode = opcode << 8 | ir.modrm; | |
6504 | goto no_support; | |
7ad10968 HZ |
6505 | break; |
6506 | } | |
6507 | break; | |
6508 | ||
a38bba38 MS |
6509 | case 0x0f08: /* invd */ |
6510 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6511 | break; |
6512 | ||
a38bba38 | 6513 | case 0x63: /* arpl */ |
7ad10968 HZ |
6514 | if (i386_record_modrm (&ir)) |
6515 | return -1; | |
cf648174 HZ |
6516 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6517 | { | |
6518 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
6519 | ? (ir.reg | rex_r) : ir.rm); | |
6520 | } | |
7ad10968 | 6521 | else |
cf648174 HZ |
6522 | { |
6523 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6524 | if (i386_record_lea_modrm (&ir)) | |
6525 | return -1; | |
6526 | } | |
6527 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
6528 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6529 | break; |
6530 | ||
a38bba38 MS |
6531 | case 0x0f02: /* lar */ |
6532 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6533 | if (i386_record_modrm (&ir)) |
6534 | return -1; | |
cf648174 HZ |
6535 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6536 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6537 | break; |
6538 | ||
6539 | case 0x0f18: | |
cf648174 HZ |
6540 | if (i386_record_modrm (&ir)) |
6541 | return -1; | |
6542 | if (ir.mod == 3 && ir.reg == 3) | |
6543 | { | |
6544 | ir.addr -= 3; | |
6545 | opcode = opcode << 8 | ir.modrm; | |
6546 | goto no_support; | |
6547 | } | |
7ad10968 HZ |
6548 | break; |
6549 | ||
7ad10968 HZ |
6550 | case 0x0f19: |
6551 | case 0x0f1a: | |
6552 | case 0x0f1b: | |
6553 | case 0x0f1c: | |
6554 | case 0x0f1d: | |
6555 | case 0x0f1e: | |
6556 | case 0x0f1f: | |
a38bba38 | 6557 | /* nop (multi byte) */ |
7ad10968 HZ |
6558 | break; |
6559 | ||
a38bba38 MS |
6560 | case 0x0f20: /* mov reg, crN */ |
6561 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6562 | if (i386_record_modrm (&ir)) |
6563 | return -1; | |
6564 | if ((ir.modrm & 0xc0) != 0xc0) | |
6565 | { | |
cf648174 | 6566 | ir.addr -= 3; |
7ad10968 HZ |
6567 | opcode = opcode << 8 | ir.modrm; |
6568 | goto no_support; | |
6569 | } | |
6570 | switch (ir.reg) | |
6571 | { | |
6572 | case 0: | |
6573 | case 2: | |
6574 | case 3: | |
6575 | case 4: | |
6576 | case 8: | |
6577 | if (opcode & 2) | |
cf648174 | 6578 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6579 | else |
cf648174 | 6580 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6581 | break; |
6582 | default: | |
cf648174 | 6583 | ir.addr -= 3; |
7ad10968 HZ |
6584 | opcode = opcode << 8 | ir.modrm; |
6585 | goto no_support; | |
6586 | break; | |
6587 | } | |
6588 | break; | |
6589 | ||
a38bba38 MS |
6590 | case 0x0f21: /* mov reg, drN */ |
6591 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6592 | if (i386_record_modrm (&ir)) |
6593 | return -1; | |
6594 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6595 | || ir.reg == 5 || ir.reg >= 8) | |
6596 | { | |
cf648174 | 6597 | ir.addr -= 3; |
7ad10968 HZ |
6598 | opcode = opcode << 8 | ir.modrm; |
6599 | goto no_support; | |
6600 | } | |
6601 | if (opcode & 2) | |
cf648174 | 6602 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6603 | else |
cf648174 | 6604 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6605 | break; |
6606 | ||
a38bba38 | 6607 | case 0x0f06: /* clts */ |
cf648174 | 6608 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6609 | break; |
6610 | ||
a3c4230a HZ |
6611 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6612 | ||
6613 | case 0x0f0d: /* 3DNow! prefetch */ | |
6614 | break; | |
6615 | ||
6616 | case 0x0f0e: /* 3DNow! femms */ | |
6617 | case 0x0f77: /* emms */ | |
6618 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6619 | goto no_support; | |
6620 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
6621 | break; | |
6622 | ||
6623 | case 0x0f0f: /* 3DNow! data */ | |
6624 | if (i386_record_modrm (&ir)) | |
6625 | return -1; | |
6626 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6627 | { | |
6628 | printf_unfiltered (_("Process record: error reading memory at " | |
6629 | "addr %s len = 1.\n"), | |
6630 | paddress (gdbarch, ir.addr)); | |
6631 | return -1; | |
6632 | } | |
6633 | ir.addr++; | |
6634 | switch (opcode8) | |
6635 | { | |
6636 | case 0x0c: /* 3DNow! pi2fw */ | |
6637 | case 0x0d: /* 3DNow! pi2fd */ | |
6638 | case 0x1c: /* 3DNow! pf2iw */ | |
6639 | case 0x1d: /* 3DNow! pf2id */ | |
6640 | case 0x8a: /* 3DNow! pfnacc */ | |
6641 | case 0x8e: /* 3DNow! pfpnacc */ | |
6642 | case 0x90: /* 3DNow! pfcmpge */ | |
6643 | case 0x94: /* 3DNow! pfmin */ | |
6644 | case 0x96: /* 3DNow! pfrcp */ | |
6645 | case 0x97: /* 3DNow! pfrsqrt */ | |
6646 | case 0x9a: /* 3DNow! pfsub */ | |
6647 | case 0x9e: /* 3DNow! pfadd */ | |
6648 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6649 | case 0xa4: /* 3DNow! pfmax */ | |
6650 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6651 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6652 | case 0xaa: /* 3DNow! pfsubr */ | |
6653 | case 0xae: /* 3DNow! pfacc */ | |
6654 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6655 | case 0xb4: /* 3DNow! pfmul */ | |
6656 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6657 | case 0xb7: /* 3DNow! pmulhrw */ | |
6658 | case 0xbb: /* 3DNow! pswapd */ | |
6659 | case 0xbf: /* 3DNow! pavgusb */ | |
6660 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6661 | goto no_support_3dnow_data; | |
6662 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6663 | break; | |
6664 | ||
6665 | default: | |
6666 | no_support_3dnow_data: | |
6667 | opcode = (opcode << 8) | opcode8; | |
6668 | goto no_support; | |
6669 | break; | |
6670 | } | |
6671 | break; | |
6672 | ||
6673 | case 0x0faa: /* rsm */ | |
6674 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6675 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6676 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6677 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6678 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6679 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6680 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6681 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6682 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6683 | break; | |
6684 | ||
6685 | case 0x0fae: | |
6686 | if (i386_record_modrm (&ir)) | |
6687 | return -1; | |
6688 | switch(ir.reg) | |
6689 | { | |
6690 | case 0: /* fxsave */ | |
6691 | { | |
6692 | uint64_t tmpu64; | |
6693 | ||
6694 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6695 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6696 | return -1; | |
6697 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6698 | return -1; | |
6699 | } | |
6700 | break; | |
6701 | ||
6702 | case 1: /* fxrstor */ | |
6703 | { | |
6704 | int i; | |
6705 | ||
6706 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6707 | ||
6708 | for (i = I387_MM0_REGNUM (tdep); | |
6709 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6710 | record_arch_list_add_reg (ir.regcache, i); | |
6711 | ||
6712 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6713 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6714 | record_arch_list_add_reg (ir.regcache, i); |
6715 | ||
6716 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6717 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6718 | ||
6719 | for (i = I387_ST0_REGNUM (tdep); | |
6720 | i386_fp_regnum_p (gdbarch, i); i++) | |
6721 | record_arch_list_add_reg (ir.regcache, i); | |
6722 | ||
6723 | for (i = I387_FCTRL_REGNUM (tdep); | |
6724 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6725 | record_arch_list_add_reg (ir.regcache, i); | |
6726 | } | |
6727 | break; | |
6728 | ||
6729 | case 2: /* ldmxcsr */ | |
6730 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6731 | goto no_support; | |
6732 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6733 | break; | |
6734 | ||
6735 | case 3: /* stmxcsr */ | |
6736 | ir.ot = OT_LONG; | |
6737 | if (i386_record_lea_modrm (&ir)) | |
6738 | return -1; | |
6739 | break; | |
6740 | ||
6741 | case 5: /* lfence */ | |
6742 | case 6: /* mfence */ | |
6743 | case 7: /* sfence clflush */ | |
6744 | break; | |
6745 | ||
6746 | default: | |
6747 | opcode = (opcode << 8) | ir.modrm; | |
6748 | goto no_support; | |
6749 | break; | |
6750 | } | |
6751 | break; | |
6752 | ||
6753 | case 0x0fc3: /* movnti */ | |
6754 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6755 | if (i386_record_modrm (&ir)) | |
6756 | return -1; | |
6757 | if (ir.mod == 3) | |
6758 | goto no_support; | |
6759 | ir.reg |= rex_r; | |
6760 | if (i386_record_lea_modrm (&ir)) | |
6761 | return -1; | |
6762 | break; | |
6763 | ||
6764 | /* Add prefix to opcode. */ | |
6765 | case 0x0f10: | |
6766 | case 0x0f11: | |
6767 | case 0x0f12: | |
6768 | case 0x0f13: | |
6769 | case 0x0f14: | |
6770 | case 0x0f15: | |
6771 | case 0x0f16: | |
6772 | case 0x0f17: | |
6773 | case 0x0f28: | |
6774 | case 0x0f29: | |
6775 | case 0x0f2a: | |
6776 | case 0x0f2b: | |
6777 | case 0x0f2c: | |
6778 | case 0x0f2d: | |
6779 | case 0x0f2e: | |
6780 | case 0x0f2f: | |
6781 | case 0x0f38: | |
6782 | case 0x0f39: | |
6783 | case 0x0f3a: | |
6784 | case 0x0f50: | |
6785 | case 0x0f51: | |
6786 | case 0x0f52: | |
6787 | case 0x0f53: | |
6788 | case 0x0f54: | |
6789 | case 0x0f55: | |
6790 | case 0x0f56: | |
6791 | case 0x0f57: | |
6792 | case 0x0f58: | |
6793 | case 0x0f59: | |
6794 | case 0x0f5a: | |
6795 | case 0x0f5b: | |
6796 | case 0x0f5c: | |
6797 | case 0x0f5d: | |
6798 | case 0x0f5e: | |
6799 | case 0x0f5f: | |
6800 | case 0x0f60: | |
6801 | case 0x0f61: | |
6802 | case 0x0f62: | |
6803 | case 0x0f63: | |
6804 | case 0x0f64: | |
6805 | case 0x0f65: | |
6806 | case 0x0f66: | |
6807 | case 0x0f67: | |
6808 | case 0x0f68: | |
6809 | case 0x0f69: | |
6810 | case 0x0f6a: | |
6811 | case 0x0f6b: | |
6812 | case 0x0f6c: | |
6813 | case 0x0f6d: | |
6814 | case 0x0f6e: | |
6815 | case 0x0f6f: | |
6816 | case 0x0f70: | |
6817 | case 0x0f71: | |
6818 | case 0x0f72: | |
6819 | case 0x0f73: | |
6820 | case 0x0f74: | |
6821 | case 0x0f75: | |
6822 | case 0x0f76: | |
6823 | case 0x0f7c: | |
6824 | case 0x0f7d: | |
6825 | case 0x0f7e: | |
6826 | case 0x0f7f: | |
6827 | case 0x0fb8: | |
6828 | case 0x0fc2: | |
6829 | case 0x0fc4: | |
6830 | case 0x0fc5: | |
6831 | case 0x0fc6: | |
6832 | case 0x0fd0: | |
6833 | case 0x0fd1: | |
6834 | case 0x0fd2: | |
6835 | case 0x0fd3: | |
6836 | case 0x0fd4: | |
6837 | case 0x0fd5: | |
6838 | case 0x0fd6: | |
6839 | case 0x0fd7: | |
6840 | case 0x0fd8: | |
6841 | case 0x0fd9: | |
6842 | case 0x0fda: | |
6843 | case 0x0fdb: | |
6844 | case 0x0fdc: | |
6845 | case 0x0fdd: | |
6846 | case 0x0fde: | |
6847 | case 0x0fdf: | |
6848 | case 0x0fe0: | |
6849 | case 0x0fe1: | |
6850 | case 0x0fe2: | |
6851 | case 0x0fe3: | |
6852 | case 0x0fe4: | |
6853 | case 0x0fe5: | |
6854 | case 0x0fe6: | |
6855 | case 0x0fe7: | |
6856 | case 0x0fe8: | |
6857 | case 0x0fe9: | |
6858 | case 0x0fea: | |
6859 | case 0x0feb: | |
6860 | case 0x0fec: | |
6861 | case 0x0fed: | |
6862 | case 0x0fee: | |
6863 | case 0x0fef: | |
6864 | case 0x0ff0: | |
6865 | case 0x0ff1: | |
6866 | case 0x0ff2: | |
6867 | case 0x0ff3: | |
6868 | case 0x0ff4: | |
6869 | case 0x0ff5: | |
6870 | case 0x0ff6: | |
6871 | case 0x0ff7: | |
6872 | case 0x0ff8: | |
6873 | case 0x0ff9: | |
6874 | case 0x0ffa: | |
6875 | case 0x0ffb: | |
6876 | case 0x0ffc: | |
6877 | case 0x0ffd: | |
6878 | case 0x0ffe: | |
6879 | switch (prefixes) | |
6880 | { | |
6881 | case PREFIX_REPNZ: | |
6882 | opcode |= 0xf20000; | |
6883 | break; | |
6884 | case PREFIX_DATA: | |
6885 | opcode |= 0x660000; | |
6886 | break; | |
6887 | case PREFIX_REPZ: | |
6888 | opcode |= 0xf30000; | |
6889 | break; | |
6890 | } | |
6891 | reswitch_prefix_add: | |
6892 | switch (opcode) | |
6893 | { | |
6894 | case 0x0f38: | |
6895 | case 0x660f38: | |
6896 | case 0xf20f38: | |
6897 | case 0x0f3a: | |
6898 | case 0x660f3a: | |
6899 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6900 | { | |
6901 | printf_unfiltered (_("Process record: error reading memory at " | |
6902 | "addr %s len = 1.\n"), | |
6903 | paddress (gdbarch, ir.addr)); | |
6904 | return -1; | |
6905 | } | |
6906 | ir.addr++; | |
6907 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6908 | goto reswitch_prefix_add; | |
6909 | break; | |
6910 | ||
6911 | case 0x0f10: /* movups */ | |
6912 | case 0x660f10: /* movupd */ | |
6913 | case 0xf30f10: /* movss */ | |
6914 | case 0xf20f10: /* movsd */ | |
6915 | case 0x0f12: /* movlps */ | |
6916 | case 0x660f12: /* movlpd */ | |
6917 | case 0xf30f12: /* movsldup */ | |
6918 | case 0xf20f12: /* movddup */ | |
6919 | case 0x0f14: /* unpcklps */ | |
6920 | case 0x660f14: /* unpcklpd */ | |
6921 | case 0x0f15: /* unpckhps */ | |
6922 | case 0x660f15: /* unpckhpd */ | |
6923 | case 0x0f16: /* movhps */ | |
6924 | case 0x660f16: /* movhpd */ | |
6925 | case 0xf30f16: /* movshdup */ | |
6926 | case 0x0f28: /* movaps */ | |
6927 | case 0x660f28: /* movapd */ | |
6928 | case 0x0f2a: /* cvtpi2ps */ | |
6929 | case 0x660f2a: /* cvtpi2pd */ | |
6930 | case 0xf30f2a: /* cvtsi2ss */ | |
6931 | case 0xf20f2a: /* cvtsi2sd */ | |
6932 | case 0x0f2c: /* cvttps2pi */ | |
6933 | case 0x660f2c: /* cvttpd2pi */ | |
6934 | case 0x0f2d: /* cvtps2pi */ | |
6935 | case 0x660f2d: /* cvtpd2pi */ | |
6936 | case 0x660f3800: /* pshufb */ | |
6937 | case 0x660f3801: /* phaddw */ | |
6938 | case 0x660f3802: /* phaddd */ | |
6939 | case 0x660f3803: /* phaddsw */ | |
6940 | case 0x660f3804: /* pmaddubsw */ | |
6941 | case 0x660f3805: /* phsubw */ | |
6942 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6943 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6944 | case 0x660f3808: /* psignb */ |
6945 | case 0x660f3809: /* psignw */ | |
6946 | case 0x660f380a: /* psignd */ | |
6947 | case 0x660f380b: /* pmulhrsw */ | |
6948 | case 0x660f3810: /* pblendvb */ | |
6949 | case 0x660f3814: /* blendvps */ | |
6950 | case 0x660f3815: /* blendvpd */ | |
6951 | case 0x660f381c: /* pabsb */ | |
6952 | case 0x660f381d: /* pabsw */ | |
6953 | case 0x660f381e: /* pabsd */ | |
6954 | case 0x660f3820: /* pmovsxbw */ | |
6955 | case 0x660f3821: /* pmovsxbd */ | |
6956 | case 0x660f3822: /* pmovsxbq */ | |
6957 | case 0x660f3823: /* pmovsxwd */ | |
6958 | case 0x660f3824: /* pmovsxwq */ | |
6959 | case 0x660f3825: /* pmovsxdq */ | |
6960 | case 0x660f3828: /* pmuldq */ | |
6961 | case 0x660f3829: /* pcmpeqq */ | |
6962 | case 0x660f382a: /* movntdqa */ | |
6963 | case 0x660f3a08: /* roundps */ | |
6964 | case 0x660f3a09: /* roundpd */ | |
6965 | case 0x660f3a0a: /* roundss */ | |
6966 | case 0x660f3a0b: /* roundsd */ | |
6967 | case 0x660f3a0c: /* blendps */ | |
6968 | case 0x660f3a0d: /* blendpd */ | |
6969 | case 0x660f3a0e: /* pblendw */ | |
6970 | case 0x660f3a0f: /* palignr */ | |
6971 | case 0x660f3a20: /* pinsrb */ | |
6972 | case 0x660f3a21: /* insertps */ | |
6973 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6974 | case 0x660f3a40: /* dpps */ | |
6975 | case 0x660f3a41: /* dppd */ | |
6976 | case 0x660f3a42: /* mpsadbw */ | |
6977 | case 0x660f3a60: /* pcmpestrm */ | |
6978 | case 0x660f3a61: /* pcmpestri */ | |
6979 | case 0x660f3a62: /* pcmpistrm */ | |
6980 | case 0x660f3a63: /* pcmpistri */ | |
6981 | case 0x0f51: /* sqrtps */ | |
6982 | case 0x660f51: /* sqrtpd */ | |
6983 | case 0xf20f51: /* sqrtsd */ | |
6984 | case 0xf30f51: /* sqrtss */ | |
6985 | case 0x0f52: /* rsqrtps */ | |
6986 | case 0xf30f52: /* rsqrtss */ | |
6987 | case 0x0f53: /* rcpps */ | |
6988 | case 0xf30f53: /* rcpss */ | |
6989 | case 0x0f54: /* andps */ | |
6990 | case 0x660f54: /* andpd */ | |
6991 | case 0x0f55: /* andnps */ | |
6992 | case 0x660f55: /* andnpd */ | |
6993 | case 0x0f56: /* orps */ | |
6994 | case 0x660f56: /* orpd */ | |
6995 | case 0x0f57: /* xorps */ | |
6996 | case 0x660f57: /* xorpd */ | |
6997 | case 0x0f58: /* addps */ | |
6998 | case 0x660f58: /* addpd */ | |
6999 | case 0xf20f58: /* addsd */ | |
7000 | case 0xf30f58: /* addss */ | |
7001 | case 0x0f59: /* mulps */ | |
7002 | case 0x660f59: /* mulpd */ | |
7003 | case 0xf20f59: /* mulsd */ | |
7004 | case 0xf30f59: /* mulss */ | |
7005 | case 0x0f5a: /* cvtps2pd */ | |
7006 | case 0x660f5a: /* cvtpd2ps */ | |
7007 | case 0xf20f5a: /* cvtsd2ss */ | |
7008 | case 0xf30f5a: /* cvtss2sd */ | |
7009 | case 0x0f5b: /* cvtdq2ps */ | |
7010 | case 0x660f5b: /* cvtps2dq */ | |
7011 | case 0xf30f5b: /* cvttps2dq */ | |
7012 | case 0x0f5c: /* subps */ | |
7013 | case 0x660f5c: /* subpd */ | |
7014 | case 0xf20f5c: /* subsd */ | |
7015 | case 0xf30f5c: /* subss */ | |
7016 | case 0x0f5d: /* minps */ | |
7017 | case 0x660f5d: /* minpd */ | |
7018 | case 0xf20f5d: /* minsd */ | |
7019 | case 0xf30f5d: /* minss */ | |
7020 | case 0x0f5e: /* divps */ | |
7021 | case 0x660f5e: /* divpd */ | |
7022 | case 0xf20f5e: /* divsd */ | |
7023 | case 0xf30f5e: /* divss */ | |
7024 | case 0x0f5f: /* maxps */ | |
7025 | case 0x660f5f: /* maxpd */ | |
7026 | case 0xf20f5f: /* maxsd */ | |
7027 | case 0xf30f5f: /* maxss */ | |
7028 | case 0x660f60: /* punpcklbw */ | |
7029 | case 0x660f61: /* punpcklwd */ | |
7030 | case 0x660f62: /* punpckldq */ | |
7031 | case 0x660f63: /* packsswb */ | |
7032 | case 0x660f64: /* pcmpgtb */ | |
7033 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7034 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7035 | case 0x660f67: /* packuswb */ |
7036 | case 0x660f68: /* punpckhbw */ | |
7037 | case 0x660f69: /* punpckhwd */ | |
7038 | case 0x660f6a: /* punpckhdq */ | |
7039 | case 0x660f6b: /* packssdw */ | |
7040 | case 0x660f6c: /* punpcklqdq */ | |
7041 | case 0x660f6d: /* punpckhqdq */ | |
7042 | case 0x660f6e: /* movd */ | |
7043 | case 0x660f6f: /* movdqa */ | |
7044 | case 0xf30f6f: /* movdqu */ | |
7045 | case 0x660f70: /* pshufd */ | |
7046 | case 0xf20f70: /* pshuflw */ | |
7047 | case 0xf30f70: /* pshufhw */ | |
7048 | case 0x660f74: /* pcmpeqb */ | |
7049 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7050 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7051 | case 0x660f7c: /* haddpd */ |
7052 | case 0xf20f7c: /* haddps */ | |
7053 | case 0x660f7d: /* hsubpd */ | |
7054 | case 0xf20f7d: /* hsubps */ | |
7055 | case 0xf30f7e: /* movq */ | |
7056 | case 0x0fc2: /* cmpps */ | |
7057 | case 0x660fc2: /* cmppd */ | |
7058 | case 0xf20fc2: /* cmpsd */ | |
7059 | case 0xf30fc2: /* cmpss */ | |
7060 | case 0x660fc4: /* pinsrw */ | |
7061 | case 0x0fc6: /* shufps */ | |
7062 | case 0x660fc6: /* shufpd */ | |
7063 | case 0x660fd0: /* addsubpd */ | |
7064 | case 0xf20fd0: /* addsubps */ | |
7065 | case 0x660fd1: /* psrlw */ | |
7066 | case 0x660fd2: /* psrld */ | |
7067 | case 0x660fd3: /* psrlq */ | |
7068 | case 0x660fd4: /* paddq */ | |
7069 | case 0x660fd5: /* pmullw */ | |
7070 | case 0xf30fd6: /* movq2dq */ | |
7071 | case 0x660fd8: /* psubusb */ | |
7072 | case 0x660fd9: /* psubusw */ | |
7073 | case 0x660fda: /* pminub */ | |
7074 | case 0x660fdb: /* pand */ | |
7075 | case 0x660fdc: /* paddusb */ | |
7076 | case 0x660fdd: /* paddusw */ | |
7077 | case 0x660fde: /* pmaxub */ | |
7078 | case 0x660fdf: /* pandn */ | |
7079 | case 0x660fe0: /* pavgb */ | |
7080 | case 0x660fe1: /* psraw */ | |
7081 | case 0x660fe2: /* psrad */ | |
7082 | case 0x660fe3: /* pavgw */ | |
7083 | case 0x660fe4: /* pmulhuw */ | |
7084 | case 0x660fe5: /* pmulhw */ | |
7085 | case 0x660fe6: /* cvttpd2dq */ | |
7086 | case 0xf20fe6: /* cvtpd2dq */ | |
7087 | case 0xf30fe6: /* cvtdq2pd */ | |
7088 | case 0x660fe8: /* psubsb */ | |
7089 | case 0x660fe9: /* psubsw */ | |
7090 | case 0x660fea: /* pminsw */ | |
7091 | case 0x660feb: /* por */ | |
7092 | case 0x660fec: /* paddsb */ | |
7093 | case 0x660fed: /* paddsw */ | |
7094 | case 0x660fee: /* pmaxsw */ | |
7095 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7096 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7097 | case 0x660ff1: /* psllw */ |
7098 | case 0x660ff2: /* pslld */ | |
7099 | case 0x660ff3: /* psllq */ | |
7100 | case 0x660ff4: /* pmuludq */ | |
7101 | case 0x660ff5: /* pmaddwd */ | |
7102 | case 0x660ff6: /* psadbw */ | |
7103 | case 0x660ff8: /* psubb */ | |
7104 | case 0x660ff9: /* psubw */ | |
56d2815c | 7105 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7106 | case 0x660ffb: /* psubq */ |
7107 | case 0x660ffc: /* paddb */ | |
7108 | case 0x660ffd: /* paddw */ | |
56d2815c | 7109 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7110 | if (i386_record_modrm (&ir)) |
7111 | return -1; | |
7112 | ir.reg |= rex_r; | |
c131fcee | 7113 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
7114 | goto no_support; |
7115 | record_arch_list_add_reg (ir.regcache, | |
7116 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
7117 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
7118 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7119 | break; | |
7120 | ||
7121 | case 0x0f11: /* movups */ | |
7122 | case 0x660f11: /* movupd */ | |
7123 | case 0xf30f11: /* movss */ | |
7124 | case 0xf20f11: /* movsd */ | |
7125 | case 0x0f13: /* movlps */ | |
7126 | case 0x660f13: /* movlpd */ | |
7127 | case 0x0f17: /* movhps */ | |
7128 | case 0x660f17: /* movhpd */ | |
7129 | case 0x0f29: /* movaps */ | |
7130 | case 0x660f29: /* movapd */ | |
7131 | case 0x660f3a14: /* pextrb */ | |
7132 | case 0x660f3a15: /* pextrw */ | |
7133 | case 0x660f3a16: /* pextrd pextrq */ | |
7134 | case 0x660f3a17: /* extractps */ | |
7135 | case 0x660f7f: /* movdqa */ | |
7136 | case 0xf30f7f: /* movdqu */ | |
7137 | if (i386_record_modrm (&ir)) | |
7138 | return -1; | |
7139 | if (ir.mod == 3) | |
7140 | { | |
7141 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7142 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7143 | goto no_support; | |
7144 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7145 | if (!i386_xmm_regnum_p (gdbarch, |
7146 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7147 | goto no_support; |
7148 | record_arch_list_add_reg (ir.regcache, | |
7149 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7150 | } | |
7151 | else | |
7152 | { | |
7153 | switch (opcode) | |
7154 | { | |
7155 | case 0x660f3a14: | |
7156 | ir.ot = OT_BYTE; | |
7157 | break; | |
7158 | case 0x660f3a15: | |
7159 | ir.ot = OT_WORD; | |
7160 | break; | |
7161 | case 0x660f3a16: | |
7162 | ir.ot = OT_LONG; | |
7163 | break; | |
7164 | case 0x660f3a17: | |
7165 | ir.ot = OT_QUAD; | |
7166 | break; | |
7167 | default: | |
7168 | ir.ot = OT_DQUAD; | |
7169 | break; | |
7170 | } | |
7171 | if (i386_record_lea_modrm (&ir)) | |
7172 | return -1; | |
7173 | } | |
7174 | break; | |
7175 | ||
7176 | case 0x0f2b: /* movntps */ | |
7177 | case 0x660f2b: /* movntpd */ | |
7178 | case 0x0fe7: /* movntq */ | |
7179 | case 0x660fe7: /* movntdq */ | |
7180 | if (ir.mod == 3) | |
7181 | goto no_support; | |
7182 | if (opcode == 0x0fe7) | |
7183 | ir.ot = OT_QUAD; | |
7184 | else | |
7185 | ir.ot = OT_DQUAD; | |
7186 | if (i386_record_lea_modrm (&ir)) | |
7187 | return -1; | |
7188 | break; | |
7189 | ||
7190 | case 0xf30f2c: /* cvttss2si */ | |
7191 | case 0xf20f2c: /* cvttsd2si */ | |
7192 | case 0xf30f2d: /* cvtss2si */ | |
7193 | case 0xf20f2d: /* cvtsd2si */ | |
7194 | case 0xf20f38f0: /* crc32 */ | |
7195 | case 0xf20f38f1: /* crc32 */ | |
7196 | case 0x0f50: /* movmskps */ | |
7197 | case 0x660f50: /* movmskpd */ | |
7198 | case 0x0fc5: /* pextrw */ | |
7199 | case 0x660fc5: /* pextrw */ | |
7200 | case 0x0fd7: /* pmovmskb */ | |
7201 | case 0x660fd7: /* pmovmskb */ | |
7202 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
7203 | break; | |
7204 | ||
7205 | case 0x0f3800: /* pshufb */ | |
7206 | case 0x0f3801: /* phaddw */ | |
7207 | case 0x0f3802: /* phaddd */ | |
7208 | case 0x0f3803: /* phaddsw */ | |
7209 | case 0x0f3804: /* pmaddubsw */ | |
7210 | case 0x0f3805: /* phsubw */ | |
7211 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7212 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7213 | case 0x0f3808: /* psignb */ |
7214 | case 0x0f3809: /* psignw */ | |
7215 | case 0x0f380a: /* psignd */ | |
7216 | case 0x0f380b: /* pmulhrsw */ | |
7217 | case 0x0f381c: /* pabsb */ | |
7218 | case 0x0f381d: /* pabsw */ | |
7219 | case 0x0f381e: /* pabsd */ | |
7220 | case 0x0f382b: /* packusdw */ | |
7221 | case 0x0f3830: /* pmovzxbw */ | |
7222 | case 0x0f3831: /* pmovzxbd */ | |
7223 | case 0x0f3832: /* pmovzxbq */ | |
7224 | case 0x0f3833: /* pmovzxwd */ | |
7225 | case 0x0f3834: /* pmovzxwq */ | |
7226 | case 0x0f3835: /* pmovzxdq */ | |
7227 | case 0x0f3837: /* pcmpgtq */ | |
7228 | case 0x0f3838: /* pminsb */ | |
7229 | case 0x0f3839: /* pminsd */ | |
7230 | case 0x0f383a: /* pminuw */ | |
7231 | case 0x0f383b: /* pminud */ | |
7232 | case 0x0f383c: /* pmaxsb */ | |
7233 | case 0x0f383d: /* pmaxsd */ | |
7234 | case 0x0f383e: /* pmaxuw */ | |
7235 | case 0x0f383f: /* pmaxud */ | |
7236 | case 0x0f3840: /* pmulld */ | |
7237 | case 0x0f3841: /* phminposuw */ | |
7238 | case 0x0f3a0f: /* palignr */ | |
7239 | case 0x0f60: /* punpcklbw */ | |
7240 | case 0x0f61: /* punpcklwd */ | |
7241 | case 0x0f62: /* punpckldq */ | |
7242 | case 0x0f63: /* packsswb */ | |
7243 | case 0x0f64: /* pcmpgtb */ | |
7244 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7245 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7246 | case 0x0f67: /* packuswb */ |
7247 | case 0x0f68: /* punpckhbw */ | |
7248 | case 0x0f69: /* punpckhwd */ | |
7249 | case 0x0f6a: /* punpckhdq */ | |
7250 | case 0x0f6b: /* packssdw */ | |
7251 | case 0x0f6e: /* movd */ | |
7252 | case 0x0f6f: /* movq */ | |
7253 | case 0x0f70: /* pshufw */ | |
7254 | case 0x0f74: /* pcmpeqb */ | |
7255 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7256 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7257 | case 0x0fc4: /* pinsrw */ |
7258 | case 0x0fd1: /* psrlw */ | |
7259 | case 0x0fd2: /* psrld */ | |
7260 | case 0x0fd3: /* psrlq */ | |
7261 | case 0x0fd4: /* paddq */ | |
7262 | case 0x0fd5: /* pmullw */ | |
7263 | case 0xf20fd6: /* movdq2q */ | |
7264 | case 0x0fd8: /* psubusb */ | |
7265 | case 0x0fd9: /* psubusw */ | |
7266 | case 0x0fda: /* pminub */ | |
7267 | case 0x0fdb: /* pand */ | |
7268 | case 0x0fdc: /* paddusb */ | |
7269 | case 0x0fdd: /* paddusw */ | |
7270 | case 0x0fde: /* pmaxub */ | |
7271 | case 0x0fdf: /* pandn */ | |
7272 | case 0x0fe0: /* pavgb */ | |
7273 | case 0x0fe1: /* psraw */ | |
7274 | case 0x0fe2: /* psrad */ | |
7275 | case 0x0fe3: /* pavgw */ | |
7276 | case 0x0fe4: /* pmulhuw */ | |
7277 | case 0x0fe5: /* pmulhw */ | |
7278 | case 0x0fe8: /* psubsb */ | |
7279 | case 0x0fe9: /* psubsw */ | |
7280 | case 0x0fea: /* pminsw */ | |
7281 | case 0x0feb: /* por */ | |
7282 | case 0x0fec: /* paddsb */ | |
7283 | case 0x0fed: /* paddsw */ | |
7284 | case 0x0fee: /* pmaxsw */ | |
7285 | case 0x0fef: /* pxor */ | |
7286 | case 0x0ff1: /* psllw */ | |
7287 | case 0x0ff2: /* pslld */ | |
7288 | case 0x0ff3: /* psllq */ | |
7289 | case 0x0ff4: /* pmuludq */ | |
7290 | case 0x0ff5: /* pmaddwd */ | |
7291 | case 0x0ff6: /* psadbw */ | |
7292 | case 0x0ff8: /* psubb */ | |
7293 | case 0x0ff9: /* psubw */ | |
56d2815c | 7294 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7295 | case 0x0ffb: /* psubq */ |
7296 | case 0x0ffc: /* paddb */ | |
7297 | case 0x0ffd: /* paddw */ | |
56d2815c | 7298 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7299 | if (i386_record_modrm (&ir)) |
7300 | return -1; | |
7301 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7302 | goto no_support; | |
7303 | record_arch_list_add_reg (ir.regcache, | |
7304 | I387_MM0_REGNUM (tdep) + ir.reg); | |
7305 | break; | |
7306 | ||
7307 | case 0x0f71: /* psllw */ | |
7308 | case 0x0f72: /* pslld */ | |
7309 | case 0x0f73: /* psllq */ | |
7310 | if (i386_record_modrm (&ir)) | |
7311 | return -1; | |
7312 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7313 | goto no_support; | |
7314 | record_arch_list_add_reg (ir.regcache, | |
7315 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7316 | break; | |
7317 | ||
7318 | case 0x660f71: /* psllw */ | |
7319 | case 0x660f72: /* pslld */ | |
7320 | case 0x660f73: /* psllq */ | |
7321 | if (i386_record_modrm (&ir)) | |
7322 | return -1; | |
7323 | ir.rm |= ir.rex_b; | |
c131fcee | 7324 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
7325 | goto no_support; |
7326 | record_arch_list_add_reg (ir.regcache, | |
7327 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7328 | break; | |
7329 | ||
7330 | case 0x0f7e: /* movd */ | |
7331 | case 0x660f7e: /* movd */ | |
7332 | if (i386_record_modrm (&ir)) | |
7333 | return -1; | |
7334 | if (ir.mod == 3) | |
7335 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7336 | else | |
7337 | { | |
7338 | if (ir.dflag == 2) | |
7339 | ir.ot = OT_QUAD; | |
7340 | else | |
7341 | ir.ot = OT_LONG; | |
7342 | if (i386_record_lea_modrm (&ir)) | |
7343 | return -1; | |
7344 | } | |
7345 | break; | |
7346 | ||
7347 | case 0x0f7f: /* movq */ | |
7348 | if (i386_record_modrm (&ir)) | |
7349 | return -1; | |
7350 | if (ir.mod == 3) | |
7351 | { | |
7352 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7353 | goto no_support; | |
7354 | record_arch_list_add_reg (ir.regcache, | |
7355 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7356 | } | |
7357 | else | |
7358 | { | |
7359 | ir.ot = OT_QUAD; | |
7360 | if (i386_record_lea_modrm (&ir)) | |
7361 | return -1; | |
7362 | } | |
7363 | break; | |
7364 | ||
7365 | case 0xf30fb8: /* popcnt */ | |
7366 | if (i386_record_modrm (&ir)) | |
7367 | return -1; | |
7368 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
7369 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7370 | break; | |
7371 | ||
7372 | case 0x660fd6: /* movq */ | |
7373 | if (i386_record_modrm (&ir)) | |
7374 | return -1; | |
7375 | if (ir.mod == 3) | |
7376 | { | |
7377 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7378 | if (!i386_xmm_regnum_p (gdbarch, |
7379 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7380 | goto no_support; |
7381 | record_arch_list_add_reg (ir.regcache, | |
7382 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7383 | } | |
7384 | else | |
7385 | { | |
7386 | ir.ot = OT_QUAD; | |
7387 | if (i386_record_lea_modrm (&ir)) | |
7388 | return -1; | |
7389 | } | |
7390 | break; | |
7391 | ||
7392 | case 0x660f3817: /* ptest */ | |
7393 | case 0x0f2e: /* ucomiss */ | |
7394 | case 0x660f2e: /* ucomisd */ | |
7395 | case 0x0f2f: /* comiss */ | |
7396 | case 0x660f2f: /* comisd */ | |
7397 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7398 | break; | |
7399 | ||
7400 | case 0x0ff7: /* maskmovq */ | |
7401 | regcache_raw_read_unsigned (ir.regcache, | |
7402 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7403 | &addr); | |
7404 | if (record_arch_list_add_mem (addr, 64)) | |
7405 | return -1; | |
7406 | break; | |
7407 | ||
7408 | case 0x660ff7: /* maskmovdqu */ | |
7409 | regcache_raw_read_unsigned (ir.regcache, | |
7410 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7411 | &addr); | |
7412 | if (record_arch_list_add_mem (addr, 128)) | |
7413 | return -1; | |
7414 | break; | |
7415 | ||
7416 | default: | |
7417 | goto no_support; | |
7418 | break; | |
7419 | } | |
7420 | break; | |
7ad10968 HZ |
7421 | |
7422 | default: | |
7ad10968 HZ |
7423 | goto no_support; |
7424 | break; | |
7425 | } | |
7426 | ||
cf648174 HZ |
7427 | /* In the future, maybe still need to deal with need_dasm. */ |
7428 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
7429 | if (record_arch_list_add_end ()) |
7430 | return -1; | |
7431 | ||
7432 | return 0; | |
7433 | ||
01fe1b41 | 7434 | no_support: |
a3c4230a HZ |
7435 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7436 | "at address %s.\n"), | |
7437 | (unsigned int) (opcode), | |
7438 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7439 | return -1; |
7440 | } | |
7441 | ||
cf648174 HZ |
7442 | static const int i386_record_regmap[] = |
7443 | { | |
7444 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7445 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7446 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7447 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7448 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7449 | }; | |
7450 | ||
7a697b8d | 7451 | /* Check that the given address appears suitable for a fast |
405f8e94 | 7452 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
7453 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
7454 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
7455 | middle of the tracepoint jump. On x86, it may be possible to use |
7456 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
7457 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
7458 | of instruction to replace, and 0 if not, plus an explanatory |
7459 | string. */ | |
7460 | ||
7461 | static int | |
7462 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7463 | CORE_ADDR addr, int *isize, char **msg) | |
7464 | { | |
7465 | int len, jumplen; | |
7466 | static struct ui_file *gdb_null = NULL; | |
7467 | ||
405f8e94 SS |
7468 | /* Ask the target for the minimum instruction length supported. */ |
7469 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
7470 | ||
7471 | if (jumplen < 0) | |
7472 | { | |
7473 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
7474 | operation, assume that fast tracepoints will always be implemented | |
7475 | using 4-byte relative jumps on both x86 and x86-64. */ | |
7476 | jumplen = 5; | |
7477 | } | |
7478 | else if (jumplen == 0) | |
7479 | { | |
7480 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
7481 | returns zero, then the IPA has not loaded yet. In this case, | |
7482 | we optimistically assume that truncated 2-byte relative jumps | |
7483 | will be available on x86, and compensate later if this assumption | |
7484 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
7485 | jumps will always be used. */ | |
7486 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
7487 | } | |
7a697b8d SS |
7488 | |
7489 | /* Dummy file descriptor for the disassembler. */ | |
7490 | if (!gdb_null) | |
7491 | gdb_null = ui_file_new (); | |
7492 | ||
7493 | /* Check for fit. */ | |
7494 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
7495 | if (isize) |
7496 | *isize = len; | |
7497 | ||
7a697b8d SS |
7498 | if (len < jumplen) |
7499 | { | |
7500 | /* Return a bit of target-specific detail to add to the caller's | |
7501 | generic failure message. */ | |
7502 | if (msg) | |
1777feb0 MS |
7503 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7504 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7505 | len, jumplen); |
7506 | return 0; | |
7507 | } | |
405f8e94 SS |
7508 | else |
7509 | { | |
7510 | if (msg) | |
7511 | *msg = NULL; | |
7512 | return 1; | |
7513 | } | |
7a697b8d SS |
7514 | } |
7515 | ||
90884b2b L |
7516 | static int |
7517 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7518 | struct tdesc_arch_data *tdesc_data) | |
7519 | { | |
7520 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7521 | const struct tdesc_feature *feature_core; |
7522 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7523 | int i, num_regs, valid_p; |
7524 | ||
7525 | if (! tdesc_has_registers (tdesc)) | |
7526 | return 0; | |
7527 | ||
7528 | /* Get core registers. */ | |
7529 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7530 | if (feature_core == NULL) |
7531 | return 0; | |
90884b2b L |
7532 | |
7533 | /* Get SSE registers. */ | |
c131fcee | 7534 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7535 | |
c131fcee L |
7536 | /* Try AVX registers. */ |
7537 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7538 | ||
90884b2b L |
7539 | valid_p = 1; |
7540 | ||
c131fcee L |
7541 | /* The XCR0 bits. */ |
7542 | if (feature_avx) | |
7543 | { | |
3a13a53b L |
7544 | /* AVX register description requires SSE register description. */ |
7545 | if (!feature_sse) | |
7546 | return 0; | |
7547 | ||
c131fcee L |
7548 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7549 | ||
7550 | /* It may have been set by OSABI initialization function. */ | |
7551 | if (tdep->num_ymm_regs == 0) | |
7552 | { | |
7553 | tdep->ymmh_register_names = i386_ymmh_names; | |
7554 | tdep->num_ymm_regs = 8; | |
7555 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7556 | } | |
7557 | ||
7558 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7559 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7560 | tdep->ymm0h_regnum + i, | |
7561 | tdep->ymmh_register_names[i]); | |
7562 | } | |
3a13a53b | 7563 | else if (feature_sse) |
c131fcee | 7564 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7565 | else |
7566 | { | |
7567 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7568 | tdep->num_xmm_regs = 0; | |
7569 | } | |
c131fcee | 7570 | |
90884b2b L |
7571 | num_regs = tdep->num_core_regs; |
7572 | for (i = 0; i < num_regs; i++) | |
7573 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7574 | tdep->register_names[i]); | |
7575 | ||
3a13a53b L |
7576 | if (feature_sse) |
7577 | { | |
7578 | /* Need to include %mxcsr, so add one. */ | |
7579 | num_regs += tdep->num_xmm_regs + 1; | |
7580 | for (; i < num_regs; i++) | |
7581 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7582 | tdep->register_names[i]); | |
7583 | } | |
90884b2b L |
7584 | |
7585 | return valid_p; | |
7586 | } | |
7587 | ||
7ad10968 HZ |
7588 | \f |
7589 | static struct gdbarch * | |
7590 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7591 | { | |
7592 | struct gdbarch_tdep *tdep; | |
7593 | struct gdbarch *gdbarch; | |
90884b2b L |
7594 | struct tdesc_arch_data *tdesc_data; |
7595 | const struct target_desc *tdesc; | |
1ba53b71 | 7596 | int mm0_regnum; |
c131fcee | 7597 | int ymm0_regnum; |
7ad10968 HZ |
7598 | |
7599 | /* If there is already a candidate, use it. */ | |
7600 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7601 | if (arches != NULL) | |
7602 | return arches->gdbarch; | |
7603 | ||
7604 | /* Allocate space for the new architecture. */ | |
7605 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7606 | gdbarch = gdbarch_alloc (&info, tdep); | |
7607 | ||
7608 | /* General-purpose registers. */ | |
7609 | tdep->gregset = NULL; | |
7610 | tdep->gregset_reg_offset = NULL; | |
7611 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7612 | tdep->sizeof_gregset = 0; | |
7613 | ||
7614 | /* Floating-point registers. */ | |
7615 | tdep->fpregset = NULL; | |
7616 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7617 | ||
c131fcee L |
7618 | tdep->xstateregset = NULL; |
7619 | ||
7ad10968 HZ |
7620 | /* The default settings include the FPU registers, the MMX registers |
7621 | and the SSE registers. This can be overridden for a specific ABI | |
7622 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7623 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7624 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7625 | |
7626 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7627 | ||
7ad10968 HZ |
7628 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7629 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7630 | ||
7631 | tdep->jb_pc_offset = -1; | |
7632 | tdep->struct_return = pcc_struct_return; | |
7633 | tdep->sigtramp_start = 0; | |
7634 | tdep->sigtramp_end = 0; | |
7635 | tdep->sigtramp_p = i386_sigtramp_p; | |
7636 | tdep->sigcontext_addr = NULL; | |
7637 | tdep->sc_reg_offset = NULL; | |
7638 | tdep->sc_pc_offset = -1; | |
7639 | tdep->sc_sp_offset = -1; | |
7640 | ||
c131fcee L |
7641 | tdep->xsave_xcr0_offset = -1; |
7642 | ||
cf648174 HZ |
7643 | tdep->record_regmap = i386_record_regmap; |
7644 | ||
205c306f DM |
7645 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7646 | ||
7ad10968 HZ |
7647 | /* The format used for `long double' on almost all i386 targets is |
7648 | the i387 extended floating-point format. In fact, of all targets | |
7649 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7650 | on having a `long double' that's not `long' at all. */ | |
7651 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7652 | ||
7653 | /* Although the i387 extended floating-point has only 80 significant | |
7654 | bits, a `long double' actually takes up 96, probably to enforce | |
7655 | alignment. */ | |
7656 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7657 | ||
7ad10968 HZ |
7658 | /* Register numbers of various important registers. */ |
7659 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7660 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7661 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7662 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7663 | ||
7664 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7665 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7666 | differ in how they number %ebp, %esp, %eflags, and the | |
7667 | floating-point registers, and are implemented by the arrays | |
7668 | dbx_register_map[] and svr4_dbx_register_map in | |
7669 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7670 | gcc/config/i386.c, which it designates as the "default" register | |
7671 | map used in 64bit mode. This last register numbering scheme is | |
7672 | implemented in dbx64_register_map, and is used for AMD64; see | |
7673 | amd64-tdep.c. | |
7674 | ||
7675 | Currently, each GCC i386 target always uses the same register | |
7676 | numbering scheme across all its supported debugging formats | |
7677 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7678 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7679 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7680 | respective config header in a manner independent of the requested | |
7681 | output debugging format. | |
7682 | ||
7683 | This does not match the arrangement below, which presumes that | |
7684 | the SDB and stabs numbering schemes differ from the DWARF and | |
7685 | DWARF 2 ones. The reason for this arrangement is that it is | |
7686 | likely to get the numbering scheme for the target's | |
7687 | default/native debug format right. For targets where GCC is the | |
7688 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7689 | targets where the native toolchain uses a different numbering | |
7690 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7691 | the defaults below will have to be overridden, like | |
7692 | i386_elf_init_abi() does. */ | |
7693 | ||
7694 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7695 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7696 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7697 | ||
7698 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7699 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7700 | ||
7701 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7702 | be in use on any of the supported i386 targets. */ | |
7703 | ||
7704 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7705 | ||
7706 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7707 | ||
7708 | /* Call dummy code. */ | |
7709 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
e04e5beb | 7710 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7711 | |
7712 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7713 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7714 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7715 | ||
7716 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7717 | ||
7718 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7719 | ||
7720 | /* Stack grows downward. */ | |
7721 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7722 | ||
7723 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7724 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7725 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7726 | ||
7727 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7728 | ||
7ad10968 HZ |
7729 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7730 | ||
7731 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7732 | ||
7733 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7734 | ||
7735 | /* Add the i386 register groups. */ | |
7736 | i386_add_reggroups (gdbarch); | |
90884b2b | 7737 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7738 | |
143985b7 AF |
7739 | /* Helper for function argument information. */ |
7740 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7741 | ||
06da04c6 | 7742 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7743 | appended to the list first, so that it supercedes the DWARF |
7744 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7745 | currently fails). */ |
7746 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7747 | ||
7748 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7749 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7750 | CFI info will be used if it is available. */ |
10458914 | 7751 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7752 | |
acd5c798 | 7753 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7754 | |
1ba53b71 | 7755 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7756 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7757 | i386_pseudo_register_read_value); | |
90884b2b L |
7758 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7759 | ||
7760 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7761 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7762 | ||
c131fcee L |
7763 | /* Override the normal target description method to make the AVX |
7764 | upper halves anonymous. */ | |
7765 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7766 | ||
7767 | /* Even though the default ABI only includes general-purpose registers, | |
7768 | floating-point registers and the SSE registers, we have to leave a | |
7769 | gap for the upper AVX registers. */ | |
7770 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7771 | |
7772 | /* Get the x86 target description from INFO. */ | |
7773 | tdesc = info.target_desc; | |
7774 | if (! tdesc_has_registers (tdesc)) | |
7775 | tdesc = tdesc_i386; | |
7776 | tdep->tdesc = tdesc; | |
7777 | ||
7778 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7779 | tdep->register_names = i386_register_names; | |
7780 | ||
c131fcee L |
7781 | /* No upper YMM registers. */ |
7782 | tdep->ymmh_register_names = NULL; | |
7783 | tdep->ymm0h_regnum = -1; | |
7784 | ||
1ba53b71 L |
7785 | tdep->num_byte_regs = 8; |
7786 | tdep->num_word_regs = 8; | |
7787 | tdep->num_dword_regs = 0; | |
7788 | tdep->num_mmx_regs = 8; | |
c131fcee | 7789 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7790 | |
90884b2b L |
7791 | tdesc_data = tdesc_data_alloc (); |
7792 | ||
dde08ee1 PA |
7793 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7794 | ||
6710bf39 SS |
7795 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7796 | ||
3ce1502b | 7797 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7798 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7799 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7800 | |
c131fcee L |
7801 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7802 | { | |
7803 | tdesc_data_cleanup (tdesc_data); | |
7804 | xfree (tdep); | |
7805 | gdbarch_free (gdbarch); | |
7806 | return NULL; | |
7807 | } | |
7808 | ||
1ba53b71 L |
7809 | /* Wire in pseudo registers. Number of pseudo registers may be |
7810 | changed. */ | |
7811 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7812 | + tdep->num_word_regs | |
7813 | + tdep->num_dword_regs | |
c131fcee L |
7814 | + tdep->num_mmx_regs |
7815 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7816 | |
90884b2b L |
7817 | /* Target description may be changed. */ |
7818 | tdesc = tdep->tdesc; | |
7819 | ||
90884b2b L |
7820 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7821 | ||
7822 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7823 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7824 | ||
1ba53b71 L |
7825 | /* Make %al the first pseudo-register. */ |
7826 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7827 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7828 | ||
c131fcee | 7829 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7830 | if (tdep->num_dword_regs) |
7831 | { | |
1c6272a6 | 7832 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7833 | tdep->eax_regnum = ymm0_regnum; |
7834 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7835 | } |
7836 | else | |
7837 | tdep->eax_regnum = -1; | |
7838 | ||
c131fcee L |
7839 | mm0_regnum = ymm0_regnum; |
7840 | if (tdep->num_ymm_regs) | |
7841 | { | |
1c6272a6 | 7842 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7843 | tdep->ymm0_regnum = ymm0_regnum; |
7844 | mm0_regnum += tdep->num_ymm_regs; | |
7845 | } | |
7846 | else | |
7847 | tdep->ymm0_regnum = -1; | |
7848 | ||
1ba53b71 L |
7849 | if (tdep->num_mmx_regs != 0) |
7850 | { | |
1c6272a6 | 7851 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7852 | tdep->mm0_regnum = mm0_regnum; |
7853 | } | |
7854 | else | |
7855 | tdep->mm0_regnum = -1; | |
7856 | ||
06da04c6 | 7857 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7858 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7859 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7860 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7861 | |
8446b36a MK |
7862 | /* If we have a register mapping, enable the generic core file |
7863 | support, unless it has already been enabled. */ | |
7864 | if (tdep->gregset_reg_offset | |
7865 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7866 | set_gdbarch_regset_from_core_section (gdbarch, | |
7867 | i386_regset_from_core_section); | |
7868 | ||
514f746b AR |
7869 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7870 | i386_skip_permanent_breakpoint); | |
7871 | ||
7a697b8d SS |
7872 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7873 | i386_fast_tracepoint_valid_at); | |
7874 | ||
a62cc96e AC |
7875 | return gdbarch; |
7876 | } | |
7877 | ||
8201327c MK |
7878 | static enum gdb_osabi |
7879 | i386_coff_osabi_sniffer (bfd *abfd) | |
7880 | { | |
762c5349 MK |
7881 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7882 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7883 | return GDB_OSABI_GO32; |
7884 | ||
7885 | return GDB_OSABI_UNKNOWN; | |
7886 | } | |
8201327c MK |
7887 | \f |
7888 | ||
28e9e0f0 MK |
7889 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7890 | void _initialize_i386_tdep (void); | |
7891 | ||
c906108c | 7892 | void |
fba45db2 | 7893 | _initialize_i386_tdep (void) |
c906108c | 7894 | { |
a62cc96e AC |
7895 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7896 | ||
fc338970 | 7897 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7898 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7899 | &disassembly_flavor, _("\ | |
7900 | Set the disassembly flavor."), _("\ | |
7901 | Show the disassembly flavor."), _("\ | |
7902 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7903 | NULL, | |
7904 | NULL, /* FIXME: i18n: */ | |
7905 | &setlist, &showlist); | |
8201327c MK |
7906 | |
7907 | /* Add the variable that controls the convention for returning | |
7908 | structs. */ | |
7ab04401 AC |
7909 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7910 | &struct_convention, _("\ | |
7911 | Set the convention for returning small structs."), _("\ | |
7912 | Show the convention for returning small structs."), _("\ | |
7913 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7914 | is \"default\"."), | |
7915 | NULL, | |
7916 | NULL, /* FIXME: i18n: */ | |
7917 | &setlist, &showlist); | |
8201327c MK |
7918 | |
7919 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7920 | i386_coff_osabi_sniffer); | |
8201327c | 7921 | |
05816f70 | 7922 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7923 | i386_svr4_init_abi); |
05816f70 | 7924 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7925 | i386_go32_init_abi); |
38c968cf | 7926 | |
209bd28e | 7927 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7928 | i386_init_reggroups (); |
90884b2b L |
7929 | |
7930 | /* Initialize the standard target descriptions. */ | |
7931 | initialize_tdesc_i386 (); | |
3a13a53b | 7932 | initialize_tdesc_i386_mmx (); |
c131fcee | 7933 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7934 | |
7935 | /* Tell remote stub that we support XML target description. */ | |
7936 | register_remote_support_xml ("i386"); | |
c906108c | 7937 | } |