Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
0e9f083f | 48 | #include <string.h> |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 | 54 | #include "record.h" |
d02ed0bb | 55 | #include "record-full.h" |
7ad10968 HZ |
56 | #include <stdint.h> |
57 | ||
90884b2b | 58 | #include "features/i386/i386.c" |
c131fcee | 59 | #include "features/i386/i386-avx.c" |
1dbcd68c | 60 | #include "features/i386/i386-mpx.c" |
01f9f808 | 61 | #include "features/i386/i386-avx512.c" |
3a13a53b | 62 | #include "features/i386/i386-mmx.c" |
90884b2b | 63 | |
6710bf39 SS |
64 | #include "ax.h" |
65 | #include "ax-gdb.h" | |
66 | ||
55aa24fb SDJ |
67 | #include "stap-probe.h" |
68 | #include "user-regs.h" | |
69 | #include "cli/cli-utils.h" | |
70 | #include "expression.h" | |
71 | #include "parser-defs.h" | |
72 | #include <ctype.h> | |
73 | ||
c4fc7f1b | 74 | /* Register names. */ |
c40e1eab | 75 | |
90884b2b | 76 | static const char *i386_register_names[] = |
fc633446 MK |
77 | { |
78 | "eax", "ecx", "edx", "ebx", | |
79 | "esp", "ebp", "esi", "edi", | |
80 | "eip", "eflags", "cs", "ss", | |
81 | "ds", "es", "fs", "gs", | |
82 | "st0", "st1", "st2", "st3", | |
83 | "st4", "st5", "st6", "st7", | |
84 | "fctrl", "fstat", "ftag", "fiseg", | |
85 | "fioff", "foseg", "fooff", "fop", | |
86 | "xmm0", "xmm1", "xmm2", "xmm3", | |
87 | "xmm4", "xmm5", "xmm6", "xmm7", | |
88 | "mxcsr" | |
89 | }; | |
90 | ||
01f9f808 MS |
91 | static const char *i386_zmm_names[] = |
92 | { | |
93 | "zmm0", "zmm1", "zmm2", "zmm3", | |
94 | "zmm4", "zmm5", "zmm6", "zmm7" | |
95 | }; | |
96 | ||
97 | static const char *i386_zmmh_names[] = | |
98 | { | |
99 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
100 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
101 | }; | |
102 | ||
103 | static const char *i386_k_names[] = | |
104 | { | |
105 | "k0", "k1", "k2", "k3", | |
106 | "k4", "k5", "k6", "k7" | |
107 | }; | |
108 | ||
c131fcee L |
109 | static const char *i386_ymm_names[] = |
110 | { | |
111 | "ymm0", "ymm1", "ymm2", "ymm3", | |
112 | "ymm4", "ymm5", "ymm6", "ymm7", | |
113 | }; | |
114 | ||
115 | static const char *i386_ymmh_names[] = | |
116 | { | |
117 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
118 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
119 | }; | |
120 | ||
1dbcd68c WT |
121 | static const char *i386_mpx_names[] = |
122 | { | |
123 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
124 | }; | |
125 | ||
126 | /* Register names for MPX pseudo-registers. */ | |
127 | ||
128 | static const char *i386_bnd_names[] = | |
129 | { | |
130 | "bnd0", "bnd1", "bnd2", "bnd3" | |
131 | }; | |
132 | ||
c4fc7f1b | 133 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 134 | |
90884b2b | 135 | static const char *i386_mmx_names[] = |
28fc6740 AC |
136 | { |
137 | "mm0", "mm1", "mm2", "mm3", | |
138 | "mm4", "mm5", "mm6", "mm7" | |
139 | }; | |
c40e1eab | 140 | |
1ba53b71 L |
141 | /* Register names for byte pseudo-registers. */ |
142 | ||
143 | static const char *i386_byte_names[] = | |
144 | { | |
145 | "al", "cl", "dl", "bl", | |
146 | "ah", "ch", "dh", "bh" | |
147 | }; | |
148 | ||
149 | /* Register names for word pseudo-registers. */ | |
150 | ||
151 | static const char *i386_word_names[] = | |
152 | { | |
153 | "ax", "cx", "dx", "bx", | |
9cad29ac | 154 | "", "bp", "si", "di" |
1ba53b71 L |
155 | }; |
156 | ||
01f9f808 MS |
157 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
158 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
159 | we have 16 upper ZMM regs that have to be handled differently. */ | |
160 | ||
161 | const int num_lower_zmm_regs = 16; | |
162 | ||
1ba53b71 | 163 | /* MMX register? */ |
c40e1eab | 164 | |
28fc6740 | 165 | static int |
5716833c | 166 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 167 | { |
1ba53b71 L |
168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
169 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
170 | |
171 | if (mm0_regnum < 0) | |
172 | return 0; | |
173 | ||
1ba53b71 L |
174 | regnum -= mm0_regnum; |
175 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
176 | } | |
177 | ||
178 | /* Byte register? */ | |
179 | ||
180 | int | |
181 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
182 | { | |
183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
184 | ||
185 | regnum -= tdep->al_regnum; | |
186 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
187 | } | |
188 | ||
189 | /* Word register? */ | |
190 | ||
191 | int | |
192 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
193 | { | |
194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
195 | ||
196 | regnum -= tdep->ax_regnum; | |
197 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
198 | } | |
199 | ||
200 | /* Dword register? */ | |
201 | ||
202 | int | |
203 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
204 | { | |
205 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
206 | int eax_regnum = tdep->eax_regnum; | |
207 | ||
208 | if (eax_regnum < 0) | |
209 | return 0; | |
210 | ||
211 | regnum -= eax_regnum; | |
212 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
213 | } |
214 | ||
01f9f808 MS |
215 | /* AVX512 register? */ |
216 | ||
217 | int | |
218 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
219 | { | |
220 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
221 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
222 | ||
223 | if (zmm0h_regnum < 0) | |
224 | return 0; | |
225 | ||
226 | regnum -= zmm0h_regnum; | |
227 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
228 | } | |
229 | ||
230 | int | |
231 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
232 | { | |
233 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
234 | int zmm0_regnum = tdep->zmm0_regnum; | |
235 | ||
236 | if (zmm0_regnum < 0) | |
237 | return 0; | |
238 | ||
239 | regnum -= zmm0_regnum; | |
240 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
241 | } | |
242 | ||
243 | int | |
244 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
245 | { | |
246 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
247 | int k0_regnum = tdep->k0_regnum; | |
248 | ||
249 | if (k0_regnum < 0) | |
250 | return 0; | |
251 | ||
252 | regnum -= k0_regnum; | |
253 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
254 | } | |
255 | ||
9191d390 | 256 | static int |
c131fcee L |
257 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
258 | { | |
259 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
260 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
261 | ||
262 | if (ymm0h_regnum < 0) | |
263 | return 0; | |
264 | ||
265 | regnum -= ymm0h_regnum; | |
266 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
267 | } | |
268 | ||
269 | /* AVX register? */ | |
270 | ||
271 | int | |
272 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
273 | { | |
274 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
275 | int ymm0_regnum = tdep->ymm0_regnum; | |
276 | ||
277 | if (ymm0_regnum < 0) | |
278 | return 0; | |
279 | ||
280 | regnum -= ymm0_regnum; | |
281 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
282 | } | |
283 | ||
01f9f808 MS |
284 | static int |
285 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
286 | { | |
287 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
288 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
289 | ||
290 | if (ymm16h_regnum < 0) | |
291 | return 0; | |
292 | ||
293 | regnum -= ymm16h_regnum; | |
294 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
295 | } | |
296 | ||
297 | int | |
298 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
299 | { | |
300 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
301 | int ymm16_regnum = tdep->ymm16_regnum; | |
302 | ||
303 | if (ymm16_regnum < 0) | |
304 | return 0; | |
305 | ||
306 | regnum -= ymm16_regnum; | |
307 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
308 | } | |
309 | ||
1dbcd68c WT |
310 | /* BND register? */ |
311 | ||
312 | int | |
313 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
314 | { | |
315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
316 | int bnd0_regnum = tdep->bnd0_regnum; | |
317 | ||
318 | if (bnd0_regnum < 0) | |
319 | return 0; | |
320 | ||
321 | regnum -= bnd0_regnum; | |
322 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
323 | } | |
324 | ||
5716833c | 325 | /* SSE register? */ |
23a34459 | 326 | |
c131fcee L |
327 | int |
328 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 329 | { |
5716833c | 330 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 331 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 332 | |
c131fcee | 333 | if (num_xmm_regs == 0) |
5716833c MK |
334 | return 0; |
335 | ||
c131fcee L |
336 | regnum -= I387_XMM0_REGNUM (tdep); |
337 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
338 | } |
339 | ||
01f9f808 MS |
340 | /* XMM_512 register? */ |
341 | ||
342 | int | |
343 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
344 | { | |
345 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
346 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
347 | ||
348 | if (num_xmm_avx512_regs == 0) | |
349 | return 0; | |
350 | ||
351 | regnum -= I387_XMM16_REGNUM (tdep); | |
352 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
353 | } | |
354 | ||
5716833c MK |
355 | static int |
356 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 357 | { |
5716833c MK |
358 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
359 | ||
20a6ec49 | 360 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
361 | return 0; |
362 | ||
20a6ec49 | 363 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
364 | } |
365 | ||
5716833c | 366 | /* FP register? */ |
23a34459 AC |
367 | |
368 | int | |
20a6ec49 | 369 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 370 | { |
20a6ec49 MD |
371 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
372 | ||
373 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
374 | return 0; |
375 | ||
20a6ec49 MD |
376 | return (I387_ST0_REGNUM (tdep) <= regnum |
377 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
378 | } |
379 | ||
380 | int | |
20a6ec49 | 381 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 382 | { |
20a6ec49 MD |
383 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
384 | ||
385 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
386 | return 0; |
387 | ||
20a6ec49 MD |
388 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
389 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
390 | } |
391 | ||
1dbcd68c WT |
392 | /* BNDr (raw) register? */ |
393 | ||
394 | static int | |
395 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
396 | { | |
397 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
398 | ||
399 | if (I387_BND0R_REGNUM (tdep) < 0) | |
400 | return 0; | |
401 | ||
402 | regnum -= tdep->bnd0r_regnum; | |
403 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
404 | } | |
405 | ||
406 | /* BND control register? */ | |
407 | ||
408 | static int | |
409 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
410 | { | |
411 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
412 | ||
413 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
414 | return 0; | |
415 | ||
416 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
417 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
418 | } | |
419 | ||
c131fcee L |
420 | /* Return the name of register REGNUM, or the empty string if it is |
421 | an anonymous register. */ | |
422 | ||
423 | static const char * | |
424 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
425 | { | |
426 | /* Hide the upper YMM registers. */ | |
427 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
428 | return ""; | |
429 | ||
01f9f808 MS |
430 | /* Hide the upper YMM16-31 registers. */ |
431 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
432 | return ""; | |
433 | ||
434 | /* Hide the upper ZMM registers. */ | |
435 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
436 | return ""; | |
437 | ||
c131fcee L |
438 | return tdesc_register_name (gdbarch, regnum); |
439 | } | |
440 | ||
30b0e2d8 | 441 | /* Return the name of register REGNUM. */ |
fc633446 | 442 | |
1ba53b71 | 443 | const char * |
90884b2b | 444 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 445 | { |
1ba53b71 | 446 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
447 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
448 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
449 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
450 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
451 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
452 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
453 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
454 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
455 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
456 | return i386_byte_names[regnum - tdep->al_regnum]; | |
457 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
458 | return i386_word_names[regnum - tdep->ax_regnum]; | |
459 | ||
460 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
461 | } |
462 | ||
c4fc7f1b | 463 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
464 | number used by GDB. */ |
465 | ||
8201327c | 466 | static int |
d3f73121 | 467 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 468 | { |
20a6ec49 MD |
469 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
470 | ||
c4fc7f1b MK |
471 | /* This implements what GCC calls the "default" register map |
472 | (dbx_register_map[]). */ | |
473 | ||
85540d8c MK |
474 | if (reg >= 0 && reg <= 7) |
475 | { | |
9872ad24 JB |
476 | /* General-purpose registers. The debug info calls %ebp |
477 | register 4, and %esp register 5. */ | |
478 | if (reg == 4) | |
479 | return 5; | |
480 | else if (reg == 5) | |
481 | return 4; | |
482 | else return reg; | |
85540d8c MK |
483 | } |
484 | else if (reg >= 12 && reg <= 19) | |
485 | { | |
486 | /* Floating-point registers. */ | |
20a6ec49 | 487 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
488 | } |
489 | else if (reg >= 21 && reg <= 28) | |
490 | { | |
491 | /* SSE registers. */ | |
c131fcee L |
492 | int ymm0_regnum = tdep->ymm0_regnum; |
493 | ||
494 | if (ymm0_regnum >= 0 | |
495 | && i386_xmm_regnum_p (gdbarch, reg)) | |
496 | return reg - 21 + ymm0_regnum; | |
497 | else | |
498 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
499 | } |
500 | else if (reg >= 29 && reg <= 36) | |
501 | { | |
502 | /* MMX registers. */ | |
20a6ec49 | 503 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
504 | } |
505 | ||
506 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 507 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
508 | } |
509 | ||
c4fc7f1b MK |
510 | /* Convert SVR4 register number REG to the appropriate register number |
511 | used by GDB. */ | |
85540d8c | 512 | |
8201327c | 513 | static int |
d3f73121 | 514 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 515 | { |
20a6ec49 MD |
516 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
517 | ||
c4fc7f1b MK |
518 | /* This implements the GCC register map that tries to be compatible |
519 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
520 | ||
521 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
522 | numbers the floating point registers differently. */ |
523 | if (reg >= 0 && reg <= 9) | |
524 | { | |
acd5c798 | 525 | /* General-purpose registers. */ |
85540d8c MK |
526 | return reg; |
527 | } | |
528 | else if (reg >= 11 && reg <= 18) | |
529 | { | |
530 | /* Floating-point registers. */ | |
20a6ec49 | 531 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 532 | } |
c6f4c129 | 533 | else if (reg >= 21 && reg <= 36) |
85540d8c | 534 | { |
c4fc7f1b | 535 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 536 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
537 | } |
538 | ||
c6f4c129 JB |
539 | switch (reg) |
540 | { | |
20a6ec49 MD |
541 | case 37: return I387_FCTRL_REGNUM (tdep); |
542 | case 38: return I387_FSTAT_REGNUM (tdep); | |
543 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
544 | case 40: return I386_ES_REGNUM; |
545 | case 41: return I386_CS_REGNUM; | |
546 | case 42: return I386_SS_REGNUM; | |
547 | case 43: return I386_DS_REGNUM; | |
548 | case 44: return I386_FS_REGNUM; | |
549 | case 45: return I386_GS_REGNUM; | |
550 | } | |
551 | ||
85540d8c | 552 | /* This will hopefully provoke a warning. */ |
d3f73121 | 553 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 554 | } |
5716833c | 555 | |
fc338970 | 556 | \f |
917317f4 | 557 | |
fc338970 MK |
558 | /* This is the variable that is set with "set disassembly-flavor", and |
559 | its legitimate values. */ | |
53904c9e AC |
560 | static const char att_flavor[] = "att"; |
561 | static const char intel_flavor[] = "intel"; | |
40478521 | 562 | static const char *const valid_flavors[] = |
c5aa993b | 563 | { |
c906108c SS |
564 | att_flavor, |
565 | intel_flavor, | |
566 | NULL | |
567 | }; | |
53904c9e | 568 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 569 | \f |
c906108c | 570 | |
acd5c798 MK |
571 | /* Use the program counter to determine the contents and size of a |
572 | breakpoint instruction. Return a pointer to a string of bytes that | |
573 | encode a breakpoint instruction, store the length of the string in | |
574 | *LEN and optionally adjust *PC to point to the correct memory | |
575 | location for inserting the breakpoint. | |
c906108c | 576 | |
acd5c798 MK |
577 | On the i386 we have a single breakpoint that fits in a single byte |
578 | and can be inserted anywhere. | |
c906108c | 579 | |
acd5c798 | 580 | This function is 64-bit safe. */ |
63c0089f MK |
581 | |
582 | static const gdb_byte * | |
67d57894 | 583 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 584 | { |
63c0089f MK |
585 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
586 | ||
acd5c798 MK |
587 | *len = sizeof (break_insn); |
588 | return break_insn; | |
c906108c | 589 | } |
237fc4c9 PA |
590 | \f |
591 | /* Displaced instruction handling. */ | |
592 | ||
1903f0e6 DE |
593 | /* Skip the legacy instruction prefixes in INSN. |
594 | Not all prefixes are valid for any particular insn | |
595 | but we needn't care, the insn will fault if it's invalid. | |
596 | The result is a pointer to the first opcode byte, | |
597 | or NULL if we run off the end of the buffer. */ | |
598 | ||
599 | static gdb_byte * | |
600 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
601 | { | |
602 | gdb_byte *end = insn + max_len; | |
603 | ||
604 | while (insn < end) | |
605 | { | |
606 | switch (*insn) | |
607 | { | |
608 | case DATA_PREFIX_OPCODE: | |
609 | case ADDR_PREFIX_OPCODE: | |
610 | case CS_PREFIX_OPCODE: | |
611 | case DS_PREFIX_OPCODE: | |
612 | case ES_PREFIX_OPCODE: | |
613 | case FS_PREFIX_OPCODE: | |
614 | case GS_PREFIX_OPCODE: | |
615 | case SS_PREFIX_OPCODE: | |
616 | case LOCK_PREFIX_OPCODE: | |
617 | case REPE_PREFIX_OPCODE: | |
618 | case REPNE_PREFIX_OPCODE: | |
619 | ++insn; | |
620 | continue; | |
621 | default: | |
622 | return insn; | |
623 | } | |
624 | } | |
625 | ||
626 | return NULL; | |
627 | } | |
237fc4c9 PA |
628 | |
629 | static int | |
1903f0e6 | 630 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 631 | { |
1777feb0 | 632 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
633 | if (insn[0] == 0xea) |
634 | return 1; | |
635 | ||
636 | if (insn[0] == 0xff) | |
637 | { | |
1777feb0 | 638 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
639 | if ((insn[1] & 0x38) == 0x20) |
640 | return 1; | |
641 | ||
1777feb0 | 642 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
643 | if ((insn[1] & 0x38) == 0x28) |
644 | return 1; | |
645 | } | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
c2170eef MM |
650 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
651 | ||
652 | static int | |
653 | i386_jmp_p (const gdb_byte *insn) | |
654 | { | |
655 | /* jump short, relative. */ | |
656 | if (insn[0] == 0xeb) | |
657 | return 1; | |
658 | ||
659 | /* jump near, relative. */ | |
660 | if (insn[0] == 0xe9) | |
661 | return 1; | |
662 | ||
663 | return i386_absolute_jmp_p (insn); | |
664 | } | |
665 | ||
237fc4c9 | 666 | static int |
1903f0e6 | 667 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 668 | { |
1777feb0 | 669 | /* call far, absolute. */ |
237fc4c9 PA |
670 | if (insn[0] == 0x9a) |
671 | return 1; | |
672 | ||
673 | if (insn[0] == 0xff) | |
674 | { | |
1777feb0 | 675 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
676 | if ((insn[1] & 0x38) == 0x10) |
677 | return 1; | |
678 | ||
1777feb0 | 679 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
680 | if ((insn[1] & 0x38) == 0x18) |
681 | return 1; | |
682 | } | |
683 | ||
684 | return 0; | |
685 | } | |
686 | ||
687 | static int | |
1903f0e6 | 688 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
689 | { |
690 | switch (insn[0]) | |
691 | { | |
1777feb0 | 692 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 693 | case 0xc3: /* ret near */ |
1777feb0 | 694 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
695 | case 0xcb: /* ret far */ |
696 | case 0xcf: /* iret */ | |
697 | return 1; | |
698 | ||
699 | default: | |
700 | return 0; | |
701 | } | |
702 | } | |
703 | ||
704 | static int | |
1903f0e6 | 705 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
706 | { |
707 | if (i386_absolute_call_p (insn)) | |
708 | return 1; | |
709 | ||
1777feb0 | 710 | /* call near, relative. */ |
237fc4c9 PA |
711 | if (insn[0] == 0xe8) |
712 | return 1; | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
237fc4c9 PA |
717 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
718 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 719 | |
237fc4c9 | 720 | static int |
b55078be | 721 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 722 | { |
9a7f938f JK |
723 | /* Is it 'int $0x80'? */ |
724 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
725 | /* Or is it 'sysenter'? */ | |
726 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
727 | /* Or is it 'syscall'? */ | |
728 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
729 | { |
730 | *lengthp = 2; | |
731 | return 1; | |
732 | } | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
c2170eef MM |
737 | /* The gdbarch insn_is_call method. */ |
738 | ||
739 | static int | |
740 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
741 | { | |
742 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
743 | ||
744 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
745 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
746 | ||
747 | return i386_call_p (insn); | |
748 | } | |
749 | ||
750 | /* The gdbarch insn_is_ret method. */ | |
751 | ||
752 | static int | |
753 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
754 | { | |
755 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
756 | ||
757 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
758 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
759 | ||
760 | return i386_ret_p (insn); | |
761 | } | |
762 | ||
763 | /* The gdbarch insn_is_jump method. */ | |
764 | ||
765 | static int | |
766 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
767 | { | |
768 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
769 | ||
770 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
771 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
772 | ||
773 | return i386_jmp_p (insn); | |
774 | } | |
775 | ||
b55078be DE |
776 | /* Some kernels may run one past a syscall insn, so we have to cope. |
777 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
778 | ||
779 | struct displaced_step_closure * | |
780 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
781 | CORE_ADDR from, CORE_ADDR to, | |
782 | struct regcache *regs) | |
783 | { | |
784 | size_t len = gdbarch_max_insn_length (gdbarch); | |
785 | gdb_byte *buf = xmalloc (len); | |
786 | ||
787 | read_memory (from, buf, len); | |
788 | ||
789 | /* GDB may get control back after the insn after the syscall. | |
790 | Presumably this is a kernel bug. | |
791 | If this is a syscall, make sure there's a nop afterwards. */ | |
792 | { | |
793 | int syscall_length; | |
794 | gdb_byte *insn; | |
795 | ||
796 | insn = i386_skip_prefixes (buf, len); | |
797 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
798 | insn[syscall_length] = NOP_OPCODE; | |
799 | } | |
800 | ||
801 | write_memory (to, buf, len); | |
802 | ||
803 | if (debug_displaced) | |
804 | { | |
805 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
806 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
807 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
808 | } | |
809 | ||
810 | return (struct displaced_step_closure *) buf; | |
811 | } | |
812 | ||
237fc4c9 PA |
813 | /* Fix up the state of registers and memory after having single-stepped |
814 | a displaced instruction. */ | |
1903f0e6 | 815 | |
237fc4c9 PA |
816 | void |
817 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
818 | struct displaced_step_closure *closure, | |
819 | CORE_ADDR from, CORE_ADDR to, | |
820 | struct regcache *regs) | |
821 | { | |
e17a4113 UW |
822 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
823 | ||
237fc4c9 PA |
824 | /* The offset we applied to the instruction's address. |
825 | This could well be negative (when viewed as a signed 32-bit | |
826 | value), but ULONGEST won't reflect that, so take care when | |
827 | applying it. */ | |
828 | ULONGEST insn_offset = to - from; | |
829 | ||
830 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
831 | copy of the instruction. */ | |
832 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
833 | /* The start of the insn, needed in case we see some prefixes. */ |
834 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
835 | |
836 | if (debug_displaced) | |
837 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 838 | "displaced: fixup (%s, %s), " |
237fc4c9 | 839 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
840 | paddress (gdbarch, from), paddress (gdbarch, to), |
841 | insn[0], insn[1]); | |
237fc4c9 PA |
842 | |
843 | /* The list of issues to contend with here is taken from | |
844 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
845 | Yay for Free Software! */ | |
846 | ||
847 | /* Relocate the %eip, if necessary. */ | |
848 | ||
1903f0e6 DE |
849 | /* The instruction recognizers we use assume any leading prefixes |
850 | have been skipped. */ | |
851 | { | |
852 | /* This is the size of the buffer in closure. */ | |
853 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
854 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
855 | /* If there are too many prefixes, just ignore the insn. | |
856 | It will fault when run. */ | |
857 | if (opcode != NULL) | |
858 | insn = opcode; | |
859 | } | |
860 | ||
237fc4c9 PA |
861 | /* Except in the case of absolute or indirect jump or call |
862 | instructions, or a return instruction, the new eip is relative to | |
863 | the displaced instruction; make it relative. Well, signal | |
864 | handler returns don't need relocation either, but we use the | |
865 | value of %eip to recognize those; see below. */ | |
866 | if (! i386_absolute_jmp_p (insn) | |
867 | && ! i386_absolute_call_p (insn) | |
868 | && ! i386_ret_p (insn)) | |
869 | { | |
870 | ULONGEST orig_eip; | |
b55078be | 871 | int insn_len; |
237fc4c9 PA |
872 | |
873 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
874 | ||
875 | /* A signal trampoline system call changes the %eip, resuming | |
876 | execution of the main program after the signal handler has | |
877 | returned. That makes them like 'return' instructions; we | |
878 | shouldn't relocate %eip. | |
879 | ||
880 | But most system calls don't, and we do need to relocate %eip. | |
881 | ||
882 | Our heuristic for distinguishing these cases: if stepping | |
883 | over the system call instruction left control directly after | |
884 | the instruction, the we relocate --- control almost certainly | |
885 | doesn't belong in the displaced copy. Otherwise, we assume | |
886 | the instruction has put control where it belongs, and leave | |
887 | it unrelocated. Goodness help us if there are PC-relative | |
888 | system calls. */ | |
889 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
890 | && orig_eip != to + (insn - insn_start) + insn_len |
891 | /* GDB can get control back after the insn after the syscall. | |
892 | Presumably this is a kernel bug. | |
893 | i386_displaced_step_copy_insn ensures its a nop, | |
894 | we add one to the length for it. */ | |
895 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
896 | { |
897 | if (debug_displaced) | |
898 | fprintf_unfiltered (gdb_stdlog, | |
899 | "displaced: syscall changed %%eip; " | |
900 | "not relocating\n"); | |
901 | } | |
902 | else | |
903 | { | |
904 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
905 | ||
1903f0e6 DE |
906 | /* If we just stepped over a breakpoint insn, we don't backup |
907 | the pc on purpose; this is to match behaviour without | |
908 | stepping. */ | |
237fc4c9 PA |
909 | |
910 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
911 | ||
912 | if (debug_displaced) | |
913 | fprintf_unfiltered (gdb_stdlog, | |
914 | "displaced: " | |
5af949e3 UW |
915 | "relocated %%eip from %s to %s\n", |
916 | paddress (gdbarch, orig_eip), | |
917 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
918 | } |
919 | } | |
920 | ||
921 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
922 | pushed value, and should be cleared. We'll leave this for later, | |
923 | since GDB already messes up the TF flag when stepping over a | |
924 | pushfl. */ | |
925 | ||
926 | /* If the instruction was a call, the return address now atop the | |
927 | stack is the address following the copied instruction. We need | |
928 | to make it the address following the original instruction. */ | |
929 | if (i386_call_p (insn)) | |
930 | { | |
931 | ULONGEST esp; | |
932 | ULONGEST retaddr; | |
933 | const ULONGEST retaddr_len = 4; | |
934 | ||
935 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 936 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 937 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 938 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
939 | |
940 | if (debug_displaced) | |
941 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
942 | "displaced: relocated return addr at %s to %s\n", |
943 | paddress (gdbarch, esp), | |
944 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
945 | } |
946 | } | |
dde08ee1 PA |
947 | |
948 | static void | |
949 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
950 | { | |
951 | target_write_memory (*to, buf, len); | |
952 | *to += len; | |
953 | } | |
954 | ||
955 | static void | |
956 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
957 | CORE_ADDR *to, CORE_ADDR oldloc) | |
958 | { | |
959 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
960 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
961 | int offset = 0, rel32, newrel; | |
962 | int insn_length; | |
963 | gdb_byte *insn = buf; | |
964 | ||
965 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
966 | ||
967 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
968 | I386_MAX_INSN_LEN, oldloc); | |
969 | ||
970 | /* Get past the prefixes. */ | |
971 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
972 | ||
973 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
974 | the address pushed being the location where the original call in | |
975 | the user program would return to. */ | |
976 | if (insn[0] == 0xe8) | |
977 | { | |
978 | gdb_byte push_buf[16]; | |
979 | unsigned int ret_addr; | |
980 | ||
981 | /* Where "ret" in the original code will return to. */ | |
982 | ret_addr = oldloc + insn_length; | |
1777feb0 | 983 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 984 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
985 | /* Push the push. */ |
986 | append_insns (to, 5, push_buf); | |
987 | ||
988 | /* Convert the relative call to a relative jump. */ | |
989 | insn[0] = 0xe9; | |
990 | ||
991 | /* Adjust the destination offset. */ | |
992 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
993 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
994 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
995 | ||
996 | if (debug_displaced) | |
997 | fprintf_unfiltered (gdb_stdlog, | |
998 | "Adjusted insn rel32=%s at %s to" | |
999 | " rel32=%s at %s\n", | |
1000 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1001 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1002 | |
1003 | /* Write the adjusted jump into its displaced location. */ | |
1004 | append_insns (to, 5, insn); | |
1005 | return; | |
1006 | } | |
1007 | ||
1008 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1009 | handled above. */ | |
1010 | if (insn[0] == 0xe9) | |
1011 | offset = 1; | |
1012 | /* Adjust conditional jumps. */ | |
1013 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1014 | offset = 2; | |
1015 | ||
1016 | if (offset) | |
1017 | { | |
1018 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1019 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1020 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1021 | if (debug_displaced) |
1022 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1023 | "Adjusted insn rel32=%s at %s to" |
1024 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1025 | hex_string (rel32), paddress (gdbarch, oldloc), |
1026 | hex_string (newrel), paddress (gdbarch, *to)); | |
1027 | } | |
1028 | ||
1029 | /* Write the adjusted instructions into their displaced | |
1030 | location. */ | |
1031 | append_insns (to, insn_length, buf); | |
1032 | } | |
1033 | ||
fc338970 | 1034 | \f |
acd5c798 MK |
1035 | #ifdef I386_REGNO_TO_SYMMETRY |
1036 | #error "The Sequent Symmetry is no longer supported." | |
1037 | #endif | |
c906108c | 1038 | |
acd5c798 MK |
1039 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1040 | and %esp "belong" to the calling function. Therefore these | |
1041 | registers should be saved if they're going to be modified. */ | |
c906108c | 1042 | |
acd5c798 MK |
1043 | /* The maximum number of saved registers. This should include all |
1044 | registers mentioned above, and %eip. */ | |
a3386186 | 1045 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1046 | |
1047 | struct i386_frame_cache | |
c906108c | 1048 | { |
acd5c798 MK |
1049 | /* Base address. */ |
1050 | CORE_ADDR base; | |
8fbca658 | 1051 | int base_p; |
772562f8 | 1052 | LONGEST sp_offset; |
acd5c798 MK |
1053 | CORE_ADDR pc; |
1054 | ||
fd13a04a AC |
1055 | /* Saved registers. */ |
1056 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1057 | CORE_ADDR saved_sp; |
e0c62198 | 1058 | int saved_sp_reg; |
acd5c798 MK |
1059 | int pc_in_eax; |
1060 | ||
1061 | /* Stack space reserved for local variables. */ | |
1062 | long locals; | |
1063 | }; | |
1064 | ||
1065 | /* Allocate and initialize a frame cache. */ | |
1066 | ||
1067 | static struct i386_frame_cache * | |
fd13a04a | 1068 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1069 | { |
1070 | struct i386_frame_cache *cache; | |
1071 | int i; | |
1072 | ||
1073 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1074 | ||
1075 | /* Base address. */ | |
8fbca658 | 1076 | cache->base_p = 0; |
acd5c798 MK |
1077 | cache->base = 0; |
1078 | cache->sp_offset = -4; | |
1079 | cache->pc = 0; | |
1080 | ||
fd13a04a AC |
1081 | /* Saved registers. We initialize these to -1 since zero is a valid |
1082 | offset (that's where %ebp is supposed to be stored). */ | |
1083 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1084 | cache->saved_regs[i] = -1; | |
acd5c798 | 1085 | cache->saved_sp = 0; |
e0c62198 | 1086 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1087 | cache->pc_in_eax = 0; |
1088 | ||
1089 | /* Frameless until proven otherwise. */ | |
1090 | cache->locals = -1; | |
1091 | ||
1092 | return cache; | |
1093 | } | |
c906108c | 1094 | |
acd5c798 MK |
1095 | /* If the instruction at PC is a jump, return the address of its |
1096 | target. Otherwise, return PC. */ | |
c906108c | 1097 | |
acd5c798 | 1098 | static CORE_ADDR |
e17a4113 | 1099 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1100 | { |
e17a4113 | 1101 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1102 | gdb_byte op; |
acd5c798 MK |
1103 | long delta = 0; |
1104 | int data16 = 0; | |
c906108c | 1105 | |
0865b04a | 1106 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1107 | return pc; |
1108 | ||
acd5c798 | 1109 | if (op == 0x66) |
c906108c | 1110 | { |
c906108c | 1111 | data16 = 1; |
0865b04a YQ |
1112 | |
1113 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1114 | } |
1115 | ||
acd5c798 | 1116 | switch (op) |
c906108c SS |
1117 | { |
1118 | case 0xe9: | |
fc338970 | 1119 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1120 | if (data16) |
1121 | { | |
e17a4113 | 1122 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1123 | |
fc338970 MK |
1124 | /* Include the size of the jmp instruction (including the |
1125 | 0x66 prefix). */ | |
acd5c798 | 1126 | delta += 4; |
c906108c SS |
1127 | } |
1128 | else | |
1129 | { | |
e17a4113 | 1130 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1131 | |
acd5c798 MK |
1132 | /* Include the size of the jmp instruction. */ |
1133 | delta += 5; | |
c906108c SS |
1134 | } |
1135 | break; | |
1136 | case 0xeb: | |
fc338970 | 1137 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1138 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1139 | |
acd5c798 | 1140 | delta += data16 + 2; |
c906108c SS |
1141 | break; |
1142 | } | |
c906108c | 1143 | |
acd5c798 MK |
1144 | return pc + delta; |
1145 | } | |
fc338970 | 1146 | |
acd5c798 MK |
1147 | /* Check whether PC points at a prologue for a function returning a |
1148 | structure or union. If so, it updates CACHE and returns the | |
1149 | address of the first instruction after the code sequence that | |
1150 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1151 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1152 | |
acd5c798 MK |
1153 | static CORE_ADDR |
1154 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1155 | struct i386_frame_cache *cache) | |
c906108c | 1156 | { |
acd5c798 MK |
1157 | /* Functions that return a structure or union start with: |
1158 | ||
1159 | popl %eax 0x58 | |
1160 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1161 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1162 | ||
1163 | (the System V compiler puts out the second `xchg' instruction, | |
1164 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1165 | gets generated). This sequence is used to get the address of the | |
1166 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1167 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1168 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1169 | gdb_byte buf[4]; | |
1170 | gdb_byte op; | |
c906108c | 1171 | |
acd5c798 MK |
1172 | if (current_pc <= pc) |
1173 | return pc; | |
1174 | ||
0865b04a | 1175 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1176 | return pc; |
c906108c | 1177 | |
acd5c798 MK |
1178 | if (op != 0x58) /* popl %eax */ |
1179 | return pc; | |
c906108c | 1180 | |
0865b04a | 1181 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1182 | return pc; |
1183 | ||
acd5c798 MK |
1184 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1185 | return pc; | |
c906108c | 1186 | |
acd5c798 | 1187 | if (current_pc == pc) |
c906108c | 1188 | { |
acd5c798 MK |
1189 | cache->sp_offset += 4; |
1190 | return current_pc; | |
c906108c SS |
1191 | } |
1192 | ||
acd5c798 | 1193 | if (current_pc == pc + 1) |
c906108c | 1194 | { |
acd5c798 MK |
1195 | cache->pc_in_eax = 1; |
1196 | return current_pc; | |
1197 | } | |
1198 | ||
1199 | if (buf[1] == proto1[1]) | |
1200 | return pc + 4; | |
1201 | else | |
1202 | return pc + 5; | |
1203 | } | |
1204 | ||
1205 | static CORE_ADDR | |
1206 | i386_skip_probe (CORE_ADDR pc) | |
1207 | { | |
1208 | /* A function may start with | |
fc338970 | 1209 | |
acd5c798 MK |
1210 | pushl constant |
1211 | call _probe | |
1212 | addl $4, %esp | |
fc338970 | 1213 | |
acd5c798 MK |
1214 | followed by |
1215 | ||
1216 | pushl %ebp | |
fc338970 | 1217 | |
acd5c798 | 1218 | etc. */ |
63c0089f MK |
1219 | gdb_byte buf[8]; |
1220 | gdb_byte op; | |
fc338970 | 1221 | |
0865b04a | 1222 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1223 | return pc; |
acd5c798 MK |
1224 | |
1225 | if (op == 0x68 || op == 0x6a) | |
1226 | { | |
1227 | int delta; | |
c906108c | 1228 | |
acd5c798 MK |
1229 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1230 | four-byte operand, depending on the opcode. */ | |
c906108c | 1231 | if (op == 0x68) |
acd5c798 | 1232 | delta = 5; |
c906108c | 1233 | else |
acd5c798 | 1234 | delta = 2; |
c906108c | 1235 | |
acd5c798 MK |
1236 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1237 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1238 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1239 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1240 | pc += delta + sizeof (buf); |
c906108c SS |
1241 | } |
1242 | ||
acd5c798 MK |
1243 | return pc; |
1244 | } | |
1245 | ||
92dd43fa MK |
1246 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1247 | stack pointer. Check whether PC points to such code, and update | |
1248 | CACHE accordingly. Return the first instruction after the code | |
1249 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1250 | recognize the code, return PC. */ | |
1251 | ||
1252 | static CORE_ADDR | |
1253 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1254 | struct i386_frame_cache *cache) | |
1255 | { | |
e0c62198 L |
1256 | /* There are 2 code sequences to re-align stack before the frame |
1257 | gets set up: | |
1258 | ||
1259 | 1. Use a caller-saved saved register: | |
1260 | ||
1261 | leal 4(%esp), %reg | |
1262 | andl $-XXX, %esp | |
1263 | pushl -4(%reg) | |
1264 | ||
1265 | 2. Use a callee-saved saved register: | |
1266 | ||
1267 | pushl %reg | |
1268 | leal 8(%esp), %reg | |
1269 | andl $-XXX, %esp | |
1270 | pushl -4(%reg) | |
1271 | ||
1272 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1273 | ||
1274 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1275 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1276 | */ | |
1277 | ||
1278 | gdb_byte buf[14]; | |
1279 | int reg; | |
1280 | int offset, offset_and; | |
1281 | static int regnums[8] = { | |
1282 | I386_EAX_REGNUM, /* %eax */ | |
1283 | I386_ECX_REGNUM, /* %ecx */ | |
1284 | I386_EDX_REGNUM, /* %edx */ | |
1285 | I386_EBX_REGNUM, /* %ebx */ | |
1286 | I386_ESP_REGNUM, /* %esp */ | |
1287 | I386_EBP_REGNUM, /* %ebp */ | |
1288 | I386_ESI_REGNUM, /* %esi */ | |
1289 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1290 | }; |
92dd43fa | 1291 | |
0865b04a | 1292 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1293 | return pc; |
1294 | ||
1295 | /* Check caller-saved saved register. The first instruction has | |
1296 | to be "leal 4(%esp), %reg". */ | |
1297 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1298 | { | |
1299 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1300 | if ((buf[1] & 0xc7) != 0x44) | |
1301 | return pc; | |
1302 | ||
1303 | /* REG has register number. */ | |
1304 | reg = (buf[1] >> 3) & 7; | |
1305 | offset = 4; | |
1306 | } | |
1307 | else | |
1308 | { | |
1309 | /* Check callee-saved saved register. The first instruction | |
1310 | has to be "pushl %reg". */ | |
1311 | if ((buf[0] & 0xf8) != 0x50) | |
1312 | return pc; | |
1313 | ||
1314 | /* Get register. */ | |
1315 | reg = buf[0] & 0x7; | |
1316 | ||
1317 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1318 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1319 | return pc; | |
1320 | ||
1321 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1322 | if ((buf[2] & 0xc7) != 0x44) | |
1323 | return pc; | |
1324 | ||
1325 | /* REG has register number. Registers in pushl and leal have to | |
1326 | be the same. */ | |
1327 | if (reg != ((buf[2] >> 3) & 7)) | |
1328 | return pc; | |
1329 | ||
1330 | offset = 5; | |
1331 | } | |
1332 | ||
1333 | /* Rigister can't be %esp nor %ebp. */ | |
1334 | if (reg == 4 || reg == 5) | |
1335 | return pc; | |
1336 | ||
1337 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1338 | if (buf[offset + 1] != 0xe4 | |
1339 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1340 | return pc; | |
1341 | ||
1342 | offset_and = offset; | |
1343 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1344 | ||
1345 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1346 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1347 | if (buf[offset] != 0xff | |
1348 | || buf[offset + 2] != 0xfc | |
1349 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1350 | return pc; | |
1351 | ||
1352 | /* R/M has register. Registers in leal and pushl have to be the | |
1353 | same. */ | |
1354 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1355 | return pc; |
1356 | ||
e0c62198 L |
1357 | if (current_pc > pc + offset_and) |
1358 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1359 | |
e0c62198 | 1360 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1361 | } |
1362 | ||
37bdc87e | 1363 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1364 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1365 | |
1366 | /* Instruction description. */ | |
1367 | struct i386_insn | |
1368 | { | |
1369 | size_t len; | |
237fc4c9 PA |
1370 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1371 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1372 | }; |
1373 | ||
a3fcb948 | 1374 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1375 | |
a3fcb948 JG |
1376 | static int |
1377 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1378 | { |
63c0089f | 1379 | gdb_byte op; |
37bdc87e | 1380 | |
0865b04a | 1381 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1382 | return 0; |
37bdc87e | 1383 | |
a3fcb948 | 1384 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1385 | { |
a3fcb948 JG |
1386 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1387 | int insn_matched = 1; | |
1388 | size_t i; | |
37bdc87e | 1389 | |
a3fcb948 JG |
1390 | gdb_assert (pattern.len > 1); |
1391 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1392 | |
0865b04a | 1393 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1394 | return 0; |
613e8135 | 1395 | |
a3fcb948 JG |
1396 | for (i = 1; i < pattern.len; i++) |
1397 | { | |
1398 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1399 | insn_matched = 0; | |
37bdc87e | 1400 | } |
a3fcb948 JG |
1401 | return insn_matched; |
1402 | } | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1406 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1407 | the first instruction description that matches. Otherwise, return | |
1408 | NULL. */ | |
1409 | ||
1410 | static struct i386_insn * | |
1411 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1412 | { | |
1413 | struct i386_insn *pattern; | |
1414 | ||
1415 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1416 | { | |
1417 | if (i386_match_pattern (pc, *pattern)) | |
1418 | return pattern; | |
37bdc87e MK |
1419 | } |
1420 | ||
1421 | return NULL; | |
1422 | } | |
1423 | ||
a3fcb948 JG |
1424 | /* Return whether PC points inside a sequence of instructions that |
1425 | matches INSN_PATTERNS. */ | |
1426 | ||
1427 | static int | |
1428 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1429 | { | |
1430 | CORE_ADDR current_pc; | |
1431 | int ix, i; | |
a3fcb948 JG |
1432 | struct i386_insn *insn; |
1433 | ||
1434 | insn = i386_match_insn (pc, insn_patterns); | |
1435 | if (insn == NULL) | |
1436 | return 0; | |
1437 | ||
8bbdd3f4 | 1438 | current_pc = pc; |
a3fcb948 JG |
1439 | ix = insn - insn_patterns; |
1440 | for (i = ix - 1; i >= 0; i--) | |
1441 | { | |
8bbdd3f4 MK |
1442 | current_pc -= insn_patterns[i].len; |
1443 | ||
a3fcb948 JG |
1444 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1445 | return 0; | |
a3fcb948 JG |
1446 | } |
1447 | ||
1448 | current_pc = pc + insn->len; | |
1449 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1450 | { | |
1451 | if (!i386_match_pattern (current_pc, *insn)) | |
1452 | return 0; | |
1453 | ||
1454 | current_pc += insn->len; | |
1455 | } | |
1456 | ||
1457 | return 1; | |
1458 | } | |
1459 | ||
37bdc87e MK |
1460 | /* Some special instructions that might be migrated by GCC into the |
1461 | part of the prologue that sets up the new stack frame. Because the | |
1462 | stack frame hasn't been setup yet, no registers have been saved | |
1463 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1464 | touched. */ | |
1465 | ||
1466 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1467 | { | |
1777feb0 | 1468 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1469 | |
1470 | ??? Should we handle 16-bit operand-sizes here? */ | |
1471 | ||
1472 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1473 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1474 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1475 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1476 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1477 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1478 | { 5, { 0xb8 }, { 0xfe } }, | |
1479 | /* `movl imm32, %edx' */ | |
1480 | { 5, { 0xba }, { 0xff } }, | |
1481 | ||
1482 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1483 | encoding for `mov m32, %eax'. | |
1484 | ||
1485 | ??? Should we handle SIB adressing here? | |
1486 | ??? Should we handle 16-bit operand-sizes here? */ | |
1487 | ||
1488 | /* `movl m32, %eax' */ | |
1489 | { 5, { 0xa1 }, { 0xff } }, | |
1490 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1491 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1492 | /* `movl m32, %edx' */ | |
1493 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1494 | ||
1495 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1496 | Because of the symmetry, there are actually two ways to encode | |
1497 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1498 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1499 | ||
1500 | /* `subl %eax, %eax' */ | |
1501 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1502 | /* `subl %ecx, %ecx' */ | |
1503 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1504 | /* `subl %edx, %edx' */ | |
1505 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1506 | /* `xorl %eax, %eax' */ | |
1507 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1508 | /* `xorl %ecx, %ecx' */ | |
1509 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1510 | /* `xorl %edx, %edx' */ | |
1511 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1512 | { 0 } | |
1513 | }; | |
1514 | ||
e11481da PM |
1515 | |
1516 | /* Check whether PC points to a no-op instruction. */ | |
1517 | static CORE_ADDR | |
1518 | i386_skip_noop (CORE_ADDR pc) | |
1519 | { | |
1520 | gdb_byte op; | |
1521 | int check = 1; | |
1522 | ||
0865b04a | 1523 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1524 | return pc; |
e11481da PM |
1525 | |
1526 | while (check) | |
1527 | { | |
1528 | check = 0; | |
1529 | /* Ignore `nop' instruction. */ | |
1530 | if (op == 0x90) | |
1531 | { | |
1532 | pc += 1; | |
0865b04a | 1533 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1534 | return pc; |
e11481da PM |
1535 | check = 1; |
1536 | } | |
1537 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1538 | Microsoft system dlls often start with | |
1539 | a `mov %edi,%edi' instruction. | |
1540 | The 5 bytes before the function start are | |
1541 | filled with `nop' instructions. | |
1542 | This pattern can be used for hot-patching: | |
1543 | The `mov %edi, %edi' instruction can be replaced by a | |
1544 | near jump to the location of the 5 `nop' instructions | |
1545 | which can be replaced by a 32-bit jump to anywhere | |
1546 | in the 32-bit address space. */ | |
1547 | ||
1548 | else if (op == 0x8b) | |
1549 | { | |
0865b04a | 1550 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1551 | return pc; |
1552 | ||
e11481da PM |
1553 | if (op == 0xff) |
1554 | { | |
1555 | pc += 2; | |
0865b04a | 1556 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1557 | return pc; |
1558 | ||
e11481da PM |
1559 | check = 1; |
1560 | } | |
1561 | } | |
1562 | } | |
1563 | return pc; | |
1564 | } | |
1565 | ||
acd5c798 MK |
1566 | /* Check whether PC points at a code that sets up a new stack frame. |
1567 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1568 | instruction after the sequence that sets up the frame or LIMIT, |
1569 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1570 | |
1571 | static CORE_ADDR | |
e17a4113 UW |
1572 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1573 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1574 | struct i386_frame_cache *cache) |
1575 | { | |
e17a4113 | 1576 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1577 | struct i386_insn *insn; |
63c0089f | 1578 | gdb_byte op; |
26604a34 | 1579 | int skip = 0; |
acd5c798 | 1580 | |
37bdc87e MK |
1581 | if (limit <= pc) |
1582 | return limit; | |
acd5c798 | 1583 | |
0865b04a | 1584 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1585 | return pc; |
acd5c798 | 1586 | |
c906108c | 1587 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1588 | { |
acd5c798 MK |
1589 | /* Take into account that we've executed the `pushl %ebp' that |
1590 | starts this instruction sequence. */ | |
fd13a04a | 1591 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1592 | cache->sp_offset += 4; |
37bdc87e | 1593 | pc++; |
acd5c798 MK |
1594 | |
1595 | /* If that's all, return now. */ | |
37bdc87e MK |
1596 | if (limit <= pc) |
1597 | return limit; | |
26604a34 | 1598 | |
b4632131 | 1599 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1600 | GCC into the prologue and skip them. At this point in the |
1601 | prologue, code should only touch the scratch registers %eax, | |
1602 | %ecx and %edx, so while the number of posibilities is sheer, | |
1603 | it is limited. | |
5daa5b4e | 1604 | |
26604a34 MK |
1605 | Make sure we only skip these instructions if we later see the |
1606 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1607 | while (pc + skip < limit) |
26604a34 | 1608 | { |
37bdc87e MK |
1609 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1610 | if (insn == NULL) | |
1611 | break; | |
b4632131 | 1612 | |
37bdc87e | 1613 | skip += insn->len; |
26604a34 MK |
1614 | } |
1615 | ||
37bdc87e MK |
1616 | /* If that's all, return now. */ |
1617 | if (limit <= pc + skip) | |
1618 | return limit; | |
1619 | ||
0865b04a | 1620 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1621 | return pc + skip; |
37bdc87e | 1622 | |
30f8135b YQ |
1623 | /* The i386 prologue looks like |
1624 | ||
1625 | push %ebp | |
1626 | mov %esp,%ebp | |
1627 | sub $0x10,%esp | |
1628 | ||
1629 | and a different prologue can be generated for atom. | |
1630 | ||
1631 | push %ebp | |
1632 | lea (%esp),%ebp | |
1633 | lea -0x10(%esp),%esp | |
1634 | ||
1635 | We handle both of them here. */ | |
1636 | ||
acd5c798 | 1637 | switch (op) |
c906108c | 1638 | { |
30f8135b | 1639 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1640 | case 0x8b: |
0865b04a | 1641 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1642 | != 0xec) |
37bdc87e | 1643 | return pc; |
30f8135b | 1644 | pc += (skip + 2); |
c906108c SS |
1645 | break; |
1646 | case 0x89: | |
0865b04a | 1647 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1648 | != 0xe5) |
37bdc87e | 1649 | return pc; |
30f8135b YQ |
1650 | pc += (skip + 2); |
1651 | break; | |
1652 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1653 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1654 | != 0x242c) |
1655 | return pc; | |
1656 | pc += (skip + 3); | |
c906108c SS |
1657 | break; |
1658 | default: | |
37bdc87e | 1659 | return pc; |
c906108c | 1660 | } |
acd5c798 | 1661 | |
26604a34 MK |
1662 | /* OK, we actually have a frame. We just don't know how large |
1663 | it is yet. Set its size to zero. We'll adjust it if | |
1664 | necessary. We also now commit to skipping the special | |
1665 | instructions mentioned before. */ | |
acd5c798 MK |
1666 | cache->locals = 0; |
1667 | ||
1668 | /* If that's all, return now. */ | |
37bdc87e MK |
1669 | if (limit <= pc) |
1670 | return limit; | |
acd5c798 | 1671 | |
fc338970 MK |
1672 | /* Check for stack adjustment |
1673 | ||
acd5c798 | 1674 | subl $XXX, %esp |
30f8135b YQ |
1675 | or |
1676 | lea -XXX(%esp),%esp | |
fc338970 | 1677 | |
fd35795f | 1678 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1679 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1680 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1681 | return pc; |
c906108c SS |
1682 | if (op == 0x83) |
1683 | { | |
fd35795f | 1684 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1685 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1686 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1687 | return pc; |
acd5c798 | 1688 | |
37bdc87e MK |
1689 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1690 | make sense to be negative). */ | |
0865b04a | 1691 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1692 | return pc + 3; |
c906108c SS |
1693 | } |
1694 | else if (op == 0x81) | |
1695 | { | |
fd35795f | 1696 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1697 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1698 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1699 | return pc; |
acd5c798 | 1700 | |
fd35795f | 1701 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1702 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1703 | return pc + 6; |
c906108c | 1704 | } |
30f8135b YQ |
1705 | else if (op == 0x8d) |
1706 | { | |
1707 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1708 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1709 | return pc; |
1710 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1711 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1712 | return pc + 4; |
1713 | } | |
c906108c SS |
1714 | else |
1715 | { | |
30f8135b | 1716 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1717 | return pc; |
c906108c SS |
1718 | } |
1719 | } | |
37bdc87e | 1720 | else if (op == 0xc8) /* enter */ |
c906108c | 1721 | { |
0865b04a | 1722 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1723 | return pc + 4; |
c906108c | 1724 | } |
21d0e8a4 | 1725 | |
acd5c798 | 1726 | return pc; |
21d0e8a4 MK |
1727 | } |
1728 | ||
acd5c798 MK |
1729 | /* Check whether PC points at code that saves registers on the stack. |
1730 | If so, it updates CACHE and returns the address of the first | |
1731 | instruction after the register saves or CURRENT_PC, whichever is | |
1732 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1733 | |
1734 | static CORE_ADDR | |
acd5c798 MK |
1735 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1736 | struct i386_frame_cache *cache) | |
6bff26de | 1737 | { |
99ab4326 | 1738 | CORE_ADDR offset = 0; |
63c0089f | 1739 | gdb_byte op; |
99ab4326 | 1740 | int i; |
c0d1d883 | 1741 | |
99ab4326 MK |
1742 | if (cache->locals > 0) |
1743 | offset -= cache->locals; | |
1744 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1745 | { | |
0865b04a | 1746 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1747 | return pc; |
99ab4326 MK |
1748 | if (op < 0x50 || op > 0x57) |
1749 | break; | |
0d17c81d | 1750 | |
99ab4326 MK |
1751 | offset -= 4; |
1752 | cache->saved_regs[op - 0x50] = offset; | |
1753 | cache->sp_offset += 4; | |
1754 | pc++; | |
6bff26de MK |
1755 | } |
1756 | ||
acd5c798 | 1757 | return pc; |
22797942 AC |
1758 | } |
1759 | ||
acd5c798 MK |
1760 | /* Do a full analysis of the prologue at PC and update CACHE |
1761 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1762 | address where the analysis stopped. | |
ed84f6c1 | 1763 | |
fc338970 MK |
1764 | We handle these cases: |
1765 | ||
1766 | The startup sequence can be at the start of the function, or the | |
1767 | function can start with a branch to startup code at the end. | |
1768 | ||
1769 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1770 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1771 | once used in the System V compiler). | |
1772 | ||
1773 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1774 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1775 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1776 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1777 | |
1778 | Next, the registers used by this function are pushed. With the | |
1779 | System V compiler they will always be in the order: %edi, %esi, | |
1780 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1781 | restore %eax); however, the code below is willing to see the pushes | |
1782 | in any order, and will handle up to 8 of them. | |
1783 | ||
1784 | If the setup sequence is at the end of the function, then the next | |
1785 | instruction will be a branch back to the start. */ | |
c906108c | 1786 | |
acd5c798 | 1787 | static CORE_ADDR |
e17a4113 UW |
1788 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1789 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1790 | struct i386_frame_cache *cache) |
c906108c | 1791 | { |
e11481da | 1792 | pc = i386_skip_noop (pc); |
e17a4113 | 1793 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1794 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1795 | pc = i386_skip_probe (pc); | |
92dd43fa | 1796 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1797 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1798 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1799 | } |
1800 | ||
fc338970 | 1801 | /* Return PC of first real instruction. */ |
c906108c | 1802 | |
3a1e71e3 | 1803 | static CORE_ADDR |
6093d2eb | 1804 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1805 | { |
e17a4113 UW |
1806 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1807 | ||
63c0089f | 1808 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1809 | { |
1810 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1811 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1812 | }; |
acd5c798 MK |
1813 | struct i386_frame_cache cache; |
1814 | CORE_ADDR pc; | |
63c0089f | 1815 | gdb_byte op; |
acd5c798 | 1816 | int i; |
56bf0743 | 1817 | CORE_ADDR func_addr; |
4e879fc2 | 1818 | |
56bf0743 KB |
1819 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1820 | { | |
1821 | CORE_ADDR post_prologue_pc | |
1822 | = skip_prologue_using_sal (gdbarch, func_addr); | |
1823 | struct symtab *s = find_pc_symtab (func_addr); | |
1824 | ||
1825 | /* Clang always emits a line note before the prologue and another | |
1826 | one after. We trust clang to emit usable line notes. */ | |
1827 | if (post_prologue_pc | |
1828 | && (s != NULL | |
1829 | && s->producer != NULL | |
1830 | && strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) | |
1831 | return max (start_pc, post_prologue_pc); | |
1832 | } | |
1833 | ||
e0f33b1f | 1834 | cache.locals = -1; |
e17a4113 | 1835 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1836 | if (cache.locals < 0) |
1837 | return start_pc; | |
c5aa993b | 1838 | |
acd5c798 | 1839 | /* Found valid frame setup. */ |
c906108c | 1840 | |
fc338970 MK |
1841 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1842 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1843 | %ebx: |
1844 | ||
fc338970 MK |
1845 | call 0x0 |
1846 | popl %ebx | |
1847 | movl %ebx,x(%ebp) (optional) | |
1848 | addl y,%ebx | |
1849 | ||
c906108c SS |
1850 | This code is with the rest of the prologue (at the end of the |
1851 | function), so we have to skip it to get to the first real | |
1852 | instruction at the start of the function. */ | |
c5aa993b | 1853 | |
c906108c SS |
1854 | for (i = 0; i < 6; i++) |
1855 | { | |
0865b04a | 1856 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1857 | return pc; |
1858 | ||
c5aa993b | 1859 | if (pic_pat[i] != op) |
c906108c SS |
1860 | break; |
1861 | } | |
1862 | if (i == 6) | |
1863 | { | |
acd5c798 MK |
1864 | int delta = 6; |
1865 | ||
0865b04a | 1866 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1867 | return pc; |
c906108c | 1868 | |
c5aa993b | 1869 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1870 | { |
0865b04a | 1871 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1872 | |
fc338970 | 1873 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1874 | delta += 3; |
fc338970 | 1875 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1876 | delta += 6; |
fc338970 | 1877 | else /* Unexpected instruction. */ |
acd5c798 MK |
1878 | delta = 0; |
1879 | ||
0865b04a | 1880 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1881 | return pc; |
c906108c | 1882 | } |
acd5c798 | 1883 | |
c5aa993b | 1884 | /* addl y,%ebx */ |
acd5c798 | 1885 | if (delta > 0 && op == 0x81 |
0865b04a | 1886 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1887 | == 0xc3) |
c906108c | 1888 | { |
acd5c798 | 1889 | pc += delta + 6; |
c906108c SS |
1890 | } |
1891 | } | |
c5aa993b | 1892 | |
e63bbc88 MK |
1893 | /* If the function starts with a branch (to startup code at the end) |
1894 | the last instruction should bring us back to the first | |
1895 | instruction of the real code. */ | |
e17a4113 UW |
1896 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1897 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1898 | |
1899 | return pc; | |
c906108c SS |
1900 | } |
1901 | ||
4309257c PM |
1902 | /* Check that the code pointed to by PC corresponds to a call to |
1903 | __main, skip it if so. Return PC otherwise. */ | |
1904 | ||
1905 | CORE_ADDR | |
1906 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1907 | { | |
e17a4113 | 1908 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1909 | gdb_byte op; |
1910 | ||
0865b04a | 1911 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1912 | return pc; |
4309257c PM |
1913 | if (op == 0xe8) |
1914 | { | |
1915 | gdb_byte buf[4]; | |
1916 | ||
0865b04a | 1917 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1918 | { |
1919 | /* Make sure address is computed correctly as a 32bit | |
1920 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1921 | struct bound_minimal_symbol s; |
e17a4113 | 1922 | CORE_ADDR call_dest; |
4309257c | 1923 | |
e17a4113 | 1924 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1925 | call_dest = call_dest & 0xffffffffU; |
1926 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1927 | if (s.minsym != NULL |
efd66ac6 TT |
1928 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1929 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1930 | pc += 5; |
1931 | } | |
1932 | } | |
1933 | ||
1934 | return pc; | |
1935 | } | |
1936 | ||
acd5c798 | 1937 | /* This function is 64-bit safe. */ |
93924b6b | 1938 | |
acd5c798 MK |
1939 | static CORE_ADDR |
1940 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1941 | { |
63c0089f | 1942 | gdb_byte buf[8]; |
acd5c798 | 1943 | |
875f8d0e | 1944 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1945 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1946 | } |
acd5c798 | 1947 | \f |
93924b6b | 1948 | |
acd5c798 | 1949 | /* Normal frames. */ |
c5aa993b | 1950 | |
8fbca658 PA |
1951 | static void |
1952 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1953 | struct i386_frame_cache *cache) | |
a7769679 | 1954 | { |
e17a4113 UW |
1955 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1956 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1957 | gdb_byte buf[4]; |
acd5c798 MK |
1958 | int i; |
1959 | ||
8fbca658 | 1960 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1961 | |
1962 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1963 | which holds the base address for the current stack frame. | |
1964 | However, for functions that don't need it, the frame pointer is | |
1965 | optional. For these "frameless" functions the frame pointer is | |
1966 | actually the frame pointer of the calling frame. Signal | |
1967 | trampolines are just a special case of a "frameless" function. | |
1968 | They (usually) share their frame pointer with the frame that was | |
1969 | in progress when the signal occurred. */ | |
1970 | ||
10458914 | 1971 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1972 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1973 | if (cache->base == 0) |
620fa63a PA |
1974 | { |
1975 | cache->base_p = 1; | |
1976 | return; | |
1977 | } | |
acd5c798 MK |
1978 | |
1979 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1980 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1981 | |
acd5c798 | 1982 | if (cache->pc != 0) |
e17a4113 UW |
1983 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1984 | cache); | |
acd5c798 MK |
1985 | |
1986 | if (cache->locals < 0) | |
1987 | { | |
1988 | /* We didn't find a valid frame, which means that CACHE->base | |
1989 | currently holds the frame pointer for our calling frame. If | |
1990 | we're at the start of a function, or somewhere half-way its | |
1991 | prologue, the function's frame probably hasn't been fully | |
1992 | setup yet. Try to reconstruct the base address for the stack | |
1993 | frame by looking at the stack pointer. For truly "frameless" | |
1994 | functions this might work too. */ | |
1995 | ||
e0c62198 | 1996 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1997 | { |
8fbca658 PA |
1998 | /* Saved stack pointer has been saved. */ |
1999 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2000 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2001 | ||
92dd43fa MK |
2002 | /* We're halfway aligning the stack. */ |
2003 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2004 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2005 | ||
2006 | /* This will be added back below. */ | |
2007 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2008 | } | |
7618e12b | 2009 | else if (cache->pc != 0 |
0865b04a | 2010 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2011 | { |
7618e12b DJ |
2012 | /* We're in a known function, but did not find a frame |
2013 | setup. Assume that the function does not use %ebp. | |
2014 | Alternatively, we may have jumped to an invalid | |
2015 | address; in that case there is definitely no new | |
2016 | frame in %ebp. */ | |
10458914 | 2017 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2018 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2019 | + cache->sp_offset; | |
92dd43fa | 2020 | } |
7618e12b DJ |
2021 | else |
2022 | /* We're in an unknown function. We could not find the start | |
2023 | of the function to analyze the prologue; our best option is | |
2024 | to assume a typical frame layout with the caller's %ebp | |
2025 | saved. */ | |
2026 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2027 | } |
2028 | ||
8fbca658 PA |
2029 | if (cache->saved_sp_reg != -1) |
2030 | { | |
2031 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2032 | register may be unavailable). */ | |
2033 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2034 | && deprecated_frame_register_read (this_frame, |
2035 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2036 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2037 | } | |
acd5c798 MK |
2038 | /* Now that we have the base address for the stack frame we can |
2039 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2040 | else if (cache->saved_sp == 0) |
92dd43fa | 2041 | cache->saved_sp = cache->base + 8; |
a7769679 | 2042 | |
acd5c798 MK |
2043 | /* Adjust all the saved registers such that they contain addresses |
2044 | instead of offsets. */ | |
2045 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2046 | if (cache->saved_regs[i] != -1) |
2047 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2048 | |
8fbca658 PA |
2049 | cache->base_p = 1; |
2050 | } | |
2051 | ||
2052 | static struct i386_frame_cache * | |
2053 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2054 | { | |
2055 | volatile struct gdb_exception ex; | |
2056 | struct i386_frame_cache *cache; | |
2057 | ||
2058 | if (*this_cache) | |
2059 | return *this_cache; | |
2060 | ||
2061 | cache = i386_alloc_frame_cache (); | |
2062 | *this_cache = cache; | |
2063 | ||
2064 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
2065 | { | |
2066 | i386_frame_cache_1 (this_frame, cache); | |
2067 | } | |
2068 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2069 | throw_exception (ex); | |
2070 | ||
acd5c798 | 2071 | return cache; |
a7769679 MK |
2072 | } |
2073 | ||
3a1e71e3 | 2074 | static void |
10458914 | 2075 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2076 | struct frame_id *this_id) |
c906108c | 2077 | { |
10458914 | 2078 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2079 | |
5ce0145d PA |
2080 | if (!cache->base_p) |
2081 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2082 | else if (cache->base == 0) | |
2083 | { | |
2084 | /* This marks the outermost frame. */ | |
2085 | } | |
2086 | else | |
2087 | { | |
2088 | /* See the end of i386_push_dummy_call. */ | |
2089 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2090 | } | |
acd5c798 MK |
2091 | } |
2092 | ||
8fbca658 PA |
2093 | static enum unwind_stop_reason |
2094 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2095 | void **this_cache) | |
2096 | { | |
2097 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2098 | ||
2099 | if (!cache->base_p) | |
2100 | return UNWIND_UNAVAILABLE; | |
2101 | ||
2102 | /* This marks the outermost frame. */ | |
2103 | if (cache->base == 0) | |
2104 | return UNWIND_OUTERMOST; | |
2105 | ||
2106 | return UNWIND_NO_REASON; | |
2107 | } | |
2108 | ||
10458914 DJ |
2109 | static struct value * |
2110 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2111 | int regnum) | |
acd5c798 | 2112 | { |
10458914 | 2113 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2114 | |
2115 | gdb_assert (regnum >= 0); | |
2116 | ||
2117 | /* The System V ABI says that: | |
2118 | ||
2119 | "The flags register contains the system flags, such as the | |
2120 | direction flag and the carry flag. The direction flag must be | |
2121 | set to the forward (that is, zero) direction before entry and | |
2122 | upon exit from a function. Other user flags have no specified | |
2123 | role in the standard calling sequence and are not preserved." | |
2124 | ||
2125 | To guarantee the "upon exit" part of that statement we fake a | |
2126 | saved flags register that has its direction flag cleared. | |
2127 | ||
2128 | Note that GCC doesn't seem to rely on the fact that the direction | |
2129 | flag is cleared after a function return; it always explicitly | |
2130 | clears the flag before operations where it matters. | |
2131 | ||
2132 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2133 | right thing to do. The way we fake the flags register here makes | |
2134 | it impossible to change it. */ | |
2135 | ||
2136 | if (regnum == I386_EFLAGS_REGNUM) | |
2137 | { | |
10458914 | 2138 | ULONGEST val; |
c5aa993b | 2139 | |
10458914 DJ |
2140 | val = get_frame_register_unsigned (this_frame, regnum); |
2141 | val &= ~(1 << 10); | |
2142 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2143 | } |
1211c4e4 | 2144 | |
acd5c798 | 2145 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2146 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2147 | |
fcf250e2 UW |
2148 | if (regnum == I386_ESP_REGNUM |
2149 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2150 | { |
2151 | /* If the SP has been saved, but we don't know where, then this | |
2152 | means that SAVED_SP_REG register was found unavailable back | |
2153 | when we built the cache. */ | |
fcf250e2 | 2154 | if (cache->saved_sp == 0) |
8fbca658 PA |
2155 | return frame_unwind_got_register (this_frame, regnum, |
2156 | cache->saved_sp_reg); | |
2157 | else | |
2158 | return frame_unwind_got_constant (this_frame, regnum, | |
2159 | cache->saved_sp); | |
2160 | } | |
acd5c798 | 2161 | |
fd13a04a | 2162 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2163 | return frame_unwind_got_memory (this_frame, regnum, |
2164 | cache->saved_regs[regnum]); | |
fd13a04a | 2165 | |
10458914 | 2166 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2167 | } |
2168 | ||
2169 | static const struct frame_unwind i386_frame_unwind = | |
2170 | { | |
2171 | NORMAL_FRAME, | |
8fbca658 | 2172 | i386_frame_unwind_stop_reason, |
acd5c798 | 2173 | i386_frame_this_id, |
10458914 DJ |
2174 | i386_frame_prev_register, |
2175 | NULL, | |
2176 | default_frame_sniffer | |
acd5c798 | 2177 | }; |
06da04c6 MS |
2178 | |
2179 | /* Normal frames, but in a function epilogue. */ | |
2180 | ||
2181 | /* The epilogue is defined here as the 'ret' instruction, which will | |
2182 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
2183 | the function's stack frame. */ | |
2184 | ||
2185 | static int | |
2186 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2187 | { | |
2188 | gdb_byte insn; | |
e0d00bc7 JK |
2189 | struct symtab *symtab; |
2190 | ||
2191 | symtab = find_pc_symtab (pc); | |
2192 | if (symtab && symtab->epilogue_unwind_valid) | |
2193 | return 0; | |
06da04c6 MS |
2194 | |
2195 | if (target_read_memory (pc, &insn, 1)) | |
2196 | return 0; /* Can't read memory at pc. */ | |
2197 | ||
2198 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2199 | return 0; | |
2200 | ||
2201 | return 1; | |
2202 | } | |
2203 | ||
2204 | static int | |
2205 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2206 | struct frame_info *this_frame, | |
2207 | void **this_prologue_cache) | |
2208 | { | |
2209 | if (frame_relative_level (this_frame) == 0) | |
2210 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
2211 | get_frame_pc (this_frame)); | |
2212 | else | |
2213 | return 0; | |
2214 | } | |
2215 | ||
2216 | static struct i386_frame_cache * | |
2217 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2218 | { | |
8fbca658 | 2219 | volatile struct gdb_exception ex; |
06da04c6 | 2220 | struct i386_frame_cache *cache; |
0d6c2135 | 2221 | CORE_ADDR sp; |
06da04c6 MS |
2222 | |
2223 | if (*this_cache) | |
2224 | return *this_cache; | |
2225 | ||
2226 | cache = i386_alloc_frame_cache (); | |
2227 | *this_cache = cache; | |
2228 | ||
8fbca658 PA |
2229 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
2230 | { | |
0d6c2135 | 2231 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2232 | |
0d6c2135 MK |
2233 | /* At this point the stack looks as if we just entered the |
2234 | function, with the return address at the top of the | |
2235 | stack. */ | |
2236 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2237 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2238 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2239 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2240 | |
8fbca658 PA |
2241 | cache->base_p = 1; |
2242 | } | |
2243 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
2244 | throw_exception (ex); | |
06da04c6 MS |
2245 | |
2246 | return cache; | |
2247 | } | |
2248 | ||
8fbca658 PA |
2249 | static enum unwind_stop_reason |
2250 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2251 | void **this_cache) | |
2252 | { | |
0d6c2135 MK |
2253 | struct i386_frame_cache *cache = |
2254 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2255 | |
2256 | if (!cache->base_p) | |
2257 | return UNWIND_UNAVAILABLE; | |
2258 | ||
2259 | return UNWIND_NO_REASON; | |
2260 | } | |
2261 | ||
06da04c6 MS |
2262 | static void |
2263 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2264 | void **this_cache, | |
2265 | struct frame_id *this_id) | |
2266 | { | |
0d6c2135 MK |
2267 | struct i386_frame_cache *cache = |
2268 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2269 | |
8fbca658 | 2270 | if (!cache->base_p) |
5ce0145d PA |
2271 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2272 | else | |
2273 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2274 | } |
2275 | ||
0d6c2135 MK |
2276 | static struct value * |
2277 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2278 | void **this_cache, int regnum) | |
2279 | { | |
2280 | /* Make sure we've initialized the cache. */ | |
2281 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2282 | ||
2283 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2284 | } | |
2285 | ||
06da04c6 MS |
2286 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2287 | { | |
2288 | NORMAL_FRAME, | |
8fbca658 | 2289 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2290 | i386_epilogue_frame_this_id, |
0d6c2135 | 2291 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2292 | NULL, |
2293 | i386_epilogue_frame_sniffer | |
2294 | }; | |
acd5c798 MK |
2295 | \f |
2296 | ||
a3fcb948 JG |
2297 | /* Stack-based trampolines. */ |
2298 | ||
2299 | /* These trampolines are used on cross x86 targets, when taking the | |
2300 | address of a nested function. When executing these trampolines, | |
2301 | no stack frame is set up, so we are in a similar situation as in | |
2302 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2303 | ||
2304 | /* Static chain passed in register. */ | |
2305 | ||
2306 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2307 | { | |
2308 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2309 | { 5, { 0xb8 }, { 0xfe } }, | |
2310 | ||
2311 | /* `jmp imm32' */ | |
2312 | { 5, { 0xe9 }, { 0xff } }, | |
2313 | ||
2314 | {0} | |
2315 | }; | |
2316 | ||
2317 | /* Static chain passed on stack (when regparm=3). */ | |
2318 | ||
2319 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2320 | { | |
2321 | /* `push imm32' */ | |
2322 | { 5, { 0x68 }, { 0xff } }, | |
2323 | ||
2324 | /* `jmp imm32' */ | |
2325 | { 5, { 0xe9 }, { 0xff } }, | |
2326 | ||
2327 | {0} | |
2328 | }; | |
2329 | ||
2330 | /* Return whether PC points inside a stack trampoline. */ | |
2331 | ||
2332 | static int | |
6df81a63 | 2333 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2334 | { |
2335 | gdb_byte insn; | |
2c02bd72 | 2336 | const char *name; |
a3fcb948 JG |
2337 | |
2338 | /* A stack trampoline is detected if no name is associated | |
2339 | to the current pc and if it points inside a trampoline | |
2340 | sequence. */ | |
2341 | ||
2342 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2343 | if (name) | |
2344 | return 0; | |
2345 | ||
2346 | if (target_read_memory (pc, &insn, 1)) | |
2347 | return 0; | |
2348 | ||
2349 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2350 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2351 | return 0; | |
2352 | ||
2353 | return 1; | |
2354 | } | |
2355 | ||
2356 | static int | |
2357 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2358 | struct frame_info *this_frame, |
2359 | void **this_cache) | |
a3fcb948 JG |
2360 | { |
2361 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2362 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2363 | else |
2364 | return 0; | |
2365 | } | |
2366 | ||
2367 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2368 | { | |
2369 | NORMAL_FRAME, | |
2370 | i386_epilogue_frame_unwind_stop_reason, | |
2371 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2372 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2373 | NULL, |
2374 | i386_stack_tramp_frame_sniffer | |
2375 | }; | |
2376 | \f | |
6710bf39 SS |
2377 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2378 | ||
2379 | static void | |
2380 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2381 | struct agent_expr *ax, struct axs_value *value, | |
2382 | CORE_ADDR scope) | |
2383 | { | |
2384 | /* The following sequence assumes the traditional use of the base | |
2385 | register. */ | |
2386 | ax_reg (ax, I386_EBP_REGNUM); | |
2387 | ax_const_l (ax, 4); | |
2388 | ax_simple (ax, aop_add); | |
2389 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2390 | value->kind = axs_lvalue_memory; | |
2391 | } | |
2392 | \f | |
a3fcb948 | 2393 | |
acd5c798 MK |
2394 | /* Signal trampolines. */ |
2395 | ||
2396 | static struct i386_frame_cache * | |
10458914 | 2397 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2398 | { |
e17a4113 UW |
2399 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2400 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2401 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2402 | volatile struct gdb_exception ex; |
acd5c798 | 2403 | struct i386_frame_cache *cache; |
acd5c798 | 2404 | CORE_ADDR addr; |
63c0089f | 2405 | gdb_byte buf[4]; |
acd5c798 MK |
2406 | |
2407 | if (*this_cache) | |
2408 | return *this_cache; | |
2409 | ||
fd13a04a | 2410 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2411 | |
8fbca658 | 2412 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2413 | { |
8fbca658 PA |
2414 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2415 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2416 | |
8fbca658 PA |
2417 | addr = tdep->sigcontext_addr (this_frame); |
2418 | if (tdep->sc_reg_offset) | |
2419 | { | |
2420 | int i; | |
a3386186 | 2421 | |
8fbca658 PA |
2422 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2423 | ||
2424 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2425 | if (tdep->sc_reg_offset[i] != -1) | |
2426 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2427 | } | |
2428 | else | |
2429 | { | |
2430 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2431 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2432 | } | |
2433 | ||
2434 | cache->base_p = 1; | |
a3386186 | 2435 | } |
8fbca658 PA |
2436 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2437 | throw_exception (ex); | |
acd5c798 MK |
2438 | |
2439 | *this_cache = cache; | |
2440 | return cache; | |
2441 | } | |
2442 | ||
8fbca658 PA |
2443 | static enum unwind_stop_reason |
2444 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2445 | void **this_cache) | |
2446 | { | |
2447 | struct i386_frame_cache *cache = | |
2448 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2449 | ||
2450 | if (!cache->base_p) | |
2451 | return UNWIND_UNAVAILABLE; | |
2452 | ||
2453 | return UNWIND_NO_REASON; | |
2454 | } | |
2455 | ||
acd5c798 | 2456 | static void |
10458914 | 2457 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2458 | struct frame_id *this_id) |
2459 | { | |
2460 | struct i386_frame_cache *cache = | |
10458914 | 2461 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2462 | |
8fbca658 | 2463 | if (!cache->base_p) |
5ce0145d PA |
2464 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2465 | else | |
2466 | { | |
2467 | /* See the end of i386_push_dummy_call. */ | |
2468 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2469 | } | |
acd5c798 MK |
2470 | } |
2471 | ||
10458914 DJ |
2472 | static struct value * |
2473 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2474 | void **this_cache, int regnum) | |
acd5c798 MK |
2475 | { |
2476 | /* Make sure we've initialized the cache. */ | |
10458914 | 2477 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2478 | |
10458914 | 2479 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2480 | } |
c0d1d883 | 2481 | |
10458914 DJ |
2482 | static int |
2483 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2484 | struct frame_info *this_frame, | |
2485 | void **this_prologue_cache) | |
acd5c798 | 2486 | { |
10458914 | 2487 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2488 | |
911bc6ee MK |
2489 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2490 | handler. */ | |
2491 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2492 | return 0; |
1c3545ae | 2493 | |
911bc6ee MK |
2494 | if (tdep->sigtramp_p != NULL) |
2495 | { | |
10458914 DJ |
2496 | if (tdep->sigtramp_p (this_frame)) |
2497 | return 1; | |
911bc6ee MK |
2498 | } |
2499 | ||
2500 | if (tdep->sigtramp_start != 0) | |
2501 | { | |
10458914 | 2502 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2503 | |
2504 | gdb_assert (tdep->sigtramp_end != 0); | |
2505 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2506 | return 1; |
911bc6ee | 2507 | } |
acd5c798 | 2508 | |
10458914 | 2509 | return 0; |
acd5c798 | 2510 | } |
10458914 DJ |
2511 | |
2512 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2513 | { | |
2514 | SIGTRAMP_FRAME, | |
8fbca658 | 2515 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2516 | i386_sigtramp_frame_this_id, |
2517 | i386_sigtramp_frame_prev_register, | |
2518 | NULL, | |
2519 | i386_sigtramp_frame_sniffer | |
2520 | }; | |
acd5c798 MK |
2521 | \f |
2522 | ||
2523 | static CORE_ADDR | |
10458914 | 2524 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2525 | { |
10458914 | 2526 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2527 | |
2528 | return cache->base; | |
2529 | } | |
2530 | ||
2531 | static const struct frame_base i386_frame_base = | |
2532 | { | |
2533 | &i386_frame_unwind, | |
2534 | i386_frame_base_address, | |
2535 | i386_frame_base_address, | |
2536 | i386_frame_base_address | |
2537 | }; | |
2538 | ||
acd5c798 | 2539 | static struct frame_id |
10458914 | 2540 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2541 | { |
acd5c798 MK |
2542 | CORE_ADDR fp; |
2543 | ||
10458914 | 2544 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2545 | |
3e210248 | 2546 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2547 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2548 | } |
e04e5beb JM |
2549 | |
2550 | /* _Decimal128 function return values need 16-byte alignment on the | |
2551 | stack. */ | |
2552 | ||
2553 | static CORE_ADDR | |
2554 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2555 | { | |
2556 | return sp & -(CORE_ADDR)16; | |
2557 | } | |
fc338970 | 2558 | \f |
c906108c | 2559 | |
fc338970 MK |
2560 | /* Figure out where the longjmp will land. Slurp the args out of the |
2561 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2562 | structure from which we extract the address that we will land at. |
28bcfd30 | 2563 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2564 | success. */ |
c906108c | 2565 | |
8201327c | 2566 | static int |
60ade65d | 2567 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2568 | { |
436675d3 | 2569 | gdb_byte buf[4]; |
c906108c | 2570 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2571 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2572 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2573 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2574 | |
8201327c MK |
2575 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2576 | longjmp will land. */ | |
2577 | if (jb_pc_offset == -1) | |
c906108c SS |
2578 | return 0; |
2579 | ||
436675d3 | 2580 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2581 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2582 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2583 | return 0; |
2584 | ||
e17a4113 | 2585 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2586 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2587 | return 0; |
c906108c | 2588 | |
e17a4113 | 2589 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2590 | return 1; |
2591 | } | |
fc338970 | 2592 | \f |
c906108c | 2593 | |
7ccc1c74 JM |
2594 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2595 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2596 | unions containing such types must be 16-byte-aligned; other | |
2597 | arguments are 4-byte-aligned. */ | |
2598 | ||
2599 | static int | |
2600 | i386_16_byte_align_p (struct type *type) | |
2601 | { | |
2602 | type = check_typedef (type); | |
2603 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2604 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2605 | && TYPE_LENGTH (type) == 16) | |
2606 | return 1; | |
2607 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2608 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2609 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2610 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2611 | { | |
2612 | int i; | |
2613 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2614 | { | |
2615 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2616 | return 1; | |
2617 | } | |
2618 | } | |
2619 | return 0; | |
2620 | } | |
2621 | ||
a9b8d892 JK |
2622 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2623 | ||
2624 | static CORE_ADDR | |
2625 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2626 | struct value **args, int nargs, struct type *value_type, | |
2627 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2628 | struct regcache *regcache) | |
2629 | { | |
2630 | /* Use 0xcc breakpoint - 1 byte. */ | |
2631 | *bp_addr = sp - 1; | |
2632 | *real_pc = funaddr; | |
2633 | ||
2634 | /* Keep the stack aligned. */ | |
2635 | return sp - 16; | |
2636 | } | |
2637 | ||
3a1e71e3 | 2638 | static CORE_ADDR |
7d9b040b | 2639 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2640 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2641 | struct value **args, CORE_ADDR sp, int struct_return, | |
2642 | CORE_ADDR struct_addr) | |
22f8ba57 | 2643 | { |
e17a4113 | 2644 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2645 | gdb_byte buf[4]; |
acd5c798 | 2646 | int i; |
7ccc1c74 JM |
2647 | int write_pass; |
2648 | int args_space = 0; | |
acd5c798 | 2649 | |
7ccc1c74 JM |
2650 | /* Determine the total space required for arguments and struct |
2651 | return address in a first pass (allowing for 16-byte-aligned | |
2652 | arguments), then push arguments in a second pass. */ | |
2653 | ||
2654 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2655 | { |
7ccc1c74 | 2656 | int args_space_used = 0; |
7ccc1c74 JM |
2657 | |
2658 | if (struct_return) | |
2659 | { | |
2660 | if (write_pass) | |
2661 | { | |
2662 | /* Push value address. */ | |
e17a4113 | 2663 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2664 | write_memory (sp, buf, 4); |
2665 | args_space_used += 4; | |
2666 | } | |
2667 | else | |
2668 | args_space += 4; | |
2669 | } | |
2670 | ||
2671 | for (i = 0; i < nargs; i++) | |
2672 | { | |
2673 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2674 | |
7ccc1c74 JM |
2675 | if (write_pass) |
2676 | { | |
2677 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2678 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2679 | |
7ccc1c74 JM |
2680 | write_memory (sp + args_space_used, |
2681 | value_contents_all (args[i]), len); | |
2682 | /* The System V ABI says that: | |
acd5c798 | 2683 | |
7ccc1c74 JM |
2684 | "An argument's size is increased, if necessary, to make it a |
2685 | multiple of [32-bit] words. This may require tail padding, | |
2686 | depending on the size of the argument." | |
22f8ba57 | 2687 | |
7ccc1c74 JM |
2688 | This makes sure the stack stays word-aligned. */ |
2689 | args_space_used += align_up (len, 4); | |
2690 | } | |
2691 | else | |
2692 | { | |
2693 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2694 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2695 | args_space += align_up (len, 4); |
2696 | } | |
2697 | } | |
2698 | ||
2699 | if (!write_pass) | |
2700 | { | |
7ccc1c74 | 2701 | sp -= args_space; |
284c5a60 MK |
2702 | |
2703 | /* The original System V ABI only requires word alignment, | |
2704 | but modern incarnations need 16-byte alignment in order | |
2705 | to support SSE. Since wasting a few bytes here isn't | |
2706 | harmful we unconditionally enforce 16-byte alignment. */ | |
2707 | sp &= ~0xf; | |
7ccc1c74 | 2708 | } |
22f8ba57 MK |
2709 | } |
2710 | ||
acd5c798 MK |
2711 | /* Store return address. */ |
2712 | sp -= 4; | |
e17a4113 | 2713 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2714 | write_memory (sp, buf, 4); |
2715 | ||
2716 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2717 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2718 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2719 | ||
2720 | /* ...and fake a frame pointer. */ | |
2721 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2722 | ||
3e210248 AC |
2723 | /* MarkK wrote: This "+ 8" is all over the place: |
2724 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2725 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2726 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2727 | definition of the stack address of a frame. Otherwise frame id |
2728 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2729 | stack address *before* the function call as a frame's CFA. On |
2730 | the i386, when %ebp is used as a frame pointer, the offset | |
2731 | between the contents %ebp and the CFA as defined by GCC. */ | |
2732 | return sp + 8; | |
22f8ba57 MK |
2733 | } |
2734 | ||
1a309862 MK |
2735 | /* These registers are used for returning integers (and on some |
2736 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2737 | size and alignment match an integer type). */ |
acd5c798 MK |
2738 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2739 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2740 | |
c5e656c1 MK |
2741 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2742 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2743 | |
3a1e71e3 | 2744 | static void |
c5e656c1 | 2745 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2746 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2747 | { |
c5e656c1 | 2748 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2749 | int len = TYPE_LENGTH (type); |
63c0089f | 2750 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2751 | |
1e8d0a7b | 2752 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2753 | { |
5716833c | 2754 | if (tdep->st0_regnum < 0) |
1a309862 | 2755 | { |
8a3fe4f8 | 2756 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2757 | memset (valbuf, 0, len); |
ef9dff19 | 2758 | return; |
1a309862 MK |
2759 | } |
2760 | ||
c6ba6f0d MK |
2761 | /* Floating-point return values can be found in %st(0). Convert |
2762 | its contents to the desired type. This is probably not | |
2763 | exactly how it would happen on the target itself, but it is | |
2764 | the best we can do. */ | |
acd5c798 | 2765 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2766 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2767 | } |
2768 | else | |
c5aa993b | 2769 | { |
875f8d0e UW |
2770 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2771 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2772 | |
2773 | if (len <= low_size) | |
00f8375e | 2774 | { |
0818c12a | 2775 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2776 | memcpy (valbuf, buf, len); |
2777 | } | |
d4f3574e SS |
2778 | else if (len <= (low_size + high_size)) |
2779 | { | |
0818c12a | 2780 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2781 | memcpy (valbuf, buf, low_size); |
0818c12a | 2782 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2783 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2784 | } |
2785 | else | |
8e65ff28 | 2786 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2787 | _("Cannot extract return value of %d bytes long."), |
2788 | len); | |
c906108c SS |
2789 | } |
2790 | } | |
2791 | ||
c5e656c1 MK |
2792 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2793 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2794 | |
3a1e71e3 | 2795 | static void |
c5e656c1 | 2796 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2797 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2798 | { |
c5e656c1 | 2799 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2800 | int len = TYPE_LENGTH (type); |
2801 | ||
1e8d0a7b | 2802 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2803 | { |
3d7f4f49 | 2804 | ULONGEST fstat; |
63c0089f | 2805 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2806 | |
5716833c | 2807 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2808 | { |
8a3fe4f8 | 2809 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2810 | return; |
2811 | } | |
2812 | ||
635b0cc1 MK |
2813 | /* Returning floating-point values is a bit tricky. Apart from |
2814 | storing the return value in %st(0), we have to simulate the | |
2815 | state of the FPU at function return point. */ | |
2816 | ||
c6ba6f0d MK |
2817 | /* Convert the value found in VALBUF to the extended |
2818 | floating-point format used by the FPU. This is probably | |
2819 | not exactly how it would happen on the target itself, but | |
2820 | it is the best we can do. */ | |
27067745 | 2821 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2822 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2823 | |
635b0cc1 MK |
2824 | /* Set the top of the floating-point register stack to 7. The |
2825 | actual value doesn't really matter, but 7 is what a normal | |
2826 | function return would end up with if the program started out | |
2827 | with a freshly initialized FPU. */ | |
20a6ec49 | 2828 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2829 | fstat |= (7 << 11); |
20a6ec49 | 2830 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2831 | |
635b0cc1 MK |
2832 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2833 | the floating-point register stack to 7, the appropriate value | |
2834 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2835 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2836 | } |
2837 | else | |
2838 | { | |
875f8d0e UW |
2839 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2840 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2841 | |
2842 | if (len <= low_size) | |
3d7f4f49 | 2843 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2844 | else if (len <= (low_size + high_size)) |
2845 | { | |
3d7f4f49 MK |
2846 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2847 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2848 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2849 | } |
2850 | else | |
8e65ff28 | 2851 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2852 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2853 | } |
2854 | } | |
fc338970 | 2855 | \f |
ef9dff19 | 2856 | |
8201327c MK |
2857 | /* This is the variable that is set with "set struct-convention", and |
2858 | its legitimate values. */ | |
2859 | static const char default_struct_convention[] = "default"; | |
2860 | static const char pcc_struct_convention[] = "pcc"; | |
2861 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2862 | static const char *const valid_conventions[] = |
8201327c MK |
2863 | { |
2864 | default_struct_convention, | |
2865 | pcc_struct_convention, | |
2866 | reg_struct_convention, | |
2867 | NULL | |
2868 | }; | |
2869 | static const char *struct_convention = default_struct_convention; | |
2870 | ||
0e4377e1 JB |
2871 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2872 | a union type, or an array type, should be returned in registers | |
2873 | for architecture GDBARCH. */ | |
c5e656c1 | 2874 | |
8201327c | 2875 | static int |
c5e656c1 | 2876 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2877 | { |
c5e656c1 MK |
2878 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2879 | enum type_code code = TYPE_CODE (type); | |
2880 | int len = TYPE_LENGTH (type); | |
8201327c | 2881 | |
0e4377e1 JB |
2882 | gdb_assert (code == TYPE_CODE_STRUCT |
2883 | || code == TYPE_CODE_UNION | |
2884 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2885 | |
2886 | if (struct_convention == pcc_struct_convention | |
2887 | || (struct_convention == default_struct_convention | |
2888 | && tdep->struct_return == pcc_struct_return)) | |
2889 | return 0; | |
2890 | ||
9edde48e MK |
2891 | /* Structures consisting of a single `float', `double' or 'long |
2892 | double' member are returned in %st(0). */ | |
2893 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2894 | { | |
2895 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2896 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2897 | return (len == 4 || len == 8 || len == 12); | |
2898 | } | |
2899 | ||
c5e656c1 MK |
2900 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2901 | } | |
2902 | ||
2903 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2904 | should be returned. If it is supposed to be returned in registers, | |
2905 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2906 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2907 | from WRITEBUF into REGCACHE. */ | |
2908 | ||
2909 | static enum return_value_convention | |
6a3a010b | 2910 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2911 | struct type *type, struct regcache *regcache, |
2912 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2913 | { |
2914 | enum type_code code = TYPE_CODE (type); | |
2915 | ||
5daa78cc TJB |
2916 | if (((code == TYPE_CODE_STRUCT |
2917 | || code == TYPE_CODE_UNION | |
2918 | || code == TYPE_CODE_ARRAY) | |
2919 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2920 | /* Complex double and long double uses the struct return covention. */ |
2921 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2922 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2923 | /* 128-bit decimal float uses the struct return convention. */ |
2924 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2925 | { |
2926 | /* The System V ABI says that: | |
2927 | ||
2928 | "A function that returns a structure or union also sets %eax | |
2929 | to the value of the original address of the caller's area | |
2930 | before it returns. Thus when the caller receives control | |
2931 | again, the address of the returned object resides in register | |
2932 | %eax and can be used to access the object." | |
2933 | ||
2934 | So the ABI guarantees that we can always find the return | |
2935 | value just after the function has returned. */ | |
2936 | ||
0e4377e1 JB |
2937 | /* Note that the ABI doesn't mention functions returning arrays, |
2938 | which is something possible in certain languages such as Ada. | |
2939 | In this case, the value is returned as if it was wrapped in | |
2940 | a record, so the convention applied to records also applies | |
2941 | to arrays. */ | |
2942 | ||
31db7b6c MK |
2943 | if (readbuf) |
2944 | { | |
2945 | ULONGEST addr; | |
2946 | ||
2947 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2948 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2949 | } | |
2950 | ||
2951 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2952 | } | |
c5e656c1 MK |
2953 | |
2954 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2955 | `float', `double' or 'long double' member. These structures are |
2956 | returned in %st(0). For these structures, we call ourselves | |
2957 | recursively, changing TYPE into the type of the first member of | |
2958 | the structure. Since that should work for all structures that | |
2959 | have only one member, we don't bother to check the member's type | |
2960 | here. */ | |
c5e656c1 MK |
2961 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2962 | { | |
2963 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2964 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2965 | readbuf, writebuf); |
c5e656c1 MK |
2966 | } |
2967 | ||
2968 | if (readbuf) | |
2969 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2970 | if (writebuf) | |
2971 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2972 | |
c5e656c1 | 2973 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2974 | } |
2975 | \f | |
2976 | ||
27067745 UW |
2977 | struct type * |
2978 | i387_ext_type (struct gdbarch *gdbarch) | |
2979 | { | |
2980 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2981 | ||
2982 | if (!tdep->i387_ext_type) | |
90884b2b L |
2983 | { |
2984 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2985 | gdb_assert (tdep->i387_ext_type != NULL); | |
2986 | } | |
27067745 UW |
2987 | |
2988 | return tdep->i387_ext_type; | |
2989 | } | |
2990 | ||
1dbcd68c WT |
2991 | /* Construct type for pseudo BND registers. We can't use |
2992 | tdesc_find_type since a complement of one value has to be used | |
2993 | to describe the upper bound. */ | |
2994 | ||
2995 | static struct type * | |
2996 | i386_bnd_type (struct gdbarch *gdbarch) | |
2997 | { | |
2998 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2999 | ||
3000 | ||
3001 | if (!tdep->i386_bnd_type) | |
3002 | { | |
3003 | struct type *t, *bound_t; | |
3004 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3005 | ||
3006 | /* The type we're building is described bellow: */ | |
3007 | #if 0 | |
3008 | struct __bound128 | |
3009 | { | |
3010 | void *lbound; | |
3011 | void *ubound; /* One complement of raw ubound field. */ | |
3012 | }; | |
3013 | #endif | |
3014 | ||
3015 | t = arch_composite_type (gdbarch, | |
3016 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3017 | ||
3018 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3019 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3020 | ||
3021 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3022 | tdep->i386_bnd_type = t; | |
3023 | } | |
3024 | ||
3025 | return tdep->i386_bnd_type; | |
3026 | } | |
3027 | ||
01f9f808 MS |
3028 | /* Construct vector type for pseudo ZMM registers. We can't use |
3029 | tdesc_find_type since ZMM isn't described in target description. */ | |
3030 | ||
3031 | static struct type * | |
3032 | i386_zmm_type (struct gdbarch *gdbarch) | |
3033 | { | |
3034 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3035 | ||
3036 | if (!tdep->i386_zmm_type) | |
3037 | { | |
3038 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3039 | ||
3040 | /* The type we're building is this: */ | |
3041 | #if 0 | |
3042 | union __gdb_builtin_type_vec512i | |
3043 | { | |
3044 | int128_t uint128[4]; | |
3045 | int64_t v4_int64[8]; | |
3046 | int32_t v8_int32[16]; | |
3047 | int16_t v16_int16[32]; | |
3048 | int8_t v32_int8[64]; | |
3049 | double v4_double[8]; | |
3050 | float v8_float[16]; | |
3051 | }; | |
3052 | #endif | |
3053 | ||
3054 | struct type *t; | |
3055 | ||
3056 | t = arch_composite_type (gdbarch, | |
3057 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3058 | append_composite_type_field (t, "v16_float", | |
3059 | init_vector_type (bt->builtin_float, 16)); | |
3060 | append_composite_type_field (t, "v8_double", | |
3061 | init_vector_type (bt->builtin_double, 8)); | |
3062 | append_composite_type_field (t, "v64_int8", | |
3063 | init_vector_type (bt->builtin_int8, 64)); | |
3064 | append_composite_type_field (t, "v32_int16", | |
3065 | init_vector_type (bt->builtin_int16, 32)); | |
3066 | append_composite_type_field (t, "v16_int32", | |
3067 | init_vector_type (bt->builtin_int32, 16)); | |
3068 | append_composite_type_field (t, "v8_int64", | |
3069 | init_vector_type (bt->builtin_int64, 8)); | |
3070 | append_composite_type_field (t, "v4_int128", | |
3071 | init_vector_type (bt->builtin_int128, 4)); | |
3072 | ||
3073 | TYPE_VECTOR (t) = 1; | |
3074 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3075 | tdep->i386_zmm_type = t; | |
3076 | } | |
3077 | ||
3078 | return tdep->i386_zmm_type; | |
3079 | } | |
3080 | ||
c131fcee L |
3081 | /* Construct vector type for pseudo YMM registers. We can't use |
3082 | tdesc_find_type since YMM isn't described in target description. */ | |
3083 | ||
3084 | static struct type * | |
3085 | i386_ymm_type (struct gdbarch *gdbarch) | |
3086 | { | |
3087 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3088 | ||
3089 | if (!tdep->i386_ymm_type) | |
3090 | { | |
3091 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3092 | ||
3093 | /* The type we're building is this: */ | |
3094 | #if 0 | |
3095 | union __gdb_builtin_type_vec256i | |
3096 | { | |
3097 | int128_t uint128[2]; | |
3098 | int64_t v2_int64[4]; | |
3099 | int32_t v4_int32[8]; | |
3100 | int16_t v8_int16[16]; | |
3101 | int8_t v16_int8[32]; | |
3102 | double v2_double[4]; | |
3103 | float v4_float[8]; | |
3104 | }; | |
3105 | #endif | |
3106 | ||
3107 | struct type *t; | |
3108 | ||
3109 | t = arch_composite_type (gdbarch, | |
3110 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3111 | append_composite_type_field (t, "v8_float", | |
3112 | init_vector_type (bt->builtin_float, 8)); | |
3113 | append_composite_type_field (t, "v4_double", | |
3114 | init_vector_type (bt->builtin_double, 4)); | |
3115 | append_composite_type_field (t, "v32_int8", | |
3116 | init_vector_type (bt->builtin_int8, 32)); | |
3117 | append_composite_type_field (t, "v16_int16", | |
3118 | init_vector_type (bt->builtin_int16, 16)); | |
3119 | append_composite_type_field (t, "v8_int32", | |
3120 | init_vector_type (bt->builtin_int32, 8)); | |
3121 | append_composite_type_field (t, "v4_int64", | |
3122 | init_vector_type (bt->builtin_int64, 4)); | |
3123 | append_composite_type_field (t, "v2_int128", | |
3124 | init_vector_type (bt->builtin_int128, 2)); | |
3125 | ||
3126 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3127 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3128 | tdep->i386_ymm_type = t; |
3129 | } | |
3130 | ||
3131 | return tdep->i386_ymm_type; | |
3132 | } | |
3133 | ||
794ac428 | 3134 | /* Construct vector type for MMX registers. */ |
90884b2b | 3135 | static struct type * |
794ac428 UW |
3136 | i386_mmx_type (struct gdbarch *gdbarch) |
3137 | { | |
3138 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3139 | ||
3140 | if (!tdep->i386_mmx_type) | |
3141 | { | |
df4df182 UW |
3142 | const struct builtin_type *bt = builtin_type (gdbarch); |
3143 | ||
794ac428 UW |
3144 | /* The type we're building is this: */ |
3145 | #if 0 | |
3146 | union __gdb_builtin_type_vec64i | |
3147 | { | |
3148 | int64_t uint64; | |
3149 | int32_t v2_int32[2]; | |
3150 | int16_t v4_int16[4]; | |
3151 | int8_t v8_int8[8]; | |
3152 | }; | |
3153 | #endif | |
3154 | ||
3155 | struct type *t; | |
3156 | ||
e9bb382b UW |
3157 | t = arch_composite_type (gdbarch, |
3158 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3159 | |
3160 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3161 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3162 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3163 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3164 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3165 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3166 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3167 | |
876cecd0 | 3168 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3169 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3170 | tdep->i386_mmx_type = t; | |
3171 | } | |
3172 | ||
3173 | return tdep->i386_mmx_type; | |
3174 | } | |
3175 | ||
d7a0d72c | 3176 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3177 | register REGNUM. */ |
d7a0d72c | 3178 | |
fff4548b | 3179 | struct type * |
90884b2b | 3180 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3181 | { |
1dbcd68c WT |
3182 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3183 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3184 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3185 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3186 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3187 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3188 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3189 | return i386_ymm_type (gdbarch); | |
3190 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3191 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3192 | else |
3193 | { | |
3194 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3195 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3196 | return bt->builtin_int8; | |
3197 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3198 | return bt->builtin_int16; | |
3199 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3200 | return bt->builtin_int32; | |
01f9f808 MS |
3201 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3202 | return bt->builtin_int64; | |
1ba53b71 L |
3203 | } |
3204 | ||
3205 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3206 | } |
3207 | ||
28fc6740 | 3208 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3209 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3210 | |
3211 | static int | |
c86c27af | 3212 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3213 | { |
5716833c MK |
3214 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3215 | int mmxreg, fpreg; | |
28fc6740 AC |
3216 | ULONGEST fstat; |
3217 | int tos; | |
c86c27af | 3218 | |
5716833c | 3219 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3220 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3221 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3222 | fpreg = (mmxreg + tos) % 8; |
3223 | ||
20a6ec49 | 3224 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3225 | } |
3226 | ||
3543a589 TT |
3227 | /* A helper function for us by i386_pseudo_register_read_value and |
3228 | amd64_pseudo_register_read_value. It does all the work but reads | |
3229 | the data into an already-allocated value. */ | |
3230 | ||
3231 | void | |
3232 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3233 | struct regcache *regcache, | |
3234 | int regnum, | |
3235 | struct value *result_value) | |
28fc6740 | 3236 | { |
1ba53b71 | 3237 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 3238 | enum register_status status; |
3543a589 | 3239 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3240 | |
5716833c | 3241 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3242 | { |
c86c27af MK |
3243 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3244 | ||
28fc6740 | 3245 | /* Extract (always little endian). */ |
05d1431c PA |
3246 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3247 | if (status != REG_VALID) | |
3543a589 TT |
3248 | mark_value_bytes_unavailable (result_value, 0, |
3249 | TYPE_LENGTH (value_type (result_value))); | |
3250 | else | |
3251 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3252 | } |
3253 | else | |
1ba53b71 L |
3254 | { |
3255 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3256 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3257 | { | |
3258 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3259 | |
1dbcd68c WT |
3260 | /* Extract (always little endian). Read lower 128bits. */ |
3261 | status = regcache_raw_read (regcache, | |
3262 | I387_BND0R_REGNUM (tdep) + regnum, | |
3263 | raw_buf); | |
3264 | if (status != REG_VALID) | |
3265 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3266 | else | |
3267 | { | |
3268 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3269 | LONGEST upper, lower; | |
3270 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3271 | ||
3272 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3273 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3274 | upper = ~upper; | |
3275 | ||
3276 | memcpy (buf, &lower, size); | |
3277 | memcpy (buf + size, &upper, size); | |
3278 | } | |
3279 | } | |
01f9f808 MS |
3280 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3281 | { | |
3282 | regnum -= tdep->k0_regnum; | |
3283 | ||
3284 | /* Extract (always little endian). */ | |
3285 | status = regcache_raw_read (regcache, | |
3286 | tdep->k0_regnum + regnum, | |
3287 | raw_buf); | |
3288 | if (status != REG_VALID) | |
3289 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3290 | else | |
3291 | memcpy (buf, raw_buf, 8); | |
3292 | } | |
3293 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3294 | { | |
3295 | regnum -= tdep->zmm0_regnum; | |
3296 | ||
3297 | if (regnum < num_lower_zmm_regs) | |
3298 | { | |
3299 | /* Extract (always little endian). Read lower 128bits. */ | |
3300 | status = regcache_raw_read (regcache, | |
3301 | I387_XMM0_REGNUM (tdep) + regnum, | |
3302 | raw_buf); | |
3303 | if (status != REG_VALID) | |
3304 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3305 | else | |
3306 | memcpy (buf, raw_buf, 16); | |
3307 | ||
3308 | /* Extract (always little endian). Read upper 128bits. */ | |
3309 | status = regcache_raw_read (regcache, | |
3310 | tdep->ymm0h_regnum + regnum, | |
3311 | raw_buf); | |
3312 | if (status != REG_VALID) | |
3313 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3314 | else | |
3315 | memcpy (buf + 16, raw_buf, 16); | |
3316 | } | |
3317 | else | |
3318 | { | |
3319 | /* Extract (always little endian). Read lower 128bits. */ | |
3320 | status = regcache_raw_read (regcache, | |
3321 | I387_XMM16_REGNUM (tdep) + regnum | |
3322 | - num_lower_zmm_regs, | |
3323 | raw_buf); | |
3324 | if (status != REG_VALID) | |
3325 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3326 | else | |
3327 | memcpy (buf, raw_buf, 16); | |
3328 | ||
3329 | /* Extract (always little endian). Read upper 128bits. */ | |
3330 | status = regcache_raw_read (regcache, | |
3331 | I387_YMM16H_REGNUM (tdep) + regnum | |
3332 | - num_lower_zmm_regs, | |
3333 | raw_buf); | |
3334 | if (status != REG_VALID) | |
3335 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3336 | else | |
3337 | memcpy (buf + 16, raw_buf, 16); | |
3338 | } | |
3339 | ||
3340 | /* Read upper 256bits. */ | |
3341 | status = regcache_raw_read (regcache, | |
3342 | tdep->zmm0h_regnum + regnum, | |
3343 | raw_buf); | |
3344 | if (status != REG_VALID) | |
3345 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3346 | else | |
3347 | memcpy (buf + 32, raw_buf, 32); | |
3348 | } | |
1dbcd68c | 3349 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3350 | { |
3351 | regnum -= tdep->ymm0_regnum; | |
3352 | ||
1777feb0 | 3353 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3354 | status = regcache_raw_read (regcache, |
3355 | I387_XMM0_REGNUM (tdep) + regnum, | |
3356 | raw_buf); | |
3357 | if (status != REG_VALID) | |
3543a589 TT |
3358 | mark_value_bytes_unavailable (result_value, 0, 16); |
3359 | else | |
3360 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3361 | /* Read upper 128bits. */ |
05d1431c PA |
3362 | status = regcache_raw_read (regcache, |
3363 | tdep->ymm0h_regnum + regnum, | |
3364 | raw_buf); | |
3365 | if (status != REG_VALID) | |
3543a589 TT |
3366 | mark_value_bytes_unavailable (result_value, 16, 32); |
3367 | else | |
3368 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3369 | } |
01f9f808 MS |
3370 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3371 | { | |
3372 | regnum -= tdep->ymm16_regnum; | |
3373 | /* Extract (always little endian). Read lower 128bits. */ | |
3374 | status = regcache_raw_read (regcache, | |
3375 | I387_XMM16_REGNUM (tdep) + regnum, | |
3376 | raw_buf); | |
3377 | if (status != REG_VALID) | |
3378 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3379 | else | |
3380 | memcpy (buf, raw_buf, 16); | |
3381 | /* Read upper 128bits. */ | |
3382 | status = regcache_raw_read (regcache, | |
3383 | tdep->ymm16h_regnum + regnum, | |
3384 | raw_buf); | |
3385 | if (status != REG_VALID) | |
3386 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3387 | else | |
3388 | memcpy (buf + 16, raw_buf, 16); | |
3389 | } | |
c131fcee | 3390 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3391 | { |
3392 | int gpnum = regnum - tdep->ax_regnum; | |
3393 | ||
3394 | /* Extract (always little endian). */ | |
05d1431c PA |
3395 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3396 | if (status != REG_VALID) | |
3543a589 TT |
3397 | mark_value_bytes_unavailable (result_value, 0, |
3398 | TYPE_LENGTH (value_type (result_value))); | |
3399 | else | |
3400 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3401 | } |
3402 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3403 | { | |
3404 | /* Check byte pseudo registers last since this function will | |
3405 | be called from amd64_pseudo_register_read, which handles | |
3406 | byte pseudo registers differently. */ | |
3407 | int gpnum = regnum - tdep->al_regnum; | |
3408 | ||
3409 | /* Extract (always little endian). We read both lower and | |
3410 | upper registers. */ | |
05d1431c PA |
3411 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3412 | if (status != REG_VALID) | |
3543a589 TT |
3413 | mark_value_bytes_unavailable (result_value, 0, |
3414 | TYPE_LENGTH (value_type (result_value))); | |
3415 | else if (gpnum >= 4) | |
1ba53b71 L |
3416 | memcpy (buf, raw_buf + 1, 1); |
3417 | else | |
3418 | memcpy (buf, raw_buf, 1); | |
3419 | } | |
3420 | else | |
3421 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3422 | } | |
3543a589 TT |
3423 | } |
3424 | ||
3425 | static struct value * | |
3426 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3427 | struct regcache *regcache, | |
3428 | int regnum) | |
3429 | { | |
3430 | struct value *result; | |
3431 | ||
3432 | result = allocate_value (register_type (gdbarch, regnum)); | |
3433 | VALUE_LVAL (result) = lval_register; | |
3434 | VALUE_REGNUM (result) = regnum; | |
3435 | ||
3436 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3437 | |
3543a589 | 3438 | return result; |
28fc6740 AC |
3439 | } |
3440 | ||
1ba53b71 | 3441 | void |
28fc6740 | 3442 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3443 | int regnum, const gdb_byte *buf) |
28fc6740 | 3444 | { |
1ba53b71 L |
3445 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
3446 | ||
5716833c | 3447 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3448 | { |
c86c27af MK |
3449 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3450 | ||
28fc6740 | 3451 | /* Read ... */ |
1ba53b71 | 3452 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3453 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3454 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3455 | /* ... Write. */ |
1ba53b71 | 3456 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3457 | } |
3458 | else | |
1ba53b71 L |
3459 | { |
3460 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3461 | ||
1dbcd68c WT |
3462 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3463 | { | |
3464 | ULONGEST upper, lower; | |
3465 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3466 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3467 | ||
3468 | /* New values from input value. */ | |
3469 | regnum -= tdep->bnd0_regnum; | |
3470 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3471 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3472 | ||
3473 | /* Fetching register buffer. */ | |
3474 | regcache_raw_read (regcache, | |
3475 | I387_BND0R_REGNUM (tdep) + regnum, | |
3476 | raw_buf); | |
3477 | ||
3478 | upper = ~upper; | |
3479 | ||
3480 | /* Set register bits. */ | |
3481 | memcpy (raw_buf, &lower, 8); | |
3482 | memcpy (raw_buf + 8, &upper, 8); | |
3483 | ||
3484 | ||
3485 | regcache_raw_write (regcache, | |
3486 | I387_BND0R_REGNUM (tdep) + regnum, | |
3487 | raw_buf); | |
3488 | } | |
01f9f808 MS |
3489 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3490 | { | |
3491 | regnum -= tdep->k0_regnum; | |
3492 | ||
3493 | regcache_raw_write (regcache, | |
3494 | tdep->k0_regnum + regnum, | |
3495 | buf); | |
3496 | } | |
3497 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3498 | { | |
3499 | regnum -= tdep->zmm0_regnum; | |
3500 | ||
3501 | if (regnum < num_lower_zmm_regs) | |
3502 | { | |
3503 | /* Write lower 128bits. */ | |
3504 | regcache_raw_write (regcache, | |
3505 | I387_XMM0_REGNUM (tdep) + regnum, | |
3506 | buf); | |
3507 | /* Write upper 128bits. */ | |
3508 | regcache_raw_write (regcache, | |
3509 | I387_YMM0_REGNUM (tdep) + regnum, | |
3510 | buf + 16); | |
3511 | } | |
3512 | else | |
3513 | { | |
3514 | /* Write lower 128bits. */ | |
3515 | regcache_raw_write (regcache, | |
3516 | I387_XMM16_REGNUM (tdep) + regnum | |
3517 | - num_lower_zmm_regs, | |
3518 | buf); | |
3519 | /* Write upper 128bits. */ | |
3520 | regcache_raw_write (regcache, | |
3521 | I387_YMM16H_REGNUM (tdep) + regnum | |
3522 | - num_lower_zmm_regs, | |
3523 | buf + 16); | |
3524 | } | |
3525 | /* Write upper 256bits. */ | |
3526 | regcache_raw_write (regcache, | |
3527 | tdep->zmm0h_regnum + regnum, | |
3528 | buf + 32); | |
3529 | } | |
1dbcd68c | 3530 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3531 | { |
3532 | regnum -= tdep->ymm0_regnum; | |
3533 | ||
3534 | /* ... Write lower 128bits. */ | |
3535 | regcache_raw_write (regcache, | |
3536 | I387_XMM0_REGNUM (tdep) + regnum, | |
3537 | buf); | |
3538 | /* ... Write upper 128bits. */ | |
3539 | regcache_raw_write (regcache, | |
3540 | tdep->ymm0h_regnum + regnum, | |
3541 | buf + 16); | |
3542 | } | |
01f9f808 MS |
3543 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3544 | { | |
3545 | regnum -= tdep->ymm16_regnum; | |
3546 | ||
3547 | /* ... Write lower 128bits. */ | |
3548 | regcache_raw_write (regcache, | |
3549 | I387_XMM16_REGNUM (tdep) + regnum, | |
3550 | buf); | |
3551 | /* ... Write upper 128bits. */ | |
3552 | regcache_raw_write (regcache, | |
3553 | tdep->ymm16h_regnum + regnum, | |
3554 | buf + 16); | |
3555 | } | |
c131fcee | 3556 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3557 | { |
3558 | int gpnum = regnum - tdep->ax_regnum; | |
3559 | ||
3560 | /* Read ... */ | |
3561 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3562 | /* ... Modify ... (always little endian). */ | |
3563 | memcpy (raw_buf, buf, 2); | |
3564 | /* ... Write. */ | |
3565 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3566 | } | |
3567 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3568 | { | |
3569 | /* Check byte pseudo registers last since this function will | |
3570 | be called from amd64_pseudo_register_read, which handles | |
3571 | byte pseudo registers differently. */ | |
3572 | int gpnum = regnum - tdep->al_regnum; | |
3573 | ||
3574 | /* Read ... We read both lower and upper registers. */ | |
3575 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3576 | /* ... Modify ... (always little endian). */ | |
3577 | if (gpnum >= 4) | |
3578 | memcpy (raw_buf + 1, buf, 1); | |
3579 | else | |
3580 | memcpy (raw_buf, buf, 1); | |
3581 | /* ... Write. */ | |
3582 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3583 | } | |
3584 | else | |
3585 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3586 | } | |
28fc6740 | 3587 | } |
ff2e87ac AC |
3588 | \f |
3589 | ||
ff2e87ac AC |
3590 | /* Return the register number of the register allocated by GCC after |
3591 | REGNUM, or -1 if there is no such register. */ | |
3592 | ||
3593 | static int | |
3594 | i386_next_regnum (int regnum) | |
3595 | { | |
3596 | /* GCC allocates the registers in the order: | |
3597 | ||
3598 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3599 | ||
3600 | Since storing a variable in %esp doesn't make any sense we return | |
3601 | -1 for %ebp and for %esp itself. */ | |
3602 | static int next_regnum[] = | |
3603 | { | |
3604 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3605 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3606 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3607 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3608 | -1, -1, /* Slots for %esp and %ebp. */ | |
3609 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3610 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3611 | }; | |
3612 | ||
de5b9bb9 | 3613 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3614 | return next_regnum[regnum]; |
28fc6740 | 3615 | |
ff2e87ac AC |
3616 | return -1; |
3617 | } | |
3618 | ||
3619 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3620 | needs any special handling. */ | |
d7a0d72c | 3621 | |
3a1e71e3 | 3622 | static int |
1777feb0 MS |
3623 | i386_convert_register_p (struct gdbarch *gdbarch, |
3624 | int regnum, struct type *type) | |
d7a0d72c | 3625 | { |
de5b9bb9 MK |
3626 | int len = TYPE_LENGTH (type); |
3627 | ||
ff2e87ac AC |
3628 | /* Values may be spread across multiple registers. Most debugging |
3629 | formats aren't expressive enough to specify the locations, so | |
3630 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3631 | have a length that is a multiple of the word size, since GCC |
3632 | doesn't seem to put any other types into registers. */ | |
3633 | if (len > 4 && len % 4 == 0) | |
3634 | { | |
3635 | int last_regnum = regnum; | |
3636 | ||
3637 | while (len > 4) | |
3638 | { | |
3639 | last_regnum = i386_next_regnum (last_regnum); | |
3640 | len -= 4; | |
3641 | } | |
3642 | ||
3643 | if (last_regnum != -1) | |
3644 | return 1; | |
3645 | } | |
ff2e87ac | 3646 | |
0abe36f5 | 3647 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3648 | } |
3649 | ||
ff2e87ac AC |
3650 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3651 | return its contents in TO. */ | |
ac27f131 | 3652 | |
8dccd430 | 3653 | static int |
ff2e87ac | 3654 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3655 | struct type *type, gdb_byte *to, |
3656 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3657 | { |
20a6ec49 | 3658 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3659 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3660 | |
20a6ec49 | 3661 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3662 | return i387_register_to_value (frame, regnum, type, to, |
3663 | optimizedp, unavailablep); | |
ff2e87ac | 3664 | |
fd35795f | 3665 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3666 | |
3667 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3668 | |
de5b9bb9 MK |
3669 | while (len > 0) |
3670 | { | |
3671 | gdb_assert (regnum != -1); | |
20a6ec49 | 3672 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3673 | |
8dccd430 PA |
3674 | if (!get_frame_register_bytes (frame, regnum, 0, |
3675 | register_size (gdbarch, regnum), | |
3676 | to, optimizedp, unavailablep)) | |
3677 | return 0; | |
3678 | ||
de5b9bb9 MK |
3679 | regnum = i386_next_regnum (regnum); |
3680 | len -= 4; | |
42835c2b | 3681 | to += 4; |
de5b9bb9 | 3682 | } |
8dccd430 PA |
3683 | |
3684 | *optimizedp = *unavailablep = 0; | |
3685 | return 1; | |
ac27f131 MK |
3686 | } |
3687 | ||
ff2e87ac AC |
3688 | /* Write the contents FROM of a value of type TYPE into register |
3689 | REGNUM in frame FRAME. */ | |
ac27f131 | 3690 | |
3a1e71e3 | 3691 | static void |
ff2e87ac | 3692 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3693 | struct type *type, const gdb_byte *from) |
ac27f131 | 3694 | { |
de5b9bb9 | 3695 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3696 | |
20a6ec49 | 3697 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3698 | { |
d532c08f MK |
3699 | i387_value_to_register (frame, regnum, type, from); |
3700 | return; | |
3701 | } | |
3d261580 | 3702 | |
fd35795f | 3703 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3704 | |
3705 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3706 | |
de5b9bb9 MK |
3707 | while (len > 0) |
3708 | { | |
3709 | gdb_assert (regnum != -1); | |
875f8d0e | 3710 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3711 | |
42835c2b | 3712 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3713 | regnum = i386_next_regnum (regnum); |
3714 | len -= 4; | |
42835c2b | 3715 | from += 4; |
de5b9bb9 | 3716 | } |
ac27f131 | 3717 | } |
ff2e87ac | 3718 | \f |
7fdafb5a MK |
3719 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3720 | in the general-purpose register set REGSET to register cache | |
3721 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3722 | |
20187ed5 | 3723 | void |
473f17b0 MK |
3724 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3725 | int regnum, const void *gregs, size_t len) | |
3726 | { | |
09424cff AA |
3727 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3728 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3729 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3730 | int i; |
3731 | ||
3732 | gdb_assert (len == tdep->sizeof_gregset); | |
3733 | ||
3734 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3735 | { | |
3736 | if ((regnum == i || regnum == -1) | |
3737 | && tdep->gregset_reg_offset[i] != -1) | |
3738 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3739 | } | |
3740 | } | |
3741 | ||
7fdafb5a MK |
3742 | /* Collect register REGNUM from the register cache REGCACHE and store |
3743 | it in the buffer specified by GREGS and LEN as described by the | |
3744 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3745 | all registers in REGSET. */ | |
3746 | ||
3747 | void | |
3748 | i386_collect_gregset (const struct regset *regset, | |
3749 | const struct regcache *regcache, | |
3750 | int regnum, void *gregs, size_t len) | |
3751 | { | |
09424cff AA |
3752 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3753 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
156cdbee | 3754 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3755 | int i; |
3756 | ||
3757 | gdb_assert (len == tdep->sizeof_gregset); | |
3758 | ||
3759 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3760 | { | |
3761 | if ((regnum == i || regnum == -1) | |
3762 | && tdep->gregset_reg_offset[i] != -1) | |
3763 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3764 | } | |
3765 | } | |
3766 | ||
3767 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3768 | in the floating-point register set REGSET to register cache | |
3769 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3770 | |
3771 | static void | |
3772 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3773 | int regnum, const void *fpregs, size_t len) | |
3774 | { | |
09424cff AA |
3775 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3776 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3777 | |
66a72d25 MK |
3778 | if (len == I387_SIZEOF_FXSAVE) |
3779 | { | |
3780 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3781 | return; | |
3782 | } | |
3783 | ||
473f17b0 MK |
3784 | gdb_assert (len == tdep->sizeof_fpregset); |
3785 | i387_supply_fsave (regcache, regnum, fpregs); | |
3786 | } | |
8446b36a | 3787 | |
2f305df1 MK |
3788 | /* Collect register REGNUM from the register cache REGCACHE and store |
3789 | it in the buffer specified by FPREGS and LEN as described by the | |
3790 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3791 | all registers in REGSET. */ | |
7fdafb5a MK |
3792 | |
3793 | static void | |
3794 | i386_collect_fpregset (const struct regset *regset, | |
3795 | const struct regcache *regcache, | |
3796 | int regnum, void *fpregs, size_t len) | |
3797 | { | |
09424cff AA |
3798 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3799 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3800 | |
3801 | if (len == I387_SIZEOF_FXSAVE) | |
3802 | { | |
3803 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3804 | return; | |
3805 | } | |
3806 | ||
3807 | gdb_assert (len == tdep->sizeof_fpregset); | |
3808 | i387_collect_fsave (regcache, regnum, fpregs); | |
3809 | } | |
3810 | ||
c131fcee L |
3811 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3812 | ||
3813 | static void | |
3814 | i386_supply_xstateregset (const struct regset *regset, | |
3815 | struct regcache *regcache, int regnum, | |
3816 | const void *xstateregs, size_t len) | |
3817 | { | |
c131fcee L |
3818 | i387_supply_xsave (regcache, regnum, xstateregs); |
3819 | } | |
3820 | ||
3821 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3822 | ||
3823 | static void | |
3824 | i386_collect_xstateregset (const struct regset *regset, | |
3825 | const struct regcache *regcache, | |
3826 | int regnum, void *xstateregs, size_t len) | |
3827 | { | |
c131fcee L |
3828 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3829 | } | |
3830 | ||
8446b36a MK |
3831 | /* Return the appropriate register set for the core section identified |
3832 | by SECT_NAME and SECT_SIZE. */ | |
3833 | ||
3834 | const struct regset * | |
3835 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3836 | const char *sect_name, size_t sect_size) | |
3837 | { | |
3838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3839 | ||
3840 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3841 | { | |
3842 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3843 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3844 | i386_collect_gregset); | |
8446b36a MK |
3845 | return tdep->gregset; |
3846 | } | |
3847 | ||
66a72d25 MK |
3848 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3849 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3850 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3851 | { |
3852 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3853 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3854 | i386_collect_fpregset); | |
8446b36a MK |
3855 | return tdep->fpregset; |
3856 | } | |
3857 | ||
c131fcee L |
3858 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3859 | { | |
3860 | if (tdep->xstateregset == NULL) | |
3861 | tdep->xstateregset = regset_alloc (gdbarch, | |
3862 | i386_supply_xstateregset, | |
3863 | i386_collect_xstateregset); | |
3864 | ||
3865 | return tdep->xstateregset; | |
3866 | } | |
3867 | ||
8446b36a MK |
3868 | return NULL; |
3869 | } | |
473f17b0 | 3870 | \f |
fc338970 | 3871 | |
fc338970 | 3872 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3873 | |
3874 | CORE_ADDR | |
e17a4113 UW |
3875 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3876 | CORE_ADDR pc, char *name) | |
c906108c | 3877 | { |
e17a4113 UW |
3878 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3879 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3880 | ||
3881 | /* jmp *(dest) */ | |
3882 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3883 | { |
e17a4113 UW |
3884 | unsigned long indirect = |
3885 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3886 | struct minimal_symbol *indsym = |
7cbd4a93 | 3887 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3888 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3889 | |
c5aa993b | 3890 | if (symname) |
c906108c | 3891 | { |
c5aa993b JM |
3892 | if (strncmp (symname, "__imp_", 6) == 0 |
3893 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3894 | return name ? 1 : |
3895 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3896 | } |
3897 | } | |
fc338970 | 3898 | return 0; /* Not a trampoline. */ |
c906108c | 3899 | } |
fc338970 MK |
3900 | \f |
3901 | ||
10458914 DJ |
3902 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3903 | routine. */ | |
8201327c | 3904 | |
4bd207ef | 3905 | int |
10458914 | 3906 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3907 | { |
10458914 | 3908 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3909 | const char *name; |
911bc6ee MK |
3910 | |
3911 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3912 | return (name && strcmp ("_sigtramp", name) == 0); |
3913 | } | |
3914 | \f | |
3915 | ||
fc338970 MK |
3916 | /* We have two flavours of disassembly. The machinery on this page |
3917 | deals with switching between those. */ | |
c906108c SS |
3918 | |
3919 | static int | |
a89aa300 | 3920 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3921 | { |
5e3397bb MK |
3922 | gdb_assert (disassembly_flavor == att_flavor |
3923 | || disassembly_flavor == intel_flavor); | |
3924 | ||
3925 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3926 | constified, cast to prevent a compiler warning. */ | |
3927 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3928 | |
3929 | return print_insn_i386 (pc, info); | |
7a292a7a | 3930 | } |
fc338970 | 3931 | \f |
3ce1502b | 3932 | |
8201327c MK |
3933 | /* There are a few i386 architecture variants that differ only |
3934 | slightly from the generic i386 target. For now, we don't give them | |
3935 | their own source file, but include them here. As a consequence, | |
3936 | they'll always be included. */ | |
3ce1502b | 3937 | |
8201327c | 3938 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3939 | |
10458914 DJ |
3940 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3941 | routine. */ | |
911bc6ee | 3942 | |
8201327c | 3943 | static int |
10458914 | 3944 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3945 | { |
10458914 | 3946 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3947 | const char *name; |
911bc6ee | 3948 | |
05b4bd79 | 3949 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 3950 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 3951 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
3952 | || strcmp ("sigvechandler", name) == 0)); |
3953 | } | |
d2a7c97a | 3954 | |
10458914 DJ |
3955 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3956 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3957 | |
3a1e71e3 | 3958 | static CORE_ADDR |
10458914 | 3959 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3960 | { |
e17a4113 UW |
3961 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3962 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3963 | gdb_byte buf[4]; |
acd5c798 | 3964 | CORE_ADDR sp; |
3ce1502b | 3965 | |
10458914 | 3966 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3967 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3968 | |
e17a4113 | 3969 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 3970 | } |
55aa24fb SDJ |
3971 | |
3972 | \f | |
3973 | ||
3974 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
3975 | gdbarch.h. */ | |
3976 | ||
3977 | int | |
3978 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
3979 | { | |
3980 | return (*s == '$' /* Literal number. */ | |
3981 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
3982 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
3983 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
3984 | } | |
3985 | ||
5acfdbae SDJ |
3986 | /* Helper function for i386_stap_parse_special_token. |
3987 | ||
3988 | This function parses operands of the form `-8+3+1(%rbp)', which | |
3989 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
3990 | ||
3991 | Return 1 if the operand was parsed successfully, zero | |
3992 | otherwise. */ | |
3993 | ||
3994 | static int | |
3995 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
3996 | struct stap_parse_info *p) | |
3997 | { | |
3998 | const char *s = p->arg; | |
3999 | ||
4000 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4001 | { | |
4002 | int got_minus[3]; | |
4003 | int i; | |
4004 | long displacements[3]; | |
4005 | const char *start; | |
4006 | char *regname; | |
4007 | int len; | |
4008 | struct stoken str; | |
4009 | char *endp; | |
4010 | ||
4011 | got_minus[0] = 0; | |
4012 | if (*s == '+') | |
4013 | ++s; | |
4014 | else if (*s == '-') | |
4015 | { | |
4016 | ++s; | |
4017 | got_minus[0] = 1; | |
4018 | } | |
4019 | ||
d7b30f67 SDJ |
4020 | if (!isdigit ((unsigned char) *s)) |
4021 | return 0; | |
4022 | ||
5acfdbae SDJ |
4023 | displacements[0] = strtol (s, &endp, 10); |
4024 | s = endp; | |
4025 | ||
4026 | if (*s != '+' && *s != '-') | |
4027 | { | |
4028 | /* We are not dealing with a triplet. */ | |
4029 | return 0; | |
4030 | } | |
4031 | ||
4032 | got_minus[1] = 0; | |
4033 | if (*s == '+') | |
4034 | ++s; | |
4035 | else | |
4036 | { | |
4037 | ++s; | |
4038 | got_minus[1] = 1; | |
4039 | } | |
4040 | ||
d7b30f67 SDJ |
4041 | if (!isdigit ((unsigned char) *s)) |
4042 | return 0; | |
4043 | ||
5acfdbae SDJ |
4044 | displacements[1] = strtol (s, &endp, 10); |
4045 | s = endp; | |
4046 | ||
4047 | if (*s != '+' && *s != '-') | |
4048 | { | |
4049 | /* We are not dealing with a triplet. */ | |
4050 | return 0; | |
4051 | } | |
4052 | ||
4053 | got_minus[2] = 0; | |
4054 | if (*s == '+') | |
4055 | ++s; | |
4056 | else | |
4057 | { | |
4058 | ++s; | |
4059 | got_minus[2] = 1; | |
4060 | } | |
4061 | ||
d7b30f67 SDJ |
4062 | if (!isdigit ((unsigned char) *s)) |
4063 | return 0; | |
4064 | ||
5acfdbae SDJ |
4065 | displacements[2] = strtol (s, &endp, 10); |
4066 | s = endp; | |
4067 | ||
4068 | if (*s != '(' || s[1] != '%') | |
4069 | return 0; | |
4070 | ||
4071 | s += 2; | |
4072 | start = s; | |
4073 | ||
4074 | while (isalnum (*s)) | |
4075 | ++s; | |
4076 | ||
4077 | if (*s++ != ')') | |
4078 | return 0; | |
4079 | ||
d7b30f67 | 4080 | len = s - start - 1; |
5acfdbae SDJ |
4081 | regname = alloca (len + 1); |
4082 | ||
4083 | strncpy (regname, start, len); | |
4084 | regname[len] = '\0'; | |
4085 | ||
4086 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4087 | error (_("Invalid register name `%s' on expression `%s'."), | |
4088 | regname, p->saved_arg); | |
4089 | ||
4090 | for (i = 0; i < 3; i++) | |
4091 | { | |
410a0ff2 SDJ |
4092 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4093 | write_exp_elt_type | |
4094 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4095 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4096 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4097 | if (got_minus[i]) |
410a0ff2 | 4098 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4099 | } |
4100 | ||
410a0ff2 | 4101 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4102 | str.ptr = regname; |
4103 | str.length = len; | |
410a0ff2 SDJ |
4104 | write_exp_string (&p->pstate, str); |
4105 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4106 | |
410a0ff2 SDJ |
4107 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4108 | write_exp_elt_type (&p->pstate, | |
4109 | builtin_type (gdbarch)->builtin_data_ptr); | |
4110 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4111 | |
410a0ff2 SDJ |
4112 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4113 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4114 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4115 | |
410a0ff2 SDJ |
4116 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4117 | write_exp_elt_type (&p->pstate, | |
4118 | lookup_pointer_type (p->arg_type)); | |
4119 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4120 | |
410a0ff2 | 4121 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4122 | |
4123 | p->arg = s; | |
4124 | ||
4125 | return 1; | |
4126 | } | |
4127 | ||
4128 | return 0; | |
4129 | } | |
4130 | ||
4131 | /* Helper function for i386_stap_parse_special_token. | |
4132 | ||
4133 | This function parses operands of the form `register base + | |
4134 | (register index * size) + offset', as represented in | |
4135 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4136 | ||
4137 | Return 1 if the operand was parsed successfully, zero | |
4138 | otherwise. */ | |
4139 | ||
4140 | static int | |
4141 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4142 | struct stap_parse_info *p) | |
4143 | { | |
4144 | const char *s = p->arg; | |
4145 | ||
4146 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4147 | { | |
4148 | int offset_minus = 0; | |
4149 | long offset = 0; | |
4150 | int size_minus = 0; | |
4151 | long size = 0; | |
4152 | const char *start; | |
4153 | char *base; | |
4154 | int len_base; | |
4155 | char *index; | |
4156 | int len_index; | |
4157 | struct stoken base_token, index_token; | |
4158 | ||
4159 | if (*s == '+') | |
4160 | ++s; | |
4161 | else if (*s == '-') | |
4162 | { | |
4163 | ++s; | |
4164 | offset_minus = 1; | |
4165 | } | |
4166 | ||
4167 | if (offset_minus && !isdigit (*s)) | |
4168 | return 0; | |
4169 | ||
4170 | if (isdigit (*s)) | |
4171 | { | |
4172 | char *endp; | |
4173 | ||
4174 | offset = strtol (s, &endp, 10); | |
4175 | s = endp; | |
4176 | } | |
4177 | ||
4178 | if (*s != '(' || s[1] != '%') | |
4179 | return 0; | |
4180 | ||
4181 | s += 2; | |
4182 | start = s; | |
4183 | ||
4184 | while (isalnum (*s)) | |
4185 | ++s; | |
4186 | ||
4187 | if (*s != ',' || s[1] != '%') | |
4188 | return 0; | |
4189 | ||
4190 | len_base = s - start; | |
4191 | base = alloca (len_base + 1); | |
4192 | strncpy (base, start, len_base); | |
4193 | base[len_base] = '\0'; | |
4194 | ||
4195 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4196 | error (_("Invalid register name `%s' on expression `%s'."), | |
4197 | base, p->saved_arg); | |
4198 | ||
4199 | s += 2; | |
4200 | start = s; | |
4201 | ||
4202 | while (isalnum (*s)) | |
4203 | ++s; | |
4204 | ||
4205 | len_index = s - start; | |
4206 | index = alloca (len_index + 1); | |
4207 | strncpy (index, start, len_index); | |
4208 | index[len_index] = '\0'; | |
4209 | ||
4210 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4211 | error (_("Invalid register name `%s' on expression `%s'."), | |
4212 | index, p->saved_arg); | |
4213 | ||
4214 | if (*s != ',' && *s != ')') | |
4215 | return 0; | |
4216 | ||
4217 | if (*s == ',') | |
4218 | { | |
4219 | char *endp; | |
4220 | ||
4221 | ++s; | |
4222 | if (*s == '+') | |
4223 | ++s; | |
4224 | else if (*s == '-') | |
4225 | { | |
4226 | ++s; | |
4227 | size_minus = 1; | |
4228 | } | |
4229 | ||
4230 | size = strtol (s, &endp, 10); | |
4231 | s = endp; | |
4232 | ||
4233 | if (*s != ')') | |
4234 | return 0; | |
4235 | } | |
4236 | ||
4237 | ++s; | |
4238 | ||
4239 | if (offset) | |
4240 | { | |
410a0ff2 SDJ |
4241 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4242 | write_exp_elt_type (&p->pstate, | |
4243 | builtin_type (gdbarch)->builtin_long); | |
4244 | write_exp_elt_longcst (&p->pstate, offset); | |
4245 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4246 | if (offset_minus) |
410a0ff2 | 4247 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4248 | } |
4249 | ||
410a0ff2 | 4250 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4251 | base_token.ptr = base; |
4252 | base_token.length = len_base; | |
410a0ff2 SDJ |
4253 | write_exp_string (&p->pstate, base_token); |
4254 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4255 | |
4256 | if (offset) | |
410a0ff2 | 4257 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4258 | |
410a0ff2 | 4259 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4260 | index_token.ptr = index; |
4261 | index_token.length = len_index; | |
410a0ff2 SDJ |
4262 | write_exp_string (&p->pstate, index_token); |
4263 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4264 | |
4265 | if (size) | |
4266 | { | |
410a0ff2 SDJ |
4267 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4268 | write_exp_elt_type (&p->pstate, | |
4269 | builtin_type (gdbarch)->builtin_long); | |
4270 | write_exp_elt_longcst (&p->pstate, size); | |
4271 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4272 | if (size_minus) |
410a0ff2 SDJ |
4273 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4274 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4275 | } |
4276 | ||
410a0ff2 | 4277 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4278 | |
410a0ff2 SDJ |
4279 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4280 | write_exp_elt_type (&p->pstate, | |
4281 | lookup_pointer_type (p->arg_type)); | |
4282 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4283 | |
410a0ff2 | 4284 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4285 | |
4286 | p->arg = s; | |
4287 | ||
4288 | return 1; | |
4289 | } | |
4290 | ||
4291 | return 0; | |
4292 | } | |
4293 | ||
55aa24fb SDJ |
4294 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4295 | gdbarch.h. */ | |
4296 | ||
4297 | int | |
4298 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4299 | struct stap_parse_info *p) | |
4300 | { | |
55aa24fb SDJ |
4301 | /* In order to parse special tokens, we use a state-machine that go |
4302 | through every known token and try to get a match. */ | |
4303 | enum | |
4304 | { | |
4305 | TRIPLET, | |
4306 | THREE_ARG_DISPLACEMENT, | |
4307 | DONE | |
4308 | } current_state; | |
4309 | ||
4310 | current_state = TRIPLET; | |
4311 | ||
4312 | /* The special tokens to be parsed here are: | |
4313 | ||
4314 | - `register base + (register index * size) + offset', as represented | |
4315 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4316 | ||
4317 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4318 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4319 | ||
4320 | while (current_state != DONE) | |
4321 | { | |
55aa24fb SDJ |
4322 | switch (current_state) |
4323 | { | |
4324 | case TRIPLET: | |
5acfdbae SDJ |
4325 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4326 | return 1; | |
4327 | break; | |
4328 | ||
55aa24fb | 4329 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4330 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4331 | return 1; | |
4332 | break; | |
55aa24fb SDJ |
4333 | } |
4334 | ||
4335 | /* Advancing to the next state. */ | |
4336 | ++current_state; | |
4337 | } | |
4338 | ||
4339 | return 0; | |
4340 | } | |
4341 | ||
8201327c | 4342 | \f |
3ce1502b | 4343 | |
8201327c | 4344 | /* Generic ELF. */ |
d2a7c97a | 4345 | |
8201327c MK |
4346 | void |
4347 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4348 | { | |
05c0465e SDJ |
4349 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4350 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4351 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4352 | NULL }; | |
4353 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4354 | NULL }; | |
4355 | ||
c4fc7f1b MK |
4356 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4357 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4358 | |
4359 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4360 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4361 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4362 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4363 | stap_register_indirection_prefixes); | |
4364 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4365 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4366 | set_gdbarch_stap_is_single_operand (gdbarch, |
4367 | i386_stap_is_single_operand); | |
4368 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4369 | i386_stap_parse_special_token); | |
8201327c | 4370 | } |
3ce1502b | 4371 | |
8201327c | 4372 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4373 | |
8201327c MK |
4374 | void |
4375 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4376 | { | |
4377 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4378 | |
8201327c MK |
4379 | /* System V Release 4 uses ELF. */ |
4380 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4381 | |
dfe01d39 | 4382 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4383 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4384 | ||
911bc6ee | 4385 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4386 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4387 | tdep->sc_pc_offset = 36 + 14 * 4; |
4388 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4389 | |
8201327c | 4390 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4391 | } |
4392 | ||
8201327c | 4393 | /* DJGPP. */ |
3ce1502b | 4394 | |
3a1e71e3 | 4395 | static void |
8201327c | 4396 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 4397 | { |
8201327c | 4398 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 4399 | |
911bc6ee MK |
4400 | /* DJGPP doesn't have any special frames for signal handlers. */ |
4401 | tdep->sigtramp_p = NULL; | |
3ce1502b | 4402 | |
8201327c | 4403 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
4404 | |
4405 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
4406 | if (! tdesc_has_registers (info.target_desc)) |
4407 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
4408 | |
4409 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
4410 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
4411 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
4412 | set_gdbarch_sdb_reg_to_regnum. */ | |
4413 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
4414 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
4415 | |
4416 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 4417 | } |
8201327c | 4418 | \f |
2acceee2 | 4419 | |
38c968cf AC |
4420 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4421 | and "sse". */ | |
4422 | ||
4423 | static struct reggroup *i386_sse_reggroup; | |
4424 | static struct reggroup *i386_mmx_reggroup; | |
4425 | ||
4426 | static void | |
4427 | i386_init_reggroups (void) | |
4428 | { | |
4429 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4430 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4431 | } | |
4432 | ||
4433 | static void | |
4434 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4435 | { | |
4436 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4437 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4438 | reggroup_add (gdbarch, general_reggroup); | |
4439 | reggroup_add (gdbarch, float_reggroup); | |
4440 | reggroup_add (gdbarch, all_reggroup); | |
4441 | reggroup_add (gdbarch, save_reggroup); | |
4442 | reggroup_add (gdbarch, restore_reggroup); | |
4443 | reggroup_add (gdbarch, vector_reggroup); | |
4444 | reggroup_add (gdbarch, system_reggroup); | |
4445 | } | |
4446 | ||
4447 | int | |
4448 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4449 | struct reggroup *group) | |
4450 | { | |
c131fcee L |
4451 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4452 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4453 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4454 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4455 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
4456 | avx512_p, avx_p, sse_p; | |
acd5c798 | 4457 | |
1ba53b71 L |
4458 | /* Don't include pseudo registers, except for MMX, in any register |
4459 | groups. */ | |
c131fcee | 4460 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4461 | return 0; |
4462 | ||
c131fcee | 4463 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4464 | return 0; |
4465 | ||
c131fcee | 4466 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4467 | return 0; |
4468 | ||
4469 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4470 | if (group == i386_mmx_reggroup) |
4471 | return mmx_regnum_p; | |
1ba53b71 | 4472 | |
c131fcee | 4473 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4474 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4475 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4476 | if (group == i386_sse_reggroup) |
01f9f808 | 4477 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4478 | |
4479 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4480 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4481 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4482 | ||
4483 | avx512_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK) | |
4484 | == I386_XSTATE_AVX512_MASK); | |
4485 | avx_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK) | |
4486 | == I386_XSTATE_AVX_MASK) && !avx512_p; | |
4487 | sse_p = ((tdep->xcr0 & I386_XSTATE_AVX512_MASK) | |
4488 | == I386_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; | |
4489 | ||
38c968cf | 4490 | if (group == vector_reggroup) |
c131fcee | 4491 | return (mmx_regnum_p |
01f9f808 MS |
4492 | || (zmm_regnum_p && avx512_p) |
4493 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4494 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4495 | || mxcsr_regnum_p); | |
1ba53b71 L |
4496 | |
4497 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4498 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4499 | if (group == float_reggroup) |
4500 | return fp_regnum_p; | |
1ba53b71 | 4501 | |
c131fcee L |
4502 | /* For "info reg all", don't include upper YMM registers nor XMM |
4503 | registers when AVX is supported. */ | |
4504 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4505 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4506 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4507 | if (group == all_reggroup |
01f9f808 MS |
4508 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4509 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4510 | || ymmh_regnum_p | |
4511 | || ymmh_avx512_regnum_p | |
4512 | || zmmh_regnum_p)) | |
c131fcee L |
4513 | return 0; |
4514 | ||
1dbcd68c WT |
4515 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4516 | if (group == all_reggroup | |
4517 | && ((bnd_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4518 | return bnd_regnum_p; | |
4519 | ||
4520 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4521 | if (group == all_reggroup | |
4522 | && ((bndr_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4523 | return 0; | |
4524 | ||
4525 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4526 | if (group == all_reggroup | |
4527 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & I386_XSTATE_MPX_MASK)))) | |
4528 | return mpx_ctrl_regnum_p; | |
4529 | ||
38c968cf | 4530 | if (group == general_reggroup) |
1ba53b71 L |
4531 | return (!fp_regnum_p |
4532 | && !mmx_regnum_p | |
c131fcee L |
4533 | && !mxcsr_regnum_p |
4534 | && !xmm_regnum_p | |
01f9f808 | 4535 | && !xmm_avx512_regnum_p |
c131fcee | 4536 | && !ymm_regnum_p |
1dbcd68c | 4537 | && !ymmh_regnum_p |
01f9f808 MS |
4538 | && !ymm_avx512_regnum_p |
4539 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4540 | && !bndr_regnum_p |
4541 | && !bnd_regnum_p | |
01f9f808 MS |
4542 | && !mpx_ctrl_regnum_p |
4543 | && !zmm_regnum_p | |
4544 | && !zmmh_regnum_p); | |
acd5c798 | 4545 | |
38c968cf AC |
4546 | return default_register_reggroup_p (gdbarch, regnum, group); |
4547 | } | |
38c968cf | 4548 | \f |
acd5c798 | 4549 | |
f837910f MK |
4550 | /* Get the ARGIth function argument for the current function. */ |
4551 | ||
42c466d7 | 4552 | static CORE_ADDR |
143985b7 AF |
4553 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4554 | struct type *type) | |
4555 | { | |
e17a4113 UW |
4556 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4557 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4558 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4559 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4560 | } |
4561 | ||
514f746b AR |
4562 | static void |
4563 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
4564 | { | |
4565 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
4566 | ||
4567 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
4568 | adjust the PC in the regcache. */ | |
4569 | current_pc += 1; | |
4570 | regcache_write_pc (regcache, current_pc); | |
4571 | } | |
4572 | ||
4573 | ||
7ad10968 HZ |
4574 | #define PREFIX_REPZ 0x01 |
4575 | #define PREFIX_REPNZ 0x02 | |
4576 | #define PREFIX_LOCK 0x04 | |
4577 | #define PREFIX_DATA 0x08 | |
4578 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4579 | |
7ad10968 HZ |
4580 | /* operand size */ |
4581 | enum | |
4582 | { | |
4583 | OT_BYTE = 0, | |
4584 | OT_WORD, | |
4585 | OT_LONG, | |
cf648174 | 4586 | OT_QUAD, |
a3c4230a | 4587 | OT_DQUAD, |
7ad10968 | 4588 | }; |
473f17b0 | 4589 | |
7ad10968 HZ |
4590 | /* i386 arith/logic operations */ |
4591 | enum | |
4592 | { | |
4593 | OP_ADDL, | |
4594 | OP_ORL, | |
4595 | OP_ADCL, | |
4596 | OP_SBBL, | |
4597 | OP_ANDL, | |
4598 | OP_SUBL, | |
4599 | OP_XORL, | |
4600 | OP_CMPL, | |
4601 | }; | |
5716833c | 4602 | |
7ad10968 HZ |
4603 | struct i386_record_s |
4604 | { | |
cf648174 | 4605 | struct gdbarch *gdbarch; |
7ad10968 | 4606 | struct regcache *regcache; |
df61f520 | 4607 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4608 | CORE_ADDR addr; |
4609 | int aflag; | |
4610 | int dflag; | |
4611 | int override; | |
4612 | uint8_t modrm; | |
4613 | uint8_t mod, reg, rm; | |
4614 | int ot; | |
cf648174 HZ |
4615 | uint8_t rex_x; |
4616 | uint8_t rex_b; | |
4617 | int rip_offset; | |
4618 | int popl_esp_hack; | |
4619 | const int *regmap; | |
7ad10968 | 4620 | }; |
5716833c | 4621 | |
99c1624c PA |
4622 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4623 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4624 | |
7ad10968 HZ |
4625 | static int |
4626 | i386_record_modrm (struct i386_record_s *irp) | |
4627 | { | |
cf648174 | 4628 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4629 | |
4ffa4fc7 PA |
4630 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4631 | return -1; | |
4632 | ||
7ad10968 HZ |
4633 | irp->addr++; |
4634 | irp->mod = (irp->modrm >> 6) & 3; | |
4635 | irp->reg = (irp->modrm >> 3) & 7; | |
4636 | irp->rm = irp->modrm & 7; | |
5716833c | 4637 | |
7ad10968 HZ |
4638 | return 0; |
4639 | } | |
d2a7c97a | 4640 | |
99c1624c PA |
4641 | /* Extract the memory address that the current instruction writes to, |
4642 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4643 | |
7ad10968 | 4644 | static int |
cf648174 | 4645 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4646 | { |
cf648174 | 4647 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4648 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4649 | gdb_byte buf[4]; | |
4650 | ULONGEST offset64; | |
21d0e8a4 | 4651 | |
7ad10968 | 4652 | *addr = 0; |
1e87984a | 4653 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4654 | { |
1e87984a | 4655 | /* 32/64 bits */ |
7ad10968 HZ |
4656 | int havesib = 0; |
4657 | uint8_t scale = 0; | |
648d0c8b | 4658 | uint8_t byte; |
7ad10968 HZ |
4659 | uint8_t index = 0; |
4660 | uint8_t base = irp->rm; | |
896fb97d | 4661 | |
7ad10968 HZ |
4662 | if (base == 4) |
4663 | { | |
4664 | havesib = 1; | |
4ffa4fc7 PA |
4665 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4666 | return -1; | |
7ad10968 | 4667 | irp->addr++; |
648d0c8b MS |
4668 | scale = (byte >> 6) & 3; |
4669 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4670 | base = (byte & 7); | |
7ad10968 | 4671 | } |
cf648174 | 4672 | base |= irp->rex_b; |
21d0e8a4 | 4673 | |
7ad10968 HZ |
4674 | switch (irp->mod) |
4675 | { | |
4676 | case 0: | |
4677 | if ((base & 7) == 5) | |
4678 | { | |
4679 | base = 0xff; | |
4ffa4fc7 PA |
4680 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4681 | return -1; | |
7ad10968 | 4682 | irp->addr += 4; |
60a1502a | 4683 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4684 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4685 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4686 | } |
7ad10968 HZ |
4687 | break; |
4688 | case 1: | |
4ffa4fc7 PA |
4689 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4690 | return -1; | |
7ad10968 | 4691 | irp->addr++; |
60a1502a | 4692 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4693 | break; |
4694 | case 2: | |
4ffa4fc7 PA |
4695 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4696 | return -1; | |
60a1502a | 4697 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4698 | irp->addr += 4; |
4699 | break; | |
4700 | } | |
356a6b3e | 4701 | |
60a1502a | 4702 | offset64 = 0; |
7ad10968 | 4703 | if (base != 0xff) |
cf648174 HZ |
4704 | { |
4705 | if (base == 4 && irp->popl_esp_hack) | |
4706 | *addr += irp->popl_esp_hack; | |
4707 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4708 | &offset64); |
7ad10968 | 4709 | } |
cf648174 HZ |
4710 | if (irp->aflag == 2) |
4711 | { | |
60a1502a | 4712 | *addr += offset64; |
cf648174 HZ |
4713 | } |
4714 | else | |
60a1502a | 4715 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4716 | |
7ad10968 HZ |
4717 | if (havesib && (index != 4 || scale != 0)) |
4718 | { | |
cf648174 | 4719 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4720 | &offset64); |
cf648174 | 4721 | if (irp->aflag == 2) |
60a1502a | 4722 | *addr += offset64 << scale; |
cf648174 | 4723 | else |
60a1502a | 4724 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4725 | } |
e85596e0 L |
4726 | |
4727 | if (!irp->aflag) | |
4728 | { | |
4729 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4730 | address from 32-bit to 64-bit. */ | |
4731 | *addr = (uint32_t) *addr; | |
4732 | } | |
7ad10968 HZ |
4733 | } |
4734 | else | |
4735 | { | |
4736 | /* 16 bits */ | |
4737 | switch (irp->mod) | |
4738 | { | |
4739 | case 0: | |
4740 | if (irp->rm == 6) | |
4741 | { | |
4ffa4fc7 PA |
4742 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4743 | return -1; | |
7ad10968 | 4744 | irp->addr += 2; |
60a1502a | 4745 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4746 | irp->rm = 0; |
4747 | goto no_rm; | |
4748 | } | |
7ad10968 HZ |
4749 | break; |
4750 | case 1: | |
4ffa4fc7 PA |
4751 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4752 | return -1; | |
7ad10968 | 4753 | irp->addr++; |
60a1502a | 4754 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4755 | break; |
4756 | case 2: | |
4ffa4fc7 PA |
4757 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4758 | return -1; | |
7ad10968 | 4759 | irp->addr += 2; |
60a1502a | 4760 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4761 | break; |
4762 | } | |
c4fc7f1b | 4763 | |
7ad10968 HZ |
4764 | switch (irp->rm) |
4765 | { | |
4766 | case 0: | |
cf648174 HZ |
4767 | regcache_raw_read_unsigned (irp->regcache, |
4768 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4769 | &offset64); |
4770 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4771 | regcache_raw_read_unsigned (irp->regcache, |
4772 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4773 | &offset64); |
4774 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4775 | break; |
4776 | case 1: | |
cf648174 HZ |
4777 | regcache_raw_read_unsigned (irp->regcache, |
4778 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4779 | &offset64); |
4780 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4781 | regcache_raw_read_unsigned (irp->regcache, |
4782 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4783 | &offset64); |
4784 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4785 | break; |
4786 | case 2: | |
cf648174 HZ |
4787 | regcache_raw_read_unsigned (irp->regcache, |
4788 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4789 | &offset64); |
4790 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4791 | regcache_raw_read_unsigned (irp->regcache, |
4792 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4793 | &offset64); |
4794 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4795 | break; |
4796 | case 3: | |
cf648174 HZ |
4797 | regcache_raw_read_unsigned (irp->regcache, |
4798 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4799 | &offset64); |
4800 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4801 | regcache_raw_read_unsigned (irp->regcache, |
4802 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4803 | &offset64); |
4804 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4805 | break; |
4806 | case 4: | |
cf648174 HZ |
4807 | regcache_raw_read_unsigned (irp->regcache, |
4808 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4809 | &offset64); |
4810 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4811 | break; |
4812 | case 5: | |
cf648174 HZ |
4813 | regcache_raw_read_unsigned (irp->regcache, |
4814 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4815 | &offset64); |
4816 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4817 | break; |
4818 | case 6: | |
cf648174 HZ |
4819 | regcache_raw_read_unsigned (irp->regcache, |
4820 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4821 | &offset64); |
4822 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4823 | break; |
4824 | case 7: | |
cf648174 HZ |
4825 | regcache_raw_read_unsigned (irp->regcache, |
4826 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4827 | &offset64); |
4828 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4829 | break; |
4830 | } | |
4831 | *addr &= 0xffff; | |
4832 | } | |
c4fc7f1b | 4833 | |
01fe1b41 | 4834 | no_rm: |
7ad10968 HZ |
4835 | return 0; |
4836 | } | |
c4fc7f1b | 4837 | |
99c1624c PA |
4838 | /* Record the address and contents of the memory that will be changed |
4839 | by the current instruction. Return -1 if something goes wrong, 0 | |
4840 | otherwise. */ | |
356a6b3e | 4841 | |
7ad10968 HZ |
4842 | static int |
4843 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4844 | { | |
cf648174 HZ |
4845 | struct gdbarch *gdbarch = irp->gdbarch; |
4846 | uint64_t addr; | |
356a6b3e | 4847 | |
d7877f7e | 4848 | if (irp->override >= 0) |
7ad10968 | 4849 | { |
25ea693b | 4850 | if (record_full_memory_query) |
bb08c432 HZ |
4851 | { |
4852 | int q; | |
4853 | ||
4854 | target_terminal_ours (); | |
4855 | q = yquery (_("\ | |
4856 | Process record ignores the memory change of instruction at address %s\n\ | |
4857 | because it can't get the value of the segment register.\n\ | |
4858 | Do you want to stop the program?"), | |
4859 | paddress (gdbarch, irp->orig_addr)); | |
4860 | target_terminal_inferior (); | |
4861 | if (q) | |
4862 | return -1; | |
4863 | } | |
4864 | ||
7ad10968 HZ |
4865 | return 0; |
4866 | } | |
61113f8b | 4867 | |
7ad10968 HZ |
4868 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4869 | return -1; | |
96297dab | 4870 | |
25ea693b | 4871 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4872 | return -1; |
a62cc96e | 4873 | |
7ad10968 HZ |
4874 | return 0; |
4875 | } | |
b6197528 | 4876 | |
99c1624c PA |
4877 | /* Record the effects of a push operation. Return -1 if something |
4878 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4879 | |
4880 | static int | |
4881 | i386_record_push (struct i386_record_s *irp, int size) | |
4882 | { | |
648d0c8b | 4883 | ULONGEST addr; |
cf648174 | 4884 | |
25ea693b MM |
4885 | if (record_full_arch_list_add_reg (irp->regcache, |
4886 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4887 | return -1; |
4888 | regcache_raw_read_unsigned (irp->regcache, | |
4889 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4890 | &addr); |
25ea693b | 4891 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4892 | return -1; |
4893 | ||
4894 | return 0; | |
4895 | } | |
4896 | ||
0289bdd7 MS |
4897 | |
4898 | /* Defines contents to record. */ | |
4899 | #define I386_SAVE_FPU_REGS 0xfffd | |
4900 | #define I386_SAVE_FPU_ENV 0xfffe | |
4901 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4902 | ||
99c1624c PA |
4903 | /* Record the values of the floating point registers which will be |
4904 | changed by the current instruction. Returns -1 if something is | |
4905 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4906 | |
4907 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4908 | struct i386_record_s *ir, | |
4909 | uint32_t iregnum) | |
4910 | { | |
4911 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4912 | int i; | |
4913 | ||
4914 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4915 | happen. Currently we store st0-st7 registers, but we need not store all | |
4916 | registers all the time, in future we use ftag register and record only | |
4917 | those who are not marked as an empty. */ | |
4918 | ||
4919 | if (I386_SAVE_FPU_REGS == iregnum) | |
4920 | { | |
4921 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4922 | { | |
25ea693b | 4923 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4924 | return -1; |
4925 | } | |
4926 | } | |
4927 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4928 | { | |
4929 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4930 | { | |
25ea693b | 4931 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4932 | return -1; |
4933 | } | |
4934 | } | |
4935 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4936 | { | |
4937 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4938 | { | |
25ea693b | 4939 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4940 | return -1; |
4941 | } | |
4942 | } | |
4943 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
4944 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
4945 | { | |
25ea693b | 4946 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
4947 | return -1; |
4948 | } | |
4949 | else | |
4950 | { | |
4951 | /* Parameter error. */ | |
4952 | return -1; | |
4953 | } | |
4954 | if(I386_SAVE_FPU_ENV != iregnum) | |
4955 | { | |
4956 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4957 | { | |
25ea693b | 4958 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4959 | return -1; |
4960 | } | |
4961 | } | |
4962 | return 0; | |
4963 | } | |
4964 | ||
99c1624c PA |
4965 | /* Parse the current instruction, and record the values of the |
4966 | registers and memory that will be changed by the current | |
4967 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 4968 | |
25ea693b MM |
4969 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
4970 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 4971 | |
a6b808b4 | 4972 | int |
7ad10968 | 4973 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 4974 | CORE_ADDR input_addr) |
7ad10968 | 4975 | { |
60a1502a | 4976 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 4977 | int prefixes = 0; |
580879fc | 4978 | int regnum = 0; |
425b824a | 4979 | uint32_t opcode; |
f4644a3f | 4980 | uint8_t opcode8; |
648d0c8b | 4981 | ULONGEST addr; |
60a1502a | 4982 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 4983 | struct i386_record_s ir; |
0289bdd7 | 4984 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
4985 | uint8_t rex_w = -1; |
4986 | uint8_t rex_r = 0; | |
7ad10968 | 4987 | |
8408d274 | 4988 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 4989 | ir.regcache = regcache; |
648d0c8b MS |
4990 | ir.addr = input_addr; |
4991 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
4992 | ir.aflag = 1; |
4993 | ir.dflag = 1; | |
cf648174 HZ |
4994 | ir.override = -1; |
4995 | ir.popl_esp_hack = 0; | |
a3c4230a | 4996 | ir.regmap = tdep->record_regmap; |
cf648174 | 4997 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
4998 | |
4999 | if (record_debug > 1) | |
5000 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
5001 | "addr = %s\n", |
5002 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5003 | |
5004 | /* prefixes */ | |
5005 | while (1) | |
5006 | { | |
4ffa4fc7 PA |
5007 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5008 | return -1; | |
7ad10968 | 5009 | ir.addr++; |
425b824a | 5010 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5011 | { |
01fe1b41 | 5012 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5013 | prefixes |= PREFIX_REPZ; |
5014 | break; | |
01fe1b41 | 5015 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5016 | prefixes |= PREFIX_REPNZ; |
5017 | break; | |
01fe1b41 | 5018 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5019 | prefixes |= PREFIX_LOCK; |
5020 | break; | |
01fe1b41 | 5021 | case CS_PREFIX_OPCODE: |
cf648174 | 5022 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5023 | break; |
01fe1b41 | 5024 | case SS_PREFIX_OPCODE: |
cf648174 | 5025 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5026 | break; |
01fe1b41 | 5027 | case DS_PREFIX_OPCODE: |
cf648174 | 5028 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5029 | break; |
01fe1b41 | 5030 | case ES_PREFIX_OPCODE: |
cf648174 | 5031 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5032 | break; |
01fe1b41 | 5033 | case FS_PREFIX_OPCODE: |
cf648174 | 5034 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5035 | break; |
01fe1b41 | 5036 | case GS_PREFIX_OPCODE: |
cf648174 | 5037 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5038 | break; |
01fe1b41 | 5039 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5040 | prefixes |= PREFIX_DATA; |
5041 | break; | |
01fe1b41 | 5042 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5043 | prefixes |= PREFIX_ADDR; |
5044 | break; | |
d691bec7 MS |
5045 | case 0x40: /* i386 inc %eax */ |
5046 | case 0x41: /* i386 inc %ecx */ | |
5047 | case 0x42: /* i386 inc %edx */ | |
5048 | case 0x43: /* i386 inc %ebx */ | |
5049 | case 0x44: /* i386 inc %esp */ | |
5050 | case 0x45: /* i386 inc %ebp */ | |
5051 | case 0x46: /* i386 inc %esi */ | |
5052 | case 0x47: /* i386 inc %edi */ | |
5053 | case 0x48: /* i386 dec %eax */ | |
5054 | case 0x49: /* i386 dec %ecx */ | |
5055 | case 0x4a: /* i386 dec %edx */ | |
5056 | case 0x4b: /* i386 dec %ebx */ | |
5057 | case 0x4c: /* i386 dec %esp */ | |
5058 | case 0x4d: /* i386 dec %ebp */ | |
5059 | case 0x4e: /* i386 dec %esi */ | |
5060 | case 0x4f: /* i386 dec %edi */ | |
5061 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5062 | { |
5063 | /* REX */ | |
425b824a MS |
5064 | rex_w = (opcode8 >> 3) & 1; |
5065 | rex_r = (opcode8 & 0x4) << 1; | |
5066 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5067 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5068 | } |
d691bec7 MS |
5069 | else /* 32 bit target */ |
5070 | goto out_prefixes; | |
cf648174 | 5071 | break; |
7ad10968 HZ |
5072 | default: |
5073 | goto out_prefixes; | |
5074 | break; | |
5075 | } | |
5076 | } | |
01fe1b41 | 5077 | out_prefixes: |
cf648174 HZ |
5078 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5079 | { | |
5080 | ir.dflag = 2; | |
5081 | } | |
5082 | else | |
5083 | { | |
5084 | if (prefixes & PREFIX_DATA) | |
5085 | ir.dflag ^= 1; | |
5086 | } | |
7ad10968 HZ |
5087 | if (prefixes & PREFIX_ADDR) |
5088 | ir.aflag ^= 1; | |
cf648174 HZ |
5089 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5090 | ir.aflag = 2; | |
7ad10968 | 5091 | |
1777feb0 | 5092 | /* Now check op code. */ |
425b824a | 5093 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5094 | reswitch: |
7ad10968 HZ |
5095 | switch (opcode) |
5096 | { | |
5097 | case 0x0f: | |
4ffa4fc7 PA |
5098 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5099 | return -1; | |
7ad10968 | 5100 | ir.addr++; |
a3c4230a | 5101 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5102 | goto reswitch; |
5103 | break; | |
93924b6b | 5104 | |
a38bba38 | 5105 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5106 | case 0x01: |
5107 | case 0x02: | |
5108 | case 0x03: | |
5109 | case 0x04: | |
5110 | case 0x05: | |
5111 | case 0x08: | |
5112 | case 0x09: | |
5113 | case 0x0a: | |
5114 | case 0x0b: | |
5115 | case 0x0c: | |
5116 | case 0x0d: | |
5117 | case 0x10: | |
5118 | case 0x11: | |
5119 | case 0x12: | |
5120 | case 0x13: | |
5121 | case 0x14: | |
5122 | case 0x15: | |
5123 | case 0x18: | |
5124 | case 0x19: | |
5125 | case 0x1a: | |
5126 | case 0x1b: | |
5127 | case 0x1c: | |
5128 | case 0x1d: | |
5129 | case 0x20: | |
5130 | case 0x21: | |
5131 | case 0x22: | |
5132 | case 0x23: | |
5133 | case 0x24: | |
5134 | case 0x25: | |
5135 | case 0x28: | |
5136 | case 0x29: | |
5137 | case 0x2a: | |
5138 | case 0x2b: | |
5139 | case 0x2c: | |
5140 | case 0x2d: | |
5141 | case 0x30: | |
5142 | case 0x31: | |
5143 | case 0x32: | |
5144 | case 0x33: | |
5145 | case 0x34: | |
5146 | case 0x35: | |
5147 | case 0x38: | |
5148 | case 0x39: | |
5149 | case 0x3a: | |
5150 | case 0x3b: | |
5151 | case 0x3c: | |
5152 | case 0x3d: | |
5153 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5154 | { | |
5155 | if ((opcode & 1) == 0) | |
5156 | ir.ot = OT_BYTE; | |
5157 | else | |
5158 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5159 | |
7ad10968 HZ |
5160 | switch ((opcode >> 1) & 3) |
5161 | { | |
a38bba38 | 5162 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5163 | if (i386_record_modrm (&ir)) |
5164 | return -1; | |
5165 | if (ir.mod != 3) | |
5166 | { | |
5167 | if (i386_record_lea_modrm (&ir)) | |
5168 | return -1; | |
5169 | } | |
5170 | else | |
5171 | { | |
cf648174 HZ |
5172 | ir.rm |= ir.rex_b; |
5173 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5174 | ir.rm &= 0x3; |
25ea693b | 5175 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5176 | } |
5177 | break; | |
a38bba38 | 5178 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5179 | if (i386_record_modrm (&ir)) |
5180 | return -1; | |
cf648174 HZ |
5181 | ir.reg |= rex_r; |
5182 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5183 | ir.reg &= 0x3; |
25ea693b | 5184 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5185 | break; |
a38bba38 | 5186 | case 2: /* OP A, Iv */ |
25ea693b | 5187 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5188 | break; |
5189 | } | |
5190 | } | |
25ea693b | 5191 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5192 | break; |
42fdc8df | 5193 | |
a38bba38 | 5194 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5195 | case 0x81: |
5196 | case 0x82: | |
5197 | case 0x83: | |
5198 | if (i386_record_modrm (&ir)) | |
5199 | return -1; | |
8201327c | 5200 | |
7ad10968 HZ |
5201 | if (ir.reg != OP_CMPL) |
5202 | { | |
5203 | if ((opcode & 1) == 0) | |
5204 | ir.ot = OT_BYTE; | |
5205 | else | |
5206 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5207 | |
7ad10968 HZ |
5208 | if (ir.mod != 3) |
5209 | { | |
cf648174 HZ |
5210 | if (opcode == 0x83) |
5211 | ir.rip_offset = 1; | |
5212 | else | |
5213 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5214 | if (i386_record_lea_modrm (&ir)) |
5215 | return -1; | |
5216 | } | |
5217 | else | |
25ea693b | 5218 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5219 | } |
25ea693b | 5220 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5221 | break; |
5e3397bb | 5222 | |
a38bba38 | 5223 | case 0x40: /* inc */ |
7ad10968 HZ |
5224 | case 0x41: |
5225 | case 0x42: | |
5226 | case 0x43: | |
5227 | case 0x44: | |
5228 | case 0x45: | |
5229 | case 0x46: | |
5230 | case 0x47: | |
a38bba38 MS |
5231 | |
5232 | case 0x48: /* dec */ | |
7ad10968 HZ |
5233 | case 0x49: |
5234 | case 0x4a: | |
5235 | case 0x4b: | |
5236 | case 0x4c: | |
5237 | case 0x4d: | |
5238 | case 0x4e: | |
5239 | case 0x4f: | |
a38bba38 | 5240 | |
25ea693b MM |
5241 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5242 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5243 | break; |
acd5c798 | 5244 | |
a38bba38 | 5245 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5246 | case 0xf7: |
5247 | if ((opcode & 1) == 0) | |
5248 | ir.ot = OT_BYTE; | |
5249 | else | |
5250 | ir.ot = ir.dflag + OT_WORD; | |
5251 | if (i386_record_modrm (&ir)) | |
5252 | return -1; | |
acd5c798 | 5253 | |
cf648174 HZ |
5254 | if (ir.mod != 3 && ir.reg == 0) |
5255 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5256 | ||
7ad10968 HZ |
5257 | switch (ir.reg) |
5258 | { | |
a38bba38 | 5259 | case 0: /* test */ |
25ea693b | 5260 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5261 | break; |
a38bba38 MS |
5262 | case 2: /* not */ |
5263 | case 3: /* neg */ | |
7ad10968 HZ |
5264 | if (ir.mod != 3) |
5265 | { | |
5266 | if (i386_record_lea_modrm (&ir)) | |
5267 | return -1; | |
5268 | } | |
5269 | else | |
5270 | { | |
cf648174 HZ |
5271 | ir.rm |= ir.rex_b; |
5272 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5273 | ir.rm &= 0x3; |
25ea693b | 5274 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5275 | } |
a38bba38 | 5276 | if (ir.reg == 3) /* neg */ |
25ea693b | 5277 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5278 | break; |
a38bba38 MS |
5279 | case 4: /* mul */ |
5280 | case 5: /* imul */ | |
5281 | case 6: /* div */ | |
5282 | case 7: /* idiv */ | |
25ea693b | 5283 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5284 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5286 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5287 | break; |
5288 | default: | |
5289 | ir.addr -= 2; | |
5290 | opcode = opcode << 8 | ir.modrm; | |
5291 | goto no_support; | |
5292 | break; | |
5293 | } | |
5294 | break; | |
5295 | ||
a38bba38 MS |
5296 | case 0xfe: /* GRP4 */ |
5297 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5298 | if (i386_record_modrm (&ir)) |
5299 | return -1; | |
5300 | if (ir.reg >= 2 && opcode == 0xfe) | |
5301 | { | |
5302 | ir.addr -= 2; | |
5303 | opcode = opcode << 8 | ir.modrm; | |
5304 | goto no_support; | |
5305 | } | |
7ad10968 HZ |
5306 | switch (ir.reg) |
5307 | { | |
a38bba38 MS |
5308 | case 0: /* inc */ |
5309 | case 1: /* dec */ | |
cf648174 HZ |
5310 | if ((opcode & 1) == 0) |
5311 | ir.ot = OT_BYTE; | |
5312 | else | |
5313 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5314 | if (ir.mod != 3) |
5315 | { | |
5316 | if (i386_record_lea_modrm (&ir)) | |
5317 | return -1; | |
5318 | } | |
5319 | else | |
5320 | { | |
cf648174 HZ |
5321 | ir.rm |= ir.rex_b; |
5322 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5323 | ir.rm &= 0x3; |
25ea693b | 5324 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5325 | } |
25ea693b | 5326 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5327 | break; |
a38bba38 | 5328 | case 2: /* call */ |
cf648174 HZ |
5329 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5330 | ir.dflag = 2; | |
5331 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5332 | return -1; |
25ea693b | 5333 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5334 | break; |
a38bba38 | 5335 | case 3: /* lcall */ |
25ea693b | 5336 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5337 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5338 | return -1; |
25ea693b | 5339 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5340 | break; |
a38bba38 MS |
5341 | case 4: /* jmp */ |
5342 | case 5: /* ljmp */ | |
25ea693b | 5343 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5344 | break; |
a38bba38 | 5345 | case 6: /* push */ |
cf648174 HZ |
5346 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5347 | ir.dflag = 2; | |
5348 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5349 | return -1; | |
7ad10968 HZ |
5350 | break; |
5351 | default: | |
5352 | ir.addr -= 2; | |
5353 | opcode = opcode << 8 | ir.modrm; | |
5354 | goto no_support; | |
5355 | break; | |
5356 | } | |
5357 | break; | |
5358 | ||
a38bba38 | 5359 | case 0x84: /* test */ |
7ad10968 HZ |
5360 | case 0x85: |
5361 | case 0xa8: | |
5362 | case 0xa9: | |
25ea693b | 5363 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5364 | break; |
5365 | ||
a38bba38 | 5366 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5367 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5368 | break; |
5369 | ||
a38bba38 | 5370 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5371 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5372 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5373 | break; |
5374 | ||
a38bba38 | 5375 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5376 | case 0x69: |
5377 | case 0x6b: | |
5378 | ir.ot = ir.dflag + OT_WORD; | |
5379 | if (i386_record_modrm (&ir)) | |
5380 | return -1; | |
cf648174 HZ |
5381 | if (opcode == 0x69) |
5382 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5383 | else if (opcode == 0x6b) | |
5384 | ir.rip_offset = 1; | |
5385 | ir.reg |= rex_r; | |
5386 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5387 | ir.reg &= 0x3; |
25ea693b MM |
5388 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5389 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5390 | break; |
5391 | ||
a38bba38 | 5392 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5393 | case 0x0fc1: |
5394 | if ((opcode & 1) == 0) | |
5395 | ir.ot = OT_BYTE; | |
5396 | else | |
5397 | ir.ot = ir.dflag + OT_WORD; | |
5398 | if (i386_record_modrm (&ir)) | |
5399 | return -1; | |
cf648174 | 5400 | ir.reg |= rex_r; |
7ad10968 HZ |
5401 | if (ir.mod == 3) |
5402 | { | |
cf648174 | 5403 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5404 | ir.reg &= 0x3; |
25ea693b | 5405 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5406 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5407 | ir.rm &= 0x3; |
25ea693b | 5408 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5409 | } |
5410 | else | |
5411 | { | |
5412 | if (i386_record_lea_modrm (&ir)) | |
5413 | return -1; | |
cf648174 | 5414 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5415 | ir.reg &= 0x3; |
25ea693b | 5416 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5417 | } |
25ea693b | 5418 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5419 | break; |
5420 | ||
a38bba38 | 5421 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5422 | case 0x0fb1: |
5423 | if ((opcode & 1) == 0) | |
5424 | ir.ot = OT_BYTE; | |
5425 | else | |
5426 | ir.ot = ir.dflag + OT_WORD; | |
5427 | if (i386_record_modrm (&ir)) | |
5428 | return -1; | |
5429 | if (ir.mod == 3) | |
5430 | { | |
cf648174 | 5431 | ir.reg |= rex_r; |
25ea693b | 5432 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5433 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5434 | ir.reg &= 0x3; |
25ea693b | 5435 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5436 | } |
5437 | else | |
5438 | { | |
25ea693b | 5439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5440 | if (i386_record_lea_modrm (&ir)) |
5441 | return -1; | |
5442 | } | |
25ea693b | 5443 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5444 | break; |
5445 | ||
a38bba38 | 5446 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
5447 | if (i386_record_modrm (&ir)) |
5448 | return -1; | |
5449 | if (ir.mod == 3) | |
5450 | { | |
5451 | ir.addr -= 2; | |
5452 | opcode = opcode << 8 | ir.modrm; | |
5453 | goto no_support; | |
5454 | } | |
25ea693b MM |
5455 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5456 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5457 | if (i386_record_lea_modrm (&ir)) |
5458 | return -1; | |
25ea693b | 5459 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5460 | break; |
5461 | ||
a38bba38 | 5462 | case 0x50: /* push */ |
7ad10968 HZ |
5463 | case 0x51: |
5464 | case 0x52: | |
5465 | case 0x53: | |
5466 | case 0x54: | |
5467 | case 0x55: | |
5468 | case 0x56: | |
5469 | case 0x57: | |
5470 | case 0x68: | |
5471 | case 0x6a: | |
cf648174 HZ |
5472 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5473 | ir.dflag = 2; | |
5474 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5475 | return -1; | |
5476 | break; | |
5477 | ||
a38bba38 MS |
5478 | case 0x06: /* push es */ |
5479 | case 0x0e: /* push cs */ | |
5480 | case 0x16: /* push ss */ | |
5481 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5482 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5483 | { | |
5484 | ir.addr -= 1; | |
5485 | goto no_support; | |
5486 | } | |
5487 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5488 | return -1; | |
5489 | break; | |
5490 | ||
a38bba38 MS |
5491 | case 0x0fa0: /* push fs */ |
5492 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5493 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5494 | { | |
5495 | ir.addr -= 2; | |
5496 | goto no_support; | |
5497 | } | |
5498 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5499 | return -1; |
cf648174 HZ |
5500 | break; |
5501 | ||
a38bba38 | 5502 | case 0x60: /* pusha */ |
cf648174 HZ |
5503 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5504 | { | |
5505 | ir.addr -= 1; | |
5506 | goto no_support; | |
5507 | } | |
5508 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5509 | return -1; |
5510 | break; | |
5511 | ||
a38bba38 | 5512 | case 0x58: /* pop */ |
7ad10968 HZ |
5513 | case 0x59: |
5514 | case 0x5a: | |
5515 | case 0x5b: | |
5516 | case 0x5c: | |
5517 | case 0x5d: | |
5518 | case 0x5e: | |
5519 | case 0x5f: | |
25ea693b MM |
5520 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5522 | break; |
5523 | ||
a38bba38 | 5524 | case 0x61: /* popa */ |
cf648174 HZ |
5525 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5526 | { | |
5527 | ir.addr -= 1; | |
5528 | goto no_support; | |
7ad10968 | 5529 | } |
425b824a MS |
5530 | for (regnum = X86_RECORD_REAX_REGNUM; |
5531 | regnum <= X86_RECORD_REDI_REGNUM; | |
5532 | regnum++) | |
25ea693b | 5533 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5534 | break; |
5535 | ||
a38bba38 | 5536 | case 0x8f: /* pop */ |
cf648174 HZ |
5537 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5538 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5539 | else | |
5540 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5541 | if (i386_record_modrm (&ir)) |
5542 | return -1; | |
5543 | if (ir.mod == 3) | |
25ea693b | 5544 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5545 | else |
5546 | { | |
cf648174 | 5547 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5548 | if (i386_record_lea_modrm (&ir)) |
5549 | return -1; | |
5550 | } | |
25ea693b | 5551 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5552 | break; |
5553 | ||
a38bba38 | 5554 | case 0xc8: /* enter */ |
25ea693b | 5555 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5556 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5557 | ir.dflag = 2; | |
5558 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5559 | return -1; |
5560 | break; | |
5561 | ||
a38bba38 | 5562 | case 0xc9: /* leave */ |
25ea693b MM |
5563 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5564 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5565 | break; |
5566 | ||
a38bba38 | 5567 | case 0x07: /* pop es */ |
cf648174 HZ |
5568 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5569 | { | |
5570 | ir.addr -= 1; | |
5571 | goto no_support; | |
5572 | } | |
25ea693b MM |
5573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5574 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5575 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5576 | break; |
5577 | ||
a38bba38 | 5578 | case 0x17: /* pop ss */ |
cf648174 HZ |
5579 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5580 | { | |
5581 | ir.addr -= 1; | |
5582 | goto no_support; | |
5583 | } | |
25ea693b MM |
5584 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5585 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5586 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5587 | break; |
5588 | ||
a38bba38 | 5589 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5590 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5591 | { | |
5592 | ir.addr -= 1; | |
5593 | goto no_support; | |
5594 | } | |
25ea693b MM |
5595 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5596 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5597 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5598 | break; |
5599 | ||
a38bba38 | 5600 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5601 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5602 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5603 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5604 | break; |
5605 | ||
a38bba38 | 5606 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5607 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5608 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5609 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5610 | break; |
5611 | ||
a38bba38 | 5612 | case 0x88: /* mov */ |
7ad10968 HZ |
5613 | case 0x89: |
5614 | case 0xc6: | |
5615 | case 0xc7: | |
5616 | if ((opcode & 1) == 0) | |
5617 | ir.ot = OT_BYTE; | |
5618 | else | |
5619 | ir.ot = ir.dflag + OT_WORD; | |
5620 | ||
5621 | if (i386_record_modrm (&ir)) | |
5622 | return -1; | |
5623 | ||
5624 | if (ir.mod != 3) | |
5625 | { | |
cf648174 HZ |
5626 | if (opcode == 0xc6 || opcode == 0xc7) |
5627 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5628 | if (i386_record_lea_modrm (&ir)) |
5629 | return -1; | |
5630 | } | |
5631 | else | |
5632 | { | |
cf648174 HZ |
5633 | if (opcode == 0xc6 || opcode == 0xc7) |
5634 | ir.rm |= ir.rex_b; | |
5635 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5636 | ir.rm &= 0x3; |
25ea693b | 5637 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5638 | } |
7ad10968 | 5639 | break; |
cf648174 | 5640 | |
a38bba38 | 5641 | case 0x8a: /* mov */ |
7ad10968 HZ |
5642 | case 0x8b: |
5643 | if ((opcode & 1) == 0) | |
5644 | ir.ot = OT_BYTE; | |
5645 | else | |
5646 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5647 | if (i386_record_modrm (&ir)) |
5648 | return -1; | |
cf648174 HZ |
5649 | ir.reg |= rex_r; |
5650 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5651 | ir.reg &= 0x3; |
25ea693b | 5652 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5653 | break; |
7ad10968 | 5654 | |
a38bba38 | 5655 | case 0x8c: /* mov seg */ |
cf648174 | 5656 | if (i386_record_modrm (&ir)) |
7ad10968 | 5657 | return -1; |
cf648174 HZ |
5658 | if (ir.reg > 5) |
5659 | { | |
5660 | ir.addr -= 2; | |
5661 | opcode = opcode << 8 | ir.modrm; | |
5662 | goto no_support; | |
5663 | } | |
5664 | ||
5665 | if (ir.mod == 3) | |
25ea693b | 5666 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5667 | else |
5668 | { | |
5669 | ir.ot = OT_WORD; | |
5670 | if (i386_record_lea_modrm (&ir)) | |
5671 | return -1; | |
5672 | } | |
7ad10968 HZ |
5673 | break; |
5674 | ||
a38bba38 | 5675 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5676 | if (i386_record_modrm (&ir)) |
5677 | return -1; | |
7ad10968 HZ |
5678 | switch (ir.reg) |
5679 | { | |
5680 | case 0: | |
425b824a | 5681 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5682 | break; |
5683 | case 2: | |
425b824a | 5684 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5685 | break; |
5686 | case 3: | |
425b824a | 5687 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5688 | break; |
5689 | case 4: | |
425b824a | 5690 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5691 | break; |
5692 | case 5: | |
425b824a | 5693 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5694 | break; |
5695 | default: | |
5696 | ir.addr -= 2; | |
5697 | opcode = opcode << 8 | ir.modrm; | |
5698 | goto no_support; | |
5699 | break; | |
5700 | } | |
25ea693b MM |
5701 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5702 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5703 | break; |
5704 | ||
a38bba38 MS |
5705 | case 0x0fb6: /* movzbS */ |
5706 | case 0x0fb7: /* movzwS */ | |
5707 | case 0x0fbe: /* movsbS */ | |
5708 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5709 | if (i386_record_modrm (&ir)) |
5710 | return -1; | |
25ea693b | 5711 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5712 | break; |
5713 | ||
a38bba38 | 5714 | case 0x8d: /* lea */ |
7ad10968 HZ |
5715 | if (i386_record_modrm (&ir)) |
5716 | return -1; | |
5717 | if (ir.mod == 3) | |
5718 | { | |
5719 | ir.addr -= 2; | |
5720 | opcode = opcode << 8 | ir.modrm; | |
5721 | goto no_support; | |
5722 | } | |
7ad10968 | 5723 | ir.ot = ir.dflag; |
cf648174 HZ |
5724 | ir.reg |= rex_r; |
5725 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5726 | ir.reg &= 0x3; |
25ea693b | 5727 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5728 | break; |
5729 | ||
a38bba38 | 5730 | case 0xa0: /* mov EAX */ |
7ad10968 | 5731 | case 0xa1: |
a38bba38 MS |
5732 | |
5733 | case 0xd7: /* xlat */ | |
25ea693b | 5734 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5735 | break; |
5736 | ||
a38bba38 | 5737 | case 0xa2: /* mov EAX */ |
7ad10968 | 5738 | case 0xa3: |
d7877f7e | 5739 | if (ir.override >= 0) |
cf648174 | 5740 | { |
25ea693b | 5741 | if (record_full_memory_query) |
bb08c432 HZ |
5742 | { |
5743 | int q; | |
5744 | ||
5745 | target_terminal_ours (); | |
5746 | q = yquery (_("\ | |
5747 | Process record ignores the memory change of instruction at address %s\n\ | |
5748 | because it can't get the value of the segment register.\n\ | |
5749 | Do you want to stop the program?"), | |
5750 | paddress (gdbarch, ir.orig_addr)); | |
5751 | target_terminal_inferior (); | |
5752 | if (q) | |
5753 | return -1; | |
5754 | } | |
cf648174 HZ |
5755 | } |
5756 | else | |
5757 | { | |
5758 | if ((opcode & 1) == 0) | |
5759 | ir.ot = OT_BYTE; | |
5760 | else | |
5761 | ir.ot = ir.dflag + OT_WORD; | |
5762 | if (ir.aflag == 2) | |
5763 | { | |
4ffa4fc7 PA |
5764 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5765 | return -1; | |
cf648174 | 5766 | ir.addr += 8; |
60a1502a | 5767 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5768 | } |
5769 | else if (ir.aflag) | |
5770 | { | |
4ffa4fc7 PA |
5771 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5772 | return -1; | |
cf648174 | 5773 | ir.addr += 4; |
60a1502a | 5774 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5775 | } |
5776 | else | |
5777 | { | |
4ffa4fc7 PA |
5778 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5779 | return -1; | |
cf648174 | 5780 | ir.addr += 2; |
60a1502a | 5781 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5782 | } |
25ea693b | 5783 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5784 | return -1; |
5785 | } | |
7ad10968 HZ |
5786 | break; |
5787 | ||
a38bba38 | 5788 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5789 | case 0xb1: |
5790 | case 0xb2: | |
5791 | case 0xb3: | |
5792 | case 0xb4: | |
5793 | case 0xb5: | |
5794 | case 0xb6: | |
5795 | case 0xb7: | |
25ea693b MM |
5796 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5797 | ? ((opcode & 0x7) | ir.rex_b) | |
5798 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5799 | break; |
5800 | ||
a38bba38 | 5801 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5802 | case 0xb9: |
5803 | case 0xba: | |
5804 | case 0xbb: | |
5805 | case 0xbc: | |
5806 | case 0xbd: | |
5807 | case 0xbe: | |
5808 | case 0xbf: | |
25ea693b | 5809 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5810 | break; |
5811 | ||
a38bba38 | 5812 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5813 | case 0x92: |
5814 | case 0x93: | |
5815 | case 0x94: | |
5816 | case 0x95: | |
5817 | case 0x96: | |
5818 | case 0x97: | |
25ea693b MM |
5819 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5820 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5821 | break; |
5822 | ||
a38bba38 | 5823 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5824 | case 0x87: |
5825 | if ((opcode & 1) == 0) | |
5826 | ir.ot = OT_BYTE; | |
5827 | else | |
5828 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5829 | if (i386_record_modrm (&ir)) |
5830 | return -1; | |
7ad10968 HZ |
5831 | if (ir.mod == 3) |
5832 | { | |
86839d38 | 5833 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5834 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5835 | ir.rm &= 0x3; | |
25ea693b | 5836 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5837 | } |
5838 | else | |
5839 | { | |
5840 | if (i386_record_lea_modrm (&ir)) | |
5841 | return -1; | |
5842 | } | |
cf648174 HZ |
5843 | ir.reg |= rex_r; |
5844 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5845 | ir.reg &= 0x3; |
25ea693b | 5846 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5847 | break; |
5848 | ||
a38bba38 MS |
5849 | case 0xc4: /* les Gv */ |
5850 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5851 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5852 | { | |
5853 | ir.addr -= 1; | |
5854 | goto no_support; | |
5855 | } | |
d3f323f3 | 5856 | /* FALLTHROUGH */ |
a38bba38 MS |
5857 | case 0x0fb2: /* lss Gv */ |
5858 | case 0x0fb4: /* lfs Gv */ | |
5859 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5860 | if (i386_record_modrm (&ir)) |
5861 | return -1; | |
5862 | if (ir.mod == 3) | |
5863 | { | |
5864 | if (opcode > 0xff) | |
5865 | ir.addr -= 3; | |
5866 | else | |
5867 | ir.addr -= 2; | |
5868 | opcode = opcode << 8 | ir.modrm; | |
5869 | goto no_support; | |
5870 | } | |
7ad10968 HZ |
5871 | switch (opcode) |
5872 | { | |
a38bba38 | 5873 | case 0xc4: /* les Gv */ |
425b824a | 5874 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5875 | break; |
a38bba38 | 5876 | case 0xc5: /* lds Gv */ |
425b824a | 5877 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5878 | break; |
a38bba38 | 5879 | case 0x0fb2: /* lss Gv */ |
425b824a | 5880 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5881 | break; |
a38bba38 | 5882 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5883 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5884 | break; |
a38bba38 | 5885 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5886 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5887 | break; |
5888 | } | |
25ea693b MM |
5889 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5890 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5891 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5892 | break; |
5893 | ||
a38bba38 | 5894 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5895 | case 0xc1: |
5896 | case 0xd0: | |
5897 | case 0xd1: | |
5898 | case 0xd2: | |
5899 | case 0xd3: | |
5900 | if ((opcode & 1) == 0) | |
5901 | ir.ot = OT_BYTE; | |
5902 | else | |
5903 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5904 | if (i386_record_modrm (&ir)) |
5905 | return -1; | |
7ad10968 HZ |
5906 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5907 | { | |
5908 | if (i386_record_lea_modrm (&ir)) | |
5909 | return -1; | |
5910 | } | |
5911 | else | |
5912 | { | |
cf648174 HZ |
5913 | ir.rm |= ir.rex_b; |
5914 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5915 | ir.rm &= 0x3; |
25ea693b | 5916 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5917 | } |
25ea693b | 5918 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5919 | break; |
5920 | ||
5921 | case 0x0fa4: | |
5922 | case 0x0fa5: | |
5923 | case 0x0fac: | |
5924 | case 0x0fad: | |
5925 | if (i386_record_modrm (&ir)) | |
5926 | return -1; | |
5927 | if (ir.mod == 3) | |
5928 | { | |
25ea693b | 5929 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5930 | return -1; |
5931 | } | |
5932 | else | |
5933 | { | |
5934 | if (i386_record_lea_modrm (&ir)) | |
5935 | return -1; | |
5936 | } | |
5937 | break; | |
5938 | ||
a38bba38 | 5939 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5940 | case 0xd9: |
5941 | case 0xda: | |
5942 | case 0xdb: | |
5943 | case 0xdc: | |
5944 | case 0xdd: | |
5945 | case 0xde: | |
5946 | case 0xdf: | |
5947 | if (i386_record_modrm (&ir)) | |
5948 | return -1; | |
5949 | ir.reg |= ((opcode & 7) << 3); | |
5950 | if (ir.mod != 3) | |
5951 | { | |
1777feb0 | 5952 | /* Memory. */ |
955db0c0 | 5953 | uint64_t addr64; |
7ad10968 | 5954 | |
955db0c0 | 5955 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
5956 | return -1; |
5957 | switch (ir.reg) | |
5958 | { | |
7ad10968 | 5959 | case 0x02: |
0289bdd7 MS |
5960 | case 0x12: |
5961 | case 0x22: | |
5962 | case 0x32: | |
5963 | /* For fcom, ficom nothing to do. */ | |
5964 | break; | |
7ad10968 | 5965 | case 0x03: |
0289bdd7 MS |
5966 | case 0x13: |
5967 | case 0x23: | |
5968 | case 0x33: | |
5969 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5970 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5971 | return -1; | |
5972 | break; | |
5973 | case 0x00: | |
5974 | case 0x01: | |
7ad10968 HZ |
5975 | case 0x04: |
5976 | case 0x05: | |
5977 | case 0x06: | |
5978 | case 0x07: | |
5979 | case 0x10: | |
5980 | case 0x11: | |
7ad10968 HZ |
5981 | case 0x14: |
5982 | case 0x15: | |
5983 | case 0x16: | |
5984 | case 0x17: | |
5985 | case 0x20: | |
5986 | case 0x21: | |
7ad10968 HZ |
5987 | case 0x24: |
5988 | case 0x25: | |
5989 | case 0x26: | |
5990 | case 0x27: | |
5991 | case 0x30: | |
5992 | case 0x31: | |
7ad10968 HZ |
5993 | case 0x34: |
5994 | case 0x35: | |
5995 | case 0x36: | |
5996 | case 0x37: | |
0289bdd7 MS |
5997 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5998 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5999 | of code, always affects st(0) register. */ | |
6000 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6001 | return -1; | |
7ad10968 HZ |
6002 | break; |
6003 | case 0x08: | |
6004 | case 0x0a: | |
6005 | case 0x0b: | |
6006 | case 0x18: | |
6007 | case 0x19: | |
6008 | case 0x1a: | |
6009 | case 0x1b: | |
0289bdd7 | 6010 | case 0x1d: |
7ad10968 HZ |
6011 | case 0x28: |
6012 | case 0x29: | |
6013 | case 0x2a: | |
6014 | case 0x2b: | |
6015 | case 0x38: | |
6016 | case 0x39: | |
6017 | case 0x3a: | |
6018 | case 0x3b: | |
0289bdd7 MS |
6019 | case 0x3c: |
6020 | case 0x3d: | |
7ad10968 HZ |
6021 | switch (ir.reg & 7) |
6022 | { | |
6023 | case 0: | |
0289bdd7 MS |
6024 | /* Handling fld, fild. */ |
6025 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6026 | return -1; | |
7ad10968 HZ |
6027 | break; |
6028 | case 1: | |
6029 | switch (ir.reg >> 4) | |
6030 | { | |
6031 | case 0: | |
25ea693b | 6032 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6033 | return -1; |
6034 | break; | |
6035 | case 2: | |
25ea693b | 6036 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6037 | return -1; |
6038 | break; | |
6039 | case 3: | |
0289bdd7 | 6040 | break; |
7ad10968 | 6041 | default: |
25ea693b | 6042 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6043 | return -1; |
6044 | break; | |
6045 | } | |
6046 | break; | |
6047 | default: | |
6048 | switch (ir.reg >> 4) | |
6049 | { | |
6050 | case 0: | |
25ea693b | 6051 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6052 | return -1; |
6053 | if (3 == (ir.reg & 7)) | |
6054 | { | |
6055 | /* For fstp m32fp. */ | |
6056 | if (i386_record_floats (gdbarch, &ir, | |
6057 | I386_SAVE_FPU_REGS)) | |
6058 | return -1; | |
6059 | } | |
6060 | break; | |
7ad10968 | 6061 | case 1: |
25ea693b | 6062 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6063 | return -1; |
0289bdd7 MS |
6064 | if ((3 == (ir.reg & 7)) |
6065 | || (5 == (ir.reg & 7)) | |
6066 | || (7 == (ir.reg & 7))) | |
6067 | { | |
6068 | /* For fstp insn. */ | |
6069 | if (i386_record_floats (gdbarch, &ir, | |
6070 | I386_SAVE_FPU_REGS)) | |
6071 | return -1; | |
6072 | } | |
7ad10968 HZ |
6073 | break; |
6074 | case 2: | |
25ea693b | 6075 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6076 | return -1; |
0289bdd7 MS |
6077 | if (3 == (ir.reg & 7)) |
6078 | { | |
6079 | /* For fstp m64fp. */ | |
6080 | if (i386_record_floats (gdbarch, &ir, | |
6081 | I386_SAVE_FPU_REGS)) | |
6082 | return -1; | |
6083 | } | |
7ad10968 HZ |
6084 | break; |
6085 | case 3: | |
0289bdd7 MS |
6086 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6087 | { | |
6088 | /* For fistp, fbld, fild, fbstp. */ | |
6089 | if (i386_record_floats (gdbarch, &ir, | |
6090 | I386_SAVE_FPU_REGS)) | |
6091 | return -1; | |
6092 | } | |
6093 | /* Fall through */ | |
7ad10968 | 6094 | default: |
25ea693b | 6095 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6096 | return -1; |
6097 | break; | |
6098 | } | |
6099 | break; | |
6100 | } | |
6101 | break; | |
6102 | case 0x0c: | |
0289bdd7 MS |
6103 | /* Insn fldenv. */ |
6104 | if (i386_record_floats (gdbarch, &ir, | |
6105 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6106 | return -1; | |
6107 | break; | |
7ad10968 | 6108 | case 0x0d: |
0289bdd7 MS |
6109 | /* Insn fldcw. */ |
6110 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6111 | return -1; | |
6112 | break; | |
7ad10968 | 6113 | case 0x2c: |
0289bdd7 MS |
6114 | /* Insn frstor. */ |
6115 | if (i386_record_floats (gdbarch, &ir, | |
6116 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6117 | return -1; | |
7ad10968 HZ |
6118 | break; |
6119 | case 0x0e: | |
6120 | if (ir.dflag) | |
6121 | { | |
25ea693b | 6122 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6123 | return -1; |
6124 | } | |
6125 | else | |
6126 | { | |
25ea693b | 6127 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6128 | return -1; |
6129 | } | |
6130 | break; | |
6131 | case 0x0f: | |
6132 | case 0x2f: | |
25ea693b | 6133 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6134 | return -1; |
0289bdd7 MS |
6135 | /* Insn fstp, fbstp. */ |
6136 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6137 | return -1; | |
7ad10968 HZ |
6138 | break; |
6139 | case 0x1f: | |
6140 | case 0x3e: | |
25ea693b | 6141 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6142 | return -1; |
6143 | break; | |
6144 | case 0x2e: | |
6145 | if (ir.dflag) | |
6146 | { | |
25ea693b | 6147 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6148 | return -1; |
955db0c0 | 6149 | addr64 += 28; |
7ad10968 HZ |
6150 | } |
6151 | else | |
6152 | { | |
25ea693b | 6153 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6154 | return -1; |
955db0c0 | 6155 | addr64 += 14; |
7ad10968 | 6156 | } |
25ea693b | 6157 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6158 | return -1; |
0289bdd7 MS |
6159 | /* Insn fsave. */ |
6160 | if (i386_record_floats (gdbarch, &ir, | |
6161 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6162 | return -1; | |
7ad10968 HZ |
6163 | break; |
6164 | case 0x3f: | |
25ea693b | 6165 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6166 | return -1; |
0289bdd7 MS |
6167 | /* Insn fistp. */ |
6168 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6169 | return -1; | |
7ad10968 HZ |
6170 | break; |
6171 | default: | |
6172 | ir.addr -= 2; | |
6173 | opcode = opcode << 8 | ir.modrm; | |
6174 | goto no_support; | |
6175 | break; | |
6176 | } | |
6177 | } | |
0289bdd7 MS |
6178 | /* Opcode is an extension of modR/M byte. */ |
6179 | else | |
6180 | { | |
6181 | switch (opcode) | |
6182 | { | |
6183 | case 0xd8: | |
6184 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6185 | return -1; | |
6186 | break; | |
6187 | case 0xd9: | |
6188 | if (0x0c == (ir.modrm >> 4)) | |
6189 | { | |
6190 | if ((ir.modrm & 0x0f) <= 7) | |
6191 | { | |
6192 | if (i386_record_floats (gdbarch, &ir, | |
6193 | I386_SAVE_FPU_REGS)) | |
6194 | return -1; | |
6195 | } | |
6196 | else | |
6197 | { | |
6198 | if (i386_record_floats (gdbarch, &ir, | |
6199 | I387_ST0_REGNUM (tdep))) | |
6200 | return -1; | |
6201 | /* If only st(0) is changing, then we have already | |
6202 | recorded. */ | |
6203 | if ((ir.modrm & 0x0f) - 0x08) | |
6204 | { | |
6205 | if (i386_record_floats (gdbarch, &ir, | |
6206 | I387_ST0_REGNUM (tdep) + | |
6207 | ((ir.modrm & 0x0f) - 0x08))) | |
6208 | return -1; | |
6209 | } | |
6210 | } | |
6211 | } | |
6212 | else | |
6213 | { | |
6214 | switch (ir.modrm) | |
6215 | { | |
6216 | case 0xe0: | |
6217 | case 0xe1: | |
6218 | case 0xf0: | |
6219 | case 0xf5: | |
6220 | case 0xf8: | |
6221 | case 0xfa: | |
6222 | case 0xfc: | |
6223 | case 0xfe: | |
6224 | case 0xff: | |
6225 | if (i386_record_floats (gdbarch, &ir, | |
6226 | I387_ST0_REGNUM (tdep))) | |
6227 | return -1; | |
6228 | break; | |
6229 | case 0xf1: | |
6230 | case 0xf2: | |
6231 | case 0xf3: | |
6232 | case 0xf4: | |
6233 | case 0xf6: | |
6234 | case 0xf7: | |
6235 | case 0xe8: | |
6236 | case 0xe9: | |
6237 | case 0xea: | |
6238 | case 0xeb: | |
6239 | case 0xec: | |
6240 | case 0xed: | |
6241 | case 0xee: | |
6242 | case 0xf9: | |
6243 | case 0xfb: | |
6244 | if (i386_record_floats (gdbarch, &ir, | |
6245 | I386_SAVE_FPU_REGS)) | |
6246 | return -1; | |
6247 | break; | |
6248 | case 0xfd: | |
6249 | if (i386_record_floats (gdbarch, &ir, | |
6250 | I387_ST0_REGNUM (tdep))) | |
6251 | return -1; | |
6252 | if (i386_record_floats (gdbarch, &ir, | |
6253 | I387_ST0_REGNUM (tdep) + 1)) | |
6254 | return -1; | |
6255 | break; | |
6256 | } | |
6257 | } | |
6258 | break; | |
6259 | case 0xda: | |
6260 | if (0xe9 == ir.modrm) | |
6261 | { | |
6262 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6263 | return -1; | |
6264 | } | |
6265 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6266 | { | |
6267 | if (i386_record_floats (gdbarch, &ir, | |
6268 | I387_ST0_REGNUM (tdep))) | |
6269 | return -1; | |
6270 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6271 | { | |
6272 | if (i386_record_floats (gdbarch, &ir, | |
6273 | I387_ST0_REGNUM (tdep) + | |
6274 | (ir.modrm & 0x0f))) | |
6275 | return -1; | |
6276 | } | |
6277 | else if ((ir.modrm & 0x0f) - 0x08) | |
6278 | { | |
6279 | if (i386_record_floats (gdbarch, &ir, | |
6280 | I387_ST0_REGNUM (tdep) + | |
6281 | ((ir.modrm & 0x0f) - 0x08))) | |
6282 | return -1; | |
6283 | } | |
6284 | } | |
6285 | break; | |
6286 | case 0xdb: | |
6287 | if (0xe3 == ir.modrm) | |
6288 | { | |
6289 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6290 | return -1; | |
6291 | } | |
6292 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6293 | { | |
6294 | if (i386_record_floats (gdbarch, &ir, | |
6295 | I387_ST0_REGNUM (tdep))) | |
6296 | return -1; | |
6297 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6298 | { | |
6299 | if (i386_record_floats (gdbarch, &ir, | |
6300 | I387_ST0_REGNUM (tdep) + | |
6301 | (ir.modrm & 0x0f))) | |
6302 | return -1; | |
6303 | } | |
6304 | else if ((ir.modrm & 0x0f) - 0x08) | |
6305 | { | |
6306 | if (i386_record_floats (gdbarch, &ir, | |
6307 | I387_ST0_REGNUM (tdep) + | |
6308 | ((ir.modrm & 0x0f) - 0x08))) | |
6309 | return -1; | |
6310 | } | |
6311 | } | |
6312 | break; | |
6313 | case 0xdc: | |
6314 | if ((0x0c == ir.modrm >> 4) | |
6315 | || (0x0d == ir.modrm >> 4) | |
6316 | || (0x0f == ir.modrm >> 4)) | |
6317 | { | |
6318 | if ((ir.modrm & 0x0f) <= 7) | |
6319 | { | |
6320 | if (i386_record_floats (gdbarch, &ir, | |
6321 | I387_ST0_REGNUM (tdep) + | |
6322 | (ir.modrm & 0x0f))) | |
6323 | return -1; | |
6324 | } | |
6325 | else | |
6326 | { | |
6327 | if (i386_record_floats (gdbarch, &ir, | |
6328 | I387_ST0_REGNUM (tdep) + | |
6329 | ((ir.modrm & 0x0f) - 0x08))) | |
6330 | return -1; | |
6331 | } | |
6332 | } | |
6333 | break; | |
6334 | case 0xdd: | |
6335 | if (0x0c == ir.modrm >> 4) | |
6336 | { | |
6337 | if (i386_record_floats (gdbarch, &ir, | |
6338 | I387_FTAG_REGNUM (tdep))) | |
6339 | return -1; | |
6340 | } | |
6341 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6342 | { | |
6343 | if ((ir.modrm & 0x0f) <= 7) | |
6344 | { | |
6345 | if (i386_record_floats (gdbarch, &ir, | |
6346 | I387_ST0_REGNUM (tdep) + | |
6347 | (ir.modrm & 0x0f))) | |
6348 | return -1; | |
6349 | } | |
6350 | else | |
6351 | { | |
6352 | if (i386_record_floats (gdbarch, &ir, | |
6353 | I386_SAVE_FPU_REGS)) | |
6354 | return -1; | |
6355 | } | |
6356 | } | |
6357 | break; | |
6358 | case 0xde: | |
6359 | if ((0x0c == ir.modrm >> 4) | |
6360 | || (0x0e == ir.modrm >> 4) | |
6361 | || (0x0f == ir.modrm >> 4) | |
6362 | || (0xd9 == ir.modrm)) | |
6363 | { | |
6364 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6365 | return -1; | |
6366 | } | |
6367 | break; | |
6368 | case 0xdf: | |
6369 | if (0xe0 == ir.modrm) | |
6370 | { | |
25ea693b MM |
6371 | if (record_full_arch_list_add_reg (ir.regcache, |
6372 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6373 | return -1; |
6374 | } | |
6375 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6376 | { | |
6377 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6378 | return -1; | |
6379 | } | |
6380 | break; | |
6381 | } | |
6382 | } | |
7ad10968 | 6383 | break; |
7ad10968 | 6384 | /* string ops */ |
a38bba38 | 6385 | case 0xa4: /* movsS */ |
7ad10968 | 6386 | case 0xa5: |
a38bba38 | 6387 | case 0xaa: /* stosS */ |
7ad10968 | 6388 | case 0xab: |
a38bba38 | 6389 | case 0x6c: /* insS */ |
7ad10968 | 6390 | case 0x6d: |
cf648174 | 6391 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6392 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6393 | &addr); |
6394 | if (addr) | |
cf648174 | 6395 | { |
77d7dc92 HZ |
6396 | ULONGEST es, ds; |
6397 | ||
6398 | if ((opcode & 1) == 0) | |
6399 | ir.ot = OT_BYTE; | |
6400 | else | |
6401 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6402 | regcache_raw_read_unsigned (ir.regcache, |
6403 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6404 | &addr); |
77d7dc92 | 6405 | |
d7877f7e HZ |
6406 | regcache_raw_read_unsigned (ir.regcache, |
6407 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6408 | &es); | |
6409 | regcache_raw_read_unsigned (ir.regcache, | |
6410 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6411 | &ds); | |
6412 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6413 | { |
6414 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6415 | if (record_full_memory_query) |
bb08c432 HZ |
6416 | { |
6417 | int q; | |
6418 | ||
6419 | target_terminal_ours (); | |
6420 | q = yquery (_("\ | |
6421 | Process record ignores the memory change of instruction at address %s\n\ | |
6422 | because it can't get the value of the segment register.\n\ | |
6423 | Do you want to stop the program?"), | |
6424 | paddress (gdbarch, ir.orig_addr)); | |
6425 | target_terminal_inferior (); | |
6426 | if (q) | |
6427 | return -1; | |
6428 | } | |
df61f520 HZ |
6429 | } |
6430 | else | |
6431 | { | |
25ea693b | 6432 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6433 | return -1; |
77d7dc92 HZ |
6434 | } |
6435 | ||
6436 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6437 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6438 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6439 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6440 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6441 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6442 | } |
cf648174 | 6443 | break; |
7ad10968 | 6444 | |
a38bba38 | 6445 | case 0xa6: /* cmpsS */ |
cf648174 | 6446 | case 0xa7: |
25ea693b MM |
6447 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6448 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6449 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6450 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6451 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6452 | break; |
6453 | ||
a38bba38 | 6454 | case 0xac: /* lodsS */ |
7ad10968 | 6455 | case 0xad: |
25ea693b MM |
6456 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6457 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6458 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6459 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6460 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6461 | break; |
6462 | ||
a38bba38 | 6463 | case 0xae: /* scasS */ |
7ad10968 | 6464 | case 0xaf: |
25ea693b | 6465 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6466 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6467 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6468 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6469 | break; |
6470 | ||
a38bba38 | 6471 | case 0x6e: /* outsS */ |
cf648174 | 6472 | case 0x6f: |
25ea693b | 6473 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6474 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6475 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6476 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6477 | break; |
6478 | ||
a38bba38 | 6479 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6480 | case 0xe5: |
6481 | case 0xec: | |
6482 | case 0xed: | |
25ea693b MM |
6483 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6484 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6485 | break; |
6486 | ||
6487 | case 0xe6: | |
6488 | case 0xe7: | |
6489 | case 0xee: | |
6490 | case 0xef: | |
6491 | break; | |
6492 | ||
6493 | /* control */ | |
a38bba38 MS |
6494 | case 0xc2: /* ret im */ |
6495 | case 0xc3: /* ret */ | |
25ea693b MM |
6496 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6497 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6498 | break; |
6499 | ||
a38bba38 MS |
6500 | case 0xca: /* lret im */ |
6501 | case 0xcb: /* lret */ | |
6502 | case 0xcf: /* iret */ | |
25ea693b MM |
6503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6504 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6505 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6506 | break; |
6507 | ||
a38bba38 | 6508 | case 0xe8: /* call im */ |
cf648174 HZ |
6509 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6510 | ir.dflag = 2; | |
6511 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6512 | return -1; | |
7ad10968 HZ |
6513 | break; |
6514 | ||
a38bba38 | 6515 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6516 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6517 | { | |
6518 | ir.addr -= 1; | |
6519 | goto no_support; | |
6520 | } | |
25ea693b | 6521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6522 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6523 | return -1; | |
7ad10968 HZ |
6524 | break; |
6525 | ||
a38bba38 MS |
6526 | case 0xe9: /* jmp im */ |
6527 | case 0xea: /* ljmp im */ | |
6528 | case 0xeb: /* jmp Jb */ | |
6529 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6530 | case 0x71: |
6531 | case 0x72: | |
6532 | case 0x73: | |
6533 | case 0x74: | |
6534 | case 0x75: | |
6535 | case 0x76: | |
6536 | case 0x77: | |
6537 | case 0x78: | |
6538 | case 0x79: | |
6539 | case 0x7a: | |
6540 | case 0x7b: | |
6541 | case 0x7c: | |
6542 | case 0x7d: | |
6543 | case 0x7e: | |
6544 | case 0x7f: | |
a38bba38 | 6545 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6546 | case 0x0f81: |
6547 | case 0x0f82: | |
6548 | case 0x0f83: | |
6549 | case 0x0f84: | |
6550 | case 0x0f85: | |
6551 | case 0x0f86: | |
6552 | case 0x0f87: | |
6553 | case 0x0f88: | |
6554 | case 0x0f89: | |
6555 | case 0x0f8a: | |
6556 | case 0x0f8b: | |
6557 | case 0x0f8c: | |
6558 | case 0x0f8d: | |
6559 | case 0x0f8e: | |
6560 | case 0x0f8f: | |
6561 | break; | |
6562 | ||
a38bba38 | 6563 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6564 | case 0x0f91: |
6565 | case 0x0f92: | |
6566 | case 0x0f93: | |
6567 | case 0x0f94: | |
6568 | case 0x0f95: | |
6569 | case 0x0f96: | |
6570 | case 0x0f97: | |
6571 | case 0x0f98: | |
6572 | case 0x0f99: | |
6573 | case 0x0f9a: | |
6574 | case 0x0f9b: | |
6575 | case 0x0f9c: | |
6576 | case 0x0f9d: | |
6577 | case 0x0f9e: | |
6578 | case 0x0f9f: | |
25ea693b | 6579 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6580 | ir.ot = OT_BYTE; |
6581 | if (i386_record_modrm (&ir)) | |
6582 | return -1; | |
6583 | if (ir.mod == 3) | |
25ea693b MM |
6584 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6585 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6586 | else |
6587 | { | |
6588 | if (i386_record_lea_modrm (&ir)) | |
6589 | return -1; | |
6590 | } | |
6591 | break; | |
6592 | ||
a38bba38 | 6593 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6594 | case 0x0f41: |
6595 | case 0x0f42: | |
6596 | case 0x0f43: | |
6597 | case 0x0f44: | |
6598 | case 0x0f45: | |
6599 | case 0x0f46: | |
6600 | case 0x0f47: | |
6601 | case 0x0f48: | |
6602 | case 0x0f49: | |
6603 | case 0x0f4a: | |
6604 | case 0x0f4b: | |
6605 | case 0x0f4c: | |
6606 | case 0x0f4d: | |
6607 | case 0x0f4e: | |
6608 | case 0x0f4f: | |
6609 | if (i386_record_modrm (&ir)) | |
6610 | return -1; | |
cf648174 | 6611 | ir.reg |= rex_r; |
7ad10968 HZ |
6612 | if (ir.dflag == OT_BYTE) |
6613 | ir.reg &= 0x3; | |
25ea693b | 6614 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6615 | break; |
6616 | ||
6617 | /* flags */ | |
a38bba38 | 6618 | case 0x9c: /* pushf */ |
25ea693b | 6619 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6620 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6621 | ir.dflag = 2; | |
6622 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6623 | return -1; | |
7ad10968 HZ |
6624 | break; |
6625 | ||
a38bba38 | 6626 | case 0x9d: /* popf */ |
25ea693b MM |
6627 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6628 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6629 | break; |
6630 | ||
a38bba38 | 6631 | case 0x9e: /* sahf */ |
cf648174 HZ |
6632 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6633 | { | |
6634 | ir.addr -= 1; | |
6635 | goto no_support; | |
6636 | } | |
d3f323f3 | 6637 | /* FALLTHROUGH */ |
a38bba38 MS |
6638 | case 0xf5: /* cmc */ |
6639 | case 0xf8: /* clc */ | |
6640 | case 0xf9: /* stc */ | |
6641 | case 0xfc: /* cld */ | |
6642 | case 0xfd: /* std */ | |
25ea693b | 6643 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6644 | break; |
6645 | ||
a38bba38 | 6646 | case 0x9f: /* lahf */ |
cf648174 HZ |
6647 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6648 | { | |
6649 | ir.addr -= 1; | |
6650 | goto no_support; | |
6651 | } | |
25ea693b MM |
6652 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6654 | break; |
6655 | ||
6656 | /* bit operations */ | |
a38bba38 | 6657 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6658 | ir.ot = ir.dflag + OT_WORD; |
6659 | if (i386_record_modrm (&ir)) | |
6660 | return -1; | |
6661 | if (ir.reg < 4) | |
6662 | { | |
cf648174 | 6663 | ir.addr -= 2; |
7ad10968 HZ |
6664 | opcode = opcode << 8 | ir.modrm; |
6665 | goto no_support; | |
6666 | } | |
cf648174 | 6667 | if (ir.reg != 4) |
7ad10968 | 6668 | { |
cf648174 | 6669 | if (ir.mod == 3) |
25ea693b | 6670 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6671 | else |
6672 | { | |
cf648174 | 6673 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6674 | return -1; |
6675 | } | |
6676 | } | |
25ea693b | 6677 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6678 | break; |
6679 | ||
a38bba38 | 6680 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6682 | break; |
6683 | ||
a38bba38 MS |
6684 | case 0x0fab: /* bts */ |
6685 | case 0x0fb3: /* btr */ | |
6686 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6687 | ir.ot = ir.dflag + OT_WORD; |
6688 | if (i386_record_modrm (&ir)) | |
6689 | return -1; | |
6690 | if (ir.mod == 3) | |
25ea693b | 6691 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6692 | else |
6693 | { | |
955db0c0 MS |
6694 | uint64_t addr64; |
6695 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6696 | return -1; |
6697 | regcache_raw_read_unsigned (ir.regcache, | |
6698 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6699 | &addr); |
cf648174 HZ |
6700 | switch (ir.dflag) |
6701 | { | |
6702 | case 0: | |
648d0c8b | 6703 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6704 | break; |
6705 | case 1: | |
648d0c8b | 6706 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6707 | break; |
6708 | case 2: | |
648d0c8b | 6709 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6710 | break; |
6711 | } | |
25ea693b | 6712 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6713 | return -1; |
6714 | if (i386_record_lea_modrm (&ir)) | |
6715 | return -1; | |
6716 | } | |
25ea693b | 6717 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6718 | break; |
6719 | ||
a38bba38 MS |
6720 | case 0x0fbc: /* bsf */ |
6721 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6722 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6723 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6724 | break; |
6725 | ||
6726 | /* bcd */ | |
a38bba38 MS |
6727 | case 0x27: /* daa */ |
6728 | case 0x2f: /* das */ | |
6729 | case 0x37: /* aaa */ | |
6730 | case 0x3f: /* aas */ | |
6731 | case 0xd4: /* aam */ | |
6732 | case 0xd5: /* aad */ | |
cf648174 HZ |
6733 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6734 | { | |
6735 | ir.addr -= 1; | |
6736 | goto no_support; | |
6737 | } | |
25ea693b MM |
6738 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6739 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6740 | break; |
6741 | ||
6742 | /* misc */ | |
a38bba38 | 6743 | case 0x90: /* nop */ |
7ad10968 HZ |
6744 | if (prefixes & PREFIX_LOCK) |
6745 | { | |
6746 | ir.addr -= 1; | |
6747 | goto no_support; | |
6748 | } | |
6749 | break; | |
6750 | ||
a38bba38 | 6751 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6752 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6753 | return -1; | |
425b824a | 6754 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6755 | ir.addr++; |
6756 | goto reswitch; | |
7ad10968 HZ |
6757 | break; |
6758 | ||
7ad10968 | 6759 | /* XXX */ |
a38bba38 | 6760 | case 0xcc: /* int3 */ |
a3c4230a | 6761 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6762 | "int3.\n")); |
6763 | ir.addr -= 1; | |
6764 | goto no_support; | |
6765 | break; | |
6766 | ||
7ad10968 | 6767 | /* XXX */ |
a38bba38 | 6768 | case 0xcd: /* int */ |
7ad10968 HZ |
6769 | { |
6770 | int ret; | |
425b824a | 6771 | uint8_t interrupt; |
4ffa4fc7 PA |
6772 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6773 | return -1; | |
7ad10968 | 6774 | ir.addr++; |
425b824a | 6775 | if (interrupt != 0x80 |
a3c4230a | 6776 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6777 | { |
a3c4230a | 6778 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6779 | "instruction int 0x%02x.\n"), |
425b824a | 6780 | interrupt); |
7ad10968 HZ |
6781 | ir.addr -= 2; |
6782 | goto no_support; | |
6783 | } | |
a3c4230a | 6784 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6785 | if (ret) |
6786 | return ret; | |
6787 | } | |
6788 | break; | |
6789 | ||
7ad10968 | 6790 | /* XXX */ |
a38bba38 | 6791 | case 0xce: /* into */ |
a3c4230a | 6792 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6793 | "instruction into.\n")); |
6794 | ir.addr -= 1; | |
6795 | goto no_support; | |
6796 | break; | |
6797 | ||
a38bba38 MS |
6798 | case 0xfa: /* cli */ |
6799 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6800 | break; |
6801 | ||
a38bba38 | 6802 | case 0x62: /* bound */ |
a3c4230a | 6803 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6804 | "instruction bound.\n")); |
6805 | ir.addr -= 1; | |
6806 | goto no_support; | |
6807 | break; | |
6808 | ||
a38bba38 | 6809 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6810 | case 0x0fc9: |
6811 | case 0x0fca: | |
6812 | case 0x0fcb: | |
6813 | case 0x0fcc: | |
6814 | case 0x0fcd: | |
6815 | case 0x0fce: | |
6816 | case 0x0fcf: | |
25ea693b | 6817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6818 | break; |
6819 | ||
a38bba38 | 6820 | case 0xd6: /* salc */ |
cf648174 HZ |
6821 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6822 | { | |
6823 | ir.addr -= 1; | |
6824 | goto no_support; | |
6825 | } | |
25ea693b MM |
6826 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6827 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6828 | break; |
6829 | ||
a38bba38 MS |
6830 | case 0xe0: /* loopnz */ |
6831 | case 0xe1: /* loopz */ | |
6832 | case 0xe2: /* loop */ | |
6833 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6834 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6835 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6836 | break; |
6837 | ||
a38bba38 | 6838 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6839 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6840 | "instruction wrmsr.\n")); |
6841 | ir.addr -= 2; | |
6842 | goto no_support; | |
6843 | break; | |
6844 | ||
a38bba38 | 6845 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6846 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6847 | "instruction rdmsr.\n")); |
6848 | ir.addr -= 2; | |
6849 | goto no_support; | |
6850 | break; | |
6851 | ||
a38bba38 | 6852 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6853 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6854 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6855 | break; |
6856 | ||
a38bba38 | 6857 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6858 | { |
6859 | int ret; | |
cf648174 HZ |
6860 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6861 | { | |
6862 | ir.addr -= 2; | |
6863 | goto no_support; | |
6864 | } | |
a3c4230a | 6865 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6866 | { |
a3c4230a | 6867 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6868 | "instruction sysenter.\n")); |
6869 | ir.addr -= 2; | |
6870 | goto no_support; | |
6871 | } | |
a3c4230a | 6872 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6873 | if (ret) |
6874 | return ret; | |
6875 | } | |
6876 | break; | |
6877 | ||
a38bba38 | 6878 | case 0x0f35: /* sysexit */ |
a3c4230a | 6879 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6880 | "instruction sysexit.\n")); |
6881 | ir.addr -= 2; | |
6882 | goto no_support; | |
6883 | break; | |
6884 | ||
a38bba38 | 6885 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6886 | { |
6887 | int ret; | |
a3c4230a | 6888 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6889 | { |
a3c4230a | 6890 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6891 | "instruction syscall.\n")); |
6892 | ir.addr -= 2; | |
6893 | goto no_support; | |
6894 | } | |
a3c4230a | 6895 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6896 | if (ret) |
6897 | return ret; | |
6898 | } | |
6899 | break; | |
6900 | ||
a38bba38 | 6901 | case 0x0f07: /* sysret */ |
a3c4230a | 6902 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6903 | "instruction sysret.\n")); |
6904 | ir.addr -= 2; | |
6905 | goto no_support; | |
6906 | break; | |
6907 | ||
a38bba38 | 6908 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6909 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6910 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6911 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6912 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6913 | break; |
6914 | ||
a38bba38 | 6915 | case 0xf4: /* hlt */ |
a3c4230a | 6916 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6917 | "instruction hlt.\n")); |
6918 | ir.addr -= 1; | |
6919 | goto no_support; | |
6920 | break; | |
6921 | ||
6922 | case 0x0f00: | |
6923 | if (i386_record_modrm (&ir)) | |
6924 | return -1; | |
6925 | switch (ir.reg) | |
6926 | { | |
a38bba38 MS |
6927 | case 0: /* sldt */ |
6928 | case 1: /* str */ | |
7ad10968 | 6929 | if (ir.mod == 3) |
25ea693b | 6930 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6931 | else |
6932 | { | |
6933 | ir.ot = OT_WORD; | |
6934 | if (i386_record_lea_modrm (&ir)) | |
6935 | return -1; | |
6936 | } | |
6937 | break; | |
a38bba38 MS |
6938 | case 2: /* lldt */ |
6939 | case 3: /* ltr */ | |
7ad10968 | 6940 | break; |
a38bba38 MS |
6941 | case 4: /* verr */ |
6942 | case 5: /* verw */ | |
25ea693b | 6943 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6944 | break; |
6945 | default: | |
6946 | ir.addr -= 3; | |
6947 | opcode = opcode << 8 | ir.modrm; | |
6948 | goto no_support; | |
6949 | break; | |
6950 | } | |
6951 | break; | |
6952 | ||
6953 | case 0x0f01: | |
6954 | if (i386_record_modrm (&ir)) | |
6955 | return -1; | |
6956 | switch (ir.reg) | |
6957 | { | |
a38bba38 | 6958 | case 0: /* sgdt */ |
7ad10968 | 6959 | { |
955db0c0 | 6960 | uint64_t addr64; |
7ad10968 HZ |
6961 | |
6962 | if (ir.mod == 3) | |
6963 | { | |
6964 | ir.addr -= 3; | |
6965 | opcode = opcode << 8 | ir.modrm; | |
6966 | goto no_support; | |
6967 | } | |
d7877f7e | 6968 | if (ir.override >= 0) |
7ad10968 | 6969 | { |
25ea693b | 6970 | if (record_full_memory_query) |
bb08c432 HZ |
6971 | { |
6972 | int q; | |
6973 | ||
6974 | target_terminal_ours (); | |
6975 | q = yquery (_("\ | |
6976 | Process record ignores the memory change of instruction at address %s\n\ | |
6977 | because it can't get the value of the segment register.\n\ | |
6978 | Do you want to stop the program?"), | |
6979 | paddress (gdbarch, ir.orig_addr)); | |
6980 | target_terminal_inferior (); | |
6981 | if (q) | |
6982 | return -1; | |
6983 | } | |
7ad10968 HZ |
6984 | } |
6985 | else | |
6986 | { | |
955db0c0 | 6987 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6988 | return -1; |
25ea693b | 6989 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6990 | return -1; |
955db0c0 | 6991 | addr64 += 2; |
cf648174 HZ |
6992 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6993 | { | |
25ea693b | 6994 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6995 | return -1; |
6996 | } | |
6997 | else | |
6998 | { | |
25ea693b | 6999 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7000 | return -1; |
7001 | } | |
7ad10968 HZ |
7002 | } |
7003 | } | |
7004 | break; | |
7005 | case 1: | |
7006 | if (ir.mod == 3) | |
7007 | { | |
7008 | switch (ir.rm) | |
7009 | { | |
a38bba38 | 7010 | case 0: /* monitor */ |
7ad10968 | 7011 | break; |
a38bba38 | 7012 | case 1: /* mwait */ |
25ea693b | 7013 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7014 | break; |
7015 | default: | |
7016 | ir.addr -= 3; | |
7017 | opcode = opcode << 8 | ir.modrm; | |
7018 | goto no_support; | |
7019 | break; | |
7020 | } | |
7021 | } | |
7022 | else | |
7023 | { | |
7024 | /* sidt */ | |
d7877f7e | 7025 | if (ir.override >= 0) |
7ad10968 | 7026 | { |
25ea693b | 7027 | if (record_full_memory_query) |
bb08c432 HZ |
7028 | { |
7029 | int q; | |
7030 | ||
7031 | target_terminal_ours (); | |
7032 | q = yquery (_("\ | |
7033 | Process record ignores the memory change of instruction at address %s\n\ | |
7034 | because it can't get the value of the segment register.\n\ | |
7035 | Do you want to stop the program?"), | |
7036 | paddress (gdbarch, ir.orig_addr)); | |
7037 | target_terminal_inferior (); | |
7038 | if (q) | |
7039 | return -1; | |
7040 | } | |
7ad10968 HZ |
7041 | } |
7042 | else | |
7043 | { | |
955db0c0 | 7044 | uint64_t addr64; |
7ad10968 | 7045 | |
955db0c0 | 7046 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7047 | return -1; |
25ea693b | 7048 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7049 | return -1; |
955db0c0 | 7050 | addr64 += 2; |
cf648174 HZ |
7051 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7052 | { | |
25ea693b | 7053 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7054 | return -1; |
7055 | } | |
7056 | else | |
7057 | { | |
25ea693b | 7058 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7059 | return -1; |
7060 | } | |
7ad10968 HZ |
7061 | } |
7062 | } | |
7063 | break; | |
a38bba38 | 7064 | case 2: /* lgdt */ |
3800e645 MS |
7065 | if (ir.mod == 3) |
7066 | { | |
7067 | /* xgetbv */ | |
7068 | if (ir.rm == 0) | |
7069 | { | |
25ea693b MM |
7070 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7071 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7072 | break; |
7073 | } | |
7074 | /* xsetbv */ | |
7075 | else if (ir.rm == 1) | |
7076 | break; | |
7077 | } | |
a38bba38 | 7078 | case 3: /* lidt */ |
7ad10968 HZ |
7079 | if (ir.mod == 3) |
7080 | { | |
7081 | ir.addr -= 3; | |
7082 | opcode = opcode << 8 | ir.modrm; | |
7083 | goto no_support; | |
7084 | } | |
7085 | break; | |
a38bba38 | 7086 | case 4: /* smsw */ |
7ad10968 HZ |
7087 | if (ir.mod == 3) |
7088 | { | |
25ea693b | 7089 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7090 | return -1; |
7091 | } | |
7092 | else | |
7093 | { | |
7094 | ir.ot = OT_WORD; | |
7095 | if (i386_record_lea_modrm (&ir)) | |
7096 | return -1; | |
7097 | } | |
25ea693b | 7098 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7099 | break; |
a38bba38 | 7100 | case 6: /* lmsw */ |
25ea693b | 7101 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7102 | break; |
a38bba38 | 7103 | case 7: /* invlpg */ |
cf648174 HZ |
7104 | if (ir.mod == 3) |
7105 | { | |
7106 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7107 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7108 | else |
7109 | { | |
7110 | ir.addr -= 3; | |
7111 | opcode = opcode << 8 | ir.modrm; | |
7112 | goto no_support; | |
7113 | } | |
7114 | } | |
7115 | else | |
25ea693b | 7116 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7117 | break; |
7118 | default: | |
7119 | ir.addr -= 3; | |
7120 | opcode = opcode << 8 | ir.modrm; | |
7121 | goto no_support; | |
7ad10968 HZ |
7122 | break; |
7123 | } | |
7124 | break; | |
7125 | ||
a38bba38 MS |
7126 | case 0x0f08: /* invd */ |
7127 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7128 | break; |
7129 | ||
a38bba38 | 7130 | case 0x63: /* arpl */ |
7ad10968 HZ |
7131 | if (i386_record_modrm (&ir)) |
7132 | return -1; | |
cf648174 HZ |
7133 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7134 | { | |
25ea693b MM |
7135 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7136 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7137 | } |
7ad10968 | 7138 | else |
cf648174 HZ |
7139 | { |
7140 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7141 | if (i386_record_lea_modrm (&ir)) | |
7142 | return -1; | |
7143 | } | |
7144 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7145 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7146 | break; |
7147 | ||
a38bba38 MS |
7148 | case 0x0f02: /* lar */ |
7149 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7150 | if (i386_record_modrm (&ir)) |
7151 | return -1; | |
25ea693b MM |
7152 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7153 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7154 | break; |
7155 | ||
7156 | case 0x0f18: | |
cf648174 HZ |
7157 | if (i386_record_modrm (&ir)) |
7158 | return -1; | |
7159 | if (ir.mod == 3 && ir.reg == 3) | |
7160 | { | |
7161 | ir.addr -= 3; | |
7162 | opcode = opcode << 8 | ir.modrm; | |
7163 | goto no_support; | |
7164 | } | |
7ad10968 HZ |
7165 | break; |
7166 | ||
7ad10968 HZ |
7167 | case 0x0f19: |
7168 | case 0x0f1a: | |
7169 | case 0x0f1b: | |
7170 | case 0x0f1c: | |
7171 | case 0x0f1d: | |
7172 | case 0x0f1e: | |
7173 | case 0x0f1f: | |
a38bba38 | 7174 | /* nop (multi byte) */ |
7ad10968 HZ |
7175 | break; |
7176 | ||
a38bba38 MS |
7177 | case 0x0f20: /* mov reg, crN */ |
7178 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7179 | if (i386_record_modrm (&ir)) |
7180 | return -1; | |
7181 | if ((ir.modrm & 0xc0) != 0xc0) | |
7182 | { | |
cf648174 | 7183 | ir.addr -= 3; |
7ad10968 HZ |
7184 | opcode = opcode << 8 | ir.modrm; |
7185 | goto no_support; | |
7186 | } | |
7187 | switch (ir.reg) | |
7188 | { | |
7189 | case 0: | |
7190 | case 2: | |
7191 | case 3: | |
7192 | case 4: | |
7193 | case 8: | |
7194 | if (opcode & 2) | |
25ea693b | 7195 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7196 | else |
25ea693b | 7197 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7198 | break; |
7199 | default: | |
cf648174 | 7200 | ir.addr -= 3; |
7ad10968 HZ |
7201 | opcode = opcode << 8 | ir.modrm; |
7202 | goto no_support; | |
7203 | break; | |
7204 | } | |
7205 | break; | |
7206 | ||
a38bba38 MS |
7207 | case 0x0f21: /* mov reg, drN */ |
7208 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7209 | if (i386_record_modrm (&ir)) |
7210 | return -1; | |
7211 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7212 | || ir.reg == 5 || ir.reg >= 8) | |
7213 | { | |
cf648174 | 7214 | ir.addr -= 3; |
7ad10968 HZ |
7215 | opcode = opcode << 8 | ir.modrm; |
7216 | goto no_support; | |
7217 | } | |
7218 | if (opcode & 2) | |
25ea693b | 7219 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7220 | else |
25ea693b | 7221 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7222 | break; |
7223 | ||
a38bba38 | 7224 | case 0x0f06: /* clts */ |
25ea693b | 7225 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7226 | break; |
7227 | ||
a3c4230a HZ |
7228 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7229 | ||
7230 | case 0x0f0d: /* 3DNow! prefetch */ | |
7231 | break; | |
7232 | ||
7233 | case 0x0f0e: /* 3DNow! femms */ | |
7234 | case 0x0f77: /* emms */ | |
7235 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7236 | goto no_support; | |
25ea693b | 7237 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7238 | break; |
7239 | ||
7240 | case 0x0f0f: /* 3DNow! data */ | |
7241 | if (i386_record_modrm (&ir)) | |
7242 | return -1; | |
4ffa4fc7 PA |
7243 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7244 | return -1; | |
a3c4230a HZ |
7245 | ir.addr++; |
7246 | switch (opcode8) | |
7247 | { | |
7248 | case 0x0c: /* 3DNow! pi2fw */ | |
7249 | case 0x0d: /* 3DNow! pi2fd */ | |
7250 | case 0x1c: /* 3DNow! pf2iw */ | |
7251 | case 0x1d: /* 3DNow! pf2id */ | |
7252 | case 0x8a: /* 3DNow! pfnacc */ | |
7253 | case 0x8e: /* 3DNow! pfpnacc */ | |
7254 | case 0x90: /* 3DNow! pfcmpge */ | |
7255 | case 0x94: /* 3DNow! pfmin */ | |
7256 | case 0x96: /* 3DNow! pfrcp */ | |
7257 | case 0x97: /* 3DNow! pfrsqrt */ | |
7258 | case 0x9a: /* 3DNow! pfsub */ | |
7259 | case 0x9e: /* 3DNow! pfadd */ | |
7260 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7261 | case 0xa4: /* 3DNow! pfmax */ | |
7262 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7263 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7264 | case 0xaa: /* 3DNow! pfsubr */ | |
7265 | case 0xae: /* 3DNow! pfacc */ | |
7266 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7267 | case 0xb4: /* 3DNow! pfmul */ | |
7268 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7269 | case 0xb7: /* 3DNow! pmulhrw */ | |
7270 | case 0xbb: /* 3DNow! pswapd */ | |
7271 | case 0xbf: /* 3DNow! pavgusb */ | |
7272 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7273 | goto no_support_3dnow_data; | |
25ea693b | 7274 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7275 | break; |
7276 | ||
7277 | default: | |
7278 | no_support_3dnow_data: | |
7279 | opcode = (opcode << 8) | opcode8; | |
7280 | goto no_support; | |
7281 | break; | |
7282 | } | |
7283 | break; | |
7284 | ||
7285 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7286 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7287 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7288 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7289 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7290 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7291 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7292 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7293 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7294 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7295 | break; |
7296 | ||
7297 | case 0x0fae: | |
7298 | if (i386_record_modrm (&ir)) | |
7299 | return -1; | |
7300 | switch(ir.reg) | |
7301 | { | |
7302 | case 0: /* fxsave */ | |
7303 | { | |
7304 | uint64_t tmpu64; | |
7305 | ||
25ea693b | 7306 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7307 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7308 | return -1; | |
25ea693b | 7309 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7310 | return -1; |
7311 | } | |
7312 | break; | |
7313 | ||
7314 | case 1: /* fxrstor */ | |
7315 | { | |
7316 | int i; | |
7317 | ||
25ea693b | 7318 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7319 | |
7320 | for (i = I387_MM0_REGNUM (tdep); | |
7321 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7322 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7323 | |
7324 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7325 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7326 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7327 | |
7328 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7329 | record_full_arch_list_add_reg (ir.regcache, |
7330 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7331 | |
7332 | for (i = I387_ST0_REGNUM (tdep); | |
7333 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7334 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7335 | |
7336 | for (i = I387_FCTRL_REGNUM (tdep); | |
7337 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7338 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7339 | } |
7340 | break; | |
7341 | ||
7342 | case 2: /* ldmxcsr */ | |
7343 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7344 | goto no_support; | |
25ea693b | 7345 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7346 | break; |
7347 | ||
7348 | case 3: /* stmxcsr */ | |
7349 | ir.ot = OT_LONG; | |
7350 | if (i386_record_lea_modrm (&ir)) | |
7351 | return -1; | |
7352 | break; | |
7353 | ||
7354 | case 5: /* lfence */ | |
7355 | case 6: /* mfence */ | |
7356 | case 7: /* sfence clflush */ | |
7357 | break; | |
7358 | ||
7359 | default: | |
7360 | opcode = (opcode << 8) | ir.modrm; | |
7361 | goto no_support; | |
7362 | break; | |
7363 | } | |
7364 | break; | |
7365 | ||
7366 | case 0x0fc3: /* movnti */ | |
7367 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7368 | if (i386_record_modrm (&ir)) | |
7369 | return -1; | |
7370 | if (ir.mod == 3) | |
7371 | goto no_support; | |
7372 | ir.reg |= rex_r; | |
7373 | if (i386_record_lea_modrm (&ir)) | |
7374 | return -1; | |
7375 | break; | |
7376 | ||
7377 | /* Add prefix to opcode. */ | |
7378 | case 0x0f10: | |
7379 | case 0x0f11: | |
7380 | case 0x0f12: | |
7381 | case 0x0f13: | |
7382 | case 0x0f14: | |
7383 | case 0x0f15: | |
7384 | case 0x0f16: | |
7385 | case 0x0f17: | |
7386 | case 0x0f28: | |
7387 | case 0x0f29: | |
7388 | case 0x0f2a: | |
7389 | case 0x0f2b: | |
7390 | case 0x0f2c: | |
7391 | case 0x0f2d: | |
7392 | case 0x0f2e: | |
7393 | case 0x0f2f: | |
7394 | case 0x0f38: | |
7395 | case 0x0f39: | |
7396 | case 0x0f3a: | |
7397 | case 0x0f50: | |
7398 | case 0x0f51: | |
7399 | case 0x0f52: | |
7400 | case 0x0f53: | |
7401 | case 0x0f54: | |
7402 | case 0x0f55: | |
7403 | case 0x0f56: | |
7404 | case 0x0f57: | |
7405 | case 0x0f58: | |
7406 | case 0x0f59: | |
7407 | case 0x0f5a: | |
7408 | case 0x0f5b: | |
7409 | case 0x0f5c: | |
7410 | case 0x0f5d: | |
7411 | case 0x0f5e: | |
7412 | case 0x0f5f: | |
7413 | case 0x0f60: | |
7414 | case 0x0f61: | |
7415 | case 0x0f62: | |
7416 | case 0x0f63: | |
7417 | case 0x0f64: | |
7418 | case 0x0f65: | |
7419 | case 0x0f66: | |
7420 | case 0x0f67: | |
7421 | case 0x0f68: | |
7422 | case 0x0f69: | |
7423 | case 0x0f6a: | |
7424 | case 0x0f6b: | |
7425 | case 0x0f6c: | |
7426 | case 0x0f6d: | |
7427 | case 0x0f6e: | |
7428 | case 0x0f6f: | |
7429 | case 0x0f70: | |
7430 | case 0x0f71: | |
7431 | case 0x0f72: | |
7432 | case 0x0f73: | |
7433 | case 0x0f74: | |
7434 | case 0x0f75: | |
7435 | case 0x0f76: | |
7436 | case 0x0f7c: | |
7437 | case 0x0f7d: | |
7438 | case 0x0f7e: | |
7439 | case 0x0f7f: | |
7440 | case 0x0fb8: | |
7441 | case 0x0fc2: | |
7442 | case 0x0fc4: | |
7443 | case 0x0fc5: | |
7444 | case 0x0fc6: | |
7445 | case 0x0fd0: | |
7446 | case 0x0fd1: | |
7447 | case 0x0fd2: | |
7448 | case 0x0fd3: | |
7449 | case 0x0fd4: | |
7450 | case 0x0fd5: | |
7451 | case 0x0fd6: | |
7452 | case 0x0fd7: | |
7453 | case 0x0fd8: | |
7454 | case 0x0fd9: | |
7455 | case 0x0fda: | |
7456 | case 0x0fdb: | |
7457 | case 0x0fdc: | |
7458 | case 0x0fdd: | |
7459 | case 0x0fde: | |
7460 | case 0x0fdf: | |
7461 | case 0x0fe0: | |
7462 | case 0x0fe1: | |
7463 | case 0x0fe2: | |
7464 | case 0x0fe3: | |
7465 | case 0x0fe4: | |
7466 | case 0x0fe5: | |
7467 | case 0x0fe6: | |
7468 | case 0x0fe7: | |
7469 | case 0x0fe8: | |
7470 | case 0x0fe9: | |
7471 | case 0x0fea: | |
7472 | case 0x0feb: | |
7473 | case 0x0fec: | |
7474 | case 0x0fed: | |
7475 | case 0x0fee: | |
7476 | case 0x0fef: | |
7477 | case 0x0ff0: | |
7478 | case 0x0ff1: | |
7479 | case 0x0ff2: | |
7480 | case 0x0ff3: | |
7481 | case 0x0ff4: | |
7482 | case 0x0ff5: | |
7483 | case 0x0ff6: | |
7484 | case 0x0ff7: | |
7485 | case 0x0ff8: | |
7486 | case 0x0ff9: | |
7487 | case 0x0ffa: | |
7488 | case 0x0ffb: | |
7489 | case 0x0ffc: | |
7490 | case 0x0ffd: | |
7491 | case 0x0ffe: | |
f9fda3f5 L |
7492 | /* Mask out PREFIX_ADDR. */ |
7493 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7494 | { |
7495 | case PREFIX_REPNZ: | |
7496 | opcode |= 0xf20000; | |
7497 | break; | |
7498 | case PREFIX_DATA: | |
7499 | opcode |= 0x660000; | |
7500 | break; | |
7501 | case PREFIX_REPZ: | |
7502 | opcode |= 0xf30000; | |
7503 | break; | |
7504 | } | |
7505 | reswitch_prefix_add: | |
7506 | switch (opcode) | |
7507 | { | |
7508 | case 0x0f38: | |
7509 | case 0x660f38: | |
7510 | case 0xf20f38: | |
7511 | case 0x0f3a: | |
7512 | case 0x660f3a: | |
4ffa4fc7 PA |
7513 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7514 | return -1; | |
a3c4230a HZ |
7515 | ir.addr++; |
7516 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7517 | goto reswitch_prefix_add; | |
7518 | break; | |
7519 | ||
7520 | case 0x0f10: /* movups */ | |
7521 | case 0x660f10: /* movupd */ | |
7522 | case 0xf30f10: /* movss */ | |
7523 | case 0xf20f10: /* movsd */ | |
7524 | case 0x0f12: /* movlps */ | |
7525 | case 0x660f12: /* movlpd */ | |
7526 | case 0xf30f12: /* movsldup */ | |
7527 | case 0xf20f12: /* movddup */ | |
7528 | case 0x0f14: /* unpcklps */ | |
7529 | case 0x660f14: /* unpcklpd */ | |
7530 | case 0x0f15: /* unpckhps */ | |
7531 | case 0x660f15: /* unpckhpd */ | |
7532 | case 0x0f16: /* movhps */ | |
7533 | case 0x660f16: /* movhpd */ | |
7534 | case 0xf30f16: /* movshdup */ | |
7535 | case 0x0f28: /* movaps */ | |
7536 | case 0x660f28: /* movapd */ | |
7537 | case 0x0f2a: /* cvtpi2ps */ | |
7538 | case 0x660f2a: /* cvtpi2pd */ | |
7539 | case 0xf30f2a: /* cvtsi2ss */ | |
7540 | case 0xf20f2a: /* cvtsi2sd */ | |
7541 | case 0x0f2c: /* cvttps2pi */ | |
7542 | case 0x660f2c: /* cvttpd2pi */ | |
7543 | case 0x0f2d: /* cvtps2pi */ | |
7544 | case 0x660f2d: /* cvtpd2pi */ | |
7545 | case 0x660f3800: /* pshufb */ | |
7546 | case 0x660f3801: /* phaddw */ | |
7547 | case 0x660f3802: /* phaddd */ | |
7548 | case 0x660f3803: /* phaddsw */ | |
7549 | case 0x660f3804: /* pmaddubsw */ | |
7550 | case 0x660f3805: /* phsubw */ | |
7551 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7552 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7553 | case 0x660f3808: /* psignb */ |
7554 | case 0x660f3809: /* psignw */ | |
7555 | case 0x660f380a: /* psignd */ | |
7556 | case 0x660f380b: /* pmulhrsw */ | |
7557 | case 0x660f3810: /* pblendvb */ | |
7558 | case 0x660f3814: /* blendvps */ | |
7559 | case 0x660f3815: /* blendvpd */ | |
7560 | case 0x660f381c: /* pabsb */ | |
7561 | case 0x660f381d: /* pabsw */ | |
7562 | case 0x660f381e: /* pabsd */ | |
7563 | case 0x660f3820: /* pmovsxbw */ | |
7564 | case 0x660f3821: /* pmovsxbd */ | |
7565 | case 0x660f3822: /* pmovsxbq */ | |
7566 | case 0x660f3823: /* pmovsxwd */ | |
7567 | case 0x660f3824: /* pmovsxwq */ | |
7568 | case 0x660f3825: /* pmovsxdq */ | |
7569 | case 0x660f3828: /* pmuldq */ | |
7570 | case 0x660f3829: /* pcmpeqq */ | |
7571 | case 0x660f382a: /* movntdqa */ | |
7572 | case 0x660f3a08: /* roundps */ | |
7573 | case 0x660f3a09: /* roundpd */ | |
7574 | case 0x660f3a0a: /* roundss */ | |
7575 | case 0x660f3a0b: /* roundsd */ | |
7576 | case 0x660f3a0c: /* blendps */ | |
7577 | case 0x660f3a0d: /* blendpd */ | |
7578 | case 0x660f3a0e: /* pblendw */ | |
7579 | case 0x660f3a0f: /* palignr */ | |
7580 | case 0x660f3a20: /* pinsrb */ | |
7581 | case 0x660f3a21: /* insertps */ | |
7582 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7583 | case 0x660f3a40: /* dpps */ | |
7584 | case 0x660f3a41: /* dppd */ | |
7585 | case 0x660f3a42: /* mpsadbw */ | |
7586 | case 0x660f3a60: /* pcmpestrm */ | |
7587 | case 0x660f3a61: /* pcmpestri */ | |
7588 | case 0x660f3a62: /* pcmpistrm */ | |
7589 | case 0x660f3a63: /* pcmpistri */ | |
7590 | case 0x0f51: /* sqrtps */ | |
7591 | case 0x660f51: /* sqrtpd */ | |
7592 | case 0xf20f51: /* sqrtsd */ | |
7593 | case 0xf30f51: /* sqrtss */ | |
7594 | case 0x0f52: /* rsqrtps */ | |
7595 | case 0xf30f52: /* rsqrtss */ | |
7596 | case 0x0f53: /* rcpps */ | |
7597 | case 0xf30f53: /* rcpss */ | |
7598 | case 0x0f54: /* andps */ | |
7599 | case 0x660f54: /* andpd */ | |
7600 | case 0x0f55: /* andnps */ | |
7601 | case 0x660f55: /* andnpd */ | |
7602 | case 0x0f56: /* orps */ | |
7603 | case 0x660f56: /* orpd */ | |
7604 | case 0x0f57: /* xorps */ | |
7605 | case 0x660f57: /* xorpd */ | |
7606 | case 0x0f58: /* addps */ | |
7607 | case 0x660f58: /* addpd */ | |
7608 | case 0xf20f58: /* addsd */ | |
7609 | case 0xf30f58: /* addss */ | |
7610 | case 0x0f59: /* mulps */ | |
7611 | case 0x660f59: /* mulpd */ | |
7612 | case 0xf20f59: /* mulsd */ | |
7613 | case 0xf30f59: /* mulss */ | |
7614 | case 0x0f5a: /* cvtps2pd */ | |
7615 | case 0x660f5a: /* cvtpd2ps */ | |
7616 | case 0xf20f5a: /* cvtsd2ss */ | |
7617 | case 0xf30f5a: /* cvtss2sd */ | |
7618 | case 0x0f5b: /* cvtdq2ps */ | |
7619 | case 0x660f5b: /* cvtps2dq */ | |
7620 | case 0xf30f5b: /* cvttps2dq */ | |
7621 | case 0x0f5c: /* subps */ | |
7622 | case 0x660f5c: /* subpd */ | |
7623 | case 0xf20f5c: /* subsd */ | |
7624 | case 0xf30f5c: /* subss */ | |
7625 | case 0x0f5d: /* minps */ | |
7626 | case 0x660f5d: /* minpd */ | |
7627 | case 0xf20f5d: /* minsd */ | |
7628 | case 0xf30f5d: /* minss */ | |
7629 | case 0x0f5e: /* divps */ | |
7630 | case 0x660f5e: /* divpd */ | |
7631 | case 0xf20f5e: /* divsd */ | |
7632 | case 0xf30f5e: /* divss */ | |
7633 | case 0x0f5f: /* maxps */ | |
7634 | case 0x660f5f: /* maxpd */ | |
7635 | case 0xf20f5f: /* maxsd */ | |
7636 | case 0xf30f5f: /* maxss */ | |
7637 | case 0x660f60: /* punpcklbw */ | |
7638 | case 0x660f61: /* punpcklwd */ | |
7639 | case 0x660f62: /* punpckldq */ | |
7640 | case 0x660f63: /* packsswb */ | |
7641 | case 0x660f64: /* pcmpgtb */ | |
7642 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7643 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7644 | case 0x660f67: /* packuswb */ |
7645 | case 0x660f68: /* punpckhbw */ | |
7646 | case 0x660f69: /* punpckhwd */ | |
7647 | case 0x660f6a: /* punpckhdq */ | |
7648 | case 0x660f6b: /* packssdw */ | |
7649 | case 0x660f6c: /* punpcklqdq */ | |
7650 | case 0x660f6d: /* punpckhqdq */ | |
7651 | case 0x660f6e: /* movd */ | |
7652 | case 0x660f6f: /* movdqa */ | |
7653 | case 0xf30f6f: /* movdqu */ | |
7654 | case 0x660f70: /* pshufd */ | |
7655 | case 0xf20f70: /* pshuflw */ | |
7656 | case 0xf30f70: /* pshufhw */ | |
7657 | case 0x660f74: /* pcmpeqb */ | |
7658 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7659 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7660 | case 0x660f7c: /* haddpd */ |
7661 | case 0xf20f7c: /* haddps */ | |
7662 | case 0x660f7d: /* hsubpd */ | |
7663 | case 0xf20f7d: /* hsubps */ | |
7664 | case 0xf30f7e: /* movq */ | |
7665 | case 0x0fc2: /* cmpps */ | |
7666 | case 0x660fc2: /* cmppd */ | |
7667 | case 0xf20fc2: /* cmpsd */ | |
7668 | case 0xf30fc2: /* cmpss */ | |
7669 | case 0x660fc4: /* pinsrw */ | |
7670 | case 0x0fc6: /* shufps */ | |
7671 | case 0x660fc6: /* shufpd */ | |
7672 | case 0x660fd0: /* addsubpd */ | |
7673 | case 0xf20fd0: /* addsubps */ | |
7674 | case 0x660fd1: /* psrlw */ | |
7675 | case 0x660fd2: /* psrld */ | |
7676 | case 0x660fd3: /* psrlq */ | |
7677 | case 0x660fd4: /* paddq */ | |
7678 | case 0x660fd5: /* pmullw */ | |
7679 | case 0xf30fd6: /* movq2dq */ | |
7680 | case 0x660fd8: /* psubusb */ | |
7681 | case 0x660fd9: /* psubusw */ | |
7682 | case 0x660fda: /* pminub */ | |
7683 | case 0x660fdb: /* pand */ | |
7684 | case 0x660fdc: /* paddusb */ | |
7685 | case 0x660fdd: /* paddusw */ | |
7686 | case 0x660fde: /* pmaxub */ | |
7687 | case 0x660fdf: /* pandn */ | |
7688 | case 0x660fe0: /* pavgb */ | |
7689 | case 0x660fe1: /* psraw */ | |
7690 | case 0x660fe2: /* psrad */ | |
7691 | case 0x660fe3: /* pavgw */ | |
7692 | case 0x660fe4: /* pmulhuw */ | |
7693 | case 0x660fe5: /* pmulhw */ | |
7694 | case 0x660fe6: /* cvttpd2dq */ | |
7695 | case 0xf20fe6: /* cvtpd2dq */ | |
7696 | case 0xf30fe6: /* cvtdq2pd */ | |
7697 | case 0x660fe8: /* psubsb */ | |
7698 | case 0x660fe9: /* psubsw */ | |
7699 | case 0x660fea: /* pminsw */ | |
7700 | case 0x660feb: /* por */ | |
7701 | case 0x660fec: /* paddsb */ | |
7702 | case 0x660fed: /* paddsw */ | |
7703 | case 0x660fee: /* pmaxsw */ | |
7704 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7705 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7706 | case 0x660ff1: /* psllw */ |
7707 | case 0x660ff2: /* pslld */ | |
7708 | case 0x660ff3: /* psllq */ | |
7709 | case 0x660ff4: /* pmuludq */ | |
7710 | case 0x660ff5: /* pmaddwd */ | |
7711 | case 0x660ff6: /* psadbw */ | |
7712 | case 0x660ff8: /* psubb */ | |
7713 | case 0x660ff9: /* psubw */ | |
56d2815c | 7714 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7715 | case 0x660ffb: /* psubq */ |
7716 | case 0x660ffc: /* paddb */ | |
7717 | case 0x660ffd: /* paddw */ | |
56d2815c | 7718 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7719 | if (i386_record_modrm (&ir)) |
7720 | return -1; | |
7721 | ir.reg |= rex_r; | |
c131fcee | 7722 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7723 | goto no_support; |
25ea693b MM |
7724 | record_full_arch_list_add_reg (ir.regcache, |
7725 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7726 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7727 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7728 | break; |
7729 | ||
7730 | case 0x0f11: /* movups */ | |
7731 | case 0x660f11: /* movupd */ | |
7732 | case 0xf30f11: /* movss */ | |
7733 | case 0xf20f11: /* movsd */ | |
7734 | case 0x0f13: /* movlps */ | |
7735 | case 0x660f13: /* movlpd */ | |
7736 | case 0x0f17: /* movhps */ | |
7737 | case 0x660f17: /* movhpd */ | |
7738 | case 0x0f29: /* movaps */ | |
7739 | case 0x660f29: /* movapd */ | |
7740 | case 0x660f3a14: /* pextrb */ | |
7741 | case 0x660f3a15: /* pextrw */ | |
7742 | case 0x660f3a16: /* pextrd pextrq */ | |
7743 | case 0x660f3a17: /* extractps */ | |
7744 | case 0x660f7f: /* movdqa */ | |
7745 | case 0xf30f7f: /* movdqu */ | |
7746 | if (i386_record_modrm (&ir)) | |
7747 | return -1; | |
7748 | if (ir.mod == 3) | |
7749 | { | |
7750 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7751 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7752 | goto no_support; | |
7753 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7754 | if (!i386_xmm_regnum_p (gdbarch, |
7755 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7756 | goto no_support; |
25ea693b MM |
7757 | record_full_arch_list_add_reg (ir.regcache, |
7758 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7759 | } |
7760 | else | |
7761 | { | |
7762 | switch (opcode) | |
7763 | { | |
7764 | case 0x660f3a14: | |
7765 | ir.ot = OT_BYTE; | |
7766 | break; | |
7767 | case 0x660f3a15: | |
7768 | ir.ot = OT_WORD; | |
7769 | break; | |
7770 | case 0x660f3a16: | |
7771 | ir.ot = OT_LONG; | |
7772 | break; | |
7773 | case 0x660f3a17: | |
7774 | ir.ot = OT_QUAD; | |
7775 | break; | |
7776 | default: | |
7777 | ir.ot = OT_DQUAD; | |
7778 | break; | |
7779 | } | |
7780 | if (i386_record_lea_modrm (&ir)) | |
7781 | return -1; | |
7782 | } | |
7783 | break; | |
7784 | ||
7785 | case 0x0f2b: /* movntps */ | |
7786 | case 0x660f2b: /* movntpd */ | |
7787 | case 0x0fe7: /* movntq */ | |
7788 | case 0x660fe7: /* movntdq */ | |
7789 | if (ir.mod == 3) | |
7790 | goto no_support; | |
7791 | if (opcode == 0x0fe7) | |
7792 | ir.ot = OT_QUAD; | |
7793 | else | |
7794 | ir.ot = OT_DQUAD; | |
7795 | if (i386_record_lea_modrm (&ir)) | |
7796 | return -1; | |
7797 | break; | |
7798 | ||
7799 | case 0xf30f2c: /* cvttss2si */ | |
7800 | case 0xf20f2c: /* cvttsd2si */ | |
7801 | case 0xf30f2d: /* cvtss2si */ | |
7802 | case 0xf20f2d: /* cvtsd2si */ | |
7803 | case 0xf20f38f0: /* crc32 */ | |
7804 | case 0xf20f38f1: /* crc32 */ | |
7805 | case 0x0f50: /* movmskps */ | |
7806 | case 0x660f50: /* movmskpd */ | |
7807 | case 0x0fc5: /* pextrw */ | |
7808 | case 0x660fc5: /* pextrw */ | |
7809 | case 0x0fd7: /* pmovmskb */ | |
7810 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7811 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7812 | break; |
7813 | ||
7814 | case 0x0f3800: /* pshufb */ | |
7815 | case 0x0f3801: /* phaddw */ | |
7816 | case 0x0f3802: /* phaddd */ | |
7817 | case 0x0f3803: /* phaddsw */ | |
7818 | case 0x0f3804: /* pmaddubsw */ | |
7819 | case 0x0f3805: /* phsubw */ | |
7820 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7821 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7822 | case 0x0f3808: /* psignb */ |
7823 | case 0x0f3809: /* psignw */ | |
7824 | case 0x0f380a: /* psignd */ | |
7825 | case 0x0f380b: /* pmulhrsw */ | |
7826 | case 0x0f381c: /* pabsb */ | |
7827 | case 0x0f381d: /* pabsw */ | |
7828 | case 0x0f381e: /* pabsd */ | |
7829 | case 0x0f382b: /* packusdw */ | |
7830 | case 0x0f3830: /* pmovzxbw */ | |
7831 | case 0x0f3831: /* pmovzxbd */ | |
7832 | case 0x0f3832: /* pmovzxbq */ | |
7833 | case 0x0f3833: /* pmovzxwd */ | |
7834 | case 0x0f3834: /* pmovzxwq */ | |
7835 | case 0x0f3835: /* pmovzxdq */ | |
7836 | case 0x0f3837: /* pcmpgtq */ | |
7837 | case 0x0f3838: /* pminsb */ | |
7838 | case 0x0f3839: /* pminsd */ | |
7839 | case 0x0f383a: /* pminuw */ | |
7840 | case 0x0f383b: /* pminud */ | |
7841 | case 0x0f383c: /* pmaxsb */ | |
7842 | case 0x0f383d: /* pmaxsd */ | |
7843 | case 0x0f383e: /* pmaxuw */ | |
7844 | case 0x0f383f: /* pmaxud */ | |
7845 | case 0x0f3840: /* pmulld */ | |
7846 | case 0x0f3841: /* phminposuw */ | |
7847 | case 0x0f3a0f: /* palignr */ | |
7848 | case 0x0f60: /* punpcklbw */ | |
7849 | case 0x0f61: /* punpcklwd */ | |
7850 | case 0x0f62: /* punpckldq */ | |
7851 | case 0x0f63: /* packsswb */ | |
7852 | case 0x0f64: /* pcmpgtb */ | |
7853 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7854 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7855 | case 0x0f67: /* packuswb */ |
7856 | case 0x0f68: /* punpckhbw */ | |
7857 | case 0x0f69: /* punpckhwd */ | |
7858 | case 0x0f6a: /* punpckhdq */ | |
7859 | case 0x0f6b: /* packssdw */ | |
7860 | case 0x0f6e: /* movd */ | |
7861 | case 0x0f6f: /* movq */ | |
7862 | case 0x0f70: /* pshufw */ | |
7863 | case 0x0f74: /* pcmpeqb */ | |
7864 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7865 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7866 | case 0x0fc4: /* pinsrw */ |
7867 | case 0x0fd1: /* psrlw */ | |
7868 | case 0x0fd2: /* psrld */ | |
7869 | case 0x0fd3: /* psrlq */ | |
7870 | case 0x0fd4: /* paddq */ | |
7871 | case 0x0fd5: /* pmullw */ | |
7872 | case 0xf20fd6: /* movdq2q */ | |
7873 | case 0x0fd8: /* psubusb */ | |
7874 | case 0x0fd9: /* psubusw */ | |
7875 | case 0x0fda: /* pminub */ | |
7876 | case 0x0fdb: /* pand */ | |
7877 | case 0x0fdc: /* paddusb */ | |
7878 | case 0x0fdd: /* paddusw */ | |
7879 | case 0x0fde: /* pmaxub */ | |
7880 | case 0x0fdf: /* pandn */ | |
7881 | case 0x0fe0: /* pavgb */ | |
7882 | case 0x0fe1: /* psraw */ | |
7883 | case 0x0fe2: /* psrad */ | |
7884 | case 0x0fe3: /* pavgw */ | |
7885 | case 0x0fe4: /* pmulhuw */ | |
7886 | case 0x0fe5: /* pmulhw */ | |
7887 | case 0x0fe8: /* psubsb */ | |
7888 | case 0x0fe9: /* psubsw */ | |
7889 | case 0x0fea: /* pminsw */ | |
7890 | case 0x0feb: /* por */ | |
7891 | case 0x0fec: /* paddsb */ | |
7892 | case 0x0fed: /* paddsw */ | |
7893 | case 0x0fee: /* pmaxsw */ | |
7894 | case 0x0fef: /* pxor */ | |
7895 | case 0x0ff1: /* psllw */ | |
7896 | case 0x0ff2: /* pslld */ | |
7897 | case 0x0ff3: /* psllq */ | |
7898 | case 0x0ff4: /* pmuludq */ | |
7899 | case 0x0ff5: /* pmaddwd */ | |
7900 | case 0x0ff6: /* psadbw */ | |
7901 | case 0x0ff8: /* psubb */ | |
7902 | case 0x0ff9: /* psubw */ | |
56d2815c | 7903 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7904 | case 0x0ffb: /* psubq */ |
7905 | case 0x0ffc: /* paddb */ | |
7906 | case 0x0ffd: /* paddw */ | |
56d2815c | 7907 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7908 | if (i386_record_modrm (&ir)) |
7909 | return -1; | |
7910 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7911 | goto no_support; | |
25ea693b MM |
7912 | record_full_arch_list_add_reg (ir.regcache, |
7913 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7914 | break; |
7915 | ||
7916 | case 0x0f71: /* psllw */ | |
7917 | case 0x0f72: /* pslld */ | |
7918 | case 0x0f73: /* psllq */ | |
7919 | if (i386_record_modrm (&ir)) | |
7920 | return -1; | |
7921 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7922 | goto no_support; | |
25ea693b MM |
7923 | record_full_arch_list_add_reg (ir.regcache, |
7924 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7925 | break; |
7926 | ||
7927 | case 0x660f71: /* psllw */ | |
7928 | case 0x660f72: /* pslld */ | |
7929 | case 0x660f73: /* psllq */ | |
7930 | if (i386_record_modrm (&ir)) | |
7931 | return -1; | |
7932 | ir.rm |= ir.rex_b; | |
c131fcee | 7933 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7934 | goto no_support; |
25ea693b MM |
7935 | record_full_arch_list_add_reg (ir.regcache, |
7936 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7937 | break; |
7938 | ||
7939 | case 0x0f7e: /* movd */ | |
7940 | case 0x660f7e: /* movd */ | |
7941 | if (i386_record_modrm (&ir)) | |
7942 | return -1; | |
7943 | if (ir.mod == 3) | |
25ea693b | 7944 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7945 | else |
7946 | { | |
7947 | if (ir.dflag == 2) | |
7948 | ir.ot = OT_QUAD; | |
7949 | else | |
7950 | ir.ot = OT_LONG; | |
7951 | if (i386_record_lea_modrm (&ir)) | |
7952 | return -1; | |
7953 | } | |
7954 | break; | |
7955 | ||
7956 | case 0x0f7f: /* movq */ | |
7957 | if (i386_record_modrm (&ir)) | |
7958 | return -1; | |
7959 | if (ir.mod == 3) | |
7960 | { | |
7961 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7962 | goto no_support; | |
25ea693b MM |
7963 | record_full_arch_list_add_reg (ir.regcache, |
7964 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7965 | } |
7966 | else | |
7967 | { | |
7968 | ir.ot = OT_QUAD; | |
7969 | if (i386_record_lea_modrm (&ir)) | |
7970 | return -1; | |
7971 | } | |
7972 | break; | |
7973 | ||
7974 | case 0xf30fb8: /* popcnt */ | |
7975 | if (i386_record_modrm (&ir)) | |
7976 | return -1; | |
25ea693b MM |
7977 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7978 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
7979 | break; |
7980 | ||
7981 | case 0x660fd6: /* movq */ | |
7982 | if (i386_record_modrm (&ir)) | |
7983 | return -1; | |
7984 | if (ir.mod == 3) | |
7985 | { | |
7986 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7987 | if (!i386_xmm_regnum_p (gdbarch, |
7988 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7989 | goto no_support; |
25ea693b MM |
7990 | record_full_arch_list_add_reg (ir.regcache, |
7991 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7992 | } |
7993 | else | |
7994 | { | |
7995 | ir.ot = OT_QUAD; | |
7996 | if (i386_record_lea_modrm (&ir)) | |
7997 | return -1; | |
7998 | } | |
7999 | break; | |
8000 | ||
8001 | case 0x660f3817: /* ptest */ | |
8002 | case 0x0f2e: /* ucomiss */ | |
8003 | case 0x660f2e: /* ucomisd */ | |
8004 | case 0x0f2f: /* comiss */ | |
8005 | case 0x660f2f: /* comisd */ | |
25ea693b | 8006 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8007 | break; |
8008 | ||
8009 | case 0x0ff7: /* maskmovq */ | |
8010 | regcache_raw_read_unsigned (ir.regcache, | |
8011 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8012 | &addr); | |
25ea693b | 8013 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8014 | return -1; |
8015 | break; | |
8016 | ||
8017 | case 0x660ff7: /* maskmovdqu */ | |
8018 | regcache_raw_read_unsigned (ir.regcache, | |
8019 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8020 | &addr); | |
25ea693b | 8021 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8022 | return -1; |
8023 | break; | |
8024 | ||
8025 | default: | |
8026 | goto no_support; | |
8027 | break; | |
8028 | } | |
8029 | break; | |
7ad10968 HZ |
8030 | |
8031 | default: | |
7ad10968 HZ |
8032 | goto no_support; |
8033 | break; | |
8034 | } | |
8035 | ||
cf648174 | 8036 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8037 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8038 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8039 | return -1; |
8040 | ||
8041 | return 0; | |
8042 | ||
01fe1b41 | 8043 | no_support: |
a3c4230a HZ |
8044 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8045 | "at address %s.\n"), | |
8046 | (unsigned int) (opcode), | |
8047 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8048 | return -1; |
8049 | } | |
8050 | ||
cf648174 HZ |
8051 | static const int i386_record_regmap[] = |
8052 | { | |
8053 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8054 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8055 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8056 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8057 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8058 | }; | |
8059 | ||
7a697b8d | 8060 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8061 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8062 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8063 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8064 | middle of the tracepoint jump. On x86, it may be possible to use |
8065 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8066 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8067 | of instruction to replace, and 0 if not, plus an explanatory |
8068 | string. */ | |
8069 | ||
8070 | static int | |
8071 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
8072 | CORE_ADDR addr, int *isize, char **msg) | |
8073 | { | |
8074 | int len, jumplen; | |
8075 | static struct ui_file *gdb_null = NULL; | |
8076 | ||
405f8e94 SS |
8077 | /* Ask the target for the minimum instruction length supported. */ |
8078 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8079 | ||
8080 | if (jumplen < 0) | |
8081 | { | |
8082 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8083 | operation, assume that fast tracepoints will always be implemented | |
8084 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8085 | jumplen = 5; | |
8086 | } | |
8087 | else if (jumplen == 0) | |
8088 | { | |
8089 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8090 | returns zero, then the IPA has not loaded yet. In this case, | |
8091 | we optimistically assume that truncated 2-byte relative jumps | |
8092 | will be available on x86, and compensate later if this assumption | |
8093 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8094 | jumps will always be used. */ | |
8095 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8096 | } | |
7a697b8d SS |
8097 | |
8098 | /* Dummy file descriptor for the disassembler. */ | |
8099 | if (!gdb_null) | |
8100 | gdb_null = ui_file_new (); | |
8101 | ||
8102 | /* Check for fit. */ | |
8103 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
8104 | if (isize) |
8105 | *isize = len; | |
8106 | ||
7a697b8d SS |
8107 | if (len < jumplen) |
8108 | { | |
8109 | /* Return a bit of target-specific detail to add to the caller's | |
8110 | generic failure message. */ | |
8111 | if (msg) | |
1777feb0 MS |
8112 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8113 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8114 | len, jumplen); |
8115 | return 0; | |
8116 | } | |
405f8e94 SS |
8117 | else |
8118 | { | |
8119 | if (msg) | |
8120 | *msg = NULL; | |
8121 | return 1; | |
8122 | } | |
7a697b8d SS |
8123 | } |
8124 | ||
90884b2b L |
8125 | static int |
8126 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8127 | struct tdesc_arch_data *tdesc_data) | |
8128 | { | |
8129 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8130 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8131 | |
8132 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
8133 | *feature_avx512; | |
90884b2b L |
8134 | int i, num_regs, valid_p; |
8135 | ||
8136 | if (! tdesc_has_registers (tdesc)) | |
8137 | return 0; | |
8138 | ||
8139 | /* Get core registers. */ | |
8140 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8141 | if (feature_core == NULL) |
8142 | return 0; | |
90884b2b L |
8143 | |
8144 | /* Get SSE registers. */ | |
c131fcee | 8145 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8146 | |
c131fcee L |
8147 | /* Try AVX registers. */ |
8148 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8149 | ||
1dbcd68c WT |
8150 | /* Try MPX registers. */ |
8151 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8152 | ||
01f9f808 MS |
8153 | /* Try AVX512 registers. */ |
8154 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8155 | ||
90884b2b L |
8156 | valid_p = 1; |
8157 | ||
c131fcee | 8158 | /* The XCR0 bits. */ |
01f9f808 MS |
8159 | if (feature_avx512) |
8160 | { | |
8161 | /* AVX512 register description requires AVX register description. */ | |
8162 | if (!feature_avx) | |
8163 | return 0; | |
8164 | ||
8165 | tdep->xcr0 = I386_XSTATE_MPX_AVX512_MASK; | |
8166 | ||
8167 | /* It may have been set by OSABI initialization function. */ | |
8168 | if (tdep->k0_regnum < 0) | |
8169 | { | |
8170 | tdep->k_register_names = i386_k_names; | |
8171 | tdep->k0_regnum = I386_K0_REGNUM; | |
8172 | } | |
8173 | ||
8174 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8175 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8176 | tdep->k0_regnum + i, | |
8177 | i386_k_names[i]); | |
8178 | ||
8179 | if (tdep->num_zmm_regs == 0) | |
8180 | { | |
8181 | tdep->zmmh_register_names = i386_zmmh_names; | |
8182 | tdep->num_zmm_regs = 8; | |
8183 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8184 | } | |
8185 | ||
8186 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8187 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8188 | tdep->zmm0h_regnum + i, | |
8189 | tdep->zmmh_register_names[i]); | |
8190 | ||
8191 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8192 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8193 | tdep->xmm16_regnum + i, | |
8194 | tdep->xmm_avx512_register_names[i]); | |
8195 | ||
8196 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8197 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8198 | tdep->ymm16h_regnum + i, | |
8199 | tdep->ymm16h_register_names[i]); | |
8200 | } | |
c131fcee L |
8201 | if (feature_avx) |
8202 | { | |
3a13a53b L |
8203 | /* AVX register description requires SSE register description. */ |
8204 | if (!feature_sse) | |
8205 | return 0; | |
8206 | ||
01f9f808 MS |
8207 | if (!feature_avx512) |
8208 | tdep->xcr0 = I386_XSTATE_AVX_MASK; | |
c131fcee L |
8209 | |
8210 | /* It may have been set by OSABI initialization function. */ | |
8211 | if (tdep->num_ymm_regs == 0) | |
8212 | { | |
8213 | tdep->ymmh_register_names = i386_ymmh_names; | |
8214 | tdep->num_ymm_regs = 8; | |
8215 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8216 | } | |
8217 | ||
8218 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8219 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8220 | tdep->ymm0h_regnum + i, | |
8221 | tdep->ymmh_register_names[i]); | |
8222 | } | |
3a13a53b | 8223 | else if (feature_sse) |
c131fcee | 8224 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
8225 | else |
8226 | { | |
8227 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
8228 | tdep->num_xmm_regs = 0; | |
8229 | } | |
c131fcee | 8230 | |
90884b2b L |
8231 | num_regs = tdep->num_core_regs; |
8232 | for (i = 0; i < num_regs; i++) | |
8233 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8234 | tdep->register_names[i]); | |
8235 | ||
3a13a53b L |
8236 | if (feature_sse) |
8237 | { | |
8238 | /* Need to include %mxcsr, so add one. */ | |
8239 | num_regs += tdep->num_xmm_regs + 1; | |
8240 | for (; i < num_regs; i++) | |
8241 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8242 | tdep->register_names[i]); | |
8243 | } | |
90884b2b | 8244 | |
1dbcd68c WT |
8245 | if (feature_mpx) |
8246 | { | |
01f9f808 | 8247 | tdep->xcr0 |= I386_XSTATE_MPX_MASK; |
1dbcd68c WT |
8248 | |
8249 | if (tdep->bnd0r_regnum < 0) | |
8250 | { | |
8251 | tdep->mpx_register_names = i386_mpx_names; | |
8252 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8253 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8254 | } | |
8255 | ||
8256 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8257 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8258 | I387_BND0R_REGNUM (tdep) + i, | |
8259 | tdep->mpx_register_names[i]); | |
8260 | } | |
8261 | ||
90884b2b L |
8262 | return valid_p; |
8263 | } | |
8264 | ||
7ad10968 HZ |
8265 | \f |
8266 | static struct gdbarch * | |
8267 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8268 | { | |
8269 | struct gdbarch_tdep *tdep; | |
8270 | struct gdbarch *gdbarch; | |
90884b2b L |
8271 | struct tdesc_arch_data *tdesc_data; |
8272 | const struct target_desc *tdesc; | |
1ba53b71 | 8273 | int mm0_regnum; |
c131fcee | 8274 | int ymm0_regnum; |
1dbcd68c WT |
8275 | int bnd0_regnum; |
8276 | int num_bnd_cooked; | |
01f9f808 MS |
8277 | int k0_regnum; |
8278 | int zmm0_regnum; | |
7ad10968 HZ |
8279 | |
8280 | /* If there is already a candidate, use it. */ | |
8281 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8282 | if (arches != NULL) | |
8283 | return arches->gdbarch; | |
8284 | ||
8285 | /* Allocate space for the new architecture. */ | |
fc270c35 | 8286 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8287 | gdbarch = gdbarch_alloc (&info, tdep); |
8288 | ||
8289 | /* General-purpose registers. */ | |
8290 | tdep->gregset = NULL; | |
8291 | tdep->gregset_reg_offset = NULL; | |
8292 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8293 | tdep->sizeof_gregset = 0; | |
8294 | ||
8295 | /* Floating-point registers. */ | |
8296 | tdep->fpregset = NULL; | |
8297 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
8298 | ||
c131fcee L |
8299 | tdep->xstateregset = NULL; |
8300 | ||
7ad10968 HZ |
8301 | /* The default settings include the FPU registers, the MMX registers |
8302 | and the SSE registers. This can be overridden for a specific ABI | |
8303 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8304 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8305 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8306 | |
8307 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8308 | ||
7ad10968 HZ |
8309 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8310 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8311 | ||
8312 | tdep->jb_pc_offset = -1; | |
8313 | tdep->struct_return = pcc_struct_return; | |
8314 | tdep->sigtramp_start = 0; | |
8315 | tdep->sigtramp_end = 0; | |
8316 | tdep->sigtramp_p = i386_sigtramp_p; | |
8317 | tdep->sigcontext_addr = NULL; | |
8318 | tdep->sc_reg_offset = NULL; | |
8319 | tdep->sc_pc_offset = -1; | |
8320 | tdep->sc_sp_offset = -1; | |
8321 | ||
c131fcee L |
8322 | tdep->xsave_xcr0_offset = -1; |
8323 | ||
cf648174 HZ |
8324 | tdep->record_regmap = i386_record_regmap; |
8325 | ||
205c306f DM |
8326 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8327 | ||
7ad10968 HZ |
8328 | /* The format used for `long double' on almost all i386 targets is |
8329 | the i387 extended floating-point format. In fact, of all targets | |
8330 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8331 | on having a `long double' that's not `long' at all. */ | |
8332 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8333 | ||
8334 | /* Although the i387 extended floating-point has only 80 significant | |
8335 | bits, a `long double' actually takes up 96, probably to enforce | |
8336 | alignment. */ | |
8337 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8338 | ||
7ad10968 HZ |
8339 | /* Register numbers of various important registers. */ |
8340 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8341 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8342 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8343 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8344 | ||
8345 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8346 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8347 | differ in how they number %ebp, %esp, %eflags, and the | |
8348 | floating-point registers, and are implemented by the arrays | |
8349 | dbx_register_map[] and svr4_dbx_register_map in | |
8350 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8351 | gcc/config/i386.c, which it designates as the "default" register | |
8352 | map used in 64bit mode. This last register numbering scheme is | |
8353 | implemented in dbx64_register_map, and is used for AMD64; see | |
8354 | amd64-tdep.c. | |
8355 | ||
8356 | Currently, each GCC i386 target always uses the same register | |
8357 | numbering scheme across all its supported debugging formats | |
8358 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8359 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8360 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8361 | respective config header in a manner independent of the requested | |
8362 | output debugging format. | |
8363 | ||
8364 | This does not match the arrangement below, which presumes that | |
8365 | the SDB and stabs numbering schemes differ from the DWARF and | |
8366 | DWARF 2 ones. The reason for this arrangement is that it is | |
8367 | likely to get the numbering scheme for the target's | |
8368 | default/native debug format right. For targets where GCC is the | |
8369 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8370 | targets where the native toolchain uses a different numbering | |
8371 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8372 | the defaults below will have to be overridden, like | |
8373 | i386_elf_init_abi() does. */ | |
8374 | ||
8375 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8376 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8377 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8378 | ||
8379 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
8380 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8381 | ||
8382 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8383 | be in use on any of the supported i386 targets. */ | |
8384 | ||
8385 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8386 | ||
8387 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8388 | ||
8389 | /* Call dummy code. */ | |
a9b8d892 JK |
8390 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8391 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8392 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8393 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8394 | |
8395 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8396 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8397 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8398 | ||
8399 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8400 | ||
8401 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8402 | ||
8403 | /* Stack grows downward. */ | |
8404 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8405 | ||
8406 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
8407 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
8408 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8409 | ||
8410 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8411 | ||
7ad10968 HZ |
8412 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8413 | ||
8414 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8415 | ||
8416 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8417 | ||
8418 | /* Add the i386 register groups. */ | |
8419 | i386_add_reggroups (gdbarch); | |
90884b2b | 8420 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8421 | |
143985b7 AF |
8422 | /* Helper for function argument information. */ |
8423 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8424 | ||
06da04c6 | 8425 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8426 | appended to the list first, so that it supercedes the DWARF |
8427 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8428 | currently fails). */ |
8429 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8430 | ||
8431 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8432 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8433 | CFI info will be used if it is available. */ |
10458914 | 8434 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8435 | |
acd5c798 | 8436 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8437 | |
1ba53b71 | 8438 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8439 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8440 | i386_pseudo_register_read_value); | |
90884b2b L |
8441 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
8442 | ||
8443 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8444 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8445 | ||
c131fcee L |
8446 | /* Override the normal target description method to make the AVX |
8447 | upper halves anonymous. */ | |
8448 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8449 | ||
8450 | /* Even though the default ABI only includes general-purpose registers, | |
8451 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 MS |
8452 | gap for the upper AVX, MPX and AVX512 registers. */ |
8453 | set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS); | |
90884b2b L |
8454 | |
8455 | /* Get the x86 target description from INFO. */ | |
8456 | tdesc = info.target_desc; | |
8457 | if (! tdesc_has_registers (tdesc)) | |
8458 | tdesc = tdesc_i386; | |
8459 | tdep->tdesc = tdesc; | |
8460 | ||
8461 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8462 | tdep->register_names = i386_register_names; | |
8463 | ||
c131fcee L |
8464 | /* No upper YMM registers. */ |
8465 | tdep->ymmh_register_names = NULL; | |
8466 | tdep->ymm0h_regnum = -1; | |
8467 | ||
01f9f808 MS |
8468 | /* No upper ZMM registers. */ |
8469 | tdep->zmmh_register_names = NULL; | |
8470 | tdep->zmm0h_regnum = -1; | |
8471 | ||
8472 | /* No high XMM registers. */ | |
8473 | tdep->xmm_avx512_register_names = NULL; | |
8474 | tdep->xmm16_regnum = -1; | |
8475 | ||
8476 | /* No upper YMM16-31 registers. */ | |
8477 | tdep->ymm16h_register_names = NULL; | |
8478 | tdep->ymm16h_regnum = -1; | |
8479 | ||
1ba53b71 L |
8480 | tdep->num_byte_regs = 8; |
8481 | tdep->num_word_regs = 8; | |
8482 | tdep->num_dword_regs = 0; | |
8483 | tdep->num_mmx_regs = 8; | |
c131fcee | 8484 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8485 | |
1dbcd68c WT |
8486 | /* No MPX registers. */ |
8487 | tdep->bnd0r_regnum = -1; | |
8488 | tdep->bndcfgu_regnum = -1; | |
8489 | ||
01f9f808 MS |
8490 | /* No AVX512 registers. */ |
8491 | tdep->k0_regnum = -1; | |
8492 | tdep->num_zmm_regs = 0; | |
8493 | tdep->num_ymm_avx512_regs = 0; | |
8494 | tdep->num_xmm_avx512_regs = 0; | |
8495 | ||
90884b2b L |
8496 | tdesc_data = tdesc_data_alloc (); |
8497 | ||
dde08ee1 PA |
8498 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8499 | ||
6710bf39 SS |
8500 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8501 | ||
c2170eef MM |
8502 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8503 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8504 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8505 | ||
3ce1502b | 8506 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 8507 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 8508 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8509 | |
c131fcee L |
8510 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8511 | { | |
8512 | tdesc_data_cleanup (tdesc_data); | |
8513 | xfree (tdep); | |
8514 | gdbarch_free (gdbarch); | |
8515 | return NULL; | |
8516 | } | |
8517 | ||
1dbcd68c WT |
8518 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8519 | ||
1ba53b71 L |
8520 | /* Wire in pseudo registers. Number of pseudo registers may be |
8521 | changed. */ | |
8522 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8523 | + tdep->num_word_regs | |
8524 | + tdep->num_dword_regs | |
c131fcee | 8525 | + tdep->num_mmx_regs |
1dbcd68c | 8526 | + tdep->num_ymm_regs |
01f9f808 MS |
8527 | + num_bnd_cooked |
8528 | + tdep->num_ymm_avx512_regs | |
8529 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8530 | |
90884b2b L |
8531 | /* Target description may be changed. */ |
8532 | tdesc = tdep->tdesc; | |
8533 | ||
90884b2b L |
8534 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8535 | ||
8536 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8537 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8538 | ||
1ba53b71 L |
8539 | /* Make %al the first pseudo-register. */ |
8540 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8541 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8542 | ||
c131fcee | 8543 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8544 | if (tdep->num_dword_regs) |
8545 | { | |
1c6272a6 | 8546 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8547 | tdep->eax_regnum = ymm0_regnum; |
8548 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8549 | } |
8550 | else | |
8551 | tdep->eax_regnum = -1; | |
8552 | ||
c131fcee L |
8553 | mm0_regnum = ymm0_regnum; |
8554 | if (tdep->num_ymm_regs) | |
8555 | { | |
1c6272a6 | 8556 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8557 | tdep->ymm0_regnum = ymm0_regnum; |
8558 | mm0_regnum += tdep->num_ymm_regs; | |
8559 | } | |
8560 | else | |
8561 | tdep->ymm0_regnum = -1; | |
8562 | ||
01f9f808 MS |
8563 | if (tdep->num_ymm_avx512_regs) |
8564 | { | |
8565 | /* Support YMM16-31 pseudo registers if available. */ | |
8566 | tdep->ymm16_regnum = mm0_regnum; | |
8567 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8568 | } | |
8569 | else | |
8570 | tdep->ymm16_regnum = -1; | |
8571 | ||
8572 | if (tdep->num_zmm_regs) | |
8573 | { | |
8574 | /* Support ZMM pseudo-register if it is available. */ | |
8575 | tdep->zmm0_regnum = mm0_regnum; | |
8576 | mm0_regnum += tdep->num_zmm_regs; | |
8577 | } | |
8578 | else | |
8579 | tdep->zmm0_regnum = -1; | |
8580 | ||
1dbcd68c | 8581 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8582 | if (tdep->num_mmx_regs != 0) |
8583 | { | |
1c6272a6 | 8584 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8585 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8586 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8587 | } |
8588 | else | |
8589 | tdep->mm0_regnum = -1; | |
8590 | ||
1dbcd68c WT |
8591 | if (tdep->bnd0r_regnum > 0) |
8592 | tdep->bnd0_regnum = bnd0_regnum; | |
8593 | else | |
8594 | tdep-> bnd0_regnum = -1; | |
8595 | ||
06da04c6 | 8596 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8597 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8598 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8599 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8600 | |
8446b36a MK |
8601 | /* If we have a register mapping, enable the generic core file |
8602 | support, unless it has already been enabled. */ | |
8603 | if (tdep->gregset_reg_offset | |
8604 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
8605 | set_gdbarch_regset_from_core_section (gdbarch, | |
8606 | i386_regset_from_core_section); | |
8607 | ||
514f746b AR |
8608 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
8609 | i386_skip_permanent_breakpoint); | |
8610 | ||
7a697b8d SS |
8611 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8612 | i386_fast_tracepoint_valid_at); | |
8613 | ||
a62cc96e AC |
8614 | return gdbarch; |
8615 | } | |
8616 | ||
8201327c MK |
8617 | static enum gdb_osabi |
8618 | i386_coff_osabi_sniffer (bfd *abfd) | |
8619 | { | |
762c5349 MK |
8620 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8621 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8622 | return GDB_OSABI_GO32; |
8623 | ||
8624 | return GDB_OSABI_UNKNOWN; | |
8625 | } | |
8201327c MK |
8626 | \f |
8627 | ||
28e9e0f0 MK |
8628 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
8629 | void _initialize_i386_tdep (void); | |
8630 | ||
c906108c | 8631 | void |
fba45db2 | 8632 | _initialize_i386_tdep (void) |
c906108c | 8633 | { |
a62cc96e AC |
8634 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8635 | ||
fc338970 | 8636 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8637 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8638 | &disassembly_flavor, _("\ | |
8639 | Set the disassembly flavor."), _("\ | |
8640 | Show the disassembly flavor."), _("\ | |
8641 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8642 | NULL, | |
8643 | NULL, /* FIXME: i18n: */ | |
8644 | &setlist, &showlist); | |
8201327c MK |
8645 | |
8646 | /* Add the variable that controls the convention for returning | |
8647 | structs. */ | |
7ab04401 AC |
8648 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
8649 | &struct_convention, _("\ | |
8650 | Set the convention for returning small structs."), _("\ | |
8651 | Show the convention for returning small structs."), _("\ | |
8652 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
8653 | is \"default\"."), | |
8654 | NULL, | |
8655 | NULL, /* FIXME: i18n: */ | |
8656 | &setlist, &showlist); | |
8201327c MK |
8657 | |
8658 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
8659 | i386_coff_osabi_sniffer); | |
8201327c | 8660 | |
05816f70 | 8661 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 8662 | i386_svr4_init_abi); |
05816f70 | 8663 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 8664 | i386_go32_init_abi); |
38c968cf | 8665 | |
209bd28e | 8666 | /* Initialize the i386-specific register groups. */ |
38c968cf | 8667 | i386_init_reggroups (); |
90884b2b L |
8668 | |
8669 | /* Initialize the standard target descriptions. */ | |
8670 | initialize_tdesc_i386 (); | |
3a13a53b | 8671 | initialize_tdesc_i386_mmx (); |
c131fcee | 8672 | initialize_tdesc_i386_avx (); |
1dbcd68c | 8673 | initialize_tdesc_i386_mpx (); |
01f9f808 | 8674 | initialize_tdesc_i386_avx512 (); |
c8d5aac9 L |
8675 | |
8676 | /* Tell remote stub that we support XML target description. */ | |
8677 | register_remote_support_xml ("i386"); | |
c906108c | 8678 | } |