Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4c38e0a4 JB |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, |
5 | 2010 Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
7a697b8d | 46 | #include "disasm.h" |
acd5c798 | 47 | |
3d261580 | 48 | #include "gdb_assert.h" |
acd5c798 | 49 | #include "gdb_string.h" |
3d261580 | 50 | |
d2a7c97a | 51 | #include "i386-tdep.h" |
61113f8b | 52 | #include "i387-tdep.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
c4fc7f1b | 57 | /* Register names. */ |
c40e1eab | 58 | |
fc633446 MK |
59 | static char *i386_register_names[] = |
60 | { | |
61 | "eax", "ecx", "edx", "ebx", | |
62 | "esp", "ebp", "esi", "edi", | |
63 | "eip", "eflags", "cs", "ss", | |
64 | "ds", "es", "fs", "gs", | |
65 | "st0", "st1", "st2", "st3", | |
66 | "st4", "st5", "st6", "st7", | |
67 | "fctrl", "fstat", "ftag", "fiseg", | |
68 | "fioff", "foseg", "fooff", "fop", | |
69 | "xmm0", "xmm1", "xmm2", "xmm3", | |
70 | "xmm4", "xmm5", "xmm6", "xmm7", | |
71 | "mxcsr" | |
72 | }; | |
73 | ||
1cb97e17 | 74 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 75 | |
c4fc7f1b | 76 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
77 | |
78 | static char *i386_mmx_names[] = | |
79 | { | |
80 | "mm0", "mm1", "mm2", "mm3", | |
81 | "mm4", "mm5", "mm6", "mm7" | |
82 | }; | |
c40e1eab | 83 | |
1cb97e17 | 84 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 85 | |
28fc6740 | 86 | static int |
5716833c | 87 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 88 | { |
5716833c MK |
89 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
90 | ||
91 | if (mm0_regnum < 0) | |
92 | return 0; | |
93 | ||
94 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
95 | } |
96 | ||
5716833c | 97 | /* SSE register? */ |
23a34459 | 98 | |
5716833c MK |
99 | static int |
100 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 101 | { |
5716833c MK |
102 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
103 | ||
20a6ec49 | 104 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
105 | return 0; |
106 | ||
20a6ec49 MD |
107 | return (I387_XMM0_REGNUM (tdep) <= regnum |
108 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
109 | } |
110 | ||
5716833c MK |
111 | static int |
112 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 113 | { |
5716833c MK |
114 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
115 | ||
20a6ec49 | 116 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
117 | return 0; |
118 | ||
20a6ec49 | 119 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
120 | } |
121 | ||
5716833c | 122 | /* FP register? */ |
23a34459 AC |
123 | |
124 | int | |
20a6ec49 | 125 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 126 | { |
20a6ec49 MD |
127 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
128 | ||
129 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
130 | return 0; |
131 | ||
20a6ec49 MD |
132 | return (I387_ST0_REGNUM (tdep) <= regnum |
133 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
134 | } |
135 | ||
136 | int | |
20a6ec49 | 137 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 138 | { |
20a6ec49 MD |
139 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
140 | ||
141 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
142 | return 0; |
143 | ||
20a6ec49 MD |
144 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
145 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
146 | } |
147 | ||
30b0e2d8 | 148 | /* Return the name of register REGNUM. */ |
fc633446 | 149 | |
fa88f677 | 150 | const char * |
d93859e2 | 151 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 152 | { |
d93859e2 | 153 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
20a6ec49 | 154 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; |
fc633446 | 155 | |
30b0e2d8 MK |
156 | if (regnum >= 0 && regnum < i386_num_register_names) |
157 | return i386_register_names[regnum]; | |
70913449 | 158 | |
c40e1eab | 159 | return NULL; |
fc633446 MK |
160 | } |
161 | ||
c4fc7f1b | 162 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
163 | number used by GDB. */ |
164 | ||
8201327c | 165 | static int |
d3f73121 | 166 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 167 | { |
20a6ec49 MD |
168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
169 | ||
c4fc7f1b MK |
170 | /* This implements what GCC calls the "default" register map |
171 | (dbx_register_map[]). */ | |
172 | ||
85540d8c MK |
173 | if (reg >= 0 && reg <= 7) |
174 | { | |
9872ad24 JB |
175 | /* General-purpose registers. The debug info calls %ebp |
176 | register 4, and %esp register 5. */ | |
177 | if (reg == 4) | |
178 | return 5; | |
179 | else if (reg == 5) | |
180 | return 4; | |
181 | else return reg; | |
85540d8c MK |
182 | } |
183 | else if (reg >= 12 && reg <= 19) | |
184 | { | |
185 | /* Floating-point registers. */ | |
20a6ec49 | 186 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
187 | } |
188 | else if (reg >= 21 && reg <= 28) | |
189 | { | |
190 | /* SSE registers. */ | |
20a6ec49 | 191 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
192 | } |
193 | else if (reg >= 29 && reg <= 36) | |
194 | { | |
195 | /* MMX registers. */ | |
20a6ec49 | 196 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
197 | } |
198 | ||
199 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 200 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
201 | } |
202 | ||
c4fc7f1b MK |
203 | /* Convert SVR4 register number REG to the appropriate register number |
204 | used by GDB. */ | |
85540d8c | 205 | |
8201327c | 206 | static int |
d3f73121 | 207 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 208 | { |
20a6ec49 MD |
209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
210 | ||
c4fc7f1b MK |
211 | /* This implements the GCC register map that tries to be compatible |
212 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
213 | ||
214 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
215 | numbers the floating point registers differently. */ |
216 | if (reg >= 0 && reg <= 9) | |
217 | { | |
acd5c798 | 218 | /* General-purpose registers. */ |
85540d8c MK |
219 | return reg; |
220 | } | |
221 | else if (reg >= 11 && reg <= 18) | |
222 | { | |
223 | /* Floating-point registers. */ | |
20a6ec49 | 224 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 225 | } |
c6f4c129 | 226 | else if (reg >= 21 && reg <= 36) |
85540d8c | 227 | { |
c4fc7f1b | 228 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 229 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
230 | } |
231 | ||
c6f4c129 JB |
232 | switch (reg) |
233 | { | |
20a6ec49 MD |
234 | case 37: return I387_FCTRL_REGNUM (tdep); |
235 | case 38: return I387_FSTAT_REGNUM (tdep); | |
236 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
237 | case 40: return I386_ES_REGNUM; |
238 | case 41: return I386_CS_REGNUM; | |
239 | case 42: return I386_SS_REGNUM; | |
240 | case 43: return I386_DS_REGNUM; | |
241 | case 44: return I386_FS_REGNUM; | |
242 | case 45: return I386_GS_REGNUM; | |
243 | } | |
244 | ||
85540d8c | 245 | /* This will hopefully provoke a warning. */ |
d3f73121 | 246 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 247 | } |
5716833c | 248 | |
fc338970 | 249 | \f |
917317f4 | 250 | |
fc338970 MK |
251 | /* This is the variable that is set with "set disassembly-flavor", and |
252 | its legitimate values. */ | |
53904c9e AC |
253 | static const char att_flavor[] = "att"; |
254 | static const char intel_flavor[] = "intel"; | |
255 | static const char *valid_flavors[] = | |
c5aa993b | 256 | { |
c906108c SS |
257 | att_flavor, |
258 | intel_flavor, | |
259 | NULL | |
260 | }; | |
53904c9e | 261 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 262 | \f |
c906108c | 263 | |
acd5c798 MK |
264 | /* Use the program counter to determine the contents and size of a |
265 | breakpoint instruction. Return a pointer to a string of bytes that | |
266 | encode a breakpoint instruction, store the length of the string in | |
267 | *LEN and optionally adjust *PC to point to the correct memory | |
268 | location for inserting the breakpoint. | |
c906108c | 269 | |
acd5c798 MK |
270 | On the i386 we have a single breakpoint that fits in a single byte |
271 | and can be inserted anywhere. | |
c906108c | 272 | |
acd5c798 | 273 | This function is 64-bit safe. */ |
63c0089f MK |
274 | |
275 | static const gdb_byte * | |
67d57894 | 276 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 277 | { |
63c0089f MK |
278 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
279 | ||
acd5c798 MK |
280 | *len = sizeof (break_insn); |
281 | return break_insn; | |
c906108c | 282 | } |
237fc4c9 PA |
283 | \f |
284 | /* Displaced instruction handling. */ | |
285 | ||
1903f0e6 DE |
286 | /* Skip the legacy instruction prefixes in INSN. |
287 | Not all prefixes are valid for any particular insn | |
288 | but we needn't care, the insn will fault if it's invalid. | |
289 | The result is a pointer to the first opcode byte, | |
290 | or NULL if we run off the end of the buffer. */ | |
291 | ||
292 | static gdb_byte * | |
293 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
294 | { | |
295 | gdb_byte *end = insn + max_len; | |
296 | ||
297 | while (insn < end) | |
298 | { | |
299 | switch (*insn) | |
300 | { | |
301 | case DATA_PREFIX_OPCODE: | |
302 | case ADDR_PREFIX_OPCODE: | |
303 | case CS_PREFIX_OPCODE: | |
304 | case DS_PREFIX_OPCODE: | |
305 | case ES_PREFIX_OPCODE: | |
306 | case FS_PREFIX_OPCODE: | |
307 | case GS_PREFIX_OPCODE: | |
308 | case SS_PREFIX_OPCODE: | |
309 | case LOCK_PREFIX_OPCODE: | |
310 | case REPE_PREFIX_OPCODE: | |
311 | case REPNE_PREFIX_OPCODE: | |
312 | ++insn; | |
313 | continue; | |
314 | default: | |
315 | return insn; | |
316 | } | |
317 | } | |
318 | ||
319 | return NULL; | |
320 | } | |
237fc4c9 PA |
321 | |
322 | static int | |
1903f0e6 | 323 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
324 | { |
325 | /* jmp far (absolute address in operand) */ | |
326 | if (insn[0] == 0xea) | |
327 | return 1; | |
328 | ||
329 | if (insn[0] == 0xff) | |
330 | { | |
331 | /* jump near, absolute indirect (/4) */ | |
332 | if ((insn[1] & 0x38) == 0x20) | |
333 | return 1; | |
334 | ||
335 | /* jump far, absolute indirect (/5) */ | |
336 | if ((insn[1] & 0x38) == 0x28) | |
337 | return 1; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
342 | ||
343 | static int | |
1903f0e6 | 344 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
345 | { |
346 | /* call far, absolute */ | |
347 | if (insn[0] == 0x9a) | |
348 | return 1; | |
349 | ||
350 | if (insn[0] == 0xff) | |
351 | { | |
352 | /* Call near, absolute indirect (/2) */ | |
353 | if ((insn[1] & 0x38) == 0x10) | |
354 | return 1; | |
355 | ||
356 | /* Call far, absolute indirect (/3) */ | |
357 | if ((insn[1] & 0x38) == 0x18) | |
358 | return 1; | |
359 | } | |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static int | |
1903f0e6 | 365 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
366 | { |
367 | switch (insn[0]) | |
368 | { | |
369 | case 0xc2: /* ret near, pop N bytes */ | |
370 | case 0xc3: /* ret near */ | |
371 | case 0xca: /* ret far, pop N bytes */ | |
372 | case 0xcb: /* ret far */ | |
373 | case 0xcf: /* iret */ | |
374 | return 1; | |
375 | ||
376 | default: | |
377 | return 0; | |
378 | } | |
379 | } | |
380 | ||
381 | static int | |
1903f0e6 | 382 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
383 | { |
384 | if (i386_absolute_call_p (insn)) | |
385 | return 1; | |
386 | ||
387 | /* call near, relative */ | |
388 | if (insn[0] == 0xe8) | |
389 | return 1; | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
237fc4c9 PA |
394 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
395 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 396 | |
237fc4c9 | 397 | static int |
1903f0e6 | 398 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
399 | { |
400 | if (insn[0] == 0xcd) | |
401 | { | |
402 | *lengthp = 2; | |
403 | return 1; | |
404 | } | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | /* Fix up the state of registers and memory after having single-stepped | |
410 | a displaced instruction. */ | |
1903f0e6 | 411 | |
237fc4c9 PA |
412 | void |
413 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
414 | struct displaced_step_closure *closure, | |
415 | CORE_ADDR from, CORE_ADDR to, | |
416 | struct regcache *regs) | |
417 | { | |
e17a4113 UW |
418 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
419 | ||
237fc4c9 PA |
420 | /* The offset we applied to the instruction's address. |
421 | This could well be negative (when viewed as a signed 32-bit | |
422 | value), but ULONGEST won't reflect that, so take care when | |
423 | applying it. */ | |
424 | ULONGEST insn_offset = to - from; | |
425 | ||
426 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
427 | copy of the instruction. */ | |
428 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
429 | /* The start of the insn, needed in case we see some prefixes. */ |
430 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
431 | |
432 | if (debug_displaced) | |
433 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 434 | "displaced: fixup (%s, %s), " |
237fc4c9 | 435 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
436 | paddress (gdbarch, from), paddress (gdbarch, to), |
437 | insn[0], insn[1]); | |
237fc4c9 PA |
438 | |
439 | /* The list of issues to contend with here is taken from | |
440 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
441 | Yay for Free Software! */ | |
442 | ||
443 | /* Relocate the %eip, if necessary. */ | |
444 | ||
1903f0e6 DE |
445 | /* The instruction recognizers we use assume any leading prefixes |
446 | have been skipped. */ | |
447 | { | |
448 | /* This is the size of the buffer in closure. */ | |
449 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
450 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
451 | /* If there are too many prefixes, just ignore the insn. | |
452 | It will fault when run. */ | |
453 | if (opcode != NULL) | |
454 | insn = opcode; | |
455 | } | |
456 | ||
237fc4c9 PA |
457 | /* Except in the case of absolute or indirect jump or call |
458 | instructions, or a return instruction, the new eip is relative to | |
459 | the displaced instruction; make it relative. Well, signal | |
460 | handler returns don't need relocation either, but we use the | |
461 | value of %eip to recognize those; see below. */ | |
462 | if (! i386_absolute_jmp_p (insn) | |
463 | && ! i386_absolute_call_p (insn) | |
464 | && ! i386_ret_p (insn)) | |
465 | { | |
466 | ULONGEST orig_eip; | |
467 | ULONGEST insn_len; | |
468 | ||
469 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
470 | ||
471 | /* A signal trampoline system call changes the %eip, resuming | |
472 | execution of the main program after the signal handler has | |
473 | returned. That makes them like 'return' instructions; we | |
474 | shouldn't relocate %eip. | |
475 | ||
476 | But most system calls don't, and we do need to relocate %eip. | |
477 | ||
478 | Our heuristic for distinguishing these cases: if stepping | |
479 | over the system call instruction left control directly after | |
480 | the instruction, the we relocate --- control almost certainly | |
481 | doesn't belong in the displaced copy. Otherwise, we assume | |
482 | the instruction has put control where it belongs, and leave | |
483 | it unrelocated. Goodness help us if there are PC-relative | |
484 | system calls. */ | |
485 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 486 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
487 | { |
488 | if (debug_displaced) | |
489 | fprintf_unfiltered (gdb_stdlog, | |
490 | "displaced: syscall changed %%eip; " | |
491 | "not relocating\n"); | |
492 | } | |
493 | else | |
494 | { | |
495 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
496 | ||
1903f0e6 DE |
497 | /* If we just stepped over a breakpoint insn, we don't backup |
498 | the pc on purpose; this is to match behaviour without | |
499 | stepping. */ | |
237fc4c9 PA |
500 | |
501 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
502 | ||
503 | if (debug_displaced) | |
504 | fprintf_unfiltered (gdb_stdlog, | |
505 | "displaced: " | |
5af949e3 UW |
506 | "relocated %%eip from %s to %s\n", |
507 | paddress (gdbarch, orig_eip), | |
508 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
509 | } |
510 | } | |
511 | ||
512 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
513 | pushed value, and should be cleared. We'll leave this for later, | |
514 | since GDB already messes up the TF flag when stepping over a | |
515 | pushfl. */ | |
516 | ||
517 | /* If the instruction was a call, the return address now atop the | |
518 | stack is the address following the copied instruction. We need | |
519 | to make it the address following the original instruction. */ | |
520 | if (i386_call_p (insn)) | |
521 | { | |
522 | ULONGEST esp; | |
523 | ULONGEST retaddr; | |
524 | const ULONGEST retaddr_len = 4; | |
525 | ||
526 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 527 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 528 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 529 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
530 | |
531 | if (debug_displaced) | |
532 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
533 | "displaced: relocated return addr at %s to %s\n", |
534 | paddress (gdbarch, esp), | |
535 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
536 | } |
537 | } | |
fc338970 | 538 | \f |
acd5c798 MK |
539 | #ifdef I386_REGNO_TO_SYMMETRY |
540 | #error "The Sequent Symmetry is no longer supported." | |
541 | #endif | |
c906108c | 542 | |
acd5c798 MK |
543 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
544 | and %esp "belong" to the calling function. Therefore these | |
545 | registers should be saved if they're going to be modified. */ | |
c906108c | 546 | |
acd5c798 MK |
547 | /* The maximum number of saved registers. This should include all |
548 | registers mentioned above, and %eip. */ | |
a3386186 | 549 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
550 | |
551 | struct i386_frame_cache | |
c906108c | 552 | { |
acd5c798 MK |
553 | /* Base address. */ |
554 | CORE_ADDR base; | |
772562f8 | 555 | LONGEST sp_offset; |
acd5c798 MK |
556 | CORE_ADDR pc; |
557 | ||
fd13a04a AC |
558 | /* Saved registers. */ |
559 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 560 | CORE_ADDR saved_sp; |
e0c62198 | 561 | int saved_sp_reg; |
acd5c798 MK |
562 | int pc_in_eax; |
563 | ||
564 | /* Stack space reserved for local variables. */ | |
565 | long locals; | |
566 | }; | |
567 | ||
568 | /* Allocate and initialize a frame cache. */ | |
569 | ||
570 | static struct i386_frame_cache * | |
fd13a04a | 571 | i386_alloc_frame_cache (void) |
acd5c798 MK |
572 | { |
573 | struct i386_frame_cache *cache; | |
574 | int i; | |
575 | ||
576 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
577 | ||
578 | /* Base address. */ | |
579 | cache->base = 0; | |
580 | cache->sp_offset = -4; | |
581 | cache->pc = 0; | |
582 | ||
fd13a04a AC |
583 | /* Saved registers. We initialize these to -1 since zero is a valid |
584 | offset (that's where %ebp is supposed to be stored). */ | |
585 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
586 | cache->saved_regs[i] = -1; | |
acd5c798 | 587 | cache->saved_sp = 0; |
e0c62198 | 588 | cache->saved_sp_reg = -1; |
acd5c798 MK |
589 | cache->pc_in_eax = 0; |
590 | ||
591 | /* Frameless until proven otherwise. */ | |
592 | cache->locals = -1; | |
593 | ||
594 | return cache; | |
595 | } | |
c906108c | 596 | |
acd5c798 MK |
597 | /* If the instruction at PC is a jump, return the address of its |
598 | target. Otherwise, return PC. */ | |
c906108c | 599 | |
acd5c798 | 600 | static CORE_ADDR |
e17a4113 | 601 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 602 | { |
e17a4113 | 603 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 604 | gdb_byte op; |
acd5c798 MK |
605 | long delta = 0; |
606 | int data16 = 0; | |
c906108c | 607 | |
8defab1a | 608 | target_read_memory (pc, &op, 1); |
acd5c798 | 609 | if (op == 0x66) |
c906108c | 610 | { |
c906108c | 611 | data16 = 1; |
e17a4113 | 612 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
613 | } |
614 | ||
acd5c798 | 615 | switch (op) |
c906108c SS |
616 | { |
617 | case 0xe9: | |
fc338970 | 618 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
619 | if (data16) |
620 | { | |
e17a4113 | 621 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 622 | |
fc338970 MK |
623 | /* Include the size of the jmp instruction (including the |
624 | 0x66 prefix). */ | |
acd5c798 | 625 | delta += 4; |
c906108c SS |
626 | } |
627 | else | |
628 | { | |
e17a4113 | 629 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 630 | |
acd5c798 MK |
631 | /* Include the size of the jmp instruction. */ |
632 | delta += 5; | |
c906108c SS |
633 | } |
634 | break; | |
635 | case 0xeb: | |
fc338970 | 636 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 637 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 638 | |
acd5c798 | 639 | delta += data16 + 2; |
c906108c SS |
640 | break; |
641 | } | |
c906108c | 642 | |
acd5c798 MK |
643 | return pc + delta; |
644 | } | |
fc338970 | 645 | |
acd5c798 MK |
646 | /* Check whether PC points at a prologue for a function returning a |
647 | structure or union. If so, it updates CACHE and returns the | |
648 | address of the first instruction after the code sequence that | |
649 | removes the "hidden" argument from the stack or CURRENT_PC, | |
650 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 651 | |
acd5c798 MK |
652 | static CORE_ADDR |
653 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
654 | struct i386_frame_cache *cache) | |
c906108c | 655 | { |
acd5c798 MK |
656 | /* Functions that return a structure or union start with: |
657 | ||
658 | popl %eax 0x58 | |
659 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
660 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
661 | ||
662 | (the System V compiler puts out the second `xchg' instruction, | |
663 | and the assembler doesn't try to optimize it, so the 'sib' form | |
664 | gets generated). This sequence is used to get the address of the | |
665 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
666 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
667 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
668 | gdb_byte buf[4]; | |
669 | gdb_byte op; | |
c906108c | 670 | |
acd5c798 MK |
671 | if (current_pc <= pc) |
672 | return pc; | |
673 | ||
8defab1a | 674 | target_read_memory (pc, &op, 1); |
c906108c | 675 | |
acd5c798 MK |
676 | if (op != 0x58) /* popl %eax */ |
677 | return pc; | |
c906108c | 678 | |
8defab1a | 679 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
680 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
681 | return pc; | |
c906108c | 682 | |
acd5c798 | 683 | if (current_pc == pc) |
c906108c | 684 | { |
acd5c798 MK |
685 | cache->sp_offset += 4; |
686 | return current_pc; | |
c906108c SS |
687 | } |
688 | ||
acd5c798 | 689 | if (current_pc == pc + 1) |
c906108c | 690 | { |
acd5c798 MK |
691 | cache->pc_in_eax = 1; |
692 | return current_pc; | |
693 | } | |
694 | ||
695 | if (buf[1] == proto1[1]) | |
696 | return pc + 4; | |
697 | else | |
698 | return pc + 5; | |
699 | } | |
700 | ||
701 | static CORE_ADDR | |
702 | i386_skip_probe (CORE_ADDR pc) | |
703 | { | |
704 | /* A function may start with | |
fc338970 | 705 | |
acd5c798 MK |
706 | pushl constant |
707 | call _probe | |
708 | addl $4, %esp | |
fc338970 | 709 | |
acd5c798 MK |
710 | followed by |
711 | ||
712 | pushl %ebp | |
fc338970 | 713 | |
acd5c798 | 714 | etc. */ |
63c0089f MK |
715 | gdb_byte buf[8]; |
716 | gdb_byte op; | |
fc338970 | 717 | |
8defab1a | 718 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
719 | |
720 | if (op == 0x68 || op == 0x6a) | |
721 | { | |
722 | int delta; | |
c906108c | 723 | |
acd5c798 MK |
724 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
725 | four-byte operand, depending on the opcode. */ | |
c906108c | 726 | if (op == 0x68) |
acd5c798 | 727 | delta = 5; |
c906108c | 728 | else |
acd5c798 | 729 | delta = 2; |
c906108c | 730 | |
acd5c798 MK |
731 | /* Read the following 8 bytes, which should be `call _probe' (6 |
732 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
733 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 734 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 735 | pc += delta + sizeof (buf); |
c906108c SS |
736 | } |
737 | ||
acd5c798 MK |
738 | return pc; |
739 | } | |
740 | ||
92dd43fa MK |
741 | /* GCC 4.1 and later, can put code in the prologue to realign the |
742 | stack pointer. Check whether PC points to such code, and update | |
743 | CACHE accordingly. Return the first instruction after the code | |
744 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
745 | recognize the code, return PC. */ | |
746 | ||
747 | static CORE_ADDR | |
748 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
749 | struct i386_frame_cache *cache) | |
750 | { | |
e0c62198 L |
751 | /* There are 2 code sequences to re-align stack before the frame |
752 | gets set up: | |
753 | ||
754 | 1. Use a caller-saved saved register: | |
755 | ||
756 | leal 4(%esp), %reg | |
757 | andl $-XXX, %esp | |
758 | pushl -4(%reg) | |
759 | ||
760 | 2. Use a callee-saved saved register: | |
761 | ||
762 | pushl %reg | |
763 | leal 8(%esp), %reg | |
764 | andl $-XXX, %esp | |
765 | pushl -4(%reg) | |
766 | ||
767 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
768 | ||
769 | 0x83 0xe4 0xf0 andl $-16, %esp | |
770 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
771 | */ | |
772 | ||
773 | gdb_byte buf[14]; | |
774 | int reg; | |
775 | int offset, offset_and; | |
776 | static int regnums[8] = { | |
777 | I386_EAX_REGNUM, /* %eax */ | |
778 | I386_ECX_REGNUM, /* %ecx */ | |
779 | I386_EDX_REGNUM, /* %edx */ | |
780 | I386_EBX_REGNUM, /* %ebx */ | |
781 | I386_ESP_REGNUM, /* %esp */ | |
782 | I386_EBP_REGNUM, /* %ebp */ | |
783 | I386_ESI_REGNUM, /* %esi */ | |
784 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 785 | }; |
92dd43fa | 786 | |
e0c62198 L |
787 | if (target_read_memory (pc, buf, sizeof buf)) |
788 | return pc; | |
789 | ||
790 | /* Check caller-saved saved register. The first instruction has | |
791 | to be "leal 4(%esp), %reg". */ | |
792 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
793 | { | |
794 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
795 | if ((buf[1] & 0xc7) != 0x44) | |
796 | return pc; | |
797 | ||
798 | /* REG has register number. */ | |
799 | reg = (buf[1] >> 3) & 7; | |
800 | offset = 4; | |
801 | } | |
802 | else | |
803 | { | |
804 | /* Check callee-saved saved register. The first instruction | |
805 | has to be "pushl %reg". */ | |
806 | if ((buf[0] & 0xf8) != 0x50) | |
807 | return pc; | |
808 | ||
809 | /* Get register. */ | |
810 | reg = buf[0] & 0x7; | |
811 | ||
812 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
813 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
814 | return pc; | |
815 | ||
816 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
817 | if ((buf[2] & 0xc7) != 0x44) | |
818 | return pc; | |
819 | ||
820 | /* REG has register number. Registers in pushl and leal have to | |
821 | be the same. */ | |
822 | if (reg != ((buf[2] >> 3) & 7)) | |
823 | return pc; | |
824 | ||
825 | offset = 5; | |
826 | } | |
827 | ||
828 | /* Rigister can't be %esp nor %ebp. */ | |
829 | if (reg == 4 || reg == 5) | |
830 | return pc; | |
831 | ||
832 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
833 | if (buf[offset + 1] != 0xe4 | |
834 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
835 | return pc; | |
836 | ||
837 | offset_and = offset; | |
838 | offset += buf[offset] == 0x81 ? 6 : 3; | |
839 | ||
840 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
841 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
842 | if (buf[offset] != 0xff | |
843 | || buf[offset + 2] != 0xfc | |
844 | || (buf[offset + 1] & 0xf8) != 0x70) | |
845 | return pc; | |
846 | ||
847 | /* R/M has register. Registers in leal and pushl have to be the | |
848 | same. */ | |
849 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
850 | return pc; |
851 | ||
e0c62198 L |
852 | if (current_pc > pc + offset_and) |
853 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 854 | |
e0c62198 | 855 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
856 | } |
857 | ||
37bdc87e | 858 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 859 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
860 | |
861 | /* Instruction description. */ | |
862 | struct i386_insn | |
863 | { | |
864 | size_t len; | |
237fc4c9 PA |
865 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
866 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
867 | }; |
868 | ||
869 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
870 | the first instruction description that matches. Otherwise, return | |
871 | NULL. */ | |
872 | ||
873 | static struct i386_insn * | |
874 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
875 | { | |
876 | struct i386_insn *insn; | |
63c0089f | 877 | gdb_byte op; |
37bdc87e | 878 | |
8defab1a | 879 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
880 | |
881 | for (insn = skip_insns; insn->len > 0; insn++) | |
882 | { | |
883 | if ((op & insn->mask[0]) == insn->insn[0]) | |
884 | { | |
237fc4c9 | 885 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 886 | int insn_matched = 1; |
37bdc87e MK |
887 | size_t i; |
888 | ||
889 | gdb_assert (insn->len > 1); | |
237fc4c9 | 890 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 891 | |
8defab1a | 892 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
893 | for (i = 1; i < insn->len; i++) |
894 | { | |
895 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 896 | insn_matched = 0; |
37bdc87e | 897 | } |
613e8135 MK |
898 | |
899 | if (insn_matched) | |
900 | return insn; | |
37bdc87e MK |
901 | } |
902 | } | |
903 | ||
904 | return NULL; | |
905 | } | |
906 | ||
907 | /* Some special instructions that might be migrated by GCC into the | |
908 | part of the prologue that sets up the new stack frame. Because the | |
909 | stack frame hasn't been setup yet, no registers have been saved | |
910 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
911 | touched. */ | |
912 | ||
913 | struct i386_insn i386_frame_setup_skip_insns[] = | |
914 | { | |
915 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
916 | ||
917 | ??? Should we handle 16-bit operand-sizes here? */ | |
918 | ||
919 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
920 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
921 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
922 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
923 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
924 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
925 | { 5, { 0xb8 }, { 0xfe } }, | |
926 | /* `movl imm32, %edx' */ | |
927 | { 5, { 0xba }, { 0xff } }, | |
928 | ||
929 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
930 | encoding for `mov m32, %eax'. | |
931 | ||
932 | ??? Should we handle SIB adressing here? | |
933 | ??? Should we handle 16-bit operand-sizes here? */ | |
934 | ||
935 | /* `movl m32, %eax' */ | |
936 | { 5, { 0xa1 }, { 0xff } }, | |
937 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
938 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
939 | /* `movl m32, %edx' */ | |
940 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
941 | ||
942 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
943 | Because of the symmetry, there are actually two ways to encode | |
944 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
945 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
946 | ||
947 | /* `subl %eax, %eax' */ | |
948 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
949 | /* `subl %ecx, %ecx' */ | |
950 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
951 | /* `subl %edx, %edx' */ | |
952 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
953 | /* `xorl %eax, %eax' */ | |
954 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
955 | /* `xorl %ecx, %ecx' */ | |
956 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
957 | /* `xorl %edx, %edx' */ | |
958 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
959 | { 0 } | |
960 | }; | |
961 | ||
e11481da PM |
962 | |
963 | /* Check whether PC points to a no-op instruction. */ | |
964 | static CORE_ADDR | |
965 | i386_skip_noop (CORE_ADDR pc) | |
966 | { | |
967 | gdb_byte op; | |
968 | int check = 1; | |
969 | ||
8defab1a | 970 | target_read_memory (pc, &op, 1); |
e11481da PM |
971 | |
972 | while (check) | |
973 | { | |
974 | check = 0; | |
975 | /* Ignore `nop' instruction. */ | |
976 | if (op == 0x90) | |
977 | { | |
978 | pc += 1; | |
8defab1a | 979 | target_read_memory (pc, &op, 1); |
e11481da PM |
980 | check = 1; |
981 | } | |
982 | /* Ignore no-op instruction `mov %edi, %edi'. | |
983 | Microsoft system dlls often start with | |
984 | a `mov %edi,%edi' instruction. | |
985 | The 5 bytes before the function start are | |
986 | filled with `nop' instructions. | |
987 | This pattern can be used for hot-patching: | |
988 | The `mov %edi, %edi' instruction can be replaced by a | |
989 | near jump to the location of the 5 `nop' instructions | |
990 | which can be replaced by a 32-bit jump to anywhere | |
991 | in the 32-bit address space. */ | |
992 | ||
993 | else if (op == 0x8b) | |
994 | { | |
8defab1a | 995 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
996 | if (op == 0xff) |
997 | { | |
998 | pc += 2; | |
8defab1a | 999 | target_read_memory (pc, &op, 1); |
e11481da PM |
1000 | check = 1; |
1001 | } | |
1002 | } | |
1003 | } | |
1004 | return pc; | |
1005 | } | |
1006 | ||
acd5c798 MK |
1007 | /* Check whether PC points at a code that sets up a new stack frame. |
1008 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1009 | instruction after the sequence that sets up the frame or LIMIT, |
1010 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1011 | |
1012 | static CORE_ADDR | |
e17a4113 UW |
1013 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1014 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1015 | struct i386_frame_cache *cache) |
1016 | { | |
e17a4113 | 1017 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1018 | struct i386_insn *insn; |
63c0089f | 1019 | gdb_byte op; |
26604a34 | 1020 | int skip = 0; |
acd5c798 | 1021 | |
37bdc87e MK |
1022 | if (limit <= pc) |
1023 | return limit; | |
acd5c798 | 1024 | |
8defab1a | 1025 | target_read_memory (pc, &op, 1); |
acd5c798 | 1026 | |
c906108c | 1027 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1028 | { |
acd5c798 MK |
1029 | /* Take into account that we've executed the `pushl %ebp' that |
1030 | starts this instruction sequence. */ | |
fd13a04a | 1031 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1032 | cache->sp_offset += 4; |
37bdc87e | 1033 | pc++; |
acd5c798 MK |
1034 | |
1035 | /* If that's all, return now. */ | |
37bdc87e MK |
1036 | if (limit <= pc) |
1037 | return limit; | |
26604a34 | 1038 | |
b4632131 | 1039 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1040 | GCC into the prologue and skip them. At this point in the |
1041 | prologue, code should only touch the scratch registers %eax, | |
1042 | %ecx and %edx, so while the number of posibilities is sheer, | |
1043 | it is limited. | |
5daa5b4e | 1044 | |
26604a34 MK |
1045 | Make sure we only skip these instructions if we later see the |
1046 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1047 | while (pc + skip < limit) |
26604a34 | 1048 | { |
37bdc87e MK |
1049 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1050 | if (insn == NULL) | |
1051 | break; | |
b4632131 | 1052 | |
37bdc87e | 1053 | skip += insn->len; |
26604a34 MK |
1054 | } |
1055 | ||
37bdc87e MK |
1056 | /* If that's all, return now. */ |
1057 | if (limit <= pc + skip) | |
1058 | return limit; | |
1059 | ||
8defab1a | 1060 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1061 | |
26604a34 | 1062 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1063 | switch (op) |
c906108c SS |
1064 | { |
1065 | case 0x8b: | |
e17a4113 UW |
1066 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1067 | != 0xec) | |
37bdc87e | 1068 | return pc; |
c906108c SS |
1069 | break; |
1070 | case 0x89: | |
e17a4113 UW |
1071 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1072 | != 0xe5) | |
37bdc87e | 1073 | return pc; |
c906108c SS |
1074 | break; |
1075 | default: | |
37bdc87e | 1076 | return pc; |
c906108c | 1077 | } |
acd5c798 | 1078 | |
26604a34 MK |
1079 | /* OK, we actually have a frame. We just don't know how large |
1080 | it is yet. Set its size to zero. We'll adjust it if | |
1081 | necessary. We also now commit to skipping the special | |
1082 | instructions mentioned before. */ | |
acd5c798 | 1083 | cache->locals = 0; |
37bdc87e | 1084 | pc += (skip + 2); |
acd5c798 MK |
1085 | |
1086 | /* If that's all, return now. */ | |
37bdc87e MK |
1087 | if (limit <= pc) |
1088 | return limit; | |
acd5c798 | 1089 | |
fc338970 MK |
1090 | /* Check for stack adjustment |
1091 | ||
acd5c798 | 1092 | subl $XXX, %esp |
fc338970 | 1093 | |
fd35795f | 1094 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1095 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1096 | target_read_memory (pc, &op, 1); |
c906108c SS |
1097 | if (op == 0x83) |
1098 | { | |
fd35795f | 1099 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1100 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1101 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1102 | return pc; |
acd5c798 | 1103 | |
37bdc87e MK |
1104 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1105 | make sense to be negative). */ | |
e17a4113 | 1106 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1107 | return pc + 3; |
c906108c SS |
1108 | } |
1109 | else if (op == 0x81) | |
1110 | { | |
fd35795f | 1111 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1112 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1113 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1114 | return pc; |
acd5c798 | 1115 | |
fd35795f | 1116 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1117 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1118 | return pc + 6; |
c906108c SS |
1119 | } |
1120 | else | |
1121 | { | |
acd5c798 | 1122 | /* Some instruction other than `subl'. */ |
37bdc87e | 1123 | return pc; |
c906108c SS |
1124 | } |
1125 | } | |
37bdc87e | 1126 | else if (op == 0xc8) /* enter */ |
c906108c | 1127 | { |
e17a4113 | 1128 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1129 | return pc + 4; |
c906108c | 1130 | } |
21d0e8a4 | 1131 | |
acd5c798 | 1132 | return pc; |
21d0e8a4 MK |
1133 | } |
1134 | ||
acd5c798 MK |
1135 | /* Check whether PC points at code that saves registers on the stack. |
1136 | If so, it updates CACHE and returns the address of the first | |
1137 | instruction after the register saves or CURRENT_PC, whichever is | |
1138 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1139 | |
1140 | static CORE_ADDR | |
acd5c798 MK |
1141 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1142 | struct i386_frame_cache *cache) | |
6bff26de | 1143 | { |
99ab4326 | 1144 | CORE_ADDR offset = 0; |
63c0089f | 1145 | gdb_byte op; |
99ab4326 | 1146 | int i; |
c0d1d883 | 1147 | |
99ab4326 MK |
1148 | if (cache->locals > 0) |
1149 | offset -= cache->locals; | |
1150 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1151 | { | |
8defab1a | 1152 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1153 | if (op < 0x50 || op > 0x57) |
1154 | break; | |
0d17c81d | 1155 | |
99ab4326 MK |
1156 | offset -= 4; |
1157 | cache->saved_regs[op - 0x50] = offset; | |
1158 | cache->sp_offset += 4; | |
1159 | pc++; | |
6bff26de MK |
1160 | } |
1161 | ||
acd5c798 | 1162 | return pc; |
22797942 AC |
1163 | } |
1164 | ||
acd5c798 MK |
1165 | /* Do a full analysis of the prologue at PC and update CACHE |
1166 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1167 | address where the analysis stopped. | |
ed84f6c1 | 1168 | |
fc338970 MK |
1169 | We handle these cases: |
1170 | ||
1171 | The startup sequence can be at the start of the function, or the | |
1172 | function can start with a branch to startup code at the end. | |
1173 | ||
1174 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1175 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1176 | once used in the System V compiler). | |
1177 | ||
1178 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1179 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1180 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1181 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1182 | |
1183 | Next, the registers used by this function are pushed. With the | |
1184 | System V compiler they will always be in the order: %edi, %esi, | |
1185 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1186 | restore %eax); however, the code below is willing to see the pushes | |
1187 | in any order, and will handle up to 8 of them. | |
1188 | ||
1189 | If the setup sequence is at the end of the function, then the next | |
1190 | instruction will be a branch back to the start. */ | |
c906108c | 1191 | |
acd5c798 | 1192 | static CORE_ADDR |
e17a4113 UW |
1193 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1194 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1195 | struct i386_frame_cache *cache) |
c906108c | 1196 | { |
e11481da | 1197 | pc = i386_skip_noop (pc); |
e17a4113 | 1198 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1199 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1200 | pc = i386_skip_probe (pc); | |
92dd43fa | 1201 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1202 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1203 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1204 | } |
1205 | ||
fc338970 | 1206 | /* Return PC of first real instruction. */ |
c906108c | 1207 | |
3a1e71e3 | 1208 | static CORE_ADDR |
6093d2eb | 1209 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1210 | { |
e17a4113 UW |
1211 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1212 | ||
63c0089f | 1213 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1214 | { |
1215 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1216 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1217 | }; |
acd5c798 MK |
1218 | struct i386_frame_cache cache; |
1219 | CORE_ADDR pc; | |
63c0089f | 1220 | gdb_byte op; |
acd5c798 | 1221 | int i; |
c5aa993b | 1222 | |
acd5c798 | 1223 | cache.locals = -1; |
e17a4113 | 1224 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1225 | if (cache.locals < 0) |
1226 | return start_pc; | |
c5aa993b | 1227 | |
acd5c798 | 1228 | /* Found valid frame setup. */ |
c906108c | 1229 | |
fc338970 MK |
1230 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1231 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1232 | %ebx: |
1233 | ||
fc338970 MK |
1234 | call 0x0 |
1235 | popl %ebx | |
1236 | movl %ebx,x(%ebp) (optional) | |
1237 | addl y,%ebx | |
1238 | ||
c906108c SS |
1239 | This code is with the rest of the prologue (at the end of the |
1240 | function), so we have to skip it to get to the first real | |
1241 | instruction at the start of the function. */ | |
c5aa993b | 1242 | |
c906108c SS |
1243 | for (i = 0; i < 6; i++) |
1244 | { | |
8defab1a | 1245 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1246 | if (pic_pat[i] != op) |
c906108c SS |
1247 | break; |
1248 | } | |
1249 | if (i == 6) | |
1250 | { | |
acd5c798 MK |
1251 | int delta = 6; |
1252 | ||
8defab1a | 1253 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1254 | |
c5aa993b | 1255 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1256 | { |
e17a4113 | 1257 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1258 | |
fc338970 | 1259 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1260 | delta += 3; |
fc338970 | 1261 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1262 | delta += 6; |
fc338970 | 1263 | else /* Unexpected instruction. */ |
acd5c798 MK |
1264 | delta = 0; |
1265 | ||
8defab1a | 1266 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1267 | } |
acd5c798 | 1268 | |
c5aa993b | 1269 | /* addl y,%ebx */ |
acd5c798 | 1270 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1271 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1272 | == 0xc3) | |
c906108c | 1273 | { |
acd5c798 | 1274 | pc += delta + 6; |
c906108c SS |
1275 | } |
1276 | } | |
c5aa993b | 1277 | |
e63bbc88 MK |
1278 | /* If the function starts with a branch (to startup code at the end) |
1279 | the last instruction should bring us back to the first | |
1280 | instruction of the real code. */ | |
e17a4113 UW |
1281 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1282 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1283 | |
1284 | return pc; | |
c906108c SS |
1285 | } |
1286 | ||
4309257c PM |
1287 | /* Check that the code pointed to by PC corresponds to a call to |
1288 | __main, skip it if so. Return PC otherwise. */ | |
1289 | ||
1290 | CORE_ADDR | |
1291 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1292 | { | |
e17a4113 | 1293 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1294 | gdb_byte op; |
1295 | ||
1296 | target_read_memory (pc, &op, 1); | |
1297 | if (op == 0xe8) | |
1298 | { | |
1299 | gdb_byte buf[4]; | |
1300 | ||
1301 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1302 | { | |
1303 | /* Make sure address is computed correctly as a 32bit | |
1304 | integer even if CORE_ADDR is 64 bit wide. */ | |
1305 | struct minimal_symbol *s; | |
e17a4113 | 1306 | CORE_ADDR call_dest; |
4309257c | 1307 | |
e17a4113 | 1308 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1309 | call_dest = call_dest & 0xffffffffU; |
1310 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1311 | if (s != NULL | |
1312 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1313 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1314 | pc += 5; | |
1315 | } | |
1316 | } | |
1317 | ||
1318 | return pc; | |
1319 | } | |
1320 | ||
acd5c798 | 1321 | /* This function is 64-bit safe. */ |
93924b6b | 1322 | |
acd5c798 MK |
1323 | static CORE_ADDR |
1324 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1325 | { |
63c0089f | 1326 | gdb_byte buf[8]; |
acd5c798 | 1327 | |
875f8d0e | 1328 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1329 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1330 | } |
acd5c798 | 1331 | \f |
93924b6b | 1332 | |
acd5c798 | 1333 | /* Normal frames. */ |
c5aa993b | 1334 | |
acd5c798 | 1335 | static struct i386_frame_cache * |
10458914 | 1336 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1337 | { |
e17a4113 UW |
1338 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1339 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1340 | struct i386_frame_cache *cache; |
63c0089f | 1341 | gdb_byte buf[4]; |
acd5c798 MK |
1342 | int i; |
1343 | ||
1344 | if (*this_cache) | |
1345 | return *this_cache; | |
1346 | ||
fd13a04a | 1347 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1348 | *this_cache = cache; |
1349 | ||
1350 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1351 | which holds the base address for the current stack frame. | |
1352 | However, for functions that don't need it, the frame pointer is | |
1353 | optional. For these "frameless" functions the frame pointer is | |
1354 | actually the frame pointer of the calling frame. Signal | |
1355 | trampolines are just a special case of a "frameless" function. | |
1356 | They (usually) share their frame pointer with the frame that was | |
1357 | in progress when the signal occurred. */ | |
1358 | ||
10458914 | 1359 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1360 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1361 | if (cache->base == 0) |
1362 | return cache; | |
1363 | ||
1364 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1365 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1366 | |
10458914 | 1367 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1368 | if (cache->pc != 0) |
e17a4113 UW |
1369 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1370 | cache); | |
acd5c798 | 1371 | |
e0c62198 | 1372 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1373 | { |
e0c62198 L |
1374 | /* Saved stack pointer has been saved. */ |
1375 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1376 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1377 | } |
1378 | ||
acd5c798 MK |
1379 | if (cache->locals < 0) |
1380 | { | |
1381 | /* We didn't find a valid frame, which means that CACHE->base | |
1382 | currently holds the frame pointer for our calling frame. If | |
1383 | we're at the start of a function, or somewhere half-way its | |
1384 | prologue, the function's frame probably hasn't been fully | |
1385 | setup yet. Try to reconstruct the base address for the stack | |
1386 | frame by looking at the stack pointer. For truly "frameless" | |
1387 | functions this might work too. */ | |
1388 | ||
e0c62198 | 1389 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1390 | { |
1391 | /* We're halfway aligning the stack. */ | |
1392 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1393 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1394 | ||
1395 | /* This will be added back below. */ | |
1396 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1397 | } | |
7618e12b DJ |
1398 | else if (cache->pc != 0 |
1399 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1400 | { |
7618e12b DJ |
1401 | /* We're in a known function, but did not find a frame |
1402 | setup. Assume that the function does not use %ebp. | |
1403 | Alternatively, we may have jumped to an invalid | |
1404 | address; in that case there is definitely no new | |
1405 | frame in %ebp. */ | |
10458914 | 1406 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1407 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1408 | + cache->sp_offset; | |
92dd43fa | 1409 | } |
7618e12b DJ |
1410 | else |
1411 | /* We're in an unknown function. We could not find the start | |
1412 | of the function to analyze the prologue; our best option is | |
1413 | to assume a typical frame layout with the caller's %ebp | |
1414 | saved. */ | |
1415 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1416 | } |
1417 | ||
1418 | /* Now that we have the base address for the stack frame we can | |
1419 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1420 | if (cache->saved_sp == 0) |
1421 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1422 | |
acd5c798 MK |
1423 | /* Adjust all the saved registers such that they contain addresses |
1424 | instead of offsets. */ | |
1425 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1426 | if (cache->saved_regs[i] != -1) |
1427 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1428 | |
1429 | return cache; | |
a7769679 MK |
1430 | } |
1431 | ||
3a1e71e3 | 1432 | static void |
10458914 | 1433 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1434 | struct frame_id *this_id) |
c906108c | 1435 | { |
10458914 | 1436 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1437 | |
1438 | /* This marks the outermost frame. */ | |
1439 | if (cache->base == 0) | |
1440 | return; | |
1441 | ||
3e210248 | 1442 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1443 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1444 | } | |
1445 | ||
10458914 DJ |
1446 | static struct value * |
1447 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1448 | int regnum) | |
acd5c798 | 1449 | { |
10458914 | 1450 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1451 | |
1452 | gdb_assert (regnum >= 0); | |
1453 | ||
1454 | /* The System V ABI says that: | |
1455 | ||
1456 | "The flags register contains the system flags, such as the | |
1457 | direction flag and the carry flag. The direction flag must be | |
1458 | set to the forward (that is, zero) direction before entry and | |
1459 | upon exit from a function. Other user flags have no specified | |
1460 | role in the standard calling sequence and are not preserved." | |
1461 | ||
1462 | To guarantee the "upon exit" part of that statement we fake a | |
1463 | saved flags register that has its direction flag cleared. | |
1464 | ||
1465 | Note that GCC doesn't seem to rely on the fact that the direction | |
1466 | flag is cleared after a function return; it always explicitly | |
1467 | clears the flag before operations where it matters. | |
1468 | ||
1469 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1470 | right thing to do. The way we fake the flags register here makes | |
1471 | it impossible to change it. */ | |
1472 | ||
1473 | if (regnum == I386_EFLAGS_REGNUM) | |
1474 | { | |
10458914 | 1475 | ULONGEST val; |
c5aa993b | 1476 | |
10458914 DJ |
1477 | val = get_frame_register_unsigned (this_frame, regnum); |
1478 | val &= ~(1 << 10); | |
1479 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1480 | } |
1211c4e4 | 1481 | |
acd5c798 | 1482 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1483 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1484 | |
1485 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1486 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1487 | |
fd13a04a | 1488 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1489 | return frame_unwind_got_memory (this_frame, regnum, |
1490 | cache->saved_regs[regnum]); | |
fd13a04a | 1491 | |
10458914 | 1492 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1493 | } |
1494 | ||
1495 | static const struct frame_unwind i386_frame_unwind = | |
1496 | { | |
1497 | NORMAL_FRAME, | |
1498 | i386_frame_this_id, | |
10458914 DJ |
1499 | i386_frame_prev_register, |
1500 | NULL, | |
1501 | default_frame_sniffer | |
acd5c798 | 1502 | }; |
06da04c6 MS |
1503 | |
1504 | /* Normal frames, but in a function epilogue. */ | |
1505 | ||
1506 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1507 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1508 | the function's stack frame. */ | |
1509 | ||
1510 | static int | |
1511 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1512 | { | |
1513 | gdb_byte insn; | |
1514 | ||
1515 | if (target_read_memory (pc, &insn, 1)) | |
1516 | return 0; /* Can't read memory at pc. */ | |
1517 | ||
1518 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1519 | return 0; | |
1520 | ||
1521 | return 1; | |
1522 | } | |
1523 | ||
1524 | static int | |
1525 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1526 | struct frame_info *this_frame, | |
1527 | void **this_prologue_cache) | |
1528 | { | |
1529 | if (frame_relative_level (this_frame) == 0) | |
1530 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1531 | get_frame_pc (this_frame)); | |
1532 | else | |
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | static struct i386_frame_cache * | |
1537 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1538 | { | |
1539 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1540 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1541 | struct i386_frame_cache *cache; | |
1542 | gdb_byte buf[4]; | |
1543 | ||
1544 | if (*this_cache) | |
1545 | return *this_cache; | |
1546 | ||
1547 | cache = i386_alloc_frame_cache (); | |
1548 | *this_cache = cache; | |
1549 | ||
1550 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1551 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1552 | cache->base = extract_unsigned_integer (buf, 4, | |
1553 | byte_order) + cache->sp_offset; | |
1554 | ||
1555 | /* Cache pc will be the frame func. */ | |
1556 | cache->pc = get_frame_pc (this_frame); | |
1557 | ||
1558 | /* The saved %esp will be at cache->base plus 8. */ | |
1559 | cache->saved_sp = cache->base + 8; | |
1560 | ||
1561 | /* The saved %eip will be at cache->base plus 4. */ | |
1562 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1563 | ||
1564 | return cache; | |
1565 | } | |
1566 | ||
1567 | static void | |
1568 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1569 | void **this_cache, | |
1570 | struct frame_id *this_id) | |
1571 | { | |
1572 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1573 | this_cache); | |
1574 | ||
1575 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1576 | } | |
1577 | ||
1578 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1579 | { | |
1580 | NORMAL_FRAME, | |
1581 | i386_epilogue_frame_this_id, | |
1582 | i386_frame_prev_register, | |
1583 | NULL, | |
1584 | i386_epilogue_frame_sniffer | |
1585 | }; | |
acd5c798 MK |
1586 | \f |
1587 | ||
1588 | /* Signal trampolines. */ | |
1589 | ||
1590 | static struct i386_frame_cache * | |
10458914 | 1591 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1592 | { |
e17a4113 UW |
1593 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1594 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1595 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1596 | struct i386_frame_cache *cache; |
acd5c798 | 1597 | CORE_ADDR addr; |
63c0089f | 1598 | gdb_byte buf[4]; |
acd5c798 MK |
1599 | |
1600 | if (*this_cache) | |
1601 | return *this_cache; | |
1602 | ||
fd13a04a | 1603 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1604 | |
10458914 | 1605 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1606 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1607 | |
10458914 | 1608 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1609 | if (tdep->sc_reg_offset) |
1610 | { | |
1611 | int i; | |
1612 | ||
1613 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1614 | ||
1615 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1616 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1617 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1618 | } |
1619 | else | |
1620 | { | |
fd13a04a AC |
1621 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1622 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1623 | } |
acd5c798 MK |
1624 | |
1625 | *this_cache = cache; | |
1626 | return cache; | |
1627 | } | |
1628 | ||
1629 | static void | |
10458914 | 1630 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1631 | struct frame_id *this_id) |
1632 | { | |
1633 | struct i386_frame_cache *cache = | |
10458914 | 1634 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1635 | |
3e210248 | 1636 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1637 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1638 | } |
1639 | ||
10458914 DJ |
1640 | static struct value * |
1641 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1642 | void **this_cache, int regnum) | |
acd5c798 MK |
1643 | { |
1644 | /* Make sure we've initialized the cache. */ | |
10458914 | 1645 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1646 | |
10458914 | 1647 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1648 | } |
c0d1d883 | 1649 | |
10458914 DJ |
1650 | static int |
1651 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1652 | struct frame_info *this_frame, | |
1653 | void **this_prologue_cache) | |
acd5c798 | 1654 | { |
10458914 | 1655 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1656 | |
911bc6ee MK |
1657 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1658 | handler. */ | |
1659 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1660 | return 0; |
1c3545ae | 1661 | |
911bc6ee MK |
1662 | if (tdep->sigtramp_p != NULL) |
1663 | { | |
10458914 DJ |
1664 | if (tdep->sigtramp_p (this_frame)) |
1665 | return 1; | |
911bc6ee MK |
1666 | } |
1667 | ||
1668 | if (tdep->sigtramp_start != 0) | |
1669 | { | |
10458914 | 1670 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1671 | |
1672 | gdb_assert (tdep->sigtramp_end != 0); | |
1673 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1674 | return 1; |
911bc6ee | 1675 | } |
acd5c798 | 1676 | |
10458914 | 1677 | return 0; |
acd5c798 | 1678 | } |
10458914 DJ |
1679 | |
1680 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1681 | { | |
1682 | SIGTRAMP_FRAME, | |
1683 | i386_sigtramp_frame_this_id, | |
1684 | i386_sigtramp_frame_prev_register, | |
1685 | NULL, | |
1686 | i386_sigtramp_frame_sniffer | |
1687 | }; | |
acd5c798 MK |
1688 | \f |
1689 | ||
1690 | static CORE_ADDR | |
10458914 | 1691 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1692 | { |
10458914 | 1693 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1694 | |
1695 | return cache->base; | |
1696 | } | |
1697 | ||
1698 | static const struct frame_base i386_frame_base = | |
1699 | { | |
1700 | &i386_frame_unwind, | |
1701 | i386_frame_base_address, | |
1702 | i386_frame_base_address, | |
1703 | i386_frame_base_address | |
1704 | }; | |
1705 | ||
acd5c798 | 1706 | static struct frame_id |
10458914 | 1707 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1708 | { |
acd5c798 MK |
1709 | CORE_ADDR fp; |
1710 | ||
10458914 | 1711 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1712 | |
3e210248 | 1713 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1714 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1715 | } |
fc338970 | 1716 | \f |
c906108c | 1717 | |
fc338970 MK |
1718 | /* Figure out where the longjmp will land. Slurp the args out of the |
1719 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1720 | structure from which we extract the address that we will land at. |
28bcfd30 | 1721 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1722 | success. */ |
c906108c | 1723 | |
8201327c | 1724 | static int |
60ade65d | 1725 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1726 | { |
436675d3 | 1727 | gdb_byte buf[4]; |
c906108c | 1728 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1729 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1730 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1731 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1732 | |
8201327c MK |
1733 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1734 | longjmp will land. */ | |
1735 | if (jb_pc_offset == -1) | |
c906108c SS |
1736 | return 0; |
1737 | ||
436675d3 | 1738 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1739 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1740 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1741 | return 0; |
1742 | ||
e17a4113 | 1743 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1744 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1745 | return 0; |
c906108c | 1746 | |
e17a4113 | 1747 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1748 | return 1; |
1749 | } | |
fc338970 | 1750 | \f |
c906108c | 1751 | |
7ccc1c74 JM |
1752 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1753 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1754 | unions containing such types must be 16-byte-aligned; other | |
1755 | arguments are 4-byte-aligned. */ | |
1756 | ||
1757 | static int | |
1758 | i386_16_byte_align_p (struct type *type) | |
1759 | { | |
1760 | type = check_typedef (type); | |
1761 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1762 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1763 | && TYPE_LENGTH (type) == 16) | |
1764 | return 1; | |
1765 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1766 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1767 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1768 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1769 | { | |
1770 | int i; | |
1771 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1772 | { | |
1773 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1774 | return 1; | |
1775 | } | |
1776 | } | |
1777 | return 0; | |
1778 | } | |
1779 | ||
3a1e71e3 | 1780 | static CORE_ADDR |
7d9b040b | 1781 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1782 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1783 | struct value **args, CORE_ADDR sp, int struct_return, | |
1784 | CORE_ADDR struct_addr) | |
22f8ba57 | 1785 | { |
e17a4113 | 1786 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1787 | gdb_byte buf[4]; |
acd5c798 | 1788 | int i; |
7ccc1c74 JM |
1789 | int write_pass; |
1790 | int args_space = 0; | |
acd5c798 | 1791 | |
7ccc1c74 JM |
1792 | /* Determine the total space required for arguments and struct |
1793 | return address in a first pass (allowing for 16-byte-aligned | |
1794 | arguments), then push arguments in a second pass. */ | |
1795 | ||
1796 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1797 | { |
7ccc1c74 JM |
1798 | int args_space_used = 0; |
1799 | int have_16_byte_aligned_arg = 0; | |
1800 | ||
1801 | if (struct_return) | |
1802 | { | |
1803 | if (write_pass) | |
1804 | { | |
1805 | /* Push value address. */ | |
e17a4113 | 1806 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
1807 | write_memory (sp, buf, 4); |
1808 | args_space_used += 4; | |
1809 | } | |
1810 | else | |
1811 | args_space += 4; | |
1812 | } | |
1813 | ||
1814 | for (i = 0; i < nargs; i++) | |
1815 | { | |
1816 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1817 | |
7ccc1c74 JM |
1818 | if (write_pass) |
1819 | { | |
1820 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1821 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1822 | |
7ccc1c74 JM |
1823 | write_memory (sp + args_space_used, |
1824 | value_contents_all (args[i]), len); | |
1825 | /* The System V ABI says that: | |
acd5c798 | 1826 | |
7ccc1c74 JM |
1827 | "An argument's size is increased, if necessary, to make it a |
1828 | multiple of [32-bit] words. This may require tail padding, | |
1829 | depending on the size of the argument." | |
22f8ba57 | 1830 | |
7ccc1c74 JM |
1831 | This makes sure the stack stays word-aligned. */ |
1832 | args_space_used += align_up (len, 4); | |
1833 | } | |
1834 | else | |
1835 | { | |
1836 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1837 | { | |
1838 | args_space = align_up (args_space, 16); | |
1839 | have_16_byte_aligned_arg = 1; | |
1840 | } | |
1841 | args_space += align_up (len, 4); | |
1842 | } | |
1843 | } | |
1844 | ||
1845 | if (!write_pass) | |
1846 | { | |
1847 | if (have_16_byte_aligned_arg) | |
1848 | args_space = align_up (args_space, 16); | |
1849 | sp -= args_space; | |
1850 | } | |
22f8ba57 MK |
1851 | } |
1852 | ||
acd5c798 MK |
1853 | /* Store return address. */ |
1854 | sp -= 4; | |
e17a4113 | 1855 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
1856 | write_memory (sp, buf, 4); |
1857 | ||
1858 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1859 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
1860 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
1861 | ||
1862 | /* ...and fake a frame pointer. */ | |
1863 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1864 | ||
3e210248 AC |
1865 | /* MarkK wrote: This "+ 8" is all over the place: |
1866 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1867 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1868 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1869 | definition of the stack address of a frame. Otherwise frame id |
1870 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1871 | stack address *before* the function call as a frame's CFA. On |
1872 | the i386, when %ebp is used as a frame pointer, the offset | |
1873 | between the contents %ebp and the CFA as defined by GCC. */ | |
1874 | return sp + 8; | |
22f8ba57 MK |
1875 | } |
1876 | ||
1a309862 MK |
1877 | /* These registers are used for returning integers (and on some |
1878 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1879 | size and alignment match an integer type). */ |
acd5c798 MK |
1880 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1881 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1882 | |
c5e656c1 MK |
1883 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1884 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1885 | |
3a1e71e3 | 1886 | static void |
c5e656c1 | 1887 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1888 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1889 | { |
c5e656c1 | 1890 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1891 | int len = TYPE_LENGTH (type); |
63c0089f | 1892 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1893 | |
1e8d0a7b | 1894 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1895 | { |
5716833c | 1896 | if (tdep->st0_regnum < 0) |
1a309862 | 1897 | { |
8a3fe4f8 | 1898 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1899 | memset (valbuf, 0, len); |
ef9dff19 | 1900 | return; |
1a309862 MK |
1901 | } |
1902 | ||
c6ba6f0d MK |
1903 | /* Floating-point return values can be found in %st(0). Convert |
1904 | its contents to the desired type. This is probably not | |
1905 | exactly how it would happen on the target itself, but it is | |
1906 | the best we can do. */ | |
acd5c798 | 1907 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 1908 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
1909 | } |
1910 | else | |
c5aa993b | 1911 | { |
875f8d0e UW |
1912 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1913 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1914 | |
1915 | if (len <= low_size) | |
00f8375e | 1916 | { |
0818c12a | 1917 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1918 | memcpy (valbuf, buf, len); |
1919 | } | |
d4f3574e SS |
1920 | else if (len <= (low_size + high_size)) |
1921 | { | |
0818c12a | 1922 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1923 | memcpy (valbuf, buf, low_size); |
0818c12a | 1924 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1925 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1926 | } |
1927 | else | |
8e65ff28 | 1928 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1929 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1930 | } |
1931 | } | |
1932 | ||
c5e656c1 MK |
1933 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1934 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1935 | |
3a1e71e3 | 1936 | static void |
c5e656c1 | 1937 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1938 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1939 | { |
c5e656c1 | 1940 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1941 | int len = TYPE_LENGTH (type); |
1942 | ||
1e8d0a7b | 1943 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1944 | { |
3d7f4f49 | 1945 | ULONGEST fstat; |
63c0089f | 1946 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1947 | |
5716833c | 1948 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1949 | { |
8a3fe4f8 | 1950 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1951 | return; |
1952 | } | |
1953 | ||
635b0cc1 MK |
1954 | /* Returning floating-point values is a bit tricky. Apart from |
1955 | storing the return value in %st(0), we have to simulate the | |
1956 | state of the FPU at function return point. */ | |
1957 | ||
c6ba6f0d MK |
1958 | /* Convert the value found in VALBUF to the extended |
1959 | floating-point format used by the FPU. This is probably | |
1960 | not exactly how it would happen on the target itself, but | |
1961 | it is the best we can do. */ | |
27067745 | 1962 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 1963 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1964 | |
635b0cc1 MK |
1965 | /* Set the top of the floating-point register stack to 7. The |
1966 | actual value doesn't really matter, but 7 is what a normal | |
1967 | function return would end up with if the program started out | |
1968 | with a freshly initialized FPU. */ | |
20a6ec49 | 1969 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1970 | fstat |= (7 << 11); |
20a6ec49 | 1971 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1972 | |
635b0cc1 MK |
1973 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1974 | the floating-point register stack to 7, the appropriate value | |
1975 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1976 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1977 | } |
1978 | else | |
1979 | { | |
875f8d0e UW |
1980 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1981 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1982 | |
1983 | if (len <= low_size) | |
3d7f4f49 | 1984 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1985 | else if (len <= (low_size + high_size)) |
1986 | { | |
3d7f4f49 MK |
1987 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1988 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1989 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1990 | } |
1991 | else | |
8e65ff28 | 1992 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1993 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1994 | } |
1995 | } | |
fc338970 | 1996 | \f |
ef9dff19 | 1997 | |
8201327c MK |
1998 | /* This is the variable that is set with "set struct-convention", and |
1999 | its legitimate values. */ | |
2000 | static const char default_struct_convention[] = "default"; | |
2001 | static const char pcc_struct_convention[] = "pcc"; | |
2002 | static const char reg_struct_convention[] = "reg"; | |
2003 | static const char *valid_conventions[] = | |
2004 | { | |
2005 | default_struct_convention, | |
2006 | pcc_struct_convention, | |
2007 | reg_struct_convention, | |
2008 | NULL | |
2009 | }; | |
2010 | static const char *struct_convention = default_struct_convention; | |
2011 | ||
0e4377e1 JB |
2012 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2013 | a union type, or an array type, should be returned in registers | |
2014 | for architecture GDBARCH. */ | |
c5e656c1 | 2015 | |
8201327c | 2016 | static int |
c5e656c1 | 2017 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2018 | { |
c5e656c1 MK |
2019 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2020 | enum type_code code = TYPE_CODE (type); | |
2021 | int len = TYPE_LENGTH (type); | |
8201327c | 2022 | |
0e4377e1 JB |
2023 | gdb_assert (code == TYPE_CODE_STRUCT |
2024 | || code == TYPE_CODE_UNION | |
2025 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2026 | |
2027 | if (struct_convention == pcc_struct_convention | |
2028 | || (struct_convention == default_struct_convention | |
2029 | && tdep->struct_return == pcc_struct_return)) | |
2030 | return 0; | |
2031 | ||
9edde48e MK |
2032 | /* Structures consisting of a single `float', `double' or 'long |
2033 | double' member are returned in %st(0). */ | |
2034 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2035 | { | |
2036 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2037 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2038 | return (len == 4 || len == 8 || len == 12); | |
2039 | } | |
2040 | ||
c5e656c1 MK |
2041 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2042 | } | |
2043 | ||
2044 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2045 | should be returned. If it is supposed to be returned in registers, | |
2046 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2047 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2048 | from WRITEBUF into REGCACHE. */ | |
2049 | ||
2050 | static enum return_value_convention | |
c055b101 CV |
2051 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2052 | struct type *type, struct regcache *regcache, | |
2053 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2054 | { |
2055 | enum type_code code = TYPE_CODE (type); | |
2056 | ||
5daa78cc TJB |
2057 | if (((code == TYPE_CODE_STRUCT |
2058 | || code == TYPE_CODE_UNION | |
2059 | || code == TYPE_CODE_ARRAY) | |
2060 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2061 | /* 128-bit decimal float uses the struct return convention. */ | |
2062 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2063 | { |
2064 | /* The System V ABI says that: | |
2065 | ||
2066 | "A function that returns a structure or union also sets %eax | |
2067 | to the value of the original address of the caller's area | |
2068 | before it returns. Thus when the caller receives control | |
2069 | again, the address of the returned object resides in register | |
2070 | %eax and can be used to access the object." | |
2071 | ||
2072 | So the ABI guarantees that we can always find the return | |
2073 | value just after the function has returned. */ | |
2074 | ||
0e4377e1 JB |
2075 | /* Note that the ABI doesn't mention functions returning arrays, |
2076 | which is something possible in certain languages such as Ada. | |
2077 | In this case, the value is returned as if it was wrapped in | |
2078 | a record, so the convention applied to records also applies | |
2079 | to arrays. */ | |
2080 | ||
31db7b6c MK |
2081 | if (readbuf) |
2082 | { | |
2083 | ULONGEST addr; | |
2084 | ||
2085 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2086 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2087 | } | |
2088 | ||
2089 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2090 | } | |
c5e656c1 MK |
2091 | |
2092 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2093 | `float', `double' or 'long double' member. These structures are |
2094 | returned in %st(0). For these structures, we call ourselves | |
2095 | recursively, changing TYPE into the type of the first member of | |
2096 | the structure. Since that should work for all structures that | |
2097 | have only one member, we don't bother to check the member's type | |
2098 | here. */ | |
c5e656c1 MK |
2099 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2100 | { | |
2101 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2102 | return i386_return_value (gdbarch, func_type, type, regcache, |
2103 | readbuf, writebuf); | |
c5e656c1 MK |
2104 | } |
2105 | ||
2106 | if (readbuf) | |
2107 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2108 | if (writebuf) | |
2109 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2110 | |
c5e656c1 | 2111 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2112 | } |
2113 | \f | |
2114 | ||
209bd28e UW |
2115 | /* Construct types for ISA-specific registers. */ |
2116 | struct type * | |
2117 | i386_eflags_type (struct gdbarch *gdbarch) | |
2118 | { | |
2119 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5ae96ec1 | 2120 | |
209bd28e UW |
2121 | if (!tdep->i386_eflags_type) |
2122 | { | |
2123 | struct type *type; | |
2124 | ||
e9bb382b | 2125 | type = arch_flags_type (gdbarch, "builtin_type_i386_eflags", 4); |
209bd28e UW |
2126 | append_flags_type_flag (type, 0, "CF"); |
2127 | append_flags_type_flag (type, 1, NULL); | |
2128 | append_flags_type_flag (type, 2, "PF"); | |
2129 | append_flags_type_flag (type, 4, "AF"); | |
2130 | append_flags_type_flag (type, 6, "ZF"); | |
2131 | append_flags_type_flag (type, 7, "SF"); | |
2132 | append_flags_type_flag (type, 8, "TF"); | |
2133 | append_flags_type_flag (type, 9, "IF"); | |
2134 | append_flags_type_flag (type, 10, "DF"); | |
2135 | append_flags_type_flag (type, 11, "OF"); | |
2136 | append_flags_type_flag (type, 14, "NT"); | |
2137 | append_flags_type_flag (type, 16, "RF"); | |
2138 | append_flags_type_flag (type, 17, "VM"); | |
2139 | append_flags_type_flag (type, 18, "AC"); | |
2140 | append_flags_type_flag (type, 19, "VIF"); | |
2141 | append_flags_type_flag (type, 20, "VIP"); | |
2142 | append_flags_type_flag (type, 21, "ID"); | |
2143 | ||
2144 | tdep->i386_eflags_type = type; | |
2145 | } | |
5ae96ec1 | 2146 | |
209bd28e UW |
2147 | return tdep->i386_eflags_type; |
2148 | } | |
2149 | ||
2150 | struct type * | |
2151 | i386_mxcsr_type (struct gdbarch *gdbarch) | |
5ae96ec1 | 2152 | { |
209bd28e UW |
2153 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2154 | ||
2155 | if (!tdep->i386_mxcsr_type) | |
2156 | { | |
2157 | struct type *type; | |
2158 | ||
e9bb382b | 2159 | type = arch_flags_type (gdbarch, "builtin_type_i386_mxcsr", 4); |
209bd28e UW |
2160 | append_flags_type_flag (type, 0, "IE"); |
2161 | append_flags_type_flag (type, 1, "DE"); | |
2162 | append_flags_type_flag (type, 2, "ZE"); | |
2163 | append_flags_type_flag (type, 3, "OE"); | |
2164 | append_flags_type_flag (type, 4, "UE"); | |
2165 | append_flags_type_flag (type, 5, "PE"); | |
2166 | append_flags_type_flag (type, 6, "DAZ"); | |
2167 | append_flags_type_flag (type, 7, "IM"); | |
2168 | append_flags_type_flag (type, 8, "DM"); | |
2169 | append_flags_type_flag (type, 9, "ZM"); | |
2170 | append_flags_type_flag (type, 10, "OM"); | |
2171 | append_flags_type_flag (type, 11, "UM"); | |
2172 | append_flags_type_flag (type, 12, "PM"); | |
2173 | append_flags_type_flag (type, 15, "FZ"); | |
2174 | ||
2175 | tdep->i386_mxcsr_type = type; | |
2176 | } | |
2177 | ||
2178 | return tdep->i386_mxcsr_type; | |
21b4b2f2 JB |
2179 | } |
2180 | ||
27067745 UW |
2181 | struct type * |
2182 | i387_ext_type (struct gdbarch *gdbarch) | |
2183 | { | |
2184 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2185 | ||
2186 | if (!tdep->i387_ext_type) | |
2187 | tdep->i387_ext_type | |
e9bb382b | 2188 | = arch_float_type (gdbarch, -1, "builtin_type_i387_ext", |
27067745 UW |
2189 | floatformats_i387_ext); |
2190 | ||
2191 | return tdep->i387_ext_type; | |
2192 | } | |
2193 | ||
794ac428 UW |
2194 | /* Construct vector type for MMX registers. */ |
2195 | struct type * | |
2196 | i386_mmx_type (struct gdbarch *gdbarch) | |
2197 | { | |
2198 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2199 | ||
2200 | if (!tdep->i386_mmx_type) | |
2201 | { | |
df4df182 UW |
2202 | const struct builtin_type *bt = builtin_type (gdbarch); |
2203 | ||
794ac428 UW |
2204 | /* The type we're building is this: */ |
2205 | #if 0 | |
2206 | union __gdb_builtin_type_vec64i | |
2207 | { | |
2208 | int64_t uint64; | |
2209 | int32_t v2_int32[2]; | |
2210 | int16_t v4_int16[4]; | |
2211 | int8_t v8_int8[8]; | |
2212 | }; | |
2213 | #endif | |
2214 | ||
2215 | struct type *t; | |
2216 | ||
e9bb382b UW |
2217 | t = arch_composite_type (gdbarch, |
2218 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2219 | |
2220 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2221 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2222 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2223 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2224 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2225 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2226 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2227 | |
876cecd0 | 2228 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2229 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2230 | tdep->i386_mmx_type = t; | |
2231 | } | |
2232 | ||
2233 | return tdep->i386_mmx_type; | |
2234 | } | |
2235 | ||
2236 | struct type * | |
2237 | i386_sse_type (struct gdbarch *gdbarch) | |
2238 | { | |
2239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2240 | ||
2241 | if (!tdep->i386_sse_type) | |
2242 | { | |
df4df182 UW |
2243 | const struct builtin_type *bt = builtin_type (gdbarch); |
2244 | ||
794ac428 UW |
2245 | /* The type we're building is this: */ |
2246 | #if 0 | |
2247 | union __gdb_builtin_type_vec128i | |
2248 | { | |
2249 | int128_t uint128; | |
2250 | int64_t v2_int64[2]; | |
2251 | int32_t v4_int32[4]; | |
2252 | int16_t v8_int16[8]; | |
2253 | int8_t v16_int8[16]; | |
2254 | double v2_double[2]; | |
2255 | float v4_float[4]; | |
2256 | }; | |
2257 | #endif | |
2258 | ||
2259 | struct type *t; | |
2260 | ||
e9bb382b UW |
2261 | t = arch_composite_type (gdbarch, |
2262 | "__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
794ac428 | 2263 | append_composite_type_field (t, "v4_float", |
df4df182 | 2264 | init_vector_type (bt->builtin_float, 4)); |
794ac428 | 2265 | append_composite_type_field (t, "v2_double", |
df4df182 | 2266 | init_vector_type (bt->builtin_double, 2)); |
794ac428 | 2267 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2268 | init_vector_type (bt->builtin_int8, 16)); |
794ac428 | 2269 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2270 | init_vector_type (bt->builtin_int16, 8)); |
794ac428 | 2271 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2272 | init_vector_type (bt->builtin_int32, 4)); |
794ac428 | 2273 | append_composite_type_field (t, "v2_int64", |
df4df182 UW |
2274 | init_vector_type (bt->builtin_int64, 2)); |
2275 | append_composite_type_field (t, "uint128", bt->builtin_int128); | |
794ac428 | 2276 | |
876cecd0 | 2277 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2278 | TYPE_NAME (t) = "builtin_type_vec128i"; |
2279 | tdep->i386_sse_type = t; | |
2280 | } | |
2281 | ||
2282 | return tdep->i386_sse_type; | |
2283 | } | |
2284 | ||
d7a0d72c MK |
2285 | /* Return the GDB type object for the "standard" data type of data in |
2286 | register REGNUM. Perhaps %esi and %edi should go here, but | |
2287 | potentially they could be used for things other than address. */ | |
2288 | ||
3a1e71e3 | 2289 | static struct type * |
4e259f09 | 2290 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2291 | { |
ab533587 | 2292 | if (regnum == I386_EIP_REGNUM) |
0dfff4cb | 2293 | return builtin_type (gdbarch)->builtin_func_ptr; |
ab533587 | 2294 | |
5ae96ec1 | 2295 | if (regnum == I386_EFLAGS_REGNUM) |
209bd28e | 2296 | return i386_eflags_type (gdbarch); |
5ae96ec1 | 2297 | |
ab533587 | 2298 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) |
0dfff4cb | 2299 | return builtin_type (gdbarch)->builtin_data_ptr; |
d7a0d72c | 2300 | |
20a6ec49 | 2301 | if (i386_fp_regnum_p (gdbarch, regnum)) |
27067745 | 2302 | return i387_ext_type (gdbarch); |
d7a0d72c | 2303 | |
878d9193 | 2304 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
794ac428 | 2305 | return i386_mmx_type (gdbarch); |
878d9193 | 2306 | |
5716833c | 2307 | if (i386_sse_regnum_p (gdbarch, regnum)) |
794ac428 | 2308 | return i386_sse_type (gdbarch); |
d7a0d72c | 2309 | |
20a6ec49 | 2310 | if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch))) |
209bd28e | 2311 | return i386_mxcsr_type (gdbarch); |
878d9193 | 2312 | |
0dfff4cb | 2313 | return builtin_type (gdbarch)->builtin_int; |
d7a0d72c MK |
2314 | } |
2315 | ||
28fc6740 | 2316 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2317 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2318 | |
2319 | static int | |
c86c27af | 2320 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2321 | { |
5716833c MK |
2322 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2323 | int mmxreg, fpreg; | |
28fc6740 AC |
2324 | ULONGEST fstat; |
2325 | int tos; | |
c86c27af | 2326 | |
5716833c | 2327 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2328 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2329 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2330 | fpreg = (mmxreg + tos) % 8; |
2331 | ||
20a6ec49 | 2332 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2333 | } |
2334 | ||
2335 | static void | |
2336 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2337 | int regnum, gdb_byte *buf) |
28fc6740 | 2338 | { |
5716833c | 2339 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2340 | { |
63c0089f | 2341 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2342 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2343 | ||
28fc6740 | 2344 | /* Extract (always little endian). */ |
c86c27af | 2345 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2346 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2347 | } |
2348 | else | |
2349 | regcache_raw_read (regcache, regnum, buf); | |
2350 | } | |
2351 | ||
2352 | static void | |
2353 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2354 | int regnum, const gdb_byte *buf) |
28fc6740 | 2355 | { |
5716833c | 2356 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2357 | { |
63c0089f | 2358 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2359 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2360 | ||
28fc6740 AC |
2361 | /* Read ... */ |
2362 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2363 | /* ... Modify ... (always little endian). */ | |
f837910f | 2364 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2365 | /* ... Write. */ |
2366 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2367 | } | |
2368 | else | |
2369 | regcache_raw_write (regcache, regnum, buf); | |
2370 | } | |
ff2e87ac AC |
2371 | \f |
2372 | ||
ff2e87ac AC |
2373 | /* Return the register number of the register allocated by GCC after |
2374 | REGNUM, or -1 if there is no such register. */ | |
2375 | ||
2376 | static int | |
2377 | i386_next_regnum (int regnum) | |
2378 | { | |
2379 | /* GCC allocates the registers in the order: | |
2380 | ||
2381 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2382 | ||
2383 | Since storing a variable in %esp doesn't make any sense we return | |
2384 | -1 for %ebp and for %esp itself. */ | |
2385 | static int next_regnum[] = | |
2386 | { | |
2387 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2388 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2389 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2390 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2391 | -1, -1, /* Slots for %esp and %ebp. */ | |
2392 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2393 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2394 | }; | |
2395 | ||
de5b9bb9 | 2396 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2397 | return next_regnum[regnum]; |
28fc6740 | 2398 | |
ff2e87ac AC |
2399 | return -1; |
2400 | } | |
2401 | ||
2402 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2403 | needs any special handling. */ | |
d7a0d72c | 2404 | |
3a1e71e3 | 2405 | static int |
0abe36f5 | 2406 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2407 | { |
de5b9bb9 MK |
2408 | int len = TYPE_LENGTH (type); |
2409 | ||
ff2e87ac AC |
2410 | /* Values may be spread across multiple registers. Most debugging |
2411 | formats aren't expressive enough to specify the locations, so | |
2412 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2413 | have a length that is a multiple of the word size, since GCC |
2414 | doesn't seem to put any other types into registers. */ | |
2415 | if (len > 4 && len % 4 == 0) | |
2416 | { | |
2417 | int last_regnum = regnum; | |
2418 | ||
2419 | while (len > 4) | |
2420 | { | |
2421 | last_regnum = i386_next_regnum (last_regnum); | |
2422 | len -= 4; | |
2423 | } | |
2424 | ||
2425 | if (last_regnum != -1) | |
2426 | return 1; | |
2427 | } | |
ff2e87ac | 2428 | |
0abe36f5 | 2429 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2430 | } |
2431 | ||
ff2e87ac AC |
2432 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2433 | return its contents in TO. */ | |
ac27f131 | 2434 | |
3a1e71e3 | 2435 | static void |
ff2e87ac | 2436 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2437 | struct type *type, gdb_byte *to) |
ac27f131 | 2438 | { |
20a6ec49 | 2439 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2440 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2441 | |
ff2e87ac AC |
2442 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2443 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2444 | |
20a6ec49 | 2445 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2446 | { |
d532c08f MK |
2447 | i387_register_to_value (frame, regnum, type, to); |
2448 | return; | |
8d7f6b4a | 2449 | } |
ff2e87ac | 2450 | |
fd35795f | 2451 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2452 | |
2453 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2454 | |
de5b9bb9 MK |
2455 | while (len > 0) |
2456 | { | |
2457 | gdb_assert (regnum != -1); | |
20a6ec49 | 2458 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2459 | |
42835c2b | 2460 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2461 | regnum = i386_next_regnum (regnum); |
2462 | len -= 4; | |
42835c2b | 2463 | to += 4; |
de5b9bb9 | 2464 | } |
ac27f131 MK |
2465 | } |
2466 | ||
ff2e87ac AC |
2467 | /* Write the contents FROM of a value of type TYPE into register |
2468 | REGNUM in frame FRAME. */ | |
ac27f131 | 2469 | |
3a1e71e3 | 2470 | static void |
ff2e87ac | 2471 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2472 | struct type *type, const gdb_byte *from) |
ac27f131 | 2473 | { |
de5b9bb9 | 2474 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2475 | |
20a6ec49 | 2476 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2477 | { |
d532c08f MK |
2478 | i387_value_to_register (frame, regnum, type, from); |
2479 | return; | |
2480 | } | |
3d261580 | 2481 | |
fd35795f | 2482 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2483 | |
2484 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2485 | |
de5b9bb9 MK |
2486 | while (len > 0) |
2487 | { | |
2488 | gdb_assert (regnum != -1); | |
875f8d0e | 2489 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2490 | |
42835c2b | 2491 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2492 | regnum = i386_next_regnum (regnum); |
2493 | len -= 4; | |
42835c2b | 2494 | from += 4; |
de5b9bb9 | 2495 | } |
ac27f131 | 2496 | } |
ff2e87ac | 2497 | \f |
7fdafb5a MK |
2498 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2499 | in the general-purpose register set REGSET to register cache | |
2500 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2501 | |
20187ed5 | 2502 | void |
473f17b0 MK |
2503 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2504 | int regnum, const void *gregs, size_t len) | |
2505 | { | |
9ea75c57 | 2506 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2507 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2508 | int i; |
2509 | ||
2510 | gdb_assert (len == tdep->sizeof_gregset); | |
2511 | ||
2512 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2513 | { | |
2514 | if ((regnum == i || regnum == -1) | |
2515 | && tdep->gregset_reg_offset[i] != -1) | |
2516 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2517 | } | |
2518 | } | |
2519 | ||
7fdafb5a MK |
2520 | /* Collect register REGNUM from the register cache REGCACHE and store |
2521 | it in the buffer specified by GREGS and LEN as described by the | |
2522 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2523 | all registers in REGSET. */ | |
2524 | ||
2525 | void | |
2526 | i386_collect_gregset (const struct regset *regset, | |
2527 | const struct regcache *regcache, | |
2528 | int regnum, void *gregs, size_t len) | |
2529 | { | |
2530 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2531 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2532 | int i; |
2533 | ||
2534 | gdb_assert (len == tdep->sizeof_gregset); | |
2535 | ||
2536 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2537 | { | |
2538 | if ((regnum == i || regnum == -1) | |
2539 | && tdep->gregset_reg_offset[i] != -1) | |
2540 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2541 | } | |
2542 | } | |
2543 | ||
2544 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2545 | in the floating-point register set REGSET to register cache | |
2546 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2547 | |
2548 | static void | |
2549 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2550 | int regnum, const void *fpregs, size_t len) | |
2551 | { | |
9ea75c57 | 2552 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2553 | |
66a72d25 MK |
2554 | if (len == I387_SIZEOF_FXSAVE) |
2555 | { | |
2556 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2557 | return; | |
2558 | } | |
2559 | ||
473f17b0 MK |
2560 | gdb_assert (len == tdep->sizeof_fpregset); |
2561 | i387_supply_fsave (regcache, regnum, fpregs); | |
2562 | } | |
8446b36a | 2563 | |
2f305df1 MK |
2564 | /* Collect register REGNUM from the register cache REGCACHE and store |
2565 | it in the buffer specified by FPREGS and LEN as described by the | |
2566 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2567 | all registers in REGSET. */ | |
7fdafb5a MK |
2568 | |
2569 | static void | |
2570 | i386_collect_fpregset (const struct regset *regset, | |
2571 | const struct regcache *regcache, | |
2572 | int regnum, void *fpregs, size_t len) | |
2573 | { | |
2574 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2575 | ||
2576 | if (len == I387_SIZEOF_FXSAVE) | |
2577 | { | |
2578 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2579 | return; | |
2580 | } | |
2581 | ||
2582 | gdb_assert (len == tdep->sizeof_fpregset); | |
2583 | i387_collect_fsave (regcache, regnum, fpregs); | |
2584 | } | |
2585 | ||
8446b36a MK |
2586 | /* Return the appropriate register set for the core section identified |
2587 | by SECT_NAME and SECT_SIZE. */ | |
2588 | ||
2589 | const struct regset * | |
2590 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2591 | const char *sect_name, size_t sect_size) | |
2592 | { | |
2593 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2594 | ||
2595 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2596 | { | |
2597 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2598 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2599 | i386_collect_gregset); | |
8446b36a MK |
2600 | return tdep->gregset; |
2601 | } | |
2602 | ||
66a72d25 MK |
2603 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2604 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2605 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2606 | { |
2607 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2608 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2609 | i386_collect_fpregset); | |
8446b36a MK |
2610 | return tdep->fpregset; |
2611 | } | |
2612 | ||
2613 | return NULL; | |
2614 | } | |
473f17b0 | 2615 | \f |
fc338970 | 2616 | |
fc338970 | 2617 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2618 | |
2619 | CORE_ADDR | |
e17a4113 UW |
2620 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2621 | CORE_ADDR pc, char *name) | |
c906108c | 2622 | { |
e17a4113 UW |
2623 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2624 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2625 | ||
2626 | /* jmp *(dest) */ | |
2627 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2628 | { |
e17a4113 UW |
2629 | unsigned long indirect = |
2630 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2631 | struct minimal_symbol *indsym = |
fc338970 | 2632 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2633 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2634 | |
c5aa993b | 2635 | if (symname) |
c906108c | 2636 | { |
c5aa993b JM |
2637 | if (strncmp (symname, "__imp_", 6) == 0 |
2638 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2639 | return name ? 1 : |
2640 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2641 | } |
2642 | } | |
fc338970 | 2643 | return 0; /* Not a trampoline. */ |
c906108c | 2644 | } |
fc338970 MK |
2645 | \f |
2646 | ||
10458914 DJ |
2647 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2648 | routine. */ | |
8201327c | 2649 | |
4bd207ef | 2650 | int |
10458914 | 2651 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2652 | { |
10458914 | 2653 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2654 | char *name; |
2655 | ||
2656 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2657 | return (name && strcmp ("_sigtramp", name) == 0); |
2658 | } | |
2659 | \f | |
2660 | ||
fc338970 MK |
2661 | /* We have two flavours of disassembly. The machinery on this page |
2662 | deals with switching between those. */ | |
c906108c SS |
2663 | |
2664 | static int | |
a89aa300 | 2665 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2666 | { |
5e3397bb MK |
2667 | gdb_assert (disassembly_flavor == att_flavor |
2668 | || disassembly_flavor == intel_flavor); | |
2669 | ||
2670 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2671 | constified, cast to prevent a compiler warning. */ | |
2672 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2673 | |
2674 | return print_insn_i386 (pc, info); | |
7a292a7a | 2675 | } |
fc338970 | 2676 | \f |
3ce1502b | 2677 | |
8201327c MK |
2678 | /* There are a few i386 architecture variants that differ only |
2679 | slightly from the generic i386 target. For now, we don't give them | |
2680 | their own source file, but include them here. As a consequence, | |
2681 | they'll always be included. */ | |
3ce1502b | 2682 | |
8201327c | 2683 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2684 | |
10458914 DJ |
2685 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2686 | routine. */ | |
911bc6ee | 2687 | |
8201327c | 2688 | static int |
10458914 | 2689 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2690 | { |
10458914 | 2691 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2692 | char *name; |
2693 | ||
acd5c798 MK |
2694 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2695 | currently unknown. */ | |
911bc6ee | 2696 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2697 | return (name && (strcmp ("_sigreturn", name) == 0 |
2698 | || strcmp ("_sigacthandler", name) == 0 | |
2699 | || strcmp ("sigvechandler", name) == 0)); | |
2700 | } | |
d2a7c97a | 2701 | |
10458914 DJ |
2702 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2703 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2704 | |
3a1e71e3 | 2705 | static CORE_ADDR |
10458914 | 2706 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2707 | { |
e17a4113 UW |
2708 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2709 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2710 | gdb_byte buf[4]; |
acd5c798 | 2711 | CORE_ADDR sp; |
3ce1502b | 2712 | |
10458914 | 2713 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2714 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2715 | |
e17a4113 | 2716 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2717 | } |
2718 | \f | |
3ce1502b | 2719 | |
8201327c | 2720 | /* Generic ELF. */ |
d2a7c97a | 2721 | |
8201327c MK |
2722 | void |
2723 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2724 | { | |
c4fc7f1b MK |
2725 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2726 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2727 | } |
3ce1502b | 2728 | |
8201327c | 2729 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2730 | |
8201327c MK |
2731 | void |
2732 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2733 | { | |
2734 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2735 | |
8201327c MK |
2736 | /* System V Release 4 uses ELF. */ |
2737 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2738 | |
dfe01d39 | 2739 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2740 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2741 | ||
911bc6ee | 2742 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2743 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2744 | tdep->sc_pc_offset = 36 + 14 * 4; |
2745 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2746 | |
8201327c | 2747 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2748 | } |
2749 | ||
8201327c | 2750 | /* DJGPP. */ |
3ce1502b | 2751 | |
3a1e71e3 | 2752 | static void |
8201327c | 2753 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2754 | { |
8201327c | 2755 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2756 | |
911bc6ee MK |
2757 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2758 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2759 | |
8201327c | 2760 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2761 | |
2762 | /* DJGPP does not support the SSE registers. */ | |
2763 | tdep->num_xmm_regs = 0; | |
2764 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS); | |
3d22076f EZ |
2765 | |
2766 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2767 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2768 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2769 | set_gdbarch_sdb_reg_to_regnum. */ | |
2770 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2771 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2772 | } |
8201327c | 2773 | \f |
2acceee2 | 2774 | |
38c968cf AC |
2775 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2776 | and "sse". */ | |
2777 | ||
2778 | static struct reggroup *i386_sse_reggroup; | |
2779 | static struct reggroup *i386_mmx_reggroup; | |
2780 | ||
2781 | static void | |
2782 | i386_init_reggroups (void) | |
2783 | { | |
2784 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2785 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2786 | } | |
2787 | ||
2788 | static void | |
2789 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2790 | { | |
2791 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2792 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2793 | reggroup_add (gdbarch, general_reggroup); | |
2794 | reggroup_add (gdbarch, float_reggroup); | |
2795 | reggroup_add (gdbarch, all_reggroup); | |
2796 | reggroup_add (gdbarch, save_reggroup); | |
2797 | reggroup_add (gdbarch, restore_reggroup); | |
2798 | reggroup_add (gdbarch, vector_reggroup); | |
2799 | reggroup_add (gdbarch, system_reggroup); | |
2800 | } | |
2801 | ||
2802 | int | |
2803 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2804 | struct reggroup *group) | |
2805 | { | |
5716833c MK |
2806 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2807 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2808 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2809 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2810 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2811 | |
38c968cf AC |
2812 | if (group == i386_mmx_reggroup) |
2813 | return mmx_regnum_p; | |
2814 | if (group == i386_sse_reggroup) | |
2815 | return sse_regnum_p; | |
2816 | if (group == vector_reggroup) | |
2817 | return (mmx_regnum_p || sse_regnum_p); | |
2818 | if (group == float_reggroup) | |
2819 | return fp_regnum_p; | |
2820 | if (group == general_reggroup) | |
2821 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2822 | |
38c968cf AC |
2823 | return default_register_reggroup_p (gdbarch, regnum, group); |
2824 | } | |
38c968cf | 2825 | \f |
acd5c798 | 2826 | |
f837910f MK |
2827 | /* Get the ARGIth function argument for the current function. */ |
2828 | ||
42c466d7 | 2829 | static CORE_ADDR |
143985b7 AF |
2830 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2831 | struct type *type) | |
2832 | { | |
e17a4113 UW |
2833 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2834 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 2835 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 2836 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
2837 | } |
2838 | ||
514f746b AR |
2839 | static void |
2840 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2841 | { | |
2842 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2843 | ||
2844 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2845 | adjust the PC in the regcache. */ | |
2846 | current_pc += 1; | |
2847 | regcache_write_pc (regcache, current_pc); | |
2848 | } | |
2849 | ||
2850 | ||
7ad10968 HZ |
2851 | #define PREFIX_REPZ 0x01 |
2852 | #define PREFIX_REPNZ 0x02 | |
2853 | #define PREFIX_LOCK 0x04 | |
2854 | #define PREFIX_DATA 0x08 | |
2855 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2856 | |
7ad10968 HZ |
2857 | /* operand size */ |
2858 | enum | |
2859 | { | |
2860 | OT_BYTE = 0, | |
2861 | OT_WORD, | |
2862 | OT_LONG, | |
cf648174 | 2863 | OT_QUAD, |
7ad10968 | 2864 | }; |
473f17b0 | 2865 | |
7ad10968 HZ |
2866 | /* i386 arith/logic operations */ |
2867 | enum | |
2868 | { | |
2869 | OP_ADDL, | |
2870 | OP_ORL, | |
2871 | OP_ADCL, | |
2872 | OP_SBBL, | |
2873 | OP_ANDL, | |
2874 | OP_SUBL, | |
2875 | OP_XORL, | |
2876 | OP_CMPL, | |
2877 | }; | |
5716833c | 2878 | |
7ad10968 HZ |
2879 | struct i386_record_s |
2880 | { | |
cf648174 | 2881 | struct gdbarch *gdbarch; |
7ad10968 | 2882 | struct regcache *regcache; |
df61f520 | 2883 | CORE_ADDR orig_addr; |
7ad10968 HZ |
2884 | CORE_ADDR addr; |
2885 | int aflag; | |
2886 | int dflag; | |
2887 | int override; | |
2888 | uint8_t modrm; | |
2889 | uint8_t mod, reg, rm; | |
2890 | int ot; | |
cf648174 HZ |
2891 | uint8_t rex_x; |
2892 | uint8_t rex_b; | |
2893 | int rip_offset; | |
2894 | int popl_esp_hack; | |
2895 | const int *regmap; | |
7ad10968 | 2896 | }; |
5716833c | 2897 | |
7ad10968 HZ |
2898 | /* Parse "modrm" part in current memory address that irp->addr point to |
2899 | Return -1 if something wrong. */ | |
5716833c | 2900 | |
7ad10968 HZ |
2901 | static int |
2902 | i386_record_modrm (struct i386_record_s *irp) | |
2903 | { | |
cf648174 | 2904 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 2905 | |
7ad10968 HZ |
2906 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
2907 | { | |
2908 | if (record_debug) | |
2909 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
2910 | "addr %s len = 1.\n"), |
2911 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2912 | return -1; |
2913 | } | |
2914 | irp->addr++; | |
2915 | irp->mod = (irp->modrm >> 6) & 3; | |
2916 | irp->reg = (irp->modrm >> 3) & 7; | |
2917 | irp->rm = irp->modrm & 7; | |
5716833c | 2918 | |
7ad10968 HZ |
2919 | return 0; |
2920 | } | |
d2a7c97a | 2921 | |
7ad10968 HZ |
2922 | /* Get the memory address that current instruction write to and set it to |
2923 | the argument "addr". | |
2924 | Return -1 if something wrong. */ | |
8201327c | 2925 | |
7ad10968 | 2926 | static int |
cf648174 | 2927 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 2928 | { |
cf648174 | 2929 | struct gdbarch *gdbarch = irp->gdbarch; |
7ad10968 | 2930 | uint8_t tmpu8; |
cf648174 HZ |
2931 | int16_t tmpi16; |
2932 | int32_t tmpi32; | |
2933 | ULONGEST tmpulongest; | |
21d0e8a4 | 2934 | |
7ad10968 HZ |
2935 | *addr = 0; |
2936 | if (irp->aflag) | |
2937 | { | |
2938 | /* 32 bits */ | |
2939 | int havesib = 0; | |
2940 | uint8_t scale = 0; | |
2941 | uint8_t index = 0; | |
2942 | uint8_t base = irp->rm; | |
896fb97d | 2943 | |
7ad10968 HZ |
2944 | if (base == 4) |
2945 | { | |
2946 | havesib = 1; | |
2947 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2948 | { | |
2949 | if (record_debug) | |
2950 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2951 | "at addr %s len = 1.\n"), |
2952 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2953 | return -1; |
2954 | } | |
2955 | irp->addr++; | |
2956 | scale = (tmpu8 >> 6) & 3; | |
cf648174 | 2957 | index = ((tmpu8 >> 3) & 7) | irp->rex_x; |
7ad10968 HZ |
2958 | base = (tmpu8 & 7); |
2959 | } | |
cf648174 | 2960 | base |= irp->rex_b; |
21d0e8a4 | 2961 | |
7ad10968 HZ |
2962 | switch (irp->mod) |
2963 | { | |
2964 | case 0: | |
2965 | if ((base & 7) == 5) | |
2966 | { | |
2967 | base = 0xff; | |
cf648174 | 2968 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
2969 | { |
2970 | if (record_debug) | |
2971 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2972 | "memory at addr %s len = 4.\n"), |
2973 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2974 | return -1; |
2975 | } | |
2976 | irp->addr += 4; | |
cf648174 HZ |
2977 | *addr = tmpi32; |
2978 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) | |
2979 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 HZ |
2980 | } |
2981 | else | |
2982 | { | |
2983 | *addr = 0; | |
2984 | } | |
2985 | break; | |
2986 | case 1: | |
2987 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2988 | { | |
2989 | if (record_debug) | |
2990 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2991 | "at addr %s len = 1.\n"), |
2992 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2993 | return -1; |
2994 | } | |
2995 | irp->addr++; | |
2996 | *addr = (int8_t) tmpu8; | |
2997 | break; | |
2998 | case 2: | |
cf648174 | 2999 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
3000 | { |
3001 | if (record_debug) | |
3002 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3003 | "at addr %s len = 4.\n"), |
3004 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3005 | return -1; |
3006 | } | |
cf648174 | 3007 | *addr = tmpi32; |
7ad10968 HZ |
3008 | irp->addr += 4; |
3009 | break; | |
3010 | } | |
356a6b3e | 3011 | |
cf648174 | 3012 | tmpulongest = 0; |
7ad10968 | 3013 | if (base != 0xff) |
cf648174 HZ |
3014 | { |
3015 | if (base == 4 && irp->popl_esp_hack) | |
3016 | *addr += irp->popl_esp_hack; | |
3017 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
3018 | &tmpulongest); | |
7ad10968 | 3019 | } |
cf648174 HZ |
3020 | if (irp->aflag == 2) |
3021 | { | |
3022 | *addr += tmpulongest; | |
3023 | } | |
3024 | else | |
3025 | *addr = (uint32_t) (tmpulongest + *addr); | |
c4fc7f1b | 3026 | |
7ad10968 HZ |
3027 | if (havesib && (index != 4 || scale != 0)) |
3028 | { | |
cf648174 HZ |
3029 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
3030 | &tmpulongest); | |
3031 | if (irp->aflag == 2) | |
3032 | *addr += tmpulongest << scale; | |
3033 | else | |
3034 | *addr = (uint32_t) (*addr + (tmpulongest << scale)); | |
7ad10968 HZ |
3035 | } |
3036 | } | |
3037 | else | |
3038 | { | |
3039 | /* 16 bits */ | |
3040 | switch (irp->mod) | |
3041 | { | |
3042 | case 0: | |
3043 | if (irp->rm == 6) | |
3044 | { | |
3045 | if (target_read_memory | |
cf648174 | 3046 | (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
3047 | { |
3048 | if (record_debug) | |
3049 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3050 | "memory at addr %s len = 2.\n"), |
3051 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3052 | return -1; |
3053 | } | |
3054 | irp->addr += 2; | |
cf648174 | 3055 | *addr = tmpi16; |
7ad10968 HZ |
3056 | irp->rm = 0; |
3057 | goto no_rm; | |
3058 | } | |
3059 | else | |
3060 | { | |
3061 | *addr = 0; | |
3062 | } | |
3063 | break; | |
3064 | case 1: | |
3065 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
3066 | { | |
3067 | if (record_debug) | |
3068 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3069 | "at addr %s len = 1.\n"), |
3070 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3071 | return -1; |
3072 | } | |
3073 | irp->addr++; | |
3074 | *addr = (int8_t) tmpu8; | |
3075 | break; | |
3076 | case 2: | |
cf648174 | 3077 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
3078 | { |
3079 | if (record_debug) | |
3080 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3081 | "at addr %s len = 2.\n"), |
3082 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3083 | return -1; |
3084 | } | |
3085 | irp->addr += 2; | |
cf648174 | 3086 | *addr = tmpi16; |
7ad10968 HZ |
3087 | break; |
3088 | } | |
c4fc7f1b | 3089 | |
7ad10968 HZ |
3090 | switch (irp->rm) |
3091 | { | |
3092 | case 0: | |
cf648174 HZ |
3093 | regcache_raw_read_unsigned (irp->regcache, |
3094 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3095 | &tmpulongest); | |
3096 | *addr = (uint32_t) (*addr + tmpulongest); | |
3097 | regcache_raw_read_unsigned (irp->regcache, | |
3098 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3099 | &tmpulongest); | |
3100 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3101 | break; |
3102 | case 1: | |
cf648174 HZ |
3103 | regcache_raw_read_unsigned (irp->regcache, |
3104 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3105 | &tmpulongest); | |
3106 | *addr = (uint32_t) (*addr + tmpulongest); | |
3107 | regcache_raw_read_unsigned (irp->regcache, | |
3108 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3109 | &tmpulongest); | |
3110 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3111 | break; |
3112 | case 2: | |
cf648174 HZ |
3113 | regcache_raw_read_unsigned (irp->regcache, |
3114 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3115 | &tmpulongest); | |
3116 | *addr = (uint32_t) (*addr + tmpulongest); | |
3117 | regcache_raw_read_unsigned (irp->regcache, | |
3118 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3119 | &tmpulongest); | |
3120 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3121 | break; |
3122 | case 3: | |
cf648174 HZ |
3123 | regcache_raw_read_unsigned (irp->regcache, |
3124 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3125 | &tmpulongest); | |
3126 | *addr = (uint32_t) (*addr + tmpulongest); | |
3127 | regcache_raw_read_unsigned (irp->regcache, | |
3128 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3129 | &tmpulongest); | |
3130 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3131 | break; |
3132 | case 4: | |
cf648174 HZ |
3133 | regcache_raw_read_unsigned (irp->regcache, |
3134 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3135 | &tmpulongest); | |
3136 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3137 | break; |
3138 | case 5: | |
cf648174 HZ |
3139 | regcache_raw_read_unsigned (irp->regcache, |
3140 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3141 | &tmpulongest); | |
3142 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3143 | break; |
3144 | case 6: | |
cf648174 HZ |
3145 | regcache_raw_read_unsigned (irp->regcache, |
3146 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3147 | &tmpulongest); | |
3148 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3149 | break; |
3150 | case 7: | |
cf648174 HZ |
3151 | regcache_raw_read_unsigned (irp->regcache, |
3152 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3153 | &tmpulongest); | |
3154 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3155 | break; |
3156 | } | |
3157 | *addr &= 0xffff; | |
3158 | } | |
c4fc7f1b | 3159 | |
01fe1b41 | 3160 | no_rm: |
7ad10968 HZ |
3161 | return 0; |
3162 | } | |
c4fc7f1b | 3163 | |
7ad10968 HZ |
3164 | /* Record the value of the memory that willbe changed in current instruction |
3165 | to "record_arch_list". | |
3166 | Return -1 if something wrong. */ | |
356a6b3e | 3167 | |
7ad10968 HZ |
3168 | static int |
3169 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3170 | { | |
cf648174 HZ |
3171 | struct gdbarch *gdbarch = irp->gdbarch; |
3172 | uint64_t addr; | |
356a6b3e | 3173 | |
d7877f7e | 3174 | if (irp->override >= 0) |
7ad10968 | 3175 | { |
df61f520 HZ |
3176 | warning (_("Process record ignores the memory change " |
3177 | "of instruction at address %s because it " | |
3178 | "can't get the value of the segment register."), | |
3179 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3180 | return 0; |
3181 | } | |
61113f8b | 3182 | |
7ad10968 HZ |
3183 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3184 | return -1; | |
96297dab | 3185 | |
7ad10968 HZ |
3186 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3187 | return -1; | |
a62cc96e | 3188 | |
7ad10968 HZ |
3189 | return 0; |
3190 | } | |
b6197528 | 3191 | |
cf648174 HZ |
3192 | /* Record the push operation to "record_arch_list". |
3193 | Return -1 if something wrong. */ | |
3194 | ||
3195 | static int | |
3196 | i386_record_push (struct i386_record_s *irp, int size) | |
3197 | { | |
3198 | ULONGEST tmpulongest; | |
3199 | ||
3200 | if (record_arch_list_add_reg (irp->regcache, | |
3201 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3202 | return -1; | |
3203 | regcache_raw_read_unsigned (irp->regcache, | |
3204 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
3205 | &tmpulongest); | |
3206 | if (record_arch_list_add_mem ((CORE_ADDR) tmpulongest - size, size)) | |
3207 | return -1; | |
3208 | ||
3209 | return 0; | |
3210 | } | |
3211 | ||
0289bdd7 MS |
3212 | |
3213 | /* Defines contents to record. */ | |
3214 | #define I386_SAVE_FPU_REGS 0xfffd | |
3215 | #define I386_SAVE_FPU_ENV 0xfffe | |
3216 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3217 | ||
3218 | /* Record the value of floating point registers which will be changed by the | |
3219 | current instruction to "record_arch_list". Return -1 if something is wrong. | |
3220 | */ | |
3221 | ||
3222 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3223 | struct i386_record_s *ir, | |
3224 | uint32_t iregnum) | |
3225 | { | |
3226 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3227 | int i; | |
3228 | ||
3229 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3230 | happen. Currently we store st0-st7 registers, but we need not store all | |
3231 | registers all the time, in future we use ftag register and record only | |
3232 | those who are not marked as an empty. */ | |
3233 | ||
3234 | if (I386_SAVE_FPU_REGS == iregnum) | |
3235 | { | |
3236 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3237 | { | |
3238 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3239 | return -1; | |
3240 | } | |
3241 | } | |
3242 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3243 | { | |
3244 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3245 | { | |
3246 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3247 | return -1; | |
3248 | } | |
3249 | } | |
3250 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3251 | { | |
3252 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3253 | { | |
3254 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3255 | return -1; | |
3256 | } | |
3257 | } | |
3258 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3259 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3260 | { | |
3261 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3262 | return -1; | |
3263 | } | |
3264 | else | |
3265 | { | |
3266 | /* Parameter error. */ | |
3267 | return -1; | |
3268 | } | |
3269 | if(I386_SAVE_FPU_ENV != iregnum) | |
3270 | { | |
3271 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3272 | { | |
3273 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3274 | return -1; | |
3275 | } | |
3276 | } | |
3277 | return 0; | |
3278 | } | |
3279 | ||
7ad10968 HZ |
3280 | /* Parse the current instruction and record the values of the registers and |
3281 | memory that will be changed in current instruction to "record_arch_list". | |
3282 | Return -1 if something wrong. */ | |
8201327c | 3283 | |
cf648174 HZ |
3284 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3285 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3286 | ||
a6b808b4 | 3287 | int |
7ad10968 HZ |
3288 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
3289 | CORE_ADDR addr) | |
3290 | { | |
3291 | int prefixes = 0; | |
3292 | uint8_t tmpu8; | |
3293 | uint16_t tmpu16; | |
3294 | uint32_t tmpu32; | |
cf648174 | 3295 | ULONGEST tmpulongest; |
7ad10968 HZ |
3296 | uint32_t opcode; |
3297 | struct i386_record_s ir; | |
0289bdd7 | 3298 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3299 | int rex = 0; |
3300 | uint8_t rex_w = -1; | |
3301 | uint8_t rex_r = 0; | |
7ad10968 | 3302 | |
8408d274 | 3303 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 HZ |
3304 | ir.regcache = regcache; |
3305 | ir.addr = addr; | |
df61f520 | 3306 | ir.orig_addr = addr; |
7ad10968 HZ |
3307 | ir.aflag = 1; |
3308 | ir.dflag = 1; | |
cf648174 HZ |
3309 | ir.override = -1; |
3310 | ir.popl_esp_hack = 0; | |
3311 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; | |
3312 | ir.gdbarch = gdbarch; | |
7ad10968 HZ |
3313 | |
3314 | if (record_debug > 1) | |
3315 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3316 | "addr = %s\n", |
3317 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3318 | |
3319 | /* prefixes */ | |
3320 | while (1) | |
3321 | { | |
3322 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3323 | { | |
3324 | if (record_debug) | |
3325 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3326 | "addr %s len = 1.\n"), |
3327 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3328 | return -1; |
3329 | } | |
3330 | ir.addr++; | |
01fe1b41 | 3331 | switch (tmpu8) /* Instruction prefixes */ |
7ad10968 | 3332 | { |
01fe1b41 | 3333 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
3334 | prefixes |= PREFIX_REPZ; |
3335 | break; | |
01fe1b41 | 3336 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
3337 | prefixes |= PREFIX_REPNZ; |
3338 | break; | |
01fe1b41 | 3339 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
3340 | prefixes |= PREFIX_LOCK; |
3341 | break; | |
01fe1b41 | 3342 | case CS_PREFIX_OPCODE: |
cf648174 | 3343 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 3344 | break; |
01fe1b41 | 3345 | case SS_PREFIX_OPCODE: |
cf648174 | 3346 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 3347 | break; |
01fe1b41 | 3348 | case DS_PREFIX_OPCODE: |
cf648174 | 3349 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 3350 | break; |
01fe1b41 | 3351 | case ES_PREFIX_OPCODE: |
cf648174 | 3352 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 3353 | break; |
01fe1b41 | 3354 | case FS_PREFIX_OPCODE: |
cf648174 | 3355 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 3356 | break; |
01fe1b41 | 3357 | case GS_PREFIX_OPCODE: |
cf648174 | 3358 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 3359 | break; |
01fe1b41 | 3360 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
3361 | prefixes |= PREFIX_DATA; |
3362 | break; | |
01fe1b41 | 3363 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
3364 | prefixes |= PREFIX_ADDR; |
3365 | break; | |
d691bec7 MS |
3366 | case 0x40: /* i386 inc %eax */ |
3367 | case 0x41: /* i386 inc %ecx */ | |
3368 | case 0x42: /* i386 inc %edx */ | |
3369 | case 0x43: /* i386 inc %ebx */ | |
3370 | case 0x44: /* i386 inc %esp */ | |
3371 | case 0x45: /* i386 inc %ebp */ | |
3372 | case 0x46: /* i386 inc %esi */ | |
3373 | case 0x47: /* i386 inc %edi */ | |
3374 | case 0x48: /* i386 dec %eax */ | |
3375 | case 0x49: /* i386 dec %ecx */ | |
3376 | case 0x4a: /* i386 dec %edx */ | |
3377 | case 0x4b: /* i386 dec %ebx */ | |
3378 | case 0x4c: /* i386 dec %esp */ | |
3379 | case 0x4d: /* i386 dec %ebp */ | |
3380 | case 0x4e: /* i386 dec %esi */ | |
3381 | case 0x4f: /* i386 dec %edi */ | |
3382 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3383 | { |
3384 | /* REX */ | |
3385 | rex = 1; | |
3386 | rex_w = (tmpu8 >> 3) & 1; | |
3387 | rex_r = (tmpu8 & 0x4) << 1; | |
3388 | ir.rex_x = (tmpu8 & 0x2) << 2; | |
3389 | ir.rex_b = (tmpu8 & 0x1) << 3; | |
3390 | } | |
d691bec7 MS |
3391 | else /* 32 bit target */ |
3392 | goto out_prefixes; | |
cf648174 | 3393 | break; |
7ad10968 HZ |
3394 | default: |
3395 | goto out_prefixes; | |
3396 | break; | |
3397 | } | |
3398 | } | |
01fe1b41 | 3399 | out_prefixes: |
cf648174 HZ |
3400 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3401 | { | |
3402 | ir.dflag = 2; | |
3403 | } | |
3404 | else | |
3405 | { | |
3406 | if (prefixes & PREFIX_DATA) | |
3407 | ir.dflag ^= 1; | |
3408 | } | |
7ad10968 HZ |
3409 | if (prefixes & PREFIX_ADDR) |
3410 | ir.aflag ^= 1; | |
cf648174 HZ |
3411 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3412 | ir.aflag = 2; | |
7ad10968 HZ |
3413 | |
3414 | /* now check op code */ | |
3415 | opcode = (uint32_t) tmpu8; | |
01fe1b41 | 3416 | reswitch: |
7ad10968 HZ |
3417 | switch (opcode) |
3418 | { | |
3419 | case 0x0f: | |
3420 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3421 | { | |
3422 | if (record_debug) | |
3423 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3424 | "addr %s len = 1.\n"), |
3425 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3426 | return -1; |
3427 | } | |
3428 | ir.addr++; | |
3429 | opcode = (uint16_t) tmpu8 | 0x0f00; | |
3430 | goto reswitch; | |
3431 | break; | |
93924b6b | 3432 | |
a38bba38 | 3433 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
3434 | case 0x01: |
3435 | case 0x02: | |
3436 | case 0x03: | |
3437 | case 0x04: | |
3438 | case 0x05: | |
3439 | case 0x08: | |
3440 | case 0x09: | |
3441 | case 0x0a: | |
3442 | case 0x0b: | |
3443 | case 0x0c: | |
3444 | case 0x0d: | |
3445 | case 0x10: | |
3446 | case 0x11: | |
3447 | case 0x12: | |
3448 | case 0x13: | |
3449 | case 0x14: | |
3450 | case 0x15: | |
3451 | case 0x18: | |
3452 | case 0x19: | |
3453 | case 0x1a: | |
3454 | case 0x1b: | |
3455 | case 0x1c: | |
3456 | case 0x1d: | |
3457 | case 0x20: | |
3458 | case 0x21: | |
3459 | case 0x22: | |
3460 | case 0x23: | |
3461 | case 0x24: | |
3462 | case 0x25: | |
3463 | case 0x28: | |
3464 | case 0x29: | |
3465 | case 0x2a: | |
3466 | case 0x2b: | |
3467 | case 0x2c: | |
3468 | case 0x2d: | |
3469 | case 0x30: | |
3470 | case 0x31: | |
3471 | case 0x32: | |
3472 | case 0x33: | |
3473 | case 0x34: | |
3474 | case 0x35: | |
3475 | case 0x38: | |
3476 | case 0x39: | |
3477 | case 0x3a: | |
3478 | case 0x3b: | |
3479 | case 0x3c: | |
3480 | case 0x3d: | |
3481 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3482 | { | |
3483 | if ((opcode & 1) == 0) | |
3484 | ir.ot = OT_BYTE; | |
3485 | else | |
3486 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3487 | |
7ad10968 HZ |
3488 | switch ((opcode >> 1) & 3) |
3489 | { | |
a38bba38 | 3490 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
3491 | if (i386_record_modrm (&ir)) |
3492 | return -1; | |
3493 | if (ir.mod != 3) | |
3494 | { | |
3495 | if (i386_record_lea_modrm (&ir)) | |
3496 | return -1; | |
3497 | } | |
3498 | else | |
3499 | { | |
cf648174 HZ |
3500 | ir.rm |= ir.rex_b; |
3501 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3502 | ir.rm &= 0x3; |
cf648174 | 3503 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3504 | } |
3505 | break; | |
a38bba38 | 3506 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
3507 | if (i386_record_modrm (&ir)) |
3508 | return -1; | |
cf648174 HZ |
3509 | ir.reg |= rex_r; |
3510 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3511 | ir.reg &= 0x3; |
cf648174 | 3512 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3513 | break; |
a38bba38 | 3514 | case 2: /* OP A, Iv */ |
cf648174 | 3515 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3516 | break; |
3517 | } | |
3518 | } | |
cf648174 | 3519 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3520 | break; |
42fdc8df | 3521 | |
a38bba38 | 3522 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
3523 | case 0x81: |
3524 | case 0x82: | |
3525 | case 0x83: | |
3526 | if (i386_record_modrm (&ir)) | |
3527 | return -1; | |
8201327c | 3528 | |
7ad10968 HZ |
3529 | if (ir.reg != OP_CMPL) |
3530 | { | |
3531 | if ((opcode & 1) == 0) | |
3532 | ir.ot = OT_BYTE; | |
3533 | else | |
3534 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3535 | |
7ad10968 HZ |
3536 | if (ir.mod != 3) |
3537 | { | |
cf648174 HZ |
3538 | if (opcode == 0x83) |
3539 | ir.rip_offset = 1; | |
3540 | else | |
3541 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3542 | if (i386_record_lea_modrm (&ir)) |
3543 | return -1; | |
3544 | } | |
3545 | else | |
cf648174 | 3546 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3547 | } |
cf648174 | 3548 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3549 | break; |
5e3397bb | 3550 | |
a38bba38 | 3551 | case 0x40: /* inc */ |
7ad10968 HZ |
3552 | case 0x41: |
3553 | case 0x42: | |
3554 | case 0x43: | |
3555 | case 0x44: | |
3556 | case 0x45: | |
3557 | case 0x46: | |
3558 | case 0x47: | |
a38bba38 MS |
3559 | |
3560 | case 0x48: /* dec */ | |
7ad10968 HZ |
3561 | case 0x49: |
3562 | case 0x4a: | |
3563 | case 0x4b: | |
3564 | case 0x4c: | |
3565 | case 0x4d: | |
3566 | case 0x4e: | |
3567 | case 0x4f: | |
a38bba38 | 3568 | |
cf648174 HZ |
3569 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3570 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3571 | break; |
acd5c798 | 3572 | |
a38bba38 | 3573 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
3574 | case 0xf7: |
3575 | if ((opcode & 1) == 0) | |
3576 | ir.ot = OT_BYTE; | |
3577 | else | |
3578 | ir.ot = ir.dflag + OT_WORD; | |
3579 | if (i386_record_modrm (&ir)) | |
3580 | return -1; | |
acd5c798 | 3581 | |
cf648174 HZ |
3582 | if (ir.mod != 3 && ir.reg == 0) |
3583 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3584 | ||
7ad10968 HZ |
3585 | switch (ir.reg) |
3586 | { | |
a38bba38 | 3587 | case 0: /* test */ |
cf648174 | 3588 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3589 | break; |
a38bba38 MS |
3590 | case 2: /* not */ |
3591 | case 3: /* neg */ | |
7ad10968 HZ |
3592 | if (ir.mod != 3) |
3593 | { | |
3594 | if (i386_record_lea_modrm (&ir)) | |
3595 | return -1; | |
3596 | } | |
3597 | else | |
3598 | { | |
cf648174 HZ |
3599 | ir.rm |= ir.rex_b; |
3600 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3601 | ir.rm &= 0x3; |
cf648174 | 3602 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3603 | } |
a38bba38 | 3604 | if (ir.reg == 3) /* neg */ |
cf648174 | 3605 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3606 | break; |
a38bba38 MS |
3607 | case 4: /* mul */ |
3608 | case 5: /* imul */ | |
3609 | case 6: /* div */ | |
3610 | case 7: /* idiv */ | |
cf648174 | 3611 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3612 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3613 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3614 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3615 | break; |
3616 | default: | |
3617 | ir.addr -= 2; | |
3618 | opcode = opcode << 8 | ir.modrm; | |
3619 | goto no_support; | |
3620 | break; | |
3621 | } | |
3622 | break; | |
3623 | ||
a38bba38 MS |
3624 | case 0xfe: /* GRP4 */ |
3625 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
3626 | if (i386_record_modrm (&ir)) |
3627 | return -1; | |
3628 | if (ir.reg >= 2 && opcode == 0xfe) | |
3629 | { | |
3630 | ir.addr -= 2; | |
3631 | opcode = opcode << 8 | ir.modrm; | |
3632 | goto no_support; | |
3633 | } | |
7ad10968 HZ |
3634 | switch (ir.reg) |
3635 | { | |
a38bba38 MS |
3636 | case 0: /* inc */ |
3637 | case 1: /* dec */ | |
cf648174 HZ |
3638 | if ((opcode & 1) == 0) |
3639 | ir.ot = OT_BYTE; | |
3640 | else | |
3641 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3642 | if (ir.mod != 3) |
3643 | { | |
3644 | if (i386_record_lea_modrm (&ir)) | |
3645 | return -1; | |
3646 | } | |
3647 | else | |
3648 | { | |
cf648174 HZ |
3649 | ir.rm |= ir.rex_b; |
3650 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3651 | ir.rm &= 0x3; |
cf648174 | 3652 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3653 | } |
cf648174 | 3654 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3655 | break; |
a38bba38 | 3656 | case 2: /* call */ |
cf648174 HZ |
3657 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3658 | ir.dflag = 2; | |
3659 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3660 | return -1; |
cf648174 | 3661 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3662 | break; |
a38bba38 | 3663 | case 3: /* lcall */ |
cf648174 HZ |
3664 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3665 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3666 | return -1; |
cf648174 | 3667 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3668 | break; |
a38bba38 MS |
3669 | case 4: /* jmp */ |
3670 | case 5: /* ljmp */ | |
cf648174 HZ |
3671 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3672 | break; | |
a38bba38 | 3673 | case 6: /* push */ |
cf648174 HZ |
3674 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3675 | ir.dflag = 2; | |
3676 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3677 | return -1; | |
7ad10968 HZ |
3678 | break; |
3679 | default: | |
3680 | ir.addr -= 2; | |
3681 | opcode = opcode << 8 | ir.modrm; | |
3682 | goto no_support; | |
3683 | break; | |
3684 | } | |
3685 | break; | |
3686 | ||
a38bba38 | 3687 | case 0x84: /* test */ |
7ad10968 HZ |
3688 | case 0x85: |
3689 | case 0xa8: | |
3690 | case 0xa9: | |
cf648174 | 3691 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3692 | break; |
3693 | ||
a38bba38 | 3694 | case 0x98: /* CWDE/CBW */ |
cf648174 | 3695 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3696 | break; |
3697 | ||
a38bba38 | 3698 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
3699 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3700 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3701 | break; |
3702 | ||
a38bba38 | 3703 | case 0x0faf: /* imul */ |
7ad10968 HZ |
3704 | case 0x69: |
3705 | case 0x6b: | |
3706 | ir.ot = ir.dflag + OT_WORD; | |
3707 | if (i386_record_modrm (&ir)) | |
3708 | return -1; | |
cf648174 HZ |
3709 | if (opcode == 0x69) |
3710 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3711 | else if (opcode == 0x6b) | |
3712 | ir.rip_offset = 1; | |
3713 | ir.reg |= rex_r; | |
3714 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3715 | ir.reg &= 0x3; |
cf648174 HZ |
3716 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3717 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3718 | break; |
3719 | ||
a38bba38 | 3720 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
3721 | case 0x0fc1: |
3722 | if ((opcode & 1) == 0) | |
3723 | ir.ot = OT_BYTE; | |
3724 | else | |
3725 | ir.ot = ir.dflag + OT_WORD; | |
3726 | if (i386_record_modrm (&ir)) | |
3727 | return -1; | |
cf648174 | 3728 | ir.reg |= rex_r; |
7ad10968 HZ |
3729 | if (ir.mod == 3) |
3730 | { | |
cf648174 | 3731 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3732 | ir.reg &= 0x3; |
cf648174 HZ |
3733 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3734 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3735 | ir.rm &= 0x3; |
cf648174 | 3736 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3737 | } |
3738 | else | |
3739 | { | |
3740 | if (i386_record_lea_modrm (&ir)) | |
3741 | return -1; | |
cf648174 | 3742 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3743 | ir.reg &= 0x3; |
cf648174 | 3744 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3745 | } |
cf648174 | 3746 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3747 | break; |
3748 | ||
a38bba38 | 3749 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
3750 | case 0x0fb1: |
3751 | if ((opcode & 1) == 0) | |
3752 | ir.ot = OT_BYTE; | |
3753 | else | |
3754 | ir.ot = ir.dflag + OT_WORD; | |
3755 | if (i386_record_modrm (&ir)) | |
3756 | return -1; | |
3757 | if (ir.mod == 3) | |
3758 | { | |
cf648174 HZ |
3759 | ir.reg |= rex_r; |
3760 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
3761 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3762 | ir.reg &= 0x3; |
cf648174 | 3763 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3764 | } |
3765 | else | |
3766 | { | |
cf648174 | 3767 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3768 | if (i386_record_lea_modrm (&ir)) |
3769 | return -1; | |
3770 | } | |
cf648174 | 3771 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3772 | break; |
3773 | ||
a38bba38 | 3774 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
3775 | if (i386_record_modrm (&ir)) |
3776 | return -1; | |
3777 | if (ir.mod == 3) | |
3778 | { | |
3779 | ir.addr -= 2; | |
3780 | opcode = opcode << 8 | ir.modrm; | |
3781 | goto no_support; | |
3782 | } | |
cf648174 HZ |
3783 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3785 | if (i386_record_lea_modrm (&ir)) |
3786 | return -1; | |
cf648174 | 3787 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3788 | break; |
3789 | ||
a38bba38 | 3790 | case 0x50: /* push */ |
7ad10968 HZ |
3791 | case 0x51: |
3792 | case 0x52: | |
3793 | case 0x53: | |
3794 | case 0x54: | |
3795 | case 0x55: | |
3796 | case 0x56: | |
3797 | case 0x57: | |
3798 | case 0x68: | |
3799 | case 0x6a: | |
cf648174 HZ |
3800 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3801 | ir.dflag = 2; | |
3802 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3803 | return -1; | |
3804 | break; | |
3805 | ||
a38bba38 MS |
3806 | case 0x06: /* push es */ |
3807 | case 0x0e: /* push cs */ | |
3808 | case 0x16: /* push ss */ | |
3809 | case 0x1e: /* push ds */ | |
cf648174 HZ |
3810 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3811 | { | |
3812 | ir.addr -= 1; | |
3813 | goto no_support; | |
3814 | } | |
3815 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3816 | return -1; | |
3817 | break; | |
3818 | ||
a38bba38 MS |
3819 | case 0x0fa0: /* push fs */ |
3820 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
3821 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3822 | { | |
3823 | ir.addr -= 2; | |
3824 | goto no_support; | |
3825 | } | |
3826 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3827 | return -1; |
cf648174 HZ |
3828 | break; |
3829 | ||
a38bba38 | 3830 | case 0x60: /* pusha */ |
cf648174 HZ |
3831 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3832 | { | |
3833 | ir.addr -= 1; | |
3834 | goto no_support; | |
3835 | } | |
3836 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
3837 | return -1; |
3838 | break; | |
3839 | ||
a38bba38 | 3840 | case 0x58: /* pop */ |
7ad10968 HZ |
3841 | case 0x59: |
3842 | case 0x5a: | |
3843 | case 0x5b: | |
3844 | case 0x5c: | |
3845 | case 0x5d: | |
3846 | case 0x5e: | |
3847 | case 0x5f: | |
cf648174 HZ |
3848 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3849 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
3850 | break; |
3851 | ||
a38bba38 | 3852 | case 0x61: /* popa */ |
cf648174 HZ |
3853 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3854 | { | |
3855 | ir.addr -= 1; | |
3856 | goto no_support; | |
7ad10968 | 3857 | } |
cf648174 HZ |
3858 | for (tmpu8 = X86_RECORD_REAX_REGNUM; tmpu8 <= X86_RECORD_REDI_REGNUM; |
3859 | tmpu8++) | |
3860 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); | |
7ad10968 HZ |
3861 | break; |
3862 | ||
a38bba38 | 3863 | case 0x8f: /* pop */ |
cf648174 HZ |
3864 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3865 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
3866 | else | |
3867 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3868 | if (i386_record_modrm (&ir)) |
3869 | return -1; | |
3870 | if (ir.mod == 3) | |
cf648174 | 3871 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
3872 | else |
3873 | { | |
cf648174 | 3874 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
3875 | if (i386_record_lea_modrm (&ir)) |
3876 | return -1; | |
3877 | } | |
cf648174 | 3878 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
3879 | break; |
3880 | ||
a38bba38 | 3881 | case 0xc8: /* enter */ |
cf648174 HZ |
3882 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
3883 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3884 | ir.dflag = 2; | |
3885 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
3886 | return -1; |
3887 | break; | |
3888 | ||
a38bba38 | 3889 | case 0xc9: /* leave */ |
cf648174 HZ |
3890 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3891 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
3892 | break; |
3893 | ||
a38bba38 | 3894 | case 0x07: /* pop es */ |
cf648174 HZ |
3895 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3896 | { | |
3897 | ir.addr -= 1; | |
3898 | goto no_support; | |
3899 | } | |
3900 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3901 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
3902 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3903 | break; |
3904 | ||
a38bba38 | 3905 | case 0x17: /* pop ss */ |
cf648174 HZ |
3906 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3907 | { | |
3908 | ir.addr -= 1; | |
3909 | goto no_support; | |
3910 | } | |
3911 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3912 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
3913 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3914 | break; |
3915 | ||
a38bba38 | 3916 | case 0x1f: /* pop ds */ |
cf648174 HZ |
3917 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3918 | { | |
3919 | ir.addr -= 1; | |
3920 | goto no_support; | |
3921 | } | |
3922 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3923 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
3924 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3925 | break; |
3926 | ||
a38bba38 | 3927 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
3928 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3929 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
3930 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3931 | break; |
3932 | ||
a38bba38 | 3933 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
3934 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3935 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
3936 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3937 | break; |
3938 | ||
a38bba38 | 3939 | case 0x88: /* mov */ |
7ad10968 HZ |
3940 | case 0x89: |
3941 | case 0xc6: | |
3942 | case 0xc7: | |
3943 | if ((opcode & 1) == 0) | |
3944 | ir.ot = OT_BYTE; | |
3945 | else | |
3946 | ir.ot = ir.dflag + OT_WORD; | |
3947 | ||
3948 | if (i386_record_modrm (&ir)) | |
3949 | return -1; | |
3950 | ||
3951 | if (ir.mod != 3) | |
3952 | { | |
cf648174 HZ |
3953 | if (opcode == 0xc6 || opcode == 0xc7) |
3954 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3955 | if (i386_record_lea_modrm (&ir)) |
3956 | return -1; | |
3957 | } | |
3958 | else | |
3959 | { | |
cf648174 HZ |
3960 | if (opcode == 0xc6 || opcode == 0xc7) |
3961 | ir.rm |= ir.rex_b; | |
3962 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3963 | ir.rm &= 0x3; |
cf648174 | 3964 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3965 | } |
7ad10968 | 3966 | break; |
cf648174 | 3967 | |
a38bba38 | 3968 | case 0x8a: /* mov */ |
7ad10968 HZ |
3969 | case 0x8b: |
3970 | if ((opcode & 1) == 0) | |
3971 | ir.ot = OT_BYTE; | |
3972 | else | |
3973 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3974 | if (i386_record_modrm (&ir)) |
3975 | return -1; | |
cf648174 HZ |
3976 | ir.reg |= rex_r; |
3977 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3978 | ir.reg &= 0x3; |
cf648174 HZ |
3979 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3980 | break; | |
7ad10968 | 3981 | |
a38bba38 | 3982 | case 0x8c: /* mov seg */ |
cf648174 | 3983 | if (i386_record_modrm (&ir)) |
7ad10968 | 3984 | return -1; |
cf648174 HZ |
3985 | if (ir.reg > 5) |
3986 | { | |
3987 | ir.addr -= 2; | |
3988 | opcode = opcode << 8 | ir.modrm; | |
3989 | goto no_support; | |
3990 | } | |
3991 | ||
3992 | if (ir.mod == 3) | |
3993 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
3994 | else | |
3995 | { | |
3996 | ir.ot = OT_WORD; | |
3997 | if (i386_record_lea_modrm (&ir)) | |
3998 | return -1; | |
3999 | } | |
7ad10968 HZ |
4000 | break; |
4001 | ||
a38bba38 | 4002 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4003 | if (i386_record_modrm (&ir)) |
4004 | return -1; | |
7ad10968 HZ |
4005 | switch (ir.reg) |
4006 | { | |
4007 | case 0: | |
cf648174 | 4008 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4009 | break; |
4010 | case 2: | |
cf648174 | 4011 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4012 | break; |
4013 | case 3: | |
cf648174 | 4014 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4015 | break; |
4016 | case 4: | |
cf648174 | 4017 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4018 | break; |
4019 | case 5: | |
cf648174 | 4020 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4021 | break; |
4022 | default: | |
4023 | ir.addr -= 2; | |
4024 | opcode = opcode << 8 | ir.modrm; | |
4025 | goto no_support; | |
4026 | break; | |
4027 | } | |
cf648174 HZ |
4028 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
4029 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4030 | break; |
4031 | ||
a38bba38 MS |
4032 | case 0x0fb6: /* movzbS */ |
4033 | case 0x0fb7: /* movzwS */ | |
4034 | case 0x0fbe: /* movsbS */ | |
4035 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4036 | if (i386_record_modrm (&ir)) |
4037 | return -1; | |
cf648174 | 4038 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4039 | break; |
4040 | ||
a38bba38 | 4041 | case 0x8d: /* lea */ |
7ad10968 HZ |
4042 | if (i386_record_modrm (&ir)) |
4043 | return -1; | |
4044 | if (ir.mod == 3) | |
4045 | { | |
4046 | ir.addr -= 2; | |
4047 | opcode = opcode << 8 | ir.modrm; | |
4048 | goto no_support; | |
4049 | } | |
7ad10968 | 4050 | ir.ot = ir.dflag; |
cf648174 HZ |
4051 | ir.reg |= rex_r; |
4052 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4053 | ir.reg &= 0x3; |
cf648174 | 4054 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4055 | break; |
4056 | ||
a38bba38 | 4057 | case 0xa0: /* mov EAX */ |
7ad10968 | 4058 | case 0xa1: |
a38bba38 MS |
4059 | |
4060 | case 0xd7: /* xlat */ | |
cf648174 | 4061 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4062 | break; |
4063 | ||
a38bba38 | 4064 | case 0xa2: /* mov EAX */ |
7ad10968 | 4065 | case 0xa3: |
d7877f7e | 4066 | if (ir.override >= 0) |
cf648174 | 4067 | { |
df61f520 | 4068 | warning (_("Process record ignores the memory change " |
926569ae | 4069 | "of instruction at address %s because " |
df61f520 HZ |
4070 | "it can't get the value of the segment " |
4071 | "register."), | |
4072 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
4073 | } |
4074 | else | |
4075 | { | |
4076 | if ((opcode & 1) == 0) | |
4077 | ir.ot = OT_BYTE; | |
4078 | else | |
4079 | ir.ot = ir.dflag + OT_WORD; | |
4080 | if (ir.aflag == 2) | |
4081 | { | |
4082 | if (target_read_memory (ir.addr, (gdb_byte *) &addr, 8)) | |
4083 | { | |
4084 | if (record_debug) | |
4085 | printf_unfiltered (_("Process record: error reading " | |
4086 | "memory at addr 0x%s len = 8.\n"), | |
4087 | paddress (gdbarch, ir.addr)); | |
4088 | return -1; | |
4089 | } | |
4090 | ir.addr += 8; | |
4091 | } | |
4092 | else if (ir.aflag) | |
4093 | { | |
4094 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu32, 4)) | |
4095 | { | |
4096 | if (record_debug) | |
4097 | printf_unfiltered (_("Process record: error reading " | |
4098 | "memory at addr 0x%s len = 4.\n"), | |
4099 | paddress (gdbarch, ir.addr)); | |
4100 | return -1; | |
4101 | } | |
4102 | ir.addr += 4; | |
4103 | addr = tmpu32; | |
4104 | } | |
4105 | else | |
4106 | { | |
4107 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu16, 2)) | |
4108 | { | |
4109 | if (record_debug) | |
4110 | printf_unfiltered (_("Process record: error reading " | |
4111 | "memory at addr 0x%s len = 2.\n"), | |
4112 | paddress (gdbarch, ir.addr)); | |
4113 | return -1; | |
4114 | } | |
4115 | ir.addr += 2; | |
4116 | addr = tmpu16; | |
4117 | } | |
4118 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) | |
4119 | return -1; | |
4120 | } | |
7ad10968 HZ |
4121 | break; |
4122 | ||
a38bba38 | 4123 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4124 | case 0xb1: |
4125 | case 0xb2: | |
4126 | case 0xb3: | |
4127 | case 0xb4: | |
4128 | case 0xb5: | |
4129 | case 0xb6: | |
4130 | case 0xb7: | |
cf648174 HZ |
4131 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4132 | ? ((opcode & 0x7) | ir.rex_b) | |
4133 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4134 | break; |
4135 | ||
a38bba38 | 4136 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4137 | case 0xb9: |
4138 | case 0xba: | |
4139 | case 0xbb: | |
4140 | case 0xbc: | |
4141 | case 0xbd: | |
4142 | case 0xbe: | |
4143 | case 0xbf: | |
cf648174 | 4144 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4145 | break; |
4146 | ||
a38bba38 | 4147 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4148 | case 0x92: |
4149 | case 0x93: | |
4150 | case 0x94: | |
4151 | case 0x95: | |
4152 | case 0x96: | |
4153 | case 0x97: | |
cf648174 HZ |
4154 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4155 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4156 | break; |
4157 | ||
a38bba38 | 4158 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4159 | case 0x87: |
4160 | if ((opcode & 1) == 0) | |
4161 | ir.ot = OT_BYTE; | |
4162 | else | |
4163 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4164 | if (i386_record_modrm (&ir)) |
4165 | return -1; | |
7ad10968 HZ |
4166 | if (ir.mod == 3) |
4167 | { | |
86839d38 | 4168 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4169 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4170 | ir.rm &= 0x3; | |
4171 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4172 | } |
4173 | else | |
4174 | { | |
4175 | if (i386_record_lea_modrm (&ir)) | |
4176 | return -1; | |
4177 | } | |
cf648174 HZ |
4178 | ir.reg |= rex_r; |
4179 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4180 | ir.reg &= 0x3; |
cf648174 | 4181 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4182 | break; |
4183 | ||
a38bba38 MS |
4184 | case 0xc4: /* les Gv */ |
4185 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4186 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4187 | { | |
4188 | ir.addr -= 1; | |
4189 | goto no_support; | |
4190 | } | |
a38bba38 MS |
4191 | case 0x0fb2: /* lss Gv */ |
4192 | case 0x0fb4: /* lfs Gv */ | |
4193 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4194 | if (i386_record_modrm (&ir)) |
4195 | return -1; | |
4196 | if (ir.mod == 3) | |
4197 | { | |
4198 | if (opcode > 0xff) | |
4199 | ir.addr -= 3; | |
4200 | else | |
4201 | ir.addr -= 2; | |
4202 | opcode = opcode << 8 | ir.modrm; | |
4203 | goto no_support; | |
4204 | } | |
7ad10968 HZ |
4205 | switch (opcode) |
4206 | { | |
a38bba38 | 4207 | case 0xc4: /* les Gv */ |
cf648174 | 4208 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 | 4209 | break; |
a38bba38 | 4210 | case 0xc5: /* lds Gv */ |
cf648174 | 4211 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 | 4212 | break; |
a38bba38 | 4213 | case 0x0fb2: /* lss Gv */ |
cf648174 | 4214 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 | 4215 | break; |
a38bba38 | 4216 | case 0x0fb4: /* lfs Gv */ |
cf648174 | 4217 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 | 4218 | break; |
a38bba38 | 4219 | case 0x0fb5: /* lgs Gv */ |
cf648174 | 4220 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4221 | break; |
4222 | } | |
cf648174 HZ |
4223 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
4224 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
4225 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4226 | break; |
4227 | ||
a38bba38 | 4228 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4229 | case 0xc1: |
4230 | case 0xd0: | |
4231 | case 0xd1: | |
4232 | case 0xd2: | |
4233 | case 0xd3: | |
4234 | if ((opcode & 1) == 0) | |
4235 | ir.ot = OT_BYTE; | |
4236 | else | |
4237 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4238 | if (i386_record_modrm (&ir)) |
4239 | return -1; | |
7ad10968 HZ |
4240 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4241 | { | |
4242 | if (i386_record_lea_modrm (&ir)) | |
4243 | return -1; | |
4244 | } | |
4245 | else | |
4246 | { | |
cf648174 HZ |
4247 | ir.rm |= ir.rex_b; |
4248 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4249 | ir.rm &= 0x3; |
cf648174 | 4250 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4251 | } |
cf648174 | 4252 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4253 | break; |
4254 | ||
4255 | case 0x0fa4: | |
4256 | case 0x0fa5: | |
4257 | case 0x0fac: | |
4258 | case 0x0fad: | |
4259 | if (i386_record_modrm (&ir)) | |
4260 | return -1; | |
4261 | if (ir.mod == 3) | |
4262 | { | |
4263 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4264 | return -1; | |
4265 | } | |
4266 | else | |
4267 | { | |
4268 | if (i386_record_lea_modrm (&ir)) | |
4269 | return -1; | |
4270 | } | |
4271 | break; | |
4272 | ||
a38bba38 | 4273 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4274 | case 0xd9: |
4275 | case 0xda: | |
4276 | case 0xdb: | |
4277 | case 0xdc: | |
4278 | case 0xdd: | |
4279 | case 0xde: | |
4280 | case 0xdf: | |
4281 | if (i386_record_modrm (&ir)) | |
4282 | return -1; | |
4283 | ir.reg |= ((opcode & 7) << 3); | |
4284 | if (ir.mod != 3) | |
4285 | { | |
0289bdd7 | 4286 | /* Memory. */ |
cf648174 | 4287 | uint64_t tmpu64; |
7ad10968 | 4288 | |
cf648174 | 4289 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 HZ |
4290 | return -1; |
4291 | switch (ir.reg) | |
4292 | { | |
7ad10968 | 4293 | case 0x02: |
0289bdd7 MS |
4294 | case 0x12: |
4295 | case 0x22: | |
4296 | case 0x32: | |
4297 | /* For fcom, ficom nothing to do. */ | |
4298 | break; | |
7ad10968 | 4299 | case 0x03: |
0289bdd7 MS |
4300 | case 0x13: |
4301 | case 0x23: | |
4302 | case 0x33: | |
4303 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
4304 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4305 | return -1; | |
4306 | break; | |
4307 | case 0x00: | |
4308 | case 0x01: | |
7ad10968 HZ |
4309 | case 0x04: |
4310 | case 0x05: | |
4311 | case 0x06: | |
4312 | case 0x07: | |
4313 | case 0x10: | |
4314 | case 0x11: | |
7ad10968 HZ |
4315 | case 0x14: |
4316 | case 0x15: | |
4317 | case 0x16: | |
4318 | case 0x17: | |
4319 | case 0x20: | |
4320 | case 0x21: | |
7ad10968 HZ |
4321 | case 0x24: |
4322 | case 0x25: | |
4323 | case 0x26: | |
4324 | case 0x27: | |
4325 | case 0x30: | |
4326 | case 0x31: | |
7ad10968 HZ |
4327 | case 0x34: |
4328 | case 0x35: | |
4329 | case 0x36: | |
4330 | case 0x37: | |
0289bdd7 MS |
4331 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
4332 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
4333 | of code, always affects st(0) register. */ | |
4334 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4335 | return -1; | |
7ad10968 HZ |
4336 | break; |
4337 | case 0x08: | |
4338 | case 0x0a: | |
4339 | case 0x0b: | |
4340 | case 0x18: | |
4341 | case 0x19: | |
4342 | case 0x1a: | |
4343 | case 0x1b: | |
0289bdd7 | 4344 | case 0x1d: |
7ad10968 HZ |
4345 | case 0x28: |
4346 | case 0x29: | |
4347 | case 0x2a: | |
4348 | case 0x2b: | |
4349 | case 0x38: | |
4350 | case 0x39: | |
4351 | case 0x3a: | |
4352 | case 0x3b: | |
0289bdd7 MS |
4353 | case 0x3c: |
4354 | case 0x3d: | |
7ad10968 HZ |
4355 | switch (ir.reg & 7) |
4356 | { | |
4357 | case 0: | |
0289bdd7 MS |
4358 | /* Handling fld, fild. */ |
4359 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4360 | return -1; | |
7ad10968 HZ |
4361 | break; |
4362 | case 1: | |
4363 | switch (ir.reg >> 4) | |
4364 | { | |
4365 | case 0: | |
cf648174 | 4366 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 HZ |
4367 | return -1; |
4368 | break; | |
4369 | case 2: | |
cf648174 | 4370 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 HZ |
4371 | return -1; |
4372 | break; | |
4373 | case 3: | |
0289bdd7 | 4374 | break; |
7ad10968 | 4375 | default: |
cf648174 | 4376 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4377 | return -1; |
4378 | break; | |
4379 | } | |
4380 | break; | |
4381 | default: | |
4382 | switch (ir.reg >> 4) | |
4383 | { | |
4384 | case 0: | |
0289bdd7 MS |
4385 | if (record_arch_list_add_mem (tmpu64, 4)) |
4386 | return -1; | |
4387 | if (3 == (ir.reg & 7)) | |
4388 | { | |
4389 | /* For fstp m32fp. */ | |
4390 | if (i386_record_floats (gdbarch, &ir, | |
4391 | I386_SAVE_FPU_REGS)) | |
4392 | return -1; | |
4393 | } | |
4394 | break; | |
7ad10968 | 4395 | case 1: |
cf648174 | 4396 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 | 4397 | return -1; |
0289bdd7 MS |
4398 | if ((3 == (ir.reg & 7)) |
4399 | || (5 == (ir.reg & 7)) | |
4400 | || (7 == (ir.reg & 7))) | |
4401 | { | |
4402 | /* For fstp insn. */ | |
4403 | if (i386_record_floats (gdbarch, &ir, | |
4404 | I386_SAVE_FPU_REGS)) | |
4405 | return -1; | |
4406 | } | |
7ad10968 HZ |
4407 | break; |
4408 | case 2: | |
cf648174 | 4409 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 | 4410 | return -1; |
0289bdd7 MS |
4411 | if (3 == (ir.reg & 7)) |
4412 | { | |
4413 | /* For fstp m64fp. */ | |
4414 | if (i386_record_floats (gdbarch, &ir, | |
4415 | I386_SAVE_FPU_REGS)) | |
4416 | return -1; | |
4417 | } | |
7ad10968 HZ |
4418 | break; |
4419 | case 3: | |
0289bdd7 MS |
4420 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
4421 | { | |
4422 | /* For fistp, fbld, fild, fbstp. */ | |
4423 | if (i386_record_floats (gdbarch, &ir, | |
4424 | I386_SAVE_FPU_REGS)) | |
4425 | return -1; | |
4426 | } | |
4427 | /* Fall through */ | |
7ad10968 | 4428 | default: |
cf648174 | 4429 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4430 | return -1; |
4431 | break; | |
4432 | } | |
4433 | break; | |
4434 | } | |
4435 | break; | |
4436 | case 0x0c: | |
0289bdd7 MS |
4437 | /* Insn fldenv. */ |
4438 | if (i386_record_floats (gdbarch, &ir, | |
4439 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4440 | return -1; | |
4441 | break; | |
7ad10968 | 4442 | case 0x0d: |
0289bdd7 MS |
4443 | /* Insn fldcw. */ |
4444 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
4445 | return -1; | |
4446 | break; | |
7ad10968 | 4447 | case 0x2c: |
0289bdd7 MS |
4448 | /* Insn frstor. */ |
4449 | if (i386_record_floats (gdbarch, &ir, | |
4450 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4451 | return -1; | |
7ad10968 HZ |
4452 | break; |
4453 | case 0x0e: | |
4454 | if (ir.dflag) | |
4455 | { | |
cf648174 | 4456 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 HZ |
4457 | return -1; |
4458 | } | |
4459 | else | |
4460 | { | |
cf648174 | 4461 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 HZ |
4462 | return -1; |
4463 | } | |
4464 | break; | |
4465 | case 0x0f: | |
4466 | case 0x2f: | |
cf648174 | 4467 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 | 4468 | return -1; |
0289bdd7 MS |
4469 | /* Insn fstp, fbstp. */ |
4470 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4471 | return -1; | |
7ad10968 HZ |
4472 | break; |
4473 | case 0x1f: | |
4474 | case 0x3e: | |
cf648174 | 4475 | if (record_arch_list_add_mem (tmpu64, 10)) |
7ad10968 HZ |
4476 | return -1; |
4477 | break; | |
4478 | case 0x2e: | |
4479 | if (ir.dflag) | |
4480 | { | |
cf648174 | 4481 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 | 4482 | return -1; |
cf648174 | 4483 | tmpu64 += 28; |
7ad10968 HZ |
4484 | } |
4485 | else | |
4486 | { | |
cf648174 | 4487 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 | 4488 | return -1; |
cf648174 | 4489 | tmpu64 += 14; |
7ad10968 | 4490 | } |
cf648174 | 4491 | if (record_arch_list_add_mem (tmpu64, 80)) |
7ad10968 | 4492 | return -1; |
0289bdd7 MS |
4493 | /* Insn fsave. */ |
4494 | if (i386_record_floats (gdbarch, &ir, | |
4495 | I386_SAVE_FPU_ENV_REG_STACK)) | |
4496 | return -1; | |
7ad10968 HZ |
4497 | break; |
4498 | case 0x3f: | |
cf648174 | 4499 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 | 4500 | return -1; |
0289bdd7 MS |
4501 | /* Insn fistp. */ |
4502 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4503 | return -1; | |
7ad10968 HZ |
4504 | break; |
4505 | default: | |
4506 | ir.addr -= 2; | |
4507 | opcode = opcode << 8 | ir.modrm; | |
4508 | goto no_support; | |
4509 | break; | |
4510 | } | |
4511 | } | |
0289bdd7 MS |
4512 | /* Opcode is an extension of modR/M byte. */ |
4513 | else | |
4514 | { | |
4515 | switch (opcode) | |
4516 | { | |
4517 | case 0xd8: | |
4518 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
4519 | return -1; | |
4520 | break; | |
4521 | case 0xd9: | |
4522 | if (0x0c == (ir.modrm >> 4)) | |
4523 | { | |
4524 | if ((ir.modrm & 0x0f) <= 7) | |
4525 | { | |
4526 | if (i386_record_floats (gdbarch, &ir, | |
4527 | I386_SAVE_FPU_REGS)) | |
4528 | return -1; | |
4529 | } | |
4530 | else | |
4531 | { | |
4532 | if (i386_record_floats (gdbarch, &ir, | |
4533 | I387_ST0_REGNUM (tdep))) | |
4534 | return -1; | |
4535 | /* If only st(0) is changing, then we have already | |
4536 | recorded. */ | |
4537 | if ((ir.modrm & 0x0f) - 0x08) | |
4538 | { | |
4539 | if (i386_record_floats (gdbarch, &ir, | |
4540 | I387_ST0_REGNUM (tdep) + | |
4541 | ((ir.modrm & 0x0f) - 0x08))) | |
4542 | return -1; | |
4543 | } | |
4544 | } | |
4545 | } | |
4546 | else | |
4547 | { | |
4548 | switch (ir.modrm) | |
4549 | { | |
4550 | case 0xe0: | |
4551 | case 0xe1: | |
4552 | case 0xf0: | |
4553 | case 0xf5: | |
4554 | case 0xf8: | |
4555 | case 0xfa: | |
4556 | case 0xfc: | |
4557 | case 0xfe: | |
4558 | case 0xff: | |
4559 | if (i386_record_floats (gdbarch, &ir, | |
4560 | I387_ST0_REGNUM (tdep))) | |
4561 | return -1; | |
4562 | break; | |
4563 | case 0xf1: | |
4564 | case 0xf2: | |
4565 | case 0xf3: | |
4566 | case 0xf4: | |
4567 | case 0xf6: | |
4568 | case 0xf7: | |
4569 | case 0xe8: | |
4570 | case 0xe9: | |
4571 | case 0xea: | |
4572 | case 0xeb: | |
4573 | case 0xec: | |
4574 | case 0xed: | |
4575 | case 0xee: | |
4576 | case 0xf9: | |
4577 | case 0xfb: | |
4578 | if (i386_record_floats (gdbarch, &ir, | |
4579 | I386_SAVE_FPU_REGS)) | |
4580 | return -1; | |
4581 | break; | |
4582 | case 0xfd: | |
4583 | if (i386_record_floats (gdbarch, &ir, | |
4584 | I387_ST0_REGNUM (tdep))) | |
4585 | return -1; | |
4586 | if (i386_record_floats (gdbarch, &ir, | |
4587 | I387_ST0_REGNUM (tdep) + 1)) | |
4588 | return -1; | |
4589 | break; | |
4590 | } | |
4591 | } | |
4592 | break; | |
4593 | case 0xda: | |
4594 | if (0xe9 == ir.modrm) | |
4595 | { | |
4596 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4597 | return -1; | |
4598 | } | |
4599 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4600 | { | |
4601 | if (i386_record_floats (gdbarch, &ir, | |
4602 | I387_ST0_REGNUM (tdep))) | |
4603 | return -1; | |
4604 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4605 | { | |
4606 | if (i386_record_floats (gdbarch, &ir, | |
4607 | I387_ST0_REGNUM (tdep) + | |
4608 | (ir.modrm & 0x0f))) | |
4609 | return -1; | |
4610 | } | |
4611 | else if ((ir.modrm & 0x0f) - 0x08) | |
4612 | { | |
4613 | if (i386_record_floats (gdbarch, &ir, | |
4614 | I387_ST0_REGNUM (tdep) + | |
4615 | ((ir.modrm & 0x0f) - 0x08))) | |
4616 | return -1; | |
4617 | } | |
4618 | } | |
4619 | break; | |
4620 | case 0xdb: | |
4621 | if (0xe3 == ir.modrm) | |
4622 | { | |
4623 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
4624 | return -1; | |
4625 | } | |
4626 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
4627 | { | |
4628 | if (i386_record_floats (gdbarch, &ir, | |
4629 | I387_ST0_REGNUM (tdep))) | |
4630 | return -1; | |
4631 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
4632 | { | |
4633 | if (i386_record_floats (gdbarch, &ir, | |
4634 | I387_ST0_REGNUM (tdep) + | |
4635 | (ir.modrm & 0x0f))) | |
4636 | return -1; | |
4637 | } | |
4638 | else if ((ir.modrm & 0x0f) - 0x08) | |
4639 | { | |
4640 | if (i386_record_floats (gdbarch, &ir, | |
4641 | I387_ST0_REGNUM (tdep) + | |
4642 | ((ir.modrm & 0x0f) - 0x08))) | |
4643 | return -1; | |
4644 | } | |
4645 | } | |
4646 | break; | |
4647 | case 0xdc: | |
4648 | if ((0x0c == ir.modrm >> 4) | |
4649 | || (0x0d == ir.modrm >> 4) | |
4650 | || (0x0f == ir.modrm >> 4)) | |
4651 | { | |
4652 | if ((ir.modrm & 0x0f) <= 7) | |
4653 | { | |
4654 | if (i386_record_floats (gdbarch, &ir, | |
4655 | I387_ST0_REGNUM (tdep) + | |
4656 | (ir.modrm & 0x0f))) | |
4657 | return -1; | |
4658 | } | |
4659 | else | |
4660 | { | |
4661 | if (i386_record_floats (gdbarch, &ir, | |
4662 | I387_ST0_REGNUM (tdep) + | |
4663 | ((ir.modrm & 0x0f) - 0x08))) | |
4664 | return -1; | |
4665 | } | |
4666 | } | |
4667 | break; | |
4668 | case 0xdd: | |
4669 | if (0x0c == ir.modrm >> 4) | |
4670 | { | |
4671 | if (i386_record_floats (gdbarch, &ir, | |
4672 | I387_FTAG_REGNUM (tdep))) | |
4673 | return -1; | |
4674 | } | |
4675 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4676 | { | |
4677 | if ((ir.modrm & 0x0f) <= 7) | |
4678 | { | |
4679 | if (i386_record_floats (gdbarch, &ir, | |
4680 | I387_ST0_REGNUM (tdep) + | |
4681 | (ir.modrm & 0x0f))) | |
4682 | return -1; | |
4683 | } | |
4684 | else | |
4685 | { | |
4686 | if (i386_record_floats (gdbarch, &ir, | |
4687 | I386_SAVE_FPU_REGS)) | |
4688 | return -1; | |
4689 | } | |
4690 | } | |
4691 | break; | |
4692 | case 0xde: | |
4693 | if ((0x0c == ir.modrm >> 4) | |
4694 | || (0x0e == ir.modrm >> 4) | |
4695 | || (0x0f == ir.modrm >> 4) | |
4696 | || (0xd9 == ir.modrm)) | |
4697 | { | |
4698 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4699 | return -1; | |
4700 | } | |
4701 | break; | |
4702 | case 0xdf: | |
4703 | if (0xe0 == ir.modrm) | |
4704 | { | |
4705 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
4706 | return -1; | |
4707 | } | |
4708 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
4709 | { | |
4710 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
4711 | return -1; | |
4712 | } | |
4713 | break; | |
4714 | } | |
4715 | } | |
7ad10968 | 4716 | break; |
7ad10968 | 4717 | /* string ops */ |
a38bba38 | 4718 | case 0xa4: /* movsS */ |
7ad10968 | 4719 | case 0xa5: |
a38bba38 | 4720 | case 0xaa: /* stosS */ |
7ad10968 | 4721 | case 0xab: |
a38bba38 | 4722 | case 0x6c: /* insS */ |
7ad10968 | 4723 | case 0x6d: |
cf648174 | 4724 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 4725 | ir.regmap[X86_RECORD_RECX_REGNUM], |
cf648174 | 4726 | &tmpulongest); |
77d7dc92 | 4727 | if (tmpulongest) |
cf648174 | 4728 | { |
77d7dc92 HZ |
4729 | ULONGEST es, ds; |
4730 | ||
4731 | if ((opcode & 1) == 0) | |
4732 | ir.ot = OT_BYTE; | |
4733 | else | |
4734 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
4735 | regcache_raw_read_unsigned (ir.regcache, |
4736 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
77d7dc92 HZ |
4737 | &tmpulongest); |
4738 | ||
d7877f7e HZ |
4739 | regcache_raw_read_unsigned (ir.regcache, |
4740 | ir.regmap[X86_RECORD_ES_REGNUM], | |
4741 | &es); | |
4742 | regcache_raw_read_unsigned (ir.regcache, | |
4743 | ir.regmap[X86_RECORD_DS_REGNUM], | |
4744 | &ds); | |
4745 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
4746 | { |
4747 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 4748 | warning (_("Process record ignores the memory " |
926569ae | 4749 | "change of instruction at address %s " |
df61f520 HZ |
4750 | "because it can't get the value of the " |
4751 | "ES segment register."), | |
4752 | paddress (gdbarch, ir.orig_addr)); | |
4753 | } | |
4754 | else | |
4755 | { | |
4756 | if (record_arch_list_add_mem (tmpulongest, 1 << ir.ot)) | |
4757 | return -1; | |
77d7dc92 HZ |
4758 | } |
4759 | ||
4760 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4761 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
4762 | if (opcode == 0xa4 || opcode == 0xa5) |
4763 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4764 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4765 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4766 | } | |
cf648174 | 4767 | break; |
7ad10968 | 4768 | |
a38bba38 | 4769 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
4770 | case 0xa7: |
4771 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4772 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4773 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4774 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
4775 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4776 | break; |
4777 | ||
a38bba38 | 4778 | case 0xac: /* lodsS */ |
7ad10968 | 4779 | case 0xad: |
cf648174 HZ |
4780 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4781 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4782 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4783 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4784 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4785 | break; |
4786 | ||
a38bba38 | 4787 | case 0xae: /* scasS */ |
7ad10968 | 4788 | case 0xaf: |
cf648174 | 4789 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 4790 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4791 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4792 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4793 | break; |
4794 | ||
a38bba38 | 4795 | case 0x6e: /* outsS */ |
cf648174 HZ |
4796 | case 0x6f: |
4797 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4798 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4799 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4800 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4801 | break; |
4802 | ||
a38bba38 | 4803 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
4804 | case 0xe5: |
4805 | case 0xec: | |
4806 | case 0xed: | |
cf648174 HZ |
4807 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4808 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4809 | break; |
4810 | ||
4811 | case 0xe6: | |
4812 | case 0xe7: | |
4813 | case 0xee: | |
4814 | case 0xef: | |
4815 | break; | |
4816 | ||
4817 | /* control */ | |
a38bba38 MS |
4818 | case 0xc2: /* ret im */ |
4819 | case 0xc3: /* ret */ | |
cf648174 HZ |
4820 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4821 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4822 | break; | |
4823 | ||
a38bba38 MS |
4824 | case 0xca: /* lret im */ |
4825 | case 0xcb: /* lret */ | |
4826 | case 0xcf: /* iret */ | |
cf648174 HZ |
4827 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4828 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4829 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4830 | break; |
4831 | ||
a38bba38 | 4832 | case 0xe8: /* call im */ |
cf648174 HZ |
4833 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4834 | ir.dflag = 2; | |
4835 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4836 | return -1; | |
7ad10968 HZ |
4837 | break; |
4838 | ||
a38bba38 | 4839 | case 0x9a: /* lcall im */ |
cf648174 HZ |
4840 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4841 | { | |
4842 | ir.addr -= 1; | |
4843 | goto no_support; | |
4844 | } | |
4845 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
4846 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4847 | return -1; | |
7ad10968 HZ |
4848 | break; |
4849 | ||
a38bba38 MS |
4850 | case 0xe9: /* jmp im */ |
4851 | case 0xea: /* ljmp im */ | |
4852 | case 0xeb: /* jmp Jb */ | |
4853 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
4854 | case 0x71: |
4855 | case 0x72: | |
4856 | case 0x73: | |
4857 | case 0x74: | |
4858 | case 0x75: | |
4859 | case 0x76: | |
4860 | case 0x77: | |
4861 | case 0x78: | |
4862 | case 0x79: | |
4863 | case 0x7a: | |
4864 | case 0x7b: | |
4865 | case 0x7c: | |
4866 | case 0x7d: | |
4867 | case 0x7e: | |
4868 | case 0x7f: | |
a38bba38 | 4869 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
4870 | case 0x0f81: |
4871 | case 0x0f82: | |
4872 | case 0x0f83: | |
4873 | case 0x0f84: | |
4874 | case 0x0f85: | |
4875 | case 0x0f86: | |
4876 | case 0x0f87: | |
4877 | case 0x0f88: | |
4878 | case 0x0f89: | |
4879 | case 0x0f8a: | |
4880 | case 0x0f8b: | |
4881 | case 0x0f8c: | |
4882 | case 0x0f8d: | |
4883 | case 0x0f8e: | |
4884 | case 0x0f8f: | |
4885 | break; | |
4886 | ||
a38bba38 | 4887 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
4888 | case 0x0f91: |
4889 | case 0x0f92: | |
4890 | case 0x0f93: | |
4891 | case 0x0f94: | |
4892 | case 0x0f95: | |
4893 | case 0x0f96: | |
4894 | case 0x0f97: | |
4895 | case 0x0f98: | |
4896 | case 0x0f99: | |
4897 | case 0x0f9a: | |
4898 | case 0x0f9b: | |
4899 | case 0x0f9c: | |
4900 | case 0x0f9d: | |
4901 | case 0x0f9e: | |
4902 | case 0x0f9f: | |
cf648174 | 4903 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4904 | ir.ot = OT_BYTE; |
4905 | if (i386_record_modrm (&ir)) | |
4906 | return -1; | |
4907 | if (ir.mod == 3) | |
cf648174 HZ |
4908 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
4909 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
4910 | else |
4911 | { | |
4912 | if (i386_record_lea_modrm (&ir)) | |
4913 | return -1; | |
4914 | } | |
4915 | break; | |
4916 | ||
a38bba38 | 4917 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
4918 | case 0x0f41: |
4919 | case 0x0f42: | |
4920 | case 0x0f43: | |
4921 | case 0x0f44: | |
4922 | case 0x0f45: | |
4923 | case 0x0f46: | |
4924 | case 0x0f47: | |
4925 | case 0x0f48: | |
4926 | case 0x0f49: | |
4927 | case 0x0f4a: | |
4928 | case 0x0f4b: | |
4929 | case 0x0f4c: | |
4930 | case 0x0f4d: | |
4931 | case 0x0f4e: | |
4932 | case 0x0f4f: | |
4933 | if (i386_record_modrm (&ir)) | |
4934 | return -1; | |
cf648174 | 4935 | ir.reg |= rex_r; |
7ad10968 HZ |
4936 | if (ir.dflag == OT_BYTE) |
4937 | ir.reg &= 0x3; | |
cf648174 | 4938 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4939 | break; |
4940 | ||
4941 | /* flags */ | |
a38bba38 | 4942 | case 0x9c: /* pushf */ |
cf648174 HZ |
4943 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4944 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4945 | ir.dflag = 2; | |
4946 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4947 | return -1; | |
7ad10968 HZ |
4948 | break; |
4949 | ||
a38bba38 | 4950 | case 0x9d: /* popf */ |
cf648174 HZ |
4951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4952 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4953 | break; |
4954 | ||
a38bba38 | 4955 | case 0x9e: /* sahf */ |
cf648174 HZ |
4956 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4957 | { | |
4958 | ir.addr -= 1; | |
4959 | goto no_support; | |
4960 | } | |
a38bba38 MS |
4961 | case 0xf5: /* cmc */ |
4962 | case 0xf8: /* clc */ | |
4963 | case 0xf9: /* stc */ | |
4964 | case 0xfc: /* cld */ | |
4965 | case 0xfd: /* std */ | |
cf648174 | 4966 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4967 | break; |
4968 | ||
a38bba38 | 4969 | case 0x9f: /* lahf */ |
cf648174 HZ |
4970 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4971 | { | |
4972 | ir.addr -= 1; | |
4973 | goto no_support; | |
4974 | } | |
4975 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4976 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4977 | break; |
4978 | ||
4979 | /* bit operations */ | |
a38bba38 | 4980 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
4981 | ir.ot = ir.dflag + OT_WORD; |
4982 | if (i386_record_modrm (&ir)) | |
4983 | return -1; | |
4984 | if (ir.reg < 4) | |
4985 | { | |
cf648174 | 4986 | ir.addr -= 2; |
7ad10968 HZ |
4987 | opcode = opcode << 8 | ir.modrm; |
4988 | goto no_support; | |
4989 | } | |
cf648174 | 4990 | if (ir.reg != 4) |
7ad10968 | 4991 | { |
cf648174 HZ |
4992 | if (ir.mod == 3) |
4993 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
4994 | else |
4995 | { | |
cf648174 | 4996 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
4997 | return -1; |
4998 | } | |
4999 | } | |
cf648174 | 5000 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5001 | break; |
5002 | ||
a38bba38 | 5003 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5004 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5005 | break; | |
5006 | ||
a38bba38 MS |
5007 | case 0x0fab: /* bts */ |
5008 | case 0x0fb3: /* btr */ | |
5009 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5010 | ir.ot = ir.dflag + OT_WORD; |
5011 | if (i386_record_modrm (&ir)) | |
5012 | return -1; | |
5013 | if (ir.mod == 3) | |
5014 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5015 | else | |
5016 | { | |
5017 | uint64_t tmpu64; | |
5018 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
5019 | return -1; | |
5020 | regcache_raw_read_unsigned (ir.regcache, | |
5021 | ir.regmap[ir.reg | rex_r], | |
5022 | &tmpulongest); | |
5023 | switch (ir.dflag) | |
5024 | { | |
5025 | case 0: | |
5026 | tmpu64 += ((int16_t) tmpulongest >> 4) << 4; | |
5027 | break; | |
5028 | case 1: | |
5029 | tmpu64 += ((int32_t) tmpulongest >> 5) << 5; | |
5030 | break; | |
5031 | case 2: | |
5032 | tmpu64 += ((int64_t) tmpulongest >> 6) << 6; | |
5033 | break; | |
5034 | } | |
5035 | if (record_arch_list_add_mem (tmpu64, 1 << ir.ot)) | |
5036 | return -1; | |
5037 | if (i386_record_lea_modrm (&ir)) | |
5038 | return -1; | |
5039 | } | |
5040 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5041 | break; |
5042 | ||
a38bba38 MS |
5043 | case 0x0fbc: /* bsf */ |
5044 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5045 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5046 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5047 | break; |
5048 | ||
5049 | /* bcd */ | |
a38bba38 MS |
5050 | case 0x27: /* daa */ |
5051 | case 0x2f: /* das */ | |
5052 | case 0x37: /* aaa */ | |
5053 | case 0x3f: /* aas */ | |
5054 | case 0xd4: /* aam */ | |
5055 | case 0xd5: /* aad */ | |
cf648174 HZ |
5056 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5057 | { | |
5058 | ir.addr -= 1; | |
5059 | goto no_support; | |
5060 | } | |
5061 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5062 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5063 | break; |
5064 | ||
5065 | /* misc */ | |
a38bba38 | 5066 | case 0x90: /* nop */ |
7ad10968 HZ |
5067 | if (prefixes & PREFIX_LOCK) |
5068 | { | |
5069 | ir.addr -= 1; | |
5070 | goto no_support; | |
5071 | } | |
5072 | break; | |
5073 | ||
a38bba38 | 5074 | case 0x9b: /* fwait */ |
0289bdd7 MS |
5075 | if (target_read_memory (ir.addr, &tmpu8, 1)) |
5076 | { | |
5077 | if (record_debug) | |
5078 | printf_unfiltered (_("Process record: error reading memory at " | |
5079 | "addr 0x%s len = 1.\n"), | |
5080 | paddress (gdbarch, ir.addr)); | |
5081 | return -1; | |
5082 | } | |
5083 | opcode = (uint32_t) tmpu8; | |
5084 | ir.addr++; | |
5085 | goto reswitch; | |
7ad10968 HZ |
5086 | break; |
5087 | ||
7ad10968 | 5088 | /* XXX */ |
a38bba38 | 5089 | case 0xcc: /* int3 */ |
7ad10968 HZ |
5090 | printf_unfiltered (_("Process record doesn't support instruction " |
5091 | "int3.\n")); | |
5092 | ir.addr -= 1; | |
5093 | goto no_support; | |
5094 | break; | |
5095 | ||
7ad10968 | 5096 | /* XXX */ |
a38bba38 | 5097 | case 0xcd: /* int */ |
7ad10968 HZ |
5098 | { |
5099 | int ret; | |
5100 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
5101 | { | |
5102 | if (record_debug) | |
5103 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5104 | "at addr %s len = 1.\n"), |
5105 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5106 | return -1; |
5107 | } | |
5108 | ir.addr++; | |
5109 | if (tmpu8 != 0x80 | |
5110 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) | |
5111 | { | |
5112 | printf_unfiltered (_("Process record doesn't support " | |
5113 | "instruction int 0x%02x.\n"), | |
5114 | tmpu8); | |
5115 | ir.addr -= 2; | |
5116 | goto no_support; | |
5117 | } | |
5118 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
5119 | if (ret) | |
5120 | return ret; | |
5121 | } | |
5122 | break; | |
5123 | ||
7ad10968 | 5124 | /* XXX */ |
a38bba38 | 5125 | case 0xce: /* into */ |
7ad10968 HZ |
5126 | printf_unfiltered (_("Process record doesn't support " |
5127 | "instruction into.\n")); | |
5128 | ir.addr -= 1; | |
5129 | goto no_support; | |
5130 | break; | |
5131 | ||
a38bba38 MS |
5132 | case 0xfa: /* cli */ |
5133 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5134 | break; |
5135 | ||
a38bba38 | 5136 | case 0x62: /* bound */ |
7ad10968 HZ |
5137 | printf_unfiltered (_("Process record doesn't support " |
5138 | "instruction bound.\n")); | |
5139 | ir.addr -= 1; | |
5140 | goto no_support; | |
5141 | break; | |
5142 | ||
a38bba38 | 5143 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5144 | case 0x0fc9: |
5145 | case 0x0fca: | |
5146 | case 0x0fcb: | |
5147 | case 0x0fcc: | |
5148 | case 0x0fcd: | |
5149 | case 0x0fce: | |
5150 | case 0x0fcf: | |
cf648174 | 5151 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5152 | break; |
5153 | ||
a38bba38 | 5154 | case 0xd6: /* salc */ |
cf648174 HZ |
5155 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5156 | { | |
5157 | ir.addr -= 1; | |
5158 | goto no_support; | |
5159 | } | |
5160 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5161 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5162 | break; |
5163 | ||
a38bba38 MS |
5164 | case 0xe0: /* loopnz */ |
5165 | case 0xe1: /* loopz */ | |
5166 | case 0xe2: /* loop */ | |
5167 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5168 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5169 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5170 | break; |
5171 | ||
a38bba38 | 5172 | case 0x0f30: /* wrmsr */ |
7ad10968 HZ |
5173 | printf_unfiltered (_("Process record doesn't support " |
5174 | "instruction wrmsr.\n")); | |
5175 | ir.addr -= 2; | |
5176 | goto no_support; | |
5177 | break; | |
5178 | ||
a38bba38 | 5179 | case 0x0f32: /* rdmsr */ |
7ad10968 HZ |
5180 | printf_unfiltered (_("Process record doesn't support " |
5181 | "instruction rdmsr.\n")); | |
5182 | ir.addr -= 2; | |
5183 | goto no_support; | |
5184 | break; | |
5185 | ||
a38bba38 | 5186 | case 0x0f31: /* rdtsc */ |
7ad10968 HZ |
5187 | printf_unfiltered (_("Process record doesn't support " |
5188 | "instruction rdtsc.\n")); | |
5189 | ir.addr -= 2; | |
5190 | goto no_support; | |
5191 | break; | |
5192 | ||
a38bba38 | 5193 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5194 | { |
5195 | int ret; | |
cf648174 HZ |
5196 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5197 | { | |
5198 | ir.addr -= 2; | |
5199 | goto no_support; | |
5200 | } | |
7ad10968 HZ |
5201 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
5202 | { | |
5203 | printf_unfiltered (_("Process record doesn't support " | |
5204 | "instruction sysenter.\n")); | |
5205 | ir.addr -= 2; | |
5206 | goto no_support; | |
5207 | } | |
5208 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
5209 | if (ret) | |
5210 | return ret; | |
5211 | } | |
5212 | break; | |
5213 | ||
a38bba38 | 5214 | case 0x0f35: /* sysexit */ |
7ad10968 HZ |
5215 | printf_unfiltered (_("Process record doesn't support " |
5216 | "instruction sysexit.\n")); | |
5217 | ir.addr -= 2; | |
5218 | goto no_support; | |
5219 | break; | |
5220 | ||
a38bba38 | 5221 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5222 | { |
5223 | int ret; | |
5224 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) | |
5225 | { | |
5226 | printf_unfiltered (_("Process record doesn't support " | |
5227 | "instruction syscall.\n")); | |
5228 | ir.addr -= 2; | |
5229 | goto no_support; | |
5230 | } | |
5231 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); | |
5232 | if (ret) | |
5233 | return ret; | |
5234 | } | |
5235 | break; | |
5236 | ||
a38bba38 | 5237 | case 0x0f07: /* sysret */ |
cf648174 HZ |
5238 | printf_unfiltered (_("Process record doesn't support " |
5239 | "instruction sysret.\n")); | |
5240 | ir.addr -= 2; | |
5241 | goto no_support; | |
5242 | break; | |
5243 | ||
a38bba38 | 5244 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5245 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5246 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5247 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5248 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5249 | break; |
5250 | ||
a38bba38 | 5251 | case 0xf4: /* hlt */ |
7ad10968 HZ |
5252 | printf_unfiltered (_("Process record doesn't support " |
5253 | "instruction hlt.\n")); | |
5254 | ir.addr -= 1; | |
5255 | goto no_support; | |
5256 | break; | |
5257 | ||
5258 | case 0x0f00: | |
5259 | if (i386_record_modrm (&ir)) | |
5260 | return -1; | |
5261 | switch (ir.reg) | |
5262 | { | |
a38bba38 MS |
5263 | case 0: /* sldt */ |
5264 | case 1: /* str */ | |
7ad10968 | 5265 | if (ir.mod == 3) |
cf648174 | 5266 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5267 | else |
5268 | { | |
5269 | ir.ot = OT_WORD; | |
5270 | if (i386_record_lea_modrm (&ir)) | |
5271 | return -1; | |
5272 | } | |
5273 | break; | |
a38bba38 MS |
5274 | case 2: /* lldt */ |
5275 | case 3: /* ltr */ | |
7ad10968 | 5276 | break; |
a38bba38 MS |
5277 | case 4: /* verr */ |
5278 | case 5: /* verw */ | |
cf648174 | 5279 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5280 | break; |
5281 | default: | |
5282 | ir.addr -= 3; | |
5283 | opcode = opcode << 8 | ir.modrm; | |
5284 | goto no_support; | |
5285 | break; | |
5286 | } | |
5287 | break; | |
5288 | ||
5289 | case 0x0f01: | |
5290 | if (i386_record_modrm (&ir)) | |
5291 | return -1; | |
5292 | switch (ir.reg) | |
5293 | { | |
a38bba38 | 5294 | case 0: /* sgdt */ |
7ad10968 | 5295 | { |
cf648174 | 5296 | uint64_t tmpu64; |
7ad10968 HZ |
5297 | |
5298 | if (ir.mod == 3) | |
5299 | { | |
5300 | ir.addr -= 3; | |
5301 | opcode = opcode << 8 | ir.modrm; | |
5302 | goto no_support; | |
5303 | } | |
d7877f7e | 5304 | if (ir.override >= 0) |
7ad10968 | 5305 | { |
df61f520 HZ |
5306 | warning (_("Process record ignores the memory " |
5307 | "change of instruction at " | |
5308 | "address %s because it can't get " | |
5309 | "the value of the segment " | |
5310 | "register."), | |
5311 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5312 | } |
5313 | else | |
5314 | { | |
cf648174 | 5315 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5316 | return -1; |
cf648174 | 5317 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 | 5318 | return -1; |
cf648174 HZ |
5319 | tmpu64 += 2; |
5320 | if (ir.regmap[X86_RECORD_R8_REGNUM]) | |
5321 | { | |
5322 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5323 | return -1; | |
5324 | } | |
5325 | else | |
5326 | { | |
5327 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5328 | return -1; | |
5329 | } | |
7ad10968 HZ |
5330 | } |
5331 | } | |
5332 | break; | |
5333 | case 1: | |
5334 | if (ir.mod == 3) | |
5335 | { | |
5336 | switch (ir.rm) | |
5337 | { | |
a38bba38 | 5338 | case 0: /* monitor */ |
7ad10968 | 5339 | break; |
a38bba38 | 5340 | case 1: /* mwait */ |
cf648174 | 5341 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5342 | break; |
5343 | default: | |
5344 | ir.addr -= 3; | |
5345 | opcode = opcode << 8 | ir.modrm; | |
5346 | goto no_support; | |
5347 | break; | |
5348 | } | |
5349 | } | |
5350 | else | |
5351 | { | |
5352 | /* sidt */ | |
d7877f7e | 5353 | if (ir.override >= 0) |
7ad10968 | 5354 | { |
df61f520 HZ |
5355 | warning (_("Process record ignores the memory " |
5356 | "change of instruction at " | |
5357 | "address %s because it can't get " | |
5358 | "the value of the segment " | |
5359 | "register."), | |
5360 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5361 | } |
5362 | else | |
5363 | { | |
cf648174 | 5364 | uint64_t tmpu64; |
7ad10968 | 5365 | |
cf648174 | 5366 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5367 | return -1; |
cf648174 | 5368 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
5369 | return -1; |
5370 | addr += 2; | |
cf648174 HZ |
5371 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5372 | { | |
5373 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5374 | return -1; | |
5375 | } | |
5376 | else | |
5377 | { | |
5378 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5379 | return -1; | |
5380 | } | |
7ad10968 HZ |
5381 | } |
5382 | } | |
5383 | break; | |
a38bba38 | 5384 | case 2: /* lgdt */ |
3800e645 MS |
5385 | if (ir.mod == 3) |
5386 | { | |
5387 | /* xgetbv */ | |
5388 | if (ir.rm == 0) | |
5389 | { | |
5390 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5391 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5392 | break; | |
5393 | } | |
5394 | /* xsetbv */ | |
5395 | else if (ir.rm == 1) | |
5396 | break; | |
5397 | } | |
a38bba38 | 5398 | case 3: /* lidt */ |
7ad10968 HZ |
5399 | if (ir.mod == 3) |
5400 | { | |
5401 | ir.addr -= 3; | |
5402 | opcode = opcode << 8 | ir.modrm; | |
5403 | goto no_support; | |
5404 | } | |
5405 | break; | |
a38bba38 | 5406 | case 4: /* smsw */ |
7ad10968 HZ |
5407 | if (ir.mod == 3) |
5408 | { | |
cf648174 | 5409 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5410 | return -1; |
5411 | } | |
5412 | else | |
5413 | { | |
5414 | ir.ot = OT_WORD; | |
5415 | if (i386_record_lea_modrm (&ir)) | |
5416 | return -1; | |
5417 | } | |
cf648174 | 5418 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5419 | break; |
a38bba38 | 5420 | case 6: /* lmsw */ |
cf648174 HZ |
5421 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5422 | break; | |
a38bba38 | 5423 | case 7: /* invlpg */ |
cf648174 HZ |
5424 | if (ir.mod == 3) |
5425 | { | |
5426 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5427 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5428 | else | |
5429 | { | |
5430 | ir.addr -= 3; | |
5431 | opcode = opcode << 8 | ir.modrm; | |
5432 | goto no_support; | |
5433 | } | |
5434 | } | |
5435 | else | |
5436 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5437 | break; | |
5438 | default: | |
5439 | ir.addr -= 3; | |
5440 | opcode = opcode << 8 | ir.modrm; | |
5441 | goto no_support; | |
7ad10968 HZ |
5442 | break; |
5443 | } | |
5444 | break; | |
5445 | ||
a38bba38 MS |
5446 | case 0x0f08: /* invd */ |
5447 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
5448 | break; |
5449 | ||
a38bba38 | 5450 | case 0x63: /* arpl */ |
7ad10968 HZ |
5451 | if (i386_record_modrm (&ir)) |
5452 | return -1; | |
cf648174 HZ |
5453 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5454 | { | |
5455 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5456 | ? (ir.reg | rex_r) : ir.rm); | |
5457 | } | |
7ad10968 | 5458 | else |
cf648174 HZ |
5459 | { |
5460 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5461 | if (i386_record_lea_modrm (&ir)) | |
5462 | return -1; | |
5463 | } | |
5464 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5465 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5466 | break; |
5467 | ||
a38bba38 MS |
5468 | case 0x0f02: /* lar */ |
5469 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
5470 | if (i386_record_modrm (&ir)) |
5471 | return -1; | |
cf648174 HZ |
5472 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5473 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5474 | break; |
5475 | ||
5476 | case 0x0f18: | |
cf648174 HZ |
5477 | if (i386_record_modrm (&ir)) |
5478 | return -1; | |
5479 | if (ir.mod == 3 && ir.reg == 3) | |
5480 | { | |
5481 | ir.addr -= 3; | |
5482 | opcode = opcode << 8 | ir.modrm; | |
5483 | goto no_support; | |
5484 | } | |
7ad10968 HZ |
5485 | break; |
5486 | ||
7ad10968 HZ |
5487 | case 0x0f19: |
5488 | case 0x0f1a: | |
5489 | case 0x0f1b: | |
5490 | case 0x0f1c: | |
5491 | case 0x0f1d: | |
5492 | case 0x0f1e: | |
5493 | case 0x0f1f: | |
a38bba38 | 5494 | /* nop (multi byte) */ |
7ad10968 HZ |
5495 | break; |
5496 | ||
a38bba38 MS |
5497 | case 0x0f20: /* mov reg, crN */ |
5498 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
5499 | if (i386_record_modrm (&ir)) |
5500 | return -1; | |
5501 | if ((ir.modrm & 0xc0) != 0xc0) | |
5502 | { | |
cf648174 | 5503 | ir.addr -= 3; |
7ad10968 HZ |
5504 | opcode = opcode << 8 | ir.modrm; |
5505 | goto no_support; | |
5506 | } | |
5507 | switch (ir.reg) | |
5508 | { | |
5509 | case 0: | |
5510 | case 2: | |
5511 | case 3: | |
5512 | case 4: | |
5513 | case 8: | |
5514 | if (opcode & 2) | |
cf648174 | 5515 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5516 | else |
cf648174 | 5517 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5518 | break; |
5519 | default: | |
cf648174 | 5520 | ir.addr -= 3; |
7ad10968 HZ |
5521 | opcode = opcode << 8 | ir.modrm; |
5522 | goto no_support; | |
5523 | break; | |
5524 | } | |
5525 | break; | |
5526 | ||
a38bba38 MS |
5527 | case 0x0f21: /* mov reg, drN */ |
5528 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
5529 | if (i386_record_modrm (&ir)) |
5530 | return -1; | |
5531 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5532 | || ir.reg == 5 || ir.reg >= 8) | |
5533 | { | |
cf648174 | 5534 | ir.addr -= 3; |
7ad10968 HZ |
5535 | opcode = opcode << 8 | ir.modrm; |
5536 | goto no_support; | |
5537 | } | |
5538 | if (opcode & 2) | |
cf648174 | 5539 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5540 | else |
cf648174 | 5541 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5542 | break; |
5543 | ||
a38bba38 | 5544 | case 0x0f06: /* clts */ |
cf648174 | 5545 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5546 | break; |
5547 | ||
5548 | /* MMX/SSE/SSE2/PNI support */ | |
5549 | /* XXX */ | |
5550 | ||
5551 | default: | |
5552 | if (opcode > 0xff) | |
5553 | ir.addr -= 2; | |
5554 | else | |
5555 | ir.addr -= 1; | |
5556 | goto no_support; | |
5557 | break; | |
5558 | } | |
5559 | ||
cf648174 HZ |
5560 | /* In the future, maybe still need to deal with need_dasm. */ |
5561 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
5562 | if (record_arch_list_add_end ()) |
5563 | return -1; | |
5564 | ||
5565 | return 0; | |
5566 | ||
01fe1b41 | 5567 | no_support: |
7ad10968 | 5568 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " |
5af949e3 UW |
5569 | "at address %s.\n"), |
5570 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5571 | return -1; |
5572 | } | |
5573 | ||
cf648174 HZ |
5574 | static const int i386_record_regmap[] = |
5575 | { | |
5576 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
5577 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
5578 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5579 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
5580 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
5581 | }; | |
5582 | ||
7a697b8d SS |
5583 | /* Check that the given address appears suitable for a fast |
5584 | tracepoint, which on x86 means that we need an instruction of at | |
5585 | least 5 bytes, so that we can overwrite it with a 4-byte-offset | |
5586 | jump and not have to worry about program jumps to an address in the | |
5587 | middle of the tracepoint jump. Returns 1 if OK, and writes a size | |
5588 | of instruction to replace, and 0 if not, plus an explanatory | |
5589 | string. */ | |
5590 | ||
5591 | static int | |
5592 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
5593 | CORE_ADDR addr, int *isize, char **msg) | |
5594 | { | |
5595 | int len, jumplen; | |
5596 | static struct ui_file *gdb_null = NULL; | |
5597 | ||
5598 | /* This is based on the target agent using a 4-byte relative jump. | |
5599 | Alternate future possibilities include 8-byte offset for x86-84, | |
5600 | or 3-byte jumps if the program has trampoline space close by. */ | |
5601 | jumplen = 5; | |
5602 | ||
5603 | /* Dummy file descriptor for the disassembler. */ | |
5604 | if (!gdb_null) | |
5605 | gdb_null = ui_file_new (); | |
5606 | ||
5607 | /* Check for fit. */ | |
5608 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
5609 | if (len < jumplen) | |
5610 | { | |
5611 | /* Return a bit of target-specific detail to add to the caller's | |
5612 | generic failure message. */ | |
5613 | if (msg) | |
5614 | *msg = xstrprintf (_("; instruction is only %d bytes long, need at least %d bytes for the jump"), | |
5615 | len, jumplen); | |
5616 | return 0; | |
5617 | } | |
5618 | ||
5619 | if (isize) | |
5620 | *isize = len; | |
5621 | if (msg) | |
5622 | *msg = NULL; | |
5623 | return 1; | |
5624 | } | |
5625 | ||
7ad10968 HZ |
5626 | \f |
5627 | static struct gdbarch * | |
5628 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5629 | { | |
5630 | struct gdbarch_tdep *tdep; | |
5631 | struct gdbarch *gdbarch; | |
5632 | ||
5633 | /* If there is already a candidate, use it. */ | |
5634 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5635 | if (arches != NULL) | |
5636 | return arches->gdbarch; | |
5637 | ||
5638 | /* Allocate space for the new architecture. */ | |
5639 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5640 | gdbarch = gdbarch_alloc (&info, tdep); | |
5641 | ||
5642 | /* General-purpose registers. */ | |
5643 | tdep->gregset = NULL; | |
5644 | tdep->gregset_reg_offset = NULL; | |
5645 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5646 | tdep->sizeof_gregset = 0; | |
5647 | ||
5648 | /* Floating-point registers. */ | |
5649 | tdep->fpregset = NULL; | |
5650 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5651 | ||
5652 | /* The default settings include the FPU registers, the MMX registers | |
5653 | and the SSE registers. This can be overridden for a specific ABI | |
5654 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5655 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5656 | will show up in the output of "info all-registers". Ideally we | |
5657 | should try to autodetect whether they are available, such that we | |
5658 | can prevent "info all-registers" from displaying registers that | |
5659 | aren't available. | |
5660 | ||
5661 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5662 | [the SSE registers] always (even when they don't exist) or never | |
5663 | showing them to the user (even when they do exist), I prefer the | |
5664 | former over the latter. */ | |
5665 | ||
5666 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5667 | ||
5668 | /* The MMX registers are implemented as pseudo-registers. Put off | |
5669 | calculating the register number for %mm0 until we know the number | |
5670 | of raw registers. */ | |
5671 | tdep->mm0_regnum = 0; | |
5672 | ||
5673 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
5674 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5675 | ||
5676 | tdep->jb_pc_offset = -1; | |
5677 | tdep->struct_return = pcc_struct_return; | |
5678 | tdep->sigtramp_start = 0; | |
5679 | tdep->sigtramp_end = 0; | |
5680 | tdep->sigtramp_p = i386_sigtramp_p; | |
5681 | tdep->sigcontext_addr = NULL; | |
5682 | tdep->sc_reg_offset = NULL; | |
5683 | tdep->sc_pc_offset = -1; | |
5684 | tdep->sc_sp_offset = -1; | |
5685 | ||
cf648174 HZ |
5686 | tdep->record_regmap = i386_record_regmap; |
5687 | ||
7ad10968 HZ |
5688 | /* The format used for `long double' on almost all i386 targets is |
5689 | the i387 extended floating-point format. In fact, of all targets | |
5690 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5691 | on having a `long double' that's not `long' at all. */ | |
5692 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5693 | ||
5694 | /* Although the i387 extended floating-point has only 80 significant | |
5695 | bits, a `long double' actually takes up 96, probably to enforce | |
5696 | alignment. */ | |
5697 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5698 | ||
5699 | /* The default ABI includes general-purpose registers, | |
5700 | floating-point registers, and the SSE registers. */ | |
5701 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5702 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
5703 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
5704 | ||
5705 | /* Register numbers of various important registers. */ | |
5706 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5707 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5708 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5709 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5710 | ||
5711 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5712 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5713 | differ in how they number %ebp, %esp, %eflags, and the | |
5714 | floating-point registers, and are implemented by the arrays | |
5715 | dbx_register_map[] and svr4_dbx_register_map in | |
5716 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5717 | gcc/config/i386.c, which it designates as the "default" register | |
5718 | map used in 64bit mode. This last register numbering scheme is | |
5719 | implemented in dbx64_register_map, and is used for AMD64; see | |
5720 | amd64-tdep.c. | |
5721 | ||
5722 | Currently, each GCC i386 target always uses the same register | |
5723 | numbering scheme across all its supported debugging formats | |
5724 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5725 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5726 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5727 | respective config header in a manner independent of the requested | |
5728 | output debugging format. | |
5729 | ||
5730 | This does not match the arrangement below, which presumes that | |
5731 | the SDB and stabs numbering schemes differ from the DWARF and | |
5732 | DWARF 2 ones. The reason for this arrangement is that it is | |
5733 | likely to get the numbering scheme for the target's | |
5734 | default/native debug format right. For targets where GCC is the | |
5735 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5736 | targets where the native toolchain uses a different numbering | |
5737 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5738 | the defaults below will have to be overridden, like | |
5739 | i386_elf_init_abi() does. */ | |
5740 | ||
5741 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5742 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5743 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5744 | ||
5745 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5746 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5747 | ||
5748 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5749 | be in use on any of the supported i386 targets. */ | |
5750 | ||
5751 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5752 | ||
5753 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5754 | ||
5755 | /* Call dummy code. */ | |
5756 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5757 | ||
5758 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5759 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5760 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5761 | ||
5762 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5763 | ||
5764 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5765 | ||
5766 | /* Stack grows downward. */ | |
5767 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5768 | ||
5769 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5770 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5771 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5772 | ||
5773 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5774 | ||
5775 | /* Wire in the MMX registers. */ | |
5776 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); | |
5777 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); | |
5778 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5779 | ||
5780 | set_gdbarch_print_insn (gdbarch, i386_print_insn); | |
5781 | ||
5782 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5783 | ||
5784 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5785 | ||
5786 | /* Add the i386 register groups. */ | |
5787 | i386_add_reggroups (gdbarch); | |
5788 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
38c968cf | 5789 | |
143985b7 AF |
5790 | /* Helper for function argument information. */ |
5791 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5792 | ||
06da04c6 MS |
5793 | /* Hook the function epilogue frame unwinder. This unwinder is |
5794 | appended to the list first, so that it supercedes the Dwarf | |
5795 | unwinder in function epilogues (where the Dwarf unwinder | |
5796 | currently fails). */ | |
5797 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
5798 | ||
5799 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
5800 | to the list before the prologue-based unwinders, so that Dwarf | |
5801 | CFI info will be used if it is available. */ | |
10458914 | 5802 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5803 | |
acd5c798 | 5804 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5805 | |
3ce1502b | 5806 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 5807 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5808 | |
06da04c6 | 5809 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
5810 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5811 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5812 | |
8446b36a MK |
5813 | /* If we have a register mapping, enable the generic core file |
5814 | support, unless it has already been enabled. */ | |
5815 | if (tdep->gregset_reg_offset | |
5816 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5817 | set_gdbarch_regset_from_core_section (gdbarch, | |
5818 | i386_regset_from_core_section); | |
5819 | ||
5716833c MK |
5820 | /* Unless support for MMX has been disabled, make %mm0 the first |
5821 | pseudo-register. */ | |
5822 | if (tdep->mm0_regnum == 0) | |
5823 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
5824 | ||
514f746b AR |
5825 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5826 | i386_skip_permanent_breakpoint); | |
5827 | ||
7a697b8d SS |
5828 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
5829 | i386_fast_tracepoint_valid_at); | |
5830 | ||
a62cc96e AC |
5831 | return gdbarch; |
5832 | } | |
5833 | ||
8201327c MK |
5834 | static enum gdb_osabi |
5835 | i386_coff_osabi_sniffer (bfd *abfd) | |
5836 | { | |
762c5349 MK |
5837 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5838 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5839 | return GDB_OSABI_GO32; |
5840 | ||
5841 | return GDB_OSABI_UNKNOWN; | |
5842 | } | |
8201327c MK |
5843 | \f |
5844 | ||
28e9e0f0 MK |
5845 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5846 | void _initialize_i386_tdep (void); | |
5847 | ||
c906108c | 5848 | void |
fba45db2 | 5849 | _initialize_i386_tdep (void) |
c906108c | 5850 | { |
a62cc96e AC |
5851 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5852 | ||
fc338970 | 5853 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5854 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5855 | &disassembly_flavor, _("\ | |
5856 | Set the disassembly flavor."), _("\ | |
5857 | Show the disassembly flavor."), _("\ | |
5858 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5859 | NULL, | |
5860 | NULL, /* FIXME: i18n: */ | |
5861 | &setlist, &showlist); | |
8201327c MK |
5862 | |
5863 | /* Add the variable that controls the convention for returning | |
5864 | structs. */ | |
7ab04401 AC |
5865 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5866 | &struct_convention, _("\ | |
5867 | Set the convention for returning small structs."), _("\ | |
5868 | Show the convention for returning small structs."), _("\ | |
5869 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5870 | is \"default\"."), | |
5871 | NULL, | |
5872 | NULL, /* FIXME: i18n: */ | |
5873 | &setlist, &showlist); | |
8201327c MK |
5874 | |
5875 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5876 | i386_coff_osabi_sniffer); | |
8201327c | 5877 | |
05816f70 | 5878 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5879 | i386_svr4_init_abi); |
05816f70 | 5880 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 5881 | i386_go32_init_abi); |
38c968cf | 5882 | |
209bd28e | 5883 | /* Initialize the i386-specific register groups. */ |
38c968cf | 5884 | i386_init_reggroups (); |
c906108c | 5885 | } |