Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
fd0407d6 | 42 | #include "value.h" |
a89aa300 | 43 | #include "dis-asm.h" |
7a697b8d | 44 | #include "disasm.h" |
c8d5aac9 | 45 | #include "remote.h" |
8fbca658 | 46 | #include "exceptions.h" |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
c131fcee | 52 | #include "i386-xstate.h" |
d2a7c97a | 53 | |
7ad10968 HZ |
54 | #include "record.h" |
55 | #include <stdint.h> | |
56 | ||
90884b2b | 57 | #include "features/i386/i386.c" |
c131fcee | 58 | #include "features/i386/i386-avx.c" |
3a13a53b | 59 | #include "features/i386/i386-mmx.c" |
90884b2b | 60 | |
6710bf39 SS |
61 | #include "ax.h" |
62 | #include "ax-gdb.h" | |
63 | ||
c4fc7f1b | 64 | /* Register names. */ |
c40e1eab | 65 | |
90884b2b | 66 | static const char *i386_register_names[] = |
fc633446 MK |
67 | { |
68 | "eax", "ecx", "edx", "ebx", | |
69 | "esp", "ebp", "esi", "edi", | |
70 | "eip", "eflags", "cs", "ss", | |
71 | "ds", "es", "fs", "gs", | |
72 | "st0", "st1", "st2", "st3", | |
73 | "st4", "st5", "st6", "st7", | |
74 | "fctrl", "fstat", "ftag", "fiseg", | |
75 | "fioff", "foseg", "fooff", "fop", | |
76 | "xmm0", "xmm1", "xmm2", "xmm3", | |
77 | "xmm4", "xmm5", "xmm6", "xmm7", | |
78 | "mxcsr" | |
79 | }; | |
80 | ||
c131fcee L |
81 | static const char *i386_ymm_names[] = |
82 | { | |
83 | "ymm0", "ymm1", "ymm2", "ymm3", | |
84 | "ymm4", "ymm5", "ymm6", "ymm7", | |
85 | }; | |
86 | ||
87 | static const char *i386_ymmh_names[] = | |
88 | { | |
89 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
90 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
91 | }; | |
92 | ||
c4fc7f1b | 93 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 94 | |
90884b2b | 95 | static const char *i386_mmx_names[] = |
28fc6740 AC |
96 | { |
97 | "mm0", "mm1", "mm2", "mm3", | |
98 | "mm4", "mm5", "mm6", "mm7" | |
99 | }; | |
c40e1eab | 100 | |
1ba53b71 L |
101 | /* Register names for byte pseudo-registers. */ |
102 | ||
103 | static const char *i386_byte_names[] = | |
104 | { | |
105 | "al", "cl", "dl", "bl", | |
106 | "ah", "ch", "dh", "bh" | |
107 | }; | |
108 | ||
109 | /* Register names for word pseudo-registers. */ | |
110 | ||
111 | static const char *i386_word_names[] = | |
112 | { | |
113 | "ax", "cx", "dx", "bx", | |
9cad29ac | 114 | "", "bp", "si", "di" |
1ba53b71 L |
115 | }; |
116 | ||
117 | /* MMX register? */ | |
c40e1eab | 118 | |
28fc6740 | 119 | static int |
5716833c | 120 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 121 | { |
1ba53b71 L |
122 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
123 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
124 | |
125 | if (mm0_regnum < 0) | |
126 | return 0; | |
127 | ||
1ba53b71 L |
128 | regnum -= mm0_regnum; |
129 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
130 | } | |
131 | ||
132 | /* Byte register? */ | |
133 | ||
134 | int | |
135 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
136 | { | |
137 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
138 | ||
139 | regnum -= tdep->al_regnum; | |
140 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
141 | } | |
142 | ||
143 | /* Word register? */ | |
144 | ||
145 | int | |
146 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
147 | { | |
148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
149 | ||
150 | regnum -= tdep->ax_regnum; | |
151 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
152 | } | |
153 | ||
154 | /* Dword register? */ | |
155 | ||
156 | int | |
157 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
158 | { | |
159 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
160 | int eax_regnum = tdep->eax_regnum; | |
161 | ||
162 | if (eax_regnum < 0) | |
163 | return 0; | |
164 | ||
165 | regnum -= eax_regnum; | |
166 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
167 | } |
168 | ||
9191d390 | 169 | static int |
c131fcee L |
170 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
171 | { | |
172 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
173 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
174 | ||
175 | if (ymm0h_regnum < 0) | |
176 | return 0; | |
177 | ||
178 | regnum -= ymm0h_regnum; | |
179 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
180 | } | |
181 | ||
182 | /* AVX register? */ | |
183 | ||
184 | int | |
185 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
186 | { | |
187 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
188 | int ymm0_regnum = tdep->ymm0_regnum; | |
189 | ||
190 | if (ymm0_regnum < 0) | |
191 | return 0; | |
192 | ||
193 | regnum -= ymm0_regnum; | |
194 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
195 | } | |
196 | ||
5716833c | 197 | /* SSE register? */ |
23a34459 | 198 | |
c131fcee L |
199 | int |
200 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 201 | { |
5716833c | 202 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 203 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 204 | |
c131fcee | 205 | if (num_xmm_regs == 0) |
5716833c MK |
206 | return 0; |
207 | ||
c131fcee L |
208 | regnum -= I387_XMM0_REGNUM (tdep); |
209 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
210 | } |
211 | ||
5716833c MK |
212 | static int |
213 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 214 | { |
5716833c MK |
215 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
216 | ||
20a6ec49 | 217 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
218 | return 0; |
219 | ||
20a6ec49 | 220 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
221 | } |
222 | ||
5716833c | 223 | /* FP register? */ |
23a34459 AC |
224 | |
225 | int | |
20a6ec49 | 226 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 227 | { |
20a6ec49 MD |
228 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
229 | ||
230 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
231 | return 0; |
232 | ||
20a6ec49 MD |
233 | return (I387_ST0_REGNUM (tdep) <= regnum |
234 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
235 | } |
236 | ||
237 | int | |
20a6ec49 | 238 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 239 | { |
20a6ec49 MD |
240 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
241 | ||
242 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
243 | return 0; |
244 | ||
20a6ec49 MD |
245 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
246 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
247 | } |
248 | ||
c131fcee L |
249 | /* Return the name of register REGNUM, or the empty string if it is |
250 | an anonymous register. */ | |
251 | ||
252 | static const char * | |
253 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
254 | { | |
255 | /* Hide the upper YMM registers. */ | |
256 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
257 | return ""; | |
258 | ||
259 | return tdesc_register_name (gdbarch, regnum); | |
260 | } | |
261 | ||
30b0e2d8 | 262 | /* Return the name of register REGNUM. */ |
fc633446 | 263 | |
1ba53b71 | 264 | const char * |
90884b2b | 265 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 266 | { |
1ba53b71 L |
267 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
268 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
269 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
270 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
271 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
1ba53b71 L |
272 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
273 | return i386_byte_names[regnum - tdep->al_regnum]; | |
274 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
275 | return i386_word_names[regnum - tdep->ax_regnum]; | |
276 | ||
277 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
278 | } |
279 | ||
c4fc7f1b | 280 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
281 | number used by GDB. */ |
282 | ||
8201327c | 283 | static int |
d3f73121 | 284 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 285 | { |
20a6ec49 MD |
286 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
287 | ||
c4fc7f1b MK |
288 | /* This implements what GCC calls the "default" register map |
289 | (dbx_register_map[]). */ | |
290 | ||
85540d8c MK |
291 | if (reg >= 0 && reg <= 7) |
292 | { | |
9872ad24 JB |
293 | /* General-purpose registers. The debug info calls %ebp |
294 | register 4, and %esp register 5. */ | |
295 | if (reg == 4) | |
296 | return 5; | |
297 | else if (reg == 5) | |
298 | return 4; | |
299 | else return reg; | |
85540d8c MK |
300 | } |
301 | else if (reg >= 12 && reg <= 19) | |
302 | { | |
303 | /* Floating-point registers. */ | |
20a6ec49 | 304 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
305 | } |
306 | else if (reg >= 21 && reg <= 28) | |
307 | { | |
308 | /* SSE registers. */ | |
c131fcee L |
309 | int ymm0_regnum = tdep->ymm0_regnum; |
310 | ||
311 | if (ymm0_regnum >= 0 | |
312 | && i386_xmm_regnum_p (gdbarch, reg)) | |
313 | return reg - 21 + ymm0_regnum; | |
314 | else | |
315 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
316 | } |
317 | else if (reg >= 29 && reg <= 36) | |
318 | { | |
319 | /* MMX registers. */ | |
20a6ec49 | 320 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
321 | } |
322 | ||
323 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 324 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
325 | } |
326 | ||
c4fc7f1b MK |
327 | /* Convert SVR4 register number REG to the appropriate register number |
328 | used by GDB. */ | |
85540d8c | 329 | |
8201327c | 330 | static int |
d3f73121 | 331 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 332 | { |
20a6ec49 MD |
333 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
334 | ||
c4fc7f1b MK |
335 | /* This implements the GCC register map that tries to be compatible |
336 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
337 | ||
338 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
339 | numbers the floating point registers differently. */ |
340 | if (reg >= 0 && reg <= 9) | |
341 | { | |
acd5c798 | 342 | /* General-purpose registers. */ |
85540d8c MK |
343 | return reg; |
344 | } | |
345 | else if (reg >= 11 && reg <= 18) | |
346 | { | |
347 | /* Floating-point registers. */ | |
20a6ec49 | 348 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 349 | } |
c6f4c129 | 350 | else if (reg >= 21 && reg <= 36) |
85540d8c | 351 | { |
c4fc7f1b | 352 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 353 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
354 | } |
355 | ||
c6f4c129 JB |
356 | switch (reg) |
357 | { | |
20a6ec49 MD |
358 | case 37: return I387_FCTRL_REGNUM (tdep); |
359 | case 38: return I387_FSTAT_REGNUM (tdep); | |
360 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
361 | case 40: return I386_ES_REGNUM; |
362 | case 41: return I386_CS_REGNUM; | |
363 | case 42: return I386_SS_REGNUM; | |
364 | case 43: return I386_DS_REGNUM; | |
365 | case 44: return I386_FS_REGNUM; | |
366 | case 45: return I386_GS_REGNUM; | |
367 | } | |
368 | ||
85540d8c | 369 | /* This will hopefully provoke a warning. */ |
d3f73121 | 370 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 371 | } |
5716833c | 372 | |
fc338970 | 373 | \f |
917317f4 | 374 | |
fc338970 MK |
375 | /* This is the variable that is set with "set disassembly-flavor", and |
376 | its legitimate values. */ | |
53904c9e AC |
377 | static const char att_flavor[] = "att"; |
378 | static const char intel_flavor[] = "intel"; | |
379 | static const char *valid_flavors[] = | |
c5aa993b | 380 | { |
c906108c SS |
381 | att_flavor, |
382 | intel_flavor, | |
383 | NULL | |
384 | }; | |
53904c9e | 385 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 386 | \f |
c906108c | 387 | |
acd5c798 MK |
388 | /* Use the program counter to determine the contents and size of a |
389 | breakpoint instruction. Return a pointer to a string of bytes that | |
390 | encode a breakpoint instruction, store the length of the string in | |
391 | *LEN and optionally adjust *PC to point to the correct memory | |
392 | location for inserting the breakpoint. | |
c906108c | 393 | |
acd5c798 MK |
394 | On the i386 we have a single breakpoint that fits in a single byte |
395 | and can be inserted anywhere. | |
c906108c | 396 | |
acd5c798 | 397 | This function is 64-bit safe. */ |
63c0089f MK |
398 | |
399 | static const gdb_byte * | |
67d57894 | 400 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 401 | { |
63c0089f MK |
402 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
403 | ||
acd5c798 MK |
404 | *len = sizeof (break_insn); |
405 | return break_insn; | |
c906108c | 406 | } |
237fc4c9 PA |
407 | \f |
408 | /* Displaced instruction handling. */ | |
409 | ||
1903f0e6 DE |
410 | /* Skip the legacy instruction prefixes in INSN. |
411 | Not all prefixes are valid for any particular insn | |
412 | but we needn't care, the insn will fault if it's invalid. | |
413 | The result is a pointer to the first opcode byte, | |
414 | or NULL if we run off the end of the buffer. */ | |
415 | ||
416 | static gdb_byte * | |
417 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
418 | { | |
419 | gdb_byte *end = insn + max_len; | |
420 | ||
421 | while (insn < end) | |
422 | { | |
423 | switch (*insn) | |
424 | { | |
425 | case DATA_PREFIX_OPCODE: | |
426 | case ADDR_PREFIX_OPCODE: | |
427 | case CS_PREFIX_OPCODE: | |
428 | case DS_PREFIX_OPCODE: | |
429 | case ES_PREFIX_OPCODE: | |
430 | case FS_PREFIX_OPCODE: | |
431 | case GS_PREFIX_OPCODE: | |
432 | case SS_PREFIX_OPCODE: | |
433 | case LOCK_PREFIX_OPCODE: | |
434 | case REPE_PREFIX_OPCODE: | |
435 | case REPNE_PREFIX_OPCODE: | |
436 | ++insn; | |
437 | continue; | |
438 | default: | |
439 | return insn; | |
440 | } | |
441 | } | |
442 | ||
443 | return NULL; | |
444 | } | |
237fc4c9 PA |
445 | |
446 | static int | |
1903f0e6 | 447 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 448 | { |
1777feb0 | 449 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
450 | if (insn[0] == 0xea) |
451 | return 1; | |
452 | ||
453 | if (insn[0] == 0xff) | |
454 | { | |
1777feb0 | 455 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
456 | if ((insn[1] & 0x38) == 0x20) |
457 | return 1; | |
458 | ||
1777feb0 | 459 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
460 | if ((insn[1] & 0x38) == 0x28) |
461 | return 1; | |
462 | } | |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int | |
1903f0e6 | 468 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 469 | { |
1777feb0 | 470 | /* call far, absolute. */ |
237fc4c9 PA |
471 | if (insn[0] == 0x9a) |
472 | return 1; | |
473 | ||
474 | if (insn[0] == 0xff) | |
475 | { | |
1777feb0 | 476 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
477 | if ((insn[1] & 0x38) == 0x10) |
478 | return 1; | |
479 | ||
1777feb0 | 480 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
481 | if ((insn[1] & 0x38) == 0x18) |
482 | return 1; | |
483 | } | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int | |
1903f0e6 | 489 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
490 | { |
491 | switch (insn[0]) | |
492 | { | |
1777feb0 | 493 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 494 | case 0xc3: /* ret near */ |
1777feb0 | 495 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
496 | case 0xcb: /* ret far */ |
497 | case 0xcf: /* iret */ | |
498 | return 1; | |
499 | ||
500 | default: | |
501 | return 0; | |
502 | } | |
503 | } | |
504 | ||
505 | static int | |
1903f0e6 | 506 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
507 | { |
508 | if (i386_absolute_call_p (insn)) | |
509 | return 1; | |
510 | ||
1777feb0 | 511 | /* call near, relative. */ |
237fc4c9 PA |
512 | if (insn[0] == 0xe8) |
513 | return 1; | |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
237fc4c9 PA |
518 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
519 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 520 | |
237fc4c9 | 521 | static int |
b55078be | 522 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 PA |
523 | { |
524 | if (insn[0] == 0xcd) | |
525 | { | |
526 | *lengthp = 2; | |
527 | return 1; | |
528 | } | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
b55078be DE |
533 | /* Some kernels may run one past a syscall insn, so we have to cope. |
534 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
535 | ||
536 | struct displaced_step_closure * | |
537 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
538 | CORE_ADDR from, CORE_ADDR to, | |
539 | struct regcache *regs) | |
540 | { | |
541 | size_t len = gdbarch_max_insn_length (gdbarch); | |
542 | gdb_byte *buf = xmalloc (len); | |
543 | ||
544 | read_memory (from, buf, len); | |
545 | ||
546 | /* GDB may get control back after the insn after the syscall. | |
547 | Presumably this is a kernel bug. | |
548 | If this is a syscall, make sure there's a nop afterwards. */ | |
549 | { | |
550 | int syscall_length; | |
551 | gdb_byte *insn; | |
552 | ||
553 | insn = i386_skip_prefixes (buf, len); | |
554 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
555 | insn[syscall_length] = NOP_OPCODE; | |
556 | } | |
557 | ||
558 | write_memory (to, buf, len); | |
559 | ||
560 | if (debug_displaced) | |
561 | { | |
562 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
563 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
564 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
565 | } | |
566 | ||
567 | return (struct displaced_step_closure *) buf; | |
568 | } | |
569 | ||
237fc4c9 PA |
570 | /* Fix up the state of registers and memory after having single-stepped |
571 | a displaced instruction. */ | |
1903f0e6 | 572 | |
237fc4c9 PA |
573 | void |
574 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
575 | struct displaced_step_closure *closure, | |
576 | CORE_ADDR from, CORE_ADDR to, | |
577 | struct regcache *regs) | |
578 | { | |
e17a4113 UW |
579 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
580 | ||
237fc4c9 PA |
581 | /* The offset we applied to the instruction's address. |
582 | This could well be negative (when viewed as a signed 32-bit | |
583 | value), but ULONGEST won't reflect that, so take care when | |
584 | applying it. */ | |
585 | ULONGEST insn_offset = to - from; | |
586 | ||
587 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
588 | copy of the instruction. */ | |
589 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
590 | /* The start of the insn, needed in case we see some prefixes. */ |
591 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
592 | |
593 | if (debug_displaced) | |
594 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 595 | "displaced: fixup (%s, %s), " |
237fc4c9 | 596 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
597 | paddress (gdbarch, from), paddress (gdbarch, to), |
598 | insn[0], insn[1]); | |
237fc4c9 PA |
599 | |
600 | /* The list of issues to contend with here is taken from | |
601 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
602 | Yay for Free Software! */ | |
603 | ||
604 | /* Relocate the %eip, if necessary. */ | |
605 | ||
1903f0e6 DE |
606 | /* The instruction recognizers we use assume any leading prefixes |
607 | have been skipped. */ | |
608 | { | |
609 | /* This is the size of the buffer in closure. */ | |
610 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
611 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
612 | /* If there are too many prefixes, just ignore the insn. | |
613 | It will fault when run. */ | |
614 | if (opcode != NULL) | |
615 | insn = opcode; | |
616 | } | |
617 | ||
237fc4c9 PA |
618 | /* Except in the case of absolute or indirect jump or call |
619 | instructions, or a return instruction, the new eip is relative to | |
620 | the displaced instruction; make it relative. Well, signal | |
621 | handler returns don't need relocation either, but we use the | |
622 | value of %eip to recognize those; see below. */ | |
623 | if (! i386_absolute_jmp_p (insn) | |
624 | && ! i386_absolute_call_p (insn) | |
625 | && ! i386_ret_p (insn)) | |
626 | { | |
627 | ULONGEST orig_eip; | |
b55078be | 628 | int insn_len; |
237fc4c9 PA |
629 | |
630 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
631 | ||
632 | /* A signal trampoline system call changes the %eip, resuming | |
633 | execution of the main program after the signal handler has | |
634 | returned. That makes them like 'return' instructions; we | |
635 | shouldn't relocate %eip. | |
636 | ||
637 | But most system calls don't, and we do need to relocate %eip. | |
638 | ||
639 | Our heuristic for distinguishing these cases: if stepping | |
640 | over the system call instruction left control directly after | |
641 | the instruction, the we relocate --- control almost certainly | |
642 | doesn't belong in the displaced copy. Otherwise, we assume | |
643 | the instruction has put control where it belongs, and leave | |
644 | it unrelocated. Goodness help us if there are PC-relative | |
645 | system calls. */ | |
646 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
647 | && orig_eip != to + (insn - insn_start) + insn_len |
648 | /* GDB can get control back after the insn after the syscall. | |
649 | Presumably this is a kernel bug. | |
650 | i386_displaced_step_copy_insn ensures its a nop, | |
651 | we add one to the length for it. */ | |
652 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
653 | { |
654 | if (debug_displaced) | |
655 | fprintf_unfiltered (gdb_stdlog, | |
656 | "displaced: syscall changed %%eip; " | |
657 | "not relocating\n"); | |
658 | } | |
659 | else | |
660 | { | |
661 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
662 | ||
1903f0e6 DE |
663 | /* If we just stepped over a breakpoint insn, we don't backup |
664 | the pc on purpose; this is to match behaviour without | |
665 | stepping. */ | |
237fc4c9 PA |
666 | |
667 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
668 | ||
669 | if (debug_displaced) | |
670 | fprintf_unfiltered (gdb_stdlog, | |
671 | "displaced: " | |
5af949e3 UW |
672 | "relocated %%eip from %s to %s\n", |
673 | paddress (gdbarch, orig_eip), | |
674 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
675 | } |
676 | } | |
677 | ||
678 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
679 | pushed value, and should be cleared. We'll leave this for later, | |
680 | since GDB already messes up the TF flag when stepping over a | |
681 | pushfl. */ | |
682 | ||
683 | /* If the instruction was a call, the return address now atop the | |
684 | stack is the address following the copied instruction. We need | |
685 | to make it the address following the original instruction. */ | |
686 | if (i386_call_p (insn)) | |
687 | { | |
688 | ULONGEST esp; | |
689 | ULONGEST retaddr; | |
690 | const ULONGEST retaddr_len = 4; | |
691 | ||
692 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 693 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 694 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 695 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
696 | |
697 | if (debug_displaced) | |
698 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
699 | "displaced: relocated return addr at %s to %s\n", |
700 | paddress (gdbarch, esp), | |
701 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
702 | } |
703 | } | |
dde08ee1 PA |
704 | |
705 | static void | |
706 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
707 | { | |
708 | target_write_memory (*to, buf, len); | |
709 | *to += len; | |
710 | } | |
711 | ||
712 | static void | |
713 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
714 | CORE_ADDR *to, CORE_ADDR oldloc) | |
715 | { | |
716 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
717 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
718 | int offset = 0, rel32, newrel; | |
719 | int insn_length; | |
720 | gdb_byte *insn = buf; | |
721 | ||
722 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
723 | ||
724 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
725 | I386_MAX_INSN_LEN, oldloc); | |
726 | ||
727 | /* Get past the prefixes. */ | |
728 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
729 | ||
730 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
731 | the address pushed being the location where the original call in | |
732 | the user program would return to. */ | |
733 | if (insn[0] == 0xe8) | |
734 | { | |
735 | gdb_byte push_buf[16]; | |
736 | unsigned int ret_addr; | |
737 | ||
738 | /* Where "ret" in the original code will return to. */ | |
739 | ret_addr = oldloc + insn_length; | |
1777feb0 | 740 | push_buf[0] = 0x68; /* pushq $... */ |
dde08ee1 PA |
741 | memcpy (&push_buf[1], &ret_addr, 4); |
742 | /* Push the push. */ | |
743 | append_insns (to, 5, push_buf); | |
744 | ||
745 | /* Convert the relative call to a relative jump. */ | |
746 | insn[0] = 0xe9; | |
747 | ||
748 | /* Adjust the destination offset. */ | |
749 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
750 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
751 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
752 | ||
753 | if (debug_displaced) | |
754 | fprintf_unfiltered (gdb_stdlog, | |
755 | "Adjusted insn rel32=%s at %s to" | |
756 | " rel32=%s at %s\n", | |
757 | hex_string (rel32), paddress (gdbarch, oldloc), | |
758 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
759 | |
760 | /* Write the adjusted jump into its displaced location. */ | |
761 | append_insns (to, 5, insn); | |
762 | return; | |
763 | } | |
764 | ||
765 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
766 | handled above. */ | |
767 | if (insn[0] == 0xe9) | |
768 | offset = 1; | |
769 | /* Adjust conditional jumps. */ | |
770 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
771 | offset = 2; | |
772 | ||
773 | if (offset) | |
774 | { | |
775 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
776 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 777 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
778 | if (debug_displaced) |
779 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
780 | "Adjusted insn rel32=%s at %s to" |
781 | " rel32=%s at %s\n", | |
dde08ee1 PA |
782 | hex_string (rel32), paddress (gdbarch, oldloc), |
783 | hex_string (newrel), paddress (gdbarch, *to)); | |
784 | } | |
785 | ||
786 | /* Write the adjusted instructions into their displaced | |
787 | location. */ | |
788 | append_insns (to, insn_length, buf); | |
789 | } | |
790 | ||
fc338970 | 791 | \f |
acd5c798 MK |
792 | #ifdef I386_REGNO_TO_SYMMETRY |
793 | #error "The Sequent Symmetry is no longer supported." | |
794 | #endif | |
c906108c | 795 | |
acd5c798 MK |
796 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
797 | and %esp "belong" to the calling function. Therefore these | |
798 | registers should be saved if they're going to be modified. */ | |
c906108c | 799 | |
acd5c798 MK |
800 | /* The maximum number of saved registers. This should include all |
801 | registers mentioned above, and %eip. */ | |
a3386186 | 802 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
803 | |
804 | struct i386_frame_cache | |
c906108c | 805 | { |
acd5c798 MK |
806 | /* Base address. */ |
807 | CORE_ADDR base; | |
8fbca658 | 808 | int base_p; |
772562f8 | 809 | LONGEST sp_offset; |
acd5c798 MK |
810 | CORE_ADDR pc; |
811 | ||
fd13a04a AC |
812 | /* Saved registers. */ |
813 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 814 | CORE_ADDR saved_sp; |
e0c62198 | 815 | int saved_sp_reg; |
acd5c798 MK |
816 | int pc_in_eax; |
817 | ||
818 | /* Stack space reserved for local variables. */ | |
819 | long locals; | |
820 | }; | |
821 | ||
822 | /* Allocate and initialize a frame cache. */ | |
823 | ||
824 | static struct i386_frame_cache * | |
fd13a04a | 825 | i386_alloc_frame_cache (void) |
acd5c798 MK |
826 | { |
827 | struct i386_frame_cache *cache; | |
828 | int i; | |
829 | ||
830 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
831 | ||
832 | /* Base address. */ | |
8fbca658 | 833 | cache->base_p = 0; |
acd5c798 MK |
834 | cache->base = 0; |
835 | cache->sp_offset = -4; | |
836 | cache->pc = 0; | |
837 | ||
fd13a04a AC |
838 | /* Saved registers. We initialize these to -1 since zero is a valid |
839 | offset (that's where %ebp is supposed to be stored). */ | |
840 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
841 | cache->saved_regs[i] = -1; | |
acd5c798 | 842 | cache->saved_sp = 0; |
e0c62198 | 843 | cache->saved_sp_reg = -1; |
acd5c798 MK |
844 | cache->pc_in_eax = 0; |
845 | ||
846 | /* Frameless until proven otherwise. */ | |
847 | cache->locals = -1; | |
848 | ||
849 | return cache; | |
850 | } | |
c906108c | 851 | |
acd5c798 MK |
852 | /* If the instruction at PC is a jump, return the address of its |
853 | target. Otherwise, return PC. */ | |
c906108c | 854 | |
acd5c798 | 855 | static CORE_ADDR |
e17a4113 | 856 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 857 | { |
e17a4113 | 858 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 859 | gdb_byte op; |
acd5c798 MK |
860 | long delta = 0; |
861 | int data16 = 0; | |
c906108c | 862 | |
3dcabaa8 MS |
863 | if (target_read_memory (pc, &op, 1)) |
864 | return pc; | |
865 | ||
acd5c798 | 866 | if (op == 0x66) |
c906108c | 867 | { |
c906108c | 868 | data16 = 1; |
e17a4113 | 869 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
870 | } |
871 | ||
acd5c798 | 872 | switch (op) |
c906108c SS |
873 | { |
874 | case 0xe9: | |
fc338970 | 875 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
876 | if (data16) |
877 | { | |
e17a4113 | 878 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 879 | |
fc338970 MK |
880 | /* Include the size of the jmp instruction (including the |
881 | 0x66 prefix). */ | |
acd5c798 | 882 | delta += 4; |
c906108c SS |
883 | } |
884 | else | |
885 | { | |
e17a4113 | 886 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 887 | |
acd5c798 MK |
888 | /* Include the size of the jmp instruction. */ |
889 | delta += 5; | |
c906108c SS |
890 | } |
891 | break; | |
892 | case 0xeb: | |
fc338970 | 893 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 894 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 895 | |
acd5c798 | 896 | delta += data16 + 2; |
c906108c SS |
897 | break; |
898 | } | |
c906108c | 899 | |
acd5c798 MK |
900 | return pc + delta; |
901 | } | |
fc338970 | 902 | |
acd5c798 MK |
903 | /* Check whether PC points at a prologue for a function returning a |
904 | structure or union. If so, it updates CACHE and returns the | |
905 | address of the first instruction after the code sequence that | |
906 | removes the "hidden" argument from the stack or CURRENT_PC, | |
907 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 908 | |
acd5c798 MK |
909 | static CORE_ADDR |
910 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
911 | struct i386_frame_cache *cache) | |
c906108c | 912 | { |
acd5c798 MK |
913 | /* Functions that return a structure or union start with: |
914 | ||
915 | popl %eax 0x58 | |
916 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
917 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
918 | ||
919 | (the System V compiler puts out the second `xchg' instruction, | |
920 | and the assembler doesn't try to optimize it, so the 'sib' form | |
921 | gets generated). This sequence is used to get the address of the | |
922 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
923 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
924 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
925 | gdb_byte buf[4]; | |
926 | gdb_byte op; | |
c906108c | 927 | |
acd5c798 MK |
928 | if (current_pc <= pc) |
929 | return pc; | |
930 | ||
3dcabaa8 MS |
931 | if (target_read_memory (pc, &op, 1)) |
932 | return pc; | |
c906108c | 933 | |
acd5c798 MK |
934 | if (op != 0x58) /* popl %eax */ |
935 | return pc; | |
c906108c | 936 | |
3dcabaa8 MS |
937 | if (target_read_memory (pc + 1, buf, 4)) |
938 | return pc; | |
939 | ||
acd5c798 MK |
940 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
941 | return pc; | |
c906108c | 942 | |
acd5c798 | 943 | if (current_pc == pc) |
c906108c | 944 | { |
acd5c798 MK |
945 | cache->sp_offset += 4; |
946 | return current_pc; | |
c906108c SS |
947 | } |
948 | ||
acd5c798 | 949 | if (current_pc == pc + 1) |
c906108c | 950 | { |
acd5c798 MK |
951 | cache->pc_in_eax = 1; |
952 | return current_pc; | |
953 | } | |
954 | ||
955 | if (buf[1] == proto1[1]) | |
956 | return pc + 4; | |
957 | else | |
958 | return pc + 5; | |
959 | } | |
960 | ||
961 | static CORE_ADDR | |
962 | i386_skip_probe (CORE_ADDR pc) | |
963 | { | |
964 | /* A function may start with | |
fc338970 | 965 | |
acd5c798 MK |
966 | pushl constant |
967 | call _probe | |
968 | addl $4, %esp | |
fc338970 | 969 | |
acd5c798 MK |
970 | followed by |
971 | ||
972 | pushl %ebp | |
fc338970 | 973 | |
acd5c798 | 974 | etc. */ |
63c0089f MK |
975 | gdb_byte buf[8]; |
976 | gdb_byte op; | |
fc338970 | 977 | |
3dcabaa8 MS |
978 | if (target_read_memory (pc, &op, 1)) |
979 | return pc; | |
acd5c798 MK |
980 | |
981 | if (op == 0x68 || op == 0x6a) | |
982 | { | |
983 | int delta; | |
c906108c | 984 | |
acd5c798 MK |
985 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
986 | four-byte operand, depending on the opcode. */ | |
c906108c | 987 | if (op == 0x68) |
acd5c798 | 988 | delta = 5; |
c906108c | 989 | else |
acd5c798 | 990 | delta = 2; |
c906108c | 991 | |
acd5c798 MK |
992 | /* Read the following 8 bytes, which should be `call _probe' (6 |
993 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
994 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 995 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 996 | pc += delta + sizeof (buf); |
c906108c SS |
997 | } |
998 | ||
acd5c798 MK |
999 | return pc; |
1000 | } | |
1001 | ||
92dd43fa MK |
1002 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1003 | stack pointer. Check whether PC points to such code, and update | |
1004 | CACHE accordingly. Return the first instruction after the code | |
1005 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1006 | recognize the code, return PC. */ | |
1007 | ||
1008 | static CORE_ADDR | |
1009 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1010 | struct i386_frame_cache *cache) | |
1011 | { | |
e0c62198 L |
1012 | /* There are 2 code sequences to re-align stack before the frame |
1013 | gets set up: | |
1014 | ||
1015 | 1. Use a caller-saved saved register: | |
1016 | ||
1017 | leal 4(%esp), %reg | |
1018 | andl $-XXX, %esp | |
1019 | pushl -4(%reg) | |
1020 | ||
1021 | 2. Use a callee-saved saved register: | |
1022 | ||
1023 | pushl %reg | |
1024 | leal 8(%esp), %reg | |
1025 | andl $-XXX, %esp | |
1026 | pushl -4(%reg) | |
1027 | ||
1028 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1029 | ||
1030 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1031 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1032 | */ | |
1033 | ||
1034 | gdb_byte buf[14]; | |
1035 | int reg; | |
1036 | int offset, offset_and; | |
1037 | static int regnums[8] = { | |
1038 | I386_EAX_REGNUM, /* %eax */ | |
1039 | I386_ECX_REGNUM, /* %ecx */ | |
1040 | I386_EDX_REGNUM, /* %edx */ | |
1041 | I386_EBX_REGNUM, /* %ebx */ | |
1042 | I386_ESP_REGNUM, /* %esp */ | |
1043 | I386_EBP_REGNUM, /* %ebp */ | |
1044 | I386_ESI_REGNUM, /* %esi */ | |
1045 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1046 | }; |
92dd43fa | 1047 | |
e0c62198 L |
1048 | if (target_read_memory (pc, buf, sizeof buf)) |
1049 | return pc; | |
1050 | ||
1051 | /* Check caller-saved saved register. The first instruction has | |
1052 | to be "leal 4(%esp), %reg". */ | |
1053 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1054 | { | |
1055 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1056 | if ((buf[1] & 0xc7) != 0x44) | |
1057 | return pc; | |
1058 | ||
1059 | /* REG has register number. */ | |
1060 | reg = (buf[1] >> 3) & 7; | |
1061 | offset = 4; | |
1062 | } | |
1063 | else | |
1064 | { | |
1065 | /* Check callee-saved saved register. The first instruction | |
1066 | has to be "pushl %reg". */ | |
1067 | if ((buf[0] & 0xf8) != 0x50) | |
1068 | return pc; | |
1069 | ||
1070 | /* Get register. */ | |
1071 | reg = buf[0] & 0x7; | |
1072 | ||
1073 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1074 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1075 | return pc; | |
1076 | ||
1077 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1078 | if ((buf[2] & 0xc7) != 0x44) | |
1079 | return pc; | |
1080 | ||
1081 | /* REG has register number. Registers in pushl and leal have to | |
1082 | be the same. */ | |
1083 | if (reg != ((buf[2] >> 3) & 7)) | |
1084 | return pc; | |
1085 | ||
1086 | offset = 5; | |
1087 | } | |
1088 | ||
1089 | /* Rigister can't be %esp nor %ebp. */ | |
1090 | if (reg == 4 || reg == 5) | |
1091 | return pc; | |
1092 | ||
1093 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1094 | if (buf[offset + 1] != 0xe4 | |
1095 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1096 | return pc; | |
1097 | ||
1098 | offset_and = offset; | |
1099 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1100 | ||
1101 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1102 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1103 | if (buf[offset] != 0xff | |
1104 | || buf[offset + 2] != 0xfc | |
1105 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1106 | return pc; | |
1107 | ||
1108 | /* R/M has register. Registers in leal and pushl have to be the | |
1109 | same. */ | |
1110 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1111 | return pc; |
1112 | ||
e0c62198 L |
1113 | if (current_pc > pc + offset_and) |
1114 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1115 | |
e0c62198 | 1116 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
1117 | } |
1118 | ||
37bdc87e | 1119 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1120 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1121 | |
1122 | /* Instruction description. */ | |
1123 | struct i386_insn | |
1124 | { | |
1125 | size_t len; | |
237fc4c9 PA |
1126 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1127 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1128 | }; |
1129 | ||
a3fcb948 | 1130 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1131 | |
a3fcb948 JG |
1132 | static int |
1133 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1134 | { |
63c0089f | 1135 | gdb_byte op; |
37bdc87e | 1136 | |
3dcabaa8 | 1137 | if (target_read_memory (pc, &op, 1)) |
a3fcb948 | 1138 | return 0; |
37bdc87e | 1139 | |
a3fcb948 | 1140 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1141 | { |
a3fcb948 JG |
1142 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1143 | int insn_matched = 1; | |
1144 | size_t i; | |
37bdc87e | 1145 | |
a3fcb948 JG |
1146 | gdb_assert (pattern.len > 1); |
1147 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1148 | |
a3fcb948 JG |
1149 | if (target_read_memory (pc + 1, buf, pattern.len - 1)) |
1150 | return 0; | |
613e8135 | 1151 | |
a3fcb948 JG |
1152 | for (i = 1; i < pattern.len; i++) |
1153 | { | |
1154 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1155 | insn_matched = 0; | |
37bdc87e | 1156 | } |
a3fcb948 JG |
1157 | return insn_matched; |
1158 | } | |
1159 | return 0; | |
1160 | } | |
1161 | ||
1162 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1163 | the first instruction description that matches. Otherwise, return | |
1164 | NULL. */ | |
1165 | ||
1166 | static struct i386_insn * | |
1167 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1168 | { | |
1169 | struct i386_insn *pattern; | |
1170 | ||
1171 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1172 | { | |
1173 | if (i386_match_pattern (pc, *pattern)) | |
1174 | return pattern; | |
37bdc87e MK |
1175 | } |
1176 | ||
1177 | return NULL; | |
1178 | } | |
1179 | ||
a3fcb948 JG |
1180 | /* Return whether PC points inside a sequence of instructions that |
1181 | matches INSN_PATTERNS. */ | |
1182 | ||
1183 | static int | |
1184 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1185 | { | |
1186 | CORE_ADDR current_pc; | |
1187 | int ix, i; | |
1188 | gdb_byte op; | |
1189 | struct i386_insn *insn; | |
1190 | ||
1191 | insn = i386_match_insn (pc, insn_patterns); | |
1192 | if (insn == NULL) | |
1193 | return 0; | |
1194 | ||
8bbdd3f4 | 1195 | current_pc = pc; |
a3fcb948 JG |
1196 | ix = insn - insn_patterns; |
1197 | for (i = ix - 1; i >= 0; i--) | |
1198 | { | |
8bbdd3f4 MK |
1199 | current_pc -= insn_patterns[i].len; |
1200 | ||
a3fcb948 JG |
1201 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1202 | return 0; | |
a3fcb948 JG |
1203 | } |
1204 | ||
1205 | current_pc = pc + insn->len; | |
1206 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1207 | { | |
1208 | if (!i386_match_pattern (current_pc, *insn)) | |
1209 | return 0; | |
1210 | ||
1211 | current_pc += insn->len; | |
1212 | } | |
1213 | ||
1214 | return 1; | |
1215 | } | |
1216 | ||
37bdc87e MK |
1217 | /* Some special instructions that might be migrated by GCC into the |
1218 | part of the prologue that sets up the new stack frame. Because the | |
1219 | stack frame hasn't been setup yet, no registers have been saved | |
1220 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1221 | touched. */ | |
1222 | ||
1223 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1224 | { | |
1777feb0 | 1225 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1226 | |
1227 | ??? Should we handle 16-bit operand-sizes here? */ | |
1228 | ||
1229 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1230 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1231 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1232 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1233 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1234 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1235 | { 5, { 0xb8 }, { 0xfe } }, | |
1236 | /* `movl imm32, %edx' */ | |
1237 | { 5, { 0xba }, { 0xff } }, | |
1238 | ||
1239 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1240 | encoding for `mov m32, %eax'. | |
1241 | ||
1242 | ??? Should we handle SIB adressing here? | |
1243 | ??? Should we handle 16-bit operand-sizes here? */ | |
1244 | ||
1245 | /* `movl m32, %eax' */ | |
1246 | { 5, { 0xa1 }, { 0xff } }, | |
1247 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1248 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1249 | /* `movl m32, %edx' */ | |
1250 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1251 | ||
1252 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1253 | Because of the symmetry, there are actually two ways to encode | |
1254 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1255 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1256 | ||
1257 | /* `subl %eax, %eax' */ | |
1258 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1259 | /* `subl %ecx, %ecx' */ | |
1260 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1261 | /* `subl %edx, %edx' */ | |
1262 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1263 | /* `xorl %eax, %eax' */ | |
1264 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1265 | /* `xorl %ecx, %ecx' */ | |
1266 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1267 | /* `xorl %edx, %edx' */ | |
1268 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1269 | { 0 } | |
1270 | }; | |
1271 | ||
e11481da PM |
1272 | |
1273 | /* Check whether PC points to a no-op instruction. */ | |
1274 | static CORE_ADDR | |
1275 | i386_skip_noop (CORE_ADDR pc) | |
1276 | { | |
1277 | gdb_byte op; | |
1278 | int check = 1; | |
1279 | ||
3dcabaa8 MS |
1280 | if (target_read_memory (pc, &op, 1)) |
1281 | return pc; | |
e11481da PM |
1282 | |
1283 | while (check) | |
1284 | { | |
1285 | check = 0; | |
1286 | /* Ignore `nop' instruction. */ | |
1287 | if (op == 0x90) | |
1288 | { | |
1289 | pc += 1; | |
3dcabaa8 MS |
1290 | if (target_read_memory (pc, &op, 1)) |
1291 | return pc; | |
e11481da PM |
1292 | check = 1; |
1293 | } | |
1294 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1295 | Microsoft system dlls often start with | |
1296 | a `mov %edi,%edi' instruction. | |
1297 | The 5 bytes before the function start are | |
1298 | filled with `nop' instructions. | |
1299 | This pattern can be used for hot-patching: | |
1300 | The `mov %edi, %edi' instruction can be replaced by a | |
1301 | near jump to the location of the 5 `nop' instructions | |
1302 | which can be replaced by a 32-bit jump to anywhere | |
1303 | in the 32-bit address space. */ | |
1304 | ||
1305 | else if (op == 0x8b) | |
1306 | { | |
3dcabaa8 MS |
1307 | if (target_read_memory (pc + 1, &op, 1)) |
1308 | return pc; | |
1309 | ||
e11481da PM |
1310 | if (op == 0xff) |
1311 | { | |
1312 | pc += 2; | |
3dcabaa8 MS |
1313 | if (target_read_memory (pc, &op, 1)) |
1314 | return pc; | |
1315 | ||
e11481da PM |
1316 | check = 1; |
1317 | } | |
1318 | } | |
1319 | } | |
1320 | return pc; | |
1321 | } | |
1322 | ||
acd5c798 MK |
1323 | /* Check whether PC points at a code that sets up a new stack frame. |
1324 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1325 | instruction after the sequence that sets up the frame or LIMIT, |
1326 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1327 | |
1328 | static CORE_ADDR | |
e17a4113 UW |
1329 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1330 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1331 | struct i386_frame_cache *cache) |
1332 | { | |
e17a4113 | 1333 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1334 | struct i386_insn *insn; |
63c0089f | 1335 | gdb_byte op; |
26604a34 | 1336 | int skip = 0; |
acd5c798 | 1337 | |
37bdc87e MK |
1338 | if (limit <= pc) |
1339 | return limit; | |
acd5c798 | 1340 | |
3dcabaa8 MS |
1341 | if (target_read_memory (pc, &op, 1)) |
1342 | return pc; | |
acd5c798 | 1343 | |
c906108c | 1344 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1345 | { |
acd5c798 MK |
1346 | /* Take into account that we've executed the `pushl %ebp' that |
1347 | starts this instruction sequence. */ | |
fd13a04a | 1348 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1349 | cache->sp_offset += 4; |
37bdc87e | 1350 | pc++; |
acd5c798 MK |
1351 | |
1352 | /* If that's all, return now. */ | |
37bdc87e MK |
1353 | if (limit <= pc) |
1354 | return limit; | |
26604a34 | 1355 | |
b4632131 | 1356 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1357 | GCC into the prologue and skip them. At this point in the |
1358 | prologue, code should only touch the scratch registers %eax, | |
1359 | %ecx and %edx, so while the number of posibilities is sheer, | |
1360 | it is limited. | |
5daa5b4e | 1361 | |
26604a34 MK |
1362 | Make sure we only skip these instructions if we later see the |
1363 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1364 | while (pc + skip < limit) |
26604a34 | 1365 | { |
37bdc87e MK |
1366 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1367 | if (insn == NULL) | |
1368 | break; | |
b4632131 | 1369 | |
37bdc87e | 1370 | skip += insn->len; |
26604a34 MK |
1371 | } |
1372 | ||
37bdc87e MK |
1373 | /* If that's all, return now. */ |
1374 | if (limit <= pc + skip) | |
1375 | return limit; | |
1376 | ||
3dcabaa8 MS |
1377 | if (target_read_memory (pc + skip, &op, 1)) |
1378 | return pc + skip; | |
37bdc87e | 1379 | |
26604a34 | 1380 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1381 | switch (op) |
c906108c SS |
1382 | { |
1383 | case 0x8b: | |
e17a4113 UW |
1384 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1385 | != 0xec) | |
37bdc87e | 1386 | return pc; |
c906108c SS |
1387 | break; |
1388 | case 0x89: | |
e17a4113 UW |
1389 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1390 | != 0xe5) | |
37bdc87e | 1391 | return pc; |
c906108c SS |
1392 | break; |
1393 | default: | |
37bdc87e | 1394 | return pc; |
c906108c | 1395 | } |
acd5c798 | 1396 | |
26604a34 MK |
1397 | /* OK, we actually have a frame. We just don't know how large |
1398 | it is yet. Set its size to zero. We'll adjust it if | |
1399 | necessary. We also now commit to skipping the special | |
1400 | instructions mentioned before. */ | |
acd5c798 | 1401 | cache->locals = 0; |
37bdc87e | 1402 | pc += (skip + 2); |
acd5c798 MK |
1403 | |
1404 | /* If that's all, return now. */ | |
37bdc87e MK |
1405 | if (limit <= pc) |
1406 | return limit; | |
acd5c798 | 1407 | |
fc338970 MK |
1408 | /* Check for stack adjustment |
1409 | ||
acd5c798 | 1410 | subl $XXX, %esp |
fc338970 | 1411 | |
fd35795f | 1412 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1413 | reg, so we don't have to worry about a data16 prefix. */ |
3dcabaa8 MS |
1414 | if (target_read_memory (pc, &op, 1)) |
1415 | return pc; | |
c906108c SS |
1416 | if (op == 0x83) |
1417 | { | |
fd35795f | 1418 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1419 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1420 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1421 | return pc; |
acd5c798 | 1422 | |
37bdc87e MK |
1423 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1424 | make sense to be negative). */ | |
e17a4113 | 1425 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1426 | return pc + 3; |
c906108c SS |
1427 | } |
1428 | else if (op == 0x81) | |
1429 | { | |
fd35795f | 1430 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1431 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1432 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1433 | return pc; |
acd5c798 | 1434 | |
fd35795f | 1435 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1436 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1437 | return pc + 6; |
c906108c SS |
1438 | } |
1439 | else | |
1440 | { | |
acd5c798 | 1441 | /* Some instruction other than `subl'. */ |
37bdc87e | 1442 | return pc; |
c906108c SS |
1443 | } |
1444 | } | |
37bdc87e | 1445 | else if (op == 0xc8) /* enter */ |
c906108c | 1446 | { |
e17a4113 | 1447 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1448 | return pc + 4; |
c906108c | 1449 | } |
21d0e8a4 | 1450 | |
acd5c798 | 1451 | return pc; |
21d0e8a4 MK |
1452 | } |
1453 | ||
acd5c798 MK |
1454 | /* Check whether PC points at code that saves registers on the stack. |
1455 | If so, it updates CACHE and returns the address of the first | |
1456 | instruction after the register saves or CURRENT_PC, whichever is | |
1457 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1458 | |
1459 | static CORE_ADDR | |
acd5c798 MK |
1460 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1461 | struct i386_frame_cache *cache) | |
6bff26de | 1462 | { |
99ab4326 | 1463 | CORE_ADDR offset = 0; |
63c0089f | 1464 | gdb_byte op; |
99ab4326 | 1465 | int i; |
c0d1d883 | 1466 | |
99ab4326 MK |
1467 | if (cache->locals > 0) |
1468 | offset -= cache->locals; | |
1469 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1470 | { | |
3dcabaa8 MS |
1471 | if (target_read_memory (pc, &op, 1)) |
1472 | return pc; | |
99ab4326 MK |
1473 | if (op < 0x50 || op > 0x57) |
1474 | break; | |
0d17c81d | 1475 | |
99ab4326 MK |
1476 | offset -= 4; |
1477 | cache->saved_regs[op - 0x50] = offset; | |
1478 | cache->sp_offset += 4; | |
1479 | pc++; | |
6bff26de MK |
1480 | } |
1481 | ||
acd5c798 | 1482 | return pc; |
22797942 AC |
1483 | } |
1484 | ||
acd5c798 MK |
1485 | /* Do a full analysis of the prologue at PC and update CACHE |
1486 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1487 | address where the analysis stopped. | |
ed84f6c1 | 1488 | |
fc338970 MK |
1489 | We handle these cases: |
1490 | ||
1491 | The startup sequence can be at the start of the function, or the | |
1492 | function can start with a branch to startup code at the end. | |
1493 | ||
1494 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1495 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1496 | once used in the System V compiler). | |
1497 | ||
1498 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1499 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1500 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1501 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1502 | |
1503 | Next, the registers used by this function are pushed. With the | |
1504 | System V compiler they will always be in the order: %edi, %esi, | |
1505 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1506 | restore %eax); however, the code below is willing to see the pushes | |
1507 | in any order, and will handle up to 8 of them. | |
1508 | ||
1509 | If the setup sequence is at the end of the function, then the next | |
1510 | instruction will be a branch back to the start. */ | |
c906108c | 1511 | |
acd5c798 | 1512 | static CORE_ADDR |
e17a4113 UW |
1513 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1514 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1515 | struct i386_frame_cache *cache) |
c906108c | 1516 | { |
e11481da | 1517 | pc = i386_skip_noop (pc); |
e17a4113 | 1518 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1519 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1520 | pc = i386_skip_probe (pc); | |
92dd43fa | 1521 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1522 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1523 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1524 | } |
1525 | ||
fc338970 | 1526 | /* Return PC of first real instruction. */ |
c906108c | 1527 | |
3a1e71e3 | 1528 | static CORE_ADDR |
6093d2eb | 1529 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1530 | { |
e17a4113 UW |
1531 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1532 | ||
63c0089f | 1533 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1534 | { |
1535 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1536 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1537 | }; |
acd5c798 MK |
1538 | struct i386_frame_cache cache; |
1539 | CORE_ADDR pc; | |
63c0089f | 1540 | gdb_byte op; |
acd5c798 | 1541 | int i; |
c5aa993b | 1542 | |
acd5c798 | 1543 | cache.locals = -1; |
e17a4113 | 1544 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1545 | if (cache.locals < 0) |
1546 | return start_pc; | |
c5aa993b | 1547 | |
acd5c798 | 1548 | /* Found valid frame setup. */ |
c906108c | 1549 | |
fc338970 MK |
1550 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1551 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1552 | %ebx: |
1553 | ||
fc338970 MK |
1554 | call 0x0 |
1555 | popl %ebx | |
1556 | movl %ebx,x(%ebp) (optional) | |
1557 | addl y,%ebx | |
1558 | ||
c906108c SS |
1559 | This code is with the rest of the prologue (at the end of the |
1560 | function), so we have to skip it to get to the first real | |
1561 | instruction at the start of the function. */ | |
c5aa993b | 1562 | |
c906108c SS |
1563 | for (i = 0; i < 6; i++) |
1564 | { | |
3dcabaa8 MS |
1565 | if (target_read_memory (pc + i, &op, 1)) |
1566 | return pc; | |
1567 | ||
c5aa993b | 1568 | if (pic_pat[i] != op) |
c906108c SS |
1569 | break; |
1570 | } | |
1571 | if (i == 6) | |
1572 | { | |
acd5c798 MK |
1573 | int delta = 6; |
1574 | ||
3dcabaa8 MS |
1575 | if (target_read_memory (pc + delta, &op, 1)) |
1576 | return pc; | |
c906108c | 1577 | |
c5aa993b | 1578 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1579 | { |
e17a4113 | 1580 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1581 | |
fc338970 | 1582 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1583 | delta += 3; |
fc338970 | 1584 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1585 | delta += 6; |
fc338970 | 1586 | else /* Unexpected instruction. */ |
acd5c798 MK |
1587 | delta = 0; |
1588 | ||
3dcabaa8 MS |
1589 | if (target_read_memory (pc + delta, &op, 1)) |
1590 | return pc; | |
c906108c | 1591 | } |
acd5c798 | 1592 | |
c5aa993b | 1593 | /* addl y,%ebx */ |
acd5c798 | 1594 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1595 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1596 | == 0xc3) | |
c906108c | 1597 | { |
acd5c798 | 1598 | pc += delta + 6; |
c906108c SS |
1599 | } |
1600 | } | |
c5aa993b | 1601 | |
e63bbc88 MK |
1602 | /* If the function starts with a branch (to startup code at the end) |
1603 | the last instruction should bring us back to the first | |
1604 | instruction of the real code. */ | |
e17a4113 UW |
1605 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1606 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1607 | |
1608 | return pc; | |
c906108c SS |
1609 | } |
1610 | ||
4309257c PM |
1611 | /* Check that the code pointed to by PC corresponds to a call to |
1612 | __main, skip it if so. Return PC otherwise. */ | |
1613 | ||
1614 | CORE_ADDR | |
1615 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1616 | { | |
e17a4113 | 1617 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1618 | gdb_byte op; |
1619 | ||
3dcabaa8 MS |
1620 | if (target_read_memory (pc, &op, 1)) |
1621 | return pc; | |
4309257c PM |
1622 | if (op == 0xe8) |
1623 | { | |
1624 | gdb_byte buf[4]; | |
1625 | ||
1626 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1627 | { | |
1628 | /* Make sure address is computed correctly as a 32bit | |
1629 | integer even if CORE_ADDR is 64 bit wide. */ | |
1630 | struct minimal_symbol *s; | |
e17a4113 | 1631 | CORE_ADDR call_dest; |
4309257c | 1632 | |
e17a4113 | 1633 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1634 | call_dest = call_dest & 0xffffffffU; |
1635 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1636 | if (s != NULL | |
1637 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1638 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1639 | pc += 5; | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | return pc; | |
1644 | } | |
1645 | ||
acd5c798 | 1646 | /* This function is 64-bit safe. */ |
93924b6b | 1647 | |
acd5c798 MK |
1648 | static CORE_ADDR |
1649 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1650 | { |
63c0089f | 1651 | gdb_byte buf[8]; |
acd5c798 | 1652 | |
875f8d0e | 1653 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1654 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1655 | } |
acd5c798 | 1656 | \f |
93924b6b | 1657 | |
acd5c798 | 1658 | /* Normal frames. */ |
c5aa993b | 1659 | |
8fbca658 PA |
1660 | static void |
1661 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1662 | struct i386_frame_cache *cache) | |
a7769679 | 1663 | { |
e17a4113 UW |
1664 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1665 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1666 | gdb_byte buf[4]; |
acd5c798 MK |
1667 | int i; |
1668 | ||
8fbca658 | 1669 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1670 | |
1671 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1672 | which holds the base address for the current stack frame. | |
1673 | However, for functions that don't need it, the frame pointer is | |
1674 | optional. For these "frameless" functions the frame pointer is | |
1675 | actually the frame pointer of the calling frame. Signal | |
1676 | trampolines are just a special case of a "frameless" function. | |
1677 | They (usually) share their frame pointer with the frame that was | |
1678 | in progress when the signal occurred. */ | |
1679 | ||
10458914 | 1680 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1681 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1682 | if (cache->base == 0) |
8fbca658 | 1683 | return; |
acd5c798 MK |
1684 | |
1685 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1686 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1687 | |
acd5c798 | 1688 | if (cache->pc != 0) |
e17a4113 UW |
1689 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1690 | cache); | |
acd5c798 MK |
1691 | |
1692 | if (cache->locals < 0) | |
1693 | { | |
1694 | /* We didn't find a valid frame, which means that CACHE->base | |
1695 | currently holds the frame pointer for our calling frame. If | |
1696 | we're at the start of a function, or somewhere half-way its | |
1697 | prologue, the function's frame probably hasn't been fully | |
1698 | setup yet. Try to reconstruct the base address for the stack | |
1699 | frame by looking at the stack pointer. For truly "frameless" | |
1700 | functions this might work too. */ | |
1701 | ||
e0c62198 | 1702 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1703 | { |
8fbca658 PA |
1704 | /* Saved stack pointer has been saved. */ |
1705 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
1706 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1707 | ||
92dd43fa MK |
1708 | /* We're halfway aligning the stack. */ |
1709 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1710 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1711 | ||
1712 | /* This will be added back below. */ | |
1713 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1714 | } | |
7618e12b DJ |
1715 | else if (cache->pc != 0 |
1716 | || target_read_memory (get_frame_pc (this_frame), buf, 1)) | |
92dd43fa | 1717 | { |
7618e12b DJ |
1718 | /* We're in a known function, but did not find a frame |
1719 | setup. Assume that the function does not use %ebp. | |
1720 | Alternatively, we may have jumped to an invalid | |
1721 | address; in that case there is definitely no new | |
1722 | frame in %ebp. */ | |
10458914 | 1723 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1724 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1725 | + cache->sp_offset; | |
92dd43fa | 1726 | } |
7618e12b DJ |
1727 | else |
1728 | /* We're in an unknown function. We could not find the start | |
1729 | of the function to analyze the prologue; our best option is | |
1730 | to assume a typical frame layout with the caller's %ebp | |
1731 | saved. */ | |
1732 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
1733 | } |
1734 | ||
8fbca658 PA |
1735 | if (cache->saved_sp_reg != -1) |
1736 | { | |
1737 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
1738 | register may be unavailable). */ | |
1739 | if (cache->saved_sp == 0 | |
1740 | && frame_register_read (this_frame, cache->saved_sp_reg, buf)) | |
1741 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
1742 | } | |
acd5c798 MK |
1743 | /* Now that we have the base address for the stack frame we can |
1744 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 1745 | else if (cache->saved_sp == 0) |
92dd43fa | 1746 | cache->saved_sp = cache->base + 8; |
a7769679 | 1747 | |
acd5c798 MK |
1748 | /* Adjust all the saved registers such that they contain addresses |
1749 | instead of offsets. */ | |
1750 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1751 | if (cache->saved_regs[i] != -1) |
1752 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 1753 | |
8fbca658 PA |
1754 | cache->base_p = 1; |
1755 | } | |
1756 | ||
1757 | static struct i386_frame_cache * | |
1758 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1759 | { | |
1760 | volatile struct gdb_exception ex; | |
1761 | struct i386_frame_cache *cache; | |
1762 | ||
1763 | if (*this_cache) | |
1764 | return *this_cache; | |
1765 | ||
1766 | cache = i386_alloc_frame_cache (); | |
1767 | *this_cache = cache; | |
1768 | ||
1769 | TRY_CATCH (ex, RETURN_MASK_ERROR) | |
1770 | { | |
1771 | i386_frame_cache_1 (this_frame, cache); | |
1772 | } | |
1773 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1774 | throw_exception (ex); | |
1775 | ||
acd5c798 | 1776 | return cache; |
a7769679 MK |
1777 | } |
1778 | ||
3a1e71e3 | 1779 | static void |
10458914 | 1780 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1781 | struct frame_id *this_id) |
c906108c | 1782 | { |
10458914 | 1783 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1784 | |
1785 | /* This marks the outermost frame. */ | |
1786 | if (cache->base == 0) | |
1787 | return; | |
1788 | ||
3e210248 | 1789 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1790 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1791 | } | |
1792 | ||
8fbca658 PA |
1793 | static enum unwind_stop_reason |
1794 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1795 | void **this_cache) | |
1796 | { | |
1797 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
1798 | ||
1799 | if (!cache->base_p) | |
1800 | return UNWIND_UNAVAILABLE; | |
1801 | ||
1802 | /* This marks the outermost frame. */ | |
1803 | if (cache->base == 0) | |
1804 | return UNWIND_OUTERMOST; | |
1805 | ||
1806 | return UNWIND_NO_REASON; | |
1807 | } | |
1808 | ||
10458914 DJ |
1809 | static struct value * |
1810 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1811 | int regnum) | |
acd5c798 | 1812 | { |
10458914 | 1813 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1814 | |
1815 | gdb_assert (regnum >= 0); | |
1816 | ||
1817 | /* The System V ABI says that: | |
1818 | ||
1819 | "The flags register contains the system flags, such as the | |
1820 | direction flag and the carry flag. The direction flag must be | |
1821 | set to the forward (that is, zero) direction before entry and | |
1822 | upon exit from a function. Other user flags have no specified | |
1823 | role in the standard calling sequence and are not preserved." | |
1824 | ||
1825 | To guarantee the "upon exit" part of that statement we fake a | |
1826 | saved flags register that has its direction flag cleared. | |
1827 | ||
1828 | Note that GCC doesn't seem to rely on the fact that the direction | |
1829 | flag is cleared after a function return; it always explicitly | |
1830 | clears the flag before operations where it matters. | |
1831 | ||
1832 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1833 | right thing to do. The way we fake the flags register here makes | |
1834 | it impossible to change it. */ | |
1835 | ||
1836 | if (regnum == I386_EFLAGS_REGNUM) | |
1837 | { | |
10458914 | 1838 | ULONGEST val; |
c5aa993b | 1839 | |
10458914 DJ |
1840 | val = get_frame_register_unsigned (this_frame, regnum); |
1841 | val &= ~(1 << 10); | |
1842 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1843 | } |
1211c4e4 | 1844 | |
acd5c798 | 1845 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1846 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 1847 | |
fcf250e2 UW |
1848 | if (regnum == I386_ESP_REGNUM |
1849 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
1850 | { |
1851 | /* If the SP has been saved, but we don't know where, then this | |
1852 | means that SAVED_SP_REG register was found unavailable back | |
1853 | when we built the cache. */ | |
fcf250e2 | 1854 | if (cache->saved_sp == 0) |
8fbca658 PA |
1855 | return frame_unwind_got_register (this_frame, regnum, |
1856 | cache->saved_sp_reg); | |
1857 | else | |
1858 | return frame_unwind_got_constant (this_frame, regnum, | |
1859 | cache->saved_sp); | |
1860 | } | |
acd5c798 | 1861 | |
fd13a04a | 1862 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1863 | return frame_unwind_got_memory (this_frame, regnum, |
1864 | cache->saved_regs[regnum]); | |
fd13a04a | 1865 | |
10458914 | 1866 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1867 | } |
1868 | ||
1869 | static const struct frame_unwind i386_frame_unwind = | |
1870 | { | |
1871 | NORMAL_FRAME, | |
8fbca658 | 1872 | i386_frame_unwind_stop_reason, |
acd5c798 | 1873 | i386_frame_this_id, |
10458914 DJ |
1874 | i386_frame_prev_register, |
1875 | NULL, | |
1876 | default_frame_sniffer | |
acd5c798 | 1877 | }; |
06da04c6 MS |
1878 | |
1879 | /* Normal frames, but in a function epilogue. */ | |
1880 | ||
1881 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1882 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1883 | the function's stack frame. */ | |
1884 | ||
1885 | static int | |
1886 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1887 | { | |
1888 | gdb_byte insn; | |
e0d00bc7 JK |
1889 | struct symtab *symtab; |
1890 | ||
1891 | symtab = find_pc_symtab (pc); | |
1892 | if (symtab && symtab->epilogue_unwind_valid) | |
1893 | return 0; | |
06da04c6 MS |
1894 | |
1895 | if (target_read_memory (pc, &insn, 1)) | |
1896 | return 0; /* Can't read memory at pc. */ | |
1897 | ||
1898 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1899 | return 0; | |
1900 | ||
1901 | return 1; | |
1902 | } | |
1903 | ||
1904 | static int | |
1905 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1906 | struct frame_info *this_frame, | |
1907 | void **this_prologue_cache) | |
1908 | { | |
1909 | if (frame_relative_level (this_frame) == 0) | |
1910 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1911 | get_frame_pc (this_frame)); | |
1912 | else | |
1913 | return 0; | |
1914 | } | |
1915 | ||
1916 | static struct i386_frame_cache * | |
1917 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1918 | { | |
8fbca658 | 1919 | volatile struct gdb_exception ex; |
06da04c6 | 1920 | struct i386_frame_cache *cache; |
0d6c2135 | 1921 | CORE_ADDR sp; |
06da04c6 MS |
1922 | |
1923 | if (*this_cache) | |
1924 | return *this_cache; | |
1925 | ||
1926 | cache = i386_alloc_frame_cache (); | |
1927 | *this_cache = cache; | |
1928 | ||
8fbca658 PA |
1929 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
1930 | { | |
0d6c2135 | 1931 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 1932 | |
0d6c2135 MK |
1933 | /* At this point the stack looks as if we just entered the |
1934 | function, with the return address at the top of the | |
1935 | stack. */ | |
1936 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
1937 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 1938 | cache->saved_sp = cache->base + 8; |
8fbca658 | 1939 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 1940 | |
8fbca658 PA |
1941 | cache->base_p = 1; |
1942 | } | |
1943 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) | |
1944 | throw_exception (ex); | |
06da04c6 MS |
1945 | |
1946 | return cache; | |
1947 | } | |
1948 | ||
8fbca658 PA |
1949 | static enum unwind_stop_reason |
1950 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1951 | void **this_cache) | |
1952 | { | |
0d6c2135 MK |
1953 | struct i386_frame_cache *cache = |
1954 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
1955 | |
1956 | if (!cache->base_p) | |
1957 | return UNWIND_UNAVAILABLE; | |
1958 | ||
1959 | return UNWIND_NO_REASON; | |
1960 | } | |
1961 | ||
06da04c6 MS |
1962 | static void |
1963 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1964 | void **this_cache, | |
1965 | struct frame_id *this_id) | |
1966 | { | |
0d6c2135 MK |
1967 | struct i386_frame_cache *cache = |
1968 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 1969 | |
8fbca658 PA |
1970 | if (!cache->base_p) |
1971 | return; | |
1972 | ||
06da04c6 MS |
1973 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1974 | } | |
1975 | ||
0d6c2135 MK |
1976 | static struct value * |
1977 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
1978 | void **this_cache, int regnum) | |
1979 | { | |
1980 | /* Make sure we've initialized the cache. */ | |
1981 | i386_epilogue_frame_cache (this_frame, this_cache); | |
1982 | ||
1983 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
1984 | } | |
1985 | ||
06da04c6 MS |
1986 | static const struct frame_unwind i386_epilogue_frame_unwind = |
1987 | { | |
1988 | NORMAL_FRAME, | |
8fbca658 | 1989 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 1990 | i386_epilogue_frame_this_id, |
0d6c2135 | 1991 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
1992 | NULL, |
1993 | i386_epilogue_frame_sniffer | |
1994 | }; | |
acd5c798 MK |
1995 | \f |
1996 | ||
a3fcb948 JG |
1997 | /* Stack-based trampolines. */ |
1998 | ||
1999 | /* These trampolines are used on cross x86 targets, when taking the | |
2000 | address of a nested function. When executing these trampolines, | |
2001 | no stack frame is set up, so we are in a similar situation as in | |
2002 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2003 | ||
2004 | /* Static chain passed in register. */ | |
2005 | ||
2006 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2007 | { | |
2008 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2009 | { 5, { 0xb8 }, { 0xfe } }, | |
2010 | ||
2011 | /* `jmp imm32' */ | |
2012 | { 5, { 0xe9 }, { 0xff } }, | |
2013 | ||
2014 | {0} | |
2015 | }; | |
2016 | ||
2017 | /* Static chain passed on stack (when regparm=3). */ | |
2018 | ||
2019 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2020 | { | |
2021 | /* `push imm32' */ | |
2022 | { 5, { 0x68 }, { 0xff } }, | |
2023 | ||
2024 | /* `jmp imm32' */ | |
2025 | { 5, { 0xe9 }, { 0xff } }, | |
2026 | ||
2027 | {0} | |
2028 | }; | |
2029 | ||
2030 | /* Return whether PC points inside a stack trampoline. */ | |
2031 | ||
2032 | static int | |
2033 | i386_in_stack_tramp_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2034 | { | |
2035 | gdb_byte insn; | |
2036 | char *name; | |
2037 | ||
2038 | /* A stack trampoline is detected if no name is associated | |
2039 | to the current pc and if it points inside a trampoline | |
2040 | sequence. */ | |
2041 | ||
2042 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2043 | if (name) | |
2044 | return 0; | |
2045 | ||
2046 | if (target_read_memory (pc, &insn, 1)) | |
2047 | return 0; | |
2048 | ||
2049 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2050 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2051 | return 0; | |
2052 | ||
2053 | return 1; | |
2054 | } | |
2055 | ||
2056 | static int | |
2057 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2058 | struct frame_info *this_frame, |
2059 | void **this_cache) | |
a3fcb948 JG |
2060 | { |
2061 | if (frame_relative_level (this_frame) == 0) | |
2062 | return i386_in_stack_tramp_p (get_frame_arch (this_frame), | |
2063 | get_frame_pc (this_frame)); | |
2064 | else | |
2065 | return 0; | |
2066 | } | |
2067 | ||
2068 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2069 | { | |
2070 | NORMAL_FRAME, | |
2071 | i386_epilogue_frame_unwind_stop_reason, | |
2072 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2073 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2074 | NULL, |
2075 | i386_stack_tramp_frame_sniffer | |
2076 | }; | |
2077 | \f | |
6710bf39 SS |
2078 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2079 | ||
2080 | static void | |
2081 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2082 | struct agent_expr *ax, struct axs_value *value, | |
2083 | CORE_ADDR scope) | |
2084 | { | |
2085 | /* The following sequence assumes the traditional use of the base | |
2086 | register. */ | |
2087 | ax_reg (ax, I386_EBP_REGNUM); | |
2088 | ax_const_l (ax, 4); | |
2089 | ax_simple (ax, aop_add); | |
2090 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2091 | value->kind = axs_lvalue_memory; | |
2092 | } | |
2093 | \f | |
a3fcb948 | 2094 | |
acd5c798 MK |
2095 | /* Signal trampolines. */ |
2096 | ||
2097 | static struct i386_frame_cache * | |
10458914 | 2098 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2099 | { |
e17a4113 UW |
2100 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2102 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8fbca658 | 2103 | volatile struct gdb_exception ex; |
acd5c798 | 2104 | struct i386_frame_cache *cache; |
acd5c798 | 2105 | CORE_ADDR addr; |
63c0089f | 2106 | gdb_byte buf[4]; |
acd5c798 MK |
2107 | |
2108 | if (*this_cache) | |
2109 | return *this_cache; | |
2110 | ||
fd13a04a | 2111 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2112 | |
8fbca658 | 2113 | TRY_CATCH (ex, RETURN_MASK_ERROR) |
a3386186 | 2114 | { |
8fbca658 PA |
2115 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2116 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2117 | |
8fbca658 PA |
2118 | addr = tdep->sigcontext_addr (this_frame); |
2119 | if (tdep->sc_reg_offset) | |
2120 | { | |
2121 | int i; | |
a3386186 | 2122 | |
8fbca658 PA |
2123 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2124 | ||
2125 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2126 | if (tdep->sc_reg_offset[i] != -1) | |
2127 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2128 | } | |
2129 | else | |
2130 | { | |
2131 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2132 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2133 | } | |
2134 | ||
2135 | cache->base_p = 1; | |
a3386186 | 2136 | } |
8fbca658 PA |
2137 | if (ex.reason < 0 && ex.error != NOT_AVAILABLE_ERROR) |
2138 | throw_exception (ex); | |
acd5c798 MK |
2139 | |
2140 | *this_cache = cache; | |
2141 | return cache; | |
2142 | } | |
2143 | ||
8fbca658 PA |
2144 | static enum unwind_stop_reason |
2145 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2146 | void **this_cache) | |
2147 | { | |
2148 | struct i386_frame_cache *cache = | |
2149 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2150 | ||
2151 | if (!cache->base_p) | |
2152 | return UNWIND_UNAVAILABLE; | |
2153 | ||
2154 | return UNWIND_NO_REASON; | |
2155 | } | |
2156 | ||
acd5c798 | 2157 | static void |
10458914 | 2158 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2159 | struct frame_id *this_id) |
2160 | { | |
2161 | struct i386_frame_cache *cache = | |
10458914 | 2162 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2163 | |
8fbca658 PA |
2164 | if (!cache->base_p) |
2165 | return; | |
2166 | ||
3e210248 | 2167 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2168 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
2169 | } |
2170 | ||
10458914 DJ |
2171 | static struct value * |
2172 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2173 | void **this_cache, int regnum) | |
acd5c798 MK |
2174 | { |
2175 | /* Make sure we've initialized the cache. */ | |
10458914 | 2176 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2177 | |
10458914 | 2178 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2179 | } |
c0d1d883 | 2180 | |
10458914 DJ |
2181 | static int |
2182 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2183 | struct frame_info *this_frame, | |
2184 | void **this_prologue_cache) | |
acd5c798 | 2185 | { |
10458914 | 2186 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2187 | |
911bc6ee MK |
2188 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2189 | handler. */ | |
2190 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2191 | return 0; |
1c3545ae | 2192 | |
911bc6ee MK |
2193 | if (tdep->sigtramp_p != NULL) |
2194 | { | |
10458914 DJ |
2195 | if (tdep->sigtramp_p (this_frame)) |
2196 | return 1; | |
911bc6ee MK |
2197 | } |
2198 | ||
2199 | if (tdep->sigtramp_start != 0) | |
2200 | { | |
10458914 | 2201 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2202 | |
2203 | gdb_assert (tdep->sigtramp_end != 0); | |
2204 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2205 | return 1; |
911bc6ee | 2206 | } |
acd5c798 | 2207 | |
10458914 | 2208 | return 0; |
acd5c798 | 2209 | } |
10458914 DJ |
2210 | |
2211 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2212 | { | |
2213 | SIGTRAMP_FRAME, | |
8fbca658 | 2214 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2215 | i386_sigtramp_frame_this_id, |
2216 | i386_sigtramp_frame_prev_register, | |
2217 | NULL, | |
2218 | i386_sigtramp_frame_sniffer | |
2219 | }; | |
acd5c798 MK |
2220 | \f |
2221 | ||
2222 | static CORE_ADDR | |
10458914 | 2223 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2224 | { |
10458914 | 2225 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2226 | |
2227 | return cache->base; | |
2228 | } | |
2229 | ||
2230 | static const struct frame_base i386_frame_base = | |
2231 | { | |
2232 | &i386_frame_unwind, | |
2233 | i386_frame_base_address, | |
2234 | i386_frame_base_address, | |
2235 | i386_frame_base_address | |
2236 | }; | |
2237 | ||
acd5c798 | 2238 | static struct frame_id |
10458914 | 2239 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2240 | { |
acd5c798 MK |
2241 | CORE_ADDR fp; |
2242 | ||
10458914 | 2243 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2244 | |
3e210248 | 2245 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2246 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2247 | } |
e04e5beb JM |
2248 | |
2249 | /* _Decimal128 function return values need 16-byte alignment on the | |
2250 | stack. */ | |
2251 | ||
2252 | static CORE_ADDR | |
2253 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2254 | { | |
2255 | return sp & -(CORE_ADDR)16; | |
2256 | } | |
fc338970 | 2257 | \f |
c906108c | 2258 | |
fc338970 MK |
2259 | /* Figure out where the longjmp will land. Slurp the args out of the |
2260 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2261 | structure from which we extract the address that we will land at. |
28bcfd30 | 2262 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2263 | success. */ |
c906108c | 2264 | |
8201327c | 2265 | static int |
60ade65d | 2266 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2267 | { |
436675d3 | 2268 | gdb_byte buf[4]; |
c906108c | 2269 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2270 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2271 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2272 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2273 | |
8201327c MK |
2274 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2275 | longjmp will land. */ | |
2276 | if (jb_pc_offset == -1) | |
c906108c SS |
2277 | return 0; |
2278 | ||
436675d3 | 2279 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2280 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2281 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2282 | return 0; |
2283 | ||
e17a4113 | 2284 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2285 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2286 | return 0; |
c906108c | 2287 | |
e17a4113 | 2288 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2289 | return 1; |
2290 | } | |
fc338970 | 2291 | \f |
c906108c | 2292 | |
7ccc1c74 JM |
2293 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2294 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2295 | unions containing such types must be 16-byte-aligned; other | |
2296 | arguments are 4-byte-aligned. */ | |
2297 | ||
2298 | static int | |
2299 | i386_16_byte_align_p (struct type *type) | |
2300 | { | |
2301 | type = check_typedef (type); | |
2302 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2303 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2304 | && TYPE_LENGTH (type) == 16) | |
2305 | return 1; | |
2306 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2307 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2308 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2309 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2310 | { | |
2311 | int i; | |
2312 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2313 | { | |
2314 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2315 | return 1; | |
2316 | } | |
2317 | } | |
2318 | return 0; | |
2319 | } | |
2320 | ||
3a1e71e3 | 2321 | static CORE_ADDR |
7d9b040b | 2322 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2323 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2324 | struct value **args, CORE_ADDR sp, int struct_return, | |
2325 | CORE_ADDR struct_addr) | |
22f8ba57 | 2326 | { |
e17a4113 | 2327 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2328 | gdb_byte buf[4]; |
acd5c798 | 2329 | int i; |
7ccc1c74 JM |
2330 | int write_pass; |
2331 | int args_space = 0; | |
acd5c798 | 2332 | |
7ccc1c74 JM |
2333 | /* Determine the total space required for arguments and struct |
2334 | return address in a first pass (allowing for 16-byte-aligned | |
2335 | arguments), then push arguments in a second pass. */ | |
2336 | ||
2337 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2338 | { |
7ccc1c74 JM |
2339 | int args_space_used = 0; |
2340 | int have_16_byte_aligned_arg = 0; | |
2341 | ||
2342 | if (struct_return) | |
2343 | { | |
2344 | if (write_pass) | |
2345 | { | |
2346 | /* Push value address. */ | |
e17a4113 | 2347 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2348 | write_memory (sp, buf, 4); |
2349 | args_space_used += 4; | |
2350 | } | |
2351 | else | |
2352 | args_space += 4; | |
2353 | } | |
2354 | ||
2355 | for (i = 0; i < nargs; i++) | |
2356 | { | |
2357 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2358 | |
7ccc1c74 JM |
2359 | if (write_pass) |
2360 | { | |
2361 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2362 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2363 | |
7ccc1c74 JM |
2364 | write_memory (sp + args_space_used, |
2365 | value_contents_all (args[i]), len); | |
2366 | /* The System V ABI says that: | |
acd5c798 | 2367 | |
7ccc1c74 JM |
2368 | "An argument's size is increased, if necessary, to make it a |
2369 | multiple of [32-bit] words. This may require tail padding, | |
2370 | depending on the size of the argument." | |
22f8ba57 | 2371 | |
7ccc1c74 JM |
2372 | This makes sure the stack stays word-aligned. */ |
2373 | args_space_used += align_up (len, 4); | |
2374 | } | |
2375 | else | |
2376 | { | |
2377 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2378 | { | |
2379 | args_space = align_up (args_space, 16); | |
2380 | have_16_byte_aligned_arg = 1; | |
2381 | } | |
2382 | args_space += align_up (len, 4); | |
2383 | } | |
2384 | } | |
2385 | ||
2386 | if (!write_pass) | |
2387 | { | |
2388 | if (have_16_byte_aligned_arg) | |
2389 | args_space = align_up (args_space, 16); | |
2390 | sp -= args_space; | |
2391 | } | |
22f8ba57 MK |
2392 | } |
2393 | ||
acd5c798 MK |
2394 | /* Store return address. */ |
2395 | sp -= 4; | |
e17a4113 | 2396 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2397 | write_memory (sp, buf, 4); |
2398 | ||
2399 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2400 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2401 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2402 | ||
2403 | /* ...and fake a frame pointer. */ | |
2404 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2405 | ||
3e210248 AC |
2406 | /* MarkK wrote: This "+ 8" is all over the place: |
2407 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2408 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2409 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2410 | definition of the stack address of a frame. Otherwise frame id |
2411 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2412 | stack address *before* the function call as a frame's CFA. On |
2413 | the i386, when %ebp is used as a frame pointer, the offset | |
2414 | between the contents %ebp and the CFA as defined by GCC. */ | |
2415 | return sp + 8; | |
22f8ba57 MK |
2416 | } |
2417 | ||
1a309862 MK |
2418 | /* These registers are used for returning integers (and on some |
2419 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2420 | size and alignment match an integer type). */ |
acd5c798 MK |
2421 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2422 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2423 | |
c5e656c1 MK |
2424 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2425 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2426 | |
3a1e71e3 | 2427 | static void |
c5e656c1 | 2428 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2429 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2430 | { |
c5e656c1 | 2431 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2432 | int len = TYPE_LENGTH (type); |
63c0089f | 2433 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2434 | |
1e8d0a7b | 2435 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2436 | { |
5716833c | 2437 | if (tdep->st0_regnum < 0) |
1a309862 | 2438 | { |
8a3fe4f8 | 2439 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2440 | memset (valbuf, 0, len); |
ef9dff19 | 2441 | return; |
1a309862 MK |
2442 | } |
2443 | ||
c6ba6f0d MK |
2444 | /* Floating-point return values can be found in %st(0). Convert |
2445 | its contents to the desired type. This is probably not | |
2446 | exactly how it would happen on the target itself, but it is | |
2447 | the best we can do. */ | |
acd5c798 | 2448 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2449 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2450 | } |
2451 | else | |
c5aa993b | 2452 | { |
875f8d0e UW |
2453 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2454 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2455 | |
2456 | if (len <= low_size) | |
00f8375e | 2457 | { |
0818c12a | 2458 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2459 | memcpy (valbuf, buf, len); |
2460 | } | |
d4f3574e SS |
2461 | else if (len <= (low_size + high_size)) |
2462 | { | |
0818c12a | 2463 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2464 | memcpy (valbuf, buf, low_size); |
0818c12a | 2465 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2466 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2467 | } |
2468 | else | |
8e65ff28 | 2469 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2470 | _("Cannot extract return value of %d bytes long."), |
2471 | len); | |
c906108c SS |
2472 | } |
2473 | } | |
2474 | ||
c5e656c1 MK |
2475 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2476 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2477 | |
3a1e71e3 | 2478 | static void |
c5e656c1 | 2479 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2480 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2481 | { |
c5e656c1 | 2482 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2483 | int len = TYPE_LENGTH (type); |
2484 | ||
1e8d0a7b | 2485 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2486 | { |
3d7f4f49 | 2487 | ULONGEST fstat; |
63c0089f | 2488 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2489 | |
5716833c | 2490 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2491 | { |
8a3fe4f8 | 2492 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2493 | return; |
2494 | } | |
2495 | ||
635b0cc1 MK |
2496 | /* Returning floating-point values is a bit tricky. Apart from |
2497 | storing the return value in %st(0), we have to simulate the | |
2498 | state of the FPU at function return point. */ | |
2499 | ||
c6ba6f0d MK |
2500 | /* Convert the value found in VALBUF to the extended |
2501 | floating-point format used by the FPU. This is probably | |
2502 | not exactly how it would happen on the target itself, but | |
2503 | it is the best we can do. */ | |
27067745 | 2504 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2505 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2506 | |
635b0cc1 MK |
2507 | /* Set the top of the floating-point register stack to 7. The |
2508 | actual value doesn't really matter, but 7 is what a normal | |
2509 | function return would end up with if the program started out | |
2510 | with a freshly initialized FPU. */ | |
20a6ec49 | 2511 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2512 | fstat |= (7 << 11); |
20a6ec49 | 2513 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2514 | |
635b0cc1 MK |
2515 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2516 | the floating-point register stack to 7, the appropriate value | |
2517 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2518 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2519 | } |
2520 | else | |
2521 | { | |
875f8d0e UW |
2522 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2523 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2524 | |
2525 | if (len <= low_size) | |
3d7f4f49 | 2526 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2527 | else if (len <= (low_size + high_size)) |
2528 | { | |
3d7f4f49 MK |
2529 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2530 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2531 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2532 | } |
2533 | else | |
8e65ff28 | 2534 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2535 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2536 | } |
2537 | } | |
fc338970 | 2538 | \f |
ef9dff19 | 2539 | |
8201327c MK |
2540 | /* This is the variable that is set with "set struct-convention", and |
2541 | its legitimate values. */ | |
2542 | static const char default_struct_convention[] = "default"; | |
2543 | static const char pcc_struct_convention[] = "pcc"; | |
2544 | static const char reg_struct_convention[] = "reg"; | |
2545 | static const char *valid_conventions[] = | |
2546 | { | |
2547 | default_struct_convention, | |
2548 | pcc_struct_convention, | |
2549 | reg_struct_convention, | |
2550 | NULL | |
2551 | }; | |
2552 | static const char *struct_convention = default_struct_convention; | |
2553 | ||
0e4377e1 JB |
2554 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2555 | a union type, or an array type, should be returned in registers | |
2556 | for architecture GDBARCH. */ | |
c5e656c1 | 2557 | |
8201327c | 2558 | static int |
c5e656c1 | 2559 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2560 | { |
c5e656c1 MK |
2561 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2562 | enum type_code code = TYPE_CODE (type); | |
2563 | int len = TYPE_LENGTH (type); | |
8201327c | 2564 | |
0e4377e1 JB |
2565 | gdb_assert (code == TYPE_CODE_STRUCT |
2566 | || code == TYPE_CODE_UNION | |
2567 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2568 | |
2569 | if (struct_convention == pcc_struct_convention | |
2570 | || (struct_convention == default_struct_convention | |
2571 | && tdep->struct_return == pcc_struct_return)) | |
2572 | return 0; | |
2573 | ||
9edde48e MK |
2574 | /* Structures consisting of a single `float', `double' or 'long |
2575 | double' member are returned in %st(0). */ | |
2576 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2577 | { | |
2578 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2579 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2580 | return (len == 4 || len == 8 || len == 12); | |
2581 | } | |
2582 | ||
c5e656c1 MK |
2583 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2584 | } | |
2585 | ||
2586 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2587 | should be returned. If it is supposed to be returned in registers, | |
2588 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2589 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2590 | from WRITEBUF into REGCACHE. */ | |
2591 | ||
2592 | static enum return_value_convention | |
c055b101 CV |
2593 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2594 | struct type *type, struct regcache *regcache, | |
2595 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2596 | { |
2597 | enum type_code code = TYPE_CODE (type); | |
2598 | ||
5daa78cc TJB |
2599 | if (((code == TYPE_CODE_STRUCT |
2600 | || code == TYPE_CODE_UNION | |
2601 | || code == TYPE_CODE_ARRAY) | |
2602 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2603 | /* 128-bit decimal float uses the struct return convention. */ | |
2604 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2605 | { |
2606 | /* The System V ABI says that: | |
2607 | ||
2608 | "A function that returns a structure or union also sets %eax | |
2609 | to the value of the original address of the caller's area | |
2610 | before it returns. Thus when the caller receives control | |
2611 | again, the address of the returned object resides in register | |
2612 | %eax and can be used to access the object." | |
2613 | ||
2614 | So the ABI guarantees that we can always find the return | |
2615 | value just after the function has returned. */ | |
2616 | ||
0e4377e1 JB |
2617 | /* Note that the ABI doesn't mention functions returning arrays, |
2618 | which is something possible in certain languages such as Ada. | |
2619 | In this case, the value is returned as if it was wrapped in | |
2620 | a record, so the convention applied to records also applies | |
2621 | to arrays. */ | |
2622 | ||
31db7b6c MK |
2623 | if (readbuf) |
2624 | { | |
2625 | ULONGEST addr; | |
2626 | ||
2627 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2628 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2629 | } | |
2630 | ||
2631 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2632 | } | |
c5e656c1 MK |
2633 | |
2634 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2635 | `float', `double' or 'long double' member. These structures are |
2636 | returned in %st(0). For these structures, we call ourselves | |
2637 | recursively, changing TYPE into the type of the first member of | |
2638 | the structure. Since that should work for all structures that | |
2639 | have only one member, we don't bother to check the member's type | |
2640 | here. */ | |
c5e656c1 MK |
2641 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2642 | { | |
2643 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2644 | return i386_return_value (gdbarch, func_type, type, regcache, |
2645 | readbuf, writebuf); | |
c5e656c1 MK |
2646 | } |
2647 | ||
2648 | if (readbuf) | |
2649 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2650 | if (writebuf) | |
2651 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2652 | |
c5e656c1 | 2653 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2654 | } |
2655 | \f | |
2656 | ||
27067745 UW |
2657 | struct type * |
2658 | i387_ext_type (struct gdbarch *gdbarch) | |
2659 | { | |
2660 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2661 | ||
2662 | if (!tdep->i387_ext_type) | |
90884b2b L |
2663 | { |
2664 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
2665 | gdb_assert (tdep->i387_ext_type != NULL); | |
2666 | } | |
27067745 UW |
2667 | |
2668 | return tdep->i387_ext_type; | |
2669 | } | |
2670 | ||
c131fcee L |
2671 | /* Construct vector type for pseudo YMM registers. We can't use |
2672 | tdesc_find_type since YMM isn't described in target description. */ | |
2673 | ||
2674 | static struct type * | |
2675 | i386_ymm_type (struct gdbarch *gdbarch) | |
2676 | { | |
2677 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2678 | ||
2679 | if (!tdep->i386_ymm_type) | |
2680 | { | |
2681 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2682 | ||
2683 | /* The type we're building is this: */ | |
2684 | #if 0 | |
2685 | union __gdb_builtin_type_vec256i | |
2686 | { | |
2687 | int128_t uint128[2]; | |
2688 | int64_t v2_int64[4]; | |
2689 | int32_t v4_int32[8]; | |
2690 | int16_t v8_int16[16]; | |
2691 | int8_t v16_int8[32]; | |
2692 | double v2_double[4]; | |
2693 | float v4_float[8]; | |
2694 | }; | |
2695 | #endif | |
2696 | ||
2697 | struct type *t; | |
2698 | ||
2699 | t = arch_composite_type (gdbarch, | |
2700 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2701 | append_composite_type_field (t, "v8_float", | |
2702 | init_vector_type (bt->builtin_float, 8)); | |
2703 | append_composite_type_field (t, "v4_double", | |
2704 | init_vector_type (bt->builtin_double, 4)); | |
2705 | append_composite_type_field (t, "v32_int8", | |
2706 | init_vector_type (bt->builtin_int8, 32)); | |
2707 | append_composite_type_field (t, "v16_int16", | |
2708 | init_vector_type (bt->builtin_int16, 16)); | |
2709 | append_composite_type_field (t, "v8_int32", | |
2710 | init_vector_type (bt->builtin_int32, 8)); | |
2711 | append_composite_type_field (t, "v4_int64", | |
2712 | init_vector_type (bt->builtin_int64, 4)); | |
2713 | append_composite_type_field (t, "v2_int128", | |
2714 | init_vector_type (bt->builtin_int128, 2)); | |
2715 | ||
2716 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 2717 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
2718 | tdep->i386_ymm_type = t; |
2719 | } | |
2720 | ||
2721 | return tdep->i386_ymm_type; | |
2722 | } | |
2723 | ||
794ac428 | 2724 | /* Construct vector type for MMX registers. */ |
90884b2b | 2725 | static struct type * |
794ac428 UW |
2726 | i386_mmx_type (struct gdbarch *gdbarch) |
2727 | { | |
2728 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2729 | ||
2730 | if (!tdep->i386_mmx_type) | |
2731 | { | |
df4df182 UW |
2732 | const struct builtin_type *bt = builtin_type (gdbarch); |
2733 | ||
794ac428 UW |
2734 | /* The type we're building is this: */ |
2735 | #if 0 | |
2736 | union __gdb_builtin_type_vec64i | |
2737 | { | |
2738 | int64_t uint64; | |
2739 | int32_t v2_int32[2]; | |
2740 | int16_t v4_int16[4]; | |
2741 | int8_t v8_int8[8]; | |
2742 | }; | |
2743 | #endif | |
2744 | ||
2745 | struct type *t; | |
2746 | ||
e9bb382b UW |
2747 | t = arch_composite_type (gdbarch, |
2748 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2749 | |
2750 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2751 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2752 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2753 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2754 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2755 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2756 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2757 | |
876cecd0 | 2758 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2759 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2760 | tdep->i386_mmx_type = t; | |
2761 | } | |
2762 | ||
2763 | return tdep->i386_mmx_type; | |
2764 | } | |
2765 | ||
d7a0d72c | 2766 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 2767 | register REGNUM. */ |
d7a0d72c | 2768 | |
3a1e71e3 | 2769 | static struct type * |
90884b2b | 2770 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2771 | { |
1ba53b71 L |
2772 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
2773 | return i386_mmx_type (gdbarch); | |
c131fcee L |
2774 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
2775 | return i386_ymm_type (gdbarch); | |
1ba53b71 L |
2776 | else |
2777 | { | |
2778 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2779 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
2780 | return bt->builtin_int8; | |
2781 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
2782 | return bt->builtin_int16; | |
2783 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
2784 | return bt->builtin_int32; | |
2785 | } | |
2786 | ||
2787 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
2788 | } |
2789 | ||
28fc6740 | 2790 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2791 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2792 | |
2793 | static int | |
c86c27af | 2794 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2795 | { |
5716833c MK |
2796 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2797 | int mmxreg, fpreg; | |
28fc6740 AC |
2798 | ULONGEST fstat; |
2799 | int tos; | |
c86c27af | 2800 | |
5716833c | 2801 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2802 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2803 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2804 | fpreg = (mmxreg + tos) % 8; |
2805 | ||
20a6ec49 | 2806 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2807 | } |
2808 | ||
3543a589 TT |
2809 | /* A helper function for us by i386_pseudo_register_read_value and |
2810 | amd64_pseudo_register_read_value. It does all the work but reads | |
2811 | the data into an already-allocated value. */ | |
2812 | ||
2813 | void | |
2814 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
2815 | struct regcache *regcache, | |
2816 | int regnum, | |
2817 | struct value *result_value) | |
28fc6740 | 2818 | { |
1ba53b71 | 2819 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 2820 | enum register_status status; |
3543a589 | 2821 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 2822 | |
5716833c | 2823 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2824 | { |
c86c27af MK |
2825 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2826 | ||
28fc6740 | 2827 | /* Extract (always little endian). */ |
05d1431c PA |
2828 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
2829 | if (status != REG_VALID) | |
3543a589 TT |
2830 | mark_value_bytes_unavailable (result_value, 0, |
2831 | TYPE_LENGTH (value_type (result_value))); | |
2832 | else | |
2833 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
2834 | } |
2835 | else | |
1ba53b71 L |
2836 | { |
2837 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2838 | ||
c131fcee L |
2839 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2840 | { | |
2841 | regnum -= tdep->ymm0_regnum; | |
2842 | ||
1777feb0 | 2843 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
2844 | status = regcache_raw_read (regcache, |
2845 | I387_XMM0_REGNUM (tdep) + regnum, | |
2846 | raw_buf); | |
2847 | if (status != REG_VALID) | |
3543a589 TT |
2848 | mark_value_bytes_unavailable (result_value, 0, 16); |
2849 | else | |
2850 | memcpy (buf, raw_buf, 16); | |
c131fcee | 2851 | /* Read upper 128bits. */ |
05d1431c PA |
2852 | status = regcache_raw_read (regcache, |
2853 | tdep->ymm0h_regnum + regnum, | |
2854 | raw_buf); | |
2855 | if (status != REG_VALID) | |
3543a589 TT |
2856 | mark_value_bytes_unavailable (result_value, 16, 32); |
2857 | else | |
2858 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee L |
2859 | } |
2860 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2861 | { |
2862 | int gpnum = regnum - tdep->ax_regnum; | |
2863 | ||
2864 | /* Extract (always little endian). */ | |
05d1431c PA |
2865 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
2866 | if (status != REG_VALID) | |
3543a589 TT |
2867 | mark_value_bytes_unavailable (result_value, 0, |
2868 | TYPE_LENGTH (value_type (result_value))); | |
2869 | else | |
2870 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
2871 | } |
2872 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2873 | { | |
2874 | /* Check byte pseudo registers last since this function will | |
2875 | be called from amd64_pseudo_register_read, which handles | |
2876 | byte pseudo registers differently. */ | |
2877 | int gpnum = regnum - tdep->al_regnum; | |
2878 | ||
2879 | /* Extract (always little endian). We read both lower and | |
2880 | upper registers. */ | |
05d1431c PA |
2881 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
2882 | if (status != REG_VALID) | |
3543a589 TT |
2883 | mark_value_bytes_unavailable (result_value, 0, |
2884 | TYPE_LENGTH (value_type (result_value))); | |
2885 | else if (gpnum >= 4) | |
1ba53b71 L |
2886 | memcpy (buf, raw_buf + 1, 1); |
2887 | else | |
2888 | memcpy (buf, raw_buf, 1); | |
2889 | } | |
2890 | else | |
2891 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2892 | } | |
3543a589 TT |
2893 | } |
2894 | ||
2895 | static struct value * | |
2896 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
2897 | struct regcache *regcache, | |
2898 | int regnum) | |
2899 | { | |
2900 | struct value *result; | |
2901 | ||
2902 | result = allocate_value (register_type (gdbarch, regnum)); | |
2903 | VALUE_LVAL (result) = lval_register; | |
2904 | VALUE_REGNUM (result) = regnum; | |
2905 | ||
2906 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 2907 | |
3543a589 | 2908 | return result; |
28fc6740 AC |
2909 | } |
2910 | ||
1ba53b71 | 2911 | void |
28fc6740 | 2912 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 2913 | int regnum, const gdb_byte *buf) |
28fc6740 | 2914 | { |
1ba53b71 L |
2915 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
2916 | ||
5716833c | 2917 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2918 | { |
c86c27af MK |
2919 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2920 | ||
28fc6740 | 2921 | /* Read ... */ |
1ba53b71 | 2922 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 2923 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 2924 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 2925 | /* ... Write. */ |
1ba53b71 | 2926 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
2927 | } |
2928 | else | |
1ba53b71 L |
2929 | { |
2930 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2931 | ||
c131fcee L |
2932 | if (i386_ymm_regnum_p (gdbarch, regnum)) |
2933 | { | |
2934 | regnum -= tdep->ymm0_regnum; | |
2935 | ||
2936 | /* ... Write lower 128bits. */ | |
2937 | regcache_raw_write (regcache, | |
2938 | I387_XMM0_REGNUM (tdep) + regnum, | |
2939 | buf); | |
2940 | /* ... Write upper 128bits. */ | |
2941 | regcache_raw_write (regcache, | |
2942 | tdep->ymm0h_regnum + regnum, | |
2943 | buf + 16); | |
2944 | } | |
2945 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
1ba53b71 L |
2946 | { |
2947 | int gpnum = regnum - tdep->ax_regnum; | |
2948 | ||
2949 | /* Read ... */ | |
2950 | regcache_raw_read (regcache, gpnum, raw_buf); | |
2951 | /* ... Modify ... (always little endian). */ | |
2952 | memcpy (raw_buf, buf, 2); | |
2953 | /* ... Write. */ | |
2954 | regcache_raw_write (regcache, gpnum, raw_buf); | |
2955 | } | |
2956 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
2957 | { | |
2958 | /* Check byte pseudo registers last since this function will | |
2959 | be called from amd64_pseudo_register_read, which handles | |
2960 | byte pseudo registers differently. */ | |
2961 | int gpnum = regnum - tdep->al_regnum; | |
2962 | ||
2963 | /* Read ... We read both lower and upper registers. */ | |
2964 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
2965 | /* ... Modify ... (always little endian). */ | |
2966 | if (gpnum >= 4) | |
2967 | memcpy (raw_buf + 1, buf, 1); | |
2968 | else | |
2969 | memcpy (raw_buf, buf, 1); | |
2970 | /* ... Write. */ | |
2971 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
2972 | } | |
2973 | else | |
2974 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
2975 | } | |
28fc6740 | 2976 | } |
ff2e87ac AC |
2977 | \f |
2978 | ||
ff2e87ac AC |
2979 | /* Return the register number of the register allocated by GCC after |
2980 | REGNUM, or -1 if there is no such register. */ | |
2981 | ||
2982 | static int | |
2983 | i386_next_regnum (int regnum) | |
2984 | { | |
2985 | /* GCC allocates the registers in the order: | |
2986 | ||
2987 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2988 | ||
2989 | Since storing a variable in %esp doesn't make any sense we return | |
2990 | -1 for %ebp and for %esp itself. */ | |
2991 | static int next_regnum[] = | |
2992 | { | |
2993 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2994 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2995 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2996 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2997 | -1, -1, /* Slots for %esp and %ebp. */ | |
2998 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2999 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3000 | }; | |
3001 | ||
de5b9bb9 | 3002 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3003 | return next_regnum[regnum]; |
28fc6740 | 3004 | |
ff2e87ac AC |
3005 | return -1; |
3006 | } | |
3007 | ||
3008 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3009 | needs any special handling. */ | |
d7a0d72c | 3010 | |
3a1e71e3 | 3011 | static int |
1777feb0 MS |
3012 | i386_convert_register_p (struct gdbarch *gdbarch, |
3013 | int regnum, struct type *type) | |
d7a0d72c | 3014 | { |
de5b9bb9 MK |
3015 | int len = TYPE_LENGTH (type); |
3016 | ||
ff2e87ac AC |
3017 | /* Values may be spread across multiple registers. Most debugging |
3018 | formats aren't expressive enough to specify the locations, so | |
3019 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3020 | have a length that is a multiple of the word size, since GCC |
3021 | doesn't seem to put any other types into registers. */ | |
3022 | if (len > 4 && len % 4 == 0) | |
3023 | { | |
3024 | int last_regnum = regnum; | |
3025 | ||
3026 | while (len > 4) | |
3027 | { | |
3028 | last_regnum = i386_next_regnum (last_regnum); | |
3029 | len -= 4; | |
3030 | } | |
3031 | ||
3032 | if (last_regnum != -1) | |
3033 | return 1; | |
3034 | } | |
ff2e87ac | 3035 | |
0abe36f5 | 3036 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3037 | } |
3038 | ||
ff2e87ac AC |
3039 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3040 | return its contents in TO. */ | |
ac27f131 | 3041 | |
8dccd430 | 3042 | static int |
ff2e87ac | 3043 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3044 | struct type *type, gdb_byte *to, |
3045 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3046 | { |
20a6ec49 | 3047 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3048 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3049 | |
20a6ec49 | 3050 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3051 | return i387_register_to_value (frame, regnum, type, to, |
3052 | optimizedp, unavailablep); | |
ff2e87ac | 3053 | |
fd35795f | 3054 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3055 | |
3056 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3057 | |
de5b9bb9 MK |
3058 | while (len > 0) |
3059 | { | |
3060 | gdb_assert (regnum != -1); | |
20a6ec49 | 3061 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3062 | |
8dccd430 PA |
3063 | if (!get_frame_register_bytes (frame, regnum, 0, |
3064 | register_size (gdbarch, regnum), | |
3065 | to, optimizedp, unavailablep)) | |
3066 | return 0; | |
3067 | ||
de5b9bb9 MK |
3068 | regnum = i386_next_regnum (regnum); |
3069 | len -= 4; | |
42835c2b | 3070 | to += 4; |
de5b9bb9 | 3071 | } |
8dccd430 PA |
3072 | |
3073 | *optimizedp = *unavailablep = 0; | |
3074 | return 1; | |
ac27f131 MK |
3075 | } |
3076 | ||
ff2e87ac AC |
3077 | /* Write the contents FROM of a value of type TYPE into register |
3078 | REGNUM in frame FRAME. */ | |
ac27f131 | 3079 | |
3a1e71e3 | 3080 | static void |
ff2e87ac | 3081 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3082 | struct type *type, const gdb_byte *from) |
ac27f131 | 3083 | { |
de5b9bb9 | 3084 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3085 | |
20a6ec49 | 3086 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3087 | { |
d532c08f MK |
3088 | i387_value_to_register (frame, regnum, type, from); |
3089 | return; | |
3090 | } | |
3d261580 | 3091 | |
fd35795f | 3092 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3093 | |
3094 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3095 | |
de5b9bb9 MK |
3096 | while (len > 0) |
3097 | { | |
3098 | gdb_assert (regnum != -1); | |
875f8d0e | 3099 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3100 | |
42835c2b | 3101 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3102 | regnum = i386_next_regnum (regnum); |
3103 | len -= 4; | |
42835c2b | 3104 | from += 4; |
de5b9bb9 | 3105 | } |
ac27f131 | 3106 | } |
ff2e87ac | 3107 | \f |
7fdafb5a MK |
3108 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3109 | in the general-purpose register set REGSET to register cache | |
3110 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3111 | |
20187ed5 | 3112 | void |
473f17b0 MK |
3113 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3114 | int regnum, const void *gregs, size_t len) | |
3115 | { | |
9ea75c57 | 3116 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 3117 | const gdb_byte *regs = gregs; |
473f17b0 MK |
3118 | int i; |
3119 | ||
3120 | gdb_assert (len == tdep->sizeof_gregset); | |
3121 | ||
3122 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3123 | { | |
3124 | if ((regnum == i || regnum == -1) | |
3125 | && tdep->gregset_reg_offset[i] != -1) | |
3126 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3127 | } | |
3128 | } | |
3129 | ||
7fdafb5a MK |
3130 | /* Collect register REGNUM from the register cache REGCACHE and store |
3131 | it in the buffer specified by GREGS and LEN as described by the | |
3132 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3133 | all registers in REGSET. */ | |
3134 | ||
3135 | void | |
3136 | i386_collect_gregset (const struct regset *regset, | |
3137 | const struct regcache *regcache, | |
3138 | int regnum, void *gregs, size_t len) | |
3139 | { | |
3140 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 3141 | gdb_byte *regs = gregs; |
7fdafb5a MK |
3142 | int i; |
3143 | ||
3144 | gdb_assert (len == tdep->sizeof_gregset); | |
3145 | ||
3146 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3147 | { | |
3148 | if ((regnum == i || regnum == -1) | |
3149 | && tdep->gregset_reg_offset[i] != -1) | |
3150 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3151 | } | |
3152 | } | |
3153 | ||
3154 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3155 | in the floating-point register set REGSET to register cache | |
3156 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3157 | |
3158 | static void | |
3159 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3160 | int regnum, const void *fpregs, size_t len) | |
3161 | { | |
9ea75c57 | 3162 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 3163 | |
66a72d25 MK |
3164 | if (len == I387_SIZEOF_FXSAVE) |
3165 | { | |
3166 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3167 | return; | |
3168 | } | |
3169 | ||
473f17b0 MK |
3170 | gdb_assert (len == tdep->sizeof_fpregset); |
3171 | i387_supply_fsave (regcache, regnum, fpregs); | |
3172 | } | |
8446b36a | 3173 | |
2f305df1 MK |
3174 | /* Collect register REGNUM from the register cache REGCACHE and store |
3175 | it in the buffer specified by FPREGS and LEN as described by the | |
3176 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3177 | all registers in REGSET. */ | |
7fdafb5a MK |
3178 | |
3179 | static void | |
3180 | i386_collect_fpregset (const struct regset *regset, | |
3181 | const struct regcache *regcache, | |
3182 | int regnum, void *fpregs, size_t len) | |
3183 | { | |
3184 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
3185 | ||
3186 | if (len == I387_SIZEOF_FXSAVE) | |
3187 | { | |
3188 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3189 | return; | |
3190 | } | |
3191 | ||
3192 | gdb_assert (len == tdep->sizeof_fpregset); | |
3193 | i387_collect_fsave (regcache, regnum, fpregs); | |
3194 | } | |
3195 | ||
c131fcee L |
3196 | /* Similar to i386_supply_fpregset, but use XSAVE extended state. */ |
3197 | ||
3198 | static void | |
3199 | i386_supply_xstateregset (const struct regset *regset, | |
3200 | struct regcache *regcache, int regnum, | |
3201 | const void *xstateregs, size_t len) | |
3202 | { | |
c131fcee L |
3203 | i387_supply_xsave (regcache, regnum, xstateregs); |
3204 | } | |
3205 | ||
3206 | /* Similar to i386_collect_fpregset , but use XSAVE extended state. */ | |
3207 | ||
3208 | static void | |
3209 | i386_collect_xstateregset (const struct regset *regset, | |
3210 | const struct regcache *regcache, | |
3211 | int regnum, void *xstateregs, size_t len) | |
3212 | { | |
c131fcee L |
3213 | i387_collect_xsave (regcache, regnum, xstateregs, 1); |
3214 | } | |
3215 | ||
8446b36a MK |
3216 | /* Return the appropriate register set for the core section identified |
3217 | by SECT_NAME and SECT_SIZE. */ | |
3218 | ||
3219 | const struct regset * | |
3220 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
3221 | const char *sect_name, size_t sect_size) | |
3222 | { | |
3223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3224 | ||
3225 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
3226 | { | |
3227 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
3228 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
3229 | i386_collect_gregset); | |
8446b36a MK |
3230 | return tdep->gregset; |
3231 | } | |
3232 | ||
66a72d25 MK |
3233 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
3234 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
3235 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
3236 | { |
3237 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
3238 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
3239 | i386_collect_fpregset); | |
8446b36a MK |
3240 | return tdep->fpregset; |
3241 | } | |
3242 | ||
c131fcee L |
3243 | if (strcmp (sect_name, ".reg-xstate") == 0) |
3244 | { | |
3245 | if (tdep->xstateregset == NULL) | |
3246 | tdep->xstateregset = regset_alloc (gdbarch, | |
3247 | i386_supply_xstateregset, | |
3248 | i386_collect_xstateregset); | |
3249 | ||
3250 | return tdep->xstateregset; | |
3251 | } | |
3252 | ||
8446b36a MK |
3253 | return NULL; |
3254 | } | |
473f17b0 | 3255 | \f |
fc338970 | 3256 | |
fc338970 | 3257 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3258 | |
3259 | CORE_ADDR | |
e17a4113 UW |
3260 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3261 | CORE_ADDR pc, char *name) | |
c906108c | 3262 | { |
e17a4113 UW |
3263 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3264 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3265 | ||
3266 | /* jmp *(dest) */ | |
3267 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3268 | { |
e17a4113 UW |
3269 | unsigned long indirect = |
3270 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3271 | struct minimal_symbol *indsym = |
fc338970 | 3272 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 3273 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3274 | |
c5aa993b | 3275 | if (symname) |
c906108c | 3276 | { |
c5aa993b JM |
3277 | if (strncmp (symname, "__imp_", 6) == 0 |
3278 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
3279 | return name ? 1 : |
3280 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3281 | } |
3282 | } | |
fc338970 | 3283 | return 0; /* Not a trampoline. */ |
c906108c | 3284 | } |
fc338970 MK |
3285 | \f |
3286 | ||
10458914 DJ |
3287 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3288 | routine. */ | |
8201327c | 3289 | |
4bd207ef | 3290 | int |
10458914 | 3291 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3292 | { |
10458914 | 3293 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3294 | char *name; |
3295 | ||
3296 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3297 | return (name && strcmp ("_sigtramp", name) == 0); |
3298 | } | |
3299 | \f | |
3300 | ||
fc338970 MK |
3301 | /* We have two flavours of disassembly. The machinery on this page |
3302 | deals with switching between those. */ | |
c906108c SS |
3303 | |
3304 | static int | |
a89aa300 | 3305 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3306 | { |
5e3397bb MK |
3307 | gdb_assert (disassembly_flavor == att_flavor |
3308 | || disassembly_flavor == intel_flavor); | |
3309 | ||
3310 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3311 | constified, cast to prevent a compiler warning. */ | |
3312 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3313 | |
3314 | return print_insn_i386 (pc, info); | |
7a292a7a | 3315 | } |
fc338970 | 3316 | \f |
3ce1502b | 3317 | |
8201327c MK |
3318 | /* There are a few i386 architecture variants that differ only |
3319 | slightly from the generic i386 target. For now, we don't give them | |
3320 | their own source file, but include them here. As a consequence, | |
3321 | they'll always be included. */ | |
3ce1502b | 3322 | |
8201327c | 3323 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3324 | |
10458914 DJ |
3325 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
3326 | routine. */ | |
911bc6ee | 3327 | |
8201327c | 3328 | static int |
10458914 | 3329 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 3330 | { |
10458914 | 3331 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
3332 | char *name; |
3333 | ||
acd5c798 MK |
3334 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
3335 | currently unknown. */ | |
911bc6ee | 3336 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
3337 | return (name && (strcmp ("_sigreturn", name) == 0 |
3338 | || strcmp ("_sigacthandler", name) == 0 | |
3339 | || strcmp ("sigvechandler", name) == 0)); | |
3340 | } | |
d2a7c97a | 3341 | |
10458914 DJ |
3342 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
3343 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 3344 | |
3a1e71e3 | 3345 | static CORE_ADDR |
10458914 | 3346 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 3347 | { |
e17a4113 UW |
3348 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3349 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 3350 | gdb_byte buf[4]; |
acd5c798 | 3351 | CORE_ADDR sp; |
3ce1502b | 3352 | |
10458914 | 3353 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 3354 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 3355 | |
e17a4113 | 3356 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
3357 | } |
3358 | \f | |
3ce1502b | 3359 | |
8201327c | 3360 | /* Generic ELF. */ |
d2a7c97a | 3361 | |
8201327c MK |
3362 | void |
3363 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3364 | { | |
c4fc7f1b MK |
3365 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
3366 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 3367 | } |
3ce1502b | 3368 | |
8201327c | 3369 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3370 | |
8201327c MK |
3371 | void |
3372 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
3373 | { | |
3374 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 3375 | |
8201327c MK |
3376 | /* System V Release 4 uses ELF. */ |
3377 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 3378 | |
dfe01d39 | 3379 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
3380 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
3381 | ||
911bc6ee | 3382 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 3383 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
3384 | tdep->sc_pc_offset = 36 + 14 * 4; |
3385 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 3386 | |
8201327c | 3387 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
3388 | } |
3389 | ||
8201327c | 3390 | /* DJGPP. */ |
3ce1502b | 3391 | |
3a1e71e3 | 3392 | static void |
8201327c | 3393 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 3394 | { |
8201327c | 3395 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 3396 | |
911bc6ee MK |
3397 | /* DJGPP doesn't have any special frames for signal handlers. */ |
3398 | tdep->sigtramp_p = NULL; | |
3ce1502b | 3399 | |
8201327c | 3400 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
3401 | |
3402 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
3403 | if (! tdesc_has_registers (info.target_desc)) |
3404 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
3405 | |
3406 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
3407 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
3408 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
3409 | set_gdbarch_sdb_reg_to_regnum. */ | |
3410 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3411 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
3412 | |
3413 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
3ce1502b | 3414 | } |
8201327c | 3415 | \f |
2acceee2 | 3416 | |
38c968cf AC |
3417 | /* i386 register groups. In addition to the normal groups, add "mmx" |
3418 | and "sse". */ | |
3419 | ||
3420 | static struct reggroup *i386_sse_reggroup; | |
3421 | static struct reggroup *i386_mmx_reggroup; | |
3422 | ||
3423 | static void | |
3424 | i386_init_reggroups (void) | |
3425 | { | |
3426 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
3427 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
3428 | } | |
3429 | ||
3430 | static void | |
3431 | i386_add_reggroups (struct gdbarch *gdbarch) | |
3432 | { | |
3433 | reggroup_add (gdbarch, i386_sse_reggroup); | |
3434 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
3435 | reggroup_add (gdbarch, general_reggroup); | |
3436 | reggroup_add (gdbarch, float_reggroup); | |
3437 | reggroup_add (gdbarch, all_reggroup); | |
3438 | reggroup_add (gdbarch, save_reggroup); | |
3439 | reggroup_add (gdbarch, restore_reggroup); | |
3440 | reggroup_add (gdbarch, vector_reggroup); | |
3441 | reggroup_add (gdbarch, system_reggroup); | |
3442 | } | |
3443 | ||
3444 | int | |
3445 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
3446 | struct reggroup *group) | |
3447 | { | |
c131fcee L |
3448 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3449 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
3450 | ymm_regnum_p, ymmh_regnum_p; | |
acd5c798 | 3451 | |
1ba53b71 L |
3452 | /* Don't include pseudo registers, except for MMX, in any register |
3453 | groups. */ | |
c131fcee | 3454 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3455 | return 0; |
3456 | ||
c131fcee | 3457 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3458 | return 0; |
3459 | ||
c131fcee | 3460 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3461 | return 0; |
3462 | ||
3463 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
3464 | if (group == i386_mmx_reggroup) |
3465 | return mmx_regnum_p; | |
1ba53b71 | 3466 | |
c131fcee L |
3467 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
3468 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); | |
38c968cf | 3469 | if (group == i386_sse_reggroup) |
c131fcee L |
3470 | return xmm_regnum_p || mxcsr_regnum_p; |
3471 | ||
3472 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
38c968cf | 3473 | if (group == vector_reggroup) |
c131fcee L |
3474 | return (mmx_regnum_p |
3475 | || ymm_regnum_p | |
3476 | || mxcsr_regnum_p | |
3477 | || (xmm_regnum_p | |
3478 | && ((tdep->xcr0 & I386_XSTATE_AVX_MASK) | |
3479 | == I386_XSTATE_SSE_MASK))); | |
1ba53b71 L |
3480 | |
3481 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
3482 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
3483 | if (group == float_reggroup) |
3484 | return fp_regnum_p; | |
1ba53b71 | 3485 | |
c131fcee L |
3486 | /* For "info reg all", don't include upper YMM registers nor XMM |
3487 | registers when AVX is supported. */ | |
3488 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
3489 | if (group == all_reggroup | |
3490 | && ((xmm_regnum_p | |
3491 | && (tdep->xcr0 & I386_XSTATE_AVX)) | |
3492 | || ymmh_regnum_p)) | |
3493 | return 0; | |
3494 | ||
38c968cf | 3495 | if (group == general_reggroup) |
1ba53b71 L |
3496 | return (!fp_regnum_p |
3497 | && !mmx_regnum_p | |
c131fcee L |
3498 | && !mxcsr_regnum_p |
3499 | && !xmm_regnum_p | |
3500 | && !ymm_regnum_p | |
3501 | && !ymmh_regnum_p); | |
acd5c798 | 3502 | |
38c968cf AC |
3503 | return default_register_reggroup_p (gdbarch, regnum, group); |
3504 | } | |
38c968cf | 3505 | \f |
acd5c798 | 3506 | |
f837910f MK |
3507 | /* Get the ARGIth function argument for the current function. */ |
3508 | ||
42c466d7 | 3509 | static CORE_ADDR |
143985b7 AF |
3510 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
3511 | struct type *type) | |
3512 | { | |
e17a4113 UW |
3513 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3514 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 3515 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 3516 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
3517 | } |
3518 | ||
514f746b AR |
3519 | static void |
3520 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
3521 | { | |
3522 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
3523 | ||
3524 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
3525 | adjust the PC in the regcache. */ | |
3526 | current_pc += 1; | |
3527 | regcache_write_pc (regcache, current_pc); | |
3528 | } | |
3529 | ||
3530 | ||
7ad10968 HZ |
3531 | #define PREFIX_REPZ 0x01 |
3532 | #define PREFIX_REPNZ 0x02 | |
3533 | #define PREFIX_LOCK 0x04 | |
3534 | #define PREFIX_DATA 0x08 | |
3535 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 3536 | |
7ad10968 HZ |
3537 | /* operand size */ |
3538 | enum | |
3539 | { | |
3540 | OT_BYTE = 0, | |
3541 | OT_WORD, | |
3542 | OT_LONG, | |
cf648174 | 3543 | OT_QUAD, |
a3c4230a | 3544 | OT_DQUAD, |
7ad10968 | 3545 | }; |
473f17b0 | 3546 | |
7ad10968 HZ |
3547 | /* i386 arith/logic operations */ |
3548 | enum | |
3549 | { | |
3550 | OP_ADDL, | |
3551 | OP_ORL, | |
3552 | OP_ADCL, | |
3553 | OP_SBBL, | |
3554 | OP_ANDL, | |
3555 | OP_SUBL, | |
3556 | OP_XORL, | |
3557 | OP_CMPL, | |
3558 | }; | |
5716833c | 3559 | |
7ad10968 HZ |
3560 | struct i386_record_s |
3561 | { | |
cf648174 | 3562 | struct gdbarch *gdbarch; |
7ad10968 | 3563 | struct regcache *regcache; |
df61f520 | 3564 | CORE_ADDR orig_addr; |
7ad10968 HZ |
3565 | CORE_ADDR addr; |
3566 | int aflag; | |
3567 | int dflag; | |
3568 | int override; | |
3569 | uint8_t modrm; | |
3570 | uint8_t mod, reg, rm; | |
3571 | int ot; | |
cf648174 HZ |
3572 | uint8_t rex_x; |
3573 | uint8_t rex_b; | |
3574 | int rip_offset; | |
3575 | int popl_esp_hack; | |
3576 | const int *regmap; | |
7ad10968 | 3577 | }; |
5716833c | 3578 | |
7ad10968 | 3579 | /* Parse "modrm" part in current memory address that irp->addr point to |
1777feb0 | 3580 | Return -1 if something wrong. */ |
5716833c | 3581 | |
7ad10968 HZ |
3582 | static int |
3583 | i386_record_modrm (struct i386_record_s *irp) | |
3584 | { | |
cf648174 | 3585 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 3586 | |
7ad10968 HZ |
3587 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
3588 | { | |
3589 | if (record_debug) | |
3590 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3591 | "addr %s len = 1.\n"), |
3592 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3593 | return -1; |
3594 | } | |
3595 | irp->addr++; | |
3596 | irp->mod = (irp->modrm >> 6) & 3; | |
3597 | irp->reg = (irp->modrm >> 3) & 7; | |
3598 | irp->rm = irp->modrm & 7; | |
5716833c | 3599 | |
7ad10968 HZ |
3600 | return 0; |
3601 | } | |
d2a7c97a | 3602 | |
7ad10968 HZ |
3603 | /* Get the memory address that current instruction write to and set it to |
3604 | the argument "addr". | |
1777feb0 | 3605 | Return -1 if something wrong. */ |
8201327c | 3606 | |
7ad10968 | 3607 | static int |
cf648174 | 3608 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 3609 | { |
cf648174 | 3610 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
3611 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3612 | gdb_byte buf[4]; | |
3613 | ULONGEST offset64; | |
21d0e8a4 | 3614 | |
7ad10968 HZ |
3615 | *addr = 0; |
3616 | if (irp->aflag) | |
3617 | { | |
3618 | /* 32 bits */ | |
3619 | int havesib = 0; | |
3620 | uint8_t scale = 0; | |
648d0c8b | 3621 | uint8_t byte; |
7ad10968 HZ |
3622 | uint8_t index = 0; |
3623 | uint8_t base = irp->rm; | |
896fb97d | 3624 | |
7ad10968 HZ |
3625 | if (base == 4) |
3626 | { | |
3627 | havesib = 1; | |
648d0c8b | 3628 | if (target_read_memory (irp->addr, &byte, 1)) |
7ad10968 HZ |
3629 | { |
3630 | if (record_debug) | |
3631 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3632 | "at addr %s len = 1.\n"), |
3633 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3634 | return -1; |
3635 | } | |
3636 | irp->addr++; | |
648d0c8b MS |
3637 | scale = (byte >> 6) & 3; |
3638 | index = ((byte >> 3) & 7) | irp->rex_x; | |
3639 | base = (byte & 7); | |
7ad10968 | 3640 | } |
cf648174 | 3641 | base |= irp->rex_b; |
21d0e8a4 | 3642 | |
7ad10968 HZ |
3643 | switch (irp->mod) |
3644 | { | |
3645 | case 0: | |
3646 | if ((base & 7) == 5) | |
3647 | { | |
3648 | base = 0xff; | |
60a1502a | 3649 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3650 | { |
3651 | if (record_debug) | |
3652 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3653 | "memory at addr %s len = 4.\n"), |
3654 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3655 | return -1; |
3656 | } | |
3657 | irp->addr += 4; | |
60a1502a | 3658 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
3659 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
3660 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 3661 | } |
7ad10968 HZ |
3662 | break; |
3663 | case 1: | |
60a1502a | 3664 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3665 | { |
3666 | if (record_debug) | |
3667 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3668 | "at addr %s len = 1.\n"), |
3669 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3670 | return -1; |
3671 | } | |
3672 | irp->addr++; | |
60a1502a | 3673 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3674 | break; |
3675 | case 2: | |
60a1502a | 3676 | if (target_read_memory (irp->addr, buf, 4)) |
7ad10968 HZ |
3677 | { |
3678 | if (record_debug) | |
3679 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3680 | "at addr %s len = 4.\n"), |
3681 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3682 | return -1; |
3683 | } | |
60a1502a | 3684 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
3685 | irp->addr += 4; |
3686 | break; | |
3687 | } | |
356a6b3e | 3688 | |
60a1502a | 3689 | offset64 = 0; |
7ad10968 | 3690 | if (base != 0xff) |
cf648174 HZ |
3691 | { |
3692 | if (base == 4 && irp->popl_esp_hack) | |
3693 | *addr += irp->popl_esp_hack; | |
3694 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 3695 | &offset64); |
7ad10968 | 3696 | } |
cf648174 HZ |
3697 | if (irp->aflag == 2) |
3698 | { | |
60a1502a | 3699 | *addr += offset64; |
cf648174 HZ |
3700 | } |
3701 | else | |
60a1502a | 3702 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 3703 | |
7ad10968 HZ |
3704 | if (havesib && (index != 4 || scale != 0)) |
3705 | { | |
cf648174 | 3706 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 3707 | &offset64); |
cf648174 | 3708 | if (irp->aflag == 2) |
60a1502a | 3709 | *addr += offset64 << scale; |
cf648174 | 3710 | else |
60a1502a | 3711 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 HZ |
3712 | } |
3713 | } | |
3714 | else | |
3715 | { | |
3716 | /* 16 bits */ | |
3717 | switch (irp->mod) | |
3718 | { | |
3719 | case 0: | |
3720 | if (irp->rm == 6) | |
3721 | { | |
60a1502a | 3722 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3723 | { |
3724 | if (record_debug) | |
3725 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3726 | "memory at addr %s len = 2.\n"), |
3727 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3728 | return -1; |
3729 | } | |
3730 | irp->addr += 2; | |
60a1502a | 3731 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3732 | irp->rm = 0; |
3733 | goto no_rm; | |
3734 | } | |
7ad10968 HZ |
3735 | break; |
3736 | case 1: | |
60a1502a | 3737 | if (target_read_memory (irp->addr, buf, 1)) |
7ad10968 HZ |
3738 | { |
3739 | if (record_debug) | |
3740 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3741 | "at addr %s len = 1.\n"), |
3742 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3743 | return -1; |
3744 | } | |
3745 | irp->addr++; | |
60a1502a | 3746 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
3747 | break; |
3748 | case 2: | |
60a1502a | 3749 | if (target_read_memory (irp->addr, buf, 2)) |
7ad10968 HZ |
3750 | { |
3751 | if (record_debug) | |
3752 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3753 | "at addr %s len = 2.\n"), |
3754 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3755 | return -1; |
3756 | } | |
3757 | irp->addr += 2; | |
60a1502a | 3758 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
3759 | break; |
3760 | } | |
c4fc7f1b | 3761 | |
7ad10968 HZ |
3762 | switch (irp->rm) |
3763 | { | |
3764 | case 0: | |
cf648174 HZ |
3765 | regcache_raw_read_unsigned (irp->regcache, |
3766 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3767 | &offset64); |
3768 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3769 | regcache_raw_read_unsigned (irp->regcache, |
3770 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3771 | &offset64); |
3772 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3773 | break; |
3774 | case 1: | |
cf648174 HZ |
3775 | regcache_raw_read_unsigned (irp->regcache, |
3776 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3777 | &offset64); |
3778 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3779 | regcache_raw_read_unsigned (irp->regcache, |
3780 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3781 | &offset64); |
3782 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3783 | break; |
3784 | case 2: | |
cf648174 HZ |
3785 | regcache_raw_read_unsigned (irp->regcache, |
3786 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3787 | &offset64); |
3788 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3789 | regcache_raw_read_unsigned (irp->regcache, |
3790 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3791 | &offset64); |
3792 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3793 | break; |
3794 | case 3: | |
cf648174 HZ |
3795 | regcache_raw_read_unsigned (irp->regcache, |
3796 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3797 | &offset64); |
3798 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
3799 | regcache_raw_read_unsigned (irp->regcache, |
3800 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3801 | &offset64); |
3802 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3803 | break; |
3804 | case 4: | |
cf648174 HZ |
3805 | regcache_raw_read_unsigned (irp->regcache, |
3806 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
3807 | &offset64); |
3808 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3809 | break; |
3810 | case 5: | |
cf648174 HZ |
3811 | regcache_raw_read_unsigned (irp->regcache, |
3812 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
3813 | &offset64); |
3814 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3815 | break; |
3816 | case 6: | |
cf648174 HZ |
3817 | regcache_raw_read_unsigned (irp->regcache, |
3818 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
3819 | &offset64); |
3820 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3821 | break; |
3822 | case 7: | |
cf648174 HZ |
3823 | regcache_raw_read_unsigned (irp->regcache, |
3824 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
3825 | &offset64); |
3826 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
3827 | break; |
3828 | } | |
3829 | *addr &= 0xffff; | |
3830 | } | |
c4fc7f1b | 3831 | |
01fe1b41 | 3832 | no_rm: |
7ad10968 HZ |
3833 | return 0; |
3834 | } | |
c4fc7f1b | 3835 | |
7ad10968 HZ |
3836 | /* Record the value of the memory that willbe changed in current instruction |
3837 | to "record_arch_list". | |
1777feb0 | 3838 | Return -1 if something wrong. */ |
356a6b3e | 3839 | |
7ad10968 HZ |
3840 | static int |
3841 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3842 | { | |
cf648174 HZ |
3843 | struct gdbarch *gdbarch = irp->gdbarch; |
3844 | uint64_t addr; | |
356a6b3e | 3845 | |
d7877f7e | 3846 | if (irp->override >= 0) |
7ad10968 | 3847 | { |
bb08c432 HZ |
3848 | if (record_memory_query) |
3849 | { | |
3850 | int q; | |
3851 | ||
3852 | target_terminal_ours (); | |
3853 | q = yquery (_("\ | |
3854 | Process record ignores the memory change of instruction at address %s\n\ | |
3855 | because it can't get the value of the segment register.\n\ | |
3856 | Do you want to stop the program?"), | |
3857 | paddress (gdbarch, irp->orig_addr)); | |
3858 | target_terminal_inferior (); | |
3859 | if (q) | |
3860 | return -1; | |
3861 | } | |
3862 | ||
7ad10968 HZ |
3863 | return 0; |
3864 | } | |
61113f8b | 3865 | |
7ad10968 HZ |
3866 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3867 | return -1; | |
96297dab | 3868 | |
7ad10968 HZ |
3869 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3870 | return -1; | |
a62cc96e | 3871 | |
7ad10968 HZ |
3872 | return 0; |
3873 | } | |
b6197528 | 3874 | |
cf648174 | 3875 | /* Record the push operation to "record_arch_list". |
1777feb0 | 3876 | Return -1 if something wrong. */ |
cf648174 HZ |
3877 | |
3878 | static int | |
3879 | i386_record_push (struct i386_record_s *irp, int size) | |
3880 | { | |
648d0c8b | 3881 | ULONGEST addr; |
cf648174 HZ |
3882 | |
3883 | if (record_arch_list_add_reg (irp->regcache, | |
3884 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3885 | return -1; | |
3886 | regcache_raw_read_unsigned (irp->regcache, | |
3887 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b MS |
3888 | &addr); |
3889 | if (record_arch_list_add_mem ((CORE_ADDR) addr - size, size)) | |
cf648174 HZ |
3890 | return -1; |
3891 | ||
3892 | return 0; | |
3893 | } | |
3894 | ||
0289bdd7 MS |
3895 | |
3896 | /* Defines contents to record. */ | |
3897 | #define I386_SAVE_FPU_REGS 0xfffd | |
3898 | #define I386_SAVE_FPU_ENV 0xfffe | |
3899 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
3900 | ||
1777feb0 MS |
3901 | /* Record the value of floating point registers which will be changed |
3902 | by the current instruction to "record_arch_list". Return -1 if | |
3903 | something is wrong. */ | |
0289bdd7 MS |
3904 | |
3905 | static int i386_record_floats (struct gdbarch *gdbarch, | |
3906 | struct i386_record_s *ir, | |
3907 | uint32_t iregnum) | |
3908 | { | |
3909 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3910 | int i; | |
3911 | ||
3912 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
3913 | happen. Currently we store st0-st7 registers, but we need not store all | |
3914 | registers all the time, in future we use ftag register and record only | |
3915 | those who are not marked as an empty. */ | |
3916 | ||
3917 | if (I386_SAVE_FPU_REGS == iregnum) | |
3918 | { | |
3919 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
3920 | { | |
3921 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3922 | return -1; | |
3923 | } | |
3924 | } | |
3925 | else if (I386_SAVE_FPU_ENV == iregnum) | |
3926 | { | |
3927 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3928 | { | |
3929 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3930 | return -1; | |
3931 | } | |
3932 | } | |
3933 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
3934 | { | |
3935 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3936 | { | |
3937 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3938 | return -1; | |
3939 | } | |
3940 | } | |
3941 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
3942 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
3943 | { | |
3944 | if (record_arch_list_add_reg (ir->regcache,iregnum)) | |
3945 | return -1; | |
3946 | } | |
3947 | else | |
3948 | { | |
3949 | /* Parameter error. */ | |
3950 | return -1; | |
3951 | } | |
3952 | if(I386_SAVE_FPU_ENV != iregnum) | |
3953 | { | |
3954 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
3955 | { | |
3956 | if (record_arch_list_add_reg (ir->regcache, i)) | |
3957 | return -1; | |
3958 | } | |
3959 | } | |
3960 | return 0; | |
3961 | } | |
3962 | ||
7ad10968 HZ |
3963 | /* Parse the current instruction and record the values of the registers and |
3964 | memory that will be changed in current instruction to "record_arch_list". | |
1777feb0 | 3965 | Return -1 if something wrong. */ |
8201327c | 3966 | |
cf648174 HZ |
3967 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3968 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3969 | ||
a6b808b4 | 3970 | int |
7ad10968 | 3971 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 3972 | CORE_ADDR input_addr) |
7ad10968 | 3973 | { |
60a1502a | 3974 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 3975 | int prefixes = 0; |
580879fc | 3976 | int regnum = 0; |
425b824a MS |
3977 | uint32_t opcode; |
3978 | uint8_t opcode8; | |
648d0c8b | 3979 | ULONGEST addr; |
60a1502a | 3980 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 3981 | struct i386_record_s ir; |
0289bdd7 | 3982 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
3983 | int rex = 0; |
3984 | uint8_t rex_w = -1; | |
3985 | uint8_t rex_r = 0; | |
7ad10968 | 3986 | |
8408d274 | 3987 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 3988 | ir.regcache = regcache; |
648d0c8b MS |
3989 | ir.addr = input_addr; |
3990 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
3991 | ir.aflag = 1; |
3992 | ir.dflag = 1; | |
cf648174 HZ |
3993 | ir.override = -1; |
3994 | ir.popl_esp_hack = 0; | |
a3c4230a | 3995 | ir.regmap = tdep->record_regmap; |
cf648174 | 3996 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
3997 | |
3998 | if (record_debug > 1) | |
3999 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
4000 | "addr = %s\n", |
4001 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4002 | |
4003 | /* prefixes */ | |
4004 | while (1) | |
4005 | { | |
425b824a | 4006 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4007 | { |
4008 | if (record_debug) | |
4009 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4010 | "addr %s len = 1.\n"), |
4011 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4012 | return -1; |
4013 | } | |
4014 | ir.addr++; | |
425b824a | 4015 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 4016 | { |
01fe1b41 | 4017 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
4018 | prefixes |= PREFIX_REPZ; |
4019 | break; | |
01fe1b41 | 4020 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
4021 | prefixes |= PREFIX_REPNZ; |
4022 | break; | |
01fe1b41 | 4023 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
4024 | prefixes |= PREFIX_LOCK; |
4025 | break; | |
01fe1b41 | 4026 | case CS_PREFIX_OPCODE: |
cf648174 | 4027 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 4028 | break; |
01fe1b41 | 4029 | case SS_PREFIX_OPCODE: |
cf648174 | 4030 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 4031 | break; |
01fe1b41 | 4032 | case DS_PREFIX_OPCODE: |
cf648174 | 4033 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 4034 | break; |
01fe1b41 | 4035 | case ES_PREFIX_OPCODE: |
cf648174 | 4036 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 4037 | break; |
01fe1b41 | 4038 | case FS_PREFIX_OPCODE: |
cf648174 | 4039 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 4040 | break; |
01fe1b41 | 4041 | case GS_PREFIX_OPCODE: |
cf648174 | 4042 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 4043 | break; |
01fe1b41 | 4044 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
4045 | prefixes |= PREFIX_DATA; |
4046 | break; | |
01fe1b41 | 4047 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
4048 | prefixes |= PREFIX_ADDR; |
4049 | break; | |
d691bec7 MS |
4050 | case 0x40: /* i386 inc %eax */ |
4051 | case 0x41: /* i386 inc %ecx */ | |
4052 | case 0x42: /* i386 inc %edx */ | |
4053 | case 0x43: /* i386 inc %ebx */ | |
4054 | case 0x44: /* i386 inc %esp */ | |
4055 | case 0x45: /* i386 inc %ebp */ | |
4056 | case 0x46: /* i386 inc %esi */ | |
4057 | case 0x47: /* i386 inc %edi */ | |
4058 | case 0x48: /* i386 dec %eax */ | |
4059 | case 0x49: /* i386 dec %ecx */ | |
4060 | case 0x4a: /* i386 dec %edx */ | |
4061 | case 0x4b: /* i386 dec %ebx */ | |
4062 | case 0x4c: /* i386 dec %esp */ | |
4063 | case 0x4d: /* i386 dec %ebp */ | |
4064 | case 0x4e: /* i386 dec %esi */ | |
4065 | case 0x4f: /* i386 dec %edi */ | |
4066 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
4067 | { |
4068 | /* REX */ | |
4069 | rex = 1; | |
425b824a MS |
4070 | rex_w = (opcode8 >> 3) & 1; |
4071 | rex_r = (opcode8 & 0x4) << 1; | |
4072 | ir.rex_x = (opcode8 & 0x2) << 2; | |
4073 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 4074 | } |
d691bec7 MS |
4075 | else /* 32 bit target */ |
4076 | goto out_prefixes; | |
cf648174 | 4077 | break; |
7ad10968 HZ |
4078 | default: |
4079 | goto out_prefixes; | |
4080 | break; | |
4081 | } | |
4082 | } | |
01fe1b41 | 4083 | out_prefixes: |
cf648174 HZ |
4084 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
4085 | { | |
4086 | ir.dflag = 2; | |
4087 | } | |
4088 | else | |
4089 | { | |
4090 | if (prefixes & PREFIX_DATA) | |
4091 | ir.dflag ^= 1; | |
4092 | } | |
7ad10968 HZ |
4093 | if (prefixes & PREFIX_ADDR) |
4094 | ir.aflag ^= 1; | |
cf648174 HZ |
4095 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4096 | ir.aflag = 2; | |
7ad10968 | 4097 | |
1777feb0 | 4098 | /* Now check op code. */ |
425b824a | 4099 | opcode = (uint32_t) opcode8; |
01fe1b41 | 4100 | reswitch: |
7ad10968 HZ |
4101 | switch (opcode) |
4102 | { | |
4103 | case 0x0f: | |
425b824a | 4104 | if (target_read_memory (ir.addr, &opcode8, 1)) |
7ad10968 HZ |
4105 | { |
4106 | if (record_debug) | |
4107 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
4108 | "addr %s len = 1.\n"), |
4109 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4110 | return -1; |
4111 | } | |
4112 | ir.addr++; | |
a3c4230a | 4113 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
4114 | goto reswitch; |
4115 | break; | |
93924b6b | 4116 | |
a38bba38 | 4117 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
4118 | case 0x01: |
4119 | case 0x02: | |
4120 | case 0x03: | |
4121 | case 0x04: | |
4122 | case 0x05: | |
4123 | case 0x08: | |
4124 | case 0x09: | |
4125 | case 0x0a: | |
4126 | case 0x0b: | |
4127 | case 0x0c: | |
4128 | case 0x0d: | |
4129 | case 0x10: | |
4130 | case 0x11: | |
4131 | case 0x12: | |
4132 | case 0x13: | |
4133 | case 0x14: | |
4134 | case 0x15: | |
4135 | case 0x18: | |
4136 | case 0x19: | |
4137 | case 0x1a: | |
4138 | case 0x1b: | |
4139 | case 0x1c: | |
4140 | case 0x1d: | |
4141 | case 0x20: | |
4142 | case 0x21: | |
4143 | case 0x22: | |
4144 | case 0x23: | |
4145 | case 0x24: | |
4146 | case 0x25: | |
4147 | case 0x28: | |
4148 | case 0x29: | |
4149 | case 0x2a: | |
4150 | case 0x2b: | |
4151 | case 0x2c: | |
4152 | case 0x2d: | |
4153 | case 0x30: | |
4154 | case 0x31: | |
4155 | case 0x32: | |
4156 | case 0x33: | |
4157 | case 0x34: | |
4158 | case 0x35: | |
4159 | case 0x38: | |
4160 | case 0x39: | |
4161 | case 0x3a: | |
4162 | case 0x3b: | |
4163 | case 0x3c: | |
4164 | case 0x3d: | |
4165 | if (((opcode >> 3) & 7) != OP_CMPL) | |
4166 | { | |
4167 | if ((opcode & 1) == 0) | |
4168 | ir.ot = OT_BYTE; | |
4169 | else | |
4170 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 4171 | |
7ad10968 HZ |
4172 | switch ((opcode >> 1) & 3) |
4173 | { | |
a38bba38 | 4174 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
4175 | if (i386_record_modrm (&ir)) |
4176 | return -1; | |
4177 | if (ir.mod != 3) | |
4178 | { | |
4179 | if (i386_record_lea_modrm (&ir)) | |
4180 | return -1; | |
4181 | } | |
4182 | else | |
4183 | { | |
cf648174 HZ |
4184 | ir.rm |= ir.rex_b; |
4185 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4186 | ir.rm &= 0x3; |
cf648174 | 4187 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4188 | } |
4189 | break; | |
a38bba38 | 4190 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
4191 | if (i386_record_modrm (&ir)) |
4192 | return -1; | |
cf648174 HZ |
4193 | ir.reg |= rex_r; |
4194 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4195 | ir.reg &= 0x3; |
cf648174 | 4196 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4197 | break; |
a38bba38 | 4198 | case 2: /* OP A, Iv */ |
cf648174 | 4199 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4200 | break; |
4201 | } | |
4202 | } | |
cf648174 | 4203 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4204 | break; |
42fdc8df | 4205 | |
a38bba38 | 4206 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
4207 | case 0x81: |
4208 | case 0x82: | |
4209 | case 0x83: | |
4210 | if (i386_record_modrm (&ir)) | |
4211 | return -1; | |
8201327c | 4212 | |
7ad10968 HZ |
4213 | if (ir.reg != OP_CMPL) |
4214 | { | |
4215 | if ((opcode & 1) == 0) | |
4216 | ir.ot = OT_BYTE; | |
4217 | else | |
4218 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 4219 | |
7ad10968 HZ |
4220 | if (ir.mod != 3) |
4221 | { | |
cf648174 HZ |
4222 | if (opcode == 0x83) |
4223 | ir.rip_offset = 1; | |
4224 | else | |
4225 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4226 | if (i386_record_lea_modrm (&ir)) |
4227 | return -1; | |
4228 | } | |
4229 | else | |
cf648174 | 4230 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 4231 | } |
cf648174 | 4232 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4233 | break; |
5e3397bb | 4234 | |
a38bba38 | 4235 | case 0x40: /* inc */ |
7ad10968 HZ |
4236 | case 0x41: |
4237 | case 0x42: | |
4238 | case 0x43: | |
4239 | case 0x44: | |
4240 | case 0x45: | |
4241 | case 0x46: | |
4242 | case 0x47: | |
a38bba38 MS |
4243 | |
4244 | case 0x48: /* dec */ | |
7ad10968 HZ |
4245 | case 0x49: |
4246 | case 0x4a: | |
4247 | case 0x4b: | |
4248 | case 0x4c: | |
4249 | case 0x4d: | |
4250 | case 0x4e: | |
4251 | case 0x4f: | |
a38bba38 | 4252 | |
cf648174 HZ |
4253 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
4254 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 4255 | break; |
acd5c798 | 4256 | |
a38bba38 | 4257 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
4258 | case 0xf7: |
4259 | if ((opcode & 1) == 0) | |
4260 | ir.ot = OT_BYTE; | |
4261 | else | |
4262 | ir.ot = ir.dflag + OT_WORD; | |
4263 | if (i386_record_modrm (&ir)) | |
4264 | return -1; | |
acd5c798 | 4265 | |
cf648174 HZ |
4266 | if (ir.mod != 3 && ir.reg == 0) |
4267 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4268 | ||
7ad10968 HZ |
4269 | switch (ir.reg) |
4270 | { | |
a38bba38 | 4271 | case 0: /* test */ |
cf648174 | 4272 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4273 | break; |
a38bba38 MS |
4274 | case 2: /* not */ |
4275 | case 3: /* neg */ | |
7ad10968 HZ |
4276 | if (ir.mod != 3) |
4277 | { | |
4278 | if (i386_record_lea_modrm (&ir)) | |
4279 | return -1; | |
4280 | } | |
4281 | else | |
4282 | { | |
cf648174 HZ |
4283 | ir.rm |= ir.rex_b; |
4284 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4285 | ir.rm &= 0x3; |
cf648174 | 4286 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4287 | } |
a38bba38 | 4288 | if (ir.reg == 3) /* neg */ |
cf648174 | 4289 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4290 | break; |
a38bba38 MS |
4291 | case 4: /* mul */ |
4292 | case 5: /* imul */ | |
4293 | case 6: /* div */ | |
4294 | case 7: /* idiv */ | |
cf648174 | 4295 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 4296 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
4297 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
4298 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4299 | break; |
4300 | default: | |
4301 | ir.addr -= 2; | |
4302 | opcode = opcode << 8 | ir.modrm; | |
4303 | goto no_support; | |
4304 | break; | |
4305 | } | |
4306 | break; | |
4307 | ||
a38bba38 MS |
4308 | case 0xfe: /* GRP4 */ |
4309 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
4310 | if (i386_record_modrm (&ir)) |
4311 | return -1; | |
4312 | if (ir.reg >= 2 && opcode == 0xfe) | |
4313 | { | |
4314 | ir.addr -= 2; | |
4315 | opcode = opcode << 8 | ir.modrm; | |
4316 | goto no_support; | |
4317 | } | |
7ad10968 HZ |
4318 | switch (ir.reg) |
4319 | { | |
a38bba38 MS |
4320 | case 0: /* inc */ |
4321 | case 1: /* dec */ | |
cf648174 HZ |
4322 | if ((opcode & 1) == 0) |
4323 | ir.ot = OT_BYTE; | |
4324 | else | |
4325 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4326 | if (ir.mod != 3) |
4327 | { | |
4328 | if (i386_record_lea_modrm (&ir)) | |
4329 | return -1; | |
4330 | } | |
4331 | else | |
4332 | { | |
cf648174 HZ |
4333 | ir.rm |= ir.rex_b; |
4334 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4335 | ir.rm &= 0x3; |
cf648174 | 4336 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4337 | } |
cf648174 | 4338 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4339 | break; |
a38bba38 | 4340 | case 2: /* call */ |
cf648174 HZ |
4341 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4342 | ir.dflag = 2; | |
4343 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4344 | return -1; |
cf648174 | 4345 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4346 | break; |
a38bba38 | 4347 | case 3: /* lcall */ |
cf648174 HZ |
4348 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4349 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4350 | return -1; |
cf648174 | 4351 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 4352 | break; |
a38bba38 MS |
4353 | case 4: /* jmp */ |
4354 | case 5: /* ljmp */ | |
cf648174 HZ |
4355 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4356 | break; | |
a38bba38 | 4357 | case 6: /* push */ |
cf648174 HZ |
4358 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4359 | ir.dflag = 2; | |
4360 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4361 | return -1; | |
7ad10968 HZ |
4362 | break; |
4363 | default: | |
4364 | ir.addr -= 2; | |
4365 | opcode = opcode << 8 | ir.modrm; | |
4366 | goto no_support; | |
4367 | break; | |
4368 | } | |
4369 | break; | |
4370 | ||
a38bba38 | 4371 | case 0x84: /* test */ |
7ad10968 HZ |
4372 | case 0x85: |
4373 | case 0xa8: | |
4374 | case 0xa9: | |
cf648174 | 4375 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4376 | break; |
4377 | ||
a38bba38 | 4378 | case 0x98: /* CWDE/CBW */ |
cf648174 | 4379 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4380 | break; |
4381 | ||
a38bba38 | 4382 | case 0x99: /* CDQ/CWD */ |
cf648174 HZ |
4383 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4384 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4385 | break; |
4386 | ||
a38bba38 | 4387 | case 0x0faf: /* imul */ |
7ad10968 HZ |
4388 | case 0x69: |
4389 | case 0x6b: | |
4390 | ir.ot = ir.dflag + OT_WORD; | |
4391 | if (i386_record_modrm (&ir)) | |
4392 | return -1; | |
cf648174 HZ |
4393 | if (opcode == 0x69) |
4394 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
4395 | else if (opcode == 0x6b) | |
4396 | ir.rip_offset = 1; | |
4397 | ir.reg |= rex_r; | |
4398 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4399 | ir.reg &= 0x3; |
cf648174 HZ |
4400 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4401 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4402 | break; |
4403 | ||
a38bba38 | 4404 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
4405 | case 0x0fc1: |
4406 | if ((opcode & 1) == 0) | |
4407 | ir.ot = OT_BYTE; | |
4408 | else | |
4409 | ir.ot = ir.dflag + OT_WORD; | |
4410 | if (i386_record_modrm (&ir)) | |
4411 | return -1; | |
cf648174 | 4412 | ir.reg |= rex_r; |
7ad10968 HZ |
4413 | if (ir.mod == 3) |
4414 | { | |
cf648174 | 4415 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4416 | ir.reg &= 0x3; |
cf648174 HZ |
4417 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4418 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4419 | ir.rm &= 0x3; |
cf648174 | 4420 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
4421 | } |
4422 | else | |
4423 | { | |
4424 | if (i386_record_lea_modrm (&ir)) | |
4425 | return -1; | |
cf648174 | 4426 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4427 | ir.reg &= 0x3; |
cf648174 | 4428 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 4429 | } |
cf648174 | 4430 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4431 | break; |
4432 | ||
a38bba38 | 4433 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
4434 | case 0x0fb1: |
4435 | if ((opcode & 1) == 0) | |
4436 | ir.ot = OT_BYTE; | |
4437 | else | |
4438 | ir.ot = ir.dflag + OT_WORD; | |
4439 | if (i386_record_modrm (&ir)) | |
4440 | return -1; | |
4441 | if (ir.mod == 3) | |
4442 | { | |
cf648174 HZ |
4443 | ir.reg |= rex_r; |
4444 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4445 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4446 | ir.reg &= 0x3; |
cf648174 | 4447 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4448 | } |
4449 | else | |
4450 | { | |
cf648174 | 4451 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4452 | if (i386_record_lea_modrm (&ir)) |
4453 | return -1; | |
4454 | } | |
cf648174 | 4455 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4456 | break; |
4457 | ||
a38bba38 | 4458 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
4459 | if (i386_record_modrm (&ir)) |
4460 | return -1; | |
4461 | if (ir.mod == 3) | |
4462 | { | |
4463 | ir.addr -= 2; | |
4464 | opcode = opcode << 8 | ir.modrm; | |
4465 | goto no_support; | |
4466 | } | |
cf648174 HZ |
4467 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4468 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
4469 | if (i386_record_lea_modrm (&ir)) |
4470 | return -1; | |
cf648174 | 4471 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4472 | break; |
4473 | ||
a38bba38 | 4474 | case 0x50: /* push */ |
7ad10968 HZ |
4475 | case 0x51: |
4476 | case 0x52: | |
4477 | case 0x53: | |
4478 | case 0x54: | |
4479 | case 0x55: | |
4480 | case 0x56: | |
4481 | case 0x57: | |
4482 | case 0x68: | |
4483 | case 0x6a: | |
cf648174 HZ |
4484 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4485 | ir.dflag = 2; | |
4486 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4487 | return -1; | |
4488 | break; | |
4489 | ||
a38bba38 MS |
4490 | case 0x06: /* push es */ |
4491 | case 0x0e: /* push cs */ | |
4492 | case 0x16: /* push ss */ | |
4493 | case 0x1e: /* push ds */ | |
cf648174 HZ |
4494 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4495 | { | |
4496 | ir.addr -= 1; | |
4497 | goto no_support; | |
4498 | } | |
4499 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4500 | return -1; | |
4501 | break; | |
4502 | ||
a38bba38 MS |
4503 | case 0x0fa0: /* push fs */ |
4504 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
4505 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4506 | { | |
4507 | ir.addr -= 2; | |
4508 | goto no_support; | |
4509 | } | |
4510 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 4511 | return -1; |
cf648174 HZ |
4512 | break; |
4513 | ||
a38bba38 | 4514 | case 0x60: /* pusha */ |
cf648174 HZ |
4515 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4516 | { | |
4517 | ir.addr -= 1; | |
4518 | goto no_support; | |
4519 | } | |
4520 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
4521 | return -1; |
4522 | break; | |
4523 | ||
a38bba38 | 4524 | case 0x58: /* pop */ |
7ad10968 HZ |
4525 | case 0x59: |
4526 | case 0x5a: | |
4527 | case 0x5b: | |
4528 | case 0x5c: | |
4529 | case 0x5d: | |
4530 | case 0x5e: | |
4531 | case 0x5f: | |
cf648174 HZ |
4532 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4533 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
4534 | break; |
4535 | ||
a38bba38 | 4536 | case 0x61: /* popa */ |
cf648174 HZ |
4537 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4538 | { | |
4539 | ir.addr -= 1; | |
4540 | goto no_support; | |
7ad10968 | 4541 | } |
425b824a MS |
4542 | for (regnum = X86_RECORD_REAX_REGNUM; |
4543 | regnum <= X86_RECORD_REDI_REGNUM; | |
4544 | regnum++) | |
4545 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); | |
7ad10968 HZ |
4546 | break; |
4547 | ||
a38bba38 | 4548 | case 0x8f: /* pop */ |
cf648174 HZ |
4549 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4550 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
4551 | else | |
4552 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4553 | if (i386_record_modrm (&ir)) |
4554 | return -1; | |
4555 | if (ir.mod == 3) | |
cf648174 | 4556 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
4557 | else |
4558 | { | |
cf648174 | 4559 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
4560 | if (i386_record_lea_modrm (&ir)) |
4561 | return -1; | |
4562 | } | |
cf648174 | 4563 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
4564 | break; |
4565 | ||
a38bba38 | 4566 | case 0xc8: /* enter */ |
cf648174 HZ |
4567 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
4568 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4569 | ir.dflag = 2; | |
4570 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
4571 | return -1; |
4572 | break; | |
4573 | ||
a38bba38 | 4574 | case 0xc9: /* leave */ |
cf648174 HZ |
4575 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4576 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
4577 | break; |
4578 | ||
a38bba38 | 4579 | case 0x07: /* pop es */ |
cf648174 HZ |
4580 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4581 | { | |
4582 | ir.addr -= 1; | |
4583 | goto no_support; | |
4584 | } | |
4585 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4586 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
4587 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4588 | break; |
4589 | ||
a38bba38 | 4590 | case 0x17: /* pop ss */ |
cf648174 HZ |
4591 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4592 | { | |
4593 | ir.addr -= 1; | |
4594 | goto no_support; | |
4595 | } | |
4596 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4597 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
4598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4599 | break; |
4600 | ||
a38bba38 | 4601 | case 0x1f: /* pop ds */ |
cf648174 HZ |
4602 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4603 | { | |
4604 | ir.addr -= 1; | |
4605 | goto no_support; | |
4606 | } | |
4607 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4608 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
4609 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4610 | break; |
4611 | ||
a38bba38 | 4612 | case 0x0fa1: /* pop fs */ |
cf648174 HZ |
4613 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4614 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
4615 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4616 | break; |
4617 | ||
a38bba38 | 4618 | case 0x0fa9: /* pop gs */ |
cf648174 HZ |
4619 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4620 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
4621 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4622 | break; |
4623 | ||
a38bba38 | 4624 | case 0x88: /* mov */ |
7ad10968 HZ |
4625 | case 0x89: |
4626 | case 0xc6: | |
4627 | case 0xc7: | |
4628 | if ((opcode & 1) == 0) | |
4629 | ir.ot = OT_BYTE; | |
4630 | else | |
4631 | ir.ot = ir.dflag + OT_WORD; | |
4632 | ||
4633 | if (i386_record_modrm (&ir)) | |
4634 | return -1; | |
4635 | ||
4636 | if (ir.mod != 3) | |
4637 | { | |
cf648174 HZ |
4638 | if (opcode == 0xc6 || opcode == 0xc7) |
4639 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
4640 | if (i386_record_lea_modrm (&ir)) |
4641 | return -1; | |
4642 | } | |
4643 | else | |
4644 | { | |
cf648174 HZ |
4645 | if (opcode == 0xc6 || opcode == 0xc7) |
4646 | ir.rm |= ir.rex_b; | |
4647 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4648 | ir.rm &= 0x3; |
cf648174 | 4649 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4650 | } |
7ad10968 | 4651 | break; |
cf648174 | 4652 | |
a38bba38 | 4653 | case 0x8a: /* mov */ |
7ad10968 HZ |
4654 | case 0x8b: |
4655 | if ((opcode & 1) == 0) | |
4656 | ir.ot = OT_BYTE; | |
4657 | else | |
4658 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4659 | if (i386_record_modrm (&ir)) |
4660 | return -1; | |
cf648174 HZ |
4661 | ir.reg |= rex_r; |
4662 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4663 | ir.reg &= 0x3; |
cf648174 HZ |
4664 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
4665 | break; | |
7ad10968 | 4666 | |
a38bba38 | 4667 | case 0x8c: /* mov seg */ |
cf648174 | 4668 | if (i386_record_modrm (&ir)) |
7ad10968 | 4669 | return -1; |
cf648174 HZ |
4670 | if (ir.reg > 5) |
4671 | { | |
4672 | ir.addr -= 2; | |
4673 | opcode = opcode << 8 | ir.modrm; | |
4674 | goto no_support; | |
4675 | } | |
4676 | ||
4677 | if (ir.mod == 3) | |
4678 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
4679 | else | |
4680 | { | |
4681 | ir.ot = OT_WORD; | |
4682 | if (i386_record_lea_modrm (&ir)) | |
4683 | return -1; | |
4684 | } | |
7ad10968 HZ |
4685 | break; |
4686 | ||
a38bba38 | 4687 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
4688 | if (i386_record_modrm (&ir)) |
4689 | return -1; | |
7ad10968 HZ |
4690 | switch (ir.reg) |
4691 | { | |
4692 | case 0: | |
425b824a | 4693 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4694 | break; |
4695 | case 2: | |
425b824a | 4696 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4697 | break; |
4698 | case 3: | |
425b824a | 4699 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4700 | break; |
4701 | case 4: | |
425b824a | 4702 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4703 | break; |
4704 | case 5: | |
425b824a | 4705 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4706 | break; |
4707 | default: | |
4708 | ir.addr -= 2; | |
4709 | opcode = opcode << 8 | ir.modrm; | |
4710 | goto no_support; | |
4711 | break; | |
4712 | } | |
425b824a | 4713 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 | 4714 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4715 | break; |
4716 | ||
a38bba38 MS |
4717 | case 0x0fb6: /* movzbS */ |
4718 | case 0x0fb7: /* movzwS */ | |
4719 | case 0x0fbe: /* movsbS */ | |
4720 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
4721 | if (i386_record_modrm (&ir)) |
4722 | return -1; | |
cf648174 | 4723 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4724 | break; |
4725 | ||
a38bba38 | 4726 | case 0x8d: /* lea */ |
7ad10968 HZ |
4727 | if (i386_record_modrm (&ir)) |
4728 | return -1; | |
4729 | if (ir.mod == 3) | |
4730 | { | |
4731 | ir.addr -= 2; | |
4732 | opcode = opcode << 8 | ir.modrm; | |
4733 | goto no_support; | |
4734 | } | |
7ad10968 | 4735 | ir.ot = ir.dflag; |
cf648174 HZ |
4736 | ir.reg |= rex_r; |
4737 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4738 | ir.reg &= 0x3; |
cf648174 | 4739 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4740 | break; |
4741 | ||
a38bba38 | 4742 | case 0xa0: /* mov EAX */ |
7ad10968 | 4743 | case 0xa1: |
a38bba38 MS |
4744 | |
4745 | case 0xd7: /* xlat */ | |
cf648174 | 4746 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4747 | break; |
4748 | ||
a38bba38 | 4749 | case 0xa2: /* mov EAX */ |
7ad10968 | 4750 | case 0xa3: |
d7877f7e | 4751 | if (ir.override >= 0) |
cf648174 | 4752 | { |
bb08c432 HZ |
4753 | if (record_memory_query) |
4754 | { | |
4755 | int q; | |
4756 | ||
4757 | target_terminal_ours (); | |
4758 | q = yquery (_("\ | |
4759 | Process record ignores the memory change of instruction at address %s\n\ | |
4760 | because it can't get the value of the segment register.\n\ | |
4761 | Do you want to stop the program?"), | |
4762 | paddress (gdbarch, ir.orig_addr)); | |
4763 | target_terminal_inferior (); | |
4764 | if (q) | |
4765 | return -1; | |
4766 | } | |
cf648174 HZ |
4767 | } |
4768 | else | |
4769 | { | |
4770 | if ((opcode & 1) == 0) | |
4771 | ir.ot = OT_BYTE; | |
4772 | else | |
4773 | ir.ot = ir.dflag + OT_WORD; | |
4774 | if (ir.aflag == 2) | |
4775 | { | |
60a1502a | 4776 | if (target_read_memory (ir.addr, buf, 8)) |
cf648174 HZ |
4777 | { |
4778 | if (record_debug) | |
4779 | printf_unfiltered (_("Process record: error reading " | |
4780 | "memory at addr 0x%s len = 8.\n"), | |
4781 | paddress (gdbarch, ir.addr)); | |
4782 | return -1; | |
4783 | } | |
4784 | ir.addr += 8; | |
60a1502a | 4785 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
4786 | } |
4787 | else if (ir.aflag) | |
4788 | { | |
60a1502a | 4789 | if (target_read_memory (ir.addr, buf, 4)) |
cf648174 HZ |
4790 | { |
4791 | if (record_debug) | |
4792 | printf_unfiltered (_("Process record: error reading " | |
4793 | "memory at addr 0x%s len = 4.\n"), | |
4794 | paddress (gdbarch, ir.addr)); | |
4795 | return -1; | |
4796 | } | |
4797 | ir.addr += 4; | |
60a1502a | 4798 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
4799 | } |
4800 | else | |
4801 | { | |
60a1502a | 4802 | if (target_read_memory (ir.addr, buf, 2)) |
cf648174 HZ |
4803 | { |
4804 | if (record_debug) | |
4805 | printf_unfiltered (_("Process record: error reading " | |
4806 | "memory at addr 0x%s len = 2.\n"), | |
4807 | paddress (gdbarch, ir.addr)); | |
4808 | return -1; | |
4809 | } | |
4810 | ir.addr += 2; | |
60a1502a | 4811 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 4812 | } |
648d0c8b | 4813 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
4814 | return -1; |
4815 | } | |
7ad10968 HZ |
4816 | break; |
4817 | ||
a38bba38 | 4818 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
4819 | case 0xb1: |
4820 | case 0xb2: | |
4821 | case 0xb3: | |
4822 | case 0xb4: | |
4823 | case 0xb5: | |
4824 | case 0xb6: | |
4825 | case 0xb7: | |
cf648174 HZ |
4826 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4827 | ? ((opcode & 0x7) | ir.rex_b) | |
4828 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4829 | break; |
4830 | ||
a38bba38 | 4831 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
4832 | case 0xb9: |
4833 | case 0xba: | |
4834 | case 0xbb: | |
4835 | case 0xbc: | |
4836 | case 0xbd: | |
4837 | case 0xbe: | |
4838 | case 0xbf: | |
cf648174 | 4839 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4840 | break; |
4841 | ||
a38bba38 | 4842 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
4843 | case 0x92: |
4844 | case 0x93: | |
4845 | case 0x94: | |
4846 | case 0x95: | |
4847 | case 0x96: | |
4848 | case 0x97: | |
cf648174 HZ |
4849 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4850 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4851 | break; |
4852 | ||
a38bba38 | 4853 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
4854 | case 0x87: |
4855 | if ((opcode & 1) == 0) | |
4856 | ir.ot = OT_BYTE; | |
4857 | else | |
4858 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4859 | if (i386_record_modrm (&ir)) |
4860 | return -1; | |
7ad10968 HZ |
4861 | if (ir.mod == 3) |
4862 | { | |
86839d38 | 4863 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4864 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4865 | ir.rm &= 0x3; | |
4866 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4867 | } |
4868 | else | |
4869 | { | |
4870 | if (i386_record_lea_modrm (&ir)) | |
4871 | return -1; | |
4872 | } | |
cf648174 HZ |
4873 | ir.reg |= rex_r; |
4874 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4875 | ir.reg &= 0x3; |
cf648174 | 4876 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4877 | break; |
4878 | ||
a38bba38 MS |
4879 | case 0xc4: /* les Gv */ |
4880 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
4881 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4882 | { | |
4883 | ir.addr -= 1; | |
4884 | goto no_support; | |
4885 | } | |
d3f323f3 | 4886 | /* FALLTHROUGH */ |
a38bba38 MS |
4887 | case 0x0fb2: /* lss Gv */ |
4888 | case 0x0fb4: /* lfs Gv */ | |
4889 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
4890 | if (i386_record_modrm (&ir)) |
4891 | return -1; | |
4892 | if (ir.mod == 3) | |
4893 | { | |
4894 | if (opcode > 0xff) | |
4895 | ir.addr -= 3; | |
4896 | else | |
4897 | ir.addr -= 2; | |
4898 | opcode = opcode << 8 | ir.modrm; | |
4899 | goto no_support; | |
4900 | } | |
7ad10968 HZ |
4901 | switch (opcode) |
4902 | { | |
a38bba38 | 4903 | case 0xc4: /* les Gv */ |
425b824a | 4904 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 4905 | break; |
a38bba38 | 4906 | case 0xc5: /* lds Gv */ |
425b824a | 4907 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 4908 | break; |
a38bba38 | 4909 | case 0x0fb2: /* lss Gv */ |
425b824a | 4910 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 4911 | break; |
a38bba38 | 4912 | case 0x0fb4: /* lfs Gv */ |
425b824a | 4913 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 4914 | break; |
a38bba38 | 4915 | case 0x0fb5: /* lgs Gv */ |
425b824a | 4916 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4917 | break; |
4918 | } | |
425b824a | 4919 | I386_RECORD_ARCH_LIST_ADD_REG (regnum); |
cf648174 HZ |
4920 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4921 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4922 | break; |
4923 | ||
a38bba38 | 4924 | case 0xc0: /* shifts */ |
7ad10968 HZ |
4925 | case 0xc1: |
4926 | case 0xd0: | |
4927 | case 0xd1: | |
4928 | case 0xd2: | |
4929 | case 0xd3: | |
4930 | if ((opcode & 1) == 0) | |
4931 | ir.ot = OT_BYTE; | |
4932 | else | |
4933 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4934 | if (i386_record_modrm (&ir)) |
4935 | return -1; | |
7ad10968 HZ |
4936 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4937 | { | |
4938 | if (i386_record_lea_modrm (&ir)) | |
4939 | return -1; | |
4940 | } | |
4941 | else | |
4942 | { | |
cf648174 HZ |
4943 | ir.rm |= ir.rex_b; |
4944 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4945 | ir.rm &= 0x3; |
cf648174 | 4946 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4947 | } |
cf648174 | 4948 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4949 | break; |
4950 | ||
4951 | case 0x0fa4: | |
4952 | case 0x0fa5: | |
4953 | case 0x0fac: | |
4954 | case 0x0fad: | |
4955 | if (i386_record_modrm (&ir)) | |
4956 | return -1; | |
4957 | if (ir.mod == 3) | |
4958 | { | |
4959 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4960 | return -1; | |
4961 | } | |
4962 | else | |
4963 | { | |
4964 | if (i386_record_lea_modrm (&ir)) | |
4965 | return -1; | |
4966 | } | |
4967 | break; | |
4968 | ||
a38bba38 | 4969 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
4970 | case 0xd9: |
4971 | case 0xda: | |
4972 | case 0xdb: | |
4973 | case 0xdc: | |
4974 | case 0xdd: | |
4975 | case 0xde: | |
4976 | case 0xdf: | |
4977 | if (i386_record_modrm (&ir)) | |
4978 | return -1; | |
4979 | ir.reg |= ((opcode & 7) << 3); | |
4980 | if (ir.mod != 3) | |
4981 | { | |
1777feb0 | 4982 | /* Memory. */ |
955db0c0 | 4983 | uint64_t addr64; |
7ad10968 | 4984 | |
955db0c0 | 4985 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
4986 | return -1; |
4987 | switch (ir.reg) | |
4988 | { | |
7ad10968 | 4989 | case 0x02: |
0289bdd7 MS |
4990 | case 0x12: |
4991 | case 0x22: | |
4992 | case 0x32: | |
4993 | /* For fcom, ficom nothing to do. */ | |
4994 | break; | |
7ad10968 | 4995 | case 0x03: |
0289bdd7 MS |
4996 | case 0x13: |
4997 | case 0x23: | |
4998 | case 0x33: | |
4999 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
5000 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5001 | return -1; | |
5002 | break; | |
5003 | case 0x00: | |
5004 | case 0x01: | |
7ad10968 HZ |
5005 | case 0x04: |
5006 | case 0x05: | |
5007 | case 0x06: | |
5008 | case 0x07: | |
5009 | case 0x10: | |
5010 | case 0x11: | |
7ad10968 HZ |
5011 | case 0x14: |
5012 | case 0x15: | |
5013 | case 0x16: | |
5014 | case 0x17: | |
5015 | case 0x20: | |
5016 | case 0x21: | |
7ad10968 HZ |
5017 | case 0x24: |
5018 | case 0x25: | |
5019 | case 0x26: | |
5020 | case 0x27: | |
5021 | case 0x30: | |
5022 | case 0x31: | |
7ad10968 HZ |
5023 | case 0x34: |
5024 | case 0x35: | |
5025 | case 0x36: | |
5026 | case 0x37: | |
0289bdd7 MS |
5027 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
5028 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
5029 | of code, always affects st(0) register. */ | |
5030 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5031 | return -1; | |
7ad10968 HZ |
5032 | break; |
5033 | case 0x08: | |
5034 | case 0x0a: | |
5035 | case 0x0b: | |
5036 | case 0x18: | |
5037 | case 0x19: | |
5038 | case 0x1a: | |
5039 | case 0x1b: | |
0289bdd7 | 5040 | case 0x1d: |
7ad10968 HZ |
5041 | case 0x28: |
5042 | case 0x29: | |
5043 | case 0x2a: | |
5044 | case 0x2b: | |
5045 | case 0x38: | |
5046 | case 0x39: | |
5047 | case 0x3a: | |
5048 | case 0x3b: | |
0289bdd7 MS |
5049 | case 0x3c: |
5050 | case 0x3d: | |
7ad10968 HZ |
5051 | switch (ir.reg & 7) |
5052 | { | |
5053 | case 0: | |
0289bdd7 MS |
5054 | /* Handling fld, fild. */ |
5055 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5056 | return -1; | |
7ad10968 HZ |
5057 | break; |
5058 | case 1: | |
5059 | switch (ir.reg >> 4) | |
5060 | { | |
5061 | case 0: | |
955db0c0 | 5062 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
5063 | return -1; |
5064 | break; | |
5065 | case 2: | |
955db0c0 | 5066 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
5067 | return -1; |
5068 | break; | |
5069 | case 3: | |
0289bdd7 | 5070 | break; |
7ad10968 | 5071 | default: |
955db0c0 | 5072 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5073 | return -1; |
5074 | break; | |
5075 | } | |
5076 | break; | |
5077 | default: | |
5078 | switch (ir.reg >> 4) | |
5079 | { | |
5080 | case 0: | |
955db0c0 | 5081 | if (record_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
5082 | return -1; |
5083 | if (3 == (ir.reg & 7)) | |
5084 | { | |
5085 | /* For fstp m32fp. */ | |
5086 | if (i386_record_floats (gdbarch, &ir, | |
5087 | I386_SAVE_FPU_REGS)) | |
5088 | return -1; | |
5089 | } | |
5090 | break; | |
7ad10968 | 5091 | case 1: |
955db0c0 | 5092 | if (record_arch_list_add_mem (addr64, 4)) |
7ad10968 | 5093 | return -1; |
0289bdd7 MS |
5094 | if ((3 == (ir.reg & 7)) |
5095 | || (5 == (ir.reg & 7)) | |
5096 | || (7 == (ir.reg & 7))) | |
5097 | { | |
5098 | /* For fstp insn. */ | |
5099 | if (i386_record_floats (gdbarch, &ir, | |
5100 | I386_SAVE_FPU_REGS)) | |
5101 | return -1; | |
5102 | } | |
7ad10968 HZ |
5103 | break; |
5104 | case 2: | |
955db0c0 | 5105 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5106 | return -1; |
0289bdd7 MS |
5107 | if (3 == (ir.reg & 7)) |
5108 | { | |
5109 | /* For fstp m64fp. */ | |
5110 | if (i386_record_floats (gdbarch, &ir, | |
5111 | I386_SAVE_FPU_REGS)) | |
5112 | return -1; | |
5113 | } | |
7ad10968 HZ |
5114 | break; |
5115 | case 3: | |
0289bdd7 MS |
5116 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
5117 | { | |
5118 | /* For fistp, fbld, fild, fbstp. */ | |
5119 | if (i386_record_floats (gdbarch, &ir, | |
5120 | I386_SAVE_FPU_REGS)) | |
5121 | return -1; | |
5122 | } | |
5123 | /* Fall through */ | |
7ad10968 | 5124 | default: |
955db0c0 | 5125 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
5126 | return -1; |
5127 | break; | |
5128 | } | |
5129 | break; | |
5130 | } | |
5131 | break; | |
5132 | case 0x0c: | |
0289bdd7 MS |
5133 | /* Insn fldenv. */ |
5134 | if (i386_record_floats (gdbarch, &ir, | |
5135 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5136 | return -1; | |
5137 | break; | |
7ad10968 | 5138 | case 0x0d: |
0289bdd7 MS |
5139 | /* Insn fldcw. */ |
5140 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
5141 | return -1; | |
5142 | break; | |
7ad10968 | 5143 | case 0x2c: |
0289bdd7 MS |
5144 | /* Insn frstor. */ |
5145 | if (i386_record_floats (gdbarch, &ir, | |
5146 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5147 | return -1; | |
7ad10968 HZ |
5148 | break; |
5149 | case 0x0e: | |
5150 | if (ir.dflag) | |
5151 | { | |
955db0c0 | 5152 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
5153 | return -1; |
5154 | } | |
5155 | else | |
5156 | { | |
955db0c0 | 5157 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
5158 | return -1; |
5159 | } | |
5160 | break; | |
5161 | case 0x0f: | |
5162 | case 0x2f: | |
955db0c0 | 5163 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 5164 | return -1; |
0289bdd7 MS |
5165 | /* Insn fstp, fbstp. */ |
5166 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5167 | return -1; | |
7ad10968 HZ |
5168 | break; |
5169 | case 0x1f: | |
5170 | case 0x3e: | |
955db0c0 | 5171 | if (record_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
5172 | return -1; |
5173 | break; | |
5174 | case 0x2e: | |
5175 | if (ir.dflag) | |
5176 | { | |
955db0c0 | 5177 | if (record_arch_list_add_mem (addr64, 28)) |
7ad10968 | 5178 | return -1; |
955db0c0 | 5179 | addr64 += 28; |
7ad10968 HZ |
5180 | } |
5181 | else | |
5182 | { | |
955db0c0 | 5183 | if (record_arch_list_add_mem (addr64, 14)) |
7ad10968 | 5184 | return -1; |
955db0c0 | 5185 | addr64 += 14; |
7ad10968 | 5186 | } |
955db0c0 | 5187 | if (record_arch_list_add_mem (addr64, 80)) |
7ad10968 | 5188 | return -1; |
0289bdd7 MS |
5189 | /* Insn fsave. */ |
5190 | if (i386_record_floats (gdbarch, &ir, | |
5191 | I386_SAVE_FPU_ENV_REG_STACK)) | |
5192 | return -1; | |
7ad10968 HZ |
5193 | break; |
5194 | case 0x3f: | |
955db0c0 | 5195 | if (record_arch_list_add_mem (addr64, 8)) |
7ad10968 | 5196 | return -1; |
0289bdd7 MS |
5197 | /* Insn fistp. */ |
5198 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5199 | return -1; | |
7ad10968 HZ |
5200 | break; |
5201 | default: | |
5202 | ir.addr -= 2; | |
5203 | opcode = opcode << 8 | ir.modrm; | |
5204 | goto no_support; | |
5205 | break; | |
5206 | } | |
5207 | } | |
0289bdd7 MS |
5208 | /* Opcode is an extension of modR/M byte. */ |
5209 | else | |
5210 | { | |
5211 | switch (opcode) | |
5212 | { | |
5213 | case 0xd8: | |
5214 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
5215 | return -1; | |
5216 | break; | |
5217 | case 0xd9: | |
5218 | if (0x0c == (ir.modrm >> 4)) | |
5219 | { | |
5220 | if ((ir.modrm & 0x0f) <= 7) | |
5221 | { | |
5222 | if (i386_record_floats (gdbarch, &ir, | |
5223 | I386_SAVE_FPU_REGS)) | |
5224 | return -1; | |
5225 | } | |
5226 | else | |
5227 | { | |
5228 | if (i386_record_floats (gdbarch, &ir, | |
5229 | I387_ST0_REGNUM (tdep))) | |
5230 | return -1; | |
5231 | /* If only st(0) is changing, then we have already | |
5232 | recorded. */ | |
5233 | if ((ir.modrm & 0x0f) - 0x08) | |
5234 | { | |
5235 | if (i386_record_floats (gdbarch, &ir, | |
5236 | I387_ST0_REGNUM (tdep) + | |
5237 | ((ir.modrm & 0x0f) - 0x08))) | |
5238 | return -1; | |
5239 | } | |
5240 | } | |
5241 | } | |
5242 | else | |
5243 | { | |
5244 | switch (ir.modrm) | |
5245 | { | |
5246 | case 0xe0: | |
5247 | case 0xe1: | |
5248 | case 0xf0: | |
5249 | case 0xf5: | |
5250 | case 0xf8: | |
5251 | case 0xfa: | |
5252 | case 0xfc: | |
5253 | case 0xfe: | |
5254 | case 0xff: | |
5255 | if (i386_record_floats (gdbarch, &ir, | |
5256 | I387_ST0_REGNUM (tdep))) | |
5257 | return -1; | |
5258 | break; | |
5259 | case 0xf1: | |
5260 | case 0xf2: | |
5261 | case 0xf3: | |
5262 | case 0xf4: | |
5263 | case 0xf6: | |
5264 | case 0xf7: | |
5265 | case 0xe8: | |
5266 | case 0xe9: | |
5267 | case 0xea: | |
5268 | case 0xeb: | |
5269 | case 0xec: | |
5270 | case 0xed: | |
5271 | case 0xee: | |
5272 | case 0xf9: | |
5273 | case 0xfb: | |
5274 | if (i386_record_floats (gdbarch, &ir, | |
5275 | I386_SAVE_FPU_REGS)) | |
5276 | return -1; | |
5277 | break; | |
5278 | case 0xfd: | |
5279 | if (i386_record_floats (gdbarch, &ir, | |
5280 | I387_ST0_REGNUM (tdep))) | |
5281 | return -1; | |
5282 | if (i386_record_floats (gdbarch, &ir, | |
5283 | I387_ST0_REGNUM (tdep) + 1)) | |
5284 | return -1; | |
5285 | break; | |
5286 | } | |
5287 | } | |
5288 | break; | |
5289 | case 0xda: | |
5290 | if (0xe9 == ir.modrm) | |
5291 | { | |
5292 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5293 | return -1; | |
5294 | } | |
5295 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5296 | { | |
5297 | if (i386_record_floats (gdbarch, &ir, | |
5298 | I387_ST0_REGNUM (tdep))) | |
5299 | return -1; | |
5300 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5301 | { | |
5302 | if (i386_record_floats (gdbarch, &ir, | |
5303 | I387_ST0_REGNUM (tdep) + | |
5304 | (ir.modrm & 0x0f))) | |
5305 | return -1; | |
5306 | } | |
5307 | else if ((ir.modrm & 0x0f) - 0x08) | |
5308 | { | |
5309 | if (i386_record_floats (gdbarch, &ir, | |
5310 | I387_ST0_REGNUM (tdep) + | |
5311 | ((ir.modrm & 0x0f) - 0x08))) | |
5312 | return -1; | |
5313 | } | |
5314 | } | |
5315 | break; | |
5316 | case 0xdb: | |
5317 | if (0xe3 == ir.modrm) | |
5318 | { | |
5319 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
5320 | return -1; | |
5321 | } | |
5322 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
5323 | { | |
5324 | if (i386_record_floats (gdbarch, &ir, | |
5325 | I387_ST0_REGNUM (tdep))) | |
5326 | return -1; | |
5327 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
5328 | { | |
5329 | if (i386_record_floats (gdbarch, &ir, | |
5330 | I387_ST0_REGNUM (tdep) + | |
5331 | (ir.modrm & 0x0f))) | |
5332 | return -1; | |
5333 | } | |
5334 | else if ((ir.modrm & 0x0f) - 0x08) | |
5335 | { | |
5336 | if (i386_record_floats (gdbarch, &ir, | |
5337 | I387_ST0_REGNUM (tdep) + | |
5338 | ((ir.modrm & 0x0f) - 0x08))) | |
5339 | return -1; | |
5340 | } | |
5341 | } | |
5342 | break; | |
5343 | case 0xdc: | |
5344 | if ((0x0c == ir.modrm >> 4) | |
5345 | || (0x0d == ir.modrm >> 4) | |
5346 | || (0x0f == ir.modrm >> 4)) | |
5347 | { | |
5348 | if ((ir.modrm & 0x0f) <= 7) | |
5349 | { | |
5350 | if (i386_record_floats (gdbarch, &ir, | |
5351 | I387_ST0_REGNUM (tdep) + | |
5352 | (ir.modrm & 0x0f))) | |
5353 | return -1; | |
5354 | } | |
5355 | else | |
5356 | { | |
5357 | if (i386_record_floats (gdbarch, &ir, | |
5358 | I387_ST0_REGNUM (tdep) + | |
5359 | ((ir.modrm & 0x0f) - 0x08))) | |
5360 | return -1; | |
5361 | } | |
5362 | } | |
5363 | break; | |
5364 | case 0xdd: | |
5365 | if (0x0c == ir.modrm >> 4) | |
5366 | { | |
5367 | if (i386_record_floats (gdbarch, &ir, | |
5368 | I387_FTAG_REGNUM (tdep))) | |
5369 | return -1; | |
5370 | } | |
5371 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5372 | { | |
5373 | if ((ir.modrm & 0x0f) <= 7) | |
5374 | { | |
5375 | if (i386_record_floats (gdbarch, &ir, | |
5376 | I387_ST0_REGNUM (tdep) + | |
5377 | (ir.modrm & 0x0f))) | |
5378 | return -1; | |
5379 | } | |
5380 | else | |
5381 | { | |
5382 | if (i386_record_floats (gdbarch, &ir, | |
5383 | I386_SAVE_FPU_REGS)) | |
5384 | return -1; | |
5385 | } | |
5386 | } | |
5387 | break; | |
5388 | case 0xde: | |
5389 | if ((0x0c == ir.modrm >> 4) | |
5390 | || (0x0e == ir.modrm >> 4) | |
5391 | || (0x0f == ir.modrm >> 4) | |
5392 | || (0xd9 == ir.modrm)) | |
5393 | { | |
5394 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5395 | return -1; | |
5396 | } | |
5397 | break; | |
5398 | case 0xdf: | |
5399 | if (0xe0 == ir.modrm) | |
5400 | { | |
5401 | if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) | |
5402 | return -1; | |
5403 | } | |
5404 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
5405 | { | |
5406 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
5407 | return -1; | |
5408 | } | |
5409 | break; | |
5410 | } | |
5411 | } | |
7ad10968 | 5412 | break; |
7ad10968 | 5413 | /* string ops */ |
a38bba38 | 5414 | case 0xa4: /* movsS */ |
7ad10968 | 5415 | case 0xa5: |
a38bba38 | 5416 | case 0xaa: /* stosS */ |
7ad10968 | 5417 | case 0xab: |
a38bba38 | 5418 | case 0x6c: /* insS */ |
7ad10968 | 5419 | case 0x6d: |
cf648174 | 5420 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 5421 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
5422 | &addr); |
5423 | if (addr) | |
cf648174 | 5424 | { |
77d7dc92 HZ |
5425 | ULONGEST es, ds; |
5426 | ||
5427 | if ((opcode & 1) == 0) | |
5428 | ir.ot = OT_BYTE; | |
5429 | else | |
5430 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
5431 | regcache_raw_read_unsigned (ir.regcache, |
5432 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 5433 | &addr); |
77d7dc92 | 5434 | |
d7877f7e HZ |
5435 | regcache_raw_read_unsigned (ir.regcache, |
5436 | ir.regmap[X86_RECORD_ES_REGNUM], | |
5437 | &es); | |
5438 | regcache_raw_read_unsigned (ir.regcache, | |
5439 | ir.regmap[X86_RECORD_DS_REGNUM], | |
5440 | &ds); | |
5441 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
5442 | { |
5443 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
bb08c432 HZ |
5444 | if (record_memory_query) |
5445 | { | |
5446 | int q; | |
5447 | ||
5448 | target_terminal_ours (); | |
5449 | q = yquery (_("\ | |
5450 | Process record ignores the memory change of instruction at address %s\n\ | |
5451 | because it can't get the value of the segment register.\n\ | |
5452 | Do you want to stop the program?"), | |
5453 | paddress (gdbarch, ir.orig_addr)); | |
5454 | target_terminal_inferior (); | |
5455 | if (q) | |
5456 | return -1; | |
5457 | } | |
df61f520 HZ |
5458 | } |
5459 | else | |
5460 | { | |
648d0c8b | 5461 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 5462 | return -1; |
77d7dc92 HZ |
5463 | } |
5464 | ||
5465 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5466 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
5467 | if (opcode == 0xa4 || opcode == 0xa5) |
5468 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5469 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5470 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5471 | } | |
cf648174 | 5472 | break; |
7ad10968 | 5473 | |
a38bba38 | 5474 | case 0xa6: /* cmpsS */ |
cf648174 HZ |
5475 | case 0xa7: |
5476 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
5477 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
5478 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
5479 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5480 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5481 | break; |
5482 | ||
a38bba38 | 5483 | case 0xac: /* lodsS */ |
7ad10968 | 5484 | case 0xad: |
cf648174 HZ |
5485 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5486 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5487 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5488 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5489 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5490 | break; |
5491 | ||
a38bba38 | 5492 | case 0xae: /* scasS */ |
7ad10968 | 5493 | case 0xaf: |
cf648174 | 5494 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 5495 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5496 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5497 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5498 | break; |
5499 | ||
a38bba38 | 5500 | case 0x6e: /* outsS */ |
cf648174 HZ |
5501 | case 0x6f: |
5502 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 5503 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
5504 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5505 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5506 | break; |
5507 | ||
a38bba38 | 5508 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
5509 | case 0xe5: |
5510 | case 0xec: | |
5511 | case 0xed: | |
cf648174 HZ |
5512 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5513 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5514 | break; |
5515 | ||
5516 | case 0xe6: | |
5517 | case 0xe7: | |
5518 | case 0xee: | |
5519 | case 0xef: | |
5520 | break; | |
5521 | ||
5522 | /* control */ | |
a38bba38 MS |
5523 | case 0xc2: /* ret im */ |
5524 | case 0xc3: /* ret */ | |
cf648174 HZ |
5525 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5526 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5527 | break; | |
5528 | ||
a38bba38 MS |
5529 | case 0xca: /* lret im */ |
5530 | case 0xcb: /* lret */ | |
5531 | case 0xcf: /* iret */ | |
cf648174 HZ |
5532 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
5533 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
5534 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5535 | break; |
5536 | ||
a38bba38 | 5537 | case 0xe8: /* call im */ |
cf648174 HZ |
5538 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5539 | ir.dflag = 2; | |
5540 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5541 | return -1; | |
7ad10968 HZ |
5542 | break; |
5543 | ||
a38bba38 | 5544 | case 0x9a: /* lcall im */ |
cf648174 HZ |
5545 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5546 | { | |
5547 | ir.addr -= 1; | |
5548 | goto no_support; | |
5549 | } | |
5550 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
5551 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5552 | return -1; | |
7ad10968 HZ |
5553 | break; |
5554 | ||
a38bba38 MS |
5555 | case 0xe9: /* jmp im */ |
5556 | case 0xea: /* ljmp im */ | |
5557 | case 0xeb: /* jmp Jb */ | |
5558 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
5559 | case 0x71: |
5560 | case 0x72: | |
5561 | case 0x73: | |
5562 | case 0x74: | |
5563 | case 0x75: | |
5564 | case 0x76: | |
5565 | case 0x77: | |
5566 | case 0x78: | |
5567 | case 0x79: | |
5568 | case 0x7a: | |
5569 | case 0x7b: | |
5570 | case 0x7c: | |
5571 | case 0x7d: | |
5572 | case 0x7e: | |
5573 | case 0x7f: | |
a38bba38 | 5574 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
5575 | case 0x0f81: |
5576 | case 0x0f82: | |
5577 | case 0x0f83: | |
5578 | case 0x0f84: | |
5579 | case 0x0f85: | |
5580 | case 0x0f86: | |
5581 | case 0x0f87: | |
5582 | case 0x0f88: | |
5583 | case 0x0f89: | |
5584 | case 0x0f8a: | |
5585 | case 0x0f8b: | |
5586 | case 0x0f8c: | |
5587 | case 0x0f8d: | |
5588 | case 0x0f8e: | |
5589 | case 0x0f8f: | |
5590 | break; | |
5591 | ||
a38bba38 | 5592 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
5593 | case 0x0f91: |
5594 | case 0x0f92: | |
5595 | case 0x0f93: | |
5596 | case 0x0f94: | |
5597 | case 0x0f95: | |
5598 | case 0x0f96: | |
5599 | case 0x0f97: | |
5600 | case 0x0f98: | |
5601 | case 0x0f99: | |
5602 | case 0x0f9a: | |
5603 | case 0x0f9b: | |
5604 | case 0x0f9c: | |
5605 | case 0x0f9d: | |
5606 | case 0x0f9e: | |
5607 | case 0x0f9f: | |
cf648174 | 5608 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5609 | ir.ot = OT_BYTE; |
5610 | if (i386_record_modrm (&ir)) | |
5611 | return -1; | |
5612 | if (ir.mod == 3) | |
cf648174 HZ |
5613 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
5614 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
5615 | else |
5616 | { | |
5617 | if (i386_record_lea_modrm (&ir)) | |
5618 | return -1; | |
5619 | } | |
5620 | break; | |
5621 | ||
a38bba38 | 5622 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
5623 | case 0x0f41: |
5624 | case 0x0f42: | |
5625 | case 0x0f43: | |
5626 | case 0x0f44: | |
5627 | case 0x0f45: | |
5628 | case 0x0f46: | |
5629 | case 0x0f47: | |
5630 | case 0x0f48: | |
5631 | case 0x0f49: | |
5632 | case 0x0f4a: | |
5633 | case 0x0f4b: | |
5634 | case 0x0f4c: | |
5635 | case 0x0f4d: | |
5636 | case 0x0f4e: | |
5637 | case 0x0f4f: | |
5638 | if (i386_record_modrm (&ir)) | |
5639 | return -1; | |
cf648174 | 5640 | ir.reg |= rex_r; |
7ad10968 HZ |
5641 | if (ir.dflag == OT_BYTE) |
5642 | ir.reg &= 0x3; | |
cf648174 | 5643 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5644 | break; |
5645 | ||
5646 | /* flags */ | |
a38bba38 | 5647 | case 0x9c: /* pushf */ |
cf648174 HZ |
5648 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5649 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
5650 | ir.dflag = 2; | |
5651 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5652 | return -1; | |
7ad10968 HZ |
5653 | break; |
5654 | ||
a38bba38 | 5655 | case 0x9d: /* popf */ |
cf648174 HZ |
5656 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5657 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5658 | break; |
5659 | ||
a38bba38 | 5660 | case 0x9e: /* sahf */ |
cf648174 HZ |
5661 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5662 | { | |
5663 | ir.addr -= 1; | |
5664 | goto no_support; | |
5665 | } | |
d3f323f3 | 5666 | /* FALLTHROUGH */ |
a38bba38 MS |
5667 | case 0xf5: /* cmc */ |
5668 | case 0xf8: /* clc */ | |
5669 | case 0xf9: /* stc */ | |
5670 | case 0xfc: /* cld */ | |
5671 | case 0xfd: /* std */ | |
cf648174 | 5672 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5673 | break; |
5674 | ||
a38bba38 | 5675 | case 0x9f: /* lahf */ |
cf648174 HZ |
5676 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5677 | { | |
5678 | ir.addr -= 1; | |
5679 | goto no_support; | |
5680 | } | |
5681 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5682 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
5683 | break; |
5684 | ||
5685 | /* bit operations */ | |
a38bba38 | 5686 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
5687 | ir.ot = ir.dflag + OT_WORD; |
5688 | if (i386_record_modrm (&ir)) | |
5689 | return -1; | |
5690 | if (ir.reg < 4) | |
5691 | { | |
cf648174 | 5692 | ir.addr -= 2; |
7ad10968 HZ |
5693 | opcode = opcode << 8 | ir.modrm; |
5694 | goto no_support; | |
5695 | } | |
cf648174 | 5696 | if (ir.reg != 4) |
7ad10968 | 5697 | { |
cf648174 HZ |
5698 | if (ir.mod == 3) |
5699 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
5700 | else |
5701 | { | |
cf648174 | 5702 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
5703 | return -1; |
5704 | } | |
5705 | } | |
cf648174 | 5706 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5707 | break; |
5708 | ||
a38bba38 | 5709 | case 0x0fa3: /* bt Gv, Ev */ |
cf648174 HZ |
5710 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5711 | break; | |
5712 | ||
a38bba38 MS |
5713 | case 0x0fab: /* bts */ |
5714 | case 0x0fb3: /* btr */ | |
5715 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
5716 | ir.ot = ir.dflag + OT_WORD; |
5717 | if (i386_record_modrm (&ir)) | |
5718 | return -1; | |
5719 | if (ir.mod == 3) | |
5720 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
5721 | else | |
5722 | { | |
955db0c0 MS |
5723 | uint64_t addr64; |
5724 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
5725 | return -1; |
5726 | regcache_raw_read_unsigned (ir.regcache, | |
5727 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 5728 | &addr); |
cf648174 HZ |
5729 | switch (ir.dflag) |
5730 | { | |
5731 | case 0: | |
648d0c8b | 5732 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
5733 | break; |
5734 | case 1: | |
648d0c8b | 5735 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
5736 | break; |
5737 | case 2: | |
648d0c8b | 5738 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
5739 | break; |
5740 | } | |
955db0c0 | 5741 | if (record_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
5742 | return -1; |
5743 | if (i386_record_lea_modrm (&ir)) | |
5744 | return -1; | |
5745 | } | |
5746 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5747 | break; |
5748 | ||
a38bba38 MS |
5749 | case 0x0fbc: /* bsf */ |
5750 | case 0x0fbd: /* bsr */ | |
cf648174 HZ |
5751 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5752 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5753 | break; |
5754 | ||
5755 | /* bcd */ | |
a38bba38 MS |
5756 | case 0x27: /* daa */ |
5757 | case 0x2f: /* das */ | |
5758 | case 0x37: /* aaa */ | |
5759 | case 0x3f: /* aas */ | |
5760 | case 0xd4: /* aam */ | |
5761 | case 0xd5: /* aad */ | |
cf648174 HZ |
5762 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5763 | { | |
5764 | ir.addr -= 1; | |
5765 | goto no_support; | |
5766 | } | |
5767 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5768 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5769 | break; |
5770 | ||
5771 | /* misc */ | |
a38bba38 | 5772 | case 0x90: /* nop */ |
7ad10968 HZ |
5773 | if (prefixes & PREFIX_LOCK) |
5774 | { | |
5775 | ir.addr -= 1; | |
5776 | goto no_support; | |
5777 | } | |
5778 | break; | |
5779 | ||
a38bba38 | 5780 | case 0x9b: /* fwait */ |
425b824a | 5781 | if (target_read_memory (ir.addr, &opcode8, 1)) |
0289bdd7 MS |
5782 | { |
5783 | if (record_debug) | |
5784 | printf_unfiltered (_("Process record: error reading memory at " | |
5785 | "addr 0x%s len = 1.\n"), | |
5786 | paddress (gdbarch, ir.addr)); | |
5787 | return -1; | |
5788 | } | |
425b824a | 5789 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
5790 | ir.addr++; |
5791 | goto reswitch; | |
7ad10968 HZ |
5792 | break; |
5793 | ||
7ad10968 | 5794 | /* XXX */ |
a38bba38 | 5795 | case 0xcc: /* int3 */ |
a3c4230a | 5796 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
5797 | "int3.\n")); |
5798 | ir.addr -= 1; | |
5799 | goto no_support; | |
5800 | break; | |
5801 | ||
7ad10968 | 5802 | /* XXX */ |
a38bba38 | 5803 | case 0xcd: /* int */ |
7ad10968 HZ |
5804 | { |
5805 | int ret; | |
425b824a MS |
5806 | uint8_t interrupt; |
5807 | if (target_read_memory (ir.addr, &interrupt, 1)) | |
7ad10968 HZ |
5808 | { |
5809 | if (record_debug) | |
5810 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
5811 | "at addr %s len = 1.\n"), |
5812 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5813 | return -1; |
5814 | } | |
5815 | ir.addr++; | |
425b824a | 5816 | if (interrupt != 0x80 |
a3c4230a | 5817 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 5818 | { |
a3c4230a | 5819 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 5820 | "instruction int 0x%02x.\n"), |
425b824a | 5821 | interrupt); |
7ad10968 HZ |
5822 | ir.addr -= 2; |
5823 | goto no_support; | |
5824 | } | |
a3c4230a | 5825 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
5826 | if (ret) |
5827 | return ret; | |
5828 | } | |
5829 | break; | |
5830 | ||
7ad10968 | 5831 | /* XXX */ |
a38bba38 | 5832 | case 0xce: /* into */ |
a3c4230a | 5833 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5834 | "instruction into.\n")); |
5835 | ir.addr -= 1; | |
5836 | goto no_support; | |
5837 | break; | |
5838 | ||
a38bba38 MS |
5839 | case 0xfa: /* cli */ |
5840 | case 0xfb: /* sti */ | |
7ad10968 HZ |
5841 | break; |
5842 | ||
a38bba38 | 5843 | case 0x62: /* bound */ |
a3c4230a | 5844 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5845 | "instruction bound.\n")); |
5846 | ir.addr -= 1; | |
5847 | goto no_support; | |
5848 | break; | |
5849 | ||
a38bba38 | 5850 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
5851 | case 0x0fc9: |
5852 | case 0x0fca: | |
5853 | case 0x0fcb: | |
5854 | case 0x0fcc: | |
5855 | case 0x0fcd: | |
5856 | case 0x0fce: | |
5857 | case 0x0fcf: | |
cf648174 | 5858 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
5859 | break; |
5860 | ||
a38bba38 | 5861 | case 0xd6: /* salc */ |
cf648174 HZ |
5862 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5863 | { | |
5864 | ir.addr -= 1; | |
5865 | goto no_support; | |
5866 | } | |
5867 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5868 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5869 | break; |
5870 | ||
a38bba38 MS |
5871 | case 0xe0: /* loopnz */ |
5872 | case 0xe1: /* loopz */ | |
5873 | case 0xe2: /* loop */ | |
5874 | case 0xe3: /* jecxz */ | |
cf648174 HZ |
5875 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
5876 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5877 | break; |
5878 | ||
a38bba38 | 5879 | case 0x0f30: /* wrmsr */ |
a3c4230a | 5880 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5881 | "instruction wrmsr.\n")); |
5882 | ir.addr -= 2; | |
5883 | goto no_support; | |
5884 | break; | |
5885 | ||
a38bba38 | 5886 | case 0x0f32: /* rdmsr */ |
a3c4230a | 5887 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5888 | "instruction rdmsr.\n")); |
5889 | ir.addr -= 2; | |
5890 | goto no_support; | |
5891 | break; | |
5892 | ||
a38bba38 | 5893 | case 0x0f31: /* rdtsc */ |
f8c4f480 HZ |
5894 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5895 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5896 | break; |
5897 | ||
a38bba38 | 5898 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
5899 | { |
5900 | int ret; | |
cf648174 HZ |
5901 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5902 | { | |
5903 | ir.addr -= 2; | |
5904 | goto no_support; | |
5905 | } | |
a3c4230a | 5906 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 5907 | { |
a3c4230a | 5908 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5909 | "instruction sysenter.\n")); |
5910 | ir.addr -= 2; | |
5911 | goto no_support; | |
5912 | } | |
a3c4230a | 5913 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
5914 | if (ret) |
5915 | return ret; | |
5916 | } | |
5917 | break; | |
5918 | ||
a38bba38 | 5919 | case 0x0f35: /* sysexit */ |
a3c4230a | 5920 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5921 | "instruction sysexit.\n")); |
5922 | ir.addr -= 2; | |
5923 | goto no_support; | |
5924 | break; | |
5925 | ||
a38bba38 | 5926 | case 0x0f05: /* syscall */ |
cf648174 HZ |
5927 | { |
5928 | int ret; | |
a3c4230a | 5929 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 5930 | { |
a3c4230a | 5931 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5932 | "instruction syscall.\n")); |
5933 | ir.addr -= 2; | |
5934 | goto no_support; | |
5935 | } | |
a3c4230a | 5936 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
5937 | if (ret) |
5938 | return ret; | |
5939 | } | |
5940 | break; | |
5941 | ||
a38bba38 | 5942 | case 0x0f07: /* sysret */ |
a3c4230a | 5943 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
5944 | "instruction sysret.\n")); |
5945 | ir.addr -= 2; | |
5946 | goto no_support; | |
5947 | break; | |
5948 | ||
a38bba38 | 5949 | case 0x0fa2: /* cpuid */ |
cf648174 HZ |
5950 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5951 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5952 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5953 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5954 | break; |
5955 | ||
a38bba38 | 5956 | case 0xf4: /* hlt */ |
a3c4230a | 5957 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
5958 | "instruction hlt.\n")); |
5959 | ir.addr -= 1; | |
5960 | goto no_support; | |
5961 | break; | |
5962 | ||
5963 | case 0x0f00: | |
5964 | if (i386_record_modrm (&ir)) | |
5965 | return -1; | |
5966 | switch (ir.reg) | |
5967 | { | |
a38bba38 MS |
5968 | case 0: /* sldt */ |
5969 | case 1: /* str */ | |
7ad10968 | 5970 | if (ir.mod == 3) |
cf648174 | 5971 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5972 | else |
5973 | { | |
5974 | ir.ot = OT_WORD; | |
5975 | if (i386_record_lea_modrm (&ir)) | |
5976 | return -1; | |
5977 | } | |
5978 | break; | |
a38bba38 MS |
5979 | case 2: /* lldt */ |
5980 | case 3: /* ltr */ | |
7ad10968 | 5981 | break; |
a38bba38 MS |
5982 | case 4: /* verr */ |
5983 | case 5: /* verw */ | |
cf648174 | 5984 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5985 | break; |
5986 | default: | |
5987 | ir.addr -= 3; | |
5988 | opcode = opcode << 8 | ir.modrm; | |
5989 | goto no_support; | |
5990 | break; | |
5991 | } | |
5992 | break; | |
5993 | ||
5994 | case 0x0f01: | |
5995 | if (i386_record_modrm (&ir)) | |
5996 | return -1; | |
5997 | switch (ir.reg) | |
5998 | { | |
a38bba38 | 5999 | case 0: /* sgdt */ |
7ad10968 | 6000 | { |
955db0c0 | 6001 | uint64_t addr64; |
7ad10968 HZ |
6002 | |
6003 | if (ir.mod == 3) | |
6004 | { | |
6005 | ir.addr -= 3; | |
6006 | opcode = opcode << 8 | ir.modrm; | |
6007 | goto no_support; | |
6008 | } | |
d7877f7e | 6009 | if (ir.override >= 0) |
7ad10968 | 6010 | { |
bb08c432 HZ |
6011 | if (record_memory_query) |
6012 | { | |
6013 | int q; | |
6014 | ||
6015 | target_terminal_ours (); | |
6016 | q = yquery (_("\ | |
6017 | Process record ignores the memory change of instruction at address %s\n\ | |
6018 | because it can't get the value of the segment register.\n\ | |
6019 | Do you want to stop the program?"), | |
6020 | paddress (gdbarch, ir.orig_addr)); | |
6021 | target_terminal_inferior (); | |
6022 | if (q) | |
6023 | return -1; | |
6024 | } | |
7ad10968 HZ |
6025 | } |
6026 | else | |
6027 | { | |
955db0c0 | 6028 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6029 | return -1; |
955db0c0 | 6030 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6031 | return -1; |
955db0c0 | 6032 | addr64 += 2; |
cf648174 HZ |
6033 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6034 | { | |
955db0c0 | 6035 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6036 | return -1; |
6037 | } | |
6038 | else | |
6039 | { | |
955db0c0 | 6040 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6041 | return -1; |
6042 | } | |
7ad10968 HZ |
6043 | } |
6044 | } | |
6045 | break; | |
6046 | case 1: | |
6047 | if (ir.mod == 3) | |
6048 | { | |
6049 | switch (ir.rm) | |
6050 | { | |
a38bba38 | 6051 | case 0: /* monitor */ |
7ad10968 | 6052 | break; |
a38bba38 | 6053 | case 1: /* mwait */ |
cf648174 | 6054 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6055 | break; |
6056 | default: | |
6057 | ir.addr -= 3; | |
6058 | opcode = opcode << 8 | ir.modrm; | |
6059 | goto no_support; | |
6060 | break; | |
6061 | } | |
6062 | } | |
6063 | else | |
6064 | { | |
6065 | /* sidt */ | |
d7877f7e | 6066 | if (ir.override >= 0) |
7ad10968 | 6067 | { |
bb08c432 HZ |
6068 | if (record_memory_query) |
6069 | { | |
6070 | int q; | |
6071 | ||
6072 | target_terminal_ours (); | |
6073 | q = yquery (_("\ | |
6074 | Process record ignores the memory change of instruction at address %s\n\ | |
6075 | because it can't get the value of the segment register.\n\ | |
6076 | Do you want to stop the program?"), | |
6077 | paddress (gdbarch, ir.orig_addr)); | |
6078 | target_terminal_inferior (); | |
6079 | if (q) | |
6080 | return -1; | |
6081 | } | |
7ad10968 HZ |
6082 | } |
6083 | else | |
6084 | { | |
955db0c0 | 6085 | uint64_t addr64; |
7ad10968 | 6086 | |
955db0c0 | 6087 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 6088 | return -1; |
955db0c0 | 6089 | if (record_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6090 | return -1; |
955db0c0 | 6091 | addr64 += 2; |
cf648174 HZ |
6092 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6093 | { | |
955db0c0 | 6094 | if (record_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
6095 | return -1; |
6096 | } | |
6097 | else | |
6098 | { | |
955db0c0 | 6099 | if (record_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
6100 | return -1; |
6101 | } | |
7ad10968 HZ |
6102 | } |
6103 | } | |
6104 | break; | |
a38bba38 | 6105 | case 2: /* lgdt */ |
3800e645 MS |
6106 | if (ir.mod == 3) |
6107 | { | |
6108 | /* xgetbv */ | |
6109 | if (ir.rm == 0) | |
6110 | { | |
6111 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6112 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6113 | break; | |
6114 | } | |
6115 | /* xsetbv */ | |
6116 | else if (ir.rm == 1) | |
6117 | break; | |
6118 | } | |
a38bba38 | 6119 | case 3: /* lidt */ |
7ad10968 HZ |
6120 | if (ir.mod == 3) |
6121 | { | |
6122 | ir.addr -= 3; | |
6123 | opcode = opcode << 8 | ir.modrm; | |
6124 | goto no_support; | |
6125 | } | |
6126 | break; | |
a38bba38 | 6127 | case 4: /* smsw */ |
7ad10968 HZ |
6128 | if (ir.mod == 3) |
6129 | { | |
cf648174 | 6130 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
6131 | return -1; |
6132 | } | |
6133 | else | |
6134 | { | |
6135 | ir.ot = OT_WORD; | |
6136 | if (i386_record_lea_modrm (&ir)) | |
6137 | return -1; | |
6138 | } | |
cf648174 | 6139 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6140 | break; |
a38bba38 | 6141 | case 6: /* lmsw */ |
cf648174 HZ |
6142 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6143 | break; | |
a38bba38 | 6144 | case 7: /* invlpg */ |
cf648174 HZ |
6145 | if (ir.mod == 3) |
6146 | { | |
6147 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
6148 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
6149 | else | |
6150 | { | |
6151 | ir.addr -= 3; | |
6152 | opcode = opcode << 8 | ir.modrm; | |
6153 | goto no_support; | |
6154 | } | |
6155 | } | |
6156 | else | |
6157 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6158 | break; | |
6159 | default: | |
6160 | ir.addr -= 3; | |
6161 | opcode = opcode << 8 | ir.modrm; | |
6162 | goto no_support; | |
7ad10968 HZ |
6163 | break; |
6164 | } | |
6165 | break; | |
6166 | ||
a38bba38 MS |
6167 | case 0x0f08: /* invd */ |
6168 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
6169 | break; |
6170 | ||
a38bba38 | 6171 | case 0x63: /* arpl */ |
7ad10968 HZ |
6172 | if (i386_record_modrm (&ir)) |
6173 | return -1; | |
cf648174 HZ |
6174 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
6175 | { | |
6176 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
6177 | ? (ir.reg | rex_r) : ir.rm); | |
6178 | } | |
7ad10968 | 6179 | else |
cf648174 HZ |
6180 | { |
6181 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
6182 | if (i386_record_lea_modrm (&ir)) | |
6183 | return -1; | |
6184 | } | |
6185 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
6186 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6187 | break; |
6188 | ||
a38bba38 MS |
6189 | case 0x0f02: /* lar */ |
6190 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
6191 | if (i386_record_modrm (&ir)) |
6192 | return -1; | |
cf648174 HZ |
6193 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6194 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6195 | break; |
6196 | ||
6197 | case 0x0f18: | |
cf648174 HZ |
6198 | if (i386_record_modrm (&ir)) |
6199 | return -1; | |
6200 | if (ir.mod == 3 && ir.reg == 3) | |
6201 | { | |
6202 | ir.addr -= 3; | |
6203 | opcode = opcode << 8 | ir.modrm; | |
6204 | goto no_support; | |
6205 | } | |
7ad10968 HZ |
6206 | break; |
6207 | ||
7ad10968 HZ |
6208 | case 0x0f19: |
6209 | case 0x0f1a: | |
6210 | case 0x0f1b: | |
6211 | case 0x0f1c: | |
6212 | case 0x0f1d: | |
6213 | case 0x0f1e: | |
6214 | case 0x0f1f: | |
a38bba38 | 6215 | /* nop (multi byte) */ |
7ad10968 HZ |
6216 | break; |
6217 | ||
a38bba38 MS |
6218 | case 0x0f20: /* mov reg, crN */ |
6219 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
6220 | if (i386_record_modrm (&ir)) |
6221 | return -1; | |
6222 | if ((ir.modrm & 0xc0) != 0xc0) | |
6223 | { | |
cf648174 | 6224 | ir.addr -= 3; |
7ad10968 HZ |
6225 | opcode = opcode << 8 | ir.modrm; |
6226 | goto no_support; | |
6227 | } | |
6228 | switch (ir.reg) | |
6229 | { | |
6230 | case 0: | |
6231 | case 2: | |
6232 | case 3: | |
6233 | case 4: | |
6234 | case 8: | |
6235 | if (opcode & 2) | |
cf648174 | 6236 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6237 | else |
cf648174 | 6238 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6239 | break; |
6240 | default: | |
cf648174 | 6241 | ir.addr -= 3; |
7ad10968 HZ |
6242 | opcode = opcode << 8 | ir.modrm; |
6243 | goto no_support; | |
6244 | break; | |
6245 | } | |
6246 | break; | |
6247 | ||
a38bba38 MS |
6248 | case 0x0f21: /* mov reg, drN */ |
6249 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
6250 | if (i386_record_modrm (&ir)) |
6251 | return -1; | |
6252 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
6253 | || ir.reg == 5 || ir.reg >= 8) | |
6254 | { | |
cf648174 | 6255 | ir.addr -= 3; |
7ad10968 HZ |
6256 | opcode = opcode << 8 | ir.modrm; |
6257 | goto no_support; | |
6258 | } | |
6259 | if (opcode & 2) | |
cf648174 | 6260 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 6261 | else |
cf648174 | 6262 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6263 | break; |
6264 | ||
a38bba38 | 6265 | case 0x0f06: /* clts */ |
cf648174 | 6266 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6267 | break; |
6268 | ||
a3c4230a HZ |
6269 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
6270 | ||
6271 | case 0x0f0d: /* 3DNow! prefetch */ | |
6272 | break; | |
6273 | ||
6274 | case 0x0f0e: /* 3DNow! femms */ | |
6275 | case 0x0f77: /* emms */ | |
6276 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
6277 | goto no_support; | |
6278 | record_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); | |
6279 | break; | |
6280 | ||
6281 | case 0x0f0f: /* 3DNow! data */ | |
6282 | if (i386_record_modrm (&ir)) | |
6283 | return -1; | |
6284 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6285 | { | |
6286 | printf_unfiltered (_("Process record: error reading memory at " | |
6287 | "addr %s len = 1.\n"), | |
6288 | paddress (gdbarch, ir.addr)); | |
6289 | return -1; | |
6290 | } | |
6291 | ir.addr++; | |
6292 | switch (opcode8) | |
6293 | { | |
6294 | case 0x0c: /* 3DNow! pi2fw */ | |
6295 | case 0x0d: /* 3DNow! pi2fd */ | |
6296 | case 0x1c: /* 3DNow! pf2iw */ | |
6297 | case 0x1d: /* 3DNow! pf2id */ | |
6298 | case 0x8a: /* 3DNow! pfnacc */ | |
6299 | case 0x8e: /* 3DNow! pfpnacc */ | |
6300 | case 0x90: /* 3DNow! pfcmpge */ | |
6301 | case 0x94: /* 3DNow! pfmin */ | |
6302 | case 0x96: /* 3DNow! pfrcp */ | |
6303 | case 0x97: /* 3DNow! pfrsqrt */ | |
6304 | case 0x9a: /* 3DNow! pfsub */ | |
6305 | case 0x9e: /* 3DNow! pfadd */ | |
6306 | case 0xa0: /* 3DNow! pfcmpgt */ | |
6307 | case 0xa4: /* 3DNow! pfmax */ | |
6308 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
6309 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
6310 | case 0xaa: /* 3DNow! pfsubr */ | |
6311 | case 0xae: /* 3DNow! pfacc */ | |
6312 | case 0xb0: /* 3DNow! pfcmpeq */ | |
6313 | case 0xb4: /* 3DNow! pfmul */ | |
6314 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
6315 | case 0xb7: /* 3DNow! pmulhrw */ | |
6316 | case 0xbb: /* 3DNow! pswapd */ | |
6317 | case 0xbf: /* 3DNow! pavgusb */ | |
6318 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6319 | goto no_support_3dnow_data; | |
6320 | record_arch_list_add_reg (ir.regcache, ir.reg); | |
6321 | break; | |
6322 | ||
6323 | default: | |
6324 | no_support_3dnow_data: | |
6325 | opcode = (opcode << 8) | opcode8; | |
6326 | goto no_support; | |
6327 | break; | |
6328 | } | |
6329 | break; | |
6330 | ||
6331 | case 0x0faa: /* rsm */ | |
6332 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6333 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
6334 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6335 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6336 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
6337 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6338 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
6339 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6340 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6341 | break; | |
6342 | ||
6343 | case 0x0fae: | |
6344 | if (i386_record_modrm (&ir)) | |
6345 | return -1; | |
6346 | switch(ir.reg) | |
6347 | { | |
6348 | case 0: /* fxsave */ | |
6349 | { | |
6350 | uint64_t tmpu64; | |
6351 | ||
6352 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6353 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
6354 | return -1; | |
6355 | if (record_arch_list_add_mem (tmpu64, 512)) | |
6356 | return -1; | |
6357 | } | |
6358 | break; | |
6359 | ||
6360 | case 1: /* fxrstor */ | |
6361 | { | |
6362 | int i; | |
6363 | ||
6364 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6365 | ||
6366 | for (i = I387_MM0_REGNUM (tdep); | |
6367 | i386_mmx_regnum_p (gdbarch, i); i++) | |
6368 | record_arch_list_add_reg (ir.regcache, i); | |
6369 | ||
6370 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 6371 | i386_xmm_regnum_p (gdbarch, i); i++) |
a3c4230a HZ |
6372 | record_arch_list_add_reg (ir.regcache, i); |
6373 | ||
6374 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6375 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6376 | ||
6377 | for (i = I387_ST0_REGNUM (tdep); | |
6378 | i386_fp_regnum_p (gdbarch, i); i++) | |
6379 | record_arch_list_add_reg (ir.regcache, i); | |
6380 | ||
6381 | for (i = I387_FCTRL_REGNUM (tdep); | |
6382 | i386_fpc_regnum_p (gdbarch, i); i++) | |
6383 | record_arch_list_add_reg (ir.regcache, i); | |
6384 | } | |
6385 | break; | |
6386 | ||
6387 | case 2: /* ldmxcsr */ | |
6388 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
6389 | goto no_support; | |
6390 | record_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
6391 | break; | |
6392 | ||
6393 | case 3: /* stmxcsr */ | |
6394 | ir.ot = OT_LONG; | |
6395 | if (i386_record_lea_modrm (&ir)) | |
6396 | return -1; | |
6397 | break; | |
6398 | ||
6399 | case 5: /* lfence */ | |
6400 | case 6: /* mfence */ | |
6401 | case 7: /* sfence clflush */ | |
6402 | break; | |
6403 | ||
6404 | default: | |
6405 | opcode = (opcode << 8) | ir.modrm; | |
6406 | goto no_support; | |
6407 | break; | |
6408 | } | |
6409 | break; | |
6410 | ||
6411 | case 0x0fc3: /* movnti */ | |
6412 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
6413 | if (i386_record_modrm (&ir)) | |
6414 | return -1; | |
6415 | if (ir.mod == 3) | |
6416 | goto no_support; | |
6417 | ir.reg |= rex_r; | |
6418 | if (i386_record_lea_modrm (&ir)) | |
6419 | return -1; | |
6420 | break; | |
6421 | ||
6422 | /* Add prefix to opcode. */ | |
6423 | case 0x0f10: | |
6424 | case 0x0f11: | |
6425 | case 0x0f12: | |
6426 | case 0x0f13: | |
6427 | case 0x0f14: | |
6428 | case 0x0f15: | |
6429 | case 0x0f16: | |
6430 | case 0x0f17: | |
6431 | case 0x0f28: | |
6432 | case 0x0f29: | |
6433 | case 0x0f2a: | |
6434 | case 0x0f2b: | |
6435 | case 0x0f2c: | |
6436 | case 0x0f2d: | |
6437 | case 0x0f2e: | |
6438 | case 0x0f2f: | |
6439 | case 0x0f38: | |
6440 | case 0x0f39: | |
6441 | case 0x0f3a: | |
6442 | case 0x0f50: | |
6443 | case 0x0f51: | |
6444 | case 0x0f52: | |
6445 | case 0x0f53: | |
6446 | case 0x0f54: | |
6447 | case 0x0f55: | |
6448 | case 0x0f56: | |
6449 | case 0x0f57: | |
6450 | case 0x0f58: | |
6451 | case 0x0f59: | |
6452 | case 0x0f5a: | |
6453 | case 0x0f5b: | |
6454 | case 0x0f5c: | |
6455 | case 0x0f5d: | |
6456 | case 0x0f5e: | |
6457 | case 0x0f5f: | |
6458 | case 0x0f60: | |
6459 | case 0x0f61: | |
6460 | case 0x0f62: | |
6461 | case 0x0f63: | |
6462 | case 0x0f64: | |
6463 | case 0x0f65: | |
6464 | case 0x0f66: | |
6465 | case 0x0f67: | |
6466 | case 0x0f68: | |
6467 | case 0x0f69: | |
6468 | case 0x0f6a: | |
6469 | case 0x0f6b: | |
6470 | case 0x0f6c: | |
6471 | case 0x0f6d: | |
6472 | case 0x0f6e: | |
6473 | case 0x0f6f: | |
6474 | case 0x0f70: | |
6475 | case 0x0f71: | |
6476 | case 0x0f72: | |
6477 | case 0x0f73: | |
6478 | case 0x0f74: | |
6479 | case 0x0f75: | |
6480 | case 0x0f76: | |
6481 | case 0x0f7c: | |
6482 | case 0x0f7d: | |
6483 | case 0x0f7e: | |
6484 | case 0x0f7f: | |
6485 | case 0x0fb8: | |
6486 | case 0x0fc2: | |
6487 | case 0x0fc4: | |
6488 | case 0x0fc5: | |
6489 | case 0x0fc6: | |
6490 | case 0x0fd0: | |
6491 | case 0x0fd1: | |
6492 | case 0x0fd2: | |
6493 | case 0x0fd3: | |
6494 | case 0x0fd4: | |
6495 | case 0x0fd5: | |
6496 | case 0x0fd6: | |
6497 | case 0x0fd7: | |
6498 | case 0x0fd8: | |
6499 | case 0x0fd9: | |
6500 | case 0x0fda: | |
6501 | case 0x0fdb: | |
6502 | case 0x0fdc: | |
6503 | case 0x0fdd: | |
6504 | case 0x0fde: | |
6505 | case 0x0fdf: | |
6506 | case 0x0fe0: | |
6507 | case 0x0fe1: | |
6508 | case 0x0fe2: | |
6509 | case 0x0fe3: | |
6510 | case 0x0fe4: | |
6511 | case 0x0fe5: | |
6512 | case 0x0fe6: | |
6513 | case 0x0fe7: | |
6514 | case 0x0fe8: | |
6515 | case 0x0fe9: | |
6516 | case 0x0fea: | |
6517 | case 0x0feb: | |
6518 | case 0x0fec: | |
6519 | case 0x0fed: | |
6520 | case 0x0fee: | |
6521 | case 0x0fef: | |
6522 | case 0x0ff0: | |
6523 | case 0x0ff1: | |
6524 | case 0x0ff2: | |
6525 | case 0x0ff3: | |
6526 | case 0x0ff4: | |
6527 | case 0x0ff5: | |
6528 | case 0x0ff6: | |
6529 | case 0x0ff7: | |
6530 | case 0x0ff8: | |
6531 | case 0x0ff9: | |
6532 | case 0x0ffa: | |
6533 | case 0x0ffb: | |
6534 | case 0x0ffc: | |
6535 | case 0x0ffd: | |
6536 | case 0x0ffe: | |
6537 | switch (prefixes) | |
6538 | { | |
6539 | case PREFIX_REPNZ: | |
6540 | opcode |= 0xf20000; | |
6541 | break; | |
6542 | case PREFIX_DATA: | |
6543 | opcode |= 0x660000; | |
6544 | break; | |
6545 | case PREFIX_REPZ: | |
6546 | opcode |= 0xf30000; | |
6547 | break; | |
6548 | } | |
6549 | reswitch_prefix_add: | |
6550 | switch (opcode) | |
6551 | { | |
6552 | case 0x0f38: | |
6553 | case 0x660f38: | |
6554 | case 0xf20f38: | |
6555 | case 0x0f3a: | |
6556 | case 0x660f3a: | |
6557 | if (target_read_memory (ir.addr, &opcode8, 1)) | |
6558 | { | |
6559 | printf_unfiltered (_("Process record: error reading memory at " | |
6560 | "addr %s len = 1.\n"), | |
6561 | paddress (gdbarch, ir.addr)); | |
6562 | return -1; | |
6563 | } | |
6564 | ir.addr++; | |
6565 | opcode = (uint32_t) opcode8 | opcode << 8; | |
6566 | goto reswitch_prefix_add; | |
6567 | break; | |
6568 | ||
6569 | case 0x0f10: /* movups */ | |
6570 | case 0x660f10: /* movupd */ | |
6571 | case 0xf30f10: /* movss */ | |
6572 | case 0xf20f10: /* movsd */ | |
6573 | case 0x0f12: /* movlps */ | |
6574 | case 0x660f12: /* movlpd */ | |
6575 | case 0xf30f12: /* movsldup */ | |
6576 | case 0xf20f12: /* movddup */ | |
6577 | case 0x0f14: /* unpcklps */ | |
6578 | case 0x660f14: /* unpcklpd */ | |
6579 | case 0x0f15: /* unpckhps */ | |
6580 | case 0x660f15: /* unpckhpd */ | |
6581 | case 0x0f16: /* movhps */ | |
6582 | case 0x660f16: /* movhpd */ | |
6583 | case 0xf30f16: /* movshdup */ | |
6584 | case 0x0f28: /* movaps */ | |
6585 | case 0x660f28: /* movapd */ | |
6586 | case 0x0f2a: /* cvtpi2ps */ | |
6587 | case 0x660f2a: /* cvtpi2pd */ | |
6588 | case 0xf30f2a: /* cvtsi2ss */ | |
6589 | case 0xf20f2a: /* cvtsi2sd */ | |
6590 | case 0x0f2c: /* cvttps2pi */ | |
6591 | case 0x660f2c: /* cvttpd2pi */ | |
6592 | case 0x0f2d: /* cvtps2pi */ | |
6593 | case 0x660f2d: /* cvtpd2pi */ | |
6594 | case 0x660f3800: /* pshufb */ | |
6595 | case 0x660f3801: /* phaddw */ | |
6596 | case 0x660f3802: /* phaddd */ | |
6597 | case 0x660f3803: /* phaddsw */ | |
6598 | case 0x660f3804: /* pmaddubsw */ | |
6599 | case 0x660f3805: /* phsubw */ | |
6600 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 6601 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
6602 | case 0x660f3808: /* psignb */ |
6603 | case 0x660f3809: /* psignw */ | |
6604 | case 0x660f380a: /* psignd */ | |
6605 | case 0x660f380b: /* pmulhrsw */ | |
6606 | case 0x660f3810: /* pblendvb */ | |
6607 | case 0x660f3814: /* blendvps */ | |
6608 | case 0x660f3815: /* blendvpd */ | |
6609 | case 0x660f381c: /* pabsb */ | |
6610 | case 0x660f381d: /* pabsw */ | |
6611 | case 0x660f381e: /* pabsd */ | |
6612 | case 0x660f3820: /* pmovsxbw */ | |
6613 | case 0x660f3821: /* pmovsxbd */ | |
6614 | case 0x660f3822: /* pmovsxbq */ | |
6615 | case 0x660f3823: /* pmovsxwd */ | |
6616 | case 0x660f3824: /* pmovsxwq */ | |
6617 | case 0x660f3825: /* pmovsxdq */ | |
6618 | case 0x660f3828: /* pmuldq */ | |
6619 | case 0x660f3829: /* pcmpeqq */ | |
6620 | case 0x660f382a: /* movntdqa */ | |
6621 | case 0x660f3a08: /* roundps */ | |
6622 | case 0x660f3a09: /* roundpd */ | |
6623 | case 0x660f3a0a: /* roundss */ | |
6624 | case 0x660f3a0b: /* roundsd */ | |
6625 | case 0x660f3a0c: /* blendps */ | |
6626 | case 0x660f3a0d: /* blendpd */ | |
6627 | case 0x660f3a0e: /* pblendw */ | |
6628 | case 0x660f3a0f: /* palignr */ | |
6629 | case 0x660f3a20: /* pinsrb */ | |
6630 | case 0x660f3a21: /* insertps */ | |
6631 | case 0x660f3a22: /* pinsrd pinsrq */ | |
6632 | case 0x660f3a40: /* dpps */ | |
6633 | case 0x660f3a41: /* dppd */ | |
6634 | case 0x660f3a42: /* mpsadbw */ | |
6635 | case 0x660f3a60: /* pcmpestrm */ | |
6636 | case 0x660f3a61: /* pcmpestri */ | |
6637 | case 0x660f3a62: /* pcmpistrm */ | |
6638 | case 0x660f3a63: /* pcmpistri */ | |
6639 | case 0x0f51: /* sqrtps */ | |
6640 | case 0x660f51: /* sqrtpd */ | |
6641 | case 0xf20f51: /* sqrtsd */ | |
6642 | case 0xf30f51: /* sqrtss */ | |
6643 | case 0x0f52: /* rsqrtps */ | |
6644 | case 0xf30f52: /* rsqrtss */ | |
6645 | case 0x0f53: /* rcpps */ | |
6646 | case 0xf30f53: /* rcpss */ | |
6647 | case 0x0f54: /* andps */ | |
6648 | case 0x660f54: /* andpd */ | |
6649 | case 0x0f55: /* andnps */ | |
6650 | case 0x660f55: /* andnpd */ | |
6651 | case 0x0f56: /* orps */ | |
6652 | case 0x660f56: /* orpd */ | |
6653 | case 0x0f57: /* xorps */ | |
6654 | case 0x660f57: /* xorpd */ | |
6655 | case 0x0f58: /* addps */ | |
6656 | case 0x660f58: /* addpd */ | |
6657 | case 0xf20f58: /* addsd */ | |
6658 | case 0xf30f58: /* addss */ | |
6659 | case 0x0f59: /* mulps */ | |
6660 | case 0x660f59: /* mulpd */ | |
6661 | case 0xf20f59: /* mulsd */ | |
6662 | case 0xf30f59: /* mulss */ | |
6663 | case 0x0f5a: /* cvtps2pd */ | |
6664 | case 0x660f5a: /* cvtpd2ps */ | |
6665 | case 0xf20f5a: /* cvtsd2ss */ | |
6666 | case 0xf30f5a: /* cvtss2sd */ | |
6667 | case 0x0f5b: /* cvtdq2ps */ | |
6668 | case 0x660f5b: /* cvtps2dq */ | |
6669 | case 0xf30f5b: /* cvttps2dq */ | |
6670 | case 0x0f5c: /* subps */ | |
6671 | case 0x660f5c: /* subpd */ | |
6672 | case 0xf20f5c: /* subsd */ | |
6673 | case 0xf30f5c: /* subss */ | |
6674 | case 0x0f5d: /* minps */ | |
6675 | case 0x660f5d: /* minpd */ | |
6676 | case 0xf20f5d: /* minsd */ | |
6677 | case 0xf30f5d: /* minss */ | |
6678 | case 0x0f5e: /* divps */ | |
6679 | case 0x660f5e: /* divpd */ | |
6680 | case 0xf20f5e: /* divsd */ | |
6681 | case 0xf30f5e: /* divss */ | |
6682 | case 0x0f5f: /* maxps */ | |
6683 | case 0x660f5f: /* maxpd */ | |
6684 | case 0xf20f5f: /* maxsd */ | |
6685 | case 0xf30f5f: /* maxss */ | |
6686 | case 0x660f60: /* punpcklbw */ | |
6687 | case 0x660f61: /* punpcklwd */ | |
6688 | case 0x660f62: /* punpckldq */ | |
6689 | case 0x660f63: /* packsswb */ | |
6690 | case 0x660f64: /* pcmpgtb */ | |
6691 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 6692 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
6693 | case 0x660f67: /* packuswb */ |
6694 | case 0x660f68: /* punpckhbw */ | |
6695 | case 0x660f69: /* punpckhwd */ | |
6696 | case 0x660f6a: /* punpckhdq */ | |
6697 | case 0x660f6b: /* packssdw */ | |
6698 | case 0x660f6c: /* punpcklqdq */ | |
6699 | case 0x660f6d: /* punpckhqdq */ | |
6700 | case 0x660f6e: /* movd */ | |
6701 | case 0x660f6f: /* movdqa */ | |
6702 | case 0xf30f6f: /* movdqu */ | |
6703 | case 0x660f70: /* pshufd */ | |
6704 | case 0xf20f70: /* pshuflw */ | |
6705 | case 0xf30f70: /* pshufhw */ | |
6706 | case 0x660f74: /* pcmpeqb */ | |
6707 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 6708 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
6709 | case 0x660f7c: /* haddpd */ |
6710 | case 0xf20f7c: /* haddps */ | |
6711 | case 0x660f7d: /* hsubpd */ | |
6712 | case 0xf20f7d: /* hsubps */ | |
6713 | case 0xf30f7e: /* movq */ | |
6714 | case 0x0fc2: /* cmpps */ | |
6715 | case 0x660fc2: /* cmppd */ | |
6716 | case 0xf20fc2: /* cmpsd */ | |
6717 | case 0xf30fc2: /* cmpss */ | |
6718 | case 0x660fc4: /* pinsrw */ | |
6719 | case 0x0fc6: /* shufps */ | |
6720 | case 0x660fc6: /* shufpd */ | |
6721 | case 0x660fd0: /* addsubpd */ | |
6722 | case 0xf20fd0: /* addsubps */ | |
6723 | case 0x660fd1: /* psrlw */ | |
6724 | case 0x660fd2: /* psrld */ | |
6725 | case 0x660fd3: /* psrlq */ | |
6726 | case 0x660fd4: /* paddq */ | |
6727 | case 0x660fd5: /* pmullw */ | |
6728 | case 0xf30fd6: /* movq2dq */ | |
6729 | case 0x660fd8: /* psubusb */ | |
6730 | case 0x660fd9: /* psubusw */ | |
6731 | case 0x660fda: /* pminub */ | |
6732 | case 0x660fdb: /* pand */ | |
6733 | case 0x660fdc: /* paddusb */ | |
6734 | case 0x660fdd: /* paddusw */ | |
6735 | case 0x660fde: /* pmaxub */ | |
6736 | case 0x660fdf: /* pandn */ | |
6737 | case 0x660fe0: /* pavgb */ | |
6738 | case 0x660fe1: /* psraw */ | |
6739 | case 0x660fe2: /* psrad */ | |
6740 | case 0x660fe3: /* pavgw */ | |
6741 | case 0x660fe4: /* pmulhuw */ | |
6742 | case 0x660fe5: /* pmulhw */ | |
6743 | case 0x660fe6: /* cvttpd2dq */ | |
6744 | case 0xf20fe6: /* cvtpd2dq */ | |
6745 | case 0xf30fe6: /* cvtdq2pd */ | |
6746 | case 0x660fe8: /* psubsb */ | |
6747 | case 0x660fe9: /* psubsw */ | |
6748 | case 0x660fea: /* pminsw */ | |
6749 | case 0x660feb: /* por */ | |
6750 | case 0x660fec: /* paddsb */ | |
6751 | case 0x660fed: /* paddsw */ | |
6752 | case 0x660fee: /* pmaxsw */ | |
6753 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 6754 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
6755 | case 0x660ff1: /* psllw */ |
6756 | case 0x660ff2: /* pslld */ | |
6757 | case 0x660ff3: /* psllq */ | |
6758 | case 0x660ff4: /* pmuludq */ | |
6759 | case 0x660ff5: /* pmaddwd */ | |
6760 | case 0x660ff6: /* psadbw */ | |
6761 | case 0x660ff8: /* psubb */ | |
6762 | case 0x660ff9: /* psubw */ | |
56d2815c | 6763 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
6764 | case 0x660ffb: /* psubq */ |
6765 | case 0x660ffc: /* paddb */ | |
6766 | case 0x660ffd: /* paddw */ | |
56d2815c | 6767 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
6768 | if (i386_record_modrm (&ir)) |
6769 | return -1; | |
6770 | ir.reg |= rex_r; | |
c131fcee | 6771 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a HZ |
6772 | goto no_support; |
6773 | record_arch_list_add_reg (ir.regcache, | |
6774 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
6775 | if ((opcode & 0xfffffffc) == 0x660f3a60) | |
6776 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
6777 | break; | |
6778 | ||
6779 | case 0x0f11: /* movups */ | |
6780 | case 0x660f11: /* movupd */ | |
6781 | case 0xf30f11: /* movss */ | |
6782 | case 0xf20f11: /* movsd */ | |
6783 | case 0x0f13: /* movlps */ | |
6784 | case 0x660f13: /* movlpd */ | |
6785 | case 0x0f17: /* movhps */ | |
6786 | case 0x660f17: /* movhpd */ | |
6787 | case 0x0f29: /* movaps */ | |
6788 | case 0x660f29: /* movapd */ | |
6789 | case 0x660f3a14: /* pextrb */ | |
6790 | case 0x660f3a15: /* pextrw */ | |
6791 | case 0x660f3a16: /* pextrd pextrq */ | |
6792 | case 0x660f3a17: /* extractps */ | |
6793 | case 0x660f7f: /* movdqa */ | |
6794 | case 0xf30f7f: /* movdqu */ | |
6795 | if (i386_record_modrm (&ir)) | |
6796 | return -1; | |
6797 | if (ir.mod == 3) | |
6798 | { | |
6799 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
6800 | || opcode == 0x0f17 || opcode == 0x660f17) | |
6801 | goto no_support; | |
6802 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
6803 | if (!i386_xmm_regnum_p (gdbarch, |
6804 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
6805 | goto no_support; |
6806 | record_arch_list_add_reg (ir.regcache, | |
6807 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6808 | } | |
6809 | else | |
6810 | { | |
6811 | switch (opcode) | |
6812 | { | |
6813 | case 0x660f3a14: | |
6814 | ir.ot = OT_BYTE; | |
6815 | break; | |
6816 | case 0x660f3a15: | |
6817 | ir.ot = OT_WORD; | |
6818 | break; | |
6819 | case 0x660f3a16: | |
6820 | ir.ot = OT_LONG; | |
6821 | break; | |
6822 | case 0x660f3a17: | |
6823 | ir.ot = OT_QUAD; | |
6824 | break; | |
6825 | default: | |
6826 | ir.ot = OT_DQUAD; | |
6827 | break; | |
6828 | } | |
6829 | if (i386_record_lea_modrm (&ir)) | |
6830 | return -1; | |
6831 | } | |
6832 | break; | |
6833 | ||
6834 | case 0x0f2b: /* movntps */ | |
6835 | case 0x660f2b: /* movntpd */ | |
6836 | case 0x0fe7: /* movntq */ | |
6837 | case 0x660fe7: /* movntdq */ | |
6838 | if (ir.mod == 3) | |
6839 | goto no_support; | |
6840 | if (opcode == 0x0fe7) | |
6841 | ir.ot = OT_QUAD; | |
6842 | else | |
6843 | ir.ot = OT_DQUAD; | |
6844 | if (i386_record_lea_modrm (&ir)) | |
6845 | return -1; | |
6846 | break; | |
6847 | ||
6848 | case 0xf30f2c: /* cvttss2si */ | |
6849 | case 0xf20f2c: /* cvttsd2si */ | |
6850 | case 0xf30f2d: /* cvtss2si */ | |
6851 | case 0xf20f2d: /* cvtsd2si */ | |
6852 | case 0xf20f38f0: /* crc32 */ | |
6853 | case 0xf20f38f1: /* crc32 */ | |
6854 | case 0x0f50: /* movmskps */ | |
6855 | case 0x660f50: /* movmskpd */ | |
6856 | case 0x0fc5: /* pextrw */ | |
6857 | case 0x660fc5: /* pextrw */ | |
6858 | case 0x0fd7: /* pmovmskb */ | |
6859 | case 0x660fd7: /* pmovmskb */ | |
6860 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6861 | break; | |
6862 | ||
6863 | case 0x0f3800: /* pshufb */ | |
6864 | case 0x0f3801: /* phaddw */ | |
6865 | case 0x0f3802: /* phaddd */ | |
6866 | case 0x0f3803: /* phaddsw */ | |
6867 | case 0x0f3804: /* pmaddubsw */ | |
6868 | case 0x0f3805: /* phsubw */ | |
6869 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 6870 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
6871 | case 0x0f3808: /* psignb */ |
6872 | case 0x0f3809: /* psignw */ | |
6873 | case 0x0f380a: /* psignd */ | |
6874 | case 0x0f380b: /* pmulhrsw */ | |
6875 | case 0x0f381c: /* pabsb */ | |
6876 | case 0x0f381d: /* pabsw */ | |
6877 | case 0x0f381e: /* pabsd */ | |
6878 | case 0x0f382b: /* packusdw */ | |
6879 | case 0x0f3830: /* pmovzxbw */ | |
6880 | case 0x0f3831: /* pmovzxbd */ | |
6881 | case 0x0f3832: /* pmovzxbq */ | |
6882 | case 0x0f3833: /* pmovzxwd */ | |
6883 | case 0x0f3834: /* pmovzxwq */ | |
6884 | case 0x0f3835: /* pmovzxdq */ | |
6885 | case 0x0f3837: /* pcmpgtq */ | |
6886 | case 0x0f3838: /* pminsb */ | |
6887 | case 0x0f3839: /* pminsd */ | |
6888 | case 0x0f383a: /* pminuw */ | |
6889 | case 0x0f383b: /* pminud */ | |
6890 | case 0x0f383c: /* pmaxsb */ | |
6891 | case 0x0f383d: /* pmaxsd */ | |
6892 | case 0x0f383e: /* pmaxuw */ | |
6893 | case 0x0f383f: /* pmaxud */ | |
6894 | case 0x0f3840: /* pmulld */ | |
6895 | case 0x0f3841: /* phminposuw */ | |
6896 | case 0x0f3a0f: /* palignr */ | |
6897 | case 0x0f60: /* punpcklbw */ | |
6898 | case 0x0f61: /* punpcklwd */ | |
6899 | case 0x0f62: /* punpckldq */ | |
6900 | case 0x0f63: /* packsswb */ | |
6901 | case 0x0f64: /* pcmpgtb */ | |
6902 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 6903 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
6904 | case 0x0f67: /* packuswb */ |
6905 | case 0x0f68: /* punpckhbw */ | |
6906 | case 0x0f69: /* punpckhwd */ | |
6907 | case 0x0f6a: /* punpckhdq */ | |
6908 | case 0x0f6b: /* packssdw */ | |
6909 | case 0x0f6e: /* movd */ | |
6910 | case 0x0f6f: /* movq */ | |
6911 | case 0x0f70: /* pshufw */ | |
6912 | case 0x0f74: /* pcmpeqb */ | |
6913 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 6914 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
6915 | case 0x0fc4: /* pinsrw */ |
6916 | case 0x0fd1: /* psrlw */ | |
6917 | case 0x0fd2: /* psrld */ | |
6918 | case 0x0fd3: /* psrlq */ | |
6919 | case 0x0fd4: /* paddq */ | |
6920 | case 0x0fd5: /* pmullw */ | |
6921 | case 0xf20fd6: /* movdq2q */ | |
6922 | case 0x0fd8: /* psubusb */ | |
6923 | case 0x0fd9: /* psubusw */ | |
6924 | case 0x0fda: /* pminub */ | |
6925 | case 0x0fdb: /* pand */ | |
6926 | case 0x0fdc: /* paddusb */ | |
6927 | case 0x0fdd: /* paddusw */ | |
6928 | case 0x0fde: /* pmaxub */ | |
6929 | case 0x0fdf: /* pandn */ | |
6930 | case 0x0fe0: /* pavgb */ | |
6931 | case 0x0fe1: /* psraw */ | |
6932 | case 0x0fe2: /* psrad */ | |
6933 | case 0x0fe3: /* pavgw */ | |
6934 | case 0x0fe4: /* pmulhuw */ | |
6935 | case 0x0fe5: /* pmulhw */ | |
6936 | case 0x0fe8: /* psubsb */ | |
6937 | case 0x0fe9: /* psubsw */ | |
6938 | case 0x0fea: /* pminsw */ | |
6939 | case 0x0feb: /* por */ | |
6940 | case 0x0fec: /* paddsb */ | |
6941 | case 0x0fed: /* paddsw */ | |
6942 | case 0x0fee: /* pmaxsw */ | |
6943 | case 0x0fef: /* pxor */ | |
6944 | case 0x0ff1: /* psllw */ | |
6945 | case 0x0ff2: /* pslld */ | |
6946 | case 0x0ff3: /* psllq */ | |
6947 | case 0x0ff4: /* pmuludq */ | |
6948 | case 0x0ff5: /* pmaddwd */ | |
6949 | case 0x0ff6: /* psadbw */ | |
6950 | case 0x0ff8: /* psubb */ | |
6951 | case 0x0ff9: /* psubw */ | |
56d2815c | 6952 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
6953 | case 0x0ffb: /* psubq */ |
6954 | case 0x0ffc: /* paddb */ | |
6955 | case 0x0ffd: /* paddw */ | |
56d2815c | 6956 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
6957 | if (i386_record_modrm (&ir)) |
6958 | return -1; | |
6959 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
6960 | goto no_support; | |
6961 | record_arch_list_add_reg (ir.regcache, | |
6962 | I387_MM0_REGNUM (tdep) + ir.reg); | |
6963 | break; | |
6964 | ||
6965 | case 0x0f71: /* psllw */ | |
6966 | case 0x0f72: /* pslld */ | |
6967 | case 0x0f73: /* psllq */ | |
6968 | if (i386_record_modrm (&ir)) | |
6969 | return -1; | |
6970 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
6971 | goto no_support; | |
6972 | record_arch_list_add_reg (ir.regcache, | |
6973 | I387_MM0_REGNUM (tdep) + ir.rm); | |
6974 | break; | |
6975 | ||
6976 | case 0x660f71: /* psllw */ | |
6977 | case 0x660f72: /* pslld */ | |
6978 | case 0x660f73: /* psllq */ | |
6979 | if (i386_record_modrm (&ir)) | |
6980 | return -1; | |
6981 | ir.rm |= ir.rex_b; | |
c131fcee | 6982 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a HZ |
6983 | goto no_support; |
6984 | record_arch_list_add_reg (ir.regcache, | |
6985 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
6986 | break; | |
6987 | ||
6988 | case 0x0f7e: /* movd */ | |
6989 | case 0x660f7e: /* movd */ | |
6990 | if (i386_record_modrm (&ir)) | |
6991 | return -1; | |
6992 | if (ir.mod == 3) | |
6993 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
6994 | else | |
6995 | { | |
6996 | if (ir.dflag == 2) | |
6997 | ir.ot = OT_QUAD; | |
6998 | else | |
6999 | ir.ot = OT_LONG; | |
7000 | if (i386_record_lea_modrm (&ir)) | |
7001 | return -1; | |
7002 | } | |
7003 | break; | |
7004 | ||
7005 | case 0x0f7f: /* movq */ | |
7006 | if (i386_record_modrm (&ir)) | |
7007 | return -1; | |
7008 | if (ir.mod == 3) | |
7009 | { | |
7010 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7011 | goto no_support; | |
7012 | record_arch_list_add_reg (ir.regcache, | |
7013 | I387_MM0_REGNUM (tdep) + ir.rm); | |
7014 | } | |
7015 | else | |
7016 | { | |
7017 | ir.ot = OT_QUAD; | |
7018 | if (i386_record_lea_modrm (&ir)) | |
7019 | return -1; | |
7020 | } | |
7021 | break; | |
7022 | ||
7023 | case 0xf30fb8: /* popcnt */ | |
7024 | if (i386_record_modrm (&ir)) | |
7025 | return -1; | |
7026 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); | |
7027 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7028 | break; | |
7029 | ||
7030 | case 0x660fd6: /* movq */ | |
7031 | if (i386_record_modrm (&ir)) | |
7032 | return -1; | |
7033 | if (ir.mod == 3) | |
7034 | { | |
7035 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7036 | if (!i386_xmm_regnum_p (gdbarch, |
7037 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a HZ |
7038 | goto no_support; |
7039 | record_arch_list_add_reg (ir.regcache, | |
7040 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
7041 | } | |
7042 | else | |
7043 | { | |
7044 | ir.ot = OT_QUAD; | |
7045 | if (i386_record_lea_modrm (&ir)) | |
7046 | return -1; | |
7047 | } | |
7048 | break; | |
7049 | ||
7050 | case 0x660f3817: /* ptest */ | |
7051 | case 0x0f2e: /* ucomiss */ | |
7052 | case 0x660f2e: /* ucomisd */ | |
7053 | case 0x0f2f: /* comiss */ | |
7054 | case 0x660f2f: /* comisd */ | |
7055 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7056 | break; | |
7057 | ||
7058 | case 0x0ff7: /* maskmovq */ | |
7059 | regcache_raw_read_unsigned (ir.regcache, | |
7060 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7061 | &addr); | |
7062 | if (record_arch_list_add_mem (addr, 64)) | |
7063 | return -1; | |
7064 | break; | |
7065 | ||
7066 | case 0x660ff7: /* maskmovdqu */ | |
7067 | regcache_raw_read_unsigned (ir.regcache, | |
7068 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
7069 | &addr); | |
7070 | if (record_arch_list_add_mem (addr, 128)) | |
7071 | return -1; | |
7072 | break; | |
7073 | ||
7074 | default: | |
7075 | goto no_support; | |
7076 | break; | |
7077 | } | |
7078 | break; | |
7ad10968 HZ |
7079 | |
7080 | default: | |
7ad10968 HZ |
7081 | goto no_support; |
7082 | break; | |
7083 | } | |
7084 | ||
cf648174 HZ |
7085 | /* In the future, maybe still need to deal with need_dasm. */ |
7086 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
7087 | if (record_arch_list_add_end ()) |
7088 | return -1; | |
7089 | ||
7090 | return 0; | |
7091 | ||
01fe1b41 | 7092 | no_support: |
a3c4230a HZ |
7093 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
7094 | "at address %s.\n"), | |
7095 | (unsigned int) (opcode), | |
7096 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
7097 | return -1; |
7098 | } | |
7099 | ||
cf648174 HZ |
7100 | static const int i386_record_regmap[] = |
7101 | { | |
7102 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
7103 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
7104 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7105 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
7106 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
7107 | }; | |
7108 | ||
7a697b8d | 7109 | /* Check that the given address appears suitable for a fast |
405f8e94 | 7110 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
7111 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
7112 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
7113 | middle of the tracepoint jump. On x86, it may be possible to use |
7114 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
7115 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
7116 | of instruction to replace, and 0 if not, plus an explanatory |
7117 | string. */ | |
7118 | ||
7119 | static int | |
7120 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, | |
7121 | CORE_ADDR addr, int *isize, char **msg) | |
7122 | { | |
7123 | int len, jumplen; | |
7124 | static struct ui_file *gdb_null = NULL; | |
7125 | ||
405f8e94 SS |
7126 | /* Ask the target for the minimum instruction length supported. */ |
7127 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
7128 | ||
7129 | if (jumplen < 0) | |
7130 | { | |
7131 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
7132 | operation, assume that fast tracepoints will always be implemented | |
7133 | using 4-byte relative jumps on both x86 and x86-64. */ | |
7134 | jumplen = 5; | |
7135 | } | |
7136 | else if (jumplen == 0) | |
7137 | { | |
7138 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
7139 | returns zero, then the IPA has not loaded yet. In this case, | |
7140 | we optimistically assume that truncated 2-byte relative jumps | |
7141 | will be available on x86, and compensate later if this assumption | |
7142 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
7143 | jumps will always be used. */ | |
7144 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
7145 | } | |
7a697b8d SS |
7146 | |
7147 | /* Dummy file descriptor for the disassembler. */ | |
7148 | if (!gdb_null) | |
7149 | gdb_null = ui_file_new (); | |
7150 | ||
7151 | /* Check for fit. */ | |
7152 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 SS |
7153 | if (isize) |
7154 | *isize = len; | |
7155 | ||
7a697b8d SS |
7156 | if (len < jumplen) |
7157 | { | |
7158 | /* Return a bit of target-specific detail to add to the caller's | |
7159 | generic failure message. */ | |
7160 | if (msg) | |
1777feb0 MS |
7161 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
7162 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
7163 | len, jumplen); |
7164 | return 0; | |
7165 | } | |
405f8e94 SS |
7166 | else |
7167 | { | |
7168 | if (msg) | |
7169 | *msg = NULL; | |
7170 | return 1; | |
7171 | } | |
7a697b8d SS |
7172 | } |
7173 | ||
90884b2b L |
7174 | static int |
7175 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
7176 | struct tdesc_arch_data *tdesc_data) | |
7177 | { | |
7178 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee L |
7179 | const struct tdesc_feature *feature_core; |
7180 | const struct tdesc_feature *feature_sse, *feature_avx; | |
90884b2b L |
7181 | int i, num_regs, valid_p; |
7182 | ||
7183 | if (! tdesc_has_registers (tdesc)) | |
7184 | return 0; | |
7185 | ||
7186 | /* Get core registers. */ | |
7187 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
7188 | if (feature_core == NULL) |
7189 | return 0; | |
90884b2b L |
7190 | |
7191 | /* Get SSE registers. */ | |
c131fcee | 7192 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 7193 | |
c131fcee L |
7194 | /* Try AVX registers. */ |
7195 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
7196 | ||
90884b2b L |
7197 | valid_p = 1; |
7198 | ||
c131fcee L |
7199 | /* The XCR0 bits. */ |
7200 | if (feature_avx) | |
7201 | { | |
3a13a53b L |
7202 | /* AVX register description requires SSE register description. */ |
7203 | if (!feature_sse) | |
7204 | return 0; | |
7205 | ||
c131fcee L |
7206 | tdep->xcr0 = I386_XSTATE_AVX_MASK; |
7207 | ||
7208 | /* It may have been set by OSABI initialization function. */ | |
7209 | if (tdep->num_ymm_regs == 0) | |
7210 | { | |
7211 | tdep->ymmh_register_names = i386_ymmh_names; | |
7212 | tdep->num_ymm_regs = 8; | |
7213 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
7214 | } | |
7215 | ||
7216 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
7217 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
7218 | tdep->ymm0h_regnum + i, | |
7219 | tdep->ymmh_register_names[i]); | |
7220 | } | |
3a13a53b | 7221 | else if (feature_sse) |
c131fcee | 7222 | tdep->xcr0 = I386_XSTATE_SSE_MASK; |
3a13a53b L |
7223 | else |
7224 | { | |
7225 | tdep->xcr0 = I386_XSTATE_X87_MASK; | |
7226 | tdep->num_xmm_regs = 0; | |
7227 | } | |
c131fcee | 7228 | |
90884b2b L |
7229 | num_regs = tdep->num_core_regs; |
7230 | for (i = 0; i < num_regs; i++) | |
7231 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
7232 | tdep->register_names[i]); | |
7233 | ||
3a13a53b L |
7234 | if (feature_sse) |
7235 | { | |
7236 | /* Need to include %mxcsr, so add one. */ | |
7237 | num_regs += tdep->num_xmm_regs + 1; | |
7238 | for (; i < num_regs; i++) | |
7239 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
7240 | tdep->register_names[i]); | |
7241 | } | |
90884b2b L |
7242 | |
7243 | return valid_p; | |
7244 | } | |
7245 | ||
7ad10968 HZ |
7246 | \f |
7247 | static struct gdbarch * | |
7248 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
7249 | { | |
7250 | struct gdbarch_tdep *tdep; | |
7251 | struct gdbarch *gdbarch; | |
90884b2b L |
7252 | struct tdesc_arch_data *tdesc_data; |
7253 | const struct target_desc *tdesc; | |
1ba53b71 | 7254 | int mm0_regnum; |
c131fcee | 7255 | int ymm0_regnum; |
7ad10968 HZ |
7256 | |
7257 | /* If there is already a candidate, use it. */ | |
7258 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
7259 | if (arches != NULL) | |
7260 | return arches->gdbarch; | |
7261 | ||
7262 | /* Allocate space for the new architecture. */ | |
7263 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
7264 | gdbarch = gdbarch_alloc (&info, tdep); | |
7265 | ||
7266 | /* General-purpose registers. */ | |
7267 | tdep->gregset = NULL; | |
7268 | tdep->gregset_reg_offset = NULL; | |
7269 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
7270 | tdep->sizeof_gregset = 0; | |
7271 | ||
7272 | /* Floating-point registers. */ | |
7273 | tdep->fpregset = NULL; | |
7274 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
7275 | ||
c131fcee L |
7276 | tdep->xstateregset = NULL; |
7277 | ||
7ad10968 HZ |
7278 | /* The default settings include the FPU registers, the MMX registers |
7279 | and the SSE registers. This can be overridden for a specific ABI | |
7280 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
7281 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 7282 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
7283 | |
7284 | tdep->st0_regnum = I386_ST0_REGNUM; | |
7285 | ||
7ad10968 HZ |
7286 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
7287 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
7288 | ||
7289 | tdep->jb_pc_offset = -1; | |
7290 | tdep->struct_return = pcc_struct_return; | |
7291 | tdep->sigtramp_start = 0; | |
7292 | tdep->sigtramp_end = 0; | |
7293 | tdep->sigtramp_p = i386_sigtramp_p; | |
7294 | tdep->sigcontext_addr = NULL; | |
7295 | tdep->sc_reg_offset = NULL; | |
7296 | tdep->sc_pc_offset = -1; | |
7297 | tdep->sc_sp_offset = -1; | |
7298 | ||
c131fcee L |
7299 | tdep->xsave_xcr0_offset = -1; |
7300 | ||
cf648174 HZ |
7301 | tdep->record_regmap = i386_record_regmap; |
7302 | ||
205c306f DM |
7303 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
7304 | ||
7ad10968 HZ |
7305 | /* The format used for `long double' on almost all i386 targets is |
7306 | the i387 extended floating-point format. In fact, of all targets | |
7307 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
7308 | on having a `long double' that's not `long' at all. */ | |
7309 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
7310 | ||
7311 | /* Although the i387 extended floating-point has only 80 significant | |
7312 | bits, a `long double' actually takes up 96, probably to enforce | |
7313 | alignment. */ | |
7314 | set_gdbarch_long_double_bit (gdbarch, 96); | |
7315 | ||
7ad10968 HZ |
7316 | /* Register numbers of various important registers. */ |
7317 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
7318 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
7319 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
7320 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
7321 | ||
7322 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
7323 | numbering schemes on the i386: dbx and SVR4. These schemes | |
7324 | differ in how they number %ebp, %esp, %eflags, and the | |
7325 | floating-point registers, and are implemented by the arrays | |
7326 | dbx_register_map[] and svr4_dbx_register_map in | |
7327 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
7328 | gcc/config/i386.c, which it designates as the "default" register | |
7329 | map used in 64bit mode. This last register numbering scheme is | |
7330 | implemented in dbx64_register_map, and is used for AMD64; see | |
7331 | amd64-tdep.c. | |
7332 | ||
7333 | Currently, each GCC i386 target always uses the same register | |
7334 | numbering scheme across all its supported debugging formats | |
7335 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
7336 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
7337 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
7338 | respective config header in a manner independent of the requested | |
7339 | output debugging format. | |
7340 | ||
7341 | This does not match the arrangement below, which presumes that | |
7342 | the SDB and stabs numbering schemes differ from the DWARF and | |
7343 | DWARF 2 ones. The reason for this arrangement is that it is | |
7344 | likely to get the numbering scheme for the target's | |
7345 | default/native debug format right. For targets where GCC is the | |
7346 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
7347 | targets where the native toolchain uses a different numbering | |
7348 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
7349 | the defaults below will have to be overridden, like | |
7350 | i386_elf_init_abi() does. */ | |
7351 | ||
7352 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
7353 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7354 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
7355 | ||
7356 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
7357 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
7358 | ||
7359 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
7360 | be in use on any of the supported i386 targets. */ | |
7361 | ||
7362 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
7363 | ||
7364 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
7365 | ||
7366 | /* Call dummy code. */ | |
7367 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
e04e5beb | 7368 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
7369 | |
7370 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
7371 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
7372 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
7373 | ||
7374 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
7375 | ||
7376 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
7377 | ||
7378 | /* Stack grows downward. */ | |
7379 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7380 | ||
7381 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
7382 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
7383 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
7384 | ||
7385 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
7386 | ||
7ad10968 HZ |
7387 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
7388 | ||
7389 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
7390 | ||
7391 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
7392 | ||
7393 | /* Add the i386 register groups. */ | |
7394 | i386_add_reggroups (gdbarch); | |
90884b2b | 7395 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 7396 | |
143985b7 AF |
7397 | /* Helper for function argument information. */ |
7398 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
7399 | ||
06da04c6 | 7400 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
7401 | appended to the list first, so that it supercedes the DWARF |
7402 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
7403 | currently fails). */ |
7404 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
7405 | ||
7406 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 7407 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 7408 | CFI info will be used if it is available. */ |
10458914 | 7409 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 7410 | |
acd5c798 | 7411 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 7412 | |
1ba53b71 | 7413 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
7414 | set_gdbarch_pseudo_register_read_value (gdbarch, |
7415 | i386_pseudo_register_read_value); | |
90884b2b L |
7416 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
7417 | ||
7418 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
7419 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
7420 | ||
c131fcee L |
7421 | /* Override the normal target description method to make the AVX |
7422 | upper halves anonymous. */ | |
7423 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
7424 | ||
7425 | /* Even though the default ABI only includes general-purpose registers, | |
7426 | floating-point registers and the SSE registers, we have to leave a | |
7427 | gap for the upper AVX registers. */ | |
7428 | set_gdbarch_num_regs (gdbarch, I386_AVX_NUM_REGS); | |
90884b2b L |
7429 | |
7430 | /* Get the x86 target description from INFO. */ | |
7431 | tdesc = info.target_desc; | |
7432 | if (! tdesc_has_registers (tdesc)) | |
7433 | tdesc = tdesc_i386; | |
7434 | tdep->tdesc = tdesc; | |
7435 | ||
7436 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
7437 | tdep->register_names = i386_register_names; | |
7438 | ||
c131fcee L |
7439 | /* No upper YMM registers. */ |
7440 | tdep->ymmh_register_names = NULL; | |
7441 | tdep->ymm0h_regnum = -1; | |
7442 | ||
1ba53b71 L |
7443 | tdep->num_byte_regs = 8; |
7444 | tdep->num_word_regs = 8; | |
7445 | tdep->num_dword_regs = 0; | |
7446 | tdep->num_mmx_regs = 8; | |
c131fcee | 7447 | tdep->num_ymm_regs = 0; |
1ba53b71 | 7448 | |
90884b2b L |
7449 | tdesc_data = tdesc_data_alloc (); |
7450 | ||
dde08ee1 PA |
7451 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
7452 | ||
6710bf39 SS |
7453 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
7454 | ||
3ce1502b | 7455 | /* Hook in ABI-specific overrides, if they have been registered. */ |
90884b2b | 7456 | info.tdep_info = (void *) tdesc_data; |
4be87837 | 7457 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 7458 | |
c131fcee L |
7459 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
7460 | { | |
7461 | tdesc_data_cleanup (tdesc_data); | |
7462 | xfree (tdep); | |
7463 | gdbarch_free (gdbarch); | |
7464 | return NULL; | |
7465 | } | |
7466 | ||
1ba53b71 L |
7467 | /* Wire in pseudo registers. Number of pseudo registers may be |
7468 | changed. */ | |
7469 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
7470 | + tdep->num_word_regs | |
7471 | + tdep->num_dword_regs | |
c131fcee L |
7472 | + tdep->num_mmx_regs |
7473 | + tdep->num_ymm_regs)); | |
1ba53b71 | 7474 | |
90884b2b L |
7475 | /* Target description may be changed. */ |
7476 | tdesc = tdep->tdesc; | |
7477 | ||
90884b2b L |
7478 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
7479 | ||
7480 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
7481 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
7482 | ||
1ba53b71 L |
7483 | /* Make %al the first pseudo-register. */ |
7484 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
7485 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
7486 | ||
c131fcee | 7487 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
7488 | if (tdep->num_dword_regs) |
7489 | { | |
1c6272a6 | 7490 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
7491 | tdep->eax_regnum = ymm0_regnum; |
7492 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
7493 | } |
7494 | else | |
7495 | tdep->eax_regnum = -1; | |
7496 | ||
c131fcee L |
7497 | mm0_regnum = ymm0_regnum; |
7498 | if (tdep->num_ymm_regs) | |
7499 | { | |
1c6272a6 | 7500 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
7501 | tdep->ymm0_regnum = ymm0_regnum; |
7502 | mm0_regnum += tdep->num_ymm_regs; | |
7503 | } | |
7504 | else | |
7505 | tdep->ymm0_regnum = -1; | |
7506 | ||
1ba53b71 L |
7507 | if (tdep->num_mmx_regs != 0) |
7508 | { | |
1c6272a6 | 7509 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 L |
7510 | tdep->mm0_regnum = mm0_regnum; |
7511 | } | |
7512 | else | |
7513 | tdep->mm0_regnum = -1; | |
7514 | ||
06da04c6 | 7515 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 7516 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
7517 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
7518 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 7519 | |
8446b36a MK |
7520 | /* If we have a register mapping, enable the generic core file |
7521 | support, unless it has already been enabled. */ | |
7522 | if (tdep->gregset_reg_offset | |
7523 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
7524 | set_gdbarch_regset_from_core_section (gdbarch, | |
7525 | i386_regset_from_core_section); | |
7526 | ||
514f746b AR |
7527 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
7528 | i386_skip_permanent_breakpoint); | |
7529 | ||
7a697b8d SS |
7530 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
7531 | i386_fast_tracepoint_valid_at); | |
7532 | ||
a62cc96e AC |
7533 | return gdbarch; |
7534 | } | |
7535 | ||
8201327c MK |
7536 | static enum gdb_osabi |
7537 | i386_coff_osabi_sniffer (bfd *abfd) | |
7538 | { | |
762c5349 MK |
7539 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
7540 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
7541 | return GDB_OSABI_GO32; |
7542 | ||
7543 | return GDB_OSABI_UNKNOWN; | |
7544 | } | |
8201327c MK |
7545 | \f |
7546 | ||
28e9e0f0 MK |
7547 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
7548 | void _initialize_i386_tdep (void); | |
7549 | ||
c906108c | 7550 | void |
fba45db2 | 7551 | _initialize_i386_tdep (void) |
c906108c | 7552 | { |
a62cc96e AC |
7553 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
7554 | ||
fc338970 | 7555 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
7556 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
7557 | &disassembly_flavor, _("\ | |
7558 | Set the disassembly flavor."), _("\ | |
7559 | Show the disassembly flavor."), _("\ | |
7560 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
7561 | NULL, | |
7562 | NULL, /* FIXME: i18n: */ | |
7563 | &setlist, &showlist); | |
8201327c MK |
7564 | |
7565 | /* Add the variable that controls the convention for returning | |
7566 | structs. */ | |
7ab04401 AC |
7567 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
7568 | &struct_convention, _("\ | |
7569 | Set the convention for returning small structs."), _("\ | |
7570 | Show the convention for returning small structs."), _("\ | |
7571 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
7572 | is \"default\"."), | |
7573 | NULL, | |
7574 | NULL, /* FIXME: i18n: */ | |
7575 | &setlist, &showlist); | |
8201327c MK |
7576 | |
7577 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
7578 | i386_coff_osabi_sniffer); | |
8201327c | 7579 | |
05816f70 | 7580 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 7581 | i386_svr4_init_abi); |
05816f70 | 7582 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 7583 | i386_go32_init_abi); |
38c968cf | 7584 | |
209bd28e | 7585 | /* Initialize the i386-specific register groups. */ |
38c968cf | 7586 | i386_init_reggroups (); |
90884b2b L |
7587 | |
7588 | /* Initialize the standard target descriptions. */ | |
7589 | initialize_tdesc_i386 (); | |
3a13a53b | 7590 | initialize_tdesc_i386_mmx (); |
c131fcee | 7591 | initialize_tdesc_i386_avx (); |
c8d5aac9 L |
7592 | |
7593 | /* Tell remote stub that we support XML target description. */ | |
7594 | register_remote_support_xml ("i386"); | |
c906108c | 7595 | } |