Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
5ae96ec1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
acd5c798 | 46 | |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
d2a7c97a | 52 | |
7ad10968 HZ |
53 | #include "record.h" |
54 | #include <stdint.h> | |
55 | ||
c4fc7f1b | 56 | /* Register names. */ |
c40e1eab | 57 | |
fc633446 MK |
58 | static char *i386_register_names[] = |
59 | { | |
60 | "eax", "ecx", "edx", "ebx", | |
61 | "esp", "ebp", "esi", "edi", | |
62 | "eip", "eflags", "cs", "ss", | |
63 | "ds", "es", "fs", "gs", | |
64 | "st0", "st1", "st2", "st3", | |
65 | "st4", "st5", "st6", "st7", | |
66 | "fctrl", "fstat", "ftag", "fiseg", | |
67 | "fioff", "foseg", "fooff", "fop", | |
68 | "xmm0", "xmm1", "xmm2", "xmm3", | |
69 | "xmm4", "xmm5", "xmm6", "xmm7", | |
70 | "mxcsr" | |
71 | }; | |
72 | ||
1cb97e17 | 73 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 74 | |
c4fc7f1b | 75 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
76 | |
77 | static char *i386_mmx_names[] = | |
78 | { | |
79 | "mm0", "mm1", "mm2", "mm3", | |
80 | "mm4", "mm5", "mm6", "mm7" | |
81 | }; | |
c40e1eab | 82 | |
1cb97e17 | 83 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 84 | |
28fc6740 | 85 | static int |
5716833c | 86 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 87 | { |
5716833c MK |
88 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
89 | ||
90 | if (mm0_regnum < 0) | |
91 | return 0; | |
92 | ||
93 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
94 | } |
95 | ||
5716833c | 96 | /* SSE register? */ |
23a34459 | 97 | |
5716833c MK |
98 | static int |
99 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 100 | { |
5716833c MK |
101 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
102 | ||
20a6ec49 | 103 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
104 | return 0; |
105 | ||
20a6ec49 MD |
106 | return (I387_XMM0_REGNUM (tdep) <= regnum |
107 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
108 | } |
109 | ||
5716833c MK |
110 | static int |
111 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 112 | { |
5716833c MK |
113 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
114 | ||
20a6ec49 | 115 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
116 | return 0; |
117 | ||
20a6ec49 | 118 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
119 | } |
120 | ||
5716833c | 121 | /* FP register? */ |
23a34459 AC |
122 | |
123 | int | |
20a6ec49 | 124 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 125 | { |
20a6ec49 MD |
126 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
127 | ||
128 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
129 | return 0; |
130 | ||
20a6ec49 MD |
131 | return (I387_ST0_REGNUM (tdep) <= regnum |
132 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
133 | } |
134 | ||
135 | int | |
20a6ec49 | 136 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 137 | { |
20a6ec49 MD |
138 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
139 | ||
140 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
141 | return 0; |
142 | ||
20a6ec49 MD |
143 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
144 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
145 | } |
146 | ||
30b0e2d8 | 147 | /* Return the name of register REGNUM. */ |
fc633446 | 148 | |
fa88f677 | 149 | const char * |
d93859e2 | 150 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 151 | { |
d93859e2 | 152 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
20a6ec49 | 153 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; |
fc633446 | 154 | |
30b0e2d8 MK |
155 | if (regnum >= 0 && regnum < i386_num_register_names) |
156 | return i386_register_names[regnum]; | |
70913449 | 157 | |
c40e1eab | 158 | return NULL; |
fc633446 MK |
159 | } |
160 | ||
c4fc7f1b | 161 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
162 | number used by GDB. */ |
163 | ||
8201327c | 164 | static int |
d3f73121 | 165 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 166 | { |
20a6ec49 MD |
167 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
168 | ||
c4fc7f1b MK |
169 | /* This implements what GCC calls the "default" register map |
170 | (dbx_register_map[]). */ | |
171 | ||
85540d8c MK |
172 | if (reg >= 0 && reg <= 7) |
173 | { | |
9872ad24 JB |
174 | /* General-purpose registers. The debug info calls %ebp |
175 | register 4, and %esp register 5. */ | |
176 | if (reg == 4) | |
177 | return 5; | |
178 | else if (reg == 5) | |
179 | return 4; | |
180 | else return reg; | |
85540d8c MK |
181 | } |
182 | else if (reg >= 12 && reg <= 19) | |
183 | { | |
184 | /* Floating-point registers. */ | |
20a6ec49 | 185 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
186 | } |
187 | else if (reg >= 21 && reg <= 28) | |
188 | { | |
189 | /* SSE registers. */ | |
20a6ec49 | 190 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
191 | } |
192 | else if (reg >= 29 && reg <= 36) | |
193 | { | |
194 | /* MMX registers. */ | |
20a6ec49 | 195 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
196 | } |
197 | ||
198 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 199 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
200 | } |
201 | ||
c4fc7f1b MK |
202 | /* Convert SVR4 register number REG to the appropriate register number |
203 | used by GDB. */ | |
85540d8c | 204 | |
8201327c | 205 | static int |
d3f73121 | 206 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 207 | { |
20a6ec49 MD |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
209 | ||
c4fc7f1b MK |
210 | /* This implements the GCC register map that tries to be compatible |
211 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
212 | ||
213 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
214 | numbers the floating point registers differently. */ |
215 | if (reg >= 0 && reg <= 9) | |
216 | { | |
acd5c798 | 217 | /* General-purpose registers. */ |
85540d8c MK |
218 | return reg; |
219 | } | |
220 | else if (reg >= 11 && reg <= 18) | |
221 | { | |
222 | /* Floating-point registers. */ | |
20a6ec49 | 223 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 224 | } |
c6f4c129 | 225 | else if (reg >= 21 && reg <= 36) |
85540d8c | 226 | { |
c4fc7f1b | 227 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 228 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
229 | } |
230 | ||
c6f4c129 JB |
231 | switch (reg) |
232 | { | |
20a6ec49 MD |
233 | case 37: return I387_FCTRL_REGNUM (tdep); |
234 | case 38: return I387_FSTAT_REGNUM (tdep); | |
235 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
236 | case 40: return I386_ES_REGNUM; |
237 | case 41: return I386_CS_REGNUM; | |
238 | case 42: return I386_SS_REGNUM; | |
239 | case 43: return I386_DS_REGNUM; | |
240 | case 44: return I386_FS_REGNUM; | |
241 | case 45: return I386_GS_REGNUM; | |
242 | } | |
243 | ||
85540d8c | 244 | /* This will hopefully provoke a warning. */ |
d3f73121 | 245 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 246 | } |
5716833c | 247 | |
fc338970 | 248 | \f |
917317f4 | 249 | |
fc338970 MK |
250 | /* This is the variable that is set with "set disassembly-flavor", and |
251 | its legitimate values. */ | |
53904c9e AC |
252 | static const char att_flavor[] = "att"; |
253 | static const char intel_flavor[] = "intel"; | |
254 | static const char *valid_flavors[] = | |
c5aa993b | 255 | { |
c906108c SS |
256 | att_flavor, |
257 | intel_flavor, | |
258 | NULL | |
259 | }; | |
53904c9e | 260 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 261 | \f |
c906108c | 262 | |
acd5c798 MK |
263 | /* Use the program counter to determine the contents and size of a |
264 | breakpoint instruction. Return a pointer to a string of bytes that | |
265 | encode a breakpoint instruction, store the length of the string in | |
266 | *LEN and optionally adjust *PC to point to the correct memory | |
267 | location for inserting the breakpoint. | |
c906108c | 268 | |
acd5c798 MK |
269 | On the i386 we have a single breakpoint that fits in a single byte |
270 | and can be inserted anywhere. | |
c906108c | 271 | |
acd5c798 | 272 | This function is 64-bit safe. */ |
63c0089f MK |
273 | |
274 | static const gdb_byte * | |
67d57894 | 275 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 276 | { |
63c0089f MK |
277 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
278 | ||
acd5c798 MK |
279 | *len = sizeof (break_insn); |
280 | return break_insn; | |
c906108c | 281 | } |
237fc4c9 PA |
282 | \f |
283 | /* Displaced instruction handling. */ | |
284 | ||
1903f0e6 DE |
285 | /* Skip the legacy instruction prefixes in INSN. |
286 | Not all prefixes are valid for any particular insn | |
287 | but we needn't care, the insn will fault if it's invalid. | |
288 | The result is a pointer to the first opcode byte, | |
289 | or NULL if we run off the end of the buffer. */ | |
290 | ||
291 | static gdb_byte * | |
292 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
293 | { | |
294 | gdb_byte *end = insn + max_len; | |
295 | ||
296 | while (insn < end) | |
297 | { | |
298 | switch (*insn) | |
299 | { | |
300 | case DATA_PREFIX_OPCODE: | |
301 | case ADDR_PREFIX_OPCODE: | |
302 | case CS_PREFIX_OPCODE: | |
303 | case DS_PREFIX_OPCODE: | |
304 | case ES_PREFIX_OPCODE: | |
305 | case FS_PREFIX_OPCODE: | |
306 | case GS_PREFIX_OPCODE: | |
307 | case SS_PREFIX_OPCODE: | |
308 | case LOCK_PREFIX_OPCODE: | |
309 | case REPE_PREFIX_OPCODE: | |
310 | case REPNE_PREFIX_OPCODE: | |
311 | ++insn; | |
312 | continue; | |
313 | default: | |
314 | return insn; | |
315 | } | |
316 | } | |
317 | ||
318 | return NULL; | |
319 | } | |
237fc4c9 PA |
320 | |
321 | static int | |
1903f0e6 | 322 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
323 | { |
324 | /* jmp far (absolute address in operand) */ | |
325 | if (insn[0] == 0xea) | |
326 | return 1; | |
327 | ||
328 | if (insn[0] == 0xff) | |
329 | { | |
330 | /* jump near, absolute indirect (/4) */ | |
331 | if ((insn[1] & 0x38) == 0x20) | |
332 | return 1; | |
333 | ||
334 | /* jump far, absolute indirect (/5) */ | |
335 | if ((insn[1] & 0x38) == 0x28) | |
336 | return 1; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
342 | static int | |
1903f0e6 | 343 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
344 | { |
345 | /* call far, absolute */ | |
346 | if (insn[0] == 0x9a) | |
347 | return 1; | |
348 | ||
349 | if (insn[0] == 0xff) | |
350 | { | |
351 | /* Call near, absolute indirect (/2) */ | |
352 | if ((insn[1] & 0x38) == 0x10) | |
353 | return 1; | |
354 | ||
355 | /* Call far, absolute indirect (/3) */ | |
356 | if ((insn[1] & 0x38) == 0x18) | |
357 | return 1; | |
358 | } | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static int | |
1903f0e6 | 364 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
365 | { |
366 | switch (insn[0]) | |
367 | { | |
368 | case 0xc2: /* ret near, pop N bytes */ | |
369 | case 0xc3: /* ret near */ | |
370 | case 0xca: /* ret far, pop N bytes */ | |
371 | case 0xcb: /* ret far */ | |
372 | case 0xcf: /* iret */ | |
373 | return 1; | |
374 | ||
375 | default: | |
376 | return 0; | |
377 | } | |
378 | } | |
379 | ||
380 | static int | |
1903f0e6 | 381 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
382 | { |
383 | if (i386_absolute_call_p (insn)) | |
384 | return 1; | |
385 | ||
386 | /* call near, relative */ | |
387 | if (insn[0] == 0xe8) | |
388 | return 1; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
237fc4c9 PA |
393 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
394 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 395 | |
237fc4c9 | 396 | static int |
1903f0e6 | 397 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
398 | { |
399 | if (insn[0] == 0xcd) | |
400 | { | |
401 | *lengthp = 2; | |
402 | return 1; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | /* Fix up the state of registers and memory after having single-stepped | |
409 | a displaced instruction. */ | |
1903f0e6 | 410 | |
237fc4c9 PA |
411 | void |
412 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
413 | struct displaced_step_closure *closure, | |
414 | CORE_ADDR from, CORE_ADDR to, | |
415 | struct regcache *regs) | |
416 | { | |
e17a4113 UW |
417 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
418 | ||
237fc4c9 PA |
419 | /* The offset we applied to the instruction's address. |
420 | This could well be negative (when viewed as a signed 32-bit | |
421 | value), but ULONGEST won't reflect that, so take care when | |
422 | applying it. */ | |
423 | ULONGEST insn_offset = to - from; | |
424 | ||
425 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
426 | copy of the instruction. */ | |
427 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
428 | /* The start of the insn, needed in case we see some prefixes. */ |
429 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
430 | |
431 | if (debug_displaced) | |
432 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 433 | "displaced: fixup (%s, %s), " |
237fc4c9 | 434 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
435 | paddress (gdbarch, from), paddress (gdbarch, to), |
436 | insn[0], insn[1]); | |
237fc4c9 PA |
437 | |
438 | /* The list of issues to contend with here is taken from | |
439 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
440 | Yay for Free Software! */ | |
441 | ||
442 | /* Relocate the %eip, if necessary. */ | |
443 | ||
1903f0e6 DE |
444 | /* The instruction recognizers we use assume any leading prefixes |
445 | have been skipped. */ | |
446 | { | |
447 | /* This is the size of the buffer in closure. */ | |
448 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
449 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
450 | /* If there are too many prefixes, just ignore the insn. | |
451 | It will fault when run. */ | |
452 | if (opcode != NULL) | |
453 | insn = opcode; | |
454 | } | |
455 | ||
237fc4c9 PA |
456 | /* Except in the case of absolute or indirect jump or call |
457 | instructions, or a return instruction, the new eip is relative to | |
458 | the displaced instruction; make it relative. Well, signal | |
459 | handler returns don't need relocation either, but we use the | |
460 | value of %eip to recognize those; see below. */ | |
461 | if (! i386_absolute_jmp_p (insn) | |
462 | && ! i386_absolute_call_p (insn) | |
463 | && ! i386_ret_p (insn)) | |
464 | { | |
465 | ULONGEST orig_eip; | |
466 | ULONGEST insn_len; | |
467 | ||
468 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
469 | ||
470 | /* A signal trampoline system call changes the %eip, resuming | |
471 | execution of the main program after the signal handler has | |
472 | returned. That makes them like 'return' instructions; we | |
473 | shouldn't relocate %eip. | |
474 | ||
475 | But most system calls don't, and we do need to relocate %eip. | |
476 | ||
477 | Our heuristic for distinguishing these cases: if stepping | |
478 | over the system call instruction left control directly after | |
479 | the instruction, the we relocate --- control almost certainly | |
480 | doesn't belong in the displaced copy. Otherwise, we assume | |
481 | the instruction has put control where it belongs, and leave | |
482 | it unrelocated. Goodness help us if there are PC-relative | |
483 | system calls. */ | |
484 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 485 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
486 | { |
487 | if (debug_displaced) | |
488 | fprintf_unfiltered (gdb_stdlog, | |
489 | "displaced: syscall changed %%eip; " | |
490 | "not relocating\n"); | |
491 | } | |
492 | else | |
493 | { | |
494 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
495 | ||
1903f0e6 DE |
496 | /* If we just stepped over a breakpoint insn, we don't backup |
497 | the pc on purpose; this is to match behaviour without | |
498 | stepping. */ | |
237fc4c9 PA |
499 | |
500 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
501 | ||
502 | if (debug_displaced) | |
503 | fprintf_unfiltered (gdb_stdlog, | |
504 | "displaced: " | |
5af949e3 UW |
505 | "relocated %%eip from %s to %s\n", |
506 | paddress (gdbarch, orig_eip), | |
507 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
508 | } |
509 | } | |
510 | ||
511 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
512 | pushed value, and should be cleared. We'll leave this for later, | |
513 | since GDB already messes up the TF flag when stepping over a | |
514 | pushfl. */ | |
515 | ||
516 | /* If the instruction was a call, the return address now atop the | |
517 | stack is the address following the copied instruction. We need | |
518 | to make it the address following the original instruction. */ | |
519 | if (i386_call_p (insn)) | |
520 | { | |
521 | ULONGEST esp; | |
522 | ULONGEST retaddr; | |
523 | const ULONGEST retaddr_len = 4; | |
524 | ||
525 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 526 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 527 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 528 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
529 | |
530 | if (debug_displaced) | |
531 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
532 | "displaced: relocated return addr at %s to %s\n", |
533 | paddress (gdbarch, esp), | |
534 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
535 | } |
536 | } | |
fc338970 | 537 | \f |
acd5c798 MK |
538 | #ifdef I386_REGNO_TO_SYMMETRY |
539 | #error "The Sequent Symmetry is no longer supported." | |
540 | #endif | |
c906108c | 541 | |
acd5c798 MK |
542 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
543 | and %esp "belong" to the calling function. Therefore these | |
544 | registers should be saved if they're going to be modified. */ | |
c906108c | 545 | |
acd5c798 MK |
546 | /* The maximum number of saved registers. This should include all |
547 | registers mentioned above, and %eip. */ | |
a3386186 | 548 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
549 | |
550 | struct i386_frame_cache | |
c906108c | 551 | { |
acd5c798 MK |
552 | /* Base address. */ |
553 | CORE_ADDR base; | |
772562f8 | 554 | LONGEST sp_offset; |
acd5c798 MK |
555 | CORE_ADDR pc; |
556 | ||
fd13a04a AC |
557 | /* Saved registers. */ |
558 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 559 | CORE_ADDR saved_sp; |
e0c62198 | 560 | int saved_sp_reg; |
acd5c798 MK |
561 | int pc_in_eax; |
562 | ||
563 | /* Stack space reserved for local variables. */ | |
564 | long locals; | |
565 | }; | |
566 | ||
567 | /* Allocate and initialize a frame cache. */ | |
568 | ||
569 | static struct i386_frame_cache * | |
fd13a04a | 570 | i386_alloc_frame_cache (void) |
acd5c798 MK |
571 | { |
572 | struct i386_frame_cache *cache; | |
573 | int i; | |
574 | ||
575 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
576 | ||
577 | /* Base address. */ | |
578 | cache->base = 0; | |
579 | cache->sp_offset = -4; | |
580 | cache->pc = 0; | |
581 | ||
fd13a04a AC |
582 | /* Saved registers. We initialize these to -1 since zero is a valid |
583 | offset (that's where %ebp is supposed to be stored). */ | |
584 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
585 | cache->saved_regs[i] = -1; | |
acd5c798 | 586 | cache->saved_sp = 0; |
e0c62198 | 587 | cache->saved_sp_reg = -1; |
acd5c798 MK |
588 | cache->pc_in_eax = 0; |
589 | ||
590 | /* Frameless until proven otherwise. */ | |
591 | cache->locals = -1; | |
592 | ||
593 | return cache; | |
594 | } | |
c906108c | 595 | |
acd5c798 MK |
596 | /* If the instruction at PC is a jump, return the address of its |
597 | target. Otherwise, return PC. */ | |
c906108c | 598 | |
acd5c798 | 599 | static CORE_ADDR |
e17a4113 | 600 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 601 | { |
e17a4113 | 602 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 603 | gdb_byte op; |
acd5c798 MK |
604 | long delta = 0; |
605 | int data16 = 0; | |
c906108c | 606 | |
8defab1a | 607 | target_read_memory (pc, &op, 1); |
acd5c798 | 608 | if (op == 0x66) |
c906108c | 609 | { |
c906108c | 610 | data16 = 1; |
e17a4113 | 611 | op = read_memory_unsigned_integer (pc + 1, 1, byte_order); |
c906108c SS |
612 | } |
613 | ||
acd5c798 | 614 | switch (op) |
c906108c SS |
615 | { |
616 | case 0xe9: | |
fc338970 | 617 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
618 | if (data16) |
619 | { | |
e17a4113 | 620 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 621 | |
fc338970 MK |
622 | /* Include the size of the jmp instruction (including the |
623 | 0x66 prefix). */ | |
acd5c798 | 624 | delta += 4; |
c906108c SS |
625 | } |
626 | else | |
627 | { | |
e17a4113 | 628 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 629 | |
acd5c798 MK |
630 | /* Include the size of the jmp instruction. */ |
631 | delta += 5; | |
c906108c SS |
632 | } |
633 | break; | |
634 | case 0xeb: | |
fc338970 | 635 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 636 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 637 | |
acd5c798 | 638 | delta += data16 + 2; |
c906108c SS |
639 | break; |
640 | } | |
c906108c | 641 | |
acd5c798 MK |
642 | return pc + delta; |
643 | } | |
fc338970 | 644 | |
acd5c798 MK |
645 | /* Check whether PC points at a prologue for a function returning a |
646 | structure or union. If so, it updates CACHE and returns the | |
647 | address of the first instruction after the code sequence that | |
648 | removes the "hidden" argument from the stack or CURRENT_PC, | |
649 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 650 | |
acd5c798 MK |
651 | static CORE_ADDR |
652 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
653 | struct i386_frame_cache *cache) | |
c906108c | 654 | { |
acd5c798 MK |
655 | /* Functions that return a structure or union start with: |
656 | ||
657 | popl %eax 0x58 | |
658 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
659 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
660 | ||
661 | (the System V compiler puts out the second `xchg' instruction, | |
662 | and the assembler doesn't try to optimize it, so the 'sib' form | |
663 | gets generated). This sequence is used to get the address of the | |
664 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
665 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
666 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
667 | gdb_byte buf[4]; | |
668 | gdb_byte op; | |
c906108c | 669 | |
acd5c798 MK |
670 | if (current_pc <= pc) |
671 | return pc; | |
672 | ||
8defab1a | 673 | target_read_memory (pc, &op, 1); |
c906108c | 674 | |
acd5c798 MK |
675 | if (op != 0x58) /* popl %eax */ |
676 | return pc; | |
c906108c | 677 | |
8defab1a | 678 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
679 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
680 | return pc; | |
c906108c | 681 | |
acd5c798 | 682 | if (current_pc == pc) |
c906108c | 683 | { |
acd5c798 MK |
684 | cache->sp_offset += 4; |
685 | return current_pc; | |
c906108c SS |
686 | } |
687 | ||
acd5c798 | 688 | if (current_pc == pc + 1) |
c906108c | 689 | { |
acd5c798 MK |
690 | cache->pc_in_eax = 1; |
691 | return current_pc; | |
692 | } | |
693 | ||
694 | if (buf[1] == proto1[1]) | |
695 | return pc + 4; | |
696 | else | |
697 | return pc + 5; | |
698 | } | |
699 | ||
700 | static CORE_ADDR | |
701 | i386_skip_probe (CORE_ADDR pc) | |
702 | { | |
703 | /* A function may start with | |
fc338970 | 704 | |
acd5c798 MK |
705 | pushl constant |
706 | call _probe | |
707 | addl $4, %esp | |
fc338970 | 708 | |
acd5c798 MK |
709 | followed by |
710 | ||
711 | pushl %ebp | |
fc338970 | 712 | |
acd5c798 | 713 | etc. */ |
63c0089f MK |
714 | gdb_byte buf[8]; |
715 | gdb_byte op; | |
fc338970 | 716 | |
8defab1a | 717 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
718 | |
719 | if (op == 0x68 || op == 0x6a) | |
720 | { | |
721 | int delta; | |
c906108c | 722 | |
acd5c798 MK |
723 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
724 | four-byte operand, depending on the opcode. */ | |
c906108c | 725 | if (op == 0x68) |
acd5c798 | 726 | delta = 5; |
c906108c | 727 | else |
acd5c798 | 728 | delta = 2; |
c906108c | 729 | |
acd5c798 MK |
730 | /* Read the following 8 bytes, which should be `call _probe' (6 |
731 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
732 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 733 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 734 | pc += delta + sizeof (buf); |
c906108c SS |
735 | } |
736 | ||
acd5c798 MK |
737 | return pc; |
738 | } | |
739 | ||
92dd43fa MK |
740 | /* GCC 4.1 and later, can put code in the prologue to realign the |
741 | stack pointer. Check whether PC points to such code, and update | |
742 | CACHE accordingly. Return the first instruction after the code | |
743 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
744 | recognize the code, return PC. */ | |
745 | ||
746 | static CORE_ADDR | |
747 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
748 | struct i386_frame_cache *cache) | |
749 | { | |
e0c62198 L |
750 | /* There are 2 code sequences to re-align stack before the frame |
751 | gets set up: | |
752 | ||
753 | 1. Use a caller-saved saved register: | |
754 | ||
755 | leal 4(%esp), %reg | |
756 | andl $-XXX, %esp | |
757 | pushl -4(%reg) | |
758 | ||
759 | 2. Use a callee-saved saved register: | |
760 | ||
761 | pushl %reg | |
762 | leal 8(%esp), %reg | |
763 | andl $-XXX, %esp | |
764 | pushl -4(%reg) | |
765 | ||
766 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
767 | ||
768 | 0x83 0xe4 0xf0 andl $-16, %esp | |
769 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
770 | */ | |
771 | ||
772 | gdb_byte buf[14]; | |
773 | int reg; | |
774 | int offset, offset_and; | |
775 | static int regnums[8] = { | |
776 | I386_EAX_REGNUM, /* %eax */ | |
777 | I386_ECX_REGNUM, /* %ecx */ | |
778 | I386_EDX_REGNUM, /* %edx */ | |
779 | I386_EBX_REGNUM, /* %ebx */ | |
780 | I386_ESP_REGNUM, /* %esp */ | |
781 | I386_EBP_REGNUM, /* %ebp */ | |
782 | I386_ESI_REGNUM, /* %esi */ | |
783 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 784 | }; |
92dd43fa | 785 | |
e0c62198 L |
786 | if (target_read_memory (pc, buf, sizeof buf)) |
787 | return pc; | |
788 | ||
789 | /* Check caller-saved saved register. The first instruction has | |
790 | to be "leal 4(%esp), %reg". */ | |
791 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
792 | { | |
793 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
794 | if ((buf[1] & 0xc7) != 0x44) | |
795 | return pc; | |
796 | ||
797 | /* REG has register number. */ | |
798 | reg = (buf[1] >> 3) & 7; | |
799 | offset = 4; | |
800 | } | |
801 | else | |
802 | { | |
803 | /* Check callee-saved saved register. The first instruction | |
804 | has to be "pushl %reg". */ | |
805 | if ((buf[0] & 0xf8) != 0x50) | |
806 | return pc; | |
807 | ||
808 | /* Get register. */ | |
809 | reg = buf[0] & 0x7; | |
810 | ||
811 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
812 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
813 | return pc; | |
814 | ||
815 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
816 | if ((buf[2] & 0xc7) != 0x44) | |
817 | return pc; | |
818 | ||
819 | /* REG has register number. Registers in pushl and leal have to | |
820 | be the same. */ | |
821 | if (reg != ((buf[2] >> 3) & 7)) | |
822 | return pc; | |
823 | ||
824 | offset = 5; | |
825 | } | |
826 | ||
827 | /* Rigister can't be %esp nor %ebp. */ | |
828 | if (reg == 4 || reg == 5) | |
829 | return pc; | |
830 | ||
831 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
832 | if (buf[offset + 1] != 0xe4 | |
833 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
834 | return pc; | |
835 | ||
836 | offset_and = offset; | |
837 | offset += buf[offset] == 0x81 ? 6 : 3; | |
838 | ||
839 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
840 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
841 | if (buf[offset] != 0xff | |
842 | || buf[offset + 2] != 0xfc | |
843 | || (buf[offset + 1] & 0xf8) != 0x70) | |
844 | return pc; | |
845 | ||
846 | /* R/M has register. Registers in leal and pushl have to be the | |
847 | same. */ | |
848 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
849 | return pc; |
850 | ||
e0c62198 L |
851 | if (current_pc > pc + offset_and) |
852 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 853 | |
e0c62198 | 854 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
855 | } |
856 | ||
37bdc87e | 857 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 858 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
859 | |
860 | /* Instruction description. */ | |
861 | struct i386_insn | |
862 | { | |
863 | size_t len; | |
237fc4c9 PA |
864 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
865 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
866 | }; |
867 | ||
868 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
869 | the first instruction description that matches. Otherwise, return | |
870 | NULL. */ | |
871 | ||
872 | static struct i386_insn * | |
873 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
874 | { | |
875 | struct i386_insn *insn; | |
63c0089f | 876 | gdb_byte op; |
37bdc87e | 877 | |
8defab1a | 878 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
879 | |
880 | for (insn = skip_insns; insn->len > 0; insn++) | |
881 | { | |
882 | if ((op & insn->mask[0]) == insn->insn[0]) | |
883 | { | |
237fc4c9 | 884 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 885 | int insn_matched = 1; |
37bdc87e MK |
886 | size_t i; |
887 | ||
888 | gdb_assert (insn->len > 1); | |
237fc4c9 | 889 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 890 | |
8defab1a | 891 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
892 | for (i = 1; i < insn->len; i++) |
893 | { | |
894 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 895 | insn_matched = 0; |
37bdc87e | 896 | } |
613e8135 MK |
897 | |
898 | if (insn_matched) | |
899 | return insn; | |
37bdc87e MK |
900 | } |
901 | } | |
902 | ||
903 | return NULL; | |
904 | } | |
905 | ||
906 | /* Some special instructions that might be migrated by GCC into the | |
907 | part of the prologue that sets up the new stack frame. Because the | |
908 | stack frame hasn't been setup yet, no registers have been saved | |
909 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
910 | touched. */ | |
911 | ||
912 | struct i386_insn i386_frame_setup_skip_insns[] = | |
913 | { | |
914 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
915 | ||
916 | ??? Should we handle 16-bit operand-sizes here? */ | |
917 | ||
918 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
919 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
920 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
921 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
922 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
923 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
924 | { 5, { 0xb8 }, { 0xfe } }, | |
925 | /* `movl imm32, %edx' */ | |
926 | { 5, { 0xba }, { 0xff } }, | |
927 | ||
928 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
929 | encoding for `mov m32, %eax'. | |
930 | ||
931 | ??? Should we handle SIB adressing here? | |
932 | ??? Should we handle 16-bit operand-sizes here? */ | |
933 | ||
934 | /* `movl m32, %eax' */ | |
935 | { 5, { 0xa1 }, { 0xff } }, | |
936 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
937 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
938 | /* `movl m32, %edx' */ | |
939 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
940 | ||
941 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
942 | Because of the symmetry, there are actually two ways to encode | |
943 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
944 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
945 | ||
946 | /* `subl %eax, %eax' */ | |
947 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
948 | /* `subl %ecx, %ecx' */ | |
949 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
950 | /* `subl %edx, %edx' */ | |
951 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
952 | /* `xorl %eax, %eax' */ | |
953 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
954 | /* `xorl %ecx, %ecx' */ | |
955 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
956 | /* `xorl %edx, %edx' */ | |
957 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
958 | { 0 } | |
959 | }; | |
960 | ||
e11481da PM |
961 | |
962 | /* Check whether PC points to a no-op instruction. */ | |
963 | static CORE_ADDR | |
964 | i386_skip_noop (CORE_ADDR pc) | |
965 | { | |
966 | gdb_byte op; | |
967 | int check = 1; | |
968 | ||
8defab1a | 969 | target_read_memory (pc, &op, 1); |
e11481da PM |
970 | |
971 | while (check) | |
972 | { | |
973 | check = 0; | |
974 | /* Ignore `nop' instruction. */ | |
975 | if (op == 0x90) | |
976 | { | |
977 | pc += 1; | |
8defab1a | 978 | target_read_memory (pc, &op, 1); |
e11481da PM |
979 | check = 1; |
980 | } | |
981 | /* Ignore no-op instruction `mov %edi, %edi'. | |
982 | Microsoft system dlls often start with | |
983 | a `mov %edi,%edi' instruction. | |
984 | The 5 bytes before the function start are | |
985 | filled with `nop' instructions. | |
986 | This pattern can be used for hot-patching: | |
987 | The `mov %edi, %edi' instruction can be replaced by a | |
988 | near jump to the location of the 5 `nop' instructions | |
989 | which can be replaced by a 32-bit jump to anywhere | |
990 | in the 32-bit address space. */ | |
991 | ||
992 | else if (op == 0x8b) | |
993 | { | |
8defab1a | 994 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
995 | if (op == 0xff) |
996 | { | |
997 | pc += 2; | |
8defab1a | 998 | target_read_memory (pc, &op, 1); |
e11481da PM |
999 | check = 1; |
1000 | } | |
1001 | } | |
1002 | } | |
1003 | return pc; | |
1004 | } | |
1005 | ||
acd5c798 MK |
1006 | /* Check whether PC points at a code that sets up a new stack frame. |
1007 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1008 | instruction after the sequence that sets up the frame or LIMIT, |
1009 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1010 | |
1011 | static CORE_ADDR | |
e17a4113 UW |
1012 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1013 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1014 | struct i386_frame_cache *cache) |
1015 | { | |
e17a4113 | 1016 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1017 | struct i386_insn *insn; |
63c0089f | 1018 | gdb_byte op; |
26604a34 | 1019 | int skip = 0; |
acd5c798 | 1020 | |
37bdc87e MK |
1021 | if (limit <= pc) |
1022 | return limit; | |
acd5c798 | 1023 | |
8defab1a | 1024 | target_read_memory (pc, &op, 1); |
acd5c798 | 1025 | |
c906108c | 1026 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1027 | { |
acd5c798 MK |
1028 | /* Take into account that we've executed the `pushl %ebp' that |
1029 | starts this instruction sequence. */ | |
fd13a04a | 1030 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1031 | cache->sp_offset += 4; |
37bdc87e | 1032 | pc++; |
acd5c798 MK |
1033 | |
1034 | /* If that's all, return now. */ | |
37bdc87e MK |
1035 | if (limit <= pc) |
1036 | return limit; | |
26604a34 | 1037 | |
b4632131 | 1038 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1039 | GCC into the prologue and skip them. At this point in the |
1040 | prologue, code should only touch the scratch registers %eax, | |
1041 | %ecx and %edx, so while the number of posibilities is sheer, | |
1042 | it is limited. | |
5daa5b4e | 1043 | |
26604a34 MK |
1044 | Make sure we only skip these instructions if we later see the |
1045 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1046 | while (pc + skip < limit) |
26604a34 | 1047 | { |
37bdc87e MK |
1048 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1049 | if (insn == NULL) | |
1050 | break; | |
b4632131 | 1051 | |
37bdc87e | 1052 | skip += insn->len; |
26604a34 MK |
1053 | } |
1054 | ||
37bdc87e MK |
1055 | /* If that's all, return now. */ |
1056 | if (limit <= pc + skip) | |
1057 | return limit; | |
1058 | ||
8defab1a | 1059 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1060 | |
26604a34 | 1061 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1062 | switch (op) |
c906108c SS |
1063 | { |
1064 | case 0x8b: | |
e17a4113 UW |
1065 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1066 | != 0xec) | |
37bdc87e | 1067 | return pc; |
c906108c SS |
1068 | break; |
1069 | case 0x89: | |
e17a4113 UW |
1070 | if (read_memory_unsigned_integer (pc + skip + 1, 1, byte_order) |
1071 | != 0xe5) | |
37bdc87e | 1072 | return pc; |
c906108c SS |
1073 | break; |
1074 | default: | |
37bdc87e | 1075 | return pc; |
c906108c | 1076 | } |
acd5c798 | 1077 | |
26604a34 MK |
1078 | /* OK, we actually have a frame. We just don't know how large |
1079 | it is yet. Set its size to zero. We'll adjust it if | |
1080 | necessary. We also now commit to skipping the special | |
1081 | instructions mentioned before. */ | |
acd5c798 | 1082 | cache->locals = 0; |
37bdc87e | 1083 | pc += (skip + 2); |
acd5c798 MK |
1084 | |
1085 | /* If that's all, return now. */ | |
37bdc87e MK |
1086 | if (limit <= pc) |
1087 | return limit; | |
acd5c798 | 1088 | |
fc338970 MK |
1089 | /* Check for stack adjustment |
1090 | ||
acd5c798 | 1091 | subl $XXX, %esp |
fc338970 | 1092 | |
fd35795f | 1093 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1094 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1095 | target_read_memory (pc, &op, 1); |
c906108c SS |
1096 | if (op == 0x83) |
1097 | { | |
fd35795f | 1098 | /* `subl' with 8-bit immediate. */ |
e17a4113 | 1099 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1100 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1101 | return pc; |
acd5c798 | 1102 | |
37bdc87e MK |
1103 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1104 | make sense to be negative). */ | |
e17a4113 | 1105 | cache->locals = read_memory_integer (pc + 2, 1, byte_order); |
37bdc87e | 1106 | return pc + 3; |
c906108c SS |
1107 | } |
1108 | else if (op == 0x81) | |
1109 | { | |
fd35795f | 1110 | /* Maybe it is `subl' with a 32-bit immediate. */ |
e17a4113 | 1111 | if (read_memory_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1112 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1113 | return pc; |
acd5c798 | 1114 | |
fd35795f | 1115 | /* It is `subl' with a 32-bit immediate. */ |
e17a4113 | 1116 | cache->locals = read_memory_integer (pc + 2, 4, byte_order); |
37bdc87e | 1117 | return pc + 6; |
c906108c SS |
1118 | } |
1119 | else | |
1120 | { | |
acd5c798 | 1121 | /* Some instruction other than `subl'. */ |
37bdc87e | 1122 | return pc; |
c906108c SS |
1123 | } |
1124 | } | |
37bdc87e | 1125 | else if (op == 0xc8) /* enter */ |
c906108c | 1126 | { |
e17a4113 | 1127 | cache->locals = read_memory_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1128 | return pc + 4; |
c906108c | 1129 | } |
21d0e8a4 | 1130 | |
acd5c798 | 1131 | return pc; |
21d0e8a4 MK |
1132 | } |
1133 | ||
acd5c798 MK |
1134 | /* Check whether PC points at code that saves registers on the stack. |
1135 | If so, it updates CACHE and returns the address of the first | |
1136 | instruction after the register saves or CURRENT_PC, whichever is | |
1137 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1138 | |
1139 | static CORE_ADDR | |
acd5c798 MK |
1140 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1141 | struct i386_frame_cache *cache) | |
6bff26de | 1142 | { |
99ab4326 | 1143 | CORE_ADDR offset = 0; |
63c0089f | 1144 | gdb_byte op; |
99ab4326 | 1145 | int i; |
c0d1d883 | 1146 | |
99ab4326 MK |
1147 | if (cache->locals > 0) |
1148 | offset -= cache->locals; | |
1149 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1150 | { | |
8defab1a | 1151 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1152 | if (op < 0x50 || op > 0x57) |
1153 | break; | |
0d17c81d | 1154 | |
99ab4326 MK |
1155 | offset -= 4; |
1156 | cache->saved_regs[op - 0x50] = offset; | |
1157 | cache->sp_offset += 4; | |
1158 | pc++; | |
6bff26de MK |
1159 | } |
1160 | ||
acd5c798 | 1161 | return pc; |
22797942 AC |
1162 | } |
1163 | ||
acd5c798 MK |
1164 | /* Do a full analysis of the prologue at PC and update CACHE |
1165 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1166 | address where the analysis stopped. | |
ed84f6c1 | 1167 | |
fc338970 MK |
1168 | We handle these cases: |
1169 | ||
1170 | The startup sequence can be at the start of the function, or the | |
1171 | function can start with a branch to startup code at the end. | |
1172 | ||
1173 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1174 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1175 | once used in the System V compiler). | |
1176 | ||
1177 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1178 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1179 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1180 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1181 | |
1182 | Next, the registers used by this function are pushed. With the | |
1183 | System V compiler they will always be in the order: %edi, %esi, | |
1184 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1185 | restore %eax); however, the code below is willing to see the pushes | |
1186 | in any order, and will handle up to 8 of them. | |
1187 | ||
1188 | If the setup sequence is at the end of the function, then the next | |
1189 | instruction will be a branch back to the start. */ | |
c906108c | 1190 | |
acd5c798 | 1191 | static CORE_ADDR |
e17a4113 UW |
1192 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1193 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1194 | struct i386_frame_cache *cache) |
c906108c | 1195 | { |
e11481da | 1196 | pc = i386_skip_noop (pc); |
e17a4113 | 1197 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1198 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1199 | pc = i386_skip_probe (pc); | |
92dd43fa | 1200 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1201 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1202 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1203 | } |
1204 | ||
fc338970 | 1205 | /* Return PC of first real instruction. */ |
c906108c | 1206 | |
3a1e71e3 | 1207 | static CORE_ADDR |
6093d2eb | 1208 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1209 | { |
e17a4113 UW |
1210 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1211 | ||
63c0089f | 1212 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1213 | { |
1214 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1215 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1216 | }; |
acd5c798 MK |
1217 | struct i386_frame_cache cache; |
1218 | CORE_ADDR pc; | |
63c0089f | 1219 | gdb_byte op; |
acd5c798 | 1220 | int i; |
c5aa993b | 1221 | |
acd5c798 | 1222 | cache.locals = -1; |
e17a4113 | 1223 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1224 | if (cache.locals < 0) |
1225 | return start_pc; | |
c5aa993b | 1226 | |
acd5c798 | 1227 | /* Found valid frame setup. */ |
c906108c | 1228 | |
fc338970 MK |
1229 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1230 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1231 | %ebx: |
1232 | ||
fc338970 MK |
1233 | call 0x0 |
1234 | popl %ebx | |
1235 | movl %ebx,x(%ebp) (optional) | |
1236 | addl y,%ebx | |
1237 | ||
c906108c SS |
1238 | This code is with the rest of the prologue (at the end of the |
1239 | function), so we have to skip it to get to the first real | |
1240 | instruction at the start of the function. */ | |
c5aa993b | 1241 | |
c906108c SS |
1242 | for (i = 0; i < 6; i++) |
1243 | { | |
8defab1a | 1244 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1245 | if (pic_pat[i] != op) |
c906108c SS |
1246 | break; |
1247 | } | |
1248 | if (i == 6) | |
1249 | { | |
acd5c798 MK |
1250 | int delta = 6; |
1251 | ||
8defab1a | 1252 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1253 | |
c5aa993b | 1254 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1255 | { |
e17a4113 | 1256 | op = read_memory_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1257 | |
fc338970 | 1258 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1259 | delta += 3; |
fc338970 | 1260 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1261 | delta += 6; |
fc338970 | 1262 | else /* Unexpected instruction. */ |
acd5c798 MK |
1263 | delta = 0; |
1264 | ||
8defab1a | 1265 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1266 | } |
acd5c798 | 1267 | |
c5aa993b | 1268 | /* addl y,%ebx */ |
acd5c798 | 1269 | if (delta > 0 && op == 0x81 |
e17a4113 UW |
1270 | && read_memory_unsigned_integer (pc + delta + 1, 1, byte_order) |
1271 | == 0xc3) | |
c906108c | 1272 | { |
acd5c798 | 1273 | pc += delta + 6; |
c906108c SS |
1274 | } |
1275 | } | |
c5aa993b | 1276 | |
e63bbc88 MK |
1277 | /* If the function starts with a branch (to startup code at the end) |
1278 | the last instruction should bring us back to the first | |
1279 | instruction of the real code. */ | |
e17a4113 UW |
1280 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1281 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1282 | |
1283 | return pc; | |
c906108c SS |
1284 | } |
1285 | ||
4309257c PM |
1286 | /* Check that the code pointed to by PC corresponds to a call to |
1287 | __main, skip it if so. Return PC otherwise. */ | |
1288 | ||
1289 | CORE_ADDR | |
1290 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1291 | { | |
e17a4113 | 1292 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1293 | gdb_byte op; |
1294 | ||
1295 | target_read_memory (pc, &op, 1); | |
1296 | if (op == 0xe8) | |
1297 | { | |
1298 | gdb_byte buf[4]; | |
1299 | ||
1300 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1301 | { | |
1302 | /* Make sure address is computed correctly as a 32bit | |
1303 | integer even if CORE_ADDR is 64 bit wide. */ | |
1304 | struct minimal_symbol *s; | |
e17a4113 | 1305 | CORE_ADDR call_dest; |
4309257c | 1306 | |
e17a4113 | 1307 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1308 | call_dest = call_dest & 0xffffffffU; |
1309 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1310 | if (s != NULL | |
1311 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1312 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1313 | pc += 5; | |
1314 | } | |
1315 | } | |
1316 | ||
1317 | return pc; | |
1318 | } | |
1319 | ||
acd5c798 | 1320 | /* This function is 64-bit safe. */ |
93924b6b | 1321 | |
acd5c798 MK |
1322 | static CORE_ADDR |
1323 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1324 | { |
63c0089f | 1325 | gdb_byte buf[8]; |
acd5c798 | 1326 | |
875f8d0e | 1327 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1328 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1329 | } |
acd5c798 | 1330 | \f |
93924b6b | 1331 | |
acd5c798 | 1332 | /* Normal frames. */ |
c5aa993b | 1333 | |
acd5c798 | 1334 | static struct i386_frame_cache * |
10458914 | 1335 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1336 | { |
e17a4113 UW |
1337 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1338 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1339 | struct i386_frame_cache *cache; |
63c0089f | 1340 | gdb_byte buf[4]; |
acd5c798 MK |
1341 | int i; |
1342 | ||
1343 | if (*this_cache) | |
1344 | return *this_cache; | |
1345 | ||
fd13a04a | 1346 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1347 | *this_cache = cache; |
1348 | ||
1349 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1350 | which holds the base address for the current stack frame. | |
1351 | However, for functions that don't need it, the frame pointer is | |
1352 | optional. For these "frameless" functions the frame pointer is | |
1353 | actually the frame pointer of the calling frame. Signal | |
1354 | trampolines are just a special case of a "frameless" function. | |
1355 | They (usually) share their frame pointer with the frame that was | |
1356 | in progress when the signal occurred. */ | |
1357 | ||
10458914 | 1358 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1359 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 MK |
1360 | if (cache->base == 0) |
1361 | return cache; | |
1362 | ||
1363 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1364 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1365 | |
10458914 | 1366 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1367 | if (cache->pc != 0) |
e17a4113 UW |
1368 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1369 | cache); | |
acd5c798 | 1370 | |
e0c62198 | 1371 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1372 | { |
e0c62198 L |
1373 | /* Saved stack pointer has been saved. */ |
1374 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
e17a4113 | 1375 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
92dd43fa MK |
1376 | } |
1377 | ||
acd5c798 MK |
1378 | if (cache->locals < 0) |
1379 | { | |
1380 | /* We didn't find a valid frame, which means that CACHE->base | |
1381 | currently holds the frame pointer for our calling frame. If | |
1382 | we're at the start of a function, or somewhere half-way its | |
1383 | prologue, the function's frame probably hasn't been fully | |
1384 | setup yet. Try to reconstruct the base address for the stack | |
1385 | frame by looking at the stack pointer. For truly "frameless" | |
1386 | functions this might work too. */ | |
1387 | ||
e0c62198 | 1388 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1389 | { |
1390 | /* We're halfway aligning the stack. */ | |
1391 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1392 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1393 | ||
1394 | /* This will be added back below. */ | |
1395 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1396 | } | |
1397 | else | |
1398 | { | |
10458914 | 1399 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
1400 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
1401 | + cache->sp_offset; | |
92dd43fa | 1402 | } |
acd5c798 MK |
1403 | } |
1404 | ||
1405 | /* Now that we have the base address for the stack frame we can | |
1406 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1407 | if (cache->saved_sp == 0) |
1408 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1409 | |
acd5c798 MK |
1410 | /* Adjust all the saved registers such that they contain addresses |
1411 | instead of offsets. */ | |
1412 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1413 | if (cache->saved_regs[i] != -1) |
1414 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1415 | |
1416 | return cache; | |
a7769679 MK |
1417 | } |
1418 | ||
3a1e71e3 | 1419 | static void |
10458914 | 1420 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1421 | struct frame_id *this_id) |
c906108c | 1422 | { |
10458914 | 1423 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1424 | |
1425 | /* This marks the outermost frame. */ | |
1426 | if (cache->base == 0) | |
1427 | return; | |
1428 | ||
3e210248 | 1429 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1430 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1431 | } | |
1432 | ||
10458914 DJ |
1433 | static struct value * |
1434 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1435 | int regnum) | |
acd5c798 | 1436 | { |
10458914 | 1437 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1438 | |
1439 | gdb_assert (regnum >= 0); | |
1440 | ||
1441 | /* The System V ABI says that: | |
1442 | ||
1443 | "The flags register contains the system flags, such as the | |
1444 | direction flag and the carry flag. The direction flag must be | |
1445 | set to the forward (that is, zero) direction before entry and | |
1446 | upon exit from a function. Other user flags have no specified | |
1447 | role in the standard calling sequence and are not preserved." | |
1448 | ||
1449 | To guarantee the "upon exit" part of that statement we fake a | |
1450 | saved flags register that has its direction flag cleared. | |
1451 | ||
1452 | Note that GCC doesn't seem to rely on the fact that the direction | |
1453 | flag is cleared after a function return; it always explicitly | |
1454 | clears the flag before operations where it matters. | |
1455 | ||
1456 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1457 | right thing to do. The way we fake the flags register here makes | |
1458 | it impossible to change it. */ | |
1459 | ||
1460 | if (regnum == I386_EFLAGS_REGNUM) | |
1461 | { | |
10458914 | 1462 | ULONGEST val; |
c5aa993b | 1463 | |
10458914 DJ |
1464 | val = get_frame_register_unsigned (this_frame, regnum); |
1465 | val &= ~(1 << 10); | |
1466 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1467 | } |
1211c4e4 | 1468 | |
acd5c798 | 1469 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1470 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1471 | |
1472 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1473 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1474 | |
fd13a04a | 1475 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1476 | return frame_unwind_got_memory (this_frame, regnum, |
1477 | cache->saved_regs[regnum]); | |
fd13a04a | 1478 | |
10458914 | 1479 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1480 | } |
1481 | ||
1482 | static const struct frame_unwind i386_frame_unwind = | |
1483 | { | |
1484 | NORMAL_FRAME, | |
1485 | i386_frame_this_id, | |
10458914 DJ |
1486 | i386_frame_prev_register, |
1487 | NULL, | |
1488 | default_frame_sniffer | |
acd5c798 | 1489 | }; |
06da04c6 MS |
1490 | |
1491 | /* Normal frames, but in a function epilogue. */ | |
1492 | ||
1493 | /* The epilogue is defined here as the 'ret' instruction, which will | |
1494 | follow any instruction such as 'leave' or 'pop %ebp' that destroys | |
1495 | the function's stack frame. */ | |
1496 | ||
1497 | static int | |
1498 | i386_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1499 | { | |
1500 | gdb_byte insn; | |
1501 | ||
1502 | if (target_read_memory (pc, &insn, 1)) | |
1503 | return 0; /* Can't read memory at pc. */ | |
1504 | ||
1505 | if (insn != 0xc3) /* 'ret' instruction. */ | |
1506 | return 0; | |
1507 | ||
1508 | return 1; | |
1509 | } | |
1510 | ||
1511 | static int | |
1512 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
1513 | struct frame_info *this_frame, | |
1514 | void **this_prologue_cache) | |
1515 | { | |
1516 | if (frame_relative_level (this_frame) == 0) | |
1517 | return i386_in_function_epilogue_p (get_frame_arch (this_frame), | |
1518 | get_frame_pc (this_frame)); | |
1519 | else | |
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | static struct i386_frame_cache * | |
1524 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
1525 | { | |
1526 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1527 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1528 | struct i386_frame_cache *cache; | |
1529 | gdb_byte buf[4]; | |
1530 | ||
1531 | if (*this_cache) | |
1532 | return *this_cache; | |
1533 | ||
1534 | cache = i386_alloc_frame_cache (); | |
1535 | *this_cache = cache; | |
1536 | ||
1537 | /* Cache base will be %esp plus cache->sp_offset (-4). */ | |
1538 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); | |
1539 | cache->base = extract_unsigned_integer (buf, 4, | |
1540 | byte_order) + cache->sp_offset; | |
1541 | ||
1542 | /* Cache pc will be the frame func. */ | |
1543 | cache->pc = get_frame_pc (this_frame); | |
1544 | ||
1545 | /* The saved %esp will be at cache->base plus 8. */ | |
1546 | cache->saved_sp = cache->base + 8; | |
1547 | ||
1548 | /* The saved %eip will be at cache->base plus 4. */ | |
1549 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; | |
1550 | ||
1551 | return cache; | |
1552 | } | |
1553 | ||
1554 | static void | |
1555 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
1556 | void **this_cache, | |
1557 | struct frame_id *this_id) | |
1558 | { | |
1559 | struct i386_frame_cache *cache = i386_epilogue_frame_cache (this_frame, | |
1560 | this_cache); | |
1561 | ||
1562 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
1563 | } | |
1564 | ||
1565 | static const struct frame_unwind i386_epilogue_frame_unwind = | |
1566 | { | |
1567 | NORMAL_FRAME, | |
1568 | i386_epilogue_frame_this_id, | |
1569 | i386_frame_prev_register, | |
1570 | NULL, | |
1571 | i386_epilogue_frame_sniffer | |
1572 | }; | |
acd5c798 MK |
1573 | \f |
1574 | ||
1575 | /* Signal trampolines. */ | |
1576 | ||
1577 | static struct i386_frame_cache * | |
10458914 | 1578 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1579 | { |
e17a4113 UW |
1580 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1581 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1582 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 1583 | struct i386_frame_cache *cache; |
acd5c798 | 1584 | CORE_ADDR addr; |
63c0089f | 1585 | gdb_byte buf[4]; |
acd5c798 MK |
1586 | |
1587 | if (*this_cache) | |
1588 | return *this_cache; | |
1589 | ||
fd13a04a | 1590 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1591 | |
10458914 | 1592 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1593 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; |
acd5c798 | 1594 | |
10458914 | 1595 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1596 | if (tdep->sc_reg_offset) |
1597 | { | |
1598 | int i; | |
1599 | ||
1600 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1601 | ||
1602 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1603 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1604 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1605 | } |
1606 | else | |
1607 | { | |
fd13a04a AC |
1608 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1609 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1610 | } |
acd5c798 MK |
1611 | |
1612 | *this_cache = cache; | |
1613 | return cache; | |
1614 | } | |
1615 | ||
1616 | static void | |
10458914 | 1617 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1618 | struct frame_id *this_id) |
1619 | { | |
1620 | struct i386_frame_cache *cache = | |
10458914 | 1621 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1622 | |
3e210248 | 1623 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1624 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1625 | } |
1626 | ||
10458914 DJ |
1627 | static struct value * |
1628 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1629 | void **this_cache, int regnum) | |
acd5c798 MK |
1630 | { |
1631 | /* Make sure we've initialized the cache. */ | |
10458914 | 1632 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1633 | |
10458914 | 1634 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1635 | } |
c0d1d883 | 1636 | |
10458914 DJ |
1637 | static int |
1638 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1639 | struct frame_info *this_frame, | |
1640 | void **this_prologue_cache) | |
acd5c798 | 1641 | { |
10458914 | 1642 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1643 | |
911bc6ee MK |
1644 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1645 | handler. */ | |
1646 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1647 | return 0; |
1c3545ae | 1648 | |
911bc6ee MK |
1649 | if (tdep->sigtramp_p != NULL) |
1650 | { | |
10458914 DJ |
1651 | if (tdep->sigtramp_p (this_frame)) |
1652 | return 1; | |
911bc6ee MK |
1653 | } |
1654 | ||
1655 | if (tdep->sigtramp_start != 0) | |
1656 | { | |
10458914 | 1657 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1658 | |
1659 | gdb_assert (tdep->sigtramp_end != 0); | |
1660 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1661 | return 1; |
911bc6ee | 1662 | } |
acd5c798 | 1663 | |
10458914 | 1664 | return 0; |
acd5c798 | 1665 | } |
10458914 DJ |
1666 | |
1667 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1668 | { | |
1669 | SIGTRAMP_FRAME, | |
1670 | i386_sigtramp_frame_this_id, | |
1671 | i386_sigtramp_frame_prev_register, | |
1672 | NULL, | |
1673 | i386_sigtramp_frame_sniffer | |
1674 | }; | |
acd5c798 MK |
1675 | \f |
1676 | ||
1677 | static CORE_ADDR | |
10458914 | 1678 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1679 | { |
10458914 | 1680 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1681 | |
1682 | return cache->base; | |
1683 | } | |
1684 | ||
1685 | static const struct frame_base i386_frame_base = | |
1686 | { | |
1687 | &i386_frame_unwind, | |
1688 | i386_frame_base_address, | |
1689 | i386_frame_base_address, | |
1690 | i386_frame_base_address | |
1691 | }; | |
1692 | ||
acd5c798 | 1693 | static struct frame_id |
10458914 | 1694 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1695 | { |
acd5c798 MK |
1696 | CORE_ADDR fp; |
1697 | ||
10458914 | 1698 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1699 | |
3e210248 | 1700 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1701 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1702 | } |
fc338970 | 1703 | \f |
c906108c | 1704 | |
fc338970 MK |
1705 | /* Figure out where the longjmp will land. Slurp the args out of the |
1706 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1707 | structure from which we extract the address that we will land at. |
28bcfd30 | 1708 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1709 | success. */ |
c906108c | 1710 | |
8201327c | 1711 | static int |
60ade65d | 1712 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1713 | { |
436675d3 | 1714 | gdb_byte buf[4]; |
c906108c | 1715 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 1716 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 1717 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 1718 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 1719 | |
8201327c MK |
1720 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1721 | longjmp will land. */ | |
1722 | if (jb_pc_offset == -1) | |
c906108c SS |
1723 | return 0; |
1724 | ||
436675d3 | 1725 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 1726 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1727 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
1728 | return 0; |
1729 | ||
e17a4113 | 1730 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 1731 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 1732 | return 0; |
c906108c | 1733 | |
e17a4113 | 1734 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
1735 | return 1; |
1736 | } | |
fc338970 | 1737 | \f |
c906108c | 1738 | |
7ccc1c74 JM |
1739 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1740 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1741 | unions containing such types must be 16-byte-aligned; other | |
1742 | arguments are 4-byte-aligned. */ | |
1743 | ||
1744 | static int | |
1745 | i386_16_byte_align_p (struct type *type) | |
1746 | { | |
1747 | type = check_typedef (type); | |
1748 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1749 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1750 | && TYPE_LENGTH (type) == 16) | |
1751 | return 1; | |
1752 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1753 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1754 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1755 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1756 | { | |
1757 | int i; | |
1758 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1759 | { | |
1760 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1761 | return 1; | |
1762 | } | |
1763 | } | |
1764 | return 0; | |
1765 | } | |
1766 | ||
3a1e71e3 | 1767 | static CORE_ADDR |
7d9b040b | 1768 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1769 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1770 | struct value **args, CORE_ADDR sp, int struct_return, | |
1771 | CORE_ADDR struct_addr) | |
22f8ba57 | 1772 | { |
e17a4113 | 1773 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1774 | gdb_byte buf[4]; |
acd5c798 | 1775 | int i; |
7ccc1c74 JM |
1776 | int write_pass; |
1777 | int args_space = 0; | |
acd5c798 | 1778 | |
7ccc1c74 JM |
1779 | /* Determine the total space required for arguments and struct |
1780 | return address in a first pass (allowing for 16-byte-aligned | |
1781 | arguments), then push arguments in a second pass. */ | |
1782 | ||
1783 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1784 | { |
7ccc1c74 JM |
1785 | int args_space_used = 0; |
1786 | int have_16_byte_aligned_arg = 0; | |
1787 | ||
1788 | if (struct_return) | |
1789 | { | |
1790 | if (write_pass) | |
1791 | { | |
1792 | /* Push value address. */ | |
e17a4113 | 1793 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
1794 | write_memory (sp, buf, 4); |
1795 | args_space_used += 4; | |
1796 | } | |
1797 | else | |
1798 | args_space += 4; | |
1799 | } | |
1800 | ||
1801 | for (i = 0; i < nargs; i++) | |
1802 | { | |
1803 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1804 | |
7ccc1c74 JM |
1805 | if (write_pass) |
1806 | { | |
1807 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1808 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1809 | |
7ccc1c74 JM |
1810 | write_memory (sp + args_space_used, |
1811 | value_contents_all (args[i]), len); | |
1812 | /* The System V ABI says that: | |
acd5c798 | 1813 | |
7ccc1c74 JM |
1814 | "An argument's size is increased, if necessary, to make it a |
1815 | multiple of [32-bit] words. This may require tail padding, | |
1816 | depending on the size of the argument." | |
22f8ba57 | 1817 | |
7ccc1c74 JM |
1818 | This makes sure the stack stays word-aligned. */ |
1819 | args_space_used += align_up (len, 4); | |
1820 | } | |
1821 | else | |
1822 | { | |
1823 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1824 | { | |
1825 | args_space = align_up (args_space, 16); | |
1826 | have_16_byte_aligned_arg = 1; | |
1827 | } | |
1828 | args_space += align_up (len, 4); | |
1829 | } | |
1830 | } | |
1831 | ||
1832 | if (!write_pass) | |
1833 | { | |
1834 | if (have_16_byte_aligned_arg) | |
1835 | args_space = align_up (args_space, 16); | |
1836 | sp -= args_space; | |
1837 | } | |
22f8ba57 MK |
1838 | } |
1839 | ||
acd5c798 MK |
1840 | /* Store return address. */ |
1841 | sp -= 4; | |
e17a4113 | 1842 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
1843 | write_memory (sp, buf, 4); |
1844 | ||
1845 | /* Finally, update the stack pointer... */ | |
e17a4113 | 1846 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
1847 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
1848 | ||
1849 | /* ...and fake a frame pointer. */ | |
1850 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1851 | ||
3e210248 AC |
1852 | /* MarkK wrote: This "+ 8" is all over the place: |
1853 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1854 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1855 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1856 | definition of the stack address of a frame. Otherwise frame id |
1857 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1858 | stack address *before* the function call as a frame's CFA. On |
1859 | the i386, when %ebp is used as a frame pointer, the offset | |
1860 | between the contents %ebp and the CFA as defined by GCC. */ | |
1861 | return sp + 8; | |
22f8ba57 MK |
1862 | } |
1863 | ||
1a309862 MK |
1864 | /* These registers are used for returning integers (and on some |
1865 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1866 | size and alignment match an integer type). */ |
acd5c798 MK |
1867 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1868 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1869 | |
c5e656c1 MK |
1870 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1871 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1872 | |
3a1e71e3 | 1873 | static void |
c5e656c1 | 1874 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1875 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1876 | { |
c5e656c1 | 1877 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1878 | int len = TYPE_LENGTH (type); |
63c0089f | 1879 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1880 | |
1e8d0a7b | 1881 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1882 | { |
5716833c | 1883 | if (tdep->st0_regnum < 0) |
1a309862 | 1884 | { |
8a3fe4f8 | 1885 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1886 | memset (valbuf, 0, len); |
ef9dff19 | 1887 | return; |
1a309862 MK |
1888 | } |
1889 | ||
c6ba6f0d MK |
1890 | /* Floating-point return values can be found in %st(0). Convert |
1891 | its contents to the desired type. This is probably not | |
1892 | exactly how it would happen on the target itself, but it is | |
1893 | the best we can do. */ | |
acd5c798 | 1894 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 1895 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
1896 | } |
1897 | else | |
c5aa993b | 1898 | { |
875f8d0e UW |
1899 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1900 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1901 | |
1902 | if (len <= low_size) | |
00f8375e | 1903 | { |
0818c12a | 1904 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1905 | memcpy (valbuf, buf, len); |
1906 | } | |
d4f3574e SS |
1907 | else if (len <= (low_size + high_size)) |
1908 | { | |
0818c12a | 1909 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1910 | memcpy (valbuf, buf, low_size); |
0818c12a | 1911 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1912 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1913 | } |
1914 | else | |
8e65ff28 | 1915 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1916 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1917 | } |
1918 | } | |
1919 | ||
c5e656c1 MK |
1920 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1921 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1922 | |
3a1e71e3 | 1923 | static void |
c5e656c1 | 1924 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1925 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1926 | { |
c5e656c1 | 1927 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1928 | int len = TYPE_LENGTH (type); |
1929 | ||
1e8d0a7b | 1930 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1931 | { |
3d7f4f49 | 1932 | ULONGEST fstat; |
63c0089f | 1933 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1934 | |
5716833c | 1935 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1936 | { |
8a3fe4f8 | 1937 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1938 | return; |
1939 | } | |
1940 | ||
635b0cc1 MK |
1941 | /* Returning floating-point values is a bit tricky. Apart from |
1942 | storing the return value in %st(0), we have to simulate the | |
1943 | state of the FPU at function return point. */ | |
1944 | ||
c6ba6f0d MK |
1945 | /* Convert the value found in VALBUF to the extended |
1946 | floating-point format used by the FPU. This is probably | |
1947 | not exactly how it would happen on the target itself, but | |
1948 | it is the best we can do. */ | |
27067745 | 1949 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 1950 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1951 | |
635b0cc1 MK |
1952 | /* Set the top of the floating-point register stack to 7. The |
1953 | actual value doesn't really matter, but 7 is what a normal | |
1954 | function return would end up with if the program started out | |
1955 | with a freshly initialized FPU. */ | |
20a6ec49 | 1956 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1957 | fstat |= (7 << 11); |
20a6ec49 | 1958 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1959 | |
635b0cc1 MK |
1960 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1961 | the floating-point register stack to 7, the appropriate value | |
1962 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1963 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1964 | } |
1965 | else | |
1966 | { | |
875f8d0e UW |
1967 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1968 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1969 | |
1970 | if (len <= low_size) | |
3d7f4f49 | 1971 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1972 | else if (len <= (low_size + high_size)) |
1973 | { | |
3d7f4f49 MK |
1974 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1975 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1976 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1977 | } |
1978 | else | |
8e65ff28 | 1979 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1980 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1981 | } |
1982 | } | |
fc338970 | 1983 | \f |
ef9dff19 | 1984 | |
8201327c MK |
1985 | /* This is the variable that is set with "set struct-convention", and |
1986 | its legitimate values. */ | |
1987 | static const char default_struct_convention[] = "default"; | |
1988 | static const char pcc_struct_convention[] = "pcc"; | |
1989 | static const char reg_struct_convention[] = "reg"; | |
1990 | static const char *valid_conventions[] = | |
1991 | { | |
1992 | default_struct_convention, | |
1993 | pcc_struct_convention, | |
1994 | reg_struct_convention, | |
1995 | NULL | |
1996 | }; | |
1997 | static const char *struct_convention = default_struct_convention; | |
1998 | ||
0e4377e1 JB |
1999 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2000 | a union type, or an array type, should be returned in registers | |
2001 | for architecture GDBARCH. */ | |
c5e656c1 | 2002 | |
8201327c | 2003 | static int |
c5e656c1 | 2004 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2005 | { |
c5e656c1 MK |
2006 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2007 | enum type_code code = TYPE_CODE (type); | |
2008 | int len = TYPE_LENGTH (type); | |
8201327c | 2009 | |
0e4377e1 JB |
2010 | gdb_assert (code == TYPE_CODE_STRUCT |
2011 | || code == TYPE_CODE_UNION | |
2012 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2013 | |
2014 | if (struct_convention == pcc_struct_convention | |
2015 | || (struct_convention == default_struct_convention | |
2016 | && tdep->struct_return == pcc_struct_return)) | |
2017 | return 0; | |
2018 | ||
9edde48e MK |
2019 | /* Structures consisting of a single `float', `double' or 'long |
2020 | double' member are returned in %st(0). */ | |
2021 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2022 | { | |
2023 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2024 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2025 | return (len == 4 || len == 8 || len == 12); | |
2026 | } | |
2027 | ||
c5e656c1 MK |
2028 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2029 | } | |
2030 | ||
2031 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2032 | should be returned. If it is supposed to be returned in registers, | |
2033 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2034 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2035 | from WRITEBUF into REGCACHE. */ | |
2036 | ||
2037 | static enum return_value_convention | |
c055b101 CV |
2038 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
2039 | struct type *type, struct regcache *regcache, | |
2040 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2041 | { |
2042 | enum type_code code = TYPE_CODE (type); | |
2043 | ||
5daa78cc TJB |
2044 | if (((code == TYPE_CODE_STRUCT |
2045 | || code == TYPE_CODE_UNION | |
2046 | || code == TYPE_CODE_ARRAY) | |
2047 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2048 | /* 128-bit decimal float uses the struct return convention. */ | |
2049 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2050 | { |
2051 | /* The System V ABI says that: | |
2052 | ||
2053 | "A function that returns a structure or union also sets %eax | |
2054 | to the value of the original address of the caller's area | |
2055 | before it returns. Thus when the caller receives control | |
2056 | again, the address of the returned object resides in register | |
2057 | %eax and can be used to access the object." | |
2058 | ||
2059 | So the ABI guarantees that we can always find the return | |
2060 | value just after the function has returned. */ | |
2061 | ||
0e4377e1 JB |
2062 | /* Note that the ABI doesn't mention functions returning arrays, |
2063 | which is something possible in certain languages such as Ada. | |
2064 | In this case, the value is returned as if it was wrapped in | |
2065 | a record, so the convention applied to records also applies | |
2066 | to arrays. */ | |
2067 | ||
31db7b6c MK |
2068 | if (readbuf) |
2069 | { | |
2070 | ULONGEST addr; | |
2071 | ||
2072 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2073 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2074 | } | |
2075 | ||
2076 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2077 | } | |
c5e656c1 MK |
2078 | |
2079 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2080 | `float', `double' or 'long double' member. These structures are |
2081 | returned in %st(0). For these structures, we call ourselves | |
2082 | recursively, changing TYPE into the type of the first member of | |
2083 | the structure. Since that should work for all structures that | |
2084 | have only one member, we don't bother to check the member's type | |
2085 | here. */ | |
c5e656c1 MK |
2086 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2087 | { | |
2088 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
2089 | return i386_return_value (gdbarch, func_type, type, regcache, |
2090 | readbuf, writebuf); | |
c5e656c1 MK |
2091 | } |
2092 | ||
2093 | if (readbuf) | |
2094 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2095 | if (writebuf) | |
2096 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2097 | |
c5e656c1 | 2098 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2099 | } |
2100 | \f | |
2101 | ||
209bd28e UW |
2102 | /* Construct types for ISA-specific registers. */ |
2103 | struct type * | |
2104 | i386_eflags_type (struct gdbarch *gdbarch) | |
2105 | { | |
2106 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5ae96ec1 | 2107 | |
209bd28e UW |
2108 | if (!tdep->i386_eflags_type) |
2109 | { | |
2110 | struct type *type; | |
2111 | ||
e9bb382b | 2112 | type = arch_flags_type (gdbarch, "builtin_type_i386_eflags", 4); |
209bd28e UW |
2113 | append_flags_type_flag (type, 0, "CF"); |
2114 | append_flags_type_flag (type, 1, NULL); | |
2115 | append_flags_type_flag (type, 2, "PF"); | |
2116 | append_flags_type_flag (type, 4, "AF"); | |
2117 | append_flags_type_flag (type, 6, "ZF"); | |
2118 | append_flags_type_flag (type, 7, "SF"); | |
2119 | append_flags_type_flag (type, 8, "TF"); | |
2120 | append_flags_type_flag (type, 9, "IF"); | |
2121 | append_flags_type_flag (type, 10, "DF"); | |
2122 | append_flags_type_flag (type, 11, "OF"); | |
2123 | append_flags_type_flag (type, 14, "NT"); | |
2124 | append_flags_type_flag (type, 16, "RF"); | |
2125 | append_flags_type_flag (type, 17, "VM"); | |
2126 | append_flags_type_flag (type, 18, "AC"); | |
2127 | append_flags_type_flag (type, 19, "VIF"); | |
2128 | append_flags_type_flag (type, 20, "VIP"); | |
2129 | append_flags_type_flag (type, 21, "ID"); | |
2130 | ||
2131 | tdep->i386_eflags_type = type; | |
2132 | } | |
5ae96ec1 | 2133 | |
209bd28e UW |
2134 | return tdep->i386_eflags_type; |
2135 | } | |
2136 | ||
2137 | struct type * | |
2138 | i386_mxcsr_type (struct gdbarch *gdbarch) | |
5ae96ec1 | 2139 | { |
209bd28e UW |
2140 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2141 | ||
2142 | if (!tdep->i386_mxcsr_type) | |
2143 | { | |
2144 | struct type *type; | |
2145 | ||
e9bb382b | 2146 | type = arch_flags_type (gdbarch, "builtin_type_i386_mxcsr", 4); |
209bd28e UW |
2147 | append_flags_type_flag (type, 0, "IE"); |
2148 | append_flags_type_flag (type, 1, "DE"); | |
2149 | append_flags_type_flag (type, 2, "ZE"); | |
2150 | append_flags_type_flag (type, 3, "OE"); | |
2151 | append_flags_type_flag (type, 4, "UE"); | |
2152 | append_flags_type_flag (type, 5, "PE"); | |
2153 | append_flags_type_flag (type, 6, "DAZ"); | |
2154 | append_flags_type_flag (type, 7, "IM"); | |
2155 | append_flags_type_flag (type, 8, "DM"); | |
2156 | append_flags_type_flag (type, 9, "ZM"); | |
2157 | append_flags_type_flag (type, 10, "OM"); | |
2158 | append_flags_type_flag (type, 11, "UM"); | |
2159 | append_flags_type_flag (type, 12, "PM"); | |
2160 | append_flags_type_flag (type, 15, "FZ"); | |
2161 | ||
2162 | tdep->i386_mxcsr_type = type; | |
2163 | } | |
2164 | ||
2165 | return tdep->i386_mxcsr_type; | |
21b4b2f2 JB |
2166 | } |
2167 | ||
27067745 UW |
2168 | struct type * |
2169 | i387_ext_type (struct gdbarch *gdbarch) | |
2170 | { | |
2171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2172 | ||
2173 | if (!tdep->i387_ext_type) | |
2174 | tdep->i387_ext_type | |
e9bb382b | 2175 | = arch_float_type (gdbarch, -1, "builtin_type_i387_ext", |
27067745 UW |
2176 | floatformats_i387_ext); |
2177 | ||
2178 | return tdep->i387_ext_type; | |
2179 | } | |
2180 | ||
794ac428 UW |
2181 | /* Construct vector type for MMX registers. */ |
2182 | struct type * | |
2183 | i386_mmx_type (struct gdbarch *gdbarch) | |
2184 | { | |
2185 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2186 | ||
2187 | if (!tdep->i386_mmx_type) | |
2188 | { | |
df4df182 UW |
2189 | const struct builtin_type *bt = builtin_type (gdbarch); |
2190 | ||
794ac428 UW |
2191 | /* The type we're building is this: */ |
2192 | #if 0 | |
2193 | union __gdb_builtin_type_vec64i | |
2194 | { | |
2195 | int64_t uint64; | |
2196 | int32_t v2_int32[2]; | |
2197 | int16_t v4_int16[4]; | |
2198 | int8_t v8_int8[8]; | |
2199 | }; | |
2200 | #endif | |
2201 | ||
2202 | struct type *t; | |
2203 | ||
e9bb382b UW |
2204 | t = arch_composite_type (gdbarch, |
2205 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
2206 | |
2207 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 2208 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2209 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2210 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2211 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2212 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2213 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2214 | |
876cecd0 | 2215 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2216 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2217 | tdep->i386_mmx_type = t; | |
2218 | } | |
2219 | ||
2220 | return tdep->i386_mmx_type; | |
2221 | } | |
2222 | ||
2223 | struct type * | |
2224 | i386_sse_type (struct gdbarch *gdbarch) | |
2225 | { | |
2226 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2227 | ||
2228 | if (!tdep->i386_sse_type) | |
2229 | { | |
df4df182 UW |
2230 | const struct builtin_type *bt = builtin_type (gdbarch); |
2231 | ||
794ac428 UW |
2232 | /* The type we're building is this: */ |
2233 | #if 0 | |
2234 | union __gdb_builtin_type_vec128i | |
2235 | { | |
2236 | int128_t uint128; | |
2237 | int64_t v2_int64[2]; | |
2238 | int32_t v4_int32[4]; | |
2239 | int16_t v8_int16[8]; | |
2240 | int8_t v16_int8[16]; | |
2241 | double v2_double[2]; | |
2242 | float v4_float[4]; | |
2243 | }; | |
2244 | #endif | |
2245 | ||
2246 | struct type *t; | |
2247 | ||
e9bb382b UW |
2248 | t = arch_composite_type (gdbarch, |
2249 | "__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
794ac428 | 2250 | append_composite_type_field (t, "v4_float", |
df4df182 | 2251 | init_vector_type (bt->builtin_float, 4)); |
794ac428 | 2252 | append_composite_type_field (t, "v2_double", |
df4df182 | 2253 | init_vector_type (bt->builtin_double, 2)); |
794ac428 | 2254 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2255 | init_vector_type (bt->builtin_int8, 16)); |
794ac428 | 2256 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2257 | init_vector_type (bt->builtin_int16, 8)); |
794ac428 | 2258 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2259 | init_vector_type (bt->builtin_int32, 4)); |
794ac428 | 2260 | append_composite_type_field (t, "v2_int64", |
df4df182 UW |
2261 | init_vector_type (bt->builtin_int64, 2)); |
2262 | append_composite_type_field (t, "uint128", bt->builtin_int128); | |
794ac428 | 2263 | |
876cecd0 | 2264 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2265 | TYPE_NAME (t) = "builtin_type_vec128i"; |
2266 | tdep->i386_sse_type = t; | |
2267 | } | |
2268 | ||
2269 | return tdep->i386_sse_type; | |
2270 | } | |
2271 | ||
d7a0d72c MK |
2272 | /* Return the GDB type object for the "standard" data type of data in |
2273 | register REGNUM. Perhaps %esi and %edi should go here, but | |
2274 | potentially they could be used for things other than address. */ | |
2275 | ||
3a1e71e3 | 2276 | static struct type * |
4e259f09 | 2277 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2278 | { |
ab533587 | 2279 | if (regnum == I386_EIP_REGNUM) |
0dfff4cb | 2280 | return builtin_type (gdbarch)->builtin_func_ptr; |
ab533587 | 2281 | |
5ae96ec1 | 2282 | if (regnum == I386_EFLAGS_REGNUM) |
209bd28e | 2283 | return i386_eflags_type (gdbarch); |
5ae96ec1 | 2284 | |
ab533587 | 2285 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) |
0dfff4cb | 2286 | return builtin_type (gdbarch)->builtin_data_ptr; |
d7a0d72c | 2287 | |
20a6ec49 | 2288 | if (i386_fp_regnum_p (gdbarch, regnum)) |
27067745 | 2289 | return i387_ext_type (gdbarch); |
d7a0d72c | 2290 | |
878d9193 | 2291 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
794ac428 | 2292 | return i386_mmx_type (gdbarch); |
878d9193 | 2293 | |
5716833c | 2294 | if (i386_sse_regnum_p (gdbarch, regnum)) |
794ac428 | 2295 | return i386_sse_type (gdbarch); |
d7a0d72c | 2296 | |
20a6ec49 | 2297 | if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch))) |
209bd28e | 2298 | return i386_mxcsr_type (gdbarch); |
878d9193 | 2299 | |
0dfff4cb | 2300 | return builtin_type (gdbarch)->builtin_int; |
d7a0d72c MK |
2301 | } |
2302 | ||
28fc6740 | 2303 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2304 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2305 | |
2306 | static int | |
c86c27af | 2307 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2308 | { |
5716833c MK |
2309 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2310 | int mmxreg, fpreg; | |
28fc6740 AC |
2311 | ULONGEST fstat; |
2312 | int tos; | |
c86c27af | 2313 | |
5716833c | 2314 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2315 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2316 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2317 | fpreg = (mmxreg + tos) % 8; |
2318 | ||
20a6ec49 | 2319 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2320 | } |
2321 | ||
2322 | static void | |
2323 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2324 | int regnum, gdb_byte *buf) |
28fc6740 | 2325 | { |
5716833c | 2326 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2327 | { |
63c0089f | 2328 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2329 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2330 | ||
28fc6740 | 2331 | /* Extract (always little endian). */ |
c86c27af | 2332 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2333 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2334 | } |
2335 | else | |
2336 | regcache_raw_read (regcache, regnum, buf); | |
2337 | } | |
2338 | ||
2339 | static void | |
2340 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2341 | int regnum, const gdb_byte *buf) |
28fc6740 | 2342 | { |
5716833c | 2343 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2344 | { |
63c0089f | 2345 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2346 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2347 | ||
28fc6740 AC |
2348 | /* Read ... */ |
2349 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2350 | /* ... Modify ... (always little endian). */ | |
f837910f | 2351 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2352 | /* ... Write. */ |
2353 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2354 | } | |
2355 | else | |
2356 | regcache_raw_write (regcache, regnum, buf); | |
2357 | } | |
ff2e87ac AC |
2358 | \f |
2359 | ||
ff2e87ac AC |
2360 | /* Return the register number of the register allocated by GCC after |
2361 | REGNUM, or -1 if there is no such register. */ | |
2362 | ||
2363 | static int | |
2364 | i386_next_regnum (int regnum) | |
2365 | { | |
2366 | /* GCC allocates the registers in the order: | |
2367 | ||
2368 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2369 | ||
2370 | Since storing a variable in %esp doesn't make any sense we return | |
2371 | -1 for %ebp and for %esp itself. */ | |
2372 | static int next_regnum[] = | |
2373 | { | |
2374 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2375 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2376 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2377 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2378 | -1, -1, /* Slots for %esp and %ebp. */ | |
2379 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2380 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2381 | }; | |
2382 | ||
de5b9bb9 | 2383 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2384 | return next_regnum[regnum]; |
28fc6740 | 2385 | |
ff2e87ac AC |
2386 | return -1; |
2387 | } | |
2388 | ||
2389 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2390 | needs any special handling. */ | |
d7a0d72c | 2391 | |
3a1e71e3 | 2392 | static int |
0abe36f5 | 2393 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2394 | { |
de5b9bb9 MK |
2395 | int len = TYPE_LENGTH (type); |
2396 | ||
ff2e87ac AC |
2397 | /* Values may be spread across multiple registers. Most debugging |
2398 | formats aren't expressive enough to specify the locations, so | |
2399 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2400 | have a length that is a multiple of the word size, since GCC |
2401 | doesn't seem to put any other types into registers. */ | |
2402 | if (len > 4 && len % 4 == 0) | |
2403 | { | |
2404 | int last_regnum = regnum; | |
2405 | ||
2406 | while (len > 4) | |
2407 | { | |
2408 | last_regnum = i386_next_regnum (last_regnum); | |
2409 | len -= 4; | |
2410 | } | |
2411 | ||
2412 | if (last_regnum != -1) | |
2413 | return 1; | |
2414 | } | |
ff2e87ac | 2415 | |
0abe36f5 | 2416 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2417 | } |
2418 | ||
ff2e87ac AC |
2419 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2420 | return its contents in TO. */ | |
ac27f131 | 2421 | |
3a1e71e3 | 2422 | static void |
ff2e87ac | 2423 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2424 | struct type *type, gdb_byte *to) |
ac27f131 | 2425 | { |
20a6ec49 | 2426 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2427 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2428 | |
ff2e87ac AC |
2429 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2430 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2431 | |
20a6ec49 | 2432 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2433 | { |
d532c08f MK |
2434 | i387_register_to_value (frame, regnum, type, to); |
2435 | return; | |
8d7f6b4a | 2436 | } |
ff2e87ac | 2437 | |
fd35795f | 2438 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2439 | |
2440 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2441 | |
de5b9bb9 MK |
2442 | while (len > 0) |
2443 | { | |
2444 | gdb_assert (regnum != -1); | |
20a6ec49 | 2445 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2446 | |
42835c2b | 2447 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2448 | regnum = i386_next_regnum (regnum); |
2449 | len -= 4; | |
42835c2b | 2450 | to += 4; |
de5b9bb9 | 2451 | } |
ac27f131 MK |
2452 | } |
2453 | ||
ff2e87ac AC |
2454 | /* Write the contents FROM of a value of type TYPE into register |
2455 | REGNUM in frame FRAME. */ | |
ac27f131 | 2456 | |
3a1e71e3 | 2457 | static void |
ff2e87ac | 2458 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2459 | struct type *type, const gdb_byte *from) |
ac27f131 | 2460 | { |
de5b9bb9 | 2461 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2462 | |
20a6ec49 | 2463 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2464 | { |
d532c08f MK |
2465 | i387_value_to_register (frame, regnum, type, from); |
2466 | return; | |
2467 | } | |
3d261580 | 2468 | |
fd35795f | 2469 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2470 | |
2471 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2472 | |
de5b9bb9 MK |
2473 | while (len > 0) |
2474 | { | |
2475 | gdb_assert (regnum != -1); | |
875f8d0e | 2476 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2477 | |
42835c2b | 2478 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2479 | regnum = i386_next_regnum (regnum); |
2480 | len -= 4; | |
42835c2b | 2481 | from += 4; |
de5b9bb9 | 2482 | } |
ac27f131 | 2483 | } |
ff2e87ac | 2484 | \f |
7fdafb5a MK |
2485 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2486 | in the general-purpose register set REGSET to register cache | |
2487 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2488 | |
20187ed5 | 2489 | void |
473f17b0 MK |
2490 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2491 | int regnum, const void *gregs, size_t len) | |
2492 | { | |
9ea75c57 | 2493 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2494 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2495 | int i; |
2496 | ||
2497 | gdb_assert (len == tdep->sizeof_gregset); | |
2498 | ||
2499 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2500 | { | |
2501 | if ((regnum == i || regnum == -1) | |
2502 | && tdep->gregset_reg_offset[i] != -1) | |
2503 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2504 | } | |
2505 | } | |
2506 | ||
7fdafb5a MK |
2507 | /* Collect register REGNUM from the register cache REGCACHE and store |
2508 | it in the buffer specified by GREGS and LEN as described by the | |
2509 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2510 | all registers in REGSET. */ | |
2511 | ||
2512 | void | |
2513 | i386_collect_gregset (const struct regset *regset, | |
2514 | const struct regcache *regcache, | |
2515 | int regnum, void *gregs, size_t len) | |
2516 | { | |
2517 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2518 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2519 | int i; |
2520 | ||
2521 | gdb_assert (len == tdep->sizeof_gregset); | |
2522 | ||
2523 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2524 | { | |
2525 | if ((regnum == i || regnum == -1) | |
2526 | && tdep->gregset_reg_offset[i] != -1) | |
2527 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2528 | } | |
2529 | } | |
2530 | ||
2531 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2532 | in the floating-point register set REGSET to register cache | |
2533 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2534 | |
2535 | static void | |
2536 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2537 | int regnum, const void *fpregs, size_t len) | |
2538 | { | |
9ea75c57 | 2539 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2540 | |
66a72d25 MK |
2541 | if (len == I387_SIZEOF_FXSAVE) |
2542 | { | |
2543 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2544 | return; | |
2545 | } | |
2546 | ||
473f17b0 MK |
2547 | gdb_assert (len == tdep->sizeof_fpregset); |
2548 | i387_supply_fsave (regcache, regnum, fpregs); | |
2549 | } | |
8446b36a | 2550 | |
2f305df1 MK |
2551 | /* Collect register REGNUM from the register cache REGCACHE and store |
2552 | it in the buffer specified by FPREGS and LEN as described by the | |
2553 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2554 | all registers in REGSET. */ | |
7fdafb5a MK |
2555 | |
2556 | static void | |
2557 | i386_collect_fpregset (const struct regset *regset, | |
2558 | const struct regcache *regcache, | |
2559 | int regnum, void *fpregs, size_t len) | |
2560 | { | |
2561 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2562 | ||
2563 | if (len == I387_SIZEOF_FXSAVE) | |
2564 | { | |
2565 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2566 | return; | |
2567 | } | |
2568 | ||
2569 | gdb_assert (len == tdep->sizeof_fpregset); | |
2570 | i387_collect_fsave (regcache, regnum, fpregs); | |
2571 | } | |
2572 | ||
8446b36a MK |
2573 | /* Return the appropriate register set for the core section identified |
2574 | by SECT_NAME and SECT_SIZE. */ | |
2575 | ||
2576 | const struct regset * | |
2577 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2578 | const char *sect_name, size_t sect_size) | |
2579 | { | |
2580 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2581 | ||
2582 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2583 | { | |
2584 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2585 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2586 | i386_collect_gregset); | |
8446b36a MK |
2587 | return tdep->gregset; |
2588 | } | |
2589 | ||
66a72d25 MK |
2590 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2591 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2592 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2593 | { |
2594 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2595 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2596 | i386_collect_fpregset); | |
8446b36a MK |
2597 | return tdep->fpregset; |
2598 | } | |
2599 | ||
2600 | return NULL; | |
2601 | } | |
473f17b0 | 2602 | \f |
fc338970 | 2603 | |
fc338970 | 2604 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2605 | |
2606 | CORE_ADDR | |
e17a4113 UW |
2607 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
2608 | CORE_ADDR pc, char *name) | |
c906108c | 2609 | { |
e17a4113 UW |
2610 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2611 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2612 | ||
2613 | /* jmp *(dest) */ | |
2614 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 2615 | { |
e17a4113 UW |
2616 | unsigned long indirect = |
2617 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 2618 | struct minimal_symbol *indsym = |
fc338970 | 2619 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2620 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2621 | |
c5aa993b | 2622 | if (symname) |
c906108c | 2623 | { |
c5aa993b JM |
2624 | if (strncmp (symname, "__imp_", 6) == 0 |
2625 | || strncmp (symname, "_imp_", 5) == 0) | |
e17a4113 UW |
2626 | return name ? 1 : |
2627 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
2628 | } |
2629 | } | |
fc338970 | 2630 | return 0; /* Not a trampoline. */ |
c906108c | 2631 | } |
fc338970 MK |
2632 | \f |
2633 | ||
10458914 DJ |
2634 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2635 | routine. */ | |
8201327c | 2636 | |
4bd207ef | 2637 | int |
10458914 | 2638 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2639 | { |
10458914 | 2640 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2641 | char *name; |
2642 | ||
2643 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2644 | return (name && strcmp ("_sigtramp", name) == 0); |
2645 | } | |
2646 | \f | |
2647 | ||
fc338970 MK |
2648 | /* We have two flavours of disassembly. The machinery on this page |
2649 | deals with switching between those. */ | |
c906108c SS |
2650 | |
2651 | static int | |
a89aa300 | 2652 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2653 | { |
5e3397bb MK |
2654 | gdb_assert (disassembly_flavor == att_flavor |
2655 | || disassembly_flavor == intel_flavor); | |
2656 | ||
2657 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2658 | constified, cast to prevent a compiler warning. */ | |
2659 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2660 | |
2661 | return print_insn_i386 (pc, info); | |
7a292a7a | 2662 | } |
fc338970 | 2663 | \f |
3ce1502b | 2664 | |
8201327c MK |
2665 | /* There are a few i386 architecture variants that differ only |
2666 | slightly from the generic i386 target. For now, we don't give them | |
2667 | their own source file, but include them here. As a consequence, | |
2668 | they'll always be included. */ | |
3ce1502b | 2669 | |
8201327c | 2670 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2671 | |
10458914 DJ |
2672 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2673 | routine. */ | |
911bc6ee | 2674 | |
8201327c | 2675 | static int |
10458914 | 2676 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2677 | { |
10458914 | 2678 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2679 | char *name; |
2680 | ||
acd5c798 MK |
2681 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2682 | currently unknown. */ | |
911bc6ee | 2683 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2684 | return (name && (strcmp ("_sigreturn", name) == 0 |
2685 | || strcmp ("_sigacthandler", name) == 0 | |
2686 | || strcmp ("sigvechandler", name) == 0)); | |
2687 | } | |
d2a7c97a | 2688 | |
10458914 DJ |
2689 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2690 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2691 | |
3a1e71e3 | 2692 | static CORE_ADDR |
10458914 | 2693 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2694 | { |
e17a4113 UW |
2695 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2696 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 2697 | gdb_byte buf[4]; |
acd5c798 | 2698 | CORE_ADDR sp; |
3ce1502b | 2699 | |
10458914 | 2700 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2701 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 2702 | |
e17a4113 | 2703 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c MK |
2704 | } |
2705 | \f | |
3ce1502b | 2706 | |
8201327c | 2707 | /* Generic ELF. */ |
d2a7c97a | 2708 | |
8201327c MK |
2709 | void |
2710 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2711 | { | |
c4fc7f1b MK |
2712 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2713 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2714 | } |
3ce1502b | 2715 | |
8201327c | 2716 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2717 | |
8201327c MK |
2718 | void |
2719 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2720 | { | |
2721 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2722 | |
8201327c MK |
2723 | /* System V Release 4 uses ELF. */ |
2724 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2725 | |
dfe01d39 | 2726 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2727 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2728 | ||
911bc6ee | 2729 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2730 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2731 | tdep->sc_pc_offset = 36 + 14 * 4; |
2732 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2733 | |
8201327c | 2734 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2735 | } |
2736 | ||
8201327c | 2737 | /* DJGPP. */ |
3ce1502b | 2738 | |
3a1e71e3 | 2739 | static void |
8201327c | 2740 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2741 | { |
8201327c | 2742 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2743 | |
911bc6ee MK |
2744 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2745 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2746 | |
8201327c | 2747 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
2748 | |
2749 | /* DJGPP does not support the SSE registers. */ | |
2750 | tdep->num_xmm_regs = 0; | |
2751 | set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS); | |
3d22076f EZ |
2752 | |
2753 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
2754 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
2755 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
2756 | set_gdbarch_sdb_reg_to_regnum. */ | |
2757 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2758 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
3ce1502b | 2759 | } |
8201327c | 2760 | \f |
2acceee2 | 2761 | |
38c968cf AC |
2762 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2763 | and "sse". */ | |
2764 | ||
2765 | static struct reggroup *i386_sse_reggroup; | |
2766 | static struct reggroup *i386_mmx_reggroup; | |
2767 | ||
2768 | static void | |
2769 | i386_init_reggroups (void) | |
2770 | { | |
2771 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2772 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2773 | } | |
2774 | ||
2775 | static void | |
2776 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2777 | { | |
2778 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2779 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2780 | reggroup_add (gdbarch, general_reggroup); | |
2781 | reggroup_add (gdbarch, float_reggroup); | |
2782 | reggroup_add (gdbarch, all_reggroup); | |
2783 | reggroup_add (gdbarch, save_reggroup); | |
2784 | reggroup_add (gdbarch, restore_reggroup); | |
2785 | reggroup_add (gdbarch, vector_reggroup); | |
2786 | reggroup_add (gdbarch, system_reggroup); | |
2787 | } | |
2788 | ||
2789 | int | |
2790 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2791 | struct reggroup *group) | |
2792 | { | |
5716833c MK |
2793 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2794 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2795 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2796 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2797 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2798 | |
38c968cf AC |
2799 | if (group == i386_mmx_reggroup) |
2800 | return mmx_regnum_p; | |
2801 | if (group == i386_sse_reggroup) | |
2802 | return sse_regnum_p; | |
2803 | if (group == vector_reggroup) | |
2804 | return (mmx_regnum_p || sse_regnum_p); | |
2805 | if (group == float_reggroup) | |
2806 | return fp_regnum_p; | |
2807 | if (group == general_reggroup) | |
2808 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2809 | |
38c968cf AC |
2810 | return default_register_reggroup_p (gdbarch, regnum, group); |
2811 | } | |
38c968cf | 2812 | \f |
acd5c798 | 2813 | |
f837910f MK |
2814 | /* Get the ARGIth function argument for the current function. */ |
2815 | ||
42c466d7 | 2816 | static CORE_ADDR |
143985b7 AF |
2817 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2818 | struct type *type) | |
2819 | { | |
e17a4113 UW |
2820 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2821 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f837910f | 2822 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 2823 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
2824 | } |
2825 | ||
514f746b AR |
2826 | static void |
2827 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2828 | { | |
2829 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2830 | ||
2831 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2832 | adjust the PC in the regcache. */ | |
2833 | current_pc += 1; | |
2834 | regcache_write_pc (regcache, current_pc); | |
2835 | } | |
2836 | ||
2837 | ||
7ad10968 HZ |
2838 | #define PREFIX_REPZ 0x01 |
2839 | #define PREFIX_REPNZ 0x02 | |
2840 | #define PREFIX_LOCK 0x04 | |
2841 | #define PREFIX_DATA 0x08 | |
2842 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 2843 | |
7ad10968 HZ |
2844 | /* operand size */ |
2845 | enum | |
2846 | { | |
2847 | OT_BYTE = 0, | |
2848 | OT_WORD, | |
2849 | OT_LONG, | |
cf648174 | 2850 | OT_QUAD, |
7ad10968 | 2851 | }; |
473f17b0 | 2852 | |
7ad10968 HZ |
2853 | /* i386 arith/logic operations */ |
2854 | enum | |
2855 | { | |
2856 | OP_ADDL, | |
2857 | OP_ORL, | |
2858 | OP_ADCL, | |
2859 | OP_SBBL, | |
2860 | OP_ANDL, | |
2861 | OP_SUBL, | |
2862 | OP_XORL, | |
2863 | OP_CMPL, | |
2864 | }; | |
5716833c | 2865 | |
7ad10968 HZ |
2866 | struct i386_record_s |
2867 | { | |
cf648174 | 2868 | struct gdbarch *gdbarch; |
7ad10968 | 2869 | struct regcache *regcache; |
df61f520 | 2870 | CORE_ADDR orig_addr; |
7ad10968 HZ |
2871 | CORE_ADDR addr; |
2872 | int aflag; | |
2873 | int dflag; | |
2874 | int override; | |
2875 | uint8_t modrm; | |
2876 | uint8_t mod, reg, rm; | |
2877 | int ot; | |
cf648174 HZ |
2878 | uint8_t rex_x; |
2879 | uint8_t rex_b; | |
2880 | int rip_offset; | |
2881 | int popl_esp_hack; | |
2882 | const int *regmap; | |
7ad10968 | 2883 | }; |
5716833c | 2884 | |
7ad10968 HZ |
2885 | /* Parse "modrm" part in current memory address that irp->addr point to |
2886 | Return -1 if something wrong. */ | |
5716833c | 2887 | |
7ad10968 HZ |
2888 | static int |
2889 | i386_record_modrm (struct i386_record_s *irp) | |
2890 | { | |
cf648174 | 2891 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 2892 | |
7ad10968 HZ |
2893 | if (target_read_memory (irp->addr, &irp->modrm, 1)) |
2894 | { | |
2895 | if (record_debug) | |
2896 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
2897 | "addr %s len = 1.\n"), |
2898 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2899 | return -1; |
2900 | } | |
2901 | irp->addr++; | |
2902 | irp->mod = (irp->modrm >> 6) & 3; | |
2903 | irp->reg = (irp->modrm >> 3) & 7; | |
2904 | irp->rm = irp->modrm & 7; | |
5716833c | 2905 | |
7ad10968 HZ |
2906 | return 0; |
2907 | } | |
d2a7c97a | 2908 | |
7ad10968 HZ |
2909 | /* Get the memory address that current instruction write to and set it to |
2910 | the argument "addr". | |
2911 | Return -1 if something wrong. */ | |
8201327c | 2912 | |
7ad10968 | 2913 | static int |
cf648174 | 2914 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 2915 | { |
cf648174 | 2916 | struct gdbarch *gdbarch = irp->gdbarch; |
7ad10968 | 2917 | uint8_t tmpu8; |
cf648174 HZ |
2918 | int16_t tmpi16; |
2919 | int32_t tmpi32; | |
2920 | ULONGEST tmpulongest; | |
21d0e8a4 | 2921 | |
7ad10968 HZ |
2922 | *addr = 0; |
2923 | if (irp->aflag) | |
2924 | { | |
2925 | /* 32 bits */ | |
2926 | int havesib = 0; | |
2927 | uint8_t scale = 0; | |
2928 | uint8_t index = 0; | |
2929 | uint8_t base = irp->rm; | |
896fb97d | 2930 | |
7ad10968 HZ |
2931 | if (base == 4) |
2932 | { | |
2933 | havesib = 1; | |
2934 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2935 | { | |
2936 | if (record_debug) | |
2937 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2938 | "at addr %s len = 1.\n"), |
2939 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2940 | return -1; |
2941 | } | |
2942 | irp->addr++; | |
2943 | scale = (tmpu8 >> 6) & 3; | |
cf648174 | 2944 | index = ((tmpu8 >> 3) & 7) | irp->rex_x; |
7ad10968 HZ |
2945 | base = (tmpu8 & 7); |
2946 | } | |
cf648174 | 2947 | base |= irp->rex_b; |
21d0e8a4 | 2948 | |
7ad10968 HZ |
2949 | switch (irp->mod) |
2950 | { | |
2951 | case 0: | |
2952 | if ((base & 7) == 5) | |
2953 | { | |
2954 | base = 0xff; | |
cf648174 | 2955 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
2956 | { |
2957 | if (record_debug) | |
2958 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
2959 | "memory at addr %s len = 4.\n"), |
2960 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2961 | return -1; |
2962 | } | |
2963 | irp->addr += 4; | |
cf648174 HZ |
2964 | *addr = tmpi32; |
2965 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) | |
2966 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 HZ |
2967 | } |
2968 | else | |
2969 | { | |
2970 | *addr = 0; | |
2971 | } | |
2972 | break; | |
2973 | case 1: | |
2974 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
2975 | { | |
2976 | if (record_debug) | |
2977 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2978 | "at addr %s len = 1.\n"), |
2979 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2980 | return -1; |
2981 | } | |
2982 | irp->addr++; | |
2983 | *addr = (int8_t) tmpu8; | |
2984 | break; | |
2985 | case 2: | |
cf648174 | 2986 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi32, 4)) |
7ad10968 HZ |
2987 | { |
2988 | if (record_debug) | |
2989 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
2990 | "at addr %s len = 4.\n"), |
2991 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
2992 | return -1; |
2993 | } | |
cf648174 | 2994 | *addr = tmpi32; |
7ad10968 HZ |
2995 | irp->addr += 4; |
2996 | break; | |
2997 | } | |
356a6b3e | 2998 | |
cf648174 | 2999 | tmpulongest = 0; |
7ad10968 | 3000 | if (base != 0xff) |
cf648174 HZ |
3001 | { |
3002 | if (base == 4 && irp->popl_esp_hack) | |
3003 | *addr += irp->popl_esp_hack; | |
3004 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
3005 | &tmpulongest); | |
7ad10968 | 3006 | } |
cf648174 HZ |
3007 | if (irp->aflag == 2) |
3008 | { | |
3009 | *addr += tmpulongest; | |
3010 | } | |
3011 | else | |
3012 | *addr = (uint32_t) (tmpulongest + *addr); | |
c4fc7f1b | 3013 | |
7ad10968 HZ |
3014 | if (havesib && (index != 4 || scale != 0)) |
3015 | { | |
cf648174 HZ |
3016 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
3017 | &tmpulongest); | |
3018 | if (irp->aflag == 2) | |
3019 | *addr += tmpulongest << scale; | |
3020 | else | |
3021 | *addr = (uint32_t) (*addr + (tmpulongest << scale)); | |
7ad10968 HZ |
3022 | } |
3023 | } | |
3024 | else | |
3025 | { | |
3026 | /* 16 bits */ | |
3027 | switch (irp->mod) | |
3028 | { | |
3029 | case 0: | |
3030 | if (irp->rm == 6) | |
3031 | { | |
3032 | if (target_read_memory | |
cf648174 | 3033 | (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
3034 | { |
3035 | if (record_debug) | |
3036 | printf_unfiltered (_("Process record: error reading " | |
5af949e3 UW |
3037 | "memory at addr %s len = 2.\n"), |
3038 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3039 | return -1; |
3040 | } | |
3041 | irp->addr += 2; | |
cf648174 | 3042 | *addr = tmpi16; |
7ad10968 HZ |
3043 | irp->rm = 0; |
3044 | goto no_rm; | |
3045 | } | |
3046 | else | |
3047 | { | |
3048 | *addr = 0; | |
3049 | } | |
3050 | break; | |
3051 | case 1: | |
3052 | if (target_read_memory (irp->addr, &tmpu8, 1)) | |
3053 | { | |
3054 | if (record_debug) | |
3055 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3056 | "at addr %s len = 1.\n"), |
3057 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3058 | return -1; |
3059 | } | |
3060 | irp->addr++; | |
3061 | *addr = (int8_t) tmpu8; | |
3062 | break; | |
3063 | case 2: | |
cf648174 | 3064 | if (target_read_memory (irp->addr, (gdb_byte *) &tmpi16, 2)) |
7ad10968 HZ |
3065 | { |
3066 | if (record_debug) | |
3067 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
3068 | "at addr %s len = 2.\n"), |
3069 | paddress (gdbarch, irp->addr)); | |
7ad10968 HZ |
3070 | return -1; |
3071 | } | |
3072 | irp->addr += 2; | |
cf648174 | 3073 | *addr = tmpi16; |
7ad10968 HZ |
3074 | break; |
3075 | } | |
c4fc7f1b | 3076 | |
7ad10968 HZ |
3077 | switch (irp->rm) |
3078 | { | |
3079 | case 0: | |
cf648174 HZ |
3080 | regcache_raw_read_unsigned (irp->regcache, |
3081 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3082 | &tmpulongest); | |
3083 | *addr = (uint32_t) (*addr + tmpulongest); | |
3084 | regcache_raw_read_unsigned (irp->regcache, | |
3085 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3086 | &tmpulongest); | |
3087 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3088 | break; |
3089 | case 1: | |
cf648174 HZ |
3090 | regcache_raw_read_unsigned (irp->regcache, |
3091 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3092 | &tmpulongest); | |
3093 | *addr = (uint32_t) (*addr + tmpulongest); | |
3094 | regcache_raw_read_unsigned (irp->regcache, | |
3095 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3096 | &tmpulongest); | |
3097 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3098 | break; |
3099 | case 2: | |
cf648174 HZ |
3100 | regcache_raw_read_unsigned (irp->regcache, |
3101 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3102 | &tmpulongest); | |
3103 | *addr = (uint32_t) (*addr + tmpulongest); | |
3104 | regcache_raw_read_unsigned (irp->regcache, | |
3105 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3106 | &tmpulongest); | |
3107 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3108 | break; |
3109 | case 3: | |
cf648174 HZ |
3110 | regcache_raw_read_unsigned (irp->regcache, |
3111 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3112 | &tmpulongest); | |
3113 | *addr = (uint32_t) (*addr + tmpulongest); | |
3114 | regcache_raw_read_unsigned (irp->regcache, | |
3115 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3116 | &tmpulongest); | |
3117 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3118 | break; |
3119 | case 4: | |
cf648174 HZ |
3120 | regcache_raw_read_unsigned (irp->regcache, |
3121 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
3122 | &tmpulongest); | |
3123 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3124 | break; |
3125 | case 5: | |
cf648174 HZ |
3126 | regcache_raw_read_unsigned (irp->regcache, |
3127 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
3128 | &tmpulongest); | |
3129 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3130 | break; |
3131 | case 6: | |
cf648174 HZ |
3132 | regcache_raw_read_unsigned (irp->regcache, |
3133 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
3134 | &tmpulongest); | |
3135 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3136 | break; |
3137 | case 7: | |
cf648174 HZ |
3138 | regcache_raw_read_unsigned (irp->regcache, |
3139 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
3140 | &tmpulongest); | |
3141 | *addr = (uint32_t) (*addr + tmpulongest); | |
7ad10968 HZ |
3142 | break; |
3143 | } | |
3144 | *addr &= 0xffff; | |
3145 | } | |
c4fc7f1b | 3146 | |
7ad10968 HZ |
3147 | no_rm: |
3148 | return 0; | |
3149 | } | |
c4fc7f1b | 3150 | |
7ad10968 HZ |
3151 | /* Record the value of the memory that willbe changed in current instruction |
3152 | to "record_arch_list". | |
3153 | Return -1 if something wrong. */ | |
356a6b3e | 3154 | |
7ad10968 HZ |
3155 | static int |
3156 | i386_record_lea_modrm (struct i386_record_s *irp) | |
3157 | { | |
cf648174 HZ |
3158 | struct gdbarch *gdbarch = irp->gdbarch; |
3159 | uint64_t addr; | |
356a6b3e | 3160 | |
d7877f7e | 3161 | if (irp->override >= 0) |
7ad10968 | 3162 | { |
df61f520 HZ |
3163 | warning (_("Process record ignores the memory change " |
3164 | "of instruction at address %s because it " | |
3165 | "can't get the value of the segment register."), | |
3166 | paddress (gdbarch, irp->orig_addr)); | |
7ad10968 HZ |
3167 | return 0; |
3168 | } | |
61113f8b | 3169 | |
7ad10968 HZ |
3170 | if (i386_record_lea_modrm_addr (irp, &addr)) |
3171 | return -1; | |
96297dab | 3172 | |
7ad10968 HZ |
3173 | if (record_arch_list_add_mem (addr, 1 << irp->ot)) |
3174 | return -1; | |
a62cc96e | 3175 | |
7ad10968 HZ |
3176 | return 0; |
3177 | } | |
b6197528 | 3178 | |
cf648174 HZ |
3179 | /* Record the push operation to "record_arch_list". |
3180 | Return -1 if something wrong. */ | |
3181 | ||
3182 | static int | |
3183 | i386_record_push (struct i386_record_s *irp, int size) | |
3184 | { | |
3185 | ULONGEST tmpulongest; | |
3186 | ||
3187 | if (record_arch_list_add_reg (irp->regcache, | |
3188 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
3189 | return -1; | |
3190 | regcache_raw_read_unsigned (irp->regcache, | |
3191 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
3192 | &tmpulongest); | |
3193 | if (record_arch_list_add_mem ((CORE_ADDR) tmpulongest - size, size)) | |
3194 | return -1; | |
3195 | ||
3196 | return 0; | |
3197 | } | |
3198 | ||
7ad10968 HZ |
3199 | /* Parse the current instruction and record the values of the registers and |
3200 | memory that will be changed in current instruction to "record_arch_list". | |
3201 | Return -1 if something wrong. */ | |
8201327c | 3202 | |
cf648174 HZ |
3203 | #define I386_RECORD_ARCH_LIST_ADD_REG(regnum) \ |
3204 | record_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
3205 | ||
a6b808b4 | 3206 | int |
7ad10968 HZ |
3207 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
3208 | CORE_ADDR addr) | |
3209 | { | |
3210 | int prefixes = 0; | |
3211 | uint8_t tmpu8; | |
3212 | uint16_t tmpu16; | |
3213 | uint32_t tmpu32; | |
cf648174 | 3214 | ULONGEST tmpulongest; |
7ad10968 HZ |
3215 | uint32_t opcode; |
3216 | struct i386_record_s ir; | |
cf648174 HZ |
3217 | int rex = 0; |
3218 | uint8_t rex_w = -1; | |
3219 | uint8_t rex_r = 0; | |
7ad10968 | 3220 | |
8408d274 | 3221 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 HZ |
3222 | ir.regcache = regcache; |
3223 | ir.addr = addr; | |
df61f520 | 3224 | ir.orig_addr = addr; |
7ad10968 HZ |
3225 | ir.aflag = 1; |
3226 | ir.dflag = 1; | |
cf648174 HZ |
3227 | ir.override = -1; |
3228 | ir.popl_esp_hack = 0; | |
3229 | ir.regmap = gdbarch_tdep (gdbarch)->record_regmap; | |
3230 | ir.gdbarch = gdbarch; | |
7ad10968 HZ |
3231 | |
3232 | if (record_debug > 1) | |
3233 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
3234 | "addr = %s\n", |
3235 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3236 | |
3237 | /* prefixes */ | |
3238 | while (1) | |
3239 | { | |
3240 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3241 | { | |
3242 | if (record_debug) | |
3243 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3244 | "addr %s len = 1.\n"), |
3245 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3246 | return -1; |
3247 | } | |
3248 | ir.addr++; | |
3249 | switch (tmpu8) | |
3250 | { | |
3251 | case 0xf3: | |
3252 | prefixes |= PREFIX_REPZ; | |
3253 | break; | |
3254 | case 0xf2: | |
3255 | prefixes |= PREFIX_REPNZ; | |
3256 | break; | |
3257 | case 0xf0: | |
3258 | prefixes |= PREFIX_LOCK; | |
3259 | break; | |
3260 | case 0x2e: | |
cf648174 | 3261 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 HZ |
3262 | break; |
3263 | case 0x36: | |
cf648174 | 3264 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
3265 | break; |
3266 | case 0x3e: | |
cf648174 | 3267 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
3268 | break; |
3269 | case 0x26: | |
cf648174 | 3270 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
3271 | break; |
3272 | case 0x64: | |
cf648174 | 3273 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
3274 | break; |
3275 | case 0x65: | |
cf648174 | 3276 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
3277 | break; |
3278 | case 0x66: | |
3279 | prefixes |= PREFIX_DATA; | |
3280 | break; | |
3281 | case 0x67: | |
3282 | prefixes |= PREFIX_ADDR; | |
3283 | break; | |
d691bec7 MS |
3284 | case 0x40: /* i386 inc %eax */ |
3285 | case 0x41: /* i386 inc %ecx */ | |
3286 | case 0x42: /* i386 inc %edx */ | |
3287 | case 0x43: /* i386 inc %ebx */ | |
3288 | case 0x44: /* i386 inc %esp */ | |
3289 | case 0x45: /* i386 inc %ebp */ | |
3290 | case 0x46: /* i386 inc %esi */ | |
3291 | case 0x47: /* i386 inc %edi */ | |
3292 | case 0x48: /* i386 dec %eax */ | |
3293 | case 0x49: /* i386 dec %ecx */ | |
3294 | case 0x4a: /* i386 dec %edx */ | |
3295 | case 0x4b: /* i386 dec %ebx */ | |
3296 | case 0x4c: /* i386 dec %esp */ | |
3297 | case 0x4d: /* i386 dec %ebp */ | |
3298 | case 0x4e: /* i386 dec %esi */ | |
3299 | case 0x4f: /* i386 dec %edi */ | |
3300 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
3301 | { |
3302 | /* REX */ | |
3303 | rex = 1; | |
3304 | rex_w = (tmpu8 >> 3) & 1; | |
3305 | rex_r = (tmpu8 & 0x4) << 1; | |
3306 | ir.rex_x = (tmpu8 & 0x2) << 2; | |
3307 | ir.rex_b = (tmpu8 & 0x1) << 3; | |
3308 | } | |
d691bec7 MS |
3309 | else /* 32 bit target */ |
3310 | goto out_prefixes; | |
cf648174 | 3311 | break; |
7ad10968 HZ |
3312 | default: |
3313 | goto out_prefixes; | |
3314 | break; | |
3315 | } | |
3316 | } | |
3317 | out_prefixes: | |
cf648174 HZ |
3318 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
3319 | { | |
3320 | ir.dflag = 2; | |
3321 | } | |
3322 | else | |
3323 | { | |
3324 | if (prefixes & PREFIX_DATA) | |
3325 | ir.dflag ^= 1; | |
3326 | } | |
7ad10968 HZ |
3327 | if (prefixes & PREFIX_ADDR) |
3328 | ir.aflag ^= 1; | |
cf648174 HZ |
3329 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3330 | ir.aflag = 2; | |
7ad10968 HZ |
3331 | |
3332 | /* now check op code */ | |
3333 | opcode = (uint32_t) tmpu8; | |
3334 | reswitch: | |
3335 | switch (opcode) | |
3336 | { | |
3337 | case 0x0f: | |
3338 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
3339 | { | |
3340 | if (record_debug) | |
3341 | printf_unfiltered (_("Process record: error reading memory at " | |
5af949e3 UW |
3342 | "addr %s len = 1.\n"), |
3343 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
3344 | return -1; |
3345 | } | |
3346 | ir.addr++; | |
3347 | opcode = (uint16_t) tmpu8 | 0x0f00; | |
3348 | goto reswitch; | |
3349 | break; | |
93924b6b | 3350 | |
7ad10968 HZ |
3351 | /* arith & logic */ |
3352 | case 0x00: | |
3353 | case 0x01: | |
3354 | case 0x02: | |
3355 | case 0x03: | |
3356 | case 0x04: | |
3357 | case 0x05: | |
3358 | case 0x08: | |
3359 | case 0x09: | |
3360 | case 0x0a: | |
3361 | case 0x0b: | |
3362 | case 0x0c: | |
3363 | case 0x0d: | |
3364 | case 0x10: | |
3365 | case 0x11: | |
3366 | case 0x12: | |
3367 | case 0x13: | |
3368 | case 0x14: | |
3369 | case 0x15: | |
3370 | case 0x18: | |
3371 | case 0x19: | |
3372 | case 0x1a: | |
3373 | case 0x1b: | |
3374 | case 0x1c: | |
3375 | case 0x1d: | |
3376 | case 0x20: | |
3377 | case 0x21: | |
3378 | case 0x22: | |
3379 | case 0x23: | |
3380 | case 0x24: | |
3381 | case 0x25: | |
3382 | case 0x28: | |
3383 | case 0x29: | |
3384 | case 0x2a: | |
3385 | case 0x2b: | |
3386 | case 0x2c: | |
3387 | case 0x2d: | |
3388 | case 0x30: | |
3389 | case 0x31: | |
3390 | case 0x32: | |
3391 | case 0x33: | |
3392 | case 0x34: | |
3393 | case 0x35: | |
3394 | case 0x38: | |
3395 | case 0x39: | |
3396 | case 0x3a: | |
3397 | case 0x3b: | |
3398 | case 0x3c: | |
3399 | case 0x3d: | |
3400 | if (((opcode >> 3) & 7) != OP_CMPL) | |
3401 | { | |
3402 | if ((opcode & 1) == 0) | |
3403 | ir.ot = OT_BYTE; | |
3404 | else | |
3405 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 3406 | |
7ad10968 HZ |
3407 | switch ((opcode >> 1) & 3) |
3408 | { | |
3409 | /* OP Ev, Gv */ | |
3410 | case 0: | |
3411 | if (i386_record_modrm (&ir)) | |
3412 | return -1; | |
3413 | if (ir.mod != 3) | |
3414 | { | |
3415 | if (i386_record_lea_modrm (&ir)) | |
3416 | return -1; | |
3417 | } | |
3418 | else | |
3419 | { | |
cf648174 HZ |
3420 | ir.rm |= ir.rex_b; |
3421 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3422 | ir.rm &= 0x3; |
cf648174 | 3423 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3424 | } |
3425 | break; | |
3426 | /* OP Gv, Ev */ | |
3427 | case 1: | |
3428 | if (i386_record_modrm (&ir)) | |
3429 | return -1; | |
cf648174 HZ |
3430 | ir.reg |= rex_r; |
3431 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3432 | ir.reg &= 0x3; |
cf648174 | 3433 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3434 | break; |
3435 | /* OP A, Iv */ | |
3436 | case 2: | |
cf648174 | 3437 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3438 | break; |
3439 | } | |
3440 | } | |
cf648174 | 3441 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3442 | break; |
42fdc8df | 3443 | |
7ad10968 HZ |
3444 | /* GRP1 */ |
3445 | case 0x80: | |
3446 | case 0x81: | |
3447 | case 0x82: | |
3448 | case 0x83: | |
3449 | if (i386_record_modrm (&ir)) | |
3450 | return -1; | |
8201327c | 3451 | |
7ad10968 HZ |
3452 | if (ir.reg != OP_CMPL) |
3453 | { | |
3454 | if ((opcode & 1) == 0) | |
3455 | ir.ot = OT_BYTE; | |
3456 | else | |
3457 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 3458 | |
7ad10968 HZ |
3459 | if (ir.mod != 3) |
3460 | { | |
cf648174 HZ |
3461 | if (opcode == 0x83) |
3462 | ir.rip_offset = 1; | |
3463 | else | |
3464 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3465 | if (i386_record_lea_modrm (&ir)) |
3466 | return -1; | |
3467 | } | |
3468 | else | |
cf648174 | 3469 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 3470 | } |
cf648174 | 3471 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 3472 | break; |
5e3397bb | 3473 | |
7ad10968 HZ |
3474 | /* inv */ |
3475 | case 0x40: | |
3476 | case 0x41: | |
3477 | case 0x42: | |
3478 | case 0x43: | |
3479 | case 0x44: | |
3480 | case 0x45: | |
3481 | case 0x46: | |
3482 | case 0x47: | |
3483 | /* dec */ | |
3484 | case 0x48: | |
3485 | case 0x49: | |
3486 | case 0x4a: | |
3487 | case 0x4b: | |
3488 | case 0x4c: | |
3489 | case 0x4d: | |
3490 | case 0x4e: | |
3491 | case 0x4f: | |
cf648174 HZ |
3492 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 7); |
3493 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 3494 | break; |
acd5c798 | 3495 | |
7ad10968 HZ |
3496 | /* GRP3 */ |
3497 | case 0xf6: | |
3498 | case 0xf7: | |
3499 | if ((opcode & 1) == 0) | |
3500 | ir.ot = OT_BYTE; | |
3501 | else | |
3502 | ir.ot = ir.dflag + OT_WORD; | |
3503 | if (i386_record_modrm (&ir)) | |
3504 | return -1; | |
acd5c798 | 3505 | |
cf648174 HZ |
3506 | if (ir.mod != 3 && ir.reg == 0) |
3507 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3508 | ||
7ad10968 HZ |
3509 | switch (ir.reg) |
3510 | { | |
3511 | /* test */ | |
3512 | case 0: | |
cf648174 | 3513 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3514 | break; |
3515 | /* not */ | |
3516 | case 2: | |
7ad10968 HZ |
3517 | /* neg */ |
3518 | case 3: | |
3519 | if (ir.mod != 3) | |
3520 | { | |
3521 | if (i386_record_lea_modrm (&ir)) | |
3522 | return -1; | |
3523 | } | |
3524 | else | |
3525 | { | |
cf648174 HZ |
3526 | ir.rm |= ir.rex_b; |
3527 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3528 | ir.rm &= 0x3; |
cf648174 | 3529 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3530 | } |
cf648174 HZ |
3531 | /* neg */ |
3532 | if (ir.reg == 3) | |
3533 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3534 | break; |
3535 | /* mul */ | |
3536 | case 4: | |
3537 | /* imul */ | |
3538 | case 5: | |
3539 | /* div */ | |
3540 | case 6: | |
3541 | /* idiv */ | |
3542 | case 7: | |
cf648174 | 3543 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 3544 | if (ir.ot != OT_BYTE) |
cf648174 HZ |
3545 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
3546 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3547 | break; |
3548 | default: | |
3549 | ir.addr -= 2; | |
3550 | opcode = opcode << 8 | ir.modrm; | |
3551 | goto no_support; | |
3552 | break; | |
3553 | } | |
3554 | break; | |
3555 | ||
3556 | /* GRP4 */ | |
3557 | case 0xfe: | |
3558 | /* GRP5 */ | |
3559 | case 0xff: | |
7ad10968 HZ |
3560 | if (i386_record_modrm (&ir)) |
3561 | return -1; | |
3562 | if (ir.reg >= 2 && opcode == 0xfe) | |
3563 | { | |
3564 | ir.addr -= 2; | |
3565 | opcode = opcode << 8 | ir.modrm; | |
3566 | goto no_support; | |
3567 | } | |
7ad10968 HZ |
3568 | switch (ir.reg) |
3569 | { | |
3570 | /* inc */ | |
3571 | case 0: | |
3572 | /* dec */ | |
3573 | case 1: | |
cf648174 HZ |
3574 | if ((opcode & 1) == 0) |
3575 | ir.ot = OT_BYTE; | |
3576 | else | |
3577 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3578 | if (ir.mod != 3) |
3579 | { | |
3580 | if (i386_record_lea_modrm (&ir)) | |
3581 | return -1; | |
3582 | } | |
3583 | else | |
3584 | { | |
cf648174 HZ |
3585 | ir.rm |= ir.rex_b; |
3586 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3587 | ir.rm &= 0x3; |
cf648174 | 3588 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3589 | } |
cf648174 | 3590 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3591 | break; |
3592 | /* call */ | |
3593 | case 2: | |
cf648174 HZ |
3594 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3595 | ir.dflag = 2; | |
3596 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3597 | return -1; |
cf648174 | 3598 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3599 | break; |
3600 | /* lcall */ | |
3601 | case 3: | |
cf648174 HZ |
3602 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
3603 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3604 | return -1; |
cf648174 | 3605 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3606 | break; |
3607 | /* jmp */ | |
3608 | case 4: | |
3609 | /* ljmp */ | |
3610 | case 5: | |
cf648174 HZ |
3611 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
3612 | break; | |
3613 | /* push */ | |
3614 | case 6: | |
3615 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3616 | ir.dflag = 2; | |
3617 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3618 | return -1; | |
7ad10968 HZ |
3619 | break; |
3620 | default: | |
3621 | ir.addr -= 2; | |
3622 | opcode = opcode << 8 | ir.modrm; | |
3623 | goto no_support; | |
3624 | break; | |
3625 | } | |
3626 | break; | |
3627 | ||
3628 | /* test */ | |
3629 | case 0x84: | |
3630 | case 0x85: | |
3631 | case 0xa8: | |
3632 | case 0xa9: | |
cf648174 | 3633 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3634 | break; |
3635 | ||
3636 | /* CWDE/CBW */ | |
3637 | case 0x98: | |
cf648174 | 3638 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3639 | break; |
3640 | ||
3641 | /* CDQ/CWD */ | |
3642 | case 0x99: | |
cf648174 HZ |
3643 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3644 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3645 | break; |
3646 | ||
3647 | /* imul */ | |
3648 | case 0x0faf: | |
3649 | case 0x69: | |
3650 | case 0x6b: | |
3651 | ir.ot = ir.dflag + OT_WORD; | |
3652 | if (i386_record_modrm (&ir)) | |
3653 | return -1; | |
cf648174 HZ |
3654 | if (opcode == 0x69) |
3655 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
3656 | else if (opcode == 0x6b) | |
3657 | ir.rip_offset = 1; | |
3658 | ir.reg |= rex_r; | |
3659 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3660 | ir.reg &= 0x3; |
cf648174 HZ |
3661 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3662 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3663 | break; |
3664 | ||
3665 | /* xadd */ | |
3666 | case 0x0fc0: | |
3667 | case 0x0fc1: | |
3668 | if ((opcode & 1) == 0) | |
3669 | ir.ot = OT_BYTE; | |
3670 | else | |
3671 | ir.ot = ir.dflag + OT_WORD; | |
3672 | if (i386_record_modrm (&ir)) | |
3673 | return -1; | |
cf648174 | 3674 | ir.reg |= rex_r; |
7ad10968 HZ |
3675 | if (ir.mod == 3) |
3676 | { | |
cf648174 | 3677 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3678 | ir.reg &= 0x3; |
cf648174 HZ |
3679 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3680 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3681 | ir.rm &= 0x3; |
cf648174 | 3682 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
3683 | } |
3684 | else | |
3685 | { | |
3686 | if (i386_record_lea_modrm (&ir)) | |
3687 | return -1; | |
cf648174 | 3688 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 3689 | ir.reg &= 0x3; |
cf648174 | 3690 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 3691 | } |
cf648174 | 3692 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3693 | break; |
3694 | ||
3695 | /* cmpxchg */ | |
3696 | case 0x0fb0: | |
3697 | case 0x0fb1: | |
3698 | if ((opcode & 1) == 0) | |
3699 | ir.ot = OT_BYTE; | |
3700 | else | |
3701 | ir.ot = ir.dflag + OT_WORD; | |
3702 | if (i386_record_modrm (&ir)) | |
3703 | return -1; | |
3704 | if (ir.mod == 3) | |
3705 | { | |
cf648174 HZ |
3706 | ir.reg |= rex_r; |
3707 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
3708 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3709 | ir.reg &= 0x3; |
cf648174 | 3710 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
3711 | } |
3712 | else | |
3713 | { | |
cf648174 | 3714 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
3715 | if (i386_record_lea_modrm (&ir)) |
3716 | return -1; | |
3717 | } | |
cf648174 | 3718 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3719 | break; |
3720 | ||
3721 | /* cmpxchg8b */ | |
3722 | case 0x0fc7: | |
3723 | if (i386_record_modrm (&ir)) | |
3724 | return -1; | |
3725 | if (ir.mod == 3) | |
3726 | { | |
3727 | ir.addr -= 2; | |
3728 | opcode = opcode << 8 | ir.modrm; | |
3729 | goto no_support; | |
3730 | } | |
cf648174 HZ |
3731 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
3732 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
3733 | if (i386_record_lea_modrm (&ir)) |
3734 | return -1; | |
cf648174 | 3735 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
3736 | break; |
3737 | ||
3738 | /* push */ | |
3739 | case 0x50: | |
3740 | case 0x51: | |
3741 | case 0x52: | |
3742 | case 0x53: | |
3743 | case 0x54: | |
3744 | case 0x55: | |
3745 | case 0x56: | |
3746 | case 0x57: | |
3747 | case 0x68: | |
3748 | case 0x6a: | |
cf648174 HZ |
3749 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
3750 | ir.dflag = 2; | |
3751 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3752 | return -1; | |
3753 | break; | |
3754 | ||
7ad10968 HZ |
3755 | /* push es */ |
3756 | case 0x06: | |
3757 | /* push cs */ | |
3758 | case 0x0e: | |
3759 | /* push ss */ | |
3760 | case 0x16: | |
3761 | /* push ds */ | |
3762 | case 0x1e: | |
cf648174 HZ |
3763 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3764 | { | |
3765 | ir.addr -= 1; | |
3766 | goto no_support; | |
3767 | } | |
3768 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
3769 | return -1; | |
3770 | break; | |
3771 | ||
7ad10968 HZ |
3772 | /* push fs */ |
3773 | case 0x0fa0: | |
3774 | /* push gs */ | |
3775 | case 0x0fa8: | |
cf648174 HZ |
3776 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3777 | { | |
3778 | ir.addr -= 2; | |
3779 | goto no_support; | |
3780 | } | |
3781 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 3782 | return -1; |
cf648174 HZ |
3783 | break; |
3784 | ||
3785 | /* pusha */ | |
3786 | case 0x60: | |
3787 | if (ir.regmap[X86_RECORD_R8_REGNUM]) | |
3788 | { | |
3789 | ir.addr -= 1; | |
3790 | goto no_support; | |
3791 | } | |
3792 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
3793 | return -1; |
3794 | break; | |
3795 | ||
3796 | /* pop */ | |
3797 | case 0x58: | |
3798 | case 0x59: | |
3799 | case 0x5a: | |
3800 | case 0x5b: | |
3801 | case 0x5c: | |
3802 | case 0x5d: | |
3803 | case 0x5e: | |
3804 | case 0x5f: | |
cf648174 HZ |
3805 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3806 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
3807 | break; |
3808 | ||
3809 | /* popa */ | |
3810 | case 0x61: | |
cf648174 HZ |
3811 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3812 | { | |
3813 | ir.addr -= 1; | |
3814 | goto no_support; | |
7ad10968 | 3815 | } |
cf648174 HZ |
3816 | for (tmpu8 = X86_RECORD_REAX_REGNUM; tmpu8 <= X86_RECORD_REDI_REGNUM; |
3817 | tmpu8++) | |
3818 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); | |
7ad10968 HZ |
3819 | break; |
3820 | ||
3821 | /* pop */ | |
3822 | case 0x8f: | |
cf648174 HZ |
3823 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3824 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
3825 | else | |
3826 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3827 | if (i386_record_modrm (&ir)) |
3828 | return -1; | |
3829 | if (ir.mod == 3) | |
cf648174 | 3830 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
3831 | else |
3832 | { | |
cf648174 | 3833 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
3834 | if (i386_record_lea_modrm (&ir)) |
3835 | return -1; | |
3836 | } | |
cf648174 | 3837 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
3838 | break; |
3839 | ||
3840 | /* enter */ | |
3841 | case 0xc8: | |
cf648174 HZ |
3842 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
3843 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
3844 | ir.dflag = 2; | |
3845 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
3846 | return -1; |
3847 | break; | |
3848 | ||
3849 | /* leave */ | |
3850 | case 0xc9: | |
cf648174 HZ |
3851 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3852 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
3853 | break; |
3854 | ||
3855 | /* pop es */ | |
3856 | case 0x07: | |
cf648174 HZ |
3857 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3858 | { | |
3859 | ir.addr -= 1; | |
3860 | goto no_support; | |
3861 | } | |
3862 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3863 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
3864 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3865 | break; |
3866 | ||
3867 | /* pop ss */ | |
3868 | case 0x17: | |
cf648174 HZ |
3869 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3870 | { | |
3871 | ir.addr -= 1; | |
3872 | goto no_support; | |
3873 | } | |
3874 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3875 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
3876 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3877 | break; |
3878 | ||
3879 | /* pop ds */ | |
3880 | case 0x1f: | |
cf648174 HZ |
3881 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
3882 | { | |
3883 | ir.addr -= 1; | |
3884 | goto no_support; | |
3885 | } | |
3886 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
3887 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
3888 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3889 | break; |
3890 | ||
3891 | /* pop fs */ | |
3892 | case 0x0fa1: | |
cf648174 HZ |
3893 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3894 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
3895 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3896 | break; |
3897 | ||
3898 | /* pop gs */ | |
3899 | case 0x0fa9: | |
cf648174 HZ |
3900 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
3901 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
3902 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
3903 | break; |
3904 | ||
3905 | /* mov */ | |
3906 | case 0x88: | |
3907 | case 0x89: | |
3908 | case 0xc6: | |
3909 | case 0xc7: | |
3910 | if ((opcode & 1) == 0) | |
3911 | ir.ot = OT_BYTE; | |
3912 | else | |
3913 | ir.ot = ir.dflag + OT_WORD; | |
3914 | ||
3915 | if (i386_record_modrm (&ir)) | |
3916 | return -1; | |
3917 | ||
3918 | if (ir.mod != 3) | |
3919 | { | |
cf648174 HZ |
3920 | if (opcode == 0xc6 || opcode == 0xc7) |
3921 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
3922 | if (i386_record_lea_modrm (&ir)) |
3923 | return -1; | |
3924 | } | |
3925 | else | |
3926 | { | |
cf648174 HZ |
3927 | if (opcode == 0xc6 || opcode == 0xc7) |
3928 | ir.rm |= ir.rex_b; | |
3929 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3930 | ir.rm &= 0x3; |
cf648174 | 3931 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 3932 | } |
7ad10968 | 3933 | break; |
cf648174 | 3934 | |
7ad10968 HZ |
3935 | /* mov */ |
3936 | case 0x8a: | |
3937 | case 0x8b: | |
3938 | if ((opcode & 1) == 0) | |
3939 | ir.ot = OT_BYTE; | |
3940 | else | |
3941 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
3942 | if (i386_record_modrm (&ir)) |
3943 | return -1; | |
cf648174 HZ |
3944 | ir.reg |= rex_r; |
3945 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 3946 | ir.reg &= 0x3; |
cf648174 HZ |
3947 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
3948 | break; | |
7ad10968 | 3949 | |
cf648174 HZ |
3950 | /* mov seg */ |
3951 | case 0x8c: | |
3952 | if (i386_record_modrm (&ir)) | |
7ad10968 | 3953 | return -1; |
cf648174 HZ |
3954 | if (ir.reg > 5) |
3955 | { | |
3956 | ir.addr -= 2; | |
3957 | opcode = opcode << 8 | ir.modrm; | |
3958 | goto no_support; | |
3959 | } | |
3960 | ||
3961 | if (ir.mod == 3) | |
3962 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
3963 | else | |
3964 | { | |
3965 | ir.ot = OT_WORD; | |
3966 | if (i386_record_lea_modrm (&ir)) | |
3967 | return -1; | |
3968 | } | |
7ad10968 HZ |
3969 | break; |
3970 | ||
3971 | /* mov seg */ | |
3972 | case 0x8e: | |
3973 | if (i386_record_modrm (&ir)) | |
3974 | return -1; | |
7ad10968 HZ |
3975 | switch (ir.reg) |
3976 | { | |
3977 | case 0: | |
cf648174 | 3978 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
3979 | break; |
3980 | case 2: | |
cf648174 | 3981 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
3982 | break; |
3983 | case 3: | |
cf648174 | 3984 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
3985 | break; |
3986 | case 4: | |
cf648174 | 3987 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
3988 | break; |
3989 | case 5: | |
cf648174 | 3990 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
3991 | break; |
3992 | default: | |
3993 | ir.addr -= 2; | |
3994 | opcode = opcode << 8 | ir.modrm; | |
3995 | goto no_support; | |
3996 | break; | |
3997 | } | |
cf648174 HZ |
3998 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
3999 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4000 | break; |
4001 | ||
4002 | /* movzbS */ | |
4003 | case 0x0fb6: | |
4004 | /* movzwS */ | |
4005 | case 0x0fb7: | |
4006 | /* movsbS */ | |
4007 | case 0x0fbe: | |
4008 | /* movswS */ | |
4009 | case 0x0fbf: | |
4010 | if (i386_record_modrm (&ir)) | |
4011 | return -1; | |
cf648174 | 4012 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
4013 | break; |
4014 | ||
4015 | /* lea */ | |
4016 | case 0x8d: | |
4017 | if (i386_record_modrm (&ir)) | |
4018 | return -1; | |
4019 | if (ir.mod == 3) | |
4020 | { | |
4021 | ir.addr -= 2; | |
4022 | opcode = opcode << 8 | ir.modrm; | |
4023 | goto no_support; | |
4024 | } | |
7ad10968 | 4025 | ir.ot = ir.dflag; |
cf648174 HZ |
4026 | ir.reg |= rex_r; |
4027 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4028 | ir.reg &= 0x3; |
cf648174 | 4029 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4030 | break; |
4031 | ||
4032 | /* mov EAX */ | |
4033 | case 0xa0: | |
4034 | case 0xa1: | |
4035 | /* xlat */ | |
4036 | case 0xd7: | |
cf648174 | 4037 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
4038 | break; |
4039 | ||
4040 | /* mov EAX */ | |
4041 | case 0xa2: | |
4042 | case 0xa3: | |
d7877f7e | 4043 | if (ir.override >= 0) |
cf648174 | 4044 | { |
df61f520 | 4045 | warning (_("Process record ignores the memory change " |
926569ae | 4046 | "of instruction at address %s because " |
df61f520 HZ |
4047 | "it can't get the value of the segment " |
4048 | "register."), | |
4049 | paddress (gdbarch, ir.orig_addr)); | |
cf648174 HZ |
4050 | } |
4051 | else | |
4052 | { | |
4053 | if ((opcode & 1) == 0) | |
4054 | ir.ot = OT_BYTE; | |
4055 | else | |
4056 | ir.ot = ir.dflag + OT_WORD; | |
4057 | if (ir.aflag == 2) | |
4058 | { | |
4059 | if (target_read_memory (ir.addr, (gdb_byte *) &addr, 8)) | |
4060 | { | |
4061 | if (record_debug) | |
4062 | printf_unfiltered (_("Process record: error reading " | |
4063 | "memory at addr 0x%s len = 8.\n"), | |
4064 | paddress (gdbarch, ir.addr)); | |
4065 | return -1; | |
4066 | } | |
4067 | ir.addr += 8; | |
4068 | } | |
4069 | else if (ir.aflag) | |
4070 | { | |
4071 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu32, 4)) | |
4072 | { | |
4073 | if (record_debug) | |
4074 | printf_unfiltered (_("Process record: error reading " | |
4075 | "memory at addr 0x%s len = 4.\n"), | |
4076 | paddress (gdbarch, ir.addr)); | |
4077 | return -1; | |
4078 | } | |
4079 | ir.addr += 4; | |
4080 | addr = tmpu32; | |
4081 | } | |
4082 | else | |
4083 | { | |
4084 | if (target_read_memory (ir.addr, (gdb_byte *) &tmpu16, 2)) | |
4085 | { | |
4086 | if (record_debug) | |
4087 | printf_unfiltered (_("Process record: error reading " | |
4088 | "memory at addr 0x%s len = 2.\n"), | |
4089 | paddress (gdbarch, ir.addr)); | |
4090 | return -1; | |
4091 | } | |
4092 | ir.addr += 2; | |
4093 | addr = tmpu16; | |
4094 | } | |
4095 | if (record_arch_list_add_mem (addr, 1 << ir.ot)) | |
4096 | return -1; | |
4097 | } | |
7ad10968 HZ |
4098 | break; |
4099 | ||
4100 | /* mov R, Ib */ | |
4101 | case 0xb0: | |
4102 | case 0xb1: | |
4103 | case 0xb2: | |
4104 | case 0xb3: | |
4105 | case 0xb4: | |
4106 | case 0xb5: | |
4107 | case 0xb6: | |
4108 | case 0xb7: | |
cf648174 HZ |
4109 | I386_RECORD_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
4110 | ? ((opcode & 0x7) | ir.rex_b) | |
4111 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
4112 | break; |
4113 | ||
4114 | /* mov R, Iv */ | |
4115 | case 0xb8: | |
4116 | case 0xb9: | |
4117 | case 0xba: | |
4118 | case 0xbb: | |
4119 | case 0xbc: | |
4120 | case 0xbd: | |
4121 | case 0xbe: | |
4122 | case 0xbf: | |
cf648174 | 4123 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
4124 | break; |
4125 | ||
4126 | /* xchg R, EAX */ | |
4127 | case 0x91: | |
4128 | case 0x92: | |
4129 | case 0x93: | |
4130 | case 0x94: | |
4131 | case 0x95: | |
4132 | case 0x96: | |
4133 | case 0x97: | |
cf648174 HZ |
4134 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4135 | I386_RECORD_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
4136 | break; |
4137 | ||
4138 | /* xchg Ev, Gv */ | |
4139 | case 0x86: | |
4140 | case 0x87: | |
4141 | if ((opcode & 1) == 0) | |
4142 | ir.ot = OT_BYTE; | |
4143 | else | |
4144 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4145 | if (i386_record_modrm (&ir)) |
4146 | return -1; | |
7ad10968 HZ |
4147 | if (ir.mod == 3) |
4148 | { | |
86839d38 | 4149 | ir.rm |= ir.rex_b; |
cf648174 HZ |
4150 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
4151 | ir.rm &= 0x3; | |
4152 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); | |
7ad10968 HZ |
4153 | } |
4154 | else | |
4155 | { | |
4156 | if (i386_record_lea_modrm (&ir)) | |
4157 | return -1; | |
4158 | } | |
cf648174 HZ |
4159 | ir.reg |= rex_r; |
4160 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4161 | ir.reg &= 0x3; |
cf648174 | 4162 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4163 | break; |
4164 | ||
4165 | /* les Gv */ | |
4166 | case 0xc4: | |
4167 | /* lds Gv */ | |
4168 | case 0xc5: | |
cf648174 HZ |
4169 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4170 | { | |
4171 | ir.addr -= 1; | |
4172 | goto no_support; | |
4173 | } | |
7ad10968 HZ |
4174 | /* lss Gv */ |
4175 | case 0x0fb2: | |
4176 | /* lfs Gv */ | |
4177 | case 0x0fb4: | |
4178 | /* lgs Gv */ | |
4179 | case 0x0fb5: | |
4180 | if (i386_record_modrm (&ir)) | |
4181 | return -1; | |
4182 | if (ir.mod == 3) | |
4183 | { | |
4184 | if (opcode > 0xff) | |
4185 | ir.addr -= 3; | |
4186 | else | |
4187 | ir.addr -= 2; | |
4188 | opcode = opcode << 8 | ir.modrm; | |
4189 | goto no_support; | |
4190 | } | |
7ad10968 HZ |
4191 | switch (opcode) |
4192 | { | |
4193 | /* les Gv */ | |
4194 | case 0xc4: | |
cf648174 | 4195 | tmpu8 = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
4196 | break; |
4197 | /* lds Gv */ | |
4198 | case 0xc5: | |
cf648174 | 4199 | tmpu8 = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
4200 | break; |
4201 | /* lss Gv */ | |
4202 | case 0x0fb2: | |
cf648174 | 4203 | tmpu8 = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
4204 | break; |
4205 | /* lfs Gv */ | |
4206 | case 0x0fb4: | |
cf648174 | 4207 | tmpu8 = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
4208 | break; |
4209 | /* lgs Gv */ | |
4210 | case 0x0fb5: | |
cf648174 | 4211 | tmpu8 = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
4212 | break; |
4213 | } | |
cf648174 HZ |
4214 | I386_RECORD_ARCH_LIST_ADD_REG (tmpu8); |
4215 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
4216 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4217 | break; |
4218 | ||
4219 | /* shifts */ | |
4220 | case 0xc0: | |
4221 | case 0xc1: | |
4222 | case 0xd0: | |
4223 | case 0xd1: | |
4224 | case 0xd2: | |
4225 | case 0xd3: | |
4226 | if ((opcode & 1) == 0) | |
4227 | ir.ot = OT_BYTE; | |
4228 | else | |
4229 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
4230 | if (i386_record_modrm (&ir)) |
4231 | return -1; | |
7ad10968 HZ |
4232 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
4233 | { | |
4234 | if (i386_record_lea_modrm (&ir)) | |
4235 | return -1; | |
4236 | } | |
4237 | else | |
4238 | { | |
cf648174 HZ |
4239 | ir.rm |= ir.rex_b; |
4240 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 4241 | ir.rm &= 0x3; |
cf648174 | 4242 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 4243 | } |
cf648174 | 4244 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4245 | break; |
4246 | ||
4247 | case 0x0fa4: | |
4248 | case 0x0fa5: | |
4249 | case 0x0fac: | |
4250 | case 0x0fad: | |
4251 | if (i386_record_modrm (&ir)) | |
4252 | return -1; | |
4253 | if (ir.mod == 3) | |
4254 | { | |
4255 | if (record_arch_list_add_reg (ir.regcache, ir.rm)) | |
4256 | return -1; | |
4257 | } | |
4258 | else | |
4259 | { | |
4260 | if (i386_record_lea_modrm (&ir)) | |
4261 | return -1; | |
4262 | } | |
4263 | break; | |
4264 | ||
4265 | /* floats */ | |
4266 | /* It just record the memory change of instrcution. */ | |
4267 | case 0xd8: | |
4268 | case 0xd9: | |
4269 | case 0xda: | |
4270 | case 0xdb: | |
4271 | case 0xdc: | |
4272 | case 0xdd: | |
4273 | case 0xde: | |
4274 | case 0xdf: | |
4275 | if (i386_record_modrm (&ir)) | |
4276 | return -1; | |
4277 | ir.reg |= ((opcode & 7) << 3); | |
4278 | if (ir.mod != 3) | |
4279 | { | |
4280 | /* memory */ | |
cf648174 | 4281 | uint64_t tmpu64; |
7ad10968 | 4282 | |
cf648174 | 4283 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 HZ |
4284 | return -1; |
4285 | switch (ir.reg) | |
4286 | { | |
4287 | case 0x00: | |
4288 | case 0x01: | |
4289 | case 0x02: | |
4290 | case 0x03: | |
4291 | case 0x04: | |
4292 | case 0x05: | |
4293 | case 0x06: | |
4294 | case 0x07: | |
4295 | case 0x10: | |
4296 | case 0x11: | |
4297 | case 0x12: | |
4298 | case 0x13: | |
4299 | case 0x14: | |
4300 | case 0x15: | |
4301 | case 0x16: | |
4302 | case 0x17: | |
4303 | case 0x20: | |
4304 | case 0x21: | |
4305 | case 0x22: | |
4306 | case 0x23: | |
4307 | case 0x24: | |
4308 | case 0x25: | |
4309 | case 0x26: | |
4310 | case 0x27: | |
4311 | case 0x30: | |
4312 | case 0x31: | |
4313 | case 0x32: | |
4314 | case 0x33: | |
4315 | case 0x34: | |
4316 | case 0x35: | |
4317 | case 0x36: | |
4318 | case 0x37: | |
4319 | break; | |
4320 | case 0x08: | |
4321 | case 0x0a: | |
4322 | case 0x0b: | |
4323 | case 0x18: | |
4324 | case 0x19: | |
4325 | case 0x1a: | |
4326 | case 0x1b: | |
4327 | case 0x28: | |
4328 | case 0x29: | |
4329 | case 0x2a: | |
4330 | case 0x2b: | |
4331 | case 0x38: | |
4332 | case 0x39: | |
4333 | case 0x3a: | |
4334 | case 0x3b: | |
4335 | switch (ir.reg & 7) | |
4336 | { | |
4337 | case 0: | |
4338 | break; | |
4339 | case 1: | |
4340 | switch (ir.reg >> 4) | |
4341 | { | |
4342 | case 0: | |
cf648174 | 4343 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 HZ |
4344 | return -1; |
4345 | break; | |
4346 | case 2: | |
cf648174 | 4347 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 HZ |
4348 | return -1; |
4349 | break; | |
4350 | case 3: | |
4351 | default: | |
cf648174 | 4352 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4353 | return -1; |
4354 | break; | |
4355 | } | |
4356 | break; | |
4357 | default: | |
4358 | switch (ir.reg >> 4) | |
4359 | { | |
4360 | case 0: | |
4361 | case 1: | |
cf648174 | 4362 | if (record_arch_list_add_mem (tmpu64, 4)) |
7ad10968 HZ |
4363 | return -1; |
4364 | break; | |
4365 | case 2: | |
cf648174 | 4366 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 HZ |
4367 | return -1; |
4368 | break; | |
4369 | case 3: | |
4370 | default: | |
cf648174 | 4371 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4372 | return -1; |
4373 | break; | |
4374 | } | |
4375 | break; | |
4376 | } | |
4377 | break; | |
4378 | case 0x0c: | |
4379 | case 0x0d: | |
4380 | case 0x1d: | |
4381 | case 0x2c: | |
4382 | case 0x3c: | |
4383 | case 0x3d: | |
4384 | break; | |
4385 | case 0x0e: | |
4386 | if (ir.dflag) | |
4387 | { | |
cf648174 | 4388 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 HZ |
4389 | return -1; |
4390 | } | |
4391 | else | |
4392 | { | |
cf648174 | 4393 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 HZ |
4394 | return -1; |
4395 | } | |
4396 | break; | |
4397 | case 0x0f: | |
4398 | case 0x2f: | |
cf648174 | 4399 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
4400 | return -1; |
4401 | break; | |
4402 | case 0x1f: | |
4403 | case 0x3e: | |
cf648174 | 4404 | if (record_arch_list_add_mem (tmpu64, 10)) |
7ad10968 HZ |
4405 | return -1; |
4406 | break; | |
4407 | case 0x2e: | |
4408 | if (ir.dflag) | |
4409 | { | |
cf648174 | 4410 | if (record_arch_list_add_mem (tmpu64, 28)) |
7ad10968 | 4411 | return -1; |
cf648174 | 4412 | tmpu64 += 28; |
7ad10968 HZ |
4413 | } |
4414 | else | |
4415 | { | |
cf648174 | 4416 | if (record_arch_list_add_mem (tmpu64, 14)) |
7ad10968 | 4417 | return -1; |
cf648174 | 4418 | tmpu64 += 14; |
7ad10968 | 4419 | } |
cf648174 | 4420 | if (record_arch_list_add_mem (tmpu64, 80)) |
7ad10968 HZ |
4421 | return -1; |
4422 | break; | |
4423 | case 0x3f: | |
cf648174 | 4424 | if (record_arch_list_add_mem (tmpu64, 8)) |
7ad10968 HZ |
4425 | return -1; |
4426 | break; | |
4427 | default: | |
4428 | ir.addr -= 2; | |
4429 | opcode = opcode << 8 | ir.modrm; | |
4430 | goto no_support; | |
4431 | break; | |
4432 | } | |
4433 | } | |
4434 | break; | |
4435 | ||
4436 | /* string ops */ | |
4437 | /* movsS */ | |
4438 | case 0xa4: | |
4439 | case 0xa5: | |
4440 | /* stosS */ | |
4441 | case 0xaa: | |
4442 | case 0xab: | |
4443 | /* insS */ | |
4444 | case 0x6c: | |
4445 | case 0x6d: | |
cf648174 | 4446 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 4447 | ir.regmap[X86_RECORD_RECX_REGNUM], |
cf648174 | 4448 | &tmpulongest); |
77d7dc92 | 4449 | if (tmpulongest) |
cf648174 | 4450 | { |
77d7dc92 HZ |
4451 | ULONGEST es, ds; |
4452 | ||
4453 | if ((opcode & 1) == 0) | |
4454 | ir.ot = OT_BYTE; | |
4455 | else | |
4456 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
4457 | regcache_raw_read_unsigned (ir.regcache, |
4458 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
77d7dc92 HZ |
4459 | &tmpulongest); |
4460 | ||
d7877f7e HZ |
4461 | regcache_raw_read_unsigned (ir.regcache, |
4462 | ir.regmap[X86_RECORD_ES_REGNUM], | |
4463 | &es); | |
4464 | regcache_raw_read_unsigned (ir.regcache, | |
4465 | ir.regmap[X86_RECORD_DS_REGNUM], | |
4466 | &ds); | |
4467 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
4468 | { |
4469 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
df61f520 | 4470 | warning (_("Process record ignores the memory " |
926569ae | 4471 | "change of instruction at address %s " |
df61f520 HZ |
4472 | "because it can't get the value of the " |
4473 | "ES segment register."), | |
4474 | paddress (gdbarch, ir.orig_addr)); | |
4475 | } | |
4476 | else | |
4477 | { | |
4478 | if (record_arch_list_add_mem (tmpulongest, 1 << ir.ot)) | |
4479 | return -1; | |
77d7dc92 HZ |
4480 | } |
4481 | ||
4482 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4483 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
77d7dc92 HZ |
4484 | if (opcode == 0xa4 || opcode == 0xa5) |
4485 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4486 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4487 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4488 | } | |
cf648174 | 4489 | break; |
7ad10968 | 4490 | |
cf648174 HZ |
4491 | /* cmpsS */ |
4492 | case 0xa6: | |
4493 | case 0xa7: | |
4494 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
4495 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
4496 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
4497 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
4498 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4499 | break; |
4500 | ||
4501 | /* lodsS */ | |
4502 | case 0xac: | |
4503 | case 0xad: | |
cf648174 HZ |
4504 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
4505 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4506 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4507 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4508 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4509 | break; |
4510 | ||
4511 | /* scasS */ | |
4512 | case 0xae: | |
4513 | case 0xaf: | |
cf648174 | 4514 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 4515 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4516 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4517 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4518 | break; |
4519 | ||
cf648174 HZ |
4520 | /* outsS */ |
4521 | case 0x6e: | |
4522 | case 0x6f: | |
4523 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 4524 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
cf648174 HZ |
4525 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4526 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4527 | break; |
4528 | ||
4529 | /* port I/O */ | |
4530 | case 0xe4: | |
4531 | case 0xe5: | |
4532 | case 0xec: | |
4533 | case 0xed: | |
cf648174 HZ |
4534 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4535 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4536 | break; |
4537 | ||
4538 | case 0xe6: | |
4539 | case 0xe7: | |
4540 | case 0xee: | |
4541 | case 0xef: | |
4542 | break; | |
4543 | ||
4544 | /* control */ | |
4545 | /* ret im */ | |
4546 | case 0xc2: | |
4547 | /* ret */ | |
4548 | case 0xc3: | |
cf648174 HZ |
4549 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4550 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4551 | break; | |
4552 | ||
7ad10968 HZ |
4553 | /* lret im */ |
4554 | case 0xca: | |
4555 | /* lret */ | |
4556 | case 0xcb: | |
7ad10968 HZ |
4557 | /* iret */ |
4558 | case 0xcf: | |
cf648174 HZ |
4559 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
4560 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
4561 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4562 | break; |
4563 | ||
4564 | /* call im */ | |
4565 | case 0xe8: | |
cf648174 HZ |
4566 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
4567 | ir.dflag = 2; | |
4568 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4569 | return -1; | |
7ad10968 HZ |
4570 | break; |
4571 | ||
4572 | /* lcall im */ | |
4573 | case 0x9a: | |
cf648174 HZ |
4574 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4575 | { | |
4576 | ir.addr -= 1; | |
4577 | goto no_support; | |
4578 | } | |
4579 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); | |
4580 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4581 | return -1; | |
7ad10968 HZ |
4582 | break; |
4583 | ||
4584 | /* jmp im */ | |
4585 | case 0xe9: | |
4586 | /* ljmp im */ | |
4587 | case 0xea: | |
4588 | /* jmp Jb */ | |
4589 | case 0xeb: | |
4590 | /* jcc Jb */ | |
4591 | case 0x70: | |
4592 | case 0x71: | |
4593 | case 0x72: | |
4594 | case 0x73: | |
4595 | case 0x74: | |
4596 | case 0x75: | |
4597 | case 0x76: | |
4598 | case 0x77: | |
4599 | case 0x78: | |
4600 | case 0x79: | |
4601 | case 0x7a: | |
4602 | case 0x7b: | |
4603 | case 0x7c: | |
4604 | case 0x7d: | |
4605 | case 0x7e: | |
4606 | case 0x7f: | |
4607 | /* jcc Jv */ | |
4608 | case 0x0f80: | |
4609 | case 0x0f81: | |
4610 | case 0x0f82: | |
4611 | case 0x0f83: | |
4612 | case 0x0f84: | |
4613 | case 0x0f85: | |
4614 | case 0x0f86: | |
4615 | case 0x0f87: | |
4616 | case 0x0f88: | |
4617 | case 0x0f89: | |
4618 | case 0x0f8a: | |
4619 | case 0x0f8b: | |
4620 | case 0x0f8c: | |
4621 | case 0x0f8d: | |
4622 | case 0x0f8e: | |
4623 | case 0x0f8f: | |
4624 | break; | |
4625 | ||
4626 | /* setcc Gv */ | |
4627 | case 0x0f90: | |
4628 | case 0x0f91: | |
4629 | case 0x0f92: | |
4630 | case 0x0f93: | |
4631 | case 0x0f94: | |
4632 | case 0x0f95: | |
4633 | case 0x0f96: | |
4634 | case 0x0f97: | |
4635 | case 0x0f98: | |
4636 | case 0x0f99: | |
4637 | case 0x0f9a: | |
4638 | case 0x0f9b: | |
4639 | case 0x0f9c: | |
4640 | case 0x0f9d: | |
4641 | case 0x0f9e: | |
4642 | case 0x0f9f: | |
cf648174 | 4643 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4644 | ir.ot = OT_BYTE; |
4645 | if (i386_record_modrm (&ir)) | |
4646 | return -1; | |
4647 | if (ir.mod == 3) | |
cf648174 HZ |
4648 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
4649 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
4650 | else |
4651 | { | |
4652 | if (i386_record_lea_modrm (&ir)) | |
4653 | return -1; | |
4654 | } | |
4655 | break; | |
4656 | ||
4657 | /* cmov Gv, Ev */ | |
4658 | case 0x0f40: | |
4659 | case 0x0f41: | |
4660 | case 0x0f42: | |
4661 | case 0x0f43: | |
4662 | case 0x0f44: | |
4663 | case 0x0f45: | |
4664 | case 0x0f46: | |
4665 | case 0x0f47: | |
4666 | case 0x0f48: | |
4667 | case 0x0f49: | |
4668 | case 0x0f4a: | |
4669 | case 0x0f4b: | |
4670 | case 0x0f4c: | |
4671 | case 0x0f4d: | |
4672 | case 0x0f4e: | |
4673 | case 0x0f4f: | |
4674 | if (i386_record_modrm (&ir)) | |
4675 | return -1; | |
cf648174 | 4676 | ir.reg |= rex_r; |
7ad10968 HZ |
4677 | if (ir.dflag == OT_BYTE) |
4678 | ir.reg &= 0x3; | |
cf648174 | 4679 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
4680 | break; |
4681 | ||
4682 | /* flags */ | |
4683 | /* pushf */ | |
4684 | case 0x9c: | |
cf648174 HZ |
4685 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4686 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) | |
4687 | ir.dflag = 2; | |
4688 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
4689 | return -1; | |
7ad10968 HZ |
4690 | break; |
4691 | ||
4692 | /* popf */ | |
4693 | case 0x9d: | |
cf648174 HZ |
4694 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
4695 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4696 | break; |
4697 | ||
4698 | /* sahf */ | |
4699 | case 0x9e: | |
cf648174 HZ |
4700 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4701 | { | |
4702 | ir.addr -= 1; | |
4703 | goto no_support; | |
4704 | } | |
7ad10968 HZ |
4705 | /* cmc */ |
4706 | case 0xf5: | |
4707 | /* clc */ | |
4708 | case 0xf8: | |
4709 | /* stc */ | |
4710 | case 0xf9: | |
4711 | /* cld */ | |
4712 | case 0xfc: | |
4713 | /* std */ | |
4714 | case 0xfd: | |
cf648174 | 4715 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4716 | break; |
4717 | ||
4718 | /* lahf */ | |
4719 | case 0x9f: | |
cf648174 HZ |
4720 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4721 | { | |
4722 | ir.addr -= 1; | |
4723 | goto no_support; | |
4724 | } | |
4725 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
4726 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
4727 | break; |
4728 | ||
4729 | /* bit operations */ | |
4730 | /* bt/bts/btr/btc Gv, im */ | |
4731 | case 0x0fba: | |
7ad10968 HZ |
4732 | ir.ot = ir.dflag + OT_WORD; |
4733 | if (i386_record_modrm (&ir)) | |
4734 | return -1; | |
4735 | if (ir.reg < 4) | |
4736 | { | |
cf648174 | 4737 | ir.addr -= 2; |
7ad10968 HZ |
4738 | opcode = opcode << 8 | ir.modrm; |
4739 | goto no_support; | |
4740 | } | |
cf648174 | 4741 | if (ir.reg != 4) |
7ad10968 | 4742 | { |
cf648174 HZ |
4743 | if (ir.mod == 3) |
4744 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
4745 | else |
4746 | { | |
cf648174 | 4747 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
4748 | return -1; |
4749 | } | |
4750 | } | |
cf648174 | 4751 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
4752 | break; |
4753 | ||
4754 | /* bt Gv, Ev */ | |
4755 | case 0x0fa3: | |
cf648174 HZ |
4756 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
4757 | break; | |
4758 | ||
4759 | /* bts */ | |
4760 | case 0x0fab: | |
4761 | /* btr */ | |
4762 | case 0x0fb3: | |
4763 | /* btc */ | |
4764 | case 0x0fbb: | |
4765 | ir.ot = ir.dflag + OT_WORD; | |
4766 | if (i386_record_modrm (&ir)) | |
4767 | return -1; | |
4768 | if (ir.mod == 3) | |
4769 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
4770 | else | |
4771 | { | |
4772 | uint64_t tmpu64; | |
4773 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) | |
4774 | return -1; | |
4775 | regcache_raw_read_unsigned (ir.regcache, | |
4776 | ir.regmap[ir.reg | rex_r], | |
4777 | &tmpulongest); | |
4778 | switch (ir.dflag) | |
4779 | { | |
4780 | case 0: | |
4781 | tmpu64 += ((int16_t) tmpulongest >> 4) << 4; | |
4782 | break; | |
4783 | case 1: | |
4784 | tmpu64 += ((int32_t) tmpulongest >> 5) << 5; | |
4785 | break; | |
4786 | case 2: | |
4787 | tmpu64 += ((int64_t) tmpulongest >> 6) << 6; | |
4788 | break; | |
4789 | } | |
4790 | if (record_arch_list_add_mem (tmpu64, 1 << ir.ot)) | |
4791 | return -1; | |
4792 | if (i386_record_lea_modrm (&ir)) | |
4793 | return -1; | |
4794 | } | |
4795 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4796 | break; |
4797 | ||
4798 | /* bsf */ | |
4799 | case 0x0fbc: | |
4800 | /* bsr */ | |
4801 | case 0x0fbd: | |
cf648174 HZ |
4802 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
4803 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4804 | break; |
4805 | ||
4806 | /* bcd */ | |
4807 | /* daa */ | |
4808 | case 0x27: | |
4809 | /* das */ | |
4810 | case 0x2f: | |
4811 | /* aaa */ | |
4812 | case 0x37: | |
4813 | /* aas */ | |
4814 | case 0x3f: | |
4815 | /* aam */ | |
4816 | case 0xd4: | |
4817 | /* aad */ | |
4818 | case 0xd5: | |
cf648174 HZ |
4819 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4820 | { | |
4821 | ir.addr -= 1; | |
4822 | goto no_support; | |
4823 | } | |
4824 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4825 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4826 | break; |
4827 | ||
4828 | /* misc */ | |
4829 | /* nop */ | |
4830 | case 0x90: | |
4831 | if (prefixes & PREFIX_LOCK) | |
4832 | { | |
4833 | ir.addr -= 1; | |
4834 | goto no_support; | |
4835 | } | |
4836 | break; | |
4837 | ||
4838 | /* fwait */ | |
4839 | /* XXX */ | |
4840 | case 0x9b: | |
4841 | printf_unfiltered (_("Process record doesn't support instruction " | |
4842 | "fwait.\n")); | |
4843 | ir.addr -= 1; | |
4844 | goto no_support; | |
4845 | break; | |
4846 | ||
4847 | /* int3 */ | |
4848 | /* XXX */ | |
4849 | case 0xcc: | |
4850 | printf_unfiltered (_("Process record doesn't support instruction " | |
4851 | "int3.\n")); | |
4852 | ir.addr -= 1; | |
4853 | goto no_support; | |
4854 | break; | |
4855 | ||
4856 | /* int */ | |
4857 | /* XXX */ | |
4858 | case 0xcd: | |
4859 | { | |
4860 | int ret; | |
4861 | if (target_read_memory (ir.addr, &tmpu8, 1)) | |
4862 | { | |
4863 | if (record_debug) | |
4864 | printf_unfiltered (_("Process record: error reading memory " | |
5af949e3 UW |
4865 | "at addr %s len = 1.\n"), |
4866 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
4867 | return -1; |
4868 | } | |
4869 | ir.addr++; | |
4870 | if (tmpu8 != 0x80 | |
4871 | || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) | |
4872 | { | |
4873 | printf_unfiltered (_("Process record doesn't support " | |
4874 | "instruction int 0x%02x.\n"), | |
4875 | tmpu8); | |
4876 | ir.addr -= 2; | |
4877 | goto no_support; | |
4878 | } | |
4879 | ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); | |
4880 | if (ret) | |
4881 | return ret; | |
4882 | } | |
4883 | break; | |
4884 | ||
4885 | /* into */ | |
4886 | /* XXX */ | |
4887 | case 0xce: | |
4888 | printf_unfiltered (_("Process record doesn't support " | |
4889 | "instruction into.\n")); | |
4890 | ir.addr -= 1; | |
4891 | goto no_support; | |
4892 | break; | |
4893 | ||
4894 | /* cli */ | |
4895 | case 0xfa: | |
4896 | /* sti */ | |
4897 | case 0xfb: | |
4898 | break; | |
4899 | ||
4900 | /* bound */ | |
4901 | case 0x62: | |
4902 | printf_unfiltered (_("Process record doesn't support " | |
4903 | "instruction bound.\n")); | |
4904 | ir.addr -= 1; | |
4905 | goto no_support; | |
4906 | break; | |
4907 | ||
4908 | /* bswap reg */ | |
4909 | case 0x0fc8: | |
4910 | case 0x0fc9: | |
4911 | case 0x0fca: | |
4912 | case 0x0fcb: | |
4913 | case 0x0fcc: | |
4914 | case 0x0fcd: | |
4915 | case 0x0fce: | |
4916 | case 0x0fcf: | |
cf648174 | 4917 | I386_RECORD_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
4918 | break; |
4919 | ||
4920 | /* salc */ | |
4921 | case 0xd6: | |
cf648174 HZ |
4922 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4923 | { | |
4924 | ir.addr -= 1; | |
4925 | goto no_support; | |
4926 | } | |
4927 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
4928 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4929 | break; |
4930 | ||
4931 | /* loopnz */ | |
4932 | case 0xe0: | |
4933 | /* loopz */ | |
4934 | case 0xe1: | |
4935 | /* loop */ | |
4936 | case 0xe2: | |
4937 | /* jecxz */ | |
4938 | case 0xe3: | |
cf648174 HZ |
4939 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
4940 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
4941 | break; |
4942 | ||
4943 | /* wrmsr */ | |
4944 | case 0x0f30: | |
4945 | printf_unfiltered (_("Process record doesn't support " | |
4946 | "instruction wrmsr.\n")); | |
4947 | ir.addr -= 2; | |
4948 | goto no_support; | |
4949 | break; | |
4950 | ||
4951 | /* rdmsr */ | |
4952 | case 0x0f32: | |
4953 | printf_unfiltered (_("Process record doesn't support " | |
4954 | "instruction rdmsr.\n")); | |
4955 | ir.addr -= 2; | |
4956 | goto no_support; | |
4957 | break; | |
4958 | ||
4959 | /* rdtsc */ | |
4960 | case 0x0f31: | |
4961 | printf_unfiltered (_("Process record doesn't support " | |
4962 | "instruction rdtsc.\n")); | |
4963 | ir.addr -= 2; | |
4964 | goto no_support; | |
4965 | break; | |
4966 | ||
4967 | /* sysenter */ | |
4968 | case 0x0f34: | |
4969 | { | |
4970 | int ret; | |
cf648174 HZ |
4971 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
4972 | { | |
4973 | ir.addr -= 2; | |
4974 | goto no_support; | |
4975 | } | |
7ad10968 HZ |
4976 | if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) |
4977 | { | |
4978 | printf_unfiltered (_("Process record doesn't support " | |
4979 | "instruction sysenter.\n")); | |
4980 | ir.addr -= 2; | |
4981 | goto no_support; | |
4982 | } | |
4983 | ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); | |
4984 | if (ret) | |
4985 | return ret; | |
4986 | } | |
4987 | break; | |
4988 | ||
4989 | /* sysexit */ | |
4990 | case 0x0f35: | |
4991 | printf_unfiltered (_("Process record doesn't support " | |
4992 | "instruction sysexit.\n")); | |
4993 | ir.addr -= 2; | |
4994 | goto no_support; | |
4995 | break; | |
4996 | ||
cf648174 HZ |
4997 | /* syscall */ |
4998 | case 0x0f05: | |
4999 | { | |
5000 | int ret; | |
5001 | if (gdbarch_tdep (gdbarch)->i386_syscall_record == NULL) | |
5002 | { | |
5003 | printf_unfiltered (_("Process record doesn't support " | |
5004 | "instruction syscall.\n")); | |
5005 | ir.addr -= 2; | |
5006 | goto no_support; | |
5007 | } | |
5008 | ret = gdbarch_tdep (gdbarch)->i386_syscall_record (ir.regcache); | |
5009 | if (ret) | |
5010 | return ret; | |
5011 | } | |
5012 | break; | |
5013 | ||
5014 | /* sysret */ | |
5015 | case 0x0f07: | |
5016 | printf_unfiltered (_("Process record doesn't support " | |
5017 | "instruction sysret.\n")); | |
5018 | ir.addr -= 2; | |
5019 | goto no_support; | |
5020 | break; | |
5021 | ||
7ad10968 HZ |
5022 | /* cpuid */ |
5023 | case 0x0fa2: | |
cf648174 HZ |
5024 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5025 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
5026 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5027 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
5028 | break; |
5029 | ||
5030 | /* hlt */ | |
5031 | case 0xf4: | |
5032 | printf_unfiltered (_("Process record doesn't support " | |
5033 | "instruction hlt.\n")); | |
5034 | ir.addr -= 1; | |
5035 | goto no_support; | |
5036 | break; | |
5037 | ||
5038 | case 0x0f00: | |
5039 | if (i386_record_modrm (&ir)) | |
5040 | return -1; | |
5041 | switch (ir.reg) | |
5042 | { | |
5043 | /* sldt */ | |
5044 | case 0: | |
5045 | /* str */ | |
5046 | case 1: | |
5047 | if (ir.mod == 3) | |
cf648174 | 5048 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5049 | else |
5050 | { | |
5051 | ir.ot = OT_WORD; | |
5052 | if (i386_record_lea_modrm (&ir)) | |
5053 | return -1; | |
5054 | } | |
5055 | break; | |
5056 | /* lldt */ | |
5057 | case 2: | |
5058 | /* ltr */ | |
5059 | case 3: | |
5060 | break; | |
5061 | /* verr */ | |
5062 | case 4: | |
5063 | /* verw */ | |
5064 | case 5: | |
cf648174 | 5065 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5066 | break; |
5067 | default: | |
5068 | ir.addr -= 3; | |
5069 | opcode = opcode << 8 | ir.modrm; | |
5070 | goto no_support; | |
5071 | break; | |
5072 | } | |
5073 | break; | |
5074 | ||
5075 | case 0x0f01: | |
5076 | if (i386_record_modrm (&ir)) | |
5077 | return -1; | |
5078 | switch (ir.reg) | |
5079 | { | |
5080 | /* sgdt */ | |
5081 | case 0: | |
5082 | { | |
cf648174 | 5083 | uint64_t tmpu64; |
7ad10968 HZ |
5084 | |
5085 | if (ir.mod == 3) | |
5086 | { | |
5087 | ir.addr -= 3; | |
5088 | opcode = opcode << 8 | ir.modrm; | |
5089 | goto no_support; | |
5090 | } | |
d7877f7e | 5091 | if (ir.override >= 0) |
7ad10968 | 5092 | { |
df61f520 HZ |
5093 | warning (_("Process record ignores the memory " |
5094 | "change of instruction at " | |
5095 | "address %s because it can't get " | |
5096 | "the value of the segment " | |
5097 | "register."), | |
5098 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5099 | } |
5100 | else | |
5101 | { | |
cf648174 | 5102 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5103 | return -1; |
cf648174 | 5104 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 | 5105 | return -1; |
cf648174 HZ |
5106 | tmpu64 += 2; |
5107 | if (ir.regmap[X86_RECORD_R8_REGNUM]) | |
5108 | { | |
5109 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5110 | return -1; | |
5111 | } | |
5112 | else | |
5113 | { | |
5114 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5115 | return -1; | |
5116 | } | |
7ad10968 HZ |
5117 | } |
5118 | } | |
5119 | break; | |
5120 | case 1: | |
5121 | if (ir.mod == 3) | |
5122 | { | |
5123 | switch (ir.rm) | |
5124 | { | |
5125 | /* monitor */ | |
5126 | case 0: | |
5127 | break; | |
5128 | /* mwait */ | |
5129 | case 1: | |
cf648174 | 5130 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5131 | break; |
5132 | default: | |
5133 | ir.addr -= 3; | |
5134 | opcode = opcode << 8 | ir.modrm; | |
5135 | goto no_support; | |
5136 | break; | |
5137 | } | |
5138 | } | |
5139 | else | |
5140 | { | |
5141 | /* sidt */ | |
d7877f7e | 5142 | if (ir.override >= 0) |
7ad10968 | 5143 | { |
df61f520 HZ |
5144 | warning (_("Process record ignores the memory " |
5145 | "change of instruction at " | |
5146 | "address %s because it can't get " | |
5147 | "the value of the segment " | |
5148 | "register."), | |
5149 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
5150 | } |
5151 | else | |
5152 | { | |
cf648174 | 5153 | uint64_t tmpu64; |
7ad10968 | 5154 | |
cf648174 | 5155 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7ad10968 | 5156 | return -1; |
cf648174 | 5157 | if (record_arch_list_add_mem (tmpu64, 2)) |
7ad10968 HZ |
5158 | return -1; |
5159 | addr += 2; | |
cf648174 HZ |
5160 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5161 | { | |
5162 | if (record_arch_list_add_mem (tmpu64, 8)) | |
5163 | return -1; | |
5164 | } | |
5165 | else | |
5166 | { | |
5167 | if (record_arch_list_add_mem (tmpu64, 4)) | |
5168 | return -1; | |
5169 | } | |
7ad10968 HZ |
5170 | } |
5171 | } | |
5172 | break; | |
5173 | /* lgdt */ | |
5174 | case 2: | |
3800e645 MS |
5175 | if (ir.mod == 3) |
5176 | { | |
5177 | /* xgetbv */ | |
5178 | if (ir.rm == 0) | |
5179 | { | |
5180 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
5181 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
5182 | break; | |
5183 | } | |
5184 | /* xsetbv */ | |
5185 | else if (ir.rm == 1) | |
5186 | break; | |
5187 | } | |
7ad10968 HZ |
5188 | /* lidt */ |
5189 | case 3: | |
7ad10968 HZ |
5190 | if (ir.mod == 3) |
5191 | { | |
5192 | ir.addr -= 3; | |
5193 | opcode = opcode << 8 | ir.modrm; | |
5194 | goto no_support; | |
5195 | } | |
5196 | break; | |
5197 | /* smsw */ | |
5198 | case 4: | |
5199 | if (ir.mod == 3) | |
5200 | { | |
cf648174 | 5201 | if (record_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
5202 | return -1; |
5203 | } | |
5204 | else | |
5205 | { | |
5206 | ir.ot = OT_WORD; | |
5207 | if (i386_record_lea_modrm (&ir)) | |
5208 | return -1; | |
5209 | } | |
cf648174 | 5210 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5211 | break; |
5212 | /* lmsw */ | |
5213 | case 6: | |
cf648174 HZ |
5214 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
5215 | break; | |
5216 | /* invlpg */ | |
5217 | case 7: | |
5218 | if (ir.mod == 3) | |
5219 | { | |
5220 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
5221 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5222 | else | |
5223 | { | |
5224 | ir.addr -= 3; | |
5225 | opcode = opcode << 8 | ir.modrm; | |
5226 | goto no_support; | |
5227 | } | |
5228 | } | |
5229 | else | |
5230 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5231 | break; | |
5232 | default: | |
5233 | ir.addr -= 3; | |
5234 | opcode = opcode << 8 | ir.modrm; | |
5235 | goto no_support; | |
7ad10968 HZ |
5236 | break; |
5237 | } | |
5238 | break; | |
5239 | ||
5240 | /* invd */ | |
5241 | case 0x0f08: | |
5242 | /* wbinvd */ | |
5243 | case 0x0f09: | |
5244 | break; | |
5245 | ||
5246 | /* arpl */ | |
5247 | case 0x63: | |
7ad10968 HZ |
5248 | if (i386_record_modrm (&ir)) |
5249 | return -1; | |
cf648174 HZ |
5250 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
5251 | { | |
5252 | I386_RECORD_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
5253 | ? (ir.reg | rex_r) : ir.rm); | |
5254 | } | |
7ad10968 | 5255 | else |
cf648174 HZ |
5256 | { |
5257 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
5258 | if (i386_record_lea_modrm (&ir)) | |
5259 | return -1; | |
5260 | } | |
5261 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
5262 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5263 | break; |
5264 | ||
5265 | /* lar */ | |
5266 | case 0x0f02: | |
5267 | /* lsl */ | |
5268 | case 0x0f03: | |
5269 | if (i386_record_modrm (&ir)) | |
5270 | return -1; | |
cf648174 HZ |
5271 | I386_RECORD_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
5272 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5273 | break; |
5274 | ||
5275 | case 0x0f18: | |
cf648174 HZ |
5276 | if (i386_record_modrm (&ir)) |
5277 | return -1; | |
5278 | if (ir.mod == 3 && ir.reg == 3) | |
5279 | { | |
5280 | ir.addr -= 3; | |
5281 | opcode = opcode << 8 | ir.modrm; | |
5282 | goto no_support; | |
5283 | } | |
7ad10968 HZ |
5284 | break; |
5285 | ||
5286 | /* nop (multi byte) */ | |
5287 | case 0x0f19: | |
5288 | case 0x0f1a: | |
5289 | case 0x0f1b: | |
5290 | case 0x0f1c: | |
5291 | case 0x0f1d: | |
5292 | case 0x0f1e: | |
5293 | case 0x0f1f: | |
5294 | break; | |
5295 | ||
5296 | /* mov reg, crN */ | |
5297 | case 0x0f20: | |
5298 | /* mov crN, reg */ | |
5299 | case 0x0f22: | |
5300 | if (i386_record_modrm (&ir)) | |
5301 | return -1; | |
5302 | if ((ir.modrm & 0xc0) != 0xc0) | |
5303 | { | |
cf648174 | 5304 | ir.addr -= 3; |
7ad10968 HZ |
5305 | opcode = opcode << 8 | ir.modrm; |
5306 | goto no_support; | |
5307 | } | |
5308 | switch (ir.reg) | |
5309 | { | |
5310 | case 0: | |
5311 | case 2: | |
5312 | case 3: | |
5313 | case 4: | |
5314 | case 8: | |
5315 | if (opcode & 2) | |
cf648174 | 5316 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5317 | else |
cf648174 | 5318 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5319 | break; |
5320 | default: | |
cf648174 | 5321 | ir.addr -= 3; |
7ad10968 HZ |
5322 | opcode = opcode << 8 | ir.modrm; |
5323 | goto no_support; | |
5324 | break; | |
5325 | } | |
5326 | break; | |
5327 | ||
5328 | /* mov reg, drN */ | |
5329 | case 0x0f21: | |
5330 | /* mov drN, reg */ | |
5331 | case 0x0f23: | |
5332 | if (i386_record_modrm (&ir)) | |
5333 | return -1; | |
5334 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
5335 | || ir.reg == 5 || ir.reg >= 8) | |
5336 | { | |
cf648174 | 5337 | ir.addr -= 3; |
7ad10968 HZ |
5338 | opcode = opcode << 8 | ir.modrm; |
5339 | goto no_support; | |
5340 | } | |
5341 | if (opcode & 2) | |
cf648174 | 5342 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5343 | else |
cf648174 | 5344 | I386_RECORD_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5345 | break; |
5346 | ||
5347 | /* clts */ | |
5348 | case 0x0f06: | |
cf648174 | 5349 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5350 | break; |
5351 | ||
5352 | /* MMX/SSE/SSE2/PNI support */ | |
5353 | /* XXX */ | |
5354 | ||
5355 | default: | |
5356 | if (opcode > 0xff) | |
5357 | ir.addr -= 2; | |
5358 | else | |
5359 | ir.addr -= 1; | |
5360 | goto no_support; | |
5361 | break; | |
5362 | } | |
5363 | ||
cf648174 HZ |
5364 | /* In the future, maybe still need to deal with need_dasm. */ |
5365 | I386_RECORD_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); | |
7ad10968 HZ |
5366 | if (record_arch_list_add_end ()) |
5367 | return -1; | |
5368 | ||
5369 | return 0; | |
5370 | ||
5371 | no_support: | |
5372 | printf_unfiltered (_("Process record doesn't support instruction 0x%02x " | |
5af949e3 UW |
5373 | "at address %s.\n"), |
5374 | (unsigned int) (opcode), paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5375 | return -1; |
5376 | } | |
5377 | ||
cf648174 HZ |
5378 | static const int i386_record_regmap[] = |
5379 | { | |
5380 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
5381 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
5382 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5383 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
5384 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
5385 | }; | |
5386 | ||
7ad10968 HZ |
5387 | \f |
5388 | static struct gdbarch * | |
5389 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5390 | { | |
5391 | struct gdbarch_tdep *tdep; | |
5392 | struct gdbarch *gdbarch; | |
5393 | ||
5394 | /* If there is already a candidate, use it. */ | |
5395 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
5396 | if (arches != NULL) | |
5397 | return arches->gdbarch; | |
5398 | ||
5399 | /* Allocate space for the new architecture. */ | |
5400 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
5401 | gdbarch = gdbarch_alloc (&info, tdep); | |
5402 | ||
5403 | /* General-purpose registers. */ | |
5404 | tdep->gregset = NULL; | |
5405 | tdep->gregset_reg_offset = NULL; | |
5406 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
5407 | tdep->sizeof_gregset = 0; | |
5408 | ||
5409 | /* Floating-point registers. */ | |
5410 | tdep->fpregset = NULL; | |
5411 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
5412 | ||
5413 | /* The default settings include the FPU registers, the MMX registers | |
5414 | and the SSE registers. This can be overridden for a specific ABI | |
5415 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
5416 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
5417 | will show up in the output of "info all-registers". Ideally we | |
5418 | should try to autodetect whether they are available, such that we | |
5419 | can prevent "info all-registers" from displaying registers that | |
5420 | aren't available. | |
5421 | ||
5422 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
5423 | [the SSE registers] always (even when they don't exist) or never | |
5424 | showing them to the user (even when they do exist), I prefer the | |
5425 | former over the latter. */ | |
5426 | ||
5427 | tdep->st0_regnum = I386_ST0_REGNUM; | |
5428 | ||
5429 | /* The MMX registers are implemented as pseudo-registers. Put off | |
5430 | calculating the register number for %mm0 until we know the number | |
5431 | of raw registers. */ | |
5432 | tdep->mm0_regnum = 0; | |
5433 | ||
5434 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
5435 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
5436 | ||
5437 | tdep->jb_pc_offset = -1; | |
5438 | tdep->struct_return = pcc_struct_return; | |
5439 | tdep->sigtramp_start = 0; | |
5440 | tdep->sigtramp_end = 0; | |
5441 | tdep->sigtramp_p = i386_sigtramp_p; | |
5442 | tdep->sigcontext_addr = NULL; | |
5443 | tdep->sc_reg_offset = NULL; | |
5444 | tdep->sc_pc_offset = -1; | |
5445 | tdep->sc_sp_offset = -1; | |
5446 | ||
cf648174 HZ |
5447 | tdep->record_regmap = i386_record_regmap; |
5448 | ||
7ad10968 HZ |
5449 | /* The format used for `long double' on almost all i386 targets is |
5450 | the i387 extended floating-point format. In fact, of all targets | |
5451 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
5452 | on having a `long double' that's not `long' at all. */ | |
5453 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
5454 | ||
5455 | /* Although the i387 extended floating-point has only 80 significant | |
5456 | bits, a `long double' actually takes up 96, probably to enforce | |
5457 | alignment. */ | |
5458 | set_gdbarch_long_double_bit (gdbarch, 96); | |
5459 | ||
5460 | /* The default ABI includes general-purpose registers, | |
5461 | floating-point registers, and the SSE registers. */ | |
5462 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
5463 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
5464 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
5465 | ||
5466 | /* Register numbers of various important registers. */ | |
5467 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
5468 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
5469 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
5470 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
5471 | ||
5472 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
5473 | numbering schemes on the i386: dbx and SVR4. These schemes | |
5474 | differ in how they number %ebp, %esp, %eflags, and the | |
5475 | floating-point registers, and are implemented by the arrays | |
5476 | dbx_register_map[] and svr4_dbx_register_map in | |
5477 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
5478 | gcc/config/i386.c, which it designates as the "default" register | |
5479 | map used in 64bit mode. This last register numbering scheme is | |
5480 | implemented in dbx64_register_map, and is used for AMD64; see | |
5481 | amd64-tdep.c. | |
5482 | ||
5483 | Currently, each GCC i386 target always uses the same register | |
5484 | numbering scheme across all its supported debugging formats | |
5485 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
5486 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
5487 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
5488 | respective config header in a manner independent of the requested | |
5489 | output debugging format. | |
5490 | ||
5491 | This does not match the arrangement below, which presumes that | |
5492 | the SDB and stabs numbering schemes differ from the DWARF and | |
5493 | DWARF 2 ones. The reason for this arrangement is that it is | |
5494 | likely to get the numbering scheme for the target's | |
5495 | default/native debug format right. For targets where GCC is the | |
5496 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
5497 | targets where the native toolchain uses a different numbering | |
5498 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
5499 | the defaults below will have to be overridden, like | |
5500 | i386_elf_init_abi() does. */ | |
5501 | ||
5502 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
5503 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5504 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
5505 | ||
5506 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
5507 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
5508 | ||
5509 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
5510 | be in use on any of the supported i386 targets. */ | |
5511 | ||
5512 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
5513 | ||
5514 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
5515 | ||
5516 | /* Call dummy code. */ | |
5517 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); | |
5518 | ||
5519 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
5520 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
5521 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
5522 | ||
5523 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
5524 | ||
5525 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
5526 | ||
5527 | /* Stack grows downward. */ | |
5528 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
5529 | ||
5530 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
5531 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
5532 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
5533 | ||
5534 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
5535 | ||
5536 | /* Wire in the MMX registers. */ | |
5537 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); | |
5538 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); | |
5539 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
5540 | ||
5541 | set_gdbarch_print_insn (gdbarch, i386_print_insn); | |
5542 | ||
5543 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
5544 | ||
5545 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
5546 | ||
5547 | /* Add the i386 register groups. */ | |
5548 | i386_add_reggroups (gdbarch); | |
5549 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
38c968cf | 5550 | |
143985b7 AF |
5551 | /* Helper for function argument information. */ |
5552 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
5553 | ||
06da04c6 MS |
5554 | /* Hook the function epilogue frame unwinder. This unwinder is |
5555 | appended to the list first, so that it supercedes the Dwarf | |
5556 | unwinder in function epilogues (where the Dwarf unwinder | |
5557 | currently fails). */ | |
5558 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
5559 | ||
5560 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
5561 | to the list before the prologue-based unwinders, so that Dwarf | |
5562 | CFI info will be used if it is available. */ | |
10458914 | 5563 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 5564 | |
acd5c798 | 5565 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 5566 | |
3ce1502b | 5567 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 5568 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 5569 | |
06da04c6 | 5570 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
10458914 DJ |
5571 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
5572 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 5573 | |
8446b36a MK |
5574 | /* If we have a register mapping, enable the generic core file |
5575 | support, unless it has already been enabled. */ | |
5576 | if (tdep->gregset_reg_offset | |
5577 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
5578 | set_gdbarch_regset_from_core_section (gdbarch, | |
5579 | i386_regset_from_core_section); | |
5580 | ||
5716833c MK |
5581 | /* Unless support for MMX has been disabled, make %mm0 the first |
5582 | pseudo-register. */ | |
5583 | if (tdep->mm0_regnum == 0) | |
5584 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
5585 | ||
514f746b AR |
5586 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
5587 | i386_skip_permanent_breakpoint); | |
5588 | ||
a62cc96e AC |
5589 | return gdbarch; |
5590 | } | |
5591 | ||
8201327c MK |
5592 | static enum gdb_osabi |
5593 | i386_coff_osabi_sniffer (bfd *abfd) | |
5594 | { | |
762c5349 MK |
5595 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
5596 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
5597 | return GDB_OSABI_GO32; |
5598 | ||
5599 | return GDB_OSABI_UNKNOWN; | |
5600 | } | |
8201327c MK |
5601 | \f |
5602 | ||
28e9e0f0 MK |
5603 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
5604 | void _initialize_i386_tdep (void); | |
5605 | ||
c906108c | 5606 | void |
fba45db2 | 5607 | _initialize_i386_tdep (void) |
c906108c | 5608 | { |
a62cc96e AC |
5609 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
5610 | ||
fc338970 | 5611 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
5612 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
5613 | &disassembly_flavor, _("\ | |
5614 | Set the disassembly flavor."), _("\ | |
5615 | Show the disassembly flavor."), _("\ | |
5616 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
5617 | NULL, | |
5618 | NULL, /* FIXME: i18n: */ | |
5619 | &setlist, &showlist); | |
8201327c MK |
5620 | |
5621 | /* Add the variable that controls the convention for returning | |
5622 | structs. */ | |
7ab04401 AC |
5623 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
5624 | &struct_convention, _("\ | |
5625 | Set the convention for returning small structs."), _("\ | |
5626 | Show the convention for returning small structs."), _("\ | |
5627 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
5628 | is \"default\"."), | |
5629 | NULL, | |
5630 | NULL, /* FIXME: i18n: */ | |
5631 | &setlist, &showlist); | |
8201327c MK |
5632 | |
5633 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
5634 | i386_coff_osabi_sniffer); | |
8201327c | 5635 | |
05816f70 | 5636 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 5637 | i386_svr4_init_abi); |
05816f70 | 5638 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 5639 | i386_go32_init_abi); |
38c968cf | 5640 | |
209bd28e | 5641 | /* Initialize the i386-specific register groups. */ |
38c968cf | 5642 | i386_init_reggroups (); |
c906108c | 5643 | } |