Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
6aba47ca | 3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
0fb0cc75 | 4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
5ae96ec1 | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
1903f0e6 | 23 | #include "opcode/i386.h" |
acd5c798 MK |
24 | #include "arch-utils.h" |
25 | #include "command.h" | |
26 | #include "dummy-frame.h" | |
6405b0a6 | 27 | #include "dwarf2-frame.h" |
acd5c798 | 28 | #include "doublest.h" |
c906108c | 29 | #include "frame.h" |
acd5c798 MK |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
c906108c | 32 | #include "inferior.h" |
acd5c798 | 33 | #include "gdbcmd.h" |
c906108c | 34 | #include "gdbcore.h" |
e6bb342a | 35 | #include "gdbtypes.h" |
dfe01d39 | 36 | #include "objfiles.h" |
acd5c798 MK |
37 | #include "osabi.h" |
38 | #include "regcache.h" | |
39 | #include "reggroups.h" | |
473f17b0 | 40 | #include "regset.h" |
c0d1d883 | 41 | #include "symfile.h" |
c906108c | 42 | #include "symtab.h" |
acd5c798 | 43 | #include "target.h" |
fd0407d6 | 44 | #include "value.h" |
a89aa300 | 45 | #include "dis-asm.h" |
acd5c798 | 46 | |
3d261580 | 47 | #include "gdb_assert.h" |
acd5c798 | 48 | #include "gdb_string.h" |
3d261580 | 49 | |
d2a7c97a | 50 | #include "i386-tdep.h" |
61113f8b | 51 | #include "i387-tdep.h" |
d2a7c97a | 52 | |
c4fc7f1b | 53 | /* Register names. */ |
c40e1eab | 54 | |
fc633446 MK |
55 | static char *i386_register_names[] = |
56 | { | |
57 | "eax", "ecx", "edx", "ebx", | |
58 | "esp", "ebp", "esi", "edi", | |
59 | "eip", "eflags", "cs", "ss", | |
60 | "ds", "es", "fs", "gs", | |
61 | "st0", "st1", "st2", "st3", | |
62 | "st4", "st5", "st6", "st7", | |
63 | "fctrl", "fstat", "ftag", "fiseg", | |
64 | "fioff", "foseg", "fooff", "fop", | |
65 | "xmm0", "xmm1", "xmm2", "xmm3", | |
66 | "xmm4", "xmm5", "xmm6", "xmm7", | |
67 | "mxcsr" | |
68 | }; | |
69 | ||
1cb97e17 | 70 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 71 | |
c4fc7f1b | 72 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
73 | |
74 | static char *i386_mmx_names[] = | |
75 | { | |
76 | "mm0", "mm1", "mm2", "mm3", | |
77 | "mm4", "mm5", "mm6", "mm7" | |
78 | }; | |
c40e1eab | 79 | |
1cb97e17 | 80 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 81 | |
28fc6740 | 82 | static int |
5716833c | 83 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 84 | { |
5716833c MK |
85 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
86 | ||
87 | if (mm0_regnum < 0) | |
88 | return 0; | |
89 | ||
90 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
91 | } |
92 | ||
5716833c | 93 | /* SSE register? */ |
23a34459 | 94 | |
5716833c MK |
95 | static int |
96 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 97 | { |
5716833c MK |
98 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
99 | ||
20a6ec49 | 100 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
101 | return 0; |
102 | ||
20a6ec49 MD |
103 | return (I387_XMM0_REGNUM (tdep) <= regnum |
104 | && regnum < I387_MXCSR_REGNUM (tdep)); | |
23a34459 AC |
105 | } |
106 | ||
5716833c MK |
107 | static int |
108 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 109 | { |
5716833c MK |
110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
111 | ||
20a6ec49 | 112 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
113 | return 0; |
114 | ||
20a6ec49 | 115 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
116 | } |
117 | ||
5716833c | 118 | /* FP register? */ |
23a34459 AC |
119 | |
120 | int | |
20a6ec49 | 121 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 122 | { |
20a6ec49 MD |
123 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
124 | ||
125 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
126 | return 0; |
127 | ||
20a6ec49 MD |
128 | return (I387_ST0_REGNUM (tdep) <= regnum |
129 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
130 | } |
131 | ||
132 | int | |
20a6ec49 | 133 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 134 | { |
20a6ec49 MD |
135 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
136 | ||
137 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
138 | return 0; |
139 | ||
20a6ec49 MD |
140 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
141 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
142 | } |
143 | ||
30b0e2d8 | 144 | /* Return the name of register REGNUM. */ |
fc633446 | 145 | |
fa88f677 | 146 | const char * |
d93859e2 | 147 | i386_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 148 | { |
d93859e2 | 149 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
20a6ec49 | 150 | return i386_mmx_names[regnum - I387_MM0_REGNUM (gdbarch_tdep (gdbarch))]; |
fc633446 | 151 | |
30b0e2d8 MK |
152 | if (regnum >= 0 && regnum < i386_num_register_names) |
153 | return i386_register_names[regnum]; | |
70913449 | 154 | |
c40e1eab | 155 | return NULL; |
fc633446 MK |
156 | } |
157 | ||
c4fc7f1b | 158 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
159 | number used by GDB. */ |
160 | ||
8201327c | 161 | static int |
d3f73121 | 162 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 163 | { |
20a6ec49 MD |
164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
165 | ||
c4fc7f1b MK |
166 | /* This implements what GCC calls the "default" register map |
167 | (dbx_register_map[]). */ | |
168 | ||
85540d8c MK |
169 | if (reg >= 0 && reg <= 7) |
170 | { | |
9872ad24 JB |
171 | /* General-purpose registers. The debug info calls %ebp |
172 | register 4, and %esp register 5. */ | |
173 | if (reg == 4) | |
174 | return 5; | |
175 | else if (reg == 5) | |
176 | return 4; | |
177 | else return reg; | |
85540d8c MK |
178 | } |
179 | else if (reg >= 12 && reg <= 19) | |
180 | { | |
181 | /* Floating-point registers. */ | |
20a6ec49 | 182 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
183 | } |
184 | else if (reg >= 21 && reg <= 28) | |
185 | { | |
186 | /* SSE registers. */ | |
20a6ec49 | 187 | return reg - 21 + I387_XMM0_REGNUM (tdep); |
85540d8c MK |
188 | } |
189 | else if (reg >= 29 && reg <= 36) | |
190 | { | |
191 | /* MMX registers. */ | |
20a6ec49 | 192 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
193 | } |
194 | ||
195 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 196 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
197 | } |
198 | ||
c4fc7f1b MK |
199 | /* Convert SVR4 register number REG to the appropriate register number |
200 | used by GDB. */ | |
85540d8c | 201 | |
8201327c | 202 | static int |
d3f73121 | 203 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 204 | { |
20a6ec49 MD |
205 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
206 | ||
c4fc7f1b MK |
207 | /* This implements the GCC register map that tries to be compatible |
208 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
209 | ||
210 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
211 | numbers the floating point registers differently. */ |
212 | if (reg >= 0 && reg <= 9) | |
213 | { | |
acd5c798 | 214 | /* General-purpose registers. */ |
85540d8c MK |
215 | return reg; |
216 | } | |
217 | else if (reg >= 11 && reg <= 18) | |
218 | { | |
219 | /* Floating-point registers. */ | |
20a6ec49 | 220 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 221 | } |
c6f4c129 | 222 | else if (reg >= 21 && reg <= 36) |
85540d8c | 223 | { |
c4fc7f1b | 224 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 225 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
226 | } |
227 | ||
c6f4c129 JB |
228 | switch (reg) |
229 | { | |
20a6ec49 MD |
230 | case 37: return I387_FCTRL_REGNUM (tdep); |
231 | case 38: return I387_FSTAT_REGNUM (tdep); | |
232 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
233 | case 40: return I386_ES_REGNUM; |
234 | case 41: return I386_CS_REGNUM; | |
235 | case 42: return I386_SS_REGNUM; | |
236 | case 43: return I386_DS_REGNUM; | |
237 | case 44: return I386_FS_REGNUM; | |
238 | case 45: return I386_GS_REGNUM; | |
239 | } | |
240 | ||
85540d8c | 241 | /* This will hopefully provoke a warning. */ |
d3f73121 | 242 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c | 243 | } |
5716833c | 244 | |
fc338970 | 245 | \f |
917317f4 | 246 | |
fc338970 MK |
247 | /* This is the variable that is set with "set disassembly-flavor", and |
248 | its legitimate values. */ | |
53904c9e AC |
249 | static const char att_flavor[] = "att"; |
250 | static const char intel_flavor[] = "intel"; | |
251 | static const char *valid_flavors[] = | |
c5aa993b | 252 | { |
c906108c SS |
253 | att_flavor, |
254 | intel_flavor, | |
255 | NULL | |
256 | }; | |
53904c9e | 257 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 258 | \f |
c906108c | 259 | |
acd5c798 MK |
260 | /* Use the program counter to determine the contents and size of a |
261 | breakpoint instruction. Return a pointer to a string of bytes that | |
262 | encode a breakpoint instruction, store the length of the string in | |
263 | *LEN and optionally adjust *PC to point to the correct memory | |
264 | location for inserting the breakpoint. | |
c906108c | 265 | |
acd5c798 MK |
266 | On the i386 we have a single breakpoint that fits in a single byte |
267 | and can be inserted anywhere. | |
c906108c | 268 | |
acd5c798 | 269 | This function is 64-bit safe. */ |
63c0089f MK |
270 | |
271 | static const gdb_byte * | |
67d57894 | 272 | i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
c906108c | 273 | { |
63c0089f MK |
274 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
275 | ||
acd5c798 MK |
276 | *len = sizeof (break_insn); |
277 | return break_insn; | |
c906108c | 278 | } |
237fc4c9 PA |
279 | \f |
280 | /* Displaced instruction handling. */ | |
281 | ||
1903f0e6 DE |
282 | /* Skip the legacy instruction prefixes in INSN. |
283 | Not all prefixes are valid for any particular insn | |
284 | but we needn't care, the insn will fault if it's invalid. | |
285 | The result is a pointer to the first opcode byte, | |
286 | or NULL if we run off the end of the buffer. */ | |
287 | ||
288 | static gdb_byte * | |
289 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
290 | { | |
291 | gdb_byte *end = insn + max_len; | |
292 | ||
293 | while (insn < end) | |
294 | { | |
295 | switch (*insn) | |
296 | { | |
297 | case DATA_PREFIX_OPCODE: | |
298 | case ADDR_PREFIX_OPCODE: | |
299 | case CS_PREFIX_OPCODE: | |
300 | case DS_PREFIX_OPCODE: | |
301 | case ES_PREFIX_OPCODE: | |
302 | case FS_PREFIX_OPCODE: | |
303 | case GS_PREFIX_OPCODE: | |
304 | case SS_PREFIX_OPCODE: | |
305 | case LOCK_PREFIX_OPCODE: | |
306 | case REPE_PREFIX_OPCODE: | |
307 | case REPNE_PREFIX_OPCODE: | |
308 | ++insn; | |
309 | continue; | |
310 | default: | |
311 | return insn; | |
312 | } | |
313 | } | |
314 | ||
315 | return NULL; | |
316 | } | |
237fc4c9 PA |
317 | |
318 | static int | |
1903f0e6 | 319 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 PA |
320 | { |
321 | /* jmp far (absolute address in operand) */ | |
322 | if (insn[0] == 0xea) | |
323 | return 1; | |
324 | ||
325 | if (insn[0] == 0xff) | |
326 | { | |
327 | /* jump near, absolute indirect (/4) */ | |
328 | if ((insn[1] & 0x38) == 0x20) | |
329 | return 1; | |
330 | ||
331 | /* jump far, absolute indirect (/5) */ | |
332 | if ((insn[1] & 0x38) == 0x28) | |
333 | return 1; | |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static int | |
1903f0e6 | 340 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 PA |
341 | { |
342 | /* call far, absolute */ | |
343 | if (insn[0] == 0x9a) | |
344 | return 1; | |
345 | ||
346 | if (insn[0] == 0xff) | |
347 | { | |
348 | /* Call near, absolute indirect (/2) */ | |
349 | if ((insn[1] & 0x38) == 0x10) | |
350 | return 1; | |
351 | ||
352 | /* Call far, absolute indirect (/3) */ | |
353 | if ((insn[1] & 0x38) == 0x18) | |
354 | return 1; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static int | |
1903f0e6 | 361 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
362 | { |
363 | switch (insn[0]) | |
364 | { | |
365 | case 0xc2: /* ret near, pop N bytes */ | |
366 | case 0xc3: /* ret near */ | |
367 | case 0xca: /* ret far, pop N bytes */ | |
368 | case 0xcb: /* ret far */ | |
369 | case 0xcf: /* iret */ | |
370 | return 1; | |
371 | ||
372 | default: | |
373 | return 0; | |
374 | } | |
375 | } | |
376 | ||
377 | static int | |
1903f0e6 | 378 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
379 | { |
380 | if (i386_absolute_call_p (insn)) | |
381 | return 1; | |
382 | ||
383 | /* call near, relative */ | |
384 | if (insn[0] == 0xe8) | |
385 | return 1; | |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
237fc4c9 PA |
390 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
391 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 392 | |
237fc4c9 | 393 | static int |
1903f0e6 | 394 | i386_syscall_p (const gdb_byte *insn, ULONGEST *lengthp) |
237fc4c9 PA |
395 | { |
396 | if (insn[0] == 0xcd) | |
397 | { | |
398 | *lengthp = 2; | |
399 | return 1; | |
400 | } | |
401 | ||
402 | return 0; | |
403 | } | |
404 | ||
405 | /* Fix up the state of registers and memory after having single-stepped | |
406 | a displaced instruction. */ | |
1903f0e6 | 407 | |
237fc4c9 PA |
408 | void |
409 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
410 | struct displaced_step_closure *closure, | |
411 | CORE_ADDR from, CORE_ADDR to, | |
412 | struct regcache *regs) | |
413 | { | |
414 | /* The offset we applied to the instruction's address. | |
415 | This could well be negative (when viewed as a signed 32-bit | |
416 | value), but ULONGEST won't reflect that, so take care when | |
417 | applying it. */ | |
418 | ULONGEST insn_offset = to - from; | |
419 | ||
420 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
421 | copy of the instruction. */ | |
422 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
423 | /* The start of the insn, needed in case we see some prefixes. */ |
424 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
425 | |
426 | if (debug_displaced) | |
427 | fprintf_unfiltered (gdb_stdlog, | |
428 | "displaced: fixup (0x%s, 0x%s), " | |
429 | "insn = 0x%02x 0x%02x ...\n", | |
430 | paddr_nz (from), paddr_nz (to), insn[0], insn[1]); | |
431 | ||
432 | /* The list of issues to contend with here is taken from | |
433 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
434 | Yay for Free Software! */ | |
435 | ||
436 | /* Relocate the %eip, if necessary. */ | |
437 | ||
1903f0e6 DE |
438 | /* The instruction recognizers we use assume any leading prefixes |
439 | have been skipped. */ | |
440 | { | |
441 | /* This is the size of the buffer in closure. */ | |
442 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
443 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
444 | /* If there are too many prefixes, just ignore the insn. | |
445 | It will fault when run. */ | |
446 | if (opcode != NULL) | |
447 | insn = opcode; | |
448 | } | |
449 | ||
237fc4c9 PA |
450 | /* Except in the case of absolute or indirect jump or call |
451 | instructions, or a return instruction, the new eip is relative to | |
452 | the displaced instruction; make it relative. Well, signal | |
453 | handler returns don't need relocation either, but we use the | |
454 | value of %eip to recognize those; see below. */ | |
455 | if (! i386_absolute_jmp_p (insn) | |
456 | && ! i386_absolute_call_p (insn) | |
457 | && ! i386_ret_p (insn)) | |
458 | { | |
459 | ULONGEST orig_eip; | |
460 | ULONGEST insn_len; | |
461 | ||
462 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
463 | ||
464 | /* A signal trampoline system call changes the %eip, resuming | |
465 | execution of the main program after the signal handler has | |
466 | returned. That makes them like 'return' instructions; we | |
467 | shouldn't relocate %eip. | |
468 | ||
469 | But most system calls don't, and we do need to relocate %eip. | |
470 | ||
471 | Our heuristic for distinguishing these cases: if stepping | |
472 | over the system call instruction left control directly after | |
473 | the instruction, the we relocate --- control almost certainly | |
474 | doesn't belong in the displaced copy. Otherwise, we assume | |
475 | the instruction has put control where it belongs, and leave | |
476 | it unrelocated. Goodness help us if there are PC-relative | |
477 | system calls. */ | |
478 | if (i386_syscall_p (insn, &insn_len) | |
1903f0e6 | 479 | && orig_eip != to + (insn - insn_start) + insn_len) |
237fc4c9 PA |
480 | { |
481 | if (debug_displaced) | |
482 | fprintf_unfiltered (gdb_stdlog, | |
483 | "displaced: syscall changed %%eip; " | |
484 | "not relocating\n"); | |
485 | } | |
486 | else | |
487 | { | |
488 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
489 | ||
1903f0e6 DE |
490 | /* If we just stepped over a breakpoint insn, we don't backup |
491 | the pc on purpose; this is to match behaviour without | |
492 | stepping. */ | |
237fc4c9 PA |
493 | |
494 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
495 | ||
496 | if (debug_displaced) | |
497 | fprintf_unfiltered (gdb_stdlog, | |
498 | "displaced: " | |
499 | "relocated %%eip from 0x%s to 0x%s\n", | |
500 | paddr_nz (orig_eip), paddr_nz (eip)); | |
501 | } | |
502 | } | |
503 | ||
504 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
505 | pushed value, and should be cleared. We'll leave this for later, | |
506 | since GDB already messes up the TF flag when stepping over a | |
507 | pushfl. */ | |
508 | ||
509 | /* If the instruction was a call, the return address now atop the | |
510 | stack is the address following the copied instruction. We need | |
511 | to make it the address following the original instruction. */ | |
512 | if (i386_call_p (insn)) | |
513 | { | |
514 | ULONGEST esp; | |
515 | ULONGEST retaddr; | |
516 | const ULONGEST retaddr_len = 4; | |
517 | ||
518 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
519 | retaddr = read_memory_unsigned_integer (esp, retaddr_len); | |
520 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; | |
521 | write_memory_unsigned_integer (esp, retaddr_len, retaddr); | |
522 | ||
523 | if (debug_displaced) | |
524 | fprintf_unfiltered (gdb_stdlog, | |
525 | "displaced: relocated return addr at 0x%s " | |
526 | "to 0x%s\n", | |
527 | paddr_nz (esp), | |
528 | paddr_nz (retaddr)); | |
529 | } | |
530 | } | |
fc338970 | 531 | \f |
acd5c798 MK |
532 | #ifdef I386_REGNO_TO_SYMMETRY |
533 | #error "The Sequent Symmetry is no longer supported." | |
534 | #endif | |
c906108c | 535 | |
acd5c798 MK |
536 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
537 | and %esp "belong" to the calling function. Therefore these | |
538 | registers should be saved if they're going to be modified. */ | |
c906108c | 539 | |
acd5c798 MK |
540 | /* The maximum number of saved registers. This should include all |
541 | registers mentioned above, and %eip. */ | |
a3386186 | 542 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
543 | |
544 | struct i386_frame_cache | |
c906108c | 545 | { |
acd5c798 MK |
546 | /* Base address. */ |
547 | CORE_ADDR base; | |
772562f8 | 548 | LONGEST sp_offset; |
acd5c798 MK |
549 | CORE_ADDR pc; |
550 | ||
fd13a04a AC |
551 | /* Saved registers. */ |
552 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 553 | CORE_ADDR saved_sp; |
e0c62198 | 554 | int saved_sp_reg; |
acd5c798 MK |
555 | int pc_in_eax; |
556 | ||
557 | /* Stack space reserved for local variables. */ | |
558 | long locals; | |
559 | }; | |
560 | ||
561 | /* Allocate and initialize a frame cache. */ | |
562 | ||
563 | static struct i386_frame_cache * | |
fd13a04a | 564 | i386_alloc_frame_cache (void) |
acd5c798 MK |
565 | { |
566 | struct i386_frame_cache *cache; | |
567 | int i; | |
568 | ||
569 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
570 | ||
571 | /* Base address. */ | |
572 | cache->base = 0; | |
573 | cache->sp_offset = -4; | |
574 | cache->pc = 0; | |
575 | ||
fd13a04a AC |
576 | /* Saved registers. We initialize these to -1 since zero is a valid |
577 | offset (that's where %ebp is supposed to be stored). */ | |
578 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
579 | cache->saved_regs[i] = -1; | |
acd5c798 | 580 | cache->saved_sp = 0; |
e0c62198 | 581 | cache->saved_sp_reg = -1; |
acd5c798 MK |
582 | cache->pc_in_eax = 0; |
583 | ||
584 | /* Frameless until proven otherwise. */ | |
585 | cache->locals = -1; | |
586 | ||
587 | return cache; | |
588 | } | |
c906108c | 589 | |
acd5c798 MK |
590 | /* If the instruction at PC is a jump, return the address of its |
591 | target. Otherwise, return PC. */ | |
c906108c | 592 | |
acd5c798 MK |
593 | static CORE_ADDR |
594 | i386_follow_jump (CORE_ADDR pc) | |
595 | { | |
63c0089f | 596 | gdb_byte op; |
acd5c798 MK |
597 | long delta = 0; |
598 | int data16 = 0; | |
c906108c | 599 | |
8defab1a | 600 | target_read_memory (pc, &op, 1); |
acd5c798 | 601 | if (op == 0x66) |
c906108c | 602 | { |
c906108c | 603 | data16 = 1; |
acd5c798 | 604 | op = read_memory_unsigned_integer (pc + 1, 1); |
c906108c SS |
605 | } |
606 | ||
acd5c798 | 607 | switch (op) |
c906108c SS |
608 | { |
609 | case 0xe9: | |
fc338970 | 610 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
611 | if (data16) |
612 | { | |
acd5c798 | 613 | delta = read_memory_integer (pc + 2, 2); |
c906108c | 614 | |
fc338970 MK |
615 | /* Include the size of the jmp instruction (including the |
616 | 0x66 prefix). */ | |
acd5c798 | 617 | delta += 4; |
c906108c SS |
618 | } |
619 | else | |
620 | { | |
acd5c798 | 621 | delta = read_memory_integer (pc + 1, 4); |
c906108c | 622 | |
acd5c798 MK |
623 | /* Include the size of the jmp instruction. */ |
624 | delta += 5; | |
c906108c SS |
625 | } |
626 | break; | |
627 | case 0xeb: | |
fc338970 | 628 | /* Relative jump, disp8 (ignore data16). */ |
acd5c798 | 629 | delta = read_memory_integer (pc + data16 + 1, 1); |
c906108c | 630 | |
acd5c798 | 631 | delta += data16 + 2; |
c906108c SS |
632 | break; |
633 | } | |
c906108c | 634 | |
acd5c798 MK |
635 | return pc + delta; |
636 | } | |
fc338970 | 637 | |
acd5c798 MK |
638 | /* Check whether PC points at a prologue for a function returning a |
639 | structure or union. If so, it updates CACHE and returns the | |
640 | address of the first instruction after the code sequence that | |
641 | removes the "hidden" argument from the stack or CURRENT_PC, | |
642 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 643 | |
acd5c798 MK |
644 | static CORE_ADDR |
645 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
646 | struct i386_frame_cache *cache) | |
c906108c | 647 | { |
acd5c798 MK |
648 | /* Functions that return a structure or union start with: |
649 | ||
650 | popl %eax 0x58 | |
651 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
652 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
653 | ||
654 | (the System V compiler puts out the second `xchg' instruction, | |
655 | and the assembler doesn't try to optimize it, so the 'sib' form | |
656 | gets generated). This sequence is used to get the address of the | |
657 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
658 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
659 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
660 | gdb_byte buf[4]; | |
661 | gdb_byte op; | |
c906108c | 662 | |
acd5c798 MK |
663 | if (current_pc <= pc) |
664 | return pc; | |
665 | ||
8defab1a | 666 | target_read_memory (pc, &op, 1); |
c906108c | 667 | |
acd5c798 MK |
668 | if (op != 0x58) /* popl %eax */ |
669 | return pc; | |
c906108c | 670 | |
8defab1a | 671 | target_read_memory (pc + 1, buf, 4); |
acd5c798 MK |
672 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
673 | return pc; | |
c906108c | 674 | |
acd5c798 | 675 | if (current_pc == pc) |
c906108c | 676 | { |
acd5c798 MK |
677 | cache->sp_offset += 4; |
678 | return current_pc; | |
c906108c SS |
679 | } |
680 | ||
acd5c798 | 681 | if (current_pc == pc + 1) |
c906108c | 682 | { |
acd5c798 MK |
683 | cache->pc_in_eax = 1; |
684 | return current_pc; | |
685 | } | |
686 | ||
687 | if (buf[1] == proto1[1]) | |
688 | return pc + 4; | |
689 | else | |
690 | return pc + 5; | |
691 | } | |
692 | ||
693 | static CORE_ADDR | |
694 | i386_skip_probe (CORE_ADDR pc) | |
695 | { | |
696 | /* A function may start with | |
fc338970 | 697 | |
acd5c798 MK |
698 | pushl constant |
699 | call _probe | |
700 | addl $4, %esp | |
fc338970 | 701 | |
acd5c798 MK |
702 | followed by |
703 | ||
704 | pushl %ebp | |
fc338970 | 705 | |
acd5c798 | 706 | etc. */ |
63c0089f MK |
707 | gdb_byte buf[8]; |
708 | gdb_byte op; | |
fc338970 | 709 | |
8defab1a | 710 | target_read_memory (pc, &op, 1); |
acd5c798 MK |
711 | |
712 | if (op == 0x68 || op == 0x6a) | |
713 | { | |
714 | int delta; | |
c906108c | 715 | |
acd5c798 MK |
716 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
717 | four-byte operand, depending on the opcode. */ | |
c906108c | 718 | if (op == 0x68) |
acd5c798 | 719 | delta = 5; |
c906108c | 720 | else |
acd5c798 | 721 | delta = 2; |
c906108c | 722 | |
acd5c798 MK |
723 | /* Read the following 8 bytes, which should be `call _probe' (6 |
724 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
725 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 726 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 727 | pc += delta + sizeof (buf); |
c906108c SS |
728 | } |
729 | ||
acd5c798 MK |
730 | return pc; |
731 | } | |
732 | ||
92dd43fa MK |
733 | /* GCC 4.1 and later, can put code in the prologue to realign the |
734 | stack pointer. Check whether PC points to such code, and update | |
735 | CACHE accordingly. Return the first instruction after the code | |
736 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
737 | recognize the code, return PC. */ | |
738 | ||
739 | static CORE_ADDR | |
740 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
741 | struct i386_frame_cache *cache) | |
742 | { | |
e0c62198 L |
743 | /* There are 2 code sequences to re-align stack before the frame |
744 | gets set up: | |
745 | ||
746 | 1. Use a caller-saved saved register: | |
747 | ||
748 | leal 4(%esp), %reg | |
749 | andl $-XXX, %esp | |
750 | pushl -4(%reg) | |
751 | ||
752 | 2. Use a callee-saved saved register: | |
753 | ||
754 | pushl %reg | |
755 | leal 8(%esp), %reg | |
756 | andl $-XXX, %esp | |
757 | pushl -4(%reg) | |
758 | ||
759 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
760 | ||
761 | 0x83 0xe4 0xf0 andl $-16, %esp | |
762 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
763 | */ | |
764 | ||
765 | gdb_byte buf[14]; | |
766 | int reg; | |
767 | int offset, offset_and; | |
768 | static int regnums[8] = { | |
769 | I386_EAX_REGNUM, /* %eax */ | |
770 | I386_ECX_REGNUM, /* %ecx */ | |
771 | I386_EDX_REGNUM, /* %edx */ | |
772 | I386_EBX_REGNUM, /* %ebx */ | |
773 | I386_ESP_REGNUM, /* %esp */ | |
774 | I386_EBP_REGNUM, /* %ebp */ | |
775 | I386_ESI_REGNUM, /* %esi */ | |
776 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 777 | }; |
92dd43fa | 778 | |
e0c62198 L |
779 | if (target_read_memory (pc, buf, sizeof buf)) |
780 | return pc; | |
781 | ||
782 | /* Check caller-saved saved register. The first instruction has | |
783 | to be "leal 4(%esp), %reg". */ | |
784 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
785 | { | |
786 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
787 | if ((buf[1] & 0xc7) != 0x44) | |
788 | return pc; | |
789 | ||
790 | /* REG has register number. */ | |
791 | reg = (buf[1] >> 3) & 7; | |
792 | offset = 4; | |
793 | } | |
794 | else | |
795 | { | |
796 | /* Check callee-saved saved register. The first instruction | |
797 | has to be "pushl %reg". */ | |
798 | if ((buf[0] & 0xf8) != 0x50) | |
799 | return pc; | |
800 | ||
801 | /* Get register. */ | |
802 | reg = buf[0] & 0x7; | |
803 | ||
804 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
805 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
806 | return pc; | |
807 | ||
808 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
809 | if ((buf[2] & 0xc7) != 0x44) | |
810 | return pc; | |
811 | ||
812 | /* REG has register number. Registers in pushl and leal have to | |
813 | be the same. */ | |
814 | if (reg != ((buf[2] >> 3) & 7)) | |
815 | return pc; | |
816 | ||
817 | offset = 5; | |
818 | } | |
819 | ||
820 | /* Rigister can't be %esp nor %ebp. */ | |
821 | if (reg == 4 || reg == 5) | |
822 | return pc; | |
823 | ||
824 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
825 | if (buf[offset + 1] != 0xe4 | |
826 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
827 | return pc; | |
828 | ||
829 | offset_and = offset; | |
830 | offset += buf[offset] == 0x81 ? 6 : 3; | |
831 | ||
832 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
833 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
834 | if (buf[offset] != 0xff | |
835 | || buf[offset + 2] != 0xfc | |
836 | || (buf[offset + 1] & 0xf8) != 0x70) | |
837 | return pc; | |
838 | ||
839 | /* R/M has register. Registers in leal and pushl have to be the | |
840 | same. */ | |
841 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
842 | return pc; |
843 | ||
e0c62198 L |
844 | if (current_pc > pc + offset_and) |
845 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 846 | |
e0c62198 | 847 | return min (pc + offset + 3, current_pc); |
92dd43fa MK |
848 | } |
849 | ||
37bdc87e | 850 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 851 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
852 | |
853 | /* Instruction description. */ | |
854 | struct i386_insn | |
855 | { | |
856 | size_t len; | |
237fc4c9 PA |
857 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
858 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
859 | }; |
860 | ||
861 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
862 | the first instruction description that matches. Otherwise, return | |
863 | NULL. */ | |
864 | ||
865 | static struct i386_insn * | |
866 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
867 | { | |
868 | struct i386_insn *insn; | |
63c0089f | 869 | gdb_byte op; |
37bdc87e | 870 | |
8defab1a | 871 | target_read_memory (pc, &op, 1); |
37bdc87e MK |
872 | |
873 | for (insn = skip_insns; insn->len > 0; insn++) | |
874 | { | |
875 | if ((op & insn->mask[0]) == insn->insn[0]) | |
876 | { | |
237fc4c9 | 877 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
613e8135 | 878 | int insn_matched = 1; |
37bdc87e MK |
879 | size_t i; |
880 | ||
881 | gdb_assert (insn->len > 1); | |
237fc4c9 | 882 | gdb_assert (insn->len <= I386_MAX_MATCHED_INSN_LEN); |
37bdc87e | 883 | |
8defab1a | 884 | target_read_memory (pc + 1, buf, insn->len - 1); |
37bdc87e MK |
885 | for (i = 1; i < insn->len; i++) |
886 | { | |
887 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 888 | insn_matched = 0; |
37bdc87e | 889 | } |
613e8135 MK |
890 | |
891 | if (insn_matched) | |
892 | return insn; | |
37bdc87e MK |
893 | } |
894 | } | |
895 | ||
896 | return NULL; | |
897 | } | |
898 | ||
899 | /* Some special instructions that might be migrated by GCC into the | |
900 | part of the prologue that sets up the new stack frame. Because the | |
901 | stack frame hasn't been setup yet, no registers have been saved | |
902 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
903 | touched. */ | |
904 | ||
905 | struct i386_insn i386_frame_setup_skip_insns[] = | |
906 | { | |
907 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
908 | ||
909 | ??? Should we handle 16-bit operand-sizes here? */ | |
910 | ||
911 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
912 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
913 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
914 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
915 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
916 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
917 | { 5, { 0xb8 }, { 0xfe } }, | |
918 | /* `movl imm32, %edx' */ | |
919 | { 5, { 0xba }, { 0xff } }, | |
920 | ||
921 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
922 | encoding for `mov m32, %eax'. | |
923 | ||
924 | ??? Should we handle SIB adressing here? | |
925 | ??? Should we handle 16-bit operand-sizes here? */ | |
926 | ||
927 | /* `movl m32, %eax' */ | |
928 | { 5, { 0xa1 }, { 0xff } }, | |
929 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
930 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
931 | /* `movl m32, %edx' */ | |
932 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
933 | ||
934 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
935 | Because of the symmetry, there are actually two ways to encode | |
936 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
937 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
938 | ||
939 | /* `subl %eax, %eax' */ | |
940 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
941 | /* `subl %ecx, %ecx' */ | |
942 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
943 | /* `subl %edx, %edx' */ | |
944 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
945 | /* `xorl %eax, %eax' */ | |
946 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
947 | /* `xorl %ecx, %ecx' */ | |
948 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
949 | /* `xorl %edx, %edx' */ | |
950 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
951 | { 0 } | |
952 | }; | |
953 | ||
e11481da PM |
954 | |
955 | /* Check whether PC points to a no-op instruction. */ | |
956 | static CORE_ADDR | |
957 | i386_skip_noop (CORE_ADDR pc) | |
958 | { | |
959 | gdb_byte op; | |
960 | int check = 1; | |
961 | ||
8defab1a | 962 | target_read_memory (pc, &op, 1); |
e11481da PM |
963 | |
964 | while (check) | |
965 | { | |
966 | check = 0; | |
967 | /* Ignore `nop' instruction. */ | |
968 | if (op == 0x90) | |
969 | { | |
970 | pc += 1; | |
8defab1a | 971 | target_read_memory (pc, &op, 1); |
e11481da PM |
972 | check = 1; |
973 | } | |
974 | /* Ignore no-op instruction `mov %edi, %edi'. | |
975 | Microsoft system dlls often start with | |
976 | a `mov %edi,%edi' instruction. | |
977 | The 5 bytes before the function start are | |
978 | filled with `nop' instructions. | |
979 | This pattern can be used for hot-patching: | |
980 | The `mov %edi, %edi' instruction can be replaced by a | |
981 | near jump to the location of the 5 `nop' instructions | |
982 | which can be replaced by a 32-bit jump to anywhere | |
983 | in the 32-bit address space. */ | |
984 | ||
985 | else if (op == 0x8b) | |
986 | { | |
8defab1a | 987 | target_read_memory (pc + 1, &op, 1); |
e11481da PM |
988 | if (op == 0xff) |
989 | { | |
990 | pc += 2; | |
8defab1a | 991 | target_read_memory (pc, &op, 1); |
e11481da PM |
992 | check = 1; |
993 | } | |
994 | } | |
995 | } | |
996 | return pc; | |
997 | } | |
998 | ||
acd5c798 MK |
999 | /* Check whether PC points at a code that sets up a new stack frame. |
1000 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1001 | instruction after the sequence that sets up the frame or LIMIT, |
1002 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1003 | |
1004 | static CORE_ADDR | |
37bdc87e | 1005 | i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit, |
acd5c798 MK |
1006 | struct i386_frame_cache *cache) |
1007 | { | |
37bdc87e | 1008 | struct i386_insn *insn; |
63c0089f | 1009 | gdb_byte op; |
26604a34 | 1010 | int skip = 0; |
acd5c798 | 1011 | |
37bdc87e MK |
1012 | if (limit <= pc) |
1013 | return limit; | |
acd5c798 | 1014 | |
8defab1a | 1015 | target_read_memory (pc, &op, 1); |
acd5c798 | 1016 | |
c906108c | 1017 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1018 | { |
acd5c798 MK |
1019 | /* Take into account that we've executed the `pushl %ebp' that |
1020 | starts this instruction sequence. */ | |
fd13a04a | 1021 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1022 | cache->sp_offset += 4; |
37bdc87e | 1023 | pc++; |
acd5c798 MK |
1024 | |
1025 | /* If that's all, return now. */ | |
37bdc87e MK |
1026 | if (limit <= pc) |
1027 | return limit; | |
26604a34 | 1028 | |
b4632131 | 1029 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1030 | GCC into the prologue and skip them. At this point in the |
1031 | prologue, code should only touch the scratch registers %eax, | |
1032 | %ecx and %edx, so while the number of posibilities is sheer, | |
1033 | it is limited. | |
5daa5b4e | 1034 | |
26604a34 MK |
1035 | Make sure we only skip these instructions if we later see the |
1036 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1037 | while (pc + skip < limit) |
26604a34 | 1038 | { |
37bdc87e MK |
1039 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1040 | if (insn == NULL) | |
1041 | break; | |
b4632131 | 1042 | |
37bdc87e | 1043 | skip += insn->len; |
26604a34 MK |
1044 | } |
1045 | ||
37bdc87e MK |
1046 | /* If that's all, return now. */ |
1047 | if (limit <= pc + skip) | |
1048 | return limit; | |
1049 | ||
8defab1a | 1050 | target_read_memory (pc + skip, &op, 1); |
37bdc87e | 1051 | |
26604a34 | 1052 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 1053 | switch (op) |
c906108c SS |
1054 | { |
1055 | case 0x8b: | |
37bdc87e MK |
1056 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec) |
1057 | return pc; | |
c906108c SS |
1058 | break; |
1059 | case 0x89: | |
37bdc87e MK |
1060 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5) |
1061 | return pc; | |
c906108c SS |
1062 | break; |
1063 | default: | |
37bdc87e | 1064 | return pc; |
c906108c | 1065 | } |
acd5c798 | 1066 | |
26604a34 MK |
1067 | /* OK, we actually have a frame. We just don't know how large |
1068 | it is yet. Set its size to zero. We'll adjust it if | |
1069 | necessary. We also now commit to skipping the special | |
1070 | instructions mentioned before. */ | |
acd5c798 | 1071 | cache->locals = 0; |
37bdc87e | 1072 | pc += (skip + 2); |
acd5c798 MK |
1073 | |
1074 | /* If that's all, return now. */ | |
37bdc87e MK |
1075 | if (limit <= pc) |
1076 | return limit; | |
acd5c798 | 1077 | |
fc338970 MK |
1078 | /* Check for stack adjustment |
1079 | ||
acd5c798 | 1080 | subl $XXX, %esp |
fc338970 | 1081 | |
fd35795f | 1082 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1083 | reg, so we don't have to worry about a data16 prefix. */ |
8defab1a | 1084 | target_read_memory (pc, &op, 1); |
c906108c SS |
1085 | if (op == 0x83) |
1086 | { | |
fd35795f | 1087 | /* `subl' with 8-bit immediate. */ |
37bdc87e | 1088 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 1089 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1090 | return pc; |
acd5c798 | 1091 | |
37bdc87e MK |
1092 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1093 | make sense to be negative). */ | |
1094 | cache->locals = read_memory_integer (pc + 2, 1); | |
1095 | return pc + 3; | |
c906108c SS |
1096 | } |
1097 | else if (op == 0x81) | |
1098 | { | |
fd35795f | 1099 | /* Maybe it is `subl' with a 32-bit immediate. */ |
37bdc87e | 1100 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 1101 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1102 | return pc; |
acd5c798 | 1103 | |
fd35795f | 1104 | /* It is `subl' with a 32-bit immediate. */ |
37bdc87e MK |
1105 | cache->locals = read_memory_integer (pc + 2, 4); |
1106 | return pc + 6; | |
c906108c SS |
1107 | } |
1108 | else | |
1109 | { | |
acd5c798 | 1110 | /* Some instruction other than `subl'. */ |
37bdc87e | 1111 | return pc; |
c906108c SS |
1112 | } |
1113 | } | |
37bdc87e | 1114 | else if (op == 0xc8) /* enter */ |
c906108c | 1115 | { |
acd5c798 MK |
1116 | cache->locals = read_memory_unsigned_integer (pc + 1, 2); |
1117 | return pc + 4; | |
c906108c | 1118 | } |
21d0e8a4 | 1119 | |
acd5c798 | 1120 | return pc; |
21d0e8a4 MK |
1121 | } |
1122 | ||
acd5c798 MK |
1123 | /* Check whether PC points at code that saves registers on the stack. |
1124 | If so, it updates CACHE and returns the address of the first | |
1125 | instruction after the register saves or CURRENT_PC, whichever is | |
1126 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1127 | |
1128 | static CORE_ADDR | |
acd5c798 MK |
1129 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1130 | struct i386_frame_cache *cache) | |
6bff26de | 1131 | { |
99ab4326 | 1132 | CORE_ADDR offset = 0; |
63c0089f | 1133 | gdb_byte op; |
99ab4326 | 1134 | int i; |
c0d1d883 | 1135 | |
99ab4326 MK |
1136 | if (cache->locals > 0) |
1137 | offset -= cache->locals; | |
1138 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1139 | { | |
8defab1a | 1140 | target_read_memory (pc, &op, 1); |
99ab4326 MK |
1141 | if (op < 0x50 || op > 0x57) |
1142 | break; | |
0d17c81d | 1143 | |
99ab4326 MK |
1144 | offset -= 4; |
1145 | cache->saved_regs[op - 0x50] = offset; | |
1146 | cache->sp_offset += 4; | |
1147 | pc++; | |
6bff26de MK |
1148 | } |
1149 | ||
acd5c798 | 1150 | return pc; |
22797942 AC |
1151 | } |
1152 | ||
acd5c798 MK |
1153 | /* Do a full analysis of the prologue at PC and update CACHE |
1154 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1155 | address where the analysis stopped. | |
ed84f6c1 | 1156 | |
fc338970 MK |
1157 | We handle these cases: |
1158 | ||
1159 | The startup sequence can be at the start of the function, or the | |
1160 | function can start with a branch to startup code at the end. | |
1161 | ||
1162 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1163 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1164 | once used in the System V compiler). | |
1165 | ||
1166 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1167 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1168 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1169 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1170 | |
1171 | Next, the registers used by this function are pushed. With the | |
1172 | System V compiler they will always be in the order: %edi, %esi, | |
1173 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1174 | restore %eax); however, the code below is willing to see the pushes | |
1175 | in any order, and will handle up to 8 of them. | |
1176 | ||
1177 | If the setup sequence is at the end of the function, then the next | |
1178 | instruction will be a branch back to the start. */ | |
c906108c | 1179 | |
acd5c798 MK |
1180 | static CORE_ADDR |
1181 | i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
1182 | struct i386_frame_cache *cache) | |
c906108c | 1183 | { |
e11481da | 1184 | pc = i386_skip_noop (pc); |
acd5c798 MK |
1185 | pc = i386_follow_jump (pc); |
1186 | pc = i386_analyze_struct_return (pc, current_pc, cache); | |
1187 | pc = i386_skip_probe (pc); | |
92dd43fa | 1188 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
acd5c798 MK |
1189 | pc = i386_analyze_frame_setup (pc, current_pc, cache); |
1190 | return i386_analyze_register_saves (pc, current_pc, cache); | |
c906108c SS |
1191 | } |
1192 | ||
fc338970 | 1193 | /* Return PC of first real instruction. */ |
c906108c | 1194 | |
3a1e71e3 | 1195 | static CORE_ADDR |
6093d2eb | 1196 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1197 | { |
63c0089f | 1198 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1199 | { |
1200 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1201 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1202 | }; |
acd5c798 MK |
1203 | struct i386_frame_cache cache; |
1204 | CORE_ADDR pc; | |
63c0089f | 1205 | gdb_byte op; |
acd5c798 | 1206 | int i; |
c5aa993b | 1207 | |
acd5c798 MK |
1208 | cache.locals = -1; |
1209 | pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache); | |
1210 | if (cache.locals < 0) | |
1211 | return start_pc; | |
c5aa993b | 1212 | |
acd5c798 | 1213 | /* Found valid frame setup. */ |
c906108c | 1214 | |
fc338970 MK |
1215 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1216 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1217 | %ebx: |
1218 | ||
fc338970 MK |
1219 | call 0x0 |
1220 | popl %ebx | |
1221 | movl %ebx,x(%ebp) (optional) | |
1222 | addl y,%ebx | |
1223 | ||
c906108c SS |
1224 | This code is with the rest of the prologue (at the end of the |
1225 | function), so we have to skip it to get to the first real | |
1226 | instruction at the start of the function. */ | |
c5aa993b | 1227 | |
c906108c SS |
1228 | for (i = 0; i < 6; i++) |
1229 | { | |
8defab1a | 1230 | target_read_memory (pc + i, &op, 1); |
c5aa993b | 1231 | if (pic_pat[i] != op) |
c906108c SS |
1232 | break; |
1233 | } | |
1234 | if (i == 6) | |
1235 | { | |
acd5c798 MK |
1236 | int delta = 6; |
1237 | ||
8defab1a | 1238 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1239 | |
c5aa993b | 1240 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1241 | { |
acd5c798 MK |
1242 | op = read_memory_unsigned_integer (pc + delta + 1, 1); |
1243 | ||
fc338970 | 1244 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1245 | delta += 3; |
fc338970 | 1246 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1247 | delta += 6; |
fc338970 | 1248 | else /* Unexpected instruction. */ |
acd5c798 MK |
1249 | delta = 0; |
1250 | ||
8defab1a | 1251 | target_read_memory (pc + delta, &op, 1); |
c906108c | 1252 | } |
acd5c798 | 1253 | |
c5aa993b | 1254 | /* addl y,%ebx */ |
acd5c798 | 1255 | if (delta > 0 && op == 0x81 |
d5d6fca5 | 1256 | && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3) |
c906108c | 1257 | { |
acd5c798 | 1258 | pc += delta + 6; |
c906108c SS |
1259 | } |
1260 | } | |
c5aa993b | 1261 | |
e63bbc88 MK |
1262 | /* If the function starts with a branch (to startup code at the end) |
1263 | the last instruction should bring us back to the first | |
1264 | instruction of the real code. */ | |
1265 | if (i386_follow_jump (start_pc) != start_pc) | |
1266 | pc = i386_follow_jump (pc); | |
1267 | ||
1268 | return pc; | |
c906108c SS |
1269 | } |
1270 | ||
4309257c PM |
1271 | /* Check that the code pointed to by PC corresponds to a call to |
1272 | __main, skip it if so. Return PC otherwise. */ | |
1273 | ||
1274 | CORE_ADDR | |
1275 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1276 | { | |
1277 | gdb_byte op; | |
1278 | ||
1279 | target_read_memory (pc, &op, 1); | |
1280 | if (op == 0xe8) | |
1281 | { | |
1282 | gdb_byte buf[4]; | |
1283 | ||
1284 | if (target_read_memory (pc + 1, buf, sizeof buf) == 0) | |
1285 | { | |
1286 | /* Make sure address is computed correctly as a 32bit | |
1287 | integer even if CORE_ADDR is 64 bit wide. */ | |
1288 | struct minimal_symbol *s; | |
1289 | CORE_ADDR call_dest = pc + 5 + extract_signed_integer (buf, 4); | |
1290 | ||
1291 | call_dest = call_dest & 0xffffffffU; | |
1292 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1293 | if (s != NULL | |
1294 | && SYMBOL_LINKAGE_NAME (s) != NULL | |
1295 | && strcmp (SYMBOL_LINKAGE_NAME (s), "__main") == 0) | |
1296 | pc += 5; | |
1297 | } | |
1298 | } | |
1299 | ||
1300 | return pc; | |
1301 | } | |
1302 | ||
acd5c798 | 1303 | /* This function is 64-bit safe. */ |
93924b6b | 1304 | |
acd5c798 MK |
1305 | static CORE_ADDR |
1306 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1307 | { |
63c0089f | 1308 | gdb_byte buf[8]; |
acd5c798 | 1309 | |
875f8d0e | 1310 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1311 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1312 | } |
acd5c798 | 1313 | \f |
93924b6b | 1314 | |
acd5c798 | 1315 | /* Normal frames. */ |
c5aa993b | 1316 | |
acd5c798 | 1317 | static struct i386_frame_cache * |
10458914 | 1318 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) |
a7769679 | 1319 | { |
acd5c798 | 1320 | struct i386_frame_cache *cache; |
63c0089f | 1321 | gdb_byte buf[4]; |
acd5c798 MK |
1322 | int i; |
1323 | ||
1324 | if (*this_cache) | |
1325 | return *this_cache; | |
1326 | ||
fd13a04a | 1327 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1328 | *this_cache = cache; |
1329 | ||
1330 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1331 | which holds the base address for the current stack frame. | |
1332 | However, for functions that don't need it, the frame pointer is | |
1333 | optional. For these "frameless" functions the frame pointer is | |
1334 | actually the frame pointer of the calling frame. Signal | |
1335 | trampolines are just a special case of a "frameless" function. | |
1336 | They (usually) share their frame pointer with the frame that was | |
1337 | in progress when the signal occurred. */ | |
1338 | ||
10458914 | 1339 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
acd5c798 MK |
1340 | cache->base = extract_unsigned_integer (buf, 4); |
1341 | if (cache->base == 0) | |
1342 | return cache; | |
1343 | ||
1344 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1345 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1346 | |
10458914 | 1347 | cache->pc = get_frame_func (this_frame); |
acd5c798 | 1348 | if (cache->pc != 0) |
10458914 | 1349 | i386_analyze_prologue (cache->pc, get_frame_pc (this_frame), cache); |
acd5c798 | 1350 | |
e0c62198 | 1351 | if (cache->saved_sp_reg != -1) |
92dd43fa | 1352 | { |
e0c62198 L |
1353 | /* Saved stack pointer has been saved. */ |
1354 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
92dd43fa MK |
1355 | cache->saved_sp = extract_unsigned_integer(buf, 4); |
1356 | } | |
1357 | ||
acd5c798 MK |
1358 | if (cache->locals < 0) |
1359 | { | |
1360 | /* We didn't find a valid frame, which means that CACHE->base | |
1361 | currently holds the frame pointer for our calling frame. If | |
1362 | we're at the start of a function, or somewhere half-way its | |
1363 | prologue, the function's frame probably hasn't been fully | |
1364 | setup yet. Try to reconstruct the base address for the stack | |
1365 | frame by looking at the stack pointer. For truly "frameless" | |
1366 | functions this might work too. */ | |
1367 | ||
e0c62198 | 1368 | if (cache->saved_sp_reg != -1) |
92dd43fa MK |
1369 | { |
1370 | /* We're halfway aligning the stack. */ | |
1371 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
1372 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
1373 | ||
1374 | /* This will be added back below. */ | |
1375 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
1376 | } | |
1377 | else | |
1378 | { | |
10458914 | 1379 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
92dd43fa MK |
1380 | cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset; |
1381 | } | |
acd5c798 MK |
1382 | } |
1383 | ||
1384 | /* Now that we have the base address for the stack frame we can | |
1385 | calculate the value of %esp in the calling frame. */ | |
92dd43fa MK |
1386 | if (cache->saved_sp == 0) |
1387 | cache->saved_sp = cache->base + 8; | |
a7769679 | 1388 | |
acd5c798 MK |
1389 | /* Adjust all the saved registers such that they contain addresses |
1390 | instead of offsets. */ | |
1391 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
1392 | if (cache->saved_regs[i] != -1) |
1393 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
1394 | |
1395 | return cache; | |
a7769679 MK |
1396 | } |
1397 | ||
3a1e71e3 | 1398 | static void |
10458914 | 1399 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 1400 | struct frame_id *this_id) |
c906108c | 1401 | { |
10458914 | 1402 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1403 | |
1404 | /* This marks the outermost frame. */ | |
1405 | if (cache->base == 0) | |
1406 | return; | |
1407 | ||
3e210248 | 1408 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1409 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
1410 | } | |
1411 | ||
10458914 DJ |
1412 | static struct value * |
1413 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
1414 | int regnum) | |
acd5c798 | 1415 | { |
10458914 | 1416 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1417 | |
1418 | gdb_assert (regnum >= 0); | |
1419 | ||
1420 | /* The System V ABI says that: | |
1421 | ||
1422 | "The flags register contains the system flags, such as the | |
1423 | direction flag and the carry flag. The direction flag must be | |
1424 | set to the forward (that is, zero) direction before entry and | |
1425 | upon exit from a function. Other user flags have no specified | |
1426 | role in the standard calling sequence and are not preserved." | |
1427 | ||
1428 | To guarantee the "upon exit" part of that statement we fake a | |
1429 | saved flags register that has its direction flag cleared. | |
1430 | ||
1431 | Note that GCC doesn't seem to rely on the fact that the direction | |
1432 | flag is cleared after a function return; it always explicitly | |
1433 | clears the flag before operations where it matters. | |
1434 | ||
1435 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
1436 | right thing to do. The way we fake the flags register here makes | |
1437 | it impossible to change it. */ | |
1438 | ||
1439 | if (regnum == I386_EFLAGS_REGNUM) | |
1440 | { | |
10458914 | 1441 | ULONGEST val; |
c5aa993b | 1442 | |
10458914 DJ |
1443 | val = get_frame_register_unsigned (this_frame, regnum); |
1444 | val &= ~(1 << 10); | |
1445 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 1446 | } |
1211c4e4 | 1447 | |
acd5c798 | 1448 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 1449 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 MK |
1450 | |
1451 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
10458914 | 1452 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
acd5c798 | 1453 | |
fd13a04a | 1454 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
1455 | return frame_unwind_got_memory (this_frame, regnum, |
1456 | cache->saved_regs[regnum]); | |
fd13a04a | 1457 | |
10458914 | 1458 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
1459 | } |
1460 | ||
1461 | static const struct frame_unwind i386_frame_unwind = | |
1462 | { | |
1463 | NORMAL_FRAME, | |
1464 | i386_frame_this_id, | |
10458914 DJ |
1465 | i386_frame_prev_register, |
1466 | NULL, | |
1467 | default_frame_sniffer | |
acd5c798 | 1468 | }; |
acd5c798 MK |
1469 | \f |
1470 | ||
1471 | /* Signal trampolines. */ | |
1472 | ||
1473 | static struct i386_frame_cache * | |
10458914 | 1474 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 MK |
1475 | { |
1476 | struct i386_frame_cache *cache; | |
10458914 | 1477 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1478 | CORE_ADDR addr; |
63c0089f | 1479 | gdb_byte buf[4]; |
acd5c798 MK |
1480 | |
1481 | if (*this_cache) | |
1482 | return *this_cache; | |
1483 | ||
fd13a04a | 1484 | cache = i386_alloc_frame_cache (); |
acd5c798 | 1485 | |
10458914 | 1486 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 MK |
1487 | cache->base = extract_unsigned_integer (buf, 4) - 4; |
1488 | ||
10458914 | 1489 | addr = tdep->sigcontext_addr (this_frame); |
a3386186 MK |
1490 | if (tdep->sc_reg_offset) |
1491 | { | |
1492 | int i; | |
1493 | ||
1494 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1495 | ||
1496 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1497 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1498 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1499 | } |
1500 | else | |
1501 | { | |
fd13a04a AC |
1502 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1503 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1504 | } |
acd5c798 MK |
1505 | |
1506 | *this_cache = cache; | |
1507 | return cache; | |
1508 | } | |
1509 | ||
1510 | static void | |
10458914 | 1511 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
1512 | struct frame_id *this_id) |
1513 | { | |
1514 | struct i386_frame_cache *cache = | |
10458914 | 1515 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1516 | |
3e210248 | 1517 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1518 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); |
acd5c798 MK |
1519 | } |
1520 | ||
10458914 DJ |
1521 | static struct value * |
1522 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
1523 | void **this_cache, int regnum) | |
acd5c798 MK |
1524 | { |
1525 | /* Make sure we've initialized the cache. */ | |
10458914 | 1526 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 1527 | |
10458914 | 1528 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 1529 | } |
c0d1d883 | 1530 | |
10458914 DJ |
1531 | static int |
1532 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
1533 | struct frame_info *this_frame, | |
1534 | void **this_prologue_cache) | |
acd5c798 | 1535 | { |
10458914 | 1536 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 1537 | |
911bc6ee MK |
1538 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1539 | handler. */ | |
1540 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 1541 | return 0; |
1c3545ae | 1542 | |
911bc6ee MK |
1543 | if (tdep->sigtramp_p != NULL) |
1544 | { | |
10458914 DJ |
1545 | if (tdep->sigtramp_p (this_frame)) |
1546 | return 1; | |
911bc6ee MK |
1547 | } |
1548 | ||
1549 | if (tdep->sigtramp_start != 0) | |
1550 | { | |
10458914 | 1551 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
1552 | |
1553 | gdb_assert (tdep->sigtramp_end != 0); | |
1554 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 1555 | return 1; |
911bc6ee | 1556 | } |
acd5c798 | 1557 | |
10458914 | 1558 | return 0; |
acd5c798 | 1559 | } |
10458914 DJ |
1560 | |
1561 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
1562 | { | |
1563 | SIGTRAMP_FRAME, | |
1564 | i386_sigtramp_frame_this_id, | |
1565 | i386_sigtramp_frame_prev_register, | |
1566 | NULL, | |
1567 | i386_sigtramp_frame_sniffer | |
1568 | }; | |
acd5c798 MK |
1569 | \f |
1570 | ||
1571 | static CORE_ADDR | |
10458914 | 1572 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 1573 | { |
10458914 | 1574 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
1575 | |
1576 | return cache->base; | |
1577 | } | |
1578 | ||
1579 | static const struct frame_base i386_frame_base = | |
1580 | { | |
1581 | &i386_frame_unwind, | |
1582 | i386_frame_base_address, | |
1583 | i386_frame_base_address, | |
1584 | i386_frame_base_address | |
1585 | }; | |
1586 | ||
acd5c798 | 1587 | static struct frame_id |
10458914 | 1588 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 1589 | { |
acd5c798 MK |
1590 | CORE_ADDR fp; |
1591 | ||
10458914 | 1592 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 1593 | |
3e210248 | 1594 | /* See the end of i386_push_dummy_call. */ |
10458914 | 1595 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 1596 | } |
fc338970 | 1597 | \f |
c906108c | 1598 | |
fc338970 MK |
1599 | /* Figure out where the longjmp will land. Slurp the args out of the |
1600 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1601 | structure from which we extract the address that we will land at. |
28bcfd30 | 1602 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 1603 | success. */ |
c906108c | 1604 | |
8201327c | 1605 | static int |
60ade65d | 1606 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 1607 | { |
436675d3 | 1608 | gdb_byte buf[4]; |
c906108c | 1609 | CORE_ADDR sp, jb_addr; |
20a6ec49 MD |
1610 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1611 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; | |
c906108c | 1612 | |
8201327c MK |
1613 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1614 | longjmp will land. */ | |
1615 | if (jb_pc_offset == -1) | |
c906108c SS |
1616 | return 0; |
1617 | ||
436675d3 PA |
1618 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
1619 | sp = extract_unsigned_integer (buf, 4); | |
1620 | if (target_read_memory (sp + 4, buf, 4)) | |
c906108c SS |
1621 | return 0; |
1622 | ||
436675d3 PA |
1623 | jb_addr = extract_unsigned_integer (buf, 4); |
1624 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) | |
8201327c | 1625 | return 0; |
c906108c | 1626 | |
436675d3 | 1627 | *pc = extract_unsigned_integer (buf, 4); |
c906108c SS |
1628 | return 1; |
1629 | } | |
fc338970 | 1630 | \f |
c906108c | 1631 | |
7ccc1c74 JM |
1632 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
1633 | function argument. 16-byte vectors, _Decimal128 and structures or | |
1634 | unions containing such types must be 16-byte-aligned; other | |
1635 | arguments are 4-byte-aligned. */ | |
1636 | ||
1637 | static int | |
1638 | i386_16_byte_align_p (struct type *type) | |
1639 | { | |
1640 | type = check_typedef (type); | |
1641 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
1642 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
1643 | && TYPE_LENGTH (type) == 16) | |
1644 | return 1; | |
1645 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
1646 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
1647 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1648 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
1649 | { | |
1650 | int i; | |
1651 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
1652 | { | |
1653 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
1654 | return 1; | |
1655 | } | |
1656 | } | |
1657 | return 0; | |
1658 | } | |
1659 | ||
3a1e71e3 | 1660 | static CORE_ADDR |
7d9b040b | 1661 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1662 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1663 | struct value **args, CORE_ADDR sp, int struct_return, | |
1664 | CORE_ADDR struct_addr) | |
22f8ba57 | 1665 | { |
63c0089f | 1666 | gdb_byte buf[4]; |
acd5c798 | 1667 | int i; |
7ccc1c74 JM |
1668 | int write_pass; |
1669 | int args_space = 0; | |
acd5c798 | 1670 | |
7ccc1c74 JM |
1671 | /* Determine the total space required for arguments and struct |
1672 | return address in a first pass (allowing for 16-byte-aligned | |
1673 | arguments), then push arguments in a second pass. */ | |
1674 | ||
1675 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 1676 | { |
7ccc1c74 JM |
1677 | int args_space_used = 0; |
1678 | int have_16_byte_aligned_arg = 0; | |
1679 | ||
1680 | if (struct_return) | |
1681 | { | |
1682 | if (write_pass) | |
1683 | { | |
1684 | /* Push value address. */ | |
1685 | store_unsigned_integer (buf, 4, struct_addr); | |
1686 | write_memory (sp, buf, 4); | |
1687 | args_space_used += 4; | |
1688 | } | |
1689 | else | |
1690 | args_space += 4; | |
1691 | } | |
1692 | ||
1693 | for (i = 0; i < nargs; i++) | |
1694 | { | |
1695 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 1696 | |
7ccc1c74 JM |
1697 | if (write_pass) |
1698 | { | |
1699 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1700 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 1701 | |
7ccc1c74 JM |
1702 | write_memory (sp + args_space_used, |
1703 | value_contents_all (args[i]), len); | |
1704 | /* The System V ABI says that: | |
acd5c798 | 1705 | |
7ccc1c74 JM |
1706 | "An argument's size is increased, if necessary, to make it a |
1707 | multiple of [32-bit] words. This may require tail padding, | |
1708 | depending on the size of the argument." | |
22f8ba57 | 1709 | |
7ccc1c74 JM |
1710 | This makes sure the stack stays word-aligned. */ |
1711 | args_space_used += align_up (len, 4); | |
1712 | } | |
1713 | else | |
1714 | { | |
1715 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
1716 | { | |
1717 | args_space = align_up (args_space, 16); | |
1718 | have_16_byte_aligned_arg = 1; | |
1719 | } | |
1720 | args_space += align_up (len, 4); | |
1721 | } | |
1722 | } | |
1723 | ||
1724 | if (!write_pass) | |
1725 | { | |
1726 | if (have_16_byte_aligned_arg) | |
1727 | args_space = align_up (args_space, 16); | |
1728 | sp -= args_space; | |
1729 | } | |
22f8ba57 MK |
1730 | } |
1731 | ||
acd5c798 MK |
1732 | /* Store return address. */ |
1733 | sp -= 4; | |
6a65450a | 1734 | store_unsigned_integer (buf, 4, bp_addr); |
acd5c798 MK |
1735 | write_memory (sp, buf, 4); |
1736 | ||
1737 | /* Finally, update the stack pointer... */ | |
1738 | store_unsigned_integer (buf, 4, sp); | |
1739 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); | |
1740 | ||
1741 | /* ...and fake a frame pointer. */ | |
1742 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1743 | ||
3e210248 AC |
1744 | /* MarkK wrote: This "+ 8" is all over the place: |
1745 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 1746 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 1747 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
1748 | definition of the stack address of a frame. Otherwise frame id |
1749 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
1750 | stack address *before* the function call as a frame's CFA. On |
1751 | the i386, when %ebp is used as a frame pointer, the offset | |
1752 | between the contents %ebp and the CFA as defined by GCC. */ | |
1753 | return sp + 8; | |
22f8ba57 MK |
1754 | } |
1755 | ||
1a309862 MK |
1756 | /* These registers are used for returning integers (and on some |
1757 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1758 | size and alignment match an integer type). */ |
acd5c798 MK |
1759 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1760 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1761 | |
c5e656c1 MK |
1762 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1763 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1764 | |
3a1e71e3 | 1765 | static void |
c5e656c1 | 1766 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1767 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1768 | { |
c5e656c1 | 1769 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1770 | int len = TYPE_LENGTH (type); |
63c0089f | 1771 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1772 | |
1e8d0a7b | 1773 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1774 | { |
5716833c | 1775 | if (tdep->st0_regnum < 0) |
1a309862 | 1776 | { |
8a3fe4f8 | 1777 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1778 | memset (valbuf, 0, len); |
ef9dff19 | 1779 | return; |
1a309862 MK |
1780 | } |
1781 | ||
c6ba6f0d MK |
1782 | /* Floating-point return values can be found in %st(0). Convert |
1783 | its contents to the desired type. This is probably not | |
1784 | exactly how it would happen on the target itself, but it is | |
1785 | the best we can do. */ | |
acd5c798 | 1786 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
00f8375e | 1787 | convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type); |
c906108c SS |
1788 | } |
1789 | else | |
c5aa993b | 1790 | { |
875f8d0e UW |
1791 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1792 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1793 | |
1794 | if (len <= low_size) | |
00f8375e | 1795 | { |
0818c12a | 1796 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1797 | memcpy (valbuf, buf, len); |
1798 | } | |
d4f3574e SS |
1799 | else if (len <= (low_size + high_size)) |
1800 | { | |
0818c12a | 1801 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1802 | memcpy (valbuf, buf, low_size); |
0818c12a | 1803 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1804 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1805 | } |
1806 | else | |
8e65ff28 | 1807 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1808 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1809 | } |
1810 | } | |
1811 | ||
c5e656c1 MK |
1812 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1813 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1814 | |
3a1e71e3 | 1815 | static void |
c5e656c1 | 1816 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1817 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1818 | { |
c5e656c1 | 1819 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1820 | int len = TYPE_LENGTH (type); |
1821 | ||
1e8d0a7b | 1822 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1823 | { |
3d7f4f49 | 1824 | ULONGEST fstat; |
63c0089f | 1825 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1826 | |
5716833c | 1827 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1828 | { |
8a3fe4f8 | 1829 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1830 | return; |
1831 | } | |
1832 | ||
635b0cc1 MK |
1833 | /* Returning floating-point values is a bit tricky. Apart from |
1834 | storing the return value in %st(0), we have to simulate the | |
1835 | state of the FPU at function return point. */ | |
1836 | ||
c6ba6f0d MK |
1837 | /* Convert the value found in VALBUF to the extended |
1838 | floating-point format used by the FPU. This is probably | |
1839 | not exactly how it would happen on the target itself, but | |
1840 | it is the best we can do. */ | |
1841 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
acd5c798 | 1842 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1843 | |
635b0cc1 MK |
1844 | /* Set the top of the floating-point register stack to 7. The |
1845 | actual value doesn't really matter, but 7 is what a normal | |
1846 | function return would end up with if the program started out | |
1847 | with a freshly initialized FPU. */ | |
20a6ec49 | 1848 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 1849 | fstat |= (7 << 11); |
20a6ec49 | 1850 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 1851 | |
635b0cc1 MK |
1852 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1853 | the floating-point register stack to 7, the appropriate value | |
1854 | for the tag word is 0x3fff. */ | |
20a6ec49 | 1855 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
1856 | } |
1857 | else | |
1858 | { | |
875f8d0e UW |
1859 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
1860 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1861 | |
1862 | if (len <= low_size) | |
3d7f4f49 | 1863 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1864 | else if (len <= (low_size + high_size)) |
1865 | { | |
3d7f4f49 MK |
1866 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1867 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1868 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1869 | } |
1870 | else | |
8e65ff28 | 1871 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1872 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
1873 | } |
1874 | } | |
fc338970 | 1875 | \f |
ef9dff19 | 1876 | |
8201327c MK |
1877 | /* This is the variable that is set with "set struct-convention", and |
1878 | its legitimate values. */ | |
1879 | static const char default_struct_convention[] = "default"; | |
1880 | static const char pcc_struct_convention[] = "pcc"; | |
1881 | static const char reg_struct_convention[] = "reg"; | |
1882 | static const char *valid_conventions[] = | |
1883 | { | |
1884 | default_struct_convention, | |
1885 | pcc_struct_convention, | |
1886 | reg_struct_convention, | |
1887 | NULL | |
1888 | }; | |
1889 | static const char *struct_convention = default_struct_convention; | |
1890 | ||
0e4377e1 JB |
1891 | /* Return non-zero if TYPE, which is assumed to be a structure, |
1892 | a union type, or an array type, should be returned in registers | |
1893 | for architecture GDBARCH. */ | |
c5e656c1 | 1894 | |
8201327c | 1895 | static int |
c5e656c1 | 1896 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 1897 | { |
c5e656c1 MK |
1898 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1899 | enum type_code code = TYPE_CODE (type); | |
1900 | int len = TYPE_LENGTH (type); | |
8201327c | 1901 | |
0e4377e1 JB |
1902 | gdb_assert (code == TYPE_CODE_STRUCT |
1903 | || code == TYPE_CODE_UNION | |
1904 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
1905 | |
1906 | if (struct_convention == pcc_struct_convention | |
1907 | || (struct_convention == default_struct_convention | |
1908 | && tdep->struct_return == pcc_struct_return)) | |
1909 | return 0; | |
1910 | ||
9edde48e MK |
1911 | /* Structures consisting of a single `float', `double' or 'long |
1912 | double' member are returned in %st(0). */ | |
1913 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
1914 | { | |
1915 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1916 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1917 | return (len == 4 || len == 8 || len == 12); | |
1918 | } | |
1919 | ||
c5e656c1 MK |
1920 | return (len == 1 || len == 2 || len == 4 || len == 8); |
1921 | } | |
1922 | ||
1923 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
1924 | should be returned. If it is supposed to be returned in registers, | |
1925 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
1926 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
1927 | from WRITEBUF into REGCACHE. */ | |
1928 | ||
1929 | static enum return_value_convention | |
c055b101 CV |
1930 | i386_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1931 | struct type *type, struct regcache *regcache, | |
1932 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
1933 | { |
1934 | enum type_code code = TYPE_CODE (type); | |
1935 | ||
5daa78cc TJB |
1936 | if (((code == TYPE_CODE_STRUCT |
1937 | || code == TYPE_CODE_UNION | |
1938 | || code == TYPE_CODE_ARRAY) | |
1939 | && !i386_reg_struct_return_p (gdbarch, type)) | |
1940 | /* 128-bit decimal float uses the struct return convention. */ | |
1941 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
1942 | { |
1943 | /* The System V ABI says that: | |
1944 | ||
1945 | "A function that returns a structure or union also sets %eax | |
1946 | to the value of the original address of the caller's area | |
1947 | before it returns. Thus when the caller receives control | |
1948 | again, the address of the returned object resides in register | |
1949 | %eax and can be used to access the object." | |
1950 | ||
1951 | So the ABI guarantees that we can always find the return | |
1952 | value just after the function has returned. */ | |
1953 | ||
0e4377e1 JB |
1954 | /* Note that the ABI doesn't mention functions returning arrays, |
1955 | which is something possible in certain languages such as Ada. | |
1956 | In this case, the value is returned as if it was wrapped in | |
1957 | a record, so the convention applied to records also applies | |
1958 | to arrays. */ | |
1959 | ||
31db7b6c MK |
1960 | if (readbuf) |
1961 | { | |
1962 | ULONGEST addr; | |
1963 | ||
1964 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
1965 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1966 | } | |
1967 | ||
1968 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
1969 | } | |
c5e656c1 MK |
1970 | |
1971 | /* This special case is for structures consisting of a single | |
9edde48e MK |
1972 | `float', `double' or 'long double' member. These structures are |
1973 | returned in %st(0). For these structures, we call ourselves | |
1974 | recursively, changing TYPE into the type of the first member of | |
1975 | the structure. Since that should work for all structures that | |
1976 | have only one member, we don't bother to check the member's type | |
1977 | here. */ | |
c5e656c1 MK |
1978 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
1979 | { | |
1980 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
c055b101 CV |
1981 | return i386_return_value (gdbarch, func_type, type, regcache, |
1982 | readbuf, writebuf); | |
c5e656c1 MK |
1983 | } |
1984 | ||
1985 | if (readbuf) | |
1986 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
1987 | if (writebuf) | |
1988 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 1989 | |
c5e656c1 | 1990 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
1991 | } |
1992 | \f | |
1993 | ||
5ae96ec1 MK |
1994 | /* Type for %eflags. */ |
1995 | struct type *i386_eflags_type; | |
1996 | ||
794ac428 | 1997 | /* Type for %mxcsr. */ |
878d9193 | 1998 | struct type *i386_mxcsr_type; |
5ae96ec1 MK |
1999 | |
2000 | /* Construct types for ISA-specific registers. */ | |
2001 | static void | |
2002 | i386_init_types (void) | |
2003 | { | |
2004 | struct type *type; | |
2005 | ||
2006 | type = init_flags_type ("builtin_type_i386_eflags", 4); | |
2007 | append_flags_type_flag (type, 0, "CF"); | |
2008 | append_flags_type_flag (type, 1, NULL); | |
2009 | append_flags_type_flag (type, 2, "PF"); | |
2010 | append_flags_type_flag (type, 4, "AF"); | |
2011 | append_flags_type_flag (type, 6, "ZF"); | |
2012 | append_flags_type_flag (type, 7, "SF"); | |
2013 | append_flags_type_flag (type, 8, "TF"); | |
2014 | append_flags_type_flag (type, 9, "IF"); | |
2015 | append_flags_type_flag (type, 10, "DF"); | |
2016 | append_flags_type_flag (type, 11, "OF"); | |
2017 | append_flags_type_flag (type, 14, "NT"); | |
2018 | append_flags_type_flag (type, 16, "RF"); | |
2019 | append_flags_type_flag (type, 17, "VM"); | |
2020 | append_flags_type_flag (type, 18, "AC"); | |
2021 | append_flags_type_flag (type, 19, "VIF"); | |
2022 | append_flags_type_flag (type, 20, "VIP"); | |
2023 | append_flags_type_flag (type, 21, "ID"); | |
2024 | i386_eflags_type = type; | |
21b4b2f2 | 2025 | |
878d9193 MK |
2026 | type = init_flags_type ("builtin_type_i386_mxcsr", 4); |
2027 | append_flags_type_flag (type, 0, "IE"); | |
2028 | append_flags_type_flag (type, 1, "DE"); | |
2029 | append_flags_type_flag (type, 2, "ZE"); | |
2030 | append_flags_type_flag (type, 3, "OE"); | |
2031 | append_flags_type_flag (type, 4, "UE"); | |
2032 | append_flags_type_flag (type, 5, "PE"); | |
2033 | append_flags_type_flag (type, 6, "DAZ"); | |
2034 | append_flags_type_flag (type, 7, "IM"); | |
2035 | append_flags_type_flag (type, 8, "DM"); | |
2036 | append_flags_type_flag (type, 9, "ZM"); | |
2037 | append_flags_type_flag (type, 10, "OM"); | |
2038 | append_flags_type_flag (type, 11, "UM"); | |
2039 | append_flags_type_flag (type, 12, "PM"); | |
2040 | append_flags_type_flag (type, 15, "FZ"); | |
2041 | i386_mxcsr_type = type; | |
21b4b2f2 JB |
2042 | } |
2043 | ||
794ac428 UW |
2044 | /* Construct vector type for MMX registers. */ |
2045 | struct type * | |
2046 | i386_mmx_type (struct gdbarch *gdbarch) | |
2047 | { | |
2048 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2049 | ||
2050 | if (!tdep->i386_mmx_type) | |
2051 | { | |
2052 | /* The type we're building is this: */ | |
2053 | #if 0 | |
2054 | union __gdb_builtin_type_vec64i | |
2055 | { | |
2056 | int64_t uint64; | |
2057 | int32_t v2_int32[2]; | |
2058 | int16_t v4_int16[4]; | |
2059 | int8_t v8_int8[8]; | |
2060 | }; | |
2061 | #endif | |
2062 | ||
2063 | struct type *t; | |
2064 | ||
2065 | t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
2066 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
2067 | append_composite_type_field (t, "v2_int32", | |
2068 | init_vector_type (builtin_type_int32, 2)); | |
2069 | append_composite_type_field (t, "v4_int16", | |
2070 | init_vector_type (builtin_type_int16, 4)); | |
2071 | append_composite_type_field (t, "v8_int8", | |
2072 | init_vector_type (builtin_type_int8, 8)); | |
2073 | ||
876cecd0 | 2074 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2075 | TYPE_NAME (t) = "builtin_type_vec64i"; |
2076 | tdep->i386_mmx_type = t; | |
2077 | } | |
2078 | ||
2079 | return tdep->i386_mmx_type; | |
2080 | } | |
2081 | ||
2082 | struct type * | |
2083 | i386_sse_type (struct gdbarch *gdbarch) | |
2084 | { | |
2085 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2086 | ||
2087 | if (!tdep->i386_sse_type) | |
2088 | { | |
2089 | /* The type we're building is this: */ | |
2090 | #if 0 | |
2091 | union __gdb_builtin_type_vec128i | |
2092 | { | |
2093 | int128_t uint128; | |
2094 | int64_t v2_int64[2]; | |
2095 | int32_t v4_int32[4]; | |
2096 | int16_t v8_int16[8]; | |
2097 | int8_t v16_int8[16]; | |
2098 | double v2_double[2]; | |
2099 | float v4_float[4]; | |
2100 | }; | |
2101 | #endif | |
2102 | ||
2103 | struct type *t; | |
2104 | ||
2105 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
2106 | append_composite_type_field (t, "v4_float", | |
0dfff4cb UW |
2107 | init_vector_type (builtin_type (gdbarch) |
2108 | ->builtin_float, 4)); | |
794ac428 | 2109 | append_composite_type_field (t, "v2_double", |
0dfff4cb UW |
2110 | init_vector_type (builtin_type (gdbarch) |
2111 | ->builtin_double, 2)); | |
794ac428 UW |
2112 | append_composite_type_field (t, "v16_int8", |
2113 | init_vector_type (builtin_type_int8, 16)); | |
2114 | append_composite_type_field (t, "v8_int16", | |
2115 | init_vector_type (builtin_type_int16, 8)); | |
2116 | append_composite_type_field (t, "v4_int32", | |
2117 | init_vector_type (builtin_type_int32, 4)); | |
2118 | append_composite_type_field (t, "v2_int64", | |
2119 | init_vector_type (builtin_type_int64, 2)); | |
2120 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
2121 | ||
876cecd0 | 2122 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2123 | TYPE_NAME (t) = "builtin_type_vec128i"; |
2124 | tdep->i386_sse_type = t; | |
2125 | } | |
2126 | ||
2127 | return tdep->i386_sse_type; | |
2128 | } | |
2129 | ||
d7a0d72c MK |
2130 | /* Return the GDB type object for the "standard" data type of data in |
2131 | register REGNUM. Perhaps %esi and %edi should go here, but | |
2132 | potentially they could be used for things other than address. */ | |
2133 | ||
3a1e71e3 | 2134 | static struct type * |
4e259f09 | 2135 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 2136 | { |
ab533587 | 2137 | if (regnum == I386_EIP_REGNUM) |
0dfff4cb | 2138 | return builtin_type (gdbarch)->builtin_func_ptr; |
ab533587 | 2139 | |
5ae96ec1 MK |
2140 | if (regnum == I386_EFLAGS_REGNUM) |
2141 | return i386_eflags_type; | |
2142 | ||
ab533587 | 2143 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) |
0dfff4cb | 2144 | return builtin_type (gdbarch)->builtin_data_ptr; |
d7a0d72c | 2145 | |
20a6ec49 | 2146 | if (i386_fp_regnum_p (gdbarch, regnum)) |
c6ba6f0d | 2147 | return builtin_type_i387_ext; |
d7a0d72c | 2148 | |
878d9193 | 2149 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
794ac428 | 2150 | return i386_mmx_type (gdbarch); |
878d9193 | 2151 | |
5716833c | 2152 | if (i386_sse_regnum_p (gdbarch, regnum)) |
794ac428 | 2153 | return i386_sse_type (gdbarch); |
d7a0d72c | 2154 | |
20a6ec49 | 2155 | if (regnum == I387_MXCSR_REGNUM (gdbarch_tdep (gdbarch))) |
878d9193 MK |
2156 | return i386_mxcsr_type; |
2157 | ||
0dfff4cb | 2158 | return builtin_type (gdbarch)->builtin_int; |
d7a0d72c MK |
2159 | } |
2160 | ||
28fc6740 | 2161 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 2162 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
2163 | |
2164 | static int | |
c86c27af | 2165 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 2166 | { |
5716833c MK |
2167 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
2168 | int mmxreg, fpreg; | |
28fc6740 AC |
2169 | ULONGEST fstat; |
2170 | int tos; | |
c86c27af | 2171 | |
5716833c | 2172 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 2173 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 2174 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
2175 | fpreg = (mmxreg + tos) % 8; |
2176 | ||
20a6ec49 | 2177 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
2178 | } |
2179 | ||
2180 | static void | |
2181 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2182 | int regnum, gdb_byte *buf) |
28fc6740 | 2183 | { |
5716833c | 2184 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2185 | { |
63c0089f | 2186 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2187 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2188 | ||
28fc6740 | 2189 | /* Extract (always little endian). */ |
c86c27af | 2190 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 2191 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2192 | } |
2193 | else | |
2194 | regcache_raw_read (regcache, regnum, buf); | |
2195 | } | |
2196 | ||
2197 | static void | |
2198 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 2199 | int regnum, const gdb_byte *buf) |
28fc6740 | 2200 | { |
5716833c | 2201 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 2202 | { |
63c0089f | 2203 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
2204 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
2205 | ||
28fc6740 AC |
2206 | /* Read ... */ |
2207 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
2208 | /* ... Modify ... (always little endian). */ | |
f837910f | 2209 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
2210 | /* ... Write. */ |
2211 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
2212 | } | |
2213 | else | |
2214 | regcache_raw_write (regcache, regnum, buf); | |
2215 | } | |
ff2e87ac AC |
2216 | \f |
2217 | ||
ff2e87ac AC |
2218 | /* Return the register number of the register allocated by GCC after |
2219 | REGNUM, or -1 if there is no such register. */ | |
2220 | ||
2221 | static int | |
2222 | i386_next_regnum (int regnum) | |
2223 | { | |
2224 | /* GCC allocates the registers in the order: | |
2225 | ||
2226 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
2227 | ||
2228 | Since storing a variable in %esp doesn't make any sense we return | |
2229 | -1 for %ebp and for %esp itself. */ | |
2230 | static int next_regnum[] = | |
2231 | { | |
2232 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
2233 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
2234 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
2235 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
2236 | -1, -1, /* Slots for %esp and %ebp. */ | |
2237 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
2238 | I386_EBP_REGNUM /* Slot for %edi. */ | |
2239 | }; | |
2240 | ||
de5b9bb9 | 2241 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 2242 | return next_regnum[regnum]; |
28fc6740 | 2243 | |
ff2e87ac AC |
2244 | return -1; |
2245 | } | |
2246 | ||
2247 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
2248 | needs any special handling. */ | |
d7a0d72c | 2249 | |
3a1e71e3 | 2250 | static int |
0abe36f5 | 2251 | i386_convert_register_p (struct gdbarch *gdbarch, int regnum, struct type *type) |
d7a0d72c | 2252 | { |
de5b9bb9 MK |
2253 | int len = TYPE_LENGTH (type); |
2254 | ||
ff2e87ac AC |
2255 | /* Values may be spread across multiple registers. Most debugging |
2256 | formats aren't expressive enough to specify the locations, so | |
2257 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
2258 | have a length that is a multiple of the word size, since GCC |
2259 | doesn't seem to put any other types into registers. */ | |
2260 | if (len > 4 && len % 4 == 0) | |
2261 | { | |
2262 | int last_regnum = regnum; | |
2263 | ||
2264 | while (len > 4) | |
2265 | { | |
2266 | last_regnum = i386_next_regnum (last_regnum); | |
2267 | len -= 4; | |
2268 | } | |
2269 | ||
2270 | if (last_regnum != -1) | |
2271 | return 1; | |
2272 | } | |
ff2e87ac | 2273 | |
0abe36f5 | 2274 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
2275 | } |
2276 | ||
ff2e87ac AC |
2277 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
2278 | return its contents in TO. */ | |
ac27f131 | 2279 | |
3a1e71e3 | 2280 | static void |
ff2e87ac | 2281 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 2282 | struct type *type, gdb_byte *to) |
ac27f131 | 2283 | { |
20a6ec49 | 2284 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 2285 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2286 | |
ff2e87ac AC |
2287 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
2288 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 2289 | |
20a6ec49 | 2290 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8d7f6b4a | 2291 | { |
d532c08f MK |
2292 | i387_register_to_value (frame, regnum, type, to); |
2293 | return; | |
8d7f6b4a | 2294 | } |
ff2e87ac | 2295 | |
fd35795f | 2296 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
2297 | |
2298 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 2299 | |
de5b9bb9 MK |
2300 | while (len > 0) |
2301 | { | |
2302 | gdb_assert (regnum != -1); | |
20a6ec49 | 2303 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 2304 | |
42835c2b | 2305 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
2306 | regnum = i386_next_regnum (regnum); |
2307 | len -= 4; | |
42835c2b | 2308 | to += 4; |
de5b9bb9 | 2309 | } |
ac27f131 MK |
2310 | } |
2311 | ||
ff2e87ac AC |
2312 | /* Write the contents FROM of a value of type TYPE into register |
2313 | REGNUM in frame FRAME. */ | |
ac27f131 | 2314 | |
3a1e71e3 | 2315 | static void |
ff2e87ac | 2316 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 2317 | struct type *type, const gdb_byte *from) |
ac27f131 | 2318 | { |
de5b9bb9 | 2319 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 2320 | |
20a6ec49 | 2321 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 2322 | { |
d532c08f MK |
2323 | i387_value_to_register (frame, regnum, type, from); |
2324 | return; | |
2325 | } | |
3d261580 | 2326 | |
fd35795f | 2327 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
2328 | |
2329 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 2330 | |
de5b9bb9 MK |
2331 | while (len > 0) |
2332 | { | |
2333 | gdb_assert (regnum != -1); | |
875f8d0e | 2334 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 2335 | |
42835c2b | 2336 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
2337 | regnum = i386_next_regnum (regnum); |
2338 | len -= 4; | |
42835c2b | 2339 | from += 4; |
de5b9bb9 | 2340 | } |
ac27f131 | 2341 | } |
ff2e87ac | 2342 | \f |
7fdafb5a MK |
2343 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
2344 | in the general-purpose register set REGSET to register cache | |
2345 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 2346 | |
20187ed5 | 2347 | void |
473f17b0 MK |
2348 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
2349 | int regnum, const void *gregs, size_t len) | |
2350 | { | |
9ea75c57 | 2351 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 2352 | const gdb_byte *regs = gregs; |
473f17b0 MK |
2353 | int i; |
2354 | ||
2355 | gdb_assert (len == tdep->sizeof_gregset); | |
2356 | ||
2357 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2358 | { | |
2359 | if ((regnum == i || regnum == -1) | |
2360 | && tdep->gregset_reg_offset[i] != -1) | |
2361 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2362 | } | |
2363 | } | |
2364 | ||
7fdafb5a MK |
2365 | /* Collect register REGNUM from the register cache REGCACHE and store |
2366 | it in the buffer specified by GREGS and LEN as described by the | |
2367 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
2368 | all registers in REGSET. */ | |
2369 | ||
2370 | void | |
2371 | i386_collect_gregset (const struct regset *regset, | |
2372 | const struct regcache *regcache, | |
2373 | int regnum, void *gregs, size_t len) | |
2374 | { | |
2375 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 2376 | gdb_byte *regs = gregs; |
7fdafb5a MK |
2377 | int i; |
2378 | ||
2379 | gdb_assert (len == tdep->sizeof_gregset); | |
2380 | ||
2381 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
2382 | { | |
2383 | if ((regnum == i || regnum == -1) | |
2384 | && tdep->gregset_reg_offset[i] != -1) | |
2385 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
2390 | in the floating-point register set REGSET to register cache | |
2391 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
2392 | |
2393 | static void | |
2394 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
2395 | int regnum, const void *fpregs, size_t len) | |
2396 | { | |
9ea75c57 | 2397 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 2398 | |
66a72d25 MK |
2399 | if (len == I387_SIZEOF_FXSAVE) |
2400 | { | |
2401 | i387_supply_fxsave (regcache, regnum, fpregs); | |
2402 | return; | |
2403 | } | |
2404 | ||
473f17b0 MK |
2405 | gdb_assert (len == tdep->sizeof_fpregset); |
2406 | i387_supply_fsave (regcache, regnum, fpregs); | |
2407 | } | |
8446b36a | 2408 | |
2f305df1 MK |
2409 | /* Collect register REGNUM from the register cache REGCACHE and store |
2410 | it in the buffer specified by FPREGS and LEN as described by the | |
2411 | floating-point register set REGSET. If REGNUM is -1, do this for | |
2412 | all registers in REGSET. */ | |
7fdafb5a MK |
2413 | |
2414 | static void | |
2415 | i386_collect_fpregset (const struct regset *regset, | |
2416 | const struct regcache *regcache, | |
2417 | int regnum, void *fpregs, size_t len) | |
2418 | { | |
2419 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
2420 | ||
2421 | if (len == I387_SIZEOF_FXSAVE) | |
2422 | { | |
2423 | i387_collect_fxsave (regcache, regnum, fpregs); | |
2424 | return; | |
2425 | } | |
2426 | ||
2427 | gdb_assert (len == tdep->sizeof_fpregset); | |
2428 | i387_collect_fsave (regcache, regnum, fpregs); | |
2429 | } | |
2430 | ||
8446b36a MK |
2431 | /* Return the appropriate register set for the core section identified |
2432 | by SECT_NAME and SECT_SIZE. */ | |
2433 | ||
2434 | const struct regset * | |
2435 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
2436 | const char *sect_name, size_t sect_size) | |
2437 | { | |
2438 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2439 | ||
2440 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
2441 | { | |
2442 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
2443 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
2444 | i386_collect_gregset); | |
8446b36a MK |
2445 | return tdep->gregset; |
2446 | } | |
2447 | ||
66a72d25 MK |
2448 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
2449 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
2450 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
2451 | { |
2452 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
2453 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
2454 | i386_collect_fpregset); | |
8446b36a MK |
2455 | return tdep->fpregset; |
2456 | } | |
2457 | ||
2458 | return NULL; | |
2459 | } | |
473f17b0 | 2460 | \f |
fc338970 | 2461 | |
fc338970 | 2462 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
2463 | |
2464 | CORE_ADDR | |
1cce71eb | 2465 | i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name) |
c906108c | 2466 | { |
fc338970 | 2467 | if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */ |
c906108c | 2468 | { |
c5aa993b | 2469 | unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4); |
c906108c | 2470 | struct minimal_symbol *indsym = |
fc338970 | 2471 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 2472 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 2473 | |
c5aa993b | 2474 | if (symname) |
c906108c | 2475 | { |
c5aa993b JM |
2476 | if (strncmp (symname, "__imp_", 6) == 0 |
2477 | || strncmp (symname, "_imp_", 5) == 0) | |
c906108c SS |
2478 | return name ? 1 : read_memory_unsigned_integer (indirect, 4); |
2479 | } | |
2480 | } | |
fc338970 | 2481 | return 0; /* Not a trampoline. */ |
c906108c | 2482 | } |
fc338970 MK |
2483 | \f |
2484 | ||
10458914 DJ |
2485 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
2486 | routine. */ | |
8201327c | 2487 | |
4bd207ef | 2488 | int |
10458914 | 2489 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 2490 | { |
10458914 | 2491 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2492 | char *name; |
2493 | ||
2494 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
2495 | return (name && strcmp ("_sigtramp", name) == 0); |
2496 | } | |
2497 | \f | |
2498 | ||
fc338970 MK |
2499 | /* We have two flavours of disassembly. The machinery on this page |
2500 | deals with switching between those. */ | |
c906108c SS |
2501 | |
2502 | static int | |
a89aa300 | 2503 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 2504 | { |
5e3397bb MK |
2505 | gdb_assert (disassembly_flavor == att_flavor |
2506 | || disassembly_flavor == intel_flavor); | |
2507 | ||
2508 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
2509 | constified, cast to prevent a compiler warning. */ | |
2510 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
2511 | |
2512 | return print_insn_i386 (pc, info); | |
7a292a7a | 2513 | } |
fc338970 | 2514 | \f |
3ce1502b | 2515 | |
8201327c MK |
2516 | /* There are a few i386 architecture variants that differ only |
2517 | slightly from the generic i386 target. For now, we don't give them | |
2518 | their own source file, but include them here. As a consequence, | |
2519 | they'll always be included. */ | |
3ce1502b | 2520 | |
8201327c | 2521 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2522 | |
10458914 DJ |
2523 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
2524 | routine. */ | |
911bc6ee | 2525 | |
8201327c | 2526 | static int |
10458914 | 2527 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 2528 | { |
10458914 | 2529 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2530 | char *name; |
2531 | ||
acd5c798 MK |
2532 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2533 | currently unknown. */ | |
911bc6ee | 2534 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2535 | return (name && (strcmp ("_sigreturn", name) == 0 |
2536 | || strcmp ("_sigacthandler", name) == 0 | |
2537 | || strcmp ("sigvechandler", name) == 0)); | |
2538 | } | |
d2a7c97a | 2539 | |
10458914 DJ |
2540 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
2541 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 2542 | |
3a1e71e3 | 2543 | static CORE_ADDR |
10458914 | 2544 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 2545 | { |
63c0089f | 2546 | gdb_byte buf[4]; |
acd5c798 | 2547 | CORE_ADDR sp; |
3ce1502b | 2548 | |
10458914 | 2549 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
acd5c798 | 2550 | sp = extract_unsigned_integer (buf, 4); |
21d0e8a4 | 2551 | |
acd5c798 | 2552 | return read_memory_unsigned_integer (sp + 8, 4); |
8201327c MK |
2553 | } |
2554 | \f | |
3ce1502b | 2555 | |
8201327c | 2556 | /* Generic ELF. */ |
d2a7c97a | 2557 | |
8201327c MK |
2558 | void |
2559 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2560 | { | |
c4fc7f1b MK |
2561 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2562 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2563 | } |
3ce1502b | 2564 | |
8201327c | 2565 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2566 | |
8201327c MK |
2567 | void |
2568 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2569 | { | |
2570 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2571 | |
8201327c MK |
2572 | /* System V Release 4 uses ELF. */ |
2573 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2574 | |
dfe01d39 | 2575 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2576 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2577 | ||
911bc6ee | 2578 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2579 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2580 | tdep->sc_pc_offset = 36 + 14 * 4; |
2581 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2582 | |
8201327c | 2583 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2584 | } |
2585 | ||
8201327c | 2586 | /* DJGPP. */ |
3ce1502b | 2587 | |
3a1e71e3 | 2588 | static void |
8201327c | 2589 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2590 | { |
8201327c | 2591 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2592 | |
911bc6ee MK |
2593 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2594 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2595 | |
8201327c | 2596 | tdep->jb_pc_offset = 36; |
3ce1502b | 2597 | } |
8201327c | 2598 | \f |
2acceee2 | 2599 | |
38c968cf AC |
2600 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2601 | and "sse". */ | |
2602 | ||
2603 | static struct reggroup *i386_sse_reggroup; | |
2604 | static struct reggroup *i386_mmx_reggroup; | |
2605 | ||
2606 | static void | |
2607 | i386_init_reggroups (void) | |
2608 | { | |
2609 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2610 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2611 | } | |
2612 | ||
2613 | static void | |
2614 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2615 | { | |
2616 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2617 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2618 | reggroup_add (gdbarch, general_reggroup); | |
2619 | reggroup_add (gdbarch, float_reggroup); | |
2620 | reggroup_add (gdbarch, all_reggroup); | |
2621 | reggroup_add (gdbarch, save_reggroup); | |
2622 | reggroup_add (gdbarch, restore_reggroup); | |
2623 | reggroup_add (gdbarch, vector_reggroup); | |
2624 | reggroup_add (gdbarch, system_reggroup); | |
2625 | } | |
2626 | ||
2627 | int | |
2628 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2629 | struct reggroup *group) | |
2630 | { | |
5716833c MK |
2631 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2632 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
20a6ec49 MD |
2633 | int fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) |
2634 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
5716833c | 2635 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2636 | |
38c968cf AC |
2637 | if (group == i386_mmx_reggroup) |
2638 | return mmx_regnum_p; | |
2639 | if (group == i386_sse_reggroup) | |
2640 | return sse_regnum_p; | |
2641 | if (group == vector_reggroup) | |
2642 | return (mmx_regnum_p || sse_regnum_p); | |
2643 | if (group == float_reggroup) | |
2644 | return fp_regnum_p; | |
2645 | if (group == general_reggroup) | |
2646 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2647 | |
38c968cf AC |
2648 | return default_register_reggroup_p (gdbarch, regnum, group); |
2649 | } | |
38c968cf | 2650 | \f |
acd5c798 | 2651 | |
f837910f MK |
2652 | /* Get the ARGIth function argument for the current function. */ |
2653 | ||
42c466d7 | 2654 | static CORE_ADDR |
143985b7 AF |
2655 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2656 | struct type *type) | |
2657 | { | |
f837910f MK |
2658 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
2659 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4); | |
143985b7 AF |
2660 | } |
2661 | ||
514f746b AR |
2662 | static void |
2663 | i386_skip_permanent_breakpoint (struct regcache *regcache) | |
2664 | { | |
2665 | CORE_ADDR current_pc = regcache_read_pc (regcache); | |
2666 | ||
2667 | /* On i386, breakpoint is exactly 1 byte long, so we just | |
2668 | adjust the PC in the regcache. */ | |
2669 | current_pc += 1; | |
2670 | regcache_write_pc (regcache, current_pc); | |
2671 | } | |
2672 | ||
2673 | ||
143985b7 | 2674 | \f |
3a1e71e3 | 2675 | static struct gdbarch * |
a62cc96e AC |
2676 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
2677 | { | |
cd3c07fc | 2678 | struct gdbarch_tdep *tdep; |
a62cc96e AC |
2679 | struct gdbarch *gdbarch; |
2680 | ||
4be87837 DJ |
2681 | /* If there is already a candidate, use it. */ |
2682 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2683 | if (arches != NULL) | |
2684 | return arches->gdbarch; | |
a62cc96e AC |
2685 | |
2686 | /* Allocate space for the new architecture. */ | |
794ac428 | 2687 | tdep = XCALLOC (1, struct gdbarch_tdep); |
a62cc96e AC |
2688 | gdbarch = gdbarch_alloc (&info, tdep); |
2689 | ||
473f17b0 MK |
2690 | /* General-purpose registers. */ |
2691 | tdep->gregset = NULL; | |
2692 | tdep->gregset_reg_offset = NULL; | |
2693 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
2694 | tdep->sizeof_gregset = 0; | |
2695 | ||
2696 | /* Floating-point registers. */ | |
2697 | tdep->fpregset = NULL; | |
2698 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
2699 | ||
5716833c | 2700 | /* The default settings include the FPU registers, the MMX registers |
fd35795f | 2701 | and the SSE registers. This can be overridden for a specific ABI |
5716833c MK |
2702 | by adjusting the members `st0_regnum', `mm0_regnum' and |
2703 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
2704 | will show up in the output of "info all-registers". Ideally we | |
2705 | should try to autodetect whether they are available, such that we | |
2706 | can prevent "info all-registers" from displaying registers that | |
2707 | aren't available. | |
2708 | ||
2709 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
2710 | [the SSE registers] always (even when they don't exist) or never | |
2711 | showing them to the user (even when they do exist), I prefer the | |
2712 | former over the latter. */ | |
2713 | ||
2714 | tdep->st0_regnum = I386_ST0_REGNUM; | |
2715 | ||
2716 | /* The MMX registers are implemented as pseudo-registers. Put off | |
fd35795f | 2717 | calculating the register number for %mm0 until we know the number |
5716833c MK |
2718 | of raw registers. */ |
2719 | tdep->mm0_regnum = 0; | |
2720 | ||
2721 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
49ed40de | 2722 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
d2a7c97a | 2723 | |
8201327c MK |
2724 | tdep->jb_pc_offset = -1; |
2725 | tdep->struct_return = pcc_struct_return; | |
8201327c MK |
2726 | tdep->sigtramp_start = 0; |
2727 | tdep->sigtramp_end = 0; | |
911bc6ee | 2728 | tdep->sigtramp_p = i386_sigtramp_p; |
21d0e8a4 | 2729 | tdep->sigcontext_addr = NULL; |
a3386186 | 2730 | tdep->sc_reg_offset = NULL; |
8201327c | 2731 | tdep->sc_pc_offset = -1; |
21d0e8a4 | 2732 | tdep->sc_sp_offset = -1; |
8201327c | 2733 | |
896fb97d MK |
2734 | /* The format used for `long double' on almost all i386 targets is |
2735 | the i387 extended floating-point format. In fact, of all targets | |
2736 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
2737 | on having a `long double' that's not `long' at all. */ | |
8da61cc4 | 2738 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); |
21d0e8a4 | 2739 | |
66da5fd8 | 2740 | /* Although the i387 extended floating-point has only 80 significant |
896fb97d MK |
2741 | bits, a `long double' actually takes up 96, probably to enforce |
2742 | alignment. */ | |
2743 | set_gdbarch_long_double_bit (gdbarch, 96); | |
2744 | ||
49ed40de KB |
2745 | /* The default ABI includes general-purpose registers, |
2746 | floating-point registers, and the SSE registers. */ | |
2747 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
acd5c798 MK |
2748 | set_gdbarch_register_name (gdbarch, i386_register_name); |
2749 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
21d0e8a4 | 2750 | |
acd5c798 MK |
2751 | /* Register numbers of various important registers. */ |
2752 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
2753 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
2754 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
2755 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
356a6b3e | 2756 | |
c4fc7f1b MK |
2757 | /* NOTE: kettenis/20040418: GCC does have two possible register |
2758 | numbering schemes on the i386: dbx and SVR4. These schemes | |
2759 | differ in how they number %ebp, %esp, %eflags, and the | |
fd35795f | 2760 | floating-point registers, and are implemented by the arrays |
c4fc7f1b MK |
2761 | dbx_register_map[] and svr4_dbx_register_map in |
2762 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
2763 | gcc/config/i386.c, which it designates as the "default" register | |
2764 | map used in 64bit mode. This last register numbering scheme is | |
d4dc1a91 | 2765 | implemented in dbx64_register_map, and is used for AMD64; see |
c4fc7f1b MK |
2766 | amd64-tdep.c. |
2767 | ||
2768 | Currently, each GCC i386 target always uses the same register | |
2769 | numbering scheme across all its supported debugging formats | |
2770 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
2771 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
2772 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
2773 | respective config header in a manner independent of the requested | |
2774 | output debugging format. | |
2775 | ||
2776 | This does not match the arrangement below, which presumes that | |
2777 | the SDB and stabs numbering schemes differ from the DWARF and | |
2778 | DWARF 2 ones. The reason for this arrangement is that it is | |
2779 | likely to get the numbering scheme for the target's | |
2780 | default/native debug format right. For targets where GCC is the | |
2781 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
2782 | targets where the native toolchain uses a different numbering | |
2783 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
d4dc1a91 BF |
2784 | the defaults below will have to be overridden, like |
2785 | i386_elf_init_abi() does. */ | |
c4fc7f1b MK |
2786 | |
2787 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
2788 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2789 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2790 | ||
ba2b1c56 | 2791 | /* Use the SVR4 register numbering scheme for DWARF 2. */ |
c4fc7f1b | 2792 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); |
356a6b3e | 2793 | |
055d23b8 | 2794 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to |
356a6b3e MK |
2795 | be in use on any of the supported i386 targets. */ |
2796 | ||
61113f8b MK |
2797 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
2798 | ||
8201327c | 2799 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
96297dab | 2800 | |
a62cc96e | 2801 | /* Call dummy code. */ |
acd5c798 | 2802 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
a62cc96e | 2803 | |
ff2e87ac AC |
2804 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
2805 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
2806 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
b6197528 | 2807 | |
c5e656c1 | 2808 | set_gdbarch_return_value (gdbarch, i386_return_value); |
8201327c | 2809 | |
93924b6b MK |
2810 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
2811 | ||
2812 | /* Stack grows downward. */ | |
2813 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2814 | ||
2815 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
2816 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
237fc4c9 | 2817 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); |
42fdc8df | 2818 | |
42fdc8df | 2819 | set_gdbarch_frame_args_skip (gdbarch, 8); |
8201327c | 2820 | |
28fc6740 | 2821 | /* Wire in the MMX registers. */ |
0f751ff2 | 2822 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); |
28fc6740 AC |
2823 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
2824 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
2825 | ||
5e3397bb MK |
2826 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
2827 | ||
10458914 | 2828 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); |
acd5c798 MK |
2829 | |
2830 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
2831 | ||
38c968cf AC |
2832 | /* Add the i386 register groups. */ |
2833 | i386_add_reggroups (gdbarch); | |
2834 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
2835 | ||
143985b7 AF |
2836 | /* Helper for function argument information. */ |
2837 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
2838 | ||
6405b0a6 | 2839 | /* Hook in the DWARF CFI frame unwinder. */ |
10458914 | 2840 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 2841 | |
acd5c798 | 2842 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 2843 | |
3ce1502b | 2844 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2845 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 2846 | |
10458914 DJ |
2847 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
2848 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 2849 | |
8446b36a MK |
2850 | /* If we have a register mapping, enable the generic core file |
2851 | support, unless it has already been enabled. */ | |
2852 | if (tdep->gregset_reg_offset | |
2853 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
2854 | set_gdbarch_regset_from_core_section (gdbarch, | |
2855 | i386_regset_from_core_section); | |
2856 | ||
5716833c MK |
2857 | /* Unless support for MMX has been disabled, make %mm0 the first |
2858 | pseudo-register. */ | |
2859 | if (tdep->mm0_regnum == 0) | |
2860 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
2861 | ||
514f746b AR |
2862 | set_gdbarch_skip_permanent_breakpoint (gdbarch, |
2863 | i386_skip_permanent_breakpoint); | |
2864 | ||
a62cc96e AC |
2865 | return gdbarch; |
2866 | } | |
2867 | ||
8201327c MK |
2868 | static enum gdb_osabi |
2869 | i386_coff_osabi_sniffer (bfd *abfd) | |
2870 | { | |
762c5349 MK |
2871 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
2872 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
2873 | return GDB_OSABI_GO32; |
2874 | ||
2875 | return GDB_OSABI_UNKNOWN; | |
2876 | } | |
8201327c MK |
2877 | \f |
2878 | ||
28e9e0f0 MK |
2879 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2880 | void _initialize_i386_tdep (void); | |
2881 | ||
c906108c | 2882 | void |
fba45db2 | 2883 | _initialize_i386_tdep (void) |
c906108c | 2884 | { |
a62cc96e AC |
2885 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
2886 | ||
fc338970 | 2887 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
2888 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
2889 | &disassembly_flavor, _("\ | |
2890 | Set the disassembly flavor."), _("\ | |
2891 | Show the disassembly flavor."), _("\ | |
2892 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
2893 | NULL, | |
2894 | NULL, /* FIXME: i18n: */ | |
2895 | &setlist, &showlist); | |
8201327c MK |
2896 | |
2897 | /* Add the variable that controls the convention for returning | |
2898 | structs. */ | |
7ab04401 AC |
2899 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
2900 | &struct_convention, _("\ | |
2901 | Set the convention for returning small structs."), _("\ | |
2902 | Show the convention for returning small structs."), _("\ | |
2903 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
2904 | is \"default\"."), | |
2905 | NULL, | |
2906 | NULL, /* FIXME: i18n: */ | |
2907 | &setlist, &showlist); | |
8201327c MK |
2908 | |
2909 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
2910 | i386_coff_osabi_sniffer); | |
8201327c | 2911 | |
05816f70 | 2912 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 2913 | i386_svr4_init_abi); |
05816f70 | 2914 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 2915 | i386_go32_init_abi); |
38c968cf | 2916 | |
5ae96ec1 | 2917 | /* Initialize the i386-specific register groups & types. */ |
38c968cf | 2918 | i386_init_reggroups (); |
5ae96ec1 | 2919 | i386_init_types(); |
c906108c | 2920 | } |