Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f AC |
2 | |
3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, | |
4754a64e | 4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software |
931aecf5 | 5 | Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
acd5c798 MK |
25 | #include "arch-utils.h" |
26 | #include "command.h" | |
27 | #include "dummy-frame.h" | |
6405b0a6 | 28 | #include "dwarf2-frame.h" |
acd5c798 MK |
29 | #include "doublest.h" |
30 | #include "floatformat.h" | |
c906108c | 31 | #include "frame.h" |
acd5c798 MK |
32 | #include "frame-base.h" |
33 | #include "frame-unwind.h" | |
c906108c | 34 | #include "inferior.h" |
acd5c798 | 35 | #include "gdbcmd.h" |
c906108c | 36 | #include "gdbcore.h" |
dfe01d39 | 37 | #include "objfiles.h" |
acd5c798 MK |
38 | #include "osabi.h" |
39 | #include "regcache.h" | |
40 | #include "reggroups.h" | |
473f17b0 | 41 | #include "regset.h" |
c0d1d883 | 42 | #include "symfile.h" |
c906108c | 43 | #include "symtab.h" |
acd5c798 | 44 | #include "target.h" |
fd0407d6 | 45 | #include "value.h" |
a89aa300 | 46 | #include "dis-asm.h" |
acd5c798 | 47 | |
3d261580 | 48 | #include "gdb_assert.h" |
acd5c798 | 49 | #include "gdb_string.h" |
3d261580 | 50 | |
d2a7c97a | 51 | #include "i386-tdep.h" |
61113f8b | 52 | #include "i387-tdep.h" |
d2a7c97a | 53 | |
c4fc7f1b | 54 | /* Register names. */ |
c40e1eab | 55 | |
fc633446 MK |
56 | static char *i386_register_names[] = |
57 | { | |
58 | "eax", "ecx", "edx", "ebx", | |
59 | "esp", "ebp", "esi", "edi", | |
60 | "eip", "eflags", "cs", "ss", | |
61 | "ds", "es", "fs", "gs", | |
62 | "st0", "st1", "st2", "st3", | |
63 | "st4", "st5", "st6", "st7", | |
64 | "fctrl", "fstat", "ftag", "fiseg", | |
65 | "fioff", "foseg", "fooff", "fop", | |
66 | "xmm0", "xmm1", "xmm2", "xmm3", | |
67 | "xmm4", "xmm5", "xmm6", "xmm7", | |
68 | "mxcsr" | |
69 | }; | |
70 | ||
1cb97e17 | 71 | static const int i386_num_register_names = ARRAY_SIZE (i386_register_names); |
c40e1eab | 72 | |
c4fc7f1b | 73 | /* Register names for MMX pseudo-registers. */ |
28fc6740 AC |
74 | |
75 | static char *i386_mmx_names[] = | |
76 | { | |
77 | "mm0", "mm1", "mm2", "mm3", | |
78 | "mm4", "mm5", "mm6", "mm7" | |
79 | }; | |
c40e1eab | 80 | |
1cb97e17 | 81 | static const int i386_num_mmx_regs = ARRAY_SIZE (i386_mmx_names); |
c40e1eab | 82 | |
28fc6740 | 83 | static int |
5716833c | 84 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 85 | { |
5716833c MK |
86 | int mm0_regnum = gdbarch_tdep (gdbarch)->mm0_regnum; |
87 | ||
88 | if (mm0_regnum < 0) | |
89 | return 0; | |
90 | ||
91 | return (regnum >= mm0_regnum && regnum < mm0_regnum + i386_num_mmx_regs); | |
28fc6740 AC |
92 | } |
93 | ||
5716833c | 94 | /* SSE register? */ |
23a34459 | 95 | |
5716833c MK |
96 | static int |
97 | i386_sse_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 98 | { |
5716833c MK |
99 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
100 | ||
101 | #define I387_ST0_REGNUM tdep->st0_regnum | |
102 | #define I387_NUM_XMM_REGS tdep->num_xmm_regs | |
103 | ||
104 | if (I387_NUM_XMM_REGS == 0) | |
105 | return 0; | |
106 | ||
107 | return (I387_XMM0_REGNUM <= regnum && regnum < I387_MXCSR_REGNUM); | |
108 | ||
109 | #undef I387_ST0_REGNUM | |
110 | #undef I387_NUM_XMM_REGS | |
23a34459 AC |
111 | } |
112 | ||
5716833c MK |
113 | static int |
114 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 115 | { |
5716833c MK |
116 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
117 | ||
118 | #define I387_ST0_REGNUM tdep->st0_regnum | |
119 | #define I387_NUM_XMM_REGS tdep->num_xmm_regs | |
120 | ||
121 | if (I387_NUM_XMM_REGS == 0) | |
122 | return 0; | |
123 | ||
124 | return (regnum == I387_MXCSR_REGNUM); | |
125 | ||
126 | #undef I387_ST0_REGNUM | |
127 | #undef I387_NUM_XMM_REGS | |
23a34459 AC |
128 | } |
129 | ||
5716833c MK |
130 | #define I387_ST0_REGNUM (gdbarch_tdep (current_gdbarch)->st0_regnum) |
131 | #define I387_MM0_REGNUM (gdbarch_tdep (current_gdbarch)->mm0_regnum) | |
132 | #define I387_NUM_XMM_REGS (gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
133 | ||
134 | /* FP register? */ | |
23a34459 AC |
135 | |
136 | int | |
5716833c | 137 | i386_fp_regnum_p (int regnum) |
23a34459 | 138 | { |
5716833c MK |
139 | if (I387_ST0_REGNUM < 0) |
140 | return 0; | |
141 | ||
142 | return (I387_ST0_REGNUM <= regnum && regnum < I387_FCTRL_REGNUM); | |
23a34459 AC |
143 | } |
144 | ||
145 | int | |
5716833c | 146 | i386_fpc_regnum_p (int regnum) |
23a34459 | 147 | { |
5716833c MK |
148 | if (I387_ST0_REGNUM < 0) |
149 | return 0; | |
150 | ||
151 | return (I387_FCTRL_REGNUM <= regnum && regnum < I387_XMM0_REGNUM); | |
23a34459 AC |
152 | } |
153 | ||
30b0e2d8 | 154 | /* Return the name of register REGNUM. */ |
fc633446 | 155 | |
fa88f677 | 156 | const char * |
30b0e2d8 | 157 | i386_register_name (int regnum) |
fc633446 | 158 | { |
30b0e2d8 MK |
159 | if (i386_mmx_regnum_p (current_gdbarch, regnum)) |
160 | return i386_mmx_names[regnum - I387_MM0_REGNUM]; | |
fc633446 | 161 | |
30b0e2d8 MK |
162 | if (regnum >= 0 && regnum < i386_num_register_names) |
163 | return i386_register_names[regnum]; | |
70913449 | 164 | |
c40e1eab | 165 | return NULL; |
fc633446 MK |
166 | } |
167 | ||
c4fc7f1b | 168 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
169 | number used by GDB. */ |
170 | ||
8201327c | 171 | static int |
c4fc7f1b | 172 | i386_dbx_reg_to_regnum (int reg) |
85540d8c | 173 | { |
c4fc7f1b MK |
174 | /* This implements what GCC calls the "default" register map |
175 | (dbx_register_map[]). */ | |
176 | ||
85540d8c MK |
177 | if (reg >= 0 && reg <= 7) |
178 | { | |
9872ad24 JB |
179 | /* General-purpose registers. The debug info calls %ebp |
180 | register 4, and %esp register 5. */ | |
181 | if (reg == 4) | |
182 | return 5; | |
183 | else if (reg == 5) | |
184 | return 4; | |
185 | else return reg; | |
85540d8c MK |
186 | } |
187 | else if (reg >= 12 && reg <= 19) | |
188 | { | |
189 | /* Floating-point registers. */ | |
5716833c | 190 | return reg - 12 + I387_ST0_REGNUM; |
85540d8c MK |
191 | } |
192 | else if (reg >= 21 && reg <= 28) | |
193 | { | |
194 | /* SSE registers. */ | |
5716833c | 195 | return reg - 21 + I387_XMM0_REGNUM; |
85540d8c MK |
196 | } |
197 | else if (reg >= 29 && reg <= 36) | |
198 | { | |
199 | /* MMX registers. */ | |
5716833c | 200 | return reg - 29 + I387_MM0_REGNUM; |
85540d8c MK |
201 | } |
202 | ||
203 | /* This will hopefully provoke a warning. */ | |
204 | return NUM_REGS + NUM_PSEUDO_REGS; | |
205 | } | |
206 | ||
c4fc7f1b MK |
207 | /* Convert SVR4 register number REG to the appropriate register number |
208 | used by GDB. */ | |
85540d8c | 209 | |
8201327c | 210 | static int |
c4fc7f1b | 211 | i386_svr4_reg_to_regnum (int reg) |
85540d8c | 212 | { |
c4fc7f1b MK |
213 | /* This implements the GCC register map that tries to be compatible |
214 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
215 | ||
216 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
217 | numbers the floating point registers differently. */ |
218 | if (reg >= 0 && reg <= 9) | |
219 | { | |
acd5c798 | 220 | /* General-purpose registers. */ |
85540d8c MK |
221 | return reg; |
222 | } | |
223 | else if (reg >= 11 && reg <= 18) | |
224 | { | |
225 | /* Floating-point registers. */ | |
5716833c | 226 | return reg - 11 + I387_ST0_REGNUM; |
85540d8c | 227 | } |
c6f4c129 | 228 | else if (reg >= 21 && reg <= 36) |
85540d8c | 229 | { |
c4fc7f1b MK |
230 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
231 | return i386_dbx_reg_to_regnum (reg); | |
85540d8c MK |
232 | } |
233 | ||
c6f4c129 JB |
234 | switch (reg) |
235 | { | |
236 | case 37: return I387_FCTRL_REGNUM; | |
237 | case 38: return I387_FSTAT_REGNUM; | |
238 | case 39: return I387_MXCSR_REGNUM; | |
239 | case 40: return I386_ES_REGNUM; | |
240 | case 41: return I386_CS_REGNUM; | |
241 | case 42: return I386_SS_REGNUM; | |
242 | case 43: return I386_DS_REGNUM; | |
243 | case 44: return I386_FS_REGNUM; | |
244 | case 45: return I386_GS_REGNUM; | |
245 | } | |
246 | ||
85540d8c MK |
247 | /* This will hopefully provoke a warning. */ |
248 | return NUM_REGS + NUM_PSEUDO_REGS; | |
249 | } | |
5716833c MK |
250 | |
251 | #undef I387_ST0_REGNUM | |
252 | #undef I387_MM0_REGNUM | |
253 | #undef I387_NUM_XMM_REGS | |
fc338970 | 254 | \f |
917317f4 | 255 | |
fc338970 MK |
256 | /* This is the variable that is set with "set disassembly-flavor", and |
257 | its legitimate values. */ | |
53904c9e AC |
258 | static const char att_flavor[] = "att"; |
259 | static const char intel_flavor[] = "intel"; | |
260 | static const char *valid_flavors[] = | |
c5aa993b | 261 | { |
c906108c SS |
262 | att_flavor, |
263 | intel_flavor, | |
264 | NULL | |
265 | }; | |
53904c9e | 266 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 267 | \f |
c906108c | 268 | |
acd5c798 MK |
269 | /* Use the program counter to determine the contents and size of a |
270 | breakpoint instruction. Return a pointer to a string of bytes that | |
271 | encode a breakpoint instruction, store the length of the string in | |
272 | *LEN and optionally adjust *PC to point to the correct memory | |
273 | location for inserting the breakpoint. | |
c906108c | 274 | |
acd5c798 MK |
275 | On the i386 we have a single breakpoint that fits in a single byte |
276 | and can be inserted anywhere. | |
c906108c | 277 | |
acd5c798 | 278 | This function is 64-bit safe. */ |
63c0089f MK |
279 | |
280 | static const gdb_byte * | |
acd5c798 | 281 | i386_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
c906108c | 282 | { |
63c0089f MK |
283 | static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ |
284 | ||
acd5c798 MK |
285 | *len = sizeof (break_insn); |
286 | return break_insn; | |
c906108c | 287 | } |
fc338970 | 288 | \f |
acd5c798 MK |
289 | #ifdef I386_REGNO_TO_SYMMETRY |
290 | #error "The Sequent Symmetry is no longer supported." | |
291 | #endif | |
c906108c | 292 | |
acd5c798 MK |
293 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
294 | and %esp "belong" to the calling function. Therefore these | |
295 | registers should be saved if they're going to be modified. */ | |
c906108c | 296 | |
acd5c798 MK |
297 | /* The maximum number of saved registers. This should include all |
298 | registers mentioned above, and %eip. */ | |
a3386186 | 299 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
300 | |
301 | struct i386_frame_cache | |
c906108c | 302 | { |
acd5c798 MK |
303 | /* Base address. */ |
304 | CORE_ADDR base; | |
772562f8 | 305 | LONGEST sp_offset; |
acd5c798 MK |
306 | CORE_ADDR pc; |
307 | ||
fd13a04a AC |
308 | /* Saved registers. */ |
309 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 MK |
310 | CORE_ADDR saved_sp; |
311 | int pc_in_eax; | |
312 | ||
313 | /* Stack space reserved for local variables. */ | |
314 | long locals; | |
315 | }; | |
316 | ||
317 | /* Allocate and initialize a frame cache. */ | |
318 | ||
319 | static struct i386_frame_cache * | |
fd13a04a | 320 | i386_alloc_frame_cache (void) |
acd5c798 MK |
321 | { |
322 | struct i386_frame_cache *cache; | |
323 | int i; | |
324 | ||
325 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
326 | ||
327 | /* Base address. */ | |
328 | cache->base = 0; | |
329 | cache->sp_offset = -4; | |
330 | cache->pc = 0; | |
331 | ||
fd13a04a AC |
332 | /* Saved registers. We initialize these to -1 since zero is a valid |
333 | offset (that's where %ebp is supposed to be stored). */ | |
334 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
335 | cache->saved_regs[i] = -1; | |
acd5c798 MK |
336 | cache->saved_sp = 0; |
337 | cache->pc_in_eax = 0; | |
338 | ||
339 | /* Frameless until proven otherwise. */ | |
340 | cache->locals = -1; | |
341 | ||
342 | return cache; | |
343 | } | |
c906108c | 344 | |
acd5c798 MK |
345 | /* If the instruction at PC is a jump, return the address of its |
346 | target. Otherwise, return PC. */ | |
c906108c | 347 | |
acd5c798 MK |
348 | static CORE_ADDR |
349 | i386_follow_jump (CORE_ADDR pc) | |
350 | { | |
63c0089f | 351 | gdb_byte op; |
acd5c798 MK |
352 | long delta = 0; |
353 | int data16 = 0; | |
c906108c | 354 | |
acd5c798 MK |
355 | op = read_memory_unsigned_integer (pc, 1); |
356 | if (op == 0x66) | |
c906108c | 357 | { |
c906108c | 358 | data16 = 1; |
acd5c798 | 359 | op = read_memory_unsigned_integer (pc + 1, 1); |
c906108c SS |
360 | } |
361 | ||
acd5c798 | 362 | switch (op) |
c906108c SS |
363 | { |
364 | case 0xe9: | |
fc338970 | 365 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
366 | if (data16) |
367 | { | |
acd5c798 | 368 | delta = read_memory_integer (pc + 2, 2); |
c906108c | 369 | |
fc338970 MK |
370 | /* Include the size of the jmp instruction (including the |
371 | 0x66 prefix). */ | |
acd5c798 | 372 | delta += 4; |
c906108c SS |
373 | } |
374 | else | |
375 | { | |
acd5c798 | 376 | delta = read_memory_integer (pc + 1, 4); |
c906108c | 377 | |
acd5c798 MK |
378 | /* Include the size of the jmp instruction. */ |
379 | delta += 5; | |
c906108c SS |
380 | } |
381 | break; | |
382 | case 0xeb: | |
fc338970 | 383 | /* Relative jump, disp8 (ignore data16). */ |
acd5c798 | 384 | delta = read_memory_integer (pc + data16 + 1, 1); |
c906108c | 385 | |
acd5c798 | 386 | delta += data16 + 2; |
c906108c SS |
387 | break; |
388 | } | |
c906108c | 389 | |
acd5c798 MK |
390 | return pc + delta; |
391 | } | |
fc338970 | 392 | |
acd5c798 MK |
393 | /* Check whether PC points at a prologue for a function returning a |
394 | structure or union. If so, it updates CACHE and returns the | |
395 | address of the first instruction after the code sequence that | |
396 | removes the "hidden" argument from the stack or CURRENT_PC, | |
397 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 398 | |
acd5c798 MK |
399 | static CORE_ADDR |
400 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
401 | struct i386_frame_cache *cache) | |
c906108c | 402 | { |
acd5c798 MK |
403 | /* Functions that return a structure or union start with: |
404 | ||
405 | popl %eax 0x58 | |
406 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
407 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
408 | ||
409 | (the System V compiler puts out the second `xchg' instruction, | |
410 | and the assembler doesn't try to optimize it, so the 'sib' form | |
411 | gets generated). This sequence is used to get the address of the | |
412 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
413 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
414 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
415 | gdb_byte buf[4]; | |
416 | gdb_byte op; | |
c906108c | 417 | |
acd5c798 MK |
418 | if (current_pc <= pc) |
419 | return pc; | |
420 | ||
421 | op = read_memory_unsigned_integer (pc, 1); | |
c906108c | 422 | |
acd5c798 MK |
423 | if (op != 0x58) /* popl %eax */ |
424 | return pc; | |
c906108c | 425 | |
acd5c798 MK |
426 | read_memory (pc + 1, buf, 4); |
427 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) | |
428 | return pc; | |
c906108c | 429 | |
acd5c798 | 430 | if (current_pc == pc) |
c906108c | 431 | { |
acd5c798 MK |
432 | cache->sp_offset += 4; |
433 | return current_pc; | |
c906108c SS |
434 | } |
435 | ||
acd5c798 | 436 | if (current_pc == pc + 1) |
c906108c | 437 | { |
acd5c798 MK |
438 | cache->pc_in_eax = 1; |
439 | return current_pc; | |
440 | } | |
441 | ||
442 | if (buf[1] == proto1[1]) | |
443 | return pc + 4; | |
444 | else | |
445 | return pc + 5; | |
446 | } | |
447 | ||
448 | static CORE_ADDR | |
449 | i386_skip_probe (CORE_ADDR pc) | |
450 | { | |
451 | /* A function may start with | |
fc338970 | 452 | |
acd5c798 MK |
453 | pushl constant |
454 | call _probe | |
455 | addl $4, %esp | |
fc338970 | 456 | |
acd5c798 MK |
457 | followed by |
458 | ||
459 | pushl %ebp | |
fc338970 | 460 | |
acd5c798 | 461 | etc. */ |
63c0089f MK |
462 | gdb_byte buf[8]; |
463 | gdb_byte op; | |
fc338970 | 464 | |
acd5c798 MK |
465 | op = read_memory_unsigned_integer (pc, 1); |
466 | ||
467 | if (op == 0x68 || op == 0x6a) | |
468 | { | |
469 | int delta; | |
c906108c | 470 | |
acd5c798 MK |
471 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
472 | four-byte operand, depending on the opcode. */ | |
c906108c | 473 | if (op == 0x68) |
acd5c798 | 474 | delta = 5; |
c906108c | 475 | else |
acd5c798 | 476 | delta = 2; |
c906108c | 477 | |
acd5c798 MK |
478 | /* Read the following 8 bytes, which should be `call _probe' (6 |
479 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
480 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 481 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 482 | pc += delta + sizeof (buf); |
c906108c SS |
483 | } |
484 | ||
acd5c798 MK |
485 | return pc; |
486 | } | |
487 | ||
37bdc87e MK |
488 | /* Maximum instruction length we need to handle. */ |
489 | #define I386_MAX_INSN_LEN 6 | |
490 | ||
491 | /* Instruction description. */ | |
492 | struct i386_insn | |
493 | { | |
494 | size_t len; | |
63c0089f MK |
495 | gdb_byte insn[I386_MAX_INSN_LEN]; |
496 | gdb_byte mask[I386_MAX_INSN_LEN]; | |
37bdc87e MK |
497 | }; |
498 | ||
499 | /* Search for the instruction at PC in the list SKIP_INSNS. Return | |
500 | the first instruction description that matches. Otherwise, return | |
501 | NULL. */ | |
502 | ||
503 | static struct i386_insn * | |
504 | i386_match_insn (CORE_ADDR pc, struct i386_insn *skip_insns) | |
505 | { | |
506 | struct i386_insn *insn; | |
63c0089f | 507 | gdb_byte op; |
37bdc87e MK |
508 | |
509 | op = read_memory_unsigned_integer (pc, 1); | |
510 | ||
511 | for (insn = skip_insns; insn->len > 0; insn++) | |
512 | { | |
513 | if ((op & insn->mask[0]) == insn->insn[0]) | |
514 | { | |
613e8135 MK |
515 | gdb_byte buf[I386_MAX_INSN_LEN - 1]; |
516 | int insn_matched = 1; | |
37bdc87e MK |
517 | size_t i; |
518 | ||
519 | gdb_assert (insn->len > 1); | |
520 | gdb_assert (insn->len <= I386_MAX_INSN_LEN); | |
521 | ||
522 | read_memory (pc + 1, buf, insn->len - 1); | |
523 | for (i = 1; i < insn->len; i++) | |
524 | { | |
525 | if ((buf[i - 1] & insn->mask[i]) != insn->insn[i]) | |
613e8135 | 526 | insn_matched = 0; |
37bdc87e | 527 | } |
613e8135 MK |
528 | |
529 | if (insn_matched) | |
530 | return insn; | |
37bdc87e MK |
531 | } |
532 | } | |
533 | ||
534 | return NULL; | |
535 | } | |
536 | ||
537 | /* Some special instructions that might be migrated by GCC into the | |
538 | part of the prologue that sets up the new stack frame. Because the | |
539 | stack frame hasn't been setup yet, no registers have been saved | |
540 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
541 | touched. */ | |
542 | ||
543 | struct i386_insn i386_frame_setup_skip_insns[] = | |
544 | { | |
545 | /* Check for `movb imm8, r' and `movl imm32, r'. | |
546 | ||
547 | ??? Should we handle 16-bit operand-sizes here? */ | |
548 | ||
549 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
550 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
551 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
552 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
553 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
554 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
555 | { 5, { 0xb8 }, { 0xfe } }, | |
556 | /* `movl imm32, %edx' */ | |
557 | { 5, { 0xba }, { 0xff } }, | |
558 | ||
559 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
560 | encoding for `mov m32, %eax'. | |
561 | ||
562 | ??? Should we handle SIB adressing here? | |
563 | ??? Should we handle 16-bit operand-sizes here? */ | |
564 | ||
565 | /* `movl m32, %eax' */ | |
566 | { 5, { 0xa1 }, { 0xff } }, | |
567 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
568 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
569 | /* `movl m32, %edx' */ | |
570 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
571 | ||
572 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
573 | Because of the symmetry, there are actually two ways to encode | |
574 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
575 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
576 | ||
577 | /* `subl %eax, %eax' */ | |
578 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
579 | /* `subl %ecx, %ecx' */ | |
580 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
581 | /* `subl %edx, %edx' */ | |
582 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
583 | /* `xorl %eax, %eax' */ | |
584 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
585 | /* `xorl %ecx, %ecx' */ | |
586 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
587 | /* `xorl %edx, %edx' */ | |
588 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
589 | { 0 } | |
590 | }; | |
591 | ||
acd5c798 MK |
592 | /* Check whether PC points at a code that sets up a new stack frame. |
593 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
594 | instruction after the sequence that sets up the frame or LIMIT, |
595 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
596 | |
597 | static CORE_ADDR | |
37bdc87e | 598 | i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR limit, |
acd5c798 MK |
599 | struct i386_frame_cache *cache) |
600 | { | |
37bdc87e | 601 | struct i386_insn *insn; |
63c0089f | 602 | gdb_byte op; |
26604a34 | 603 | int skip = 0; |
acd5c798 | 604 | |
37bdc87e MK |
605 | if (limit <= pc) |
606 | return limit; | |
acd5c798 MK |
607 | |
608 | op = read_memory_unsigned_integer (pc, 1); | |
609 | ||
c906108c | 610 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 611 | { |
acd5c798 MK |
612 | /* Take into account that we've executed the `pushl %ebp' that |
613 | starts this instruction sequence. */ | |
fd13a04a | 614 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 615 | cache->sp_offset += 4; |
37bdc87e | 616 | pc++; |
acd5c798 MK |
617 | |
618 | /* If that's all, return now. */ | |
37bdc87e MK |
619 | if (limit <= pc) |
620 | return limit; | |
26604a34 | 621 | |
b4632131 | 622 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
623 | GCC into the prologue and skip them. At this point in the |
624 | prologue, code should only touch the scratch registers %eax, | |
625 | %ecx and %edx, so while the number of posibilities is sheer, | |
626 | it is limited. | |
5daa5b4e | 627 | |
26604a34 MK |
628 | Make sure we only skip these instructions if we later see the |
629 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 630 | while (pc + skip < limit) |
26604a34 | 631 | { |
37bdc87e MK |
632 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
633 | if (insn == NULL) | |
634 | break; | |
b4632131 | 635 | |
37bdc87e | 636 | skip += insn->len; |
26604a34 MK |
637 | } |
638 | ||
37bdc87e MK |
639 | /* If that's all, return now. */ |
640 | if (limit <= pc + skip) | |
641 | return limit; | |
642 | ||
643 | op = read_memory_unsigned_integer (pc + skip, 1); | |
644 | ||
26604a34 | 645 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
acd5c798 | 646 | switch (op) |
c906108c SS |
647 | { |
648 | case 0x8b: | |
37bdc87e MK |
649 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xec) |
650 | return pc; | |
c906108c SS |
651 | break; |
652 | case 0x89: | |
37bdc87e MK |
653 | if (read_memory_unsigned_integer (pc + skip + 1, 1) != 0xe5) |
654 | return pc; | |
c906108c SS |
655 | break; |
656 | default: | |
37bdc87e | 657 | return pc; |
c906108c | 658 | } |
acd5c798 | 659 | |
26604a34 MK |
660 | /* OK, we actually have a frame. We just don't know how large |
661 | it is yet. Set its size to zero. We'll adjust it if | |
662 | necessary. We also now commit to skipping the special | |
663 | instructions mentioned before. */ | |
acd5c798 | 664 | cache->locals = 0; |
37bdc87e | 665 | pc += (skip + 2); |
acd5c798 MK |
666 | |
667 | /* If that's all, return now. */ | |
37bdc87e MK |
668 | if (limit <= pc) |
669 | return limit; | |
acd5c798 | 670 | |
fc338970 MK |
671 | /* Check for stack adjustment |
672 | ||
acd5c798 | 673 | subl $XXX, %esp |
fc338970 | 674 | |
fd35795f | 675 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 676 | reg, so we don't have to worry about a data16 prefix. */ |
37bdc87e | 677 | op = read_memory_unsigned_integer (pc, 1); |
c906108c SS |
678 | if (op == 0x83) |
679 | { | |
fd35795f | 680 | /* `subl' with 8-bit immediate. */ |
37bdc87e | 681 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 682 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 683 | return pc; |
acd5c798 | 684 | |
37bdc87e MK |
685 | /* `subl' with signed 8-bit immediate (though it wouldn't |
686 | make sense to be negative). */ | |
687 | cache->locals = read_memory_integer (pc + 2, 1); | |
688 | return pc + 3; | |
c906108c SS |
689 | } |
690 | else if (op == 0x81) | |
691 | { | |
fd35795f | 692 | /* Maybe it is `subl' with a 32-bit immediate. */ |
37bdc87e | 693 | if (read_memory_unsigned_integer (pc + 1, 1) != 0xec) |
fc338970 | 694 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 695 | return pc; |
acd5c798 | 696 | |
fd35795f | 697 | /* It is `subl' with a 32-bit immediate. */ |
37bdc87e MK |
698 | cache->locals = read_memory_integer (pc + 2, 4); |
699 | return pc + 6; | |
c906108c SS |
700 | } |
701 | else | |
702 | { | |
acd5c798 | 703 | /* Some instruction other than `subl'. */ |
37bdc87e | 704 | return pc; |
c906108c SS |
705 | } |
706 | } | |
37bdc87e | 707 | else if (op == 0xc8) /* enter */ |
c906108c | 708 | { |
acd5c798 MK |
709 | cache->locals = read_memory_unsigned_integer (pc + 1, 2); |
710 | return pc + 4; | |
c906108c | 711 | } |
21d0e8a4 | 712 | |
acd5c798 | 713 | return pc; |
21d0e8a4 MK |
714 | } |
715 | ||
acd5c798 MK |
716 | /* Check whether PC points at code that saves registers on the stack. |
717 | If so, it updates CACHE and returns the address of the first | |
718 | instruction after the register saves or CURRENT_PC, whichever is | |
719 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
720 | |
721 | static CORE_ADDR | |
acd5c798 MK |
722 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
723 | struct i386_frame_cache *cache) | |
6bff26de | 724 | { |
99ab4326 | 725 | CORE_ADDR offset = 0; |
63c0089f | 726 | gdb_byte op; |
99ab4326 | 727 | int i; |
c0d1d883 | 728 | |
99ab4326 MK |
729 | if (cache->locals > 0) |
730 | offset -= cache->locals; | |
731 | for (i = 0; i < 8 && pc < current_pc; i++) | |
732 | { | |
733 | op = read_memory_unsigned_integer (pc, 1); | |
734 | if (op < 0x50 || op > 0x57) | |
735 | break; | |
0d17c81d | 736 | |
99ab4326 MK |
737 | offset -= 4; |
738 | cache->saved_regs[op - 0x50] = offset; | |
739 | cache->sp_offset += 4; | |
740 | pc++; | |
6bff26de MK |
741 | } |
742 | ||
acd5c798 | 743 | return pc; |
22797942 AC |
744 | } |
745 | ||
acd5c798 MK |
746 | /* Do a full analysis of the prologue at PC and update CACHE |
747 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
748 | address where the analysis stopped. | |
ed84f6c1 | 749 | |
fc338970 MK |
750 | We handle these cases: |
751 | ||
752 | The startup sequence can be at the start of the function, or the | |
753 | function can start with a branch to startup code at the end. | |
754 | ||
755 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
756 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
757 | once used in the System V compiler). | |
758 | ||
759 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
760 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
761 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
762 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
763 | |
764 | Next, the registers used by this function are pushed. With the | |
765 | System V compiler they will always be in the order: %edi, %esi, | |
766 | %ebx (and sometimes a harmless bug causes it to also save but not | |
767 | restore %eax); however, the code below is willing to see the pushes | |
768 | in any order, and will handle up to 8 of them. | |
769 | ||
770 | If the setup sequence is at the end of the function, then the next | |
771 | instruction will be a branch back to the start. */ | |
c906108c | 772 | |
acd5c798 MK |
773 | static CORE_ADDR |
774 | i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
775 | struct i386_frame_cache *cache) | |
c906108c | 776 | { |
acd5c798 MK |
777 | pc = i386_follow_jump (pc); |
778 | pc = i386_analyze_struct_return (pc, current_pc, cache); | |
779 | pc = i386_skip_probe (pc); | |
780 | pc = i386_analyze_frame_setup (pc, current_pc, cache); | |
781 | return i386_analyze_register_saves (pc, current_pc, cache); | |
c906108c SS |
782 | } |
783 | ||
fc338970 | 784 | /* Return PC of first real instruction. */ |
c906108c | 785 | |
3a1e71e3 | 786 | static CORE_ADDR |
acd5c798 | 787 | i386_skip_prologue (CORE_ADDR start_pc) |
c906108c | 788 | { |
63c0089f | 789 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
790 | { |
791 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
792 | 0x5b, /* popl %ebx */ | |
c5aa993b | 793 | }; |
acd5c798 MK |
794 | struct i386_frame_cache cache; |
795 | CORE_ADDR pc; | |
63c0089f | 796 | gdb_byte op; |
acd5c798 | 797 | int i; |
c5aa993b | 798 | |
acd5c798 MK |
799 | cache.locals = -1; |
800 | pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache); | |
801 | if (cache.locals < 0) | |
802 | return start_pc; | |
c5aa993b | 803 | |
acd5c798 | 804 | /* Found valid frame setup. */ |
c906108c | 805 | |
fc338970 MK |
806 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
807 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
808 | %ebx: |
809 | ||
fc338970 MK |
810 | call 0x0 |
811 | popl %ebx | |
812 | movl %ebx,x(%ebp) (optional) | |
813 | addl y,%ebx | |
814 | ||
c906108c SS |
815 | This code is with the rest of the prologue (at the end of the |
816 | function), so we have to skip it to get to the first real | |
817 | instruction at the start of the function. */ | |
c5aa993b | 818 | |
c906108c SS |
819 | for (i = 0; i < 6; i++) |
820 | { | |
acd5c798 | 821 | op = read_memory_unsigned_integer (pc + i, 1); |
c5aa993b | 822 | if (pic_pat[i] != op) |
c906108c SS |
823 | break; |
824 | } | |
825 | if (i == 6) | |
826 | { | |
acd5c798 MK |
827 | int delta = 6; |
828 | ||
829 | op = read_memory_unsigned_integer (pc + delta, 1); | |
c906108c | 830 | |
c5aa993b | 831 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 832 | { |
acd5c798 MK |
833 | op = read_memory_unsigned_integer (pc + delta + 1, 1); |
834 | ||
fc338970 | 835 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 836 | delta += 3; |
fc338970 | 837 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 838 | delta += 6; |
fc338970 | 839 | else /* Unexpected instruction. */ |
acd5c798 MK |
840 | delta = 0; |
841 | ||
842 | op = read_memory_unsigned_integer (pc + delta, 1); | |
c906108c | 843 | } |
acd5c798 | 844 | |
c5aa993b | 845 | /* addl y,%ebx */ |
acd5c798 MK |
846 | if (delta > 0 && op == 0x81 |
847 | && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3); | |
c906108c | 848 | { |
acd5c798 | 849 | pc += delta + 6; |
c906108c SS |
850 | } |
851 | } | |
c5aa993b | 852 | |
e63bbc88 MK |
853 | /* If the function starts with a branch (to startup code at the end) |
854 | the last instruction should bring us back to the first | |
855 | instruction of the real code. */ | |
856 | if (i386_follow_jump (start_pc) != start_pc) | |
857 | pc = i386_follow_jump (pc); | |
858 | ||
859 | return pc; | |
c906108c SS |
860 | } |
861 | ||
acd5c798 | 862 | /* This function is 64-bit safe. */ |
93924b6b | 863 | |
acd5c798 MK |
864 | static CORE_ADDR |
865 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 866 | { |
63c0089f | 867 | gdb_byte buf[8]; |
acd5c798 MK |
868 | |
869 | frame_unwind_register (next_frame, PC_REGNUM, buf); | |
870 | return extract_typed_address (buf, builtin_type_void_func_ptr); | |
93924b6b | 871 | } |
acd5c798 | 872 | \f |
93924b6b | 873 | |
acd5c798 | 874 | /* Normal frames. */ |
c5aa993b | 875 | |
acd5c798 MK |
876 | static struct i386_frame_cache * |
877 | i386_frame_cache (struct frame_info *next_frame, void **this_cache) | |
a7769679 | 878 | { |
acd5c798 | 879 | struct i386_frame_cache *cache; |
63c0089f | 880 | gdb_byte buf[4]; |
acd5c798 MK |
881 | int i; |
882 | ||
883 | if (*this_cache) | |
884 | return *this_cache; | |
885 | ||
fd13a04a | 886 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
887 | *this_cache = cache; |
888 | ||
889 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
890 | which holds the base address for the current stack frame. | |
891 | However, for functions that don't need it, the frame pointer is | |
892 | optional. For these "frameless" functions the frame pointer is | |
893 | actually the frame pointer of the calling frame. Signal | |
894 | trampolines are just a special case of a "frameless" function. | |
895 | They (usually) share their frame pointer with the frame that was | |
896 | in progress when the signal occurred. */ | |
897 | ||
898 | frame_unwind_register (next_frame, I386_EBP_REGNUM, buf); | |
899 | cache->base = extract_unsigned_integer (buf, 4); | |
900 | if (cache->base == 0) | |
901 | return cache; | |
902 | ||
903 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 904 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 MK |
905 | |
906 | cache->pc = frame_func_unwind (next_frame); | |
907 | if (cache->pc != 0) | |
908 | i386_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); | |
909 | ||
910 | if (cache->locals < 0) | |
911 | { | |
912 | /* We didn't find a valid frame, which means that CACHE->base | |
913 | currently holds the frame pointer for our calling frame. If | |
914 | we're at the start of a function, or somewhere half-way its | |
915 | prologue, the function's frame probably hasn't been fully | |
916 | setup yet. Try to reconstruct the base address for the stack | |
917 | frame by looking at the stack pointer. For truly "frameless" | |
918 | functions this might work too. */ | |
919 | ||
920 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); | |
921 | cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset; | |
922 | } | |
923 | ||
924 | /* Now that we have the base address for the stack frame we can | |
925 | calculate the value of %esp in the calling frame. */ | |
926 | cache->saved_sp = cache->base + 8; | |
a7769679 | 927 | |
acd5c798 MK |
928 | /* Adjust all the saved registers such that they contain addresses |
929 | instead of offsets. */ | |
930 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
931 | if (cache->saved_regs[i] != -1) |
932 | cache->saved_regs[i] += cache->base; | |
acd5c798 MK |
933 | |
934 | return cache; | |
a7769679 MK |
935 | } |
936 | ||
3a1e71e3 | 937 | static void |
acd5c798 MK |
938 | i386_frame_this_id (struct frame_info *next_frame, void **this_cache, |
939 | struct frame_id *this_id) | |
c906108c | 940 | { |
acd5c798 MK |
941 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); |
942 | ||
943 | /* This marks the outermost frame. */ | |
944 | if (cache->base == 0) | |
945 | return; | |
946 | ||
3e210248 | 947 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
948 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); |
949 | } | |
950 | ||
951 | static void | |
952 | i386_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
953 | int regnum, int *optimizedp, | |
954 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
c6826062 | 955 | int *realnump, gdb_byte *valuep) |
acd5c798 MK |
956 | { |
957 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); | |
958 | ||
959 | gdb_assert (regnum >= 0); | |
960 | ||
961 | /* The System V ABI says that: | |
962 | ||
963 | "The flags register contains the system flags, such as the | |
964 | direction flag and the carry flag. The direction flag must be | |
965 | set to the forward (that is, zero) direction before entry and | |
966 | upon exit from a function. Other user flags have no specified | |
967 | role in the standard calling sequence and are not preserved." | |
968 | ||
969 | To guarantee the "upon exit" part of that statement we fake a | |
970 | saved flags register that has its direction flag cleared. | |
971 | ||
972 | Note that GCC doesn't seem to rely on the fact that the direction | |
973 | flag is cleared after a function return; it always explicitly | |
974 | clears the flag before operations where it matters. | |
975 | ||
976 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
977 | right thing to do. The way we fake the flags register here makes | |
978 | it impossible to change it. */ | |
979 | ||
980 | if (regnum == I386_EFLAGS_REGNUM) | |
981 | { | |
982 | *optimizedp = 0; | |
983 | *lvalp = not_lval; | |
984 | *addrp = 0; | |
985 | *realnump = -1; | |
986 | if (valuep) | |
987 | { | |
988 | ULONGEST val; | |
c5aa993b | 989 | |
acd5c798 | 990 | /* Clear the direction flag. */ |
f837910f MK |
991 | val = frame_unwind_register_unsigned (next_frame, |
992 | I386_EFLAGS_REGNUM); | |
acd5c798 MK |
993 | val &= ~(1 << 10); |
994 | store_unsigned_integer (valuep, 4, val); | |
995 | } | |
996 | ||
997 | return; | |
998 | } | |
1211c4e4 | 999 | |
acd5c798 | 1000 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
c906108c | 1001 | { |
00b25ff3 AC |
1002 | *optimizedp = 0; |
1003 | *lvalp = lval_register; | |
1004 | *addrp = 0; | |
1005 | *realnump = I386_EAX_REGNUM; | |
1006 | if (valuep) | |
1007 | frame_unwind_register (next_frame, (*realnump), valuep); | |
acd5c798 MK |
1008 | return; |
1009 | } | |
1010 | ||
1011 | if (regnum == I386_ESP_REGNUM && cache->saved_sp) | |
1012 | { | |
1013 | *optimizedp = 0; | |
1014 | *lvalp = not_lval; | |
1015 | *addrp = 0; | |
1016 | *realnump = -1; | |
1017 | if (valuep) | |
c906108c | 1018 | { |
acd5c798 MK |
1019 | /* Store the value. */ |
1020 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
c906108c | 1021 | } |
acd5c798 | 1022 | return; |
c906108c | 1023 | } |
acd5c798 | 1024 | |
fd13a04a AC |
1025 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
1026 | { | |
1027 | *optimizedp = 0; | |
1028 | *lvalp = lval_memory; | |
1029 | *addrp = cache->saved_regs[regnum]; | |
1030 | *realnump = -1; | |
1031 | if (valuep) | |
1032 | { | |
1033 | /* Read the value in from memory. */ | |
1034 | read_memory (*addrp, valuep, | |
1035 | register_size (current_gdbarch, regnum)); | |
1036 | } | |
1037 | return; | |
1038 | } | |
1039 | ||
00b25ff3 AC |
1040 | *optimizedp = 0; |
1041 | *lvalp = lval_register; | |
1042 | *addrp = 0; | |
1043 | *realnump = regnum; | |
1044 | if (valuep) | |
1045 | frame_unwind_register (next_frame, (*realnump), valuep); | |
acd5c798 MK |
1046 | } |
1047 | ||
1048 | static const struct frame_unwind i386_frame_unwind = | |
1049 | { | |
1050 | NORMAL_FRAME, | |
1051 | i386_frame_this_id, | |
1052 | i386_frame_prev_register | |
1053 | }; | |
1054 | ||
1055 | static const struct frame_unwind * | |
336d1bba | 1056 | i386_frame_sniffer (struct frame_info *next_frame) |
acd5c798 MK |
1057 | { |
1058 | return &i386_frame_unwind; | |
1059 | } | |
1060 | \f | |
1061 | ||
1062 | /* Signal trampolines. */ | |
1063 | ||
1064 | static struct i386_frame_cache * | |
1065 | i386_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1066 | { | |
1067 | struct i386_frame_cache *cache; | |
1068 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1069 | CORE_ADDR addr; | |
63c0089f | 1070 | gdb_byte buf[4]; |
acd5c798 MK |
1071 | |
1072 | if (*this_cache) | |
1073 | return *this_cache; | |
1074 | ||
fd13a04a | 1075 | cache = i386_alloc_frame_cache (); |
acd5c798 MK |
1076 | |
1077 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); | |
1078 | cache->base = extract_unsigned_integer (buf, 4) - 4; | |
1079 | ||
1080 | addr = tdep->sigcontext_addr (next_frame); | |
a3386186 MK |
1081 | if (tdep->sc_reg_offset) |
1082 | { | |
1083 | int i; | |
1084 | ||
1085 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); | |
1086 | ||
1087 | for (i = 0; i < tdep->sc_num_regs; i++) | |
1088 | if (tdep->sc_reg_offset[i] != -1) | |
fd13a04a | 1089 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; |
a3386186 MK |
1090 | } |
1091 | else | |
1092 | { | |
fd13a04a AC |
1093 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; |
1094 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
a3386186 | 1095 | } |
acd5c798 MK |
1096 | |
1097 | *this_cache = cache; | |
1098 | return cache; | |
1099 | } | |
1100 | ||
1101 | static void | |
1102 | i386_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1103 | struct frame_id *this_id) | |
1104 | { | |
1105 | struct i386_frame_cache *cache = | |
1106 | i386_sigtramp_frame_cache (next_frame, this_cache); | |
1107 | ||
3e210248 | 1108 | /* See the end of i386_push_dummy_call. */ |
acd5c798 MK |
1109 | (*this_id) = frame_id_build (cache->base + 8, frame_pc_unwind (next_frame)); |
1110 | } | |
1111 | ||
1112 | static void | |
1113 | i386_sigtramp_frame_prev_register (struct frame_info *next_frame, | |
1114 | void **this_cache, | |
1115 | int regnum, int *optimizedp, | |
1116 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
c6826062 | 1117 | int *realnump, gdb_byte *valuep) |
acd5c798 MK |
1118 | { |
1119 | /* Make sure we've initialized the cache. */ | |
1120 | i386_sigtramp_frame_cache (next_frame, this_cache); | |
1121 | ||
1122 | i386_frame_prev_register (next_frame, this_cache, regnum, | |
1123 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c | 1124 | } |
c0d1d883 | 1125 | |
acd5c798 MK |
1126 | static const struct frame_unwind i386_sigtramp_frame_unwind = |
1127 | { | |
1128 | SIGTRAMP_FRAME, | |
1129 | i386_sigtramp_frame_this_id, | |
1130 | i386_sigtramp_frame_prev_register | |
1131 | }; | |
1132 | ||
1133 | static const struct frame_unwind * | |
336d1bba | 1134 | i386_sigtramp_frame_sniffer (struct frame_info *next_frame) |
acd5c798 | 1135 | { |
911bc6ee | 1136 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame)); |
acd5c798 | 1137 | |
911bc6ee MK |
1138 | /* We shouldn't even bother if we don't have a sigcontext_addr |
1139 | handler. */ | |
1140 | if (tdep->sigcontext_addr == NULL) | |
1c3545ae MK |
1141 | return NULL; |
1142 | ||
911bc6ee MK |
1143 | if (tdep->sigtramp_p != NULL) |
1144 | { | |
1145 | if (tdep->sigtramp_p (next_frame)) | |
1146 | return &i386_sigtramp_frame_unwind; | |
1147 | } | |
1148 | ||
1149 | if (tdep->sigtramp_start != 0) | |
1150 | { | |
1151 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1152 | ||
1153 | gdb_assert (tdep->sigtramp_end != 0); | |
1154 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
1155 | return &i386_sigtramp_frame_unwind; | |
1156 | } | |
acd5c798 MK |
1157 | |
1158 | return NULL; | |
1159 | } | |
1160 | \f | |
1161 | ||
1162 | static CORE_ADDR | |
1163 | i386_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1164 | { | |
1165 | struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache); | |
1166 | ||
1167 | return cache->base; | |
1168 | } | |
1169 | ||
1170 | static const struct frame_base i386_frame_base = | |
1171 | { | |
1172 | &i386_frame_unwind, | |
1173 | i386_frame_base_address, | |
1174 | i386_frame_base_address, | |
1175 | i386_frame_base_address | |
1176 | }; | |
1177 | ||
acd5c798 MK |
1178 | static struct frame_id |
1179 | i386_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1180 | { | |
63c0089f | 1181 | gdb_byte buf[4]; |
acd5c798 MK |
1182 | CORE_ADDR fp; |
1183 | ||
1184 | frame_unwind_register (next_frame, I386_EBP_REGNUM, buf); | |
1185 | fp = extract_unsigned_integer (buf, 4); | |
1186 | ||
3e210248 | 1187 | /* See the end of i386_push_dummy_call. */ |
acd5c798 | 1188 | return frame_id_build (fp + 8, frame_pc_unwind (next_frame)); |
c0d1d883 | 1189 | } |
fc338970 | 1190 | \f |
c906108c | 1191 | |
fc338970 MK |
1192 | /* Figure out where the longjmp will land. Slurp the args out of the |
1193 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 1194 | structure from which we extract the address that we will land at. |
28bcfd30 | 1195 | This address is copied into PC. This routine returns non-zero on |
acd5c798 MK |
1196 | success. |
1197 | ||
1198 | This function is 64-bit safe. */ | |
c906108c | 1199 | |
8201327c MK |
1200 | static int |
1201 | i386_get_longjmp_target (CORE_ADDR *pc) | |
c906108c | 1202 | { |
63c0089f | 1203 | gdb_byte buf[8]; |
c906108c | 1204 | CORE_ADDR sp, jb_addr; |
8201327c | 1205 | int jb_pc_offset = gdbarch_tdep (current_gdbarch)->jb_pc_offset; |
f9d3c2a8 | 1206 | int len = TYPE_LENGTH (builtin_type_void_func_ptr); |
c906108c | 1207 | |
8201327c MK |
1208 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
1209 | longjmp will land. */ | |
1210 | if (jb_pc_offset == -1) | |
c906108c SS |
1211 | return 0; |
1212 | ||
f837910f MK |
1213 | /* Don't use I386_ESP_REGNUM here, since this function is also used |
1214 | for AMD64. */ | |
1215 | regcache_cooked_read (current_regcache, SP_REGNUM, buf); | |
1216 | sp = extract_typed_address (buf, builtin_type_void_data_ptr); | |
28bcfd30 | 1217 | if (target_read_memory (sp + len, buf, len)) |
c906108c SS |
1218 | return 0; |
1219 | ||
f837910f | 1220 | jb_addr = extract_typed_address (buf, builtin_type_void_data_ptr); |
28bcfd30 | 1221 | if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) |
8201327c | 1222 | return 0; |
c906108c | 1223 | |
f9d3c2a8 | 1224 | *pc = extract_typed_address (buf, builtin_type_void_func_ptr); |
c906108c SS |
1225 | return 1; |
1226 | } | |
fc338970 | 1227 | \f |
c906108c | 1228 | |
3a1e71e3 | 1229 | static CORE_ADDR |
7d9b040b | 1230 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
1231 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
1232 | struct value **args, CORE_ADDR sp, int struct_return, | |
1233 | CORE_ADDR struct_addr) | |
22f8ba57 | 1234 | { |
63c0089f | 1235 | gdb_byte buf[4]; |
acd5c798 MK |
1236 | int i; |
1237 | ||
1238 | /* Push arguments in reverse order. */ | |
1239 | for (i = nargs - 1; i >= 0; i--) | |
22f8ba57 | 1240 | { |
4754a64e | 1241 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); |
acd5c798 MK |
1242 | |
1243 | /* The System V ABI says that: | |
1244 | ||
1245 | "An argument's size is increased, if necessary, to make it a | |
1246 | multiple of [32-bit] words. This may require tail padding, | |
1247 | depending on the size of the argument." | |
1248 | ||
1249 | This makes sure the stack says word-aligned. */ | |
1250 | sp -= (len + 3) & ~3; | |
46615f07 | 1251 | write_memory (sp, value_contents_all (args[i]), len); |
acd5c798 | 1252 | } |
22f8ba57 | 1253 | |
acd5c798 MK |
1254 | /* Push value address. */ |
1255 | if (struct_return) | |
1256 | { | |
22f8ba57 | 1257 | sp -= 4; |
fbd9dcd3 | 1258 | store_unsigned_integer (buf, 4, struct_addr); |
22f8ba57 MK |
1259 | write_memory (sp, buf, 4); |
1260 | } | |
1261 | ||
acd5c798 MK |
1262 | /* Store return address. */ |
1263 | sp -= 4; | |
6a65450a | 1264 | store_unsigned_integer (buf, 4, bp_addr); |
acd5c798 MK |
1265 | write_memory (sp, buf, 4); |
1266 | ||
1267 | /* Finally, update the stack pointer... */ | |
1268 | store_unsigned_integer (buf, 4, sp); | |
1269 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); | |
1270 | ||
1271 | /* ...and fake a frame pointer. */ | |
1272 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
1273 | ||
3e210248 AC |
1274 | /* MarkK wrote: This "+ 8" is all over the place: |
1275 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
1276 | i386_unwind_dummy_id). It's there, since all frame unwinders for | |
1277 | a given target have to agree (within a certain margin) on the | |
fd35795f | 1278 | definition of the stack address of a frame. Otherwise |
3e210248 AC |
1279 | frame_id_inner() won't work correctly. Since DWARF2/GCC uses the |
1280 | stack address *before* the function call as a frame's CFA. On | |
1281 | the i386, when %ebp is used as a frame pointer, the offset | |
1282 | between the contents %ebp and the CFA as defined by GCC. */ | |
1283 | return sp + 8; | |
22f8ba57 MK |
1284 | } |
1285 | ||
1a309862 MK |
1286 | /* These registers are used for returning integers (and on some |
1287 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 1288 | size and alignment match an integer type). */ |
acd5c798 MK |
1289 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
1290 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 1291 | |
c5e656c1 MK |
1292 | /* Read, for architecture GDBARCH, a function return value of TYPE |
1293 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 1294 | |
3a1e71e3 | 1295 | static void |
c5e656c1 | 1296 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1297 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 1298 | { |
c5e656c1 | 1299 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 1300 | int len = TYPE_LENGTH (type); |
63c0089f | 1301 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 1302 | |
1e8d0a7b | 1303 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 1304 | { |
5716833c | 1305 | if (tdep->st0_regnum < 0) |
1a309862 | 1306 | { |
8a3fe4f8 | 1307 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 1308 | memset (valbuf, 0, len); |
ef9dff19 | 1309 | return; |
1a309862 MK |
1310 | } |
1311 | ||
c6ba6f0d MK |
1312 | /* Floating-point return values can be found in %st(0). Convert |
1313 | its contents to the desired type. This is probably not | |
1314 | exactly how it would happen on the target itself, but it is | |
1315 | the best we can do. */ | |
acd5c798 | 1316 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
00f8375e | 1317 | convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type); |
c906108c SS |
1318 | } |
1319 | else | |
c5aa993b | 1320 | { |
f837910f MK |
1321 | int low_size = register_size (current_gdbarch, LOW_RETURN_REGNUM); |
1322 | int high_size = register_size (current_gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
1323 | |
1324 | if (len <= low_size) | |
00f8375e | 1325 | { |
0818c12a | 1326 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
1327 | memcpy (valbuf, buf, len); |
1328 | } | |
d4f3574e SS |
1329 | else if (len <= (low_size + high_size)) |
1330 | { | |
0818c12a | 1331 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 1332 | memcpy (valbuf, buf, low_size); |
0818c12a | 1333 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 1334 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
1335 | } |
1336 | else | |
8e65ff28 | 1337 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1338 | _("Cannot extract return value of %d bytes long."), len); |
c906108c SS |
1339 | } |
1340 | } | |
1341 | ||
c5e656c1 MK |
1342 | /* Write, for architecture GDBARCH, a function return value of TYPE |
1343 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 1344 | |
3a1e71e3 | 1345 | static void |
c5e656c1 | 1346 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 1347 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 1348 | { |
c5e656c1 | 1349 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
1350 | int len = TYPE_LENGTH (type); |
1351 | ||
5716833c MK |
1352 | /* Define I387_ST0_REGNUM such that we use the proper definitions |
1353 | for the architecture. */ | |
1354 | #define I387_ST0_REGNUM I386_ST0_REGNUM | |
1355 | ||
1e8d0a7b | 1356 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 1357 | { |
3d7f4f49 | 1358 | ULONGEST fstat; |
63c0089f | 1359 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 1360 | |
5716833c | 1361 | if (tdep->st0_regnum < 0) |
ef9dff19 | 1362 | { |
8a3fe4f8 | 1363 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
1364 | return; |
1365 | } | |
1366 | ||
635b0cc1 MK |
1367 | /* Returning floating-point values is a bit tricky. Apart from |
1368 | storing the return value in %st(0), we have to simulate the | |
1369 | state of the FPU at function return point. */ | |
1370 | ||
c6ba6f0d MK |
1371 | /* Convert the value found in VALBUF to the extended |
1372 | floating-point format used by the FPU. This is probably | |
1373 | not exactly how it would happen on the target itself, but | |
1374 | it is the best we can do. */ | |
1375 | convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext); | |
acd5c798 | 1376 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 1377 | |
635b0cc1 MK |
1378 | /* Set the top of the floating-point register stack to 7. The |
1379 | actual value doesn't really matter, but 7 is what a normal | |
1380 | function return would end up with if the program started out | |
1381 | with a freshly initialized FPU. */ | |
5716833c | 1382 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM, &fstat); |
ccb945b8 | 1383 | fstat |= (7 << 11); |
5716833c | 1384 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM, fstat); |
ccb945b8 | 1385 | |
635b0cc1 MK |
1386 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
1387 | the floating-point register stack to 7, the appropriate value | |
1388 | for the tag word is 0x3fff. */ | |
5716833c | 1389 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM, 0x3fff); |
ef9dff19 MK |
1390 | } |
1391 | else | |
1392 | { | |
f837910f MK |
1393 | int low_size = register_size (current_gdbarch, LOW_RETURN_REGNUM); |
1394 | int high_size = register_size (current_gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
1395 | |
1396 | if (len <= low_size) | |
3d7f4f49 | 1397 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
1398 | else if (len <= (low_size + high_size)) |
1399 | { | |
3d7f4f49 MK |
1400 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
1401 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 1402 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
1403 | } |
1404 | else | |
8e65ff28 | 1405 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1406 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 | 1407 | } |
5716833c MK |
1408 | |
1409 | #undef I387_ST0_REGNUM | |
ef9dff19 | 1410 | } |
fc338970 | 1411 | \f |
ef9dff19 | 1412 | |
8201327c MK |
1413 | /* This is the variable that is set with "set struct-convention", and |
1414 | its legitimate values. */ | |
1415 | static const char default_struct_convention[] = "default"; | |
1416 | static const char pcc_struct_convention[] = "pcc"; | |
1417 | static const char reg_struct_convention[] = "reg"; | |
1418 | static const char *valid_conventions[] = | |
1419 | { | |
1420 | default_struct_convention, | |
1421 | pcc_struct_convention, | |
1422 | reg_struct_convention, | |
1423 | NULL | |
1424 | }; | |
1425 | static const char *struct_convention = default_struct_convention; | |
1426 | ||
0e4377e1 JB |
1427 | /* Return non-zero if TYPE, which is assumed to be a structure, |
1428 | a union type, or an array type, should be returned in registers | |
1429 | for architecture GDBARCH. */ | |
c5e656c1 | 1430 | |
8201327c | 1431 | static int |
c5e656c1 | 1432 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 1433 | { |
c5e656c1 MK |
1434 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1435 | enum type_code code = TYPE_CODE (type); | |
1436 | int len = TYPE_LENGTH (type); | |
8201327c | 1437 | |
0e4377e1 JB |
1438 | gdb_assert (code == TYPE_CODE_STRUCT |
1439 | || code == TYPE_CODE_UNION | |
1440 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
1441 | |
1442 | if (struct_convention == pcc_struct_convention | |
1443 | || (struct_convention == default_struct_convention | |
1444 | && tdep->struct_return == pcc_struct_return)) | |
1445 | return 0; | |
1446 | ||
9edde48e MK |
1447 | /* Structures consisting of a single `float', `double' or 'long |
1448 | double' member are returned in %st(0). */ | |
1449 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
1450 | { | |
1451 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1452 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1453 | return (len == 4 || len == 8 || len == 12); | |
1454 | } | |
1455 | ||
c5e656c1 MK |
1456 | return (len == 1 || len == 2 || len == 4 || len == 8); |
1457 | } | |
1458 | ||
1459 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
1460 | should be returned. If it is supposed to be returned in registers, | |
1461 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
1462 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
1463 | from WRITEBUF into REGCACHE. */ | |
1464 | ||
1465 | static enum return_value_convention | |
1466 | i386_return_value (struct gdbarch *gdbarch, struct type *type, | |
42835c2b MK |
1467 | struct regcache *regcache, gdb_byte *readbuf, |
1468 | const gdb_byte *writebuf) | |
c5e656c1 MK |
1469 | { |
1470 | enum type_code code = TYPE_CODE (type); | |
1471 | ||
0e4377e1 JB |
1472 | if ((code == TYPE_CODE_STRUCT |
1473 | || code == TYPE_CODE_UNION | |
1474 | || code == TYPE_CODE_ARRAY) | |
c5e656c1 | 1475 | && !i386_reg_struct_return_p (gdbarch, type)) |
31db7b6c MK |
1476 | { |
1477 | /* The System V ABI says that: | |
1478 | ||
1479 | "A function that returns a structure or union also sets %eax | |
1480 | to the value of the original address of the caller's area | |
1481 | before it returns. Thus when the caller receives control | |
1482 | again, the address of the returned object resides in register | |
1483 | %eax and can be used to access the object." | |
1484 | ||
1485 | So the ABI guarantees that we can always find the return | |
1486 | value just after the function has returned. */ | |
1487 | ||
0e4377e1 JB |
1488 | /* Note that the ABI doesn't mention functions returning arrays, |
1489 | which is something possible in certain languages such as Ada. | |
1490 | In this case, the value is returned as if it was wrapped in | |
1491 | a record, so the convention applied to records also applies | |
1492 | to arrays. */ | |
1493 | ||
31db7b6c MK |
1494 | if (readbuf) |
1495 | { | |
1496 | ULONGEST addr; | |
1497 | ||
1498 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
1499 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1500 | } | |
1501 | ||
1502 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
1503 | } | |
c5e656c1 MK |
1504 | |
1505 | /* This special case is for structures consisting of a single | |
9edde48e MK |
1506 | `float', `double' or 'long double' member. These structures are |
1507 | returned in %st(0). For these structures, we call ourselves | |
1508 | recursively, changing TYPE into the type of the first member of | |
1509 | the structure. Since that should work for all structures that | |
1510 | have only one member, we don't bother to check the member's type | |
1511 | here. */ | |
c5e656c1 MK |
1512 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
1513 | { | |
1514 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
1515 | return i386_return_value (gdbarch, type, regcache, readbuf, writebuf); | |
1516 | } | |
1517 | ||
1518 | if (readbuf) | |
1519 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
1520 | if (writebuf) | |
1521 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 1522 | |
c5e656c1 | 1523 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
1524 | } |
1525 | \f | |
1526 | ||
21b4b2f2 JB |
1527 | /* Types for the MMX and SSE registers. */ |
1528 | static struct type *i386_mmx_type; | |
1529 | static struct type *i386_sse_type; | |
1530 | ||
1531 | /* Construct the type for MMX registers. */ | |
1532 | static struct type * | |
1533 | i386_build_mmx_type (void) | |
1534 | { | |
1535 | /* The type we're building is this: */ | |
1536 | #if 0 | |
1537 | union __gdb_builtin_type_vec64i | |
1538 | { | |
1539 | int64_t uint64; | |
1540 | int32_t v2_int32[2]; | |
1541 | int16_t v4_int16[4]; | |
1542 | int8_t v8_int8[8]; | |
1543 | }; | |
1544 | #endif | |
1545 | ||
1546 | if (! i386_mmx_type) | |
1547 | { | |
1548 | struct type *t; | |
1549 | ||
1550 | t = init_composite_type ("__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
1551 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
1552 | append_composite_type_field (t, "v2_int32", builtin_type_v2_int32); | |
1553 | append_composite_type_field (t, "v4_int16", builtin_type_v4_int16); | |
1554 | append_composite_type_field (t, "v8_int8", builtin_type_v8_int8); | |
1555 | ||
1556 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
1557 | TYPE_NAME (t) = "builtin_type_vec64i"; | |
1558 | ||
1559 | i386_mmx_type = t; | |
1560 | } | |
1561 | ||
1562 | return i386_mmx_type; | |
1563 | } | |
1564 | ||
1565 | /* Construct the type for SSE registers. */ | |
1566 | static struct type * | |
1567 | i386_build_sse_type (void) | |
1568 | { | |
1569 | if (! i386_sse_type) | |
1570 | { | |
1571 | struct type *t; | |
1572 | ||
1573 | t = init_composite_type ("__gdb_builtin_type_vec128i", TYPE_CODE_UNION); | |
1574 | append_composite_type_field (t, "v4_float", builtin_type_v4_float); | |
1575 | append_composite_type_field (t, "v2_double", builtin_type_v2_double); | |
1576 | append_composite_type_field (t, "v16_int8", builtin_type_v16_int8); | |
1577 | append_composite_type_field (t, "v8_int16", builtin_type_v8_int16); | |
1578 | append_composite_type_field (t, "v4_int32", builtin_type_v4_int32); | |
1579 | append_composite_type_field (t, "v2_int64", builtin_type_v2_int64); | |
1580 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
1581 | ||
1582 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
1583 | TYPE_NAME (t) = "builtin_type_vec128i"; | |
1584 | ||
1585 | i386_sse_type = t; | |
1586 | } | |
1587 | ||
1588 | return i386_sse_type; | |
1589 | } | |
1590 | ||
d7a0d72c MK |
1591 | /* Return the GDB type object for the "standard" data type of data in |
1592 | register REGNUM. Perhaps %esi and %edi should go here, but | |
1593 | potentially they could be used for things other than address. */ | |
1594 | ||
3a1e71e3 | 1595 | static struct type * |
4e259f09 | 1596 | i386_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 1597 | { |
ab533587 MK |
1598 | if (regnum == I386_EIP_REGNUM) |
1599 | return builtin_type_void_func_ptr; | |
1600 | ||
1601 | if (regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM) | |
1602 | return builtin_type_void_data_ptr; | |
d7a0d72c | 1603 | |
23a34459 | 1604 | if (i386_fp_regnum_p (regnum)) |
c6ba6f0d | 1605 | return builtin_type_i387_ext; |
d7a0d72c | 1606 | |
5716833c | 1607 | if (i386_sse_regnum_p (gdbarch, regnum)) |
21b4b2f2 | 1608 | return i386_build_sse_type (); |
d7a0d72c | 1609 | |
5716833c | 1610 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
21b4b2f2 | 1611 | return i386_build_mmx_type (); |
28fc6740 | 1612 | |
d7a0d72c MK |
1613 | return builtin_type_int; |
1614 | } | |
1615 | ||
28fc6740 | 1616 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 1617 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
1618 | |
1619 | static int | |
c86c27af | 1620 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 1621 | { |
5716833c MK |
1622 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
1623 | int mmxreg, fpreg; | |
28fc6740 AC |
1624 | ULONGEST fstat; |
1625 | int tos; | |
c86c27af | 1626 | |
5716833c MK |
1627 | /* Define I387_ST0_REGNUM such that we use the proper definitions |
1628 | for REGCACHE's architecture. */ | |
1629 | #define I387_ST0_REGNUM tdep->st0_regnum | |
1630 | ||
1631 | mmxreg = regnum - tdep->mm0_regnum; | |
1632 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM, &fstat); | |
28fc6740 | 1633 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
1634 | fpreg = (mmxreg + tos) % 8; |
1635 | ||
1636 | return (I387_ST0_REGNUM + fpreg); | |
c86c27af | 1637 | |
5716833c | 1638 | #undef I387_ST0_REGNUM |
28fc6740 AC |
1639 | } |
1640 | ||
1641 | static void | |
1642 | i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 1643 | int regnum, gdb_byte *buf) |
28fc6740 | 1644 | { |
5716833c | 1645 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 1646 | { |
63c0089f | 1647 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
1648 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
1649 | ||
28fc6740 | 1650 | /* Extract (always little endian). */ |
c86c27af | 1651 | regcache_raw_read (regcache, fpnum, mmx_buf); |
f837910f | 1652 | memcpy (buf, mmx_buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
1653 | } |
1654 | else | |
1655 | regcache_raw_read (regcache, regnum, buf); | |
1656 | } | |
1657 | ||
1658 | static void | |
1659 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
42835c2b | 1660 | int regnum, const gdb_byte *buf) |
28fc6740 | 1661 | { |
5716833c | 1662 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 1663 | { |
63c0089f | 1664 | gdb_byte mmx_buf[MAX_REGISTER_SIZE]; |
c86c27af MK |
1665 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
1666 | ||
28fc6740 AC |
1667 | /* Read ... */ |
1668 | regcache_raw_read (regcache, fpnum, mmx_buf); | |
1669 | /* ... Modify ... (always little endian). */ | |
f837910f | 1670 | memcpy (mmx_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 AC |
1671 | /* ... Write. */ |
1672 | regcache_raw_write (regcache, fpnum, mmx_buf); | |
1673 | } | |
1674 | else | |
1675 | regcache_raw_write (regcache, regnum, buf); | |
1676 | } | |
ff2e87ac AC |
1677 | \f |
1678 | ||
ff2e87ac AC |
1679 | /* Return the register number of the register allocated by GCC after |
1680 | REGNUM, or -1 if there is no such register. */ | |
1681 | ||
1682 | static int | |
1683 | i386_next_regnum (int regnum) | |
1684 | { | |
1685 | /* GCC allocates the registers in the order: | |
1686 | ||
1687 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
1688 | ||
1689 | Since storing a variable in %esp doesn't make any sense we return | |
1690 | -1 for %ebp and for %esp itself. */ | |
1691 | static int next_regnum[] = | |
1692 | { | |
1693 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
1694 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
1695 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
1696 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
1697 | -1, -1, /* Slots for %esp and %ebp. */ | |
1698 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
1699 | I386_EBP_REGNUM /* Slot for %edi. */ | |
1700 | }; | |
1701 | ||
de5b9bb9 | 1702 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 1703 | return next_regnum[regnum]; |
28fc6740 | 1704 | |
ff2e87ac AC |
1705 | return -1; |
1706 | } | |
1707 | ||
1708 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
1709 | needs any special handling. */ | |
d7a0d72c | 1710 | |
3a1e71e3 | 1711 | static int |
ff2e87ac | 1712 | i386_convert_register_p (int regnum, struct type *type) |
d7a0d72c | 1713 | { |
de5b9bb9 MK |
1714 | int len = TYPE_LENGTH (type); |
1715 | ||
ff2e87ac AC |
1716 | /* Values may be spread across multiple registers. Most debugging |
1717 | formats aren't expressive enough to specify the locations, so | |
1718 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
1719 | have a length that is a multiple of the word size, since GCC |
1720 | doesn't seem to put any other types into registers. */ | |
1721 | if (len > 4 && len % 4 == 0) | |
1722 | { | |
1723 | int last_regnum = regnum; | |
1724 | ||
1725 | while (len > 4) | |
1726 | { | |
1727 | last_regnum = i386_next_regnum (last_regnum); | |
1728 | len -= 4; | |
1729 | } | |
1730 | ||
1731 | if (last_regnum != -1) | |
1732 | return 1; | |
1733 | } | |
ff2e87ac | 1734 | |
23a34459 | 1735 | return i386_fp_regnum_p (regnum); |
d7a0d72c MK |
1736 | } |
1737 | ||
ff2e87ac AC |
1738 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
1739 | return its contents in TO. */ | |
ac27f131 | 1740 | |
3a1e71e3 | 1741 | static void |
ff2e87ac | 1742 | i386_register_to_value (struct frame_info *frame, int regnum, |
42835c2b | 1743 | struct type *type, gdb_byte *to) |
ac27f131 | 1744 | { |
de5b9bb9 | 1745 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 1746 | |
ff2e87ac AC |
1747 | /* FIXME: kettenis/20030609: What should we do if REGNUM isn't |
1748 | available in FRAME (i.e. if it wasn't saved)? */ | |
3d261580 | 1749 | |
ff2e87ac | 1750 | if (i386_fp_regnum_p (regnum)) |
8d7f6b4a | 1751 | { |
d532c08f MK |
1752 | i387_register_to_value (frame, regnum, type, to); |
1753 | return; | |
8d7f6b4a | 1754 | } |
ff2e87ac | 1755 | |
fd35795f | 1756 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
1757 | |
1758 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 1759 | |
de5b9bb9 MK |
1760 | while (len > 0) |
1761 | { | |
1762 | gdb_assert (regnum != -1); | |
1763 | gdb_assert (register_size (current_gdbarch, regnum) == 4); | |
d532c08f | 1764 | |
42835c2b | 1765 | get_frame_register (frame, regnum, to); |
de5b9bb9 MK |
1766 | regnum = i386_next_regnum (regnum); |
1767 | len -= 4; | |
42835c2b | 1768 | to += 4; |
de5b9bb9 | 1769 | } |
ac27f131 MK |
1770 | } |
1771 | ||
ff2e87ac AC |
1772 | /* Write the contents FROM of a value of type TYPE into register |
1773 | REGNUM in frame FRAME. */ | |
ac27f131 | 1774 | |
3a1e71e3 | 1775 | static void |
ff2e87ac | 1776 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 1777 | struct type *type, const gdb_byte *from) |
ac27f131 | 1778 | { |
de5b9bb9 | 1779 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 1780 | |
ff2e87ac | 1781 | if (i386_fp_regnum_p (regnum)) |
c6ba6f0d | 1782 | { |
d532c08f MK |
1783 | i387_value_to_register (frame, regnum, type, from); |
1784 | return; | |
1785 | } | |
3d261580 | 1786 | |
fd35795f | 1787 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
1788 | |
1789 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 1790 | |
de5b9bb9 MK |
1791 | while (len > 0) |
1792 | { | |
1793 | gdb_assert (regnum != -1); | |
1794 | gdb_assert (register_size (current_gdbarch, regnum) == 4); | |
d532c08f | 1795 | |
42835c2b | 1796 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
1797 | regnum = i386_next_regnum (regnum); |
1798 | len -= 4; | |
42835c2b | 1799 | from += 4; |
de5b9bb9 | 1800 | } |
ac27f131 | 1801 | } |
ff2e87ac | 1802 | \f |
7fdafb5a MK |
1803 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
1804 | in the general-purpose register set REGSET to register cache | |
1805 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 1806 | |
20187ed5 | 1807 | void |
473f17b0 MK |
1808 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
1809 | int regnum, const void *gregs, size_t len) | |
1810 | { | |
9ea75c57 | 1811 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
156cdbee | 1812 | const gdb_byte *regs = gregs; |
473f17b0 MK |
1813 | int i; |
1814 | ||
1815 | gdb_assert (len == tdep->sizeof_gregset); | |
1816 | ||
1817 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
1818 | { | |
1819 | if ((regnum == i || regnum == -1) | |
1820 | && tdep->gregset_reg_offset[i] != -1) | |
1821 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
1822 | } | |
1823 | } | |
1824 | ||
7fdafb5a MK |
1825 | /* Collect register REGNUM from the register cache REGCACHE and store |
1826 | it in the buffer specified by GREGS and LEN as described by the | |
1827 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
1828 | all registers in REGSET. */ | |
1829 | ||
1830 | void | |
1831 | i386_collect_gregset (const struct regset *regset, | |
1832 | const struct regcache *regcache, | |
1833 | int regnum, void *gregs, size_t len) | |
1834 | { | |
1835 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
156cdbee | 1836 | gdb_byte *regs = gregs; |
7fdafb5a MK |
1837 | int i; |
1838 | ||
1839 | gdb_assert (len == tdep->sizeof_gregset); | |
1840 | ||
1841 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
1842 | { | |
1843 | if ((regnum == i || regnum == -1) | |
1844 | && tdep->gregset_reg_offset[i] != -1) | |
1845 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
1846 | } | |
1847 | } | |
1848 | ||
1849 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
1850 | in the floating-point register set REGSET to register cache | |
1851 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
1852 | |
1853 | static void | |
1854 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
1855 | int regnum, const void *fpregs, size_t len) | |
1856 | { | |
9ea75c57 | 1857 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); |
473f17b0 | 1858 | |
66a72d25 MK |
1859 | if (len == I387_SIZEOF_FXSAVE) |
1860 | { | |
1861 | i387_supply_fxsave (regcache, regnum, fpregs); | |
1862 | return; | |
1863 | } | |
1864 | ||
473f17b0 MK |
1865 | gdb_assert (len == tdep->sizeof_fpregset); |
1866 | i387_supply_fsave (regcache, regnum, fpregs); | |
1867 | } | |
8446b36a | 1868 | |
2f305df1 MK |
1869 | /* Collect register REGNUM from the register cache REGCACHE and store |
1870 | it in the buffer specified by FPREGS and LEN as described by the | |
1871 | floating-point register set REGSET. If REGNUM is -1, do this for | |
1872 | all registers in REGSET. */ | |
7fdafb5a MK |
1873 | |
1874 | static void | |
1875 | i386_collect_fpregset (const struct regset *regset, | |
1876 | const struct regcache *regcache, | |
1877 | int regnum, void *fpregs, size_t len) | |
1878 | { | |
1879 | const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); | |
1880 | ||
1881 | if (len == I387_SIZEOF_FXSAVE) | |
1882 | { | |
1883 | i387_collect_fxsave (regcache, regnum, fpregs); | |
1884 | return; | |
1885 | } | |
1886 | ||
1887 | gdb_assert (len == tdep->sizeof_fpregset); | |
1888 | i387_collect_fsave (regcache, regnum, fpregs); | |
1889 | } | |
1890 | ||
8446b36a MK |
1891 | /* Return the appropriate register set for the core section identified |
1892 | by SECT_NAME and SECT_SIZE. */ | |
1893 | ||
1894 | const struct regset * | |
1895 | i386_regset_from_core_section (struct gdbarch *gdbarch, | |
1896 | const char *sect_name, size_t sect_size) | |
1897 | { | |
1898 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1899 | ||
1900 | if (strcmp (sect_name, ".reg") == 0 && sect_size == tdep->sizeof_gregset) | |
1901 | { | |
1902 | if (tdep->gregset == NULL) | |
7fdafb5a MK |
1903 | tdep->gregset = regset_alloc (gdbarch, i386_supply_gregset, |
1904 | i386_collect_gregset); | |
8446b36a MK |
1905 | return tdep->gregset; |
1906 | } | |
1907 | ||
66a72d25 MK |
1908 | if ((strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) |
1909 | || (strcmp (sect_name, ".reg-xfp") == 0 | |
1910 | && sect_size == I387_SIZEOF_FXSAVE)) | |
8446b36a MK |
1911 | { |
1912 | if (tdep->fpregset == NULL) | |
7fdafb5a MK |
1913 | tdep->fpregset = regset_alloc (gdbarch, i386_supply_fpregset, |
1914 | i386_collect_fpregset); | |
8446b36a MK |
1915 | return tdep->fpregset; |
1916 | } | |
1917 | ||
1918 | return NULL; | |
1919 | } | |
473f17b0 | 1920 | \f |
fc338970 | 1921 | |
c906108c | 1922 | #ifdef STATIC_TRANSFORM_NAME |
fc338970 MK |
1923 | /* SunPRO encodes the static variables. This is not related to C++ |
1924 | mangling, it is done for C too. */ | |
c906108c SS |
1925 | |
1926 | char * | |
fba45db2 | 1927 | sunpro_static_transform_name (char *name) |
c906108c SS |
1928 | { |
1929 | char *p; | |
1930 | if (IS_STATIC_TRANSFORM_NAME (name)) | |
1931 | { | |
fc338970 MK |
1932 | /* For file-local statics there will be a period, a bunch of |
1933 | junk (the contents of which match a string given in the | |
c5aa993b JM |
1934 | N_OPT), a period and the name. For function-local statics |
1935 | there will be a bunch of junk (which seems to change the | |
1936 | second character from 'A' to 'B'), a period, the name of the | |
1937 | function, and the name. So just skip everything before the | |
1938 | last period. */ | |
c906108c SS |
1939 | p = strrchr (name, '.'); |
1940 | if (p != NULL) | |
1941 | name = p + 1; | |
1942 | } | |
1943 | return name; | |
1944 | } | |
1945 | #endif /* STATIC_TRANSFORM_NAME */ | |
fc338970 | 1946 | \f |
c906108c | 1947 | |
fc338970 | 1948 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
1949 | |
1950 | CORE_ADDR | |
1cce71eb | 1951 | i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name) |
c906108c | 1952 | { |
fc338970 | 1953 | if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */ |
c906108c | 1954 | { |
c5aa993b | 1955 | unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4); |
c906108c | 1956 | struct minimal_symbol *indsym = |
fc338970 | 1957 | indirect ? lookup_minimal_symbol_by_pc (indirect) : 0; |
645dd519 | 1958 | char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 1959 | |
c5aa993b | 1960 | if (symname) |
c906108c | 1961 | { |
c5aa993b JM |
1962 | if (strncmp (symname, "__imp_", 6) == 0 |
1963 | || strncmp (symname, "_imp_", 5) == 0) | |
c906108c SS |
1964 | return name ? 1 : read_memory_unsigned_integer (indirect, 4); |
1965 | } | |
1966 | } | |
fc338970 | 1967 | return 0; /* Not a trampoline. */ |
c906108c | 1968 | } |
fc338970 MK |
1969 | \f |
1970 | ||
377d9ebd | 1971 | /* Return whether the frame preceding NEXT_FRAME corresponds to a |
911bc6ee | 1972 | sigtramp routine. */ |
8201327c MK |
1973 | |
1974 | static int | |
911bc6ee | 1975 | i386_sigtramp_p (struct frame_info *next_frame) |
8201327c | 1976 | { |
911bc6ee MK |
1977 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
1978 | char *name; | |
1979 | ||
1980 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
1981 | return (name && strcmp ("_sigtramp", name) == 0); |
1982 | } | |
1983 | \f | |
1984 | ||
fc338970 MK |
1985 | /* We have two flavours of disassembly. The machinery on this page |
1986 | deals with switching between those. */ | |
c906108c SS |
1987 | |
1988 | static int | |
a89aa300 | 1989 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 1990 | { |
5e3397bb MK |
1991 | gdb_assert (disassembly_flavor == att_flavor |
1992 | || disassembly_flavor == intel_flavor); | |
1993 | ||
1994 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
1995 | constified, cast to prevent a compiler warning. */ | |
1996 | info->disassembler_options = (char *) disassembly_flavor; | |
1997 | info->mach = gdbarch_bfd_arch_info (current_gdbarch)->mach; | |
1998 | ||
1999 | return print_insn_i386 (pc, info); | |
7a292a7a | 2000 | } |
fc338970 | 2001 | \f |
3ce1502b | 2002 | |
8201327c MK |
2003 | /* There are a few i386 architecture variants that differ only |
2004 | slightly from the generic i386 target. For now, we don't give them | |
2005 | their own source file, but include them here. As a consequence, | |
2006 | they'll always be included. */ | |
3ce1502b | 2007 | |
8201327c | 2008 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2009 | |
377d9ebd | 2010 | /* Return whether the frame preceding NEXT_FRAME corresponds to a SVR4 |
911bc6ee MK |
2011 | sigtramp routine. */ |
2012 | ||
8201327c | 2013 | static int |
911bc6ee | 2014 | i386_svr4_sigtramp_p (struct frame_info *next_frame) |
d2a7c97a | 2015 | { |
911bc6ee MK |
2016 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
2017 | char *name; | |
2018 | ||
acd5c798 MK |
2019 | /* UnixWare uses _sigacthandler. The origin of the other symbols is |
2020 | currently unknown. */ | |
911bc6ee | 2021 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c MK |
2022 | return (name && (strcmp ("_sigreturn", name) == 0 |
2023 | || strcmp ("_sigacthandler", name) == 0 | |
2024 | || strcmp ("sigvechandler", name) == 0)); | |
2025 | } | |
d2a7c97a | 2026 | |
acd5c798 MK |
2027 | /* Assuming NEXT_FRAME is for a frame following a SVR4 sigtramp |
2028 | routine, return the address of the associated sigcontext (ucontext) | |
2029 | structure. */ | |
3ce1502b | 2030 | |
3a1e71e3 | 2031 | static CORE_ADDR |
acd5c798 | 2032 | i386_svr4_sigcontext_addr (struct frame_info *next_frame) |
8201327c | 2033 | { |
63c0089f | 2034 | gdb_byte buf[4]; |
acd5c798 | 2035 | CORE_ADDR sp; |
3ce1502b | 2036 | |
acd5c798 MK |
2037 | frame_unwind_register (next_frame, I386_ESP_REGNUM, buf); |
2038 | sp = extract_unsigned_integer (buf, 4); | |
21d0e8a4 | 2039 | |
acd5c798 | 2040 | return read_memory_unsigned_integer (sp + 8, 4); |
8201327c MK |
2041 | } |
2042 | \f | |
3ce1502b | 2043 | |
8201327c | 2044 | /* Generic ELF. */ |
d2a7c97a | 2045 | |
8201327c MK |
2046 | void |
2047 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2048 | { | |
c4fc7f1b MK |
2049 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
2050 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
8201327c | 2051 | } |
3ce1502b | 2052 | |
8201327c | 2053 | /* System V Release 4 (SVR4). */ |
3ce1502b | 2054 | |
8201327c MK |
2055 | void |
2056 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
2057 | { | |
2058 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 2059 | |
8201327c MK |
2060 | /* System V Release 4 uses ELF. */ |
2061 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 2062 | |
dfe01d39 | 2063 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
2064 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
2065 | ||
911bc6ee | 2066 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 2067 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
2068 | tdep->sc_pc_offset = 36 + 14 * 4; |
2069 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 2070 | |
8201327c | 2071 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
2072 | } |
2073 | ||
8201327c | 2074 | /* DJGPP. */ |
3ce1502b | 2075 | |
3a1e71e3 | 2076 | static void |
8201327c | 2077 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2078 | { |
8201327c | 2079 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2080 | |
911bc6ee MK |
2081 | /* DJGPP doesn't have any special frames for signal handlers. */ |
2082 | tdep->sigtramp_p = NULL; | |
3ce1502b | 2083 | |
8201327c | 2084 | tdep->jb_pc_offset = 36; |
3ce1502b MK |
2085 | } |
2086 | ||
8201327c | 2087 | /* NetWare. */ |
3ce1502b | 2088 | |
3a1e71e3 | 2089 | static void |
8201327c | 2090 | i386_nw_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 2091 | { |
8201327c | 2092 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 2093 | |
8201327c | 2094 | tdep->jb_pc_offset = 24; |
d2a7c97a | 2095 | } |
8201327c | 2096 | \f |
2acceee2 | 2097 | |
38c968cf AC |
2098 | /* i386 register groups. In addition to the normal groups, add "mmx" |
2099 | and "sse". */ | |
2100 | ||
2101 | static struct reggroup *i386_sse_reggroup; | |
2102 | static struct reggroup *i386_mmx_reggroup; | |
2103 | ||
2104 | static void | |
2105 | i386_init_reggroups (void) | |
2106 | { | |
2107 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
2108 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
2109 | } | |
2110 | ||
2111 | static void | |
2112 | i386_add_reggroups (struct gdbarch *gdbarch) | |
2113 | { | |
2114 | reggroup_add (gdbarch, i386_sse_reggroup); | |
2115 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
2116 | reggroup_add (gdbarch, general_reggroup); | |
2117 | reggroup_add (gdbarch, float_reggroup); | |
2118 | reggroup_add (gdbarch, all_reggroup); | |
2119 | reggroup_add (gdbarch, save_reggroup); | |
2120 | reggroup_add (gdbarch, restore_reggroup); | |
2121 | reggroup_add (gdbarch, vector_reggroup); | |
2122 | reggroup_add (gdbarch, system_reggroup); | |
2123 | } | |
2124 | ||
2125 | int | |
2126 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2127 | struct reggroup *group) | |
2128 | { | |
5716833c MK |
2129 | int sse_regnum_p = (i386_sse_regnum_p (gdbarch, regnum) |
2130 | || i386_mxcsr_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
2131 | int fp_regnum_p = (i386_fp_regnum_p (regnum) |
2132 | || i386_fpc_regnum_p (regnum)); | |
5716833c | 2133 | int mmx_regnum_p = (i386_mmx_regnum_p (gdbarch, regnum)); |
acd5c798 | 2134 | |
38c968cf AC |
2135 | if (group == i386_mmx_reggroup) |
2136 | return mmx_regnum_p; | |
2137 | if (group == i386_sse_reggroup) | |
2138 | return sse_regnum_p; | |
2139 | if (group == vector_reggroup) | |
2140 | return (mmx_regnum_p || sse_regnum_p); | |
2141 | if (group == float_reggroup) | |
2142 | return fp_regnum_p; | |
2143 | if (group == general_reggroup) | |
2144 | return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p); | |
acd5c798 | 2145 | |
38c968cf AC |
2146 | return default_register_reggroup_p (gdbarch, regnum, group); |
2147 | } | |
38c968cf | 2148 | \f |
acd5c798 | 2149 | |
f837910f MK |
2150 | /* Get the ARGIth function argument for the current function. */ |
2151 | ||
42c466d7 | 2152 | static CORE_ADDR |
143985b7 AF |
2153 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
2154 | struct type *type) | |
2155 | { | |
f837910f MK |
2156 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
2157 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4); | |
143985b7 AF |
2158 | } |
2159 | ||
2160 | \f | |
3a1e71e3 | 2161 | static struct gdbarch * |
a62cc96e AC |
2162 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
2163 | { | |
cd3c07fc | 2164 | struct gdbarch_tdep *tdep; |
a62cc96e AC |
2165 | struct gdbarch *gdbarch; |
2166 | ||
4be87837 DJ |
2167 | /* If there is already a candidate, use it. */ |
2168 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2169 | if (arches != NULL) | |
2170 | return arches->gdbarch; | |
a62cc96e AC |
2171 | |
2172 | /* Allocate space for the new architecture. */ | |
2173 | tdep = XMALLOC (struct gdbarch_tdep); | |
2174 | gdbarch = gdbarch_alloc (&info, tdep); | |
2175 | ||
473f17b0 MK |
2176 | /* General-purpose registers. */ |
2177 | tdep->gregset = NULL; | |
2178 | tdep->gregset_reg_offset = NULL; | |
2179 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
2180 | tdep->sizeof_gregset = 0; | |
2181 | ||
2182 | /* Floating-point registers. */ | |
2183 | tdep->fpregset = NULL; | |
2184 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; | |
2185 | ||
5716833c | 2186 | /* The default settings include the FPU registers, the MMX registers |
fd35795f | 2187 | and the SSE registers. This can be overridden for a specific ABI |
5716833c MK |
2188 | by adjusting the members `st0_regnum', `mm0_regnum' and |
2189 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
2190 | will show up in the output of "info all-registers". Ideally we | |
2191 | should try to autodetect whether they are available, such that we | |
2192 | can prevent "info all-registers" from displaying registers that | |
2193 | aren't available. | |
2194 | ||
2195 | NOTE: kevinb/2003-07-13: ... if it's a choice between printing | |
2196 | [the SSE registers] always (even when they don't exist) or never | |
2197 | showing them to the user (even when they do exist), I prefer the | |
2198 | former over the latter. */ | |
2199 | ||
2200 | tdep->st0_regnum = I386_ST0_REGNUM; | |
2201 | ||
2202 | /* The MMX registers are implemented as pseudo-registers. Put off | |
fd35795f | 2203 | calculating the register number for %mm0 until we know the number |
5716833c MK |
2204 | of raw registers. */ |
2205 | tdep->mm0_regnum = 0; | |
2206 | ||
2207 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ | |
49ed40de | 2208 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; |
d2a7c97a | 2209 | |
8201327c MK |
2210 | tdep->jb_pc_offset = -1; |
2211 | tdep->struct_return = pcc_struct_return; | |
8201327c MK |
2212 | tdep->sigtramp_start = 0; |
2213 | tdep->sigtramp_end = 0; | |
911bc6ee | 2214 | tdep->sigtramp_p = i386_sigtramp_p; |
21d0e8a4 | 2215 | tdep->sigcontext_addr = NULL; |
a3386186 | 2216 | tdep->sc_reg_offset = NULL; |
8201327c | 2217 | tdep->sc_pc_offset = -1; |
21d0e8a4 | 2218 | tdep->sc_sp_offset = -1; |
8201327c | 2219 | |
896fb97d MK |
2220 | /* The format used for `long double' on almost all i386 targets is |
2221 | the i387 extended floating-point format. In fact, of all targets | |
2222 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
2223 | on having a `long double' that's not `long' at all. */ | |
2224 | set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext); | |
21d0e8a4 | 2225 | |
66da5fd8 | 2226 | /* Although the i387 extended floating-point has only 80 significant |
896fb97d MK |
2227 | bits, a `long double' actually takes up 96, probably to enforce |
2228 | alignment. */ | |
2229 | set_gdbarch_long_double_bit (gdbarch, 96); | |
2230 | ||
49ed40de KB |
2231 | /* The default ABI includes general-purpose registers, |
2232 | floating-point registers, and the SSE registers. */ | |
2233 | set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); | |
acd5c798 MK |
2234 | set_gdbarch_register_name (gdbarch, i386_register_name); |
2235 | set_gdbarch_register_type (gdbarch, i386_register_type); | |
21d0e8a4 | 2236 | |
acd5c798 MK |
2237 | /* Register numbers of various important registers. */ |
2238 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
2239 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
2240 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
2241 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
356a6b3e | 2242 | |
c4fc7f1b MK |
2243 | /* NOTE: kettenis/20040418: GCC does have two possible register |
2244 | numbering schemes on the i386: dbx and SVR4. These schemes | |
2245 | differ in how they number %ebp, %esp, %eflags, and the | |
fd35795f | 2246 | floating-point registers, and are implemented by the arrays |
c4fc7f1b MK |
2247 | dbx_register_map[] and svr4_dbx_register_map in |
2248 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
2249 | gcc/config/i386.c, which it designates as the "default" register | |
2250 | map used in 64bit mode. This last register numbering scheme is | |
d4dc1a91 | 2251 | implemented in dbx64_register_map, and is used for AMD64; see |
c4fc7f1b MK |
2252 | amd64-tdep.c. |
2253 | ||
2254 | Currently, each GCC i386 target always uses the same register | |
2255 | numbering scheme across all its supported debugging formats | |
2256 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
2257 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
2258 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
2259 | respective config header in a manner independent of the requested | |
2260 | output debugging format. | |
2261 | ||
2262 | This does not match the arrangement below, which presumes that | |
2263 | the SDB and stabs numbering schemes differ from the DWARF and | |
2264 | DWARF 2 ones. The reason for this arrangement is that it is | |
2265 | likely to get the numbering scheme for the target's | |
2266 | default/native debug format right. For targets where GCC is the | |
2267 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
2268 | targets where the native toolchain uses a different numbering | |
2269 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
d4dc1a91 BF |
2270 | the defaults below will have to be overridden, like |
2271 | i386_elf_init_abi() does. */ | |
c4fc7f1b MK |
2272 | |
2273 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
2274 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2275 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
2276 | ||
2277 | /* Use the SVR4 register numbering scheme for DWARF and DWARF 2. */ | |
2278 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
2279 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
356a6b3e MK |
2280 | |
2281 | /* We don't define ECOFF_REG_TO_REGNUM, since ECOFF doesn't seem to | |
2282 | be in use on any of the supported i386 targets. */ | |
2283 | ||
61113f8b MK |
2284 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); |
2285 | ||
8201327c | 2286 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); |
96297dab | 2287 | |
a62cc96e | 2288 | /* Call dummy code. */ |
acd5c798 | 2289 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
a62cc96e | 2290 | |
ff2e87ac AC |
2291 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); |
2292 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
2293 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
b6197528 | 2294 | |
c5e656c1 | 2295 | set_gdbarch_return_value (gdbarch, i386_return_value); |
8201327c | 2296 | |
93924b6b MK |
2297 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); |
2298 | ||
2299 | /* Stack grows downward. */ | |
2300 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2301 | ||
2302 | set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); | |
2303 | set_gdbarch_decr_pc_after_break (gdbarch, 1); | |
42fdc8df | 2304 | |
42fdc8df | 2305 | set_gdbarch_frame_args_skip (gdbarch, 8); |
8201327c | 2306 | |
28fc6740 | 2307 | /* Wire in the MMX registers. */ |
0f751ff2 | 2308 | set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); |
28fc6740 AC |
2309 | set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); |
2310 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); | |
2311 | ||
5e3397bb MK |
2312 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
2313 | ||
acd5c798 | 2314 | set_gdbarch_unwind_dummy_id (gdbarch, i386_unwind_dummy_id); |
acd5c798 MK |
2315 | |
2316 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
2317 | ||
38c968cf AC |
2318 | /* Add the i386 register groups. */ |
2319 | i386_add_reggroups (gdbarch); | |
2320 | set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); | |
2321 | ||
143985b7 AF |
2322 | /* Helper for function argument information. */ |
2323 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
2324 | ||
6405b0a6 | 2325 | /* Hook in the DWARF CFI frame unwinder. */ |
336d1bba | 2326 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
6405b0a6 | 2327 | |
acd5c798 | 2328 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 2329 | |
3ce1502b | 2330 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2331 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 2332 | |
336d1bba AC |
2333 | frame_unwind_append_sniffer (gdbarch, i386_sigtramp_frame_sniffer); |
2334 | frame_unwind_append_sniffer (gdbarch, i386_frame_sniffer); | |
acd5c798 | 2335 | |
8446b36a MK |
2336 | /* If we have a register mapping, enable the generic core file |
2337 | support, unless it has already been enabled. */ | |
2338 | if (tdep->gregset_reg_offset | |
2339 | && !gdbarch_regset_from_core_section_p (gdbarch)) | |
2340 | set_gdbarch_regset_from_core_section (gdbarch, | |
2341 | i386_regset_from_core_section); | |
2342 | ||
5716833c MK |
2343 | /* Unless support for MMX has been disabled, make %mm0 the first |
2344 | pseudo-register. */ | |
2345 | if (tdep->mm0_regnum == 0) | |
2346 | tdep->mm0_regnum = gdbarch_num_regs (gdbarch); | |
2347 | ||
a62cc96e AC |
2348 | return gdbarch; |
2349 | } | |
2350 | ||
8201327c MK |
2351 | static enum gdb_osabi |
2352 | i386_coff_osabi_sniffer (bfd *abfd) | |
2353 | { | |
762c5349 MK |
2354 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
2355 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
2356 | return GDB_OSABI_GO32; |
2357 | ||
2358 | return GDB_OSABI_UNKNOWN; | |
2359 | } | |
2360 | ||
2361 | static enum gdb_osabi | |
2362 | i386_nlm_osabi_sniffer (bfd *abfd) | |
2363 | { | |
2364 | return GDB_OSABI_NETWARE; | |
2365 | } | |
2366 | \f | |
2367 | ||
28e9e0f0 MK |
2368 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
2369 | void _initialize_i386_tdep (void); | |
2370 | ||
c906108c | 2371 | void |
fba45db2 | 2372 | _initialize_i386_tdep (void) |
c906108c | 2373 | { |
a62cc96e AC |
2374 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
2375 | ||
fc338970 | 2376 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
2377 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
2378 | &disassembly_flavor, _("\ | |
2379 | Set the disassembly flavor."), _("\ | |
2380 | Show the disassembly flavor."), _("\ | |
2381 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
2382 | NULL, | |
2383 | NULL, /* FIXME: i18n: */ | |
2384 | &setlist, &showlist); | |
8201327c MK |
2385 | |
2386 | /* Add the variable that controls the convention for returning | |
2387 | structs. */ | |
7ab04401 AC |
2388 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
2389 | &struct_convention, _("\ | |
2390 | Set the convention for returning small structs."), _("\ | |
2391 | Show the convention for returning small structs."), _("\ | |
2392 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
2393 | is \"default\"."), | |
2394 | NULL, | |
2395 | NULL, /* FIXME: i18n: */ | |
2396 | &setlist, &showlist); | |
8201327c MK |
2397 | |
2398 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, | |
2399 | i386_coff_osabi_sniffer); | |
2400 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_nlm_flavour, | |
2401 | i386_nlm_osabi_sniffer); | |
2402 | ||
05816f70 | 2403 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 2404 | i386_svr4_init_abi); |
05816f70 | 2405 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 2406 | i386_go32_init_abi); |
05816f70 | 2407 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_NETWARE, |
8201327c | 2408 | i386_nw_init_abi); |
38c968cf AC |
2409 | |
2410 | /* Initialize the i386 specific register groups. */ | |
2411 | i386_init_reggroups (); | |
c906108c | 2412 | } |