Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
b811d2c2 | 3 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
82ca8957 | 25 | #include "dwarf2/frame.h" |
c906108c | 26 | #include "frame.h" |
acd5c798 MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
c906108c | 29 | #include "inferior.h" |
45741a9c | 30 | #include "infrun.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
3b2ca824 | 42 | #include "target-float.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
268a13a5 | 49 | #include "gdbsupport/x86-xstate.h" |
1d509aa6 | 50 | #include "x86-tdep.h" |
d2a7c97a | 51 | |
7ad10968 | 52 | #include "record.h" |
d02ed0bb | 53 | #include "record-full.h" |
22916b07 YQ |
54 | #include "target-descriptions.h" |
55 | #include "arch/i386.h" | |
90884b2b | 56 | |
6710bf39 SS |
57 | #include "ax.h" |
58 | #include "ax-gdb.h" | |
59 | ||
55aa24fb SDJ |
60 | #include "stap-probe.h" |
61 | #include "user-regs.h" | |
62 | #include "cli/cli-utils.h" | |
63 | #include "expression.h" | |
64 | #include "parser-defs.h" | |
65 | #include <ctype.h> | |
325fac50 | 66 | #include <algorithm> |
7d7571f0 | 67 | #include <unordered_set> |
c2fd7fae | 68 | #include "producer.h" |
55aa24fb | 69 | |
c4fc7f1b | 70 | /* Register names. */ |
c40e1eab | 71 | |
27087b7f | 72 | static const char * const i386_register_names[] = |
fc633446 MK |
73 | { |
74 | "eax", "ecx", "edx", "ebx", | |
75 | "esp", "ebp", "esi", "edi", | |
76 | "eip", "eflags", "cs", "ss", | |
77 | "ds", "es", "fs", "gs", | |
78 | "st0", "st1", "st2", "st3", | |
79 | "st4", "st5", "st6", "st7", | |
80 | "fctrl", "fstat", "ftag", "fiseg", | |
81 | "fioff", "foseg", "fooff", "fop", | |
82 | "xmm0", "xmm1", "xmm2", "xmm3", | |
83 | "xmm4", "xmm5", "xmm6", "xmm7", | |
84 | "mxcsr" | |
85 | }; | |
86 | ||
27087b7f | 87 | static const char * const i386_zmm_names[] = |
01f9f808 MS |
88 | { |
89 | "zmm0", "zmm1", "zmm2", "zmm3", | |
90 | "zmm4", "zmm5", "zmm6", "zmm7" | |
91 | }; | |
92 | ||
27087b7f | 93 | static const char * const i386_zmmh_names[] = |
01f9f808 MS |
94 | { |
95 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
96 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
97 | }; | |
98 | ||
27087b7f | 99 | static const char * const i386_k_names[] = |
01f9f808 MS |
100 | { |
101 | "k0", "k1", "k2", "k3", | |
102 | "k4", "k5", "k6", "k7" | |
103 | }; | |
104 | ||
27087b7f | 105 | static const char * const i386_ymm_names[] = |
c131fcee L |
106 | { |
107 | "ymm0", "ymm1", "ymm2", "ymm3", | |
108 | "ymm4", "ymm5", "ymm6", "ymm7", | |
109 | }; | |
110 | ||
27087b7f | 111 | static const char * const i386_ymmh_names[] = |
c131fcee L |
112 | { |
113 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
114 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
115 | }; | |
116 | ||
27087b7f | 117 | static const char * const i386_mpx_names[] = |
1dbcd68c WT |
118 | { |
119 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
120 | }; | |
121 | ||
27087b7f | 122 | static const char * const i386_pkeys_names[] = |
51547df6 MS |
123 | { |
124 | "pkru" | |
125 | }; | |
126 | ||
1dbcd68c WT |
127 | /* Register names for MPX pseudo-registers. */ |
128 | ||
27087b7f | 129 | static const char * const i386_bnd_names[] = |
1dbcd68c WT |
130 | { |
131 | "bnd0", "bnd1", "bnd2", "bnd3" | |
132 | }; | |
133 | ||
c4fc7f1b | 134 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 135 | |
27087b7f | 136 | static const char * const i386_mmx_names[] = |
28fc6740 AC |
137 | { |
138 | "mm0", "mm1", "mm2", "mm3", | |
139 | "mm4", "mm5", "mm6", "mm7" | |
140 | }; | |
c40e1eab | 141 | |
1ba53b71 L |
142 | /* Register names for byte pseudo-registers. */ |
143 | ||
27087b7f | 144 | static const char * const i386_byte_names[] = |
1ba53b71 L |
145 | { |
146 | "al", "cl", "dl", "bl", | |
147 | "ah", "ch", "dh", "bh" | |
148 | }; | |
149 | ||
150 | /* Register names for word pseudo-registers. */ | |
151 | ||
27087b7f | 152 | static const char * const i386_word_names[] = |
1ba53b71 L |
153 | { |
154 | "ax", "cx", "dx", "bx", | |
9cad29ac | 155 | "", "bp", "si", "di" |
1ba53b71 L |
156 | }; |
157 | ||
01f9f808 MS |
158 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
159 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
160 | we have 16 upper ZMM regs that have to be handled differently. */ | |
161 | ||
162 | const int num_lower_zmm_regs = 16; | |
163 | ||
1ba53b71 | 164 | /* MMX register? */ |
c40e1eab | 165 | |
28fc6740 | 166 | static int |
5716833c | 167 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 168 | { |
1ba53b71 L |
169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
170 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
171 | |
172 | if (mm0_regnum < 0) | |
173 | return 0; | |
174 | ||
1ba53b71 L |
175 | regnum -= mm0_regnum; |
176 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
177 | } | |
178 | ||
179 | /* Byte register? */ | |
180 | ||
181 | int | |
182 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
183 | { | |
184 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
185 | ||
186 | regnum -= tdep->al_regnum; | |
187 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
188 | } | |
189 | ||
190 | /* Word register? */ | |
191 | ||
192 | int | |
193 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
194 | { | |
195 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
196 | ||
197 | regnum -= tdep->ax_regnum; | |
198 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
199 | } | |
200 | ||
201 | /* Dword register? */ | |
202 | ||
203 | int | |
204 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
205 | { | |
206 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
207 | int eax_regnum = tdep->eax_regnum; | |
208 | ||
209 | if (eax_regnum < 0) | |
210 | return 0; | |
211 | ||
212 | regnum -= eax_regnum; | |
213 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
214 | } |
215 | ||
01f9f808 MS |
216 | /* AVX512 register? */ |
217 | ||
218 | int | |
219 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
220 | { | |
221 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
222 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
223 | ||
224 | if (zmm0h_regnum < 0) | |
225 | return 0; | |
226 | ||
227 | regnum -= zmm0h_regnum; | |
228 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
229 | } | |
230 | ||
231 | int | |
232 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
233 | { | |
234 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
235 | int zmm0_regnum = tdep->zmm0_regnum; | |
236 | ||
237 | if (zmm0_regnum < 0) | |
238 | return 0; | |
239 | ||
240 | regnum -= zmm0_regnum; | |
241 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
242 | } | |
243 | ||
244 | int | |
245 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
246 | { | |
247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
248 | int k0_regnum = tdep->k0_regnum; | |
249 | ||
250 | if (k0_regnum < 0) | |
251 | return 0; | |
252 | ||
253 | regnum -= k0_regnum; | |
254 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
255 | } | |
256 | ||
9191d390 | 257 | static int |
c131fcee L |
258 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
259 | { | |
260 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
261 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
262 | ||
263 | if (ymm0h_regnum < 0) | |
264 | return 0; | |
265 | ||
266 | regnum -= ymm0h_regnum; | |
267 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
268 | } | |
269 | ||
270 | /* AVX register? */ | |
271 | ||
272 | int | |
273 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
274 | { | |
275 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
276 | int ymm0_regnum = tdep->ymm0_regnum; | |
277 | ||
278 | if (ymm0_regnum < 0) | |
279 | return 0; | |
280 | ||
281 | regnum -= ymm0_regnum; | |
282 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
283 | } | |
284 | ||
01f9f808 MS |
285 | static int |
286 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
287 | { | |
288 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
289 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
290 | ||
291 | if (ymm16h_regnum < 0) | |
292 | return 0; | |
293 | ||
294 | regnum -= ymm16h_regnum; | |
295 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
296 | } | |
297 | ||
298 | int | |
299 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
300 | { | |
301 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
302 | int ymm16_regnum = tdep->ymm16_regnum; | |
303 | ||
304 | if (ymm16_regnum < 0) | |
305 | return 0; | |
306 | ||
307 | regnum -= ymm16_regnum; | |
308 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
309 | } | |
310 | ||
1dbcd68c WT |
311 | /* BND register? */ |
312 | ||
313 | int | |
314 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
315 | { | |
316 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
317 | int bnd0_regnum = tdep->bnd0_regnum; | |
318 | ||
319 | if (bnd0_regnum < 0) | |
320 | return 0; | |
321 | ||
322 | regnum -= bnd0_regnum; | |
323 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
324 | } | |
325 | ||
5716833c | 326 | /* SSE register? */ |
23a34459 | 327 | |
c131fcee L |
328 | int |
329 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 330 | { |
5716833c | 331 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 332 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 333 | |
c131fcee | 334 | if (num_xmm_regs == 0) |
5716833c MK |
335 | return 0; |
336 | ||
c131fcee L |
337 | regnum -= I387_XMM0_REGNUM (tdep); |
338 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
339 | } |
340 | ||
01f9f808 MS |
341 | /* XMM_512 register? */ |
342 | ||
343 | int | |
344 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
345 | { | |
346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
347 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
348 | ||
349 | if (num_xmm_avx512_regs == 0) | |
350 | return 0; | |
351 | ||
352 | regnum -= I387_XMM16_REGNUM (tdep); | |
353 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
354 | } | |
355 | ||
5716833c MK |
356 | static int |
357 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 358 | { |
5716833c MK |
359 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
360 | ||
20a6ec49 | 361 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
362 | return 0; |
363 | ||
20a6ec49 | 364 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
365 | } |
366 | ||
5716833c | 367 | /* FP register? */ |
23a34459 AC |
368 | |
369 | int | |
20a6ec49 | 370 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 371 | { |
20a6ec49 MD |
372 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
373 | ||
374 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
375 | return 0; |
376 | ||
20a6ec49 MD |
377 | return (I387_ST0_REGNUM (tdep) <= regnum |
378 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
379 | } |
380 | ||
381 | int | |
20a6ec49 | 382 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 383 | { |
20a6ec49 MD |
384 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
385 | ||
386 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
387 | return 0; |
388 | ||
20a6ec49 MD |
389 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
390 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
391 | } |
392 | ||
1dbcd68c WT |
393 | /* BNDr (raw) register? */ |
394 | ||
395 | static int | |
396 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
397 | { | |
398 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
399 | ||
400 | if (I387_BND0R_REGNUM (tdep) < 0) | |
401 | return 0; | |
402 | ||
403 | regnum -= tdep->bnd0r_regnum; | |
404 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
405 | } | |
406 | ||
407 | /* BND control register? */ | |
408 | ||
409 | static int | |
410 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
411 | { | |
412 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
413 | ||
414 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
415 | return 0; | |
416 | ||
417 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
418 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
419 | } | |
420 | ||
51547df6 MS |
421 | /* PKRU register? */ |
422 | ||
423 | bool | |
424 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
425 | { | |
426 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
427 | int pkru_regnum = tdep->pkru_regnum; | |
428 | ||
429 | if (pkru_regnum < 0) | |
430 | return false; | |
431 | ||
432 | regnum -= pkru_regnum; | |
433 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
434 | } | |
435 | ||
c131fcee L |
436 | /* Return the name of register REGNUM, or the empty string if it is |
437 | an anonymous register. */ | |
438 | ||
439 | static const char * | |
440 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
441 | { | |
442 | /* Hide the upper YMM registers. */ | |
443 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
444 | return ""; | |
445 | ||
01f9f808 MS |
446 | /* Hide the upper YMM16-31 registers. */ |
447 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
448 | return ""; | |
449 | ||
450 | /* Hide the upper ZMM registers. */ | |
451 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
452 | return ""; | |
453 | ||
c131fcee L |
454 | return tdesc_register_name (gdbarch, regnum); |
455 | } | |
456 | ||
30b0e2d8 | 457 | /* Return the name of register REGNUM. */ |
fc633446 | 458 | |
1ba53b71 | 459 | const char * |
90884b2b | 460 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 461 | { |
1ba53b71 | 462 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
463 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
464 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
465 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
466 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
467 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
468 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
469 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
470 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
471 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
472 | return i386_byte_names[regnum - tdep->al_regnum]; | |
473 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
474 | return i386_word_names[regnum - tdep->ax_regnum]; | |
475 | ||
476 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
477 | } |
478 | ||
c4fc7f1b | 479 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
480 | number used by GDB. */ |
481 | ||
8201327c | 482 | static int |
d3f73121 | 483 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 484 | { |
20a6ec49 MD |
485 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
486 | ||
c4fc7f1b MK |
487 | /* This implements what GCC calls the "default" register map |
488 | (dbx_register_map[]). */ | |
489 | ||
85540d8c MK |
490 | if (reg >= 0 && reg <= 7) |
491 | { | |
9872ad24 | 492 | /* General-purpose registers. The debug info calls %ebp |
dda83cd7 | 493 | register 4, and %esp register 5. */ |
9872ad24 | 494 | if (reg == 4) |
dda83cd7 | 495 | return 5; |
9872ad24 | 496 | else if (reg == 5) |
dda83cd7 | 497 | return 4; |
9872ad24 | 498 | else return reg; |
85540d8c MK |
499 | } |
500 | else if (reg >= 12 && reg <= 19) | |
501 | { | |
502 | /* Floating-point registers. */ | |
20a6ec49 | 503 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
504 | } |
505 | else if (reg >= 21 && reg <= 28) | |
506 | { | |
507 | /* SSE registers. */ | |
c131fcee L |
508 | int ymm0_regnum = tdep->ymm0_regnum; |
509 | ||
510 | if (ymm0_regnum >= 0 | |
511 | && i386_xmm_regnum_p (gdbarch, reg)) | |
512 | return reg - 21 + ymm0_regnum; | |
513 | else | |
514 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
515 | } |
516 | else if (reg >= 29 && reg <= 36) | |
517 | { | |
518 | /* MMX registers. */ | |
20a6ec49 | 519 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
520 | } |
521 | ||
522 | /* This will hopefully provoke a warning. */ | |
f6efe3f8 | 523 | return gdbarch_num_cooked_regs (gdbarch); |
85540d8c MK |
524 | } |
525 | ||
0fde2c53 | 526 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 527 | used by GDB. */ |
85540d8c | 528 | |
8201327c | 529 | static int |
0fde2c53 | 530 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 531 | { |
20a6ec49 MD |
532 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
533 | ||
c4fc7f1b MK |
534 | /* This implements the GCC register map that tries to be compatible |
535 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
536 | ||
537 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
538 | numbers the floating point registers differently. */ |
539 | if (reg >= 0 && reg <= 9) | |
540 | { | |
acd5c798 | 541 | /* General-purpose registers. */ |
85540d8c MK |
542 | return reg; |
543 | } | |
544 | else if (reg >= 11 && reg <= 18) | |
545 | { | |
546 | /* Floating-point registers. */ | |
20a6ec49 | 547 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 548 | } |
c6f4c129 | 549 | else if (reg >= 21 && reg <= 36) |
85540d8c | 550 | { |
c4fc7f1b | 551 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 552 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
553 | } |
554 | ||
c6f4c129 JB |
555 | switch (reg) |
556 | { | |
20a6ec49 MD |
557 | case 37: return I387_FCTRL_REGNUM (tdep); |
558 | case 38: return I387_FSTAT_REGNUM (tdep); | |
559 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
560 | case 40: return I386_ES_REGNUM; |
561 | case 41: return I386_CS_REGNUM; | |
562 | case 42: return I386_SS_REGNUM; | |
563 | case 43: return I386_DS_REGNUM; | |
564 | case 44: return I386_FS_REGNUM; | |
565 | case 45: return I386_GS_REGNUM; | |
566 | } | |
567 | ||
0fde2c53 DE |
568 | return -1; |
569 | } | |
570 | ||
571 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
572 | num_regs + num_pseudo_regs for other debug formats. */ | |
573 | ||
8f10c932 | 574 | int |
0fde2c53 DE |
575 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
576 | { | |
577 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
578 | ||
579 | if (regnum == -1) | |
f6efe3f8 | 580 | return gdbarch_num_cooked_regs (gdbarch); |
0fde2c53 | 581 | return regnum; |
85540d8c | 582 | } |
5716833c | 583 | |
fc338970 | 584 | \f |
917317f4 | 585 | |
fc338970 MK |
586 | /* This is the variable that is set with "set disassembly-flavor", and |
587 | its legitimate values. */ | |
53904c9e AC |
588 | static const char att_flavor[] = "att"; |
589 | static const char intel_flavor[] = "intel"; | |
40478521 | 590 | static const char *const valid_flavors[] = |
c5aa993b | 591 | { |
c906108c SS |
592 | att_flavor, |
593 | intel_flavor, | |
594 | NULL | |
595 | }; | |
53904c9e | 596 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 597 | \f |
c906108c | 598 | |
acd5c798 MK |
599 | /* Use the program counter to determine the contents and size of a |
600 | breakpoint instruction. Return a pointer to a string of bytes that | |
601 | encode a breakpoint instruction, store the length of the string in | |
602 | *LEN and optionally adjust *PC to point to the correct memory | |
603 | location for inserting the breakpoint. | |
c906108c | 604 | |
acd5c798 MK |
605 | On the i386 we have a single breakpoint that fits in a single byte |
606 | and can be inserted anywhere. | |
c906108c | 607 | |
acd5c798 | 608 | This function is 64-bit safe. */ |
63c0089f | 609 | |
04180708 YQ |
610 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
611 | ||
612 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 613 | |
237fc4c9 PA |
614 | \f |
615 | /* Displaced instruction handling. */ | |
616 | ||
1903f0e6 DE |
617 | /* Skip the legacy instruction prefixes in INSN. |
618 | Not all prefixes are valid for any particular insn | |
619 | but we needn't care, the insn will fault if it's invalid. | |
620 | The result is a pointer to the first opcode byte, | |
621 | or NULL if we run off the end of the buffer. */ | |
622 | ||
623 | static gdb_byte * | |
624 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
625 | { | |
626 | gdb_byte *end = insn + max_len; | |
627 | ||
628 | while (insn < end) | |
629 | { | |
630 | switch (*insn) | |
631 | { | |
632 | case DATA_PREFIX_OPCODE: | |
633 | case ADDR_PREFIX_OPCODE: | |
634 | case CS_PREFIX_OPCODE: | |
635 | case DS_PREFIX_OPCODE: | |
636 | case ES_PREFIX_OPCODE: | |
637 | case FS_PREFIX_OPCODE: | |
638 | case GS_PREFIX_OPCODE: | |
639 | case SS_PREFIX_OPCODE: | |
640 | case LOCK_PREFIX_OPCODE: | |
641 | case REPE_PREFIX_OPCODE: | |
642 | case REPNE_PREFIX_OPCODE: | |
643 | ++insn; | |
644 | continue; | |
645 | default: | |
646 | return insn; | |
647 | } | |
648 | } | |
649 | ||
650 | return NULL; | |
651 | } | |
237fc4c9 PA |
652 | |
653 | static int | |
1903f0e6 | 654 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 655 | { |
1777feb0 | 656 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
657 | if (insn[0] == 0xea) |
658 | return 1; | |
659 | ||
660 | if (insn[0] == 0xff) | |
661 | { | |
1777feb0 | 662 | /* jump near, absolute indirect (/4). */ |
237fc4c9 | 663 | if ((insn[1] & 0x38) == 0x20) |
dda83cd7 | 664 | return 1; |
237fc4c9 | 665 | |
1777feb0 | 666 | /* jump far, absolute indirect (/5). */ |
237fc4c9 | 667 | if ((insn[1] & 0x38) == 0x28) |
dda83cd7 | 668 | return 1; |
237fc4c9 PA |
669 | } |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
c2170eef MM |
674 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
675 | ||
676 | static int | |
677 | i386_jmp_p (const gdb_byte *insn) | |
678 | { | |
679 | /* jump short, relative. */ | |
680 | if (insn[0] == 0xeb) | |
681 | return 1; | |
682 | ||
683 | /* jump near, relative. */ | |
684 | if (insn[0] == 0xe9) | |
685 | return 1; | |
686 | ||
687 | return i386_absolute_jmp_p (insn); | |
688 | } | |
689 | ||
237fc4c9 | 690 | static int |
1903f0e6 | 691 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 692 | { |
1777feb0 | 693 | /* call far, absolute. */ |
237fc4c9 PA |
694 | if (insn[0] == 0x9a) |
695 | return 1; | |
696 | ||
697 | if (insn[0] == 0xff) | |
698 | { | |
1777feb0 | 699 | /* Call near, absolute indirect (/2). */ |
237fc4c9 | 700 | if ((insn[1] & 0x38) == 0x10) |
dda83cd7 | 701 | return 1; |
237fc4c9 | 702 | |
1777feb0 | 703 | /* Call far, absolute indirect (/3). */ |
237fc4c9 | 704 | if ((insn[1] & 0x38) == 0x18) |
dda83cd7 | 705 | return 1; |
237fc4c9 PA |
706 | } |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | static int | |
1903f0e6 | 712 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
713 | { |
714 | switch (insn[0]) | |
715 | { | |
1777feb0 | 716 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 717 | case 0xc3: /* ret near */ |
1777feb0 | 718 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
719 | case 0xcb: /* ret far */ |
720 | case 0xcf: /* iret */ | |
721 | return 1; | |
722 | ||
723 | default: | |
724 | return 0; | |
725 | } | |
726 | } | |
727 | ||
728 | static int | |
1903f0e6 | 729 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
730 | { |
731 | if (i386_absolute_call_p (insn)) | |
732 | return 1; | |
733 | ||
1777feb0 | 734 | /* call near, relative. */ |
237fc4c9 PA |
735 | if (insn[0] == 0xe8) |
736 | return 1; | |
737 | ||
738 | return 0; | |
739 | } | |
740 | ||
237fc4c9 PA |
741 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
742 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 743 | |
237fc4c9 | 744 | static int |
b55078be | 745 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 746 | { |
9a7f938f JK |
747 | /* Is it 'int $0x80'? */ |
748 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
749 | /* Or is it 'sysenter'? */ | |
750 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
751 | /* Or is it 'syscall'? */ | |
752 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
753 | { |
754 | *lengthp = 2; | |
755 | return 1; | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
c2170eef MM |
761 | /* The gdbarch insn_is_call method. */ |
762 | ||
763 | static int | |
764 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
765 | { | |
766 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
767 | ||
768 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
769 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
770 | ||
771 | return i386_call_p (insn); | |
772 | } | |
773 | ||
774 | /* The gdbarch insn_is_ret method. */ | |
775 | ||
776 | static int | |
777 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
778 | { | |
779 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
780 | ||
781 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
782 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
783 | ||
784 | return i386_ret_p (insn); | |
785 | } | |
786 | ||
787 | /* The gdbarch insn_is_jump method. */ | |
788 | ||
789 | static int | |
790 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
791 | { | |
792 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
793 | ||
794 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
795 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
796 | ||
797 | return i386_jmp_p (insn); | |
798 | } | |
799 | ||
c2508e90 | 800 | /* Some kernels may run one past a syscall insn, so we have to cope. */ |
b55078be | 801 | |
1152d984 | 802 | displaced_step_copy_insn_closure_up |
b55078be DE |
803 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, |
804 | CORE_ADDR from, CORE_ADDR to, | |
805 | struct regcache *regs) | |
806 | { | |
807 | size_t len = gdbarch_max_insn_length (gdbarch); | |
1152d984 SM |
808 | std::unique_ptr<i386_displaced_step_copy_insn_closure> closure |
809 | (new i386_displaced_step_copy_insn_closure (len)); | |
cfba9872 | 810 | gdb_byte *buf = closure->buf.data (); |
b55078be DE |
811 | |
812 | read_memory (from, buf, len); | |
813 | ||
814 | /* GDB may get control back after the insn after the syscall. | |
815 | Presumably this is a kernel bug. | |
816 | If this is a syscall, make sure there's a nop afterwards. */ | |
817 | { | |
818 | int syscall_length; | |
819 | gdb_byte *insn; | |
820 | ||
821 | insn = i386_skip_prefixes (buf, len); | |
822 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
823 | insn[syscall_length] = NOP_OPCODE; | |
824 | } | |
825 | ||
826 | write_memory (to, buf, len); | |
827 | ||
136821d9 | 828 | displaced_debug_printf ("%s->%s: %s", |
dda83cd7 | 829 | paddress (gdbarch, from), paddress (gdbarch, to), |
136821d9 | 830 | displaced_step_dump_bytes (buf, len).c_str ()); |
b55078be | 831 | |
6d0cf446 | 832 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 833 | return displaced_step_copy_insn_closure_up (closure.release ()); |
b55078be DE |
834 | } |
835 | ||
237fc4c9 PA |
836 | /* Fix up the state of registers and memory after having single-stepped |
837 | a displaced instruction. */ | |
1903f0e6 | 838 | |
237fc4c9 PA |
839 | void |
840 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 841 | struct displaced_step_copy_insn_closure *closure_, |
dda83cd7 SM |
842 | CORE_ADDR from, CORE_ADDR to, |
843 | struct regcache *regs) | |
237fc4c9 | 844 | { |
e17a4113 UW |
845 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
846 | ||
237fc4c9 PA |
847 | /* The offset we applied to the instruction's address. |
848 | This could well be negative (when viewed as a signed 32-bit | |
849 | value), but ULONGEST won't reflect that, so take care when | |
850 | applying it. */ | |
851 | ULONGEST insn_offset = to - from; | |
852 | ||
1152d984 SM |
853 | i386_displaced_step_copy_insn_closure *closure |
854 | = (i386_displaced_step_copy_insn_closure *) closure_; | |
cfba9872 | 855 | gdb_byte *insn = closure->buf.data (); |
1903f0e6 DE |
856 | /* The start of the insn, needed in case we see some prefixes. */ |
857 | gdb_byte *insn_start = insn; | |
237fc4c9 | 858 | |
136821d9 SM |
859 | displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...", |
860 | paddress (gdbarch, from), paddress (gdbarch, to), | |
861 | insn[0], insn[1]); | |
237fc4c9 PA |
862 | |
863 | /* The list of issues to contend with here is taken from | |
864 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
865 | Yay for Free Software! */ | |
866 | ||
867 | /* Relocate the %eip, if necessary. */ | |
868 | ||
1903f0e6 DE |
869 | /* The instruction recognizers we use assume any leading prefixes |
870 | have been skipped. */ | |
871 | { | |
872 | /* This is the size of the buffer in closure. */ | |
873 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
874 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
875 | /* If there are too many prefixes, just ignore the insn. | |
876 | It will fault when run. */ | |
877 | if (opcode != NULL) | |
878 | insn = opcode; | |
879 | } | |
880 | ||
237fc4c9 PA |
881 | /* Except in the case of absolute or indirect jump or call |
882 | instructions, or a return instruction, the new eip is relative to | |
883 | the displaced instruction; make it relative. Well, signal | |
884 | handler returns don't need relocation either, but we use the | |
885 | value of %eip to recognize those; see below. */ | |
886 | if (! i386_absolute_jmp_p (insn) | |
887 | && ! i386_absolute_call_p (insn) | |
888 | && ! i386_ret_p (insn)) | |
889 | { | |
890 | ULONGEST orig_eip; | |
b55078be | 891 | int insn_len; |
237fc4c9 PA |
892 | |
893 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
894 | ||
895 | /* A signal trampoline system call changes the %eip, resuming | |
dda83cd7 SM |
896 | execution of the main program after the signal handler has |
897 | returned. That makes them like 'return' instructions; we | |
898 | shouldn't relocate %eip. | |
899 | ||
900 | But most system calls don't, and we do need to relocate %eip. | |
901 | ||
902 | Our heuristic for distinguishing these cases: if stepping | |
903 | over the system call instruction left control directly after | |
904 | the instruction, the we relocate --- control almost certainly | |
905 | doesn't belong in the displaced copy. Otherwise, we assume | |
906 | the instruction has put control where it belongs, and leave | |
907 | it unrelocated. Goodness help us if there are PC-relative | |
908 | system calls. */ | |
237fc4c9 | 909 | if (i386_syscall_p (insn, &insn_len) |
dda83cd7 | 910 | && orig_eip != to + (insn - insn_start) + insn_len |
b55078be DE |
911 | /* GDB can get control back after the insn after the syscall. |
912 | Presumably this is a kernel bug. | |
913 | i386_displaced_step_copy_insn ensures its a nop, | |
914 | we add one to the length for it. */ | |
136821d9 SM |
915 | && orig_eip != to + (insn - insn_start) + insn_len + 1) |
916 | displaced_debug_printf ("syscall changed %%eip; not relocating"); | |
237fc4c9 | 917 | else |
dda83cd7 SM |
918 | { |
919 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
237fc4c9 | 920 | |
1903f0e6 DE |
921 | /* If we just stepped over a breakpoint insn, we don't backup |
922 | the pc on purpose; this is to match behaviour without | |
923 | stepping. */ | |
237fc4c9 | 924 | |
dda83cd7 | 925 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); |
237fc4c9 | 926 | |
136821d9 SM |
927 | displaced_debug_printf ("relocated %%eip from %s to %s", |
928 | paddress (gdbarch, orig_eip), | |
929 | paddress (gdbarch, eip)); | |
dda83cd7 | 930 | } |
237fc4c9 PA |
931 | } |
932 | ||
933 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
934 | pushed value, and should be cleared. We'll leave this for later, | |
935 | since GDB already messes up the TF flag when stepping over a | |
936 | pushfl. */ | |
937 | ||
938 | /* If the instruction was a call, the return address now atop the | |
939 | stack is the address following the copied instruction. We need | |
940 | to make it the address following the original instruction. */ | |
941 | if (i386_call_p (insn)) | |
942 | { | |
943 | ULONGEST esp; | |
944 | ULONGEST retaddr; | |
945 | const ULONGEST retaddr_len = 4; | |
946 | ||
947 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 948 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 949 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 950 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 | 951 | |
136821d9 SM |
952 | displaced_debug_printf ("relocated return addr at %s to %s", |
953 | paddress (gdbarch, esp), | |
954 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
955 | } |
956 | } | |
dde08ee1 PA |
957 | |
958 | static void | |
959 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
960 | { | |
961 | target_write_memory (*to, buf, len); | |
962 | *to += len; | |
963 | } | |
964 | ||
965 | static void | |
966 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
967 | CORE_ADDR *to, CORE_ADDR oldloc) | |
968 | { | |
969 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
970 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
971 | int offset = 0, rel32, newrel; | |
972 | int insn_length; | |
973 | gdb_byte *insn = buf; | |
974 | ||
975 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
976 | ||
977 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
978 | I386_MAX_INSN_LEN, oldloc); | |
979 | ||
980 | /* Get past the prefixes. */ | |
981 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
982 | ||
983 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
984 | the address pushed being the location where the original call in | |
985 | the user program would return to. */ | |
986 | if (insn[0] == 0xe8) | |
987 | { | |
988 | gdb_byte push_buf[16]; | |
989 | unsigned int ret_addr; | |
990 | ||
991 | /* Where "ret" in the original code will return to. */ | |
992 | ret_addr = oldloc + insn_length; | |
1777feb0 | 993 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 994 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
995 | /* Push the push. */ |
996 | append_insns (to, 5, push_buf); | |
997 | ||
998 | /* Convert the relative call to a relative jump. */ | |
999 | insn[0] = 0xe9; | |
1000 | ||
1001 | /* Adjust the destination offset. */ | |
1002 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1003 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1004 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1005 | ||
136821d9 SM |
1006 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1007 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1008 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1009 | |
1010 | /* Write the adjusted jump into its displaced location. */ | |
1011 | append_insns (to, 5, insn); | |
1012 | return; | |
1013 | } | |
1014 | ||
1015 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1016 | handled above. */ | |
1017 | if (insn[0] == 0xe9) | |
1018 | offset = 1; | |
1019 | /* Adjust conditional jumps. */ | |
1020 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1021 | offset = 2; | |
1022 | ||
1023 | if (offset) | |
1024 | { | |
1025 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1026 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1027 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
136821d9 SM |
1028 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1029 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1030 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1031 | } |
1032 | ||
1033 | /* Write the adjusted instructions into their displaced | |
1034 | location. */ | |
1035 | append_insns (to, insn_length, buf); | |
1036 | } | |
1037 | ||
fc338970 | 1038 | \f |
acd5c798 MK |
1039 | #ifdef I386_REGNO_TO_SYMMETRY |
1040 | #error "The Sequent Symmetry is no longer supported." | |
1041 | #endif | |
c906108c | 1042 | |
acd5c798 MK |
1043 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1044 | and %esp "belong" to the calling function. Therefore these | |
1045 | registers should be saved if they're going to be modified. */ | |
c906108c | 1046 | |
acd5c798 MK |
1047 | /* The maximum number of saved registers. This should include all |
1048 | registers mentioned above, and %eip. */ | |
a3386186 | 1049 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1050 | |
1051 | struct i386_frame_cache | |
c906108c | 1052 | { |
acd5c798 MK |
1053 | /* Base address. */ |
1054 | CORE_ADDR base; | |
8fbca658 | 1055 | int base_p; |
772562f8 | 1056 | LONGEST sp_offset; |
acd5c798 MK |
1057 | CORE_ADDR pc; |
1058 | ||
fd13a04a AC |
1059 | /* Saved registers. */ |
1060 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1061 | CORE_ADDR saved_sp; |
e0c62198 | 1062 | int saved_sp_reg; |
acd5c798 MK |
1063 | int pc_in_eax; |
1064 | ||
1065 | /* Stack space reserved for local variables. */ | |
1066 | long locals; | |
1067 | }; | |
1068 | ||
1069 | /* Allocate and initialize a frame cache. */ | |
1070 | ||
1071 | static struct i386_frame_cache * | |
fd13a04a | 1072 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1073 | { |
1074 | struct i386_frame_cache *cache; | |
1075 | int i; | |
1076 | ||
1077 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1078 | ||
1079 | /* Base address. */ | |
8fbca658 | 1080 | cache->base_p = 0; |
acd5c798 MK |
1081 | cache->base = 0; |
1082 | cache->sp_offset = -4; | |
1083 | cache->pc = 0; | |
1084 | ||
fd13a04a AC |
1085 | /* Saved registers. We initialize these to -1 since zero is a valid |
1086 | offset (that's where %ebp is supposed to be stored). */ | |
1087 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1088 | cache->saved_regs[i] = -1; | |
acd5c798 | 1089 | cache->saved_sp = 0; |
e0c62198 | 1090 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1091 | cache->pc_in_eax = 0; |
1092 | ||
1093 | /* Frameless until proven otherwise. */ | |
1094 | cache->locals = -1; | |
1095 | ||
1096 | return cache; | |
1097 | } | |
c906108c | 1098 | |
acd5c798 MK |
1099 | /* If the instruction at PC is a jump, return the address of its |
1100 | target. Otherwise, return PC. */ | |
c906108c | 1101 | |
acd5c798 | 1102 | static CORE_ADDR |
e17a4113 | 1103 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1104 | { |
e17a4113 | 1105 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1106 | gdb_byte op; |
acd5c798 MK |
1107 | long delta = 0; |
1108 | int data16 = 0; | |
c906108c | 1109 | |
0865b04a | 1110 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1111 | return pc; |
1112 | ||
acd5c798 | 1113 | if (op == 0x66) |
c906108c | 1114 | { |
c906108c | 1115 | data16 = 1; |
0865b04a YQ |
1116 | |
1117 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1118 | } |
1119 | ||
acd5c798 | 1120 | switch (op) |
c906108c SS |
1121 | { |
1122 | case 0xe9: | |
fc338970 | 1123 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1124 | if (data16) |
1125 | { | |
e17a4113 | 1126 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1127 | |
fc338970 | 1128 | /* Include the size of the jmp instruction (including the |
dda83cd7 | 1129 | 0x66 prefix). */ |
acd5c798 | 1130 | delta += 4; |
c906108c SS |
1131 | } |
1132 | else | |
1133 | { | |
e17a4113 | 1134 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1135 | |
acd5c798 MK |
1136 | /* Include the size of the jmp instruction. */ |
1137 | delta += 5; | |
c906108c SS |
1138 | } |
1139 | break; | |
1140 | case 0xeb: | |
fc338970 | 1141 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1142 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1143 | |
acd5c798 | 1144 | delta += data16 + 2; |
c906108c SS |
1145 | break; |
1146 | } | |
c906108c | 1147 | |
acd5c798 MK |
1148 | return pc + delta; |
1149 | } | |
fc338970 | 1150 | |
acd5c798 MK |
1151 | /* Check whether PC points at a prologue for a function returning a |
1152 | structure or union. If so, it updates CACHE and returns the | |
1153 | address of the first instruction after the code sequence that | |
1154 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1155 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1156 | |
acd5c798 MK |
1157 | static CORE_ADDR |
1158 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1159 | struct i386_frame_cache *cache) | |
c906108c | 1160 | { |
acd5c798 MK |
1161 | /* Functions that return a structure or union start with: |
1162 | ||
dda83cd7 SM |
1163 | popl %eax 0x58 |
1164 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
acd5c798 MK |
1165 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 |
1166 | ||
1167 | (the System V compiler puts out the second `xchg' instruction, | |
1168 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1169 | gets generated). This sequence is used to get the address of the | |
1170 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1171 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1172 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1173 | gdb_byte buf[4]; | |
1174 | gdb_byte op; | |
c906108c | 1175 | |
acd5c798 MK |
1176 | if (current_pc <= pc) |
1177 | return pc; | |
1178 | ||
0865b04a | 1179 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1180 | return pc; |
c906108c | 1181 | |
acd5c798 MK |
1182 | if (op != 0x58) /* popl %eax */ |
1183 | return pc; | |
c906108c | 1184 | |
0865b04a | 1185 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1186 | return pc; |
1187 | ||
acd5c798 MK |
1188 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1189 | return pc; | |
c906108c | 1190 | |
acd5c798 | 1191 | if (current_pc == pc) |
c906108c | 1192 | { |
acd5c798 MK |
1193 | cache->sp_offset += 4; |
1194 | return current_pc; | |
c906108c SS |
1195 | } |
1196 | ||
acd5c798 | 1197 | if (current_pc == pc + 1) |
c906108c | 1198 | { |
acd5c798 MK |
1199 | cache->pc_in_eax = 1; |
1200 | return current_pc; | |
1201 | } | |
1202 | ||
1203 | if (buf[1] == proto1[1]) | |
1204 | return pc + 4; | |
1205 | else | |
1206 | return pc + 5; | |
1207 | } | |
1208 | ||
1209 | static CORE_ADDR | |
1210 | i386_skip_probe (CORE_ADDR pc) | |
1211 | { | |
1212 | /* A function may start with | |
fc338970 | 1213 | |
dda83cd7 SM |
1214 | pushl constant |
1215 | call _probe | |
acd5c798 | 1216 | addl $4, %esp |
fc338970 | 1217 | |
acd5c798 MK |
1218 | followed by |
1219 | ||
dda83cd7 | 1220 | pushl %ebp |
fc338970 | 1221 | |
acd5c798 | 1222 | etc. */ |
63c0089f MK |
1223 | gdb_byte buf[8]; |
1224 | gdb_byte op; | |
fc338970 | 1225 | |
0865b04a | 1226 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1227 | return pc; |
acd5c798 MK |
1228 | |
1229 | if (op == 0x68 || op == 0x6a) | |
1230 | { | |
1231 | int delta; | |
c906108c | 1232 | |
acd5c798 MK |
1233 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1234 | four-byte operand, depending on the opcode. */ | |
c906108c | 1235 | if (op == 0x68) |
acd5c798 | 1236 | delta = 5; |
c906108c | 1237 | else |
acd5c798 | 1238 | delta = 2; |
c906108c | 1239 | |
acd5c798 MK |
1240 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1241 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1242 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1243 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1244 | pc += delta + sizeof (buf); |
c906108c SS |
1245 | } |
1246 | ||
acd5c798 MK |
1247 | return pc; |
1248 | } | |
1249 | ||
92dd43fa MK |
1250 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1251 | stack pointer. Check whether PC points to such code, and update | |
1252 | CACHE accordingly. Return the first instruction after the code | |
1253 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1254 | recognize the code, return PC. */ | |
1255 | ||
1256 | static CORE_ADDR | |
1257 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1258 | struct i386_frame_cache *cache) | |
1259 | { | |
e0c62198 L |
1260 | /* There are 2 code sequences to re-align stack before the frame |
1261 | gets set up: | |
1262 | ||
1263 | 1. Use a caller-saved saved register: | |
1264 | ||
1265 | leal 4(%esp), %reg | |
1266 | andl $-XXX, %esp | |
1267 | pushl -4(%reg) | |
1268 | ||
1269 | 2. Use a callee-saved saved register: | |
1270 | ||
1271 | pushl %reg | |
1272 | leal 8(%esp), %reg | |
1273 | andl $-XXX, %esp | |
1274 | pushl -4(%reg) | |
1275 | ||
1276 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1277 | ||
1278 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1279 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1280 | */ | |
1281 | ||
1282 | gdb_byte buf[14]; | |
1283 | int reg; | |
1284 | int offset, offset_and; | |
1285 | static int regnums[8] = { | |
1286 | I386_EAX_REGNUM, /* %eax */ | |
1287 | I386_ECX_REGNUM, /* %ecx */ | |
1288 | I386_EDX_REGNUM, /* %edx */ | |
1289 | I386_EBX_REGNUM, /* %ebx */ | |
1290 | I386_ESP_REGNUM, /* %esp */ | |
1291 | I386_EBP_REGNUM, /* %ebp */ | |
1292 | I386_ESI_REGNUM, /* %esi */ | |
1293 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1294 | }; |
92dd43fa | 1295 | |
0865b04a | 1296 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1297 | return pc; |
1298 | ||
1299 | /* Check caller-saved saved register. The first instruction has | |
1300 | to be "leal 4(%esp), %reg". */ | |
1301 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1302 | { | |
1303 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1304 | if ((buf[1] & 0xc7) != 0x44) | |
1305 | return pc; | |
1306 | ||
1307 | /* REG has register number. */ | |
1308 | reg = (buf[1] >> 3) & 7; | |
1309 | offset = 4; | |
1310 | } | |
1311 | else | |
1312 | { | |
1313 | /* Check callee-saved saved register. The first instruction | |
1314 | has to be "pushl %reg". */ | |
1315 | if ((buf[0] & 0xf8) != 0x50) | |
1316 | return pc; | |
1317 | ||
1318 | /* Get register. */ | |
1319 | reg = buf[0] & 0x7; | |
1320 | ||
1321 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1322 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1323 | return pc; | |
1324 | ||
1325 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1326 | if ((buf[2] & 0xc7) != 0x44) | |
1327 | return pc; | |
1328 | ||
1329 | /* REG has register number. Registers in pushl and leal have to | |
1330 | be the same. */ | |
1331 | if (reg != ((buf[2] >> 3) & 7)) | |
1332 | return pc; | |
1333 | ||
1334 | offset = 5; | |
1335 | } | |
1336 | ||
1337 | /* Rigister can't be %esp nor %ebp. */ | |
1338 | if (reg == 4 || reg == 5) | |
1339 | return pc; | |
1340 | ||
1341 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1342 | if (buf[offset + 1] != 0xe4 | |
1343 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1344 | return pc; | |
1345 | ||
1346 | offset_and = offset; | |
1347 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1348 | ||
1349 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1350 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1351 | if (buf[offset] != 0xff | |
1352 | || buf[offset + 2] != 0xfc | |
1353 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1354 | return pc; | |
1355 | ||
1356 | /* R/M has register. Registers in leal and pushl have to be the | |
1357 | same. */ | |
1358 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1359 | return pc; |
1360 | ||
e0c62198 L |
1361 | if (current_pc > pc + offset_and) |
1362 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1363 | |
325fac50 | 1364 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1365 | } |
1366 | ||
37bdc87e | 1367 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1368 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1369 | |
1370 | /* Instruction description. */ | |
1371 | struct i386_insn | |
1372 | { | |
1373 | size_t len; | |
237fc4c9 PA |
1374 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1375 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1376 | }; |
1377 | ||
a3fcb948 | 1378 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1379 | |
a3fcb948 JG |
1380 | static int |
1381 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1382 | { |
63c0089f | 1383 | gdb_byte op; |
37bdc87e | 1384 | |
0865b04a | 1385 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1386 | return 0; |
37bdc87e | 1387 | |
a3fcb948 | 1388 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1389 | { |
a3fcb948 JG |
1390 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1391 | int insn_matched = 1; | |
1392 | size_t i; | |
37bdc87e | 1393 | |
a3fcb948 JG |
1394 | gdb_assert (pattern.len > 1); |
1395 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1396 | |
0865b04a | 1397 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1398 | return 0; |
613e8135 | 1399 | |
a3fcb948 JG |
1400 | for (i = 1; i < pattern.len; i++) |
1401 | { | |
1402 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1403 | insn_matched = 0; | |
37bdc87e | 1404 | } |
a3fcb948 JG |
1405 | return insn_matched; |
1406 | } | |
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1411 | the first instruction description that matches. Otherwise, return | |
1412 | NULL. */ | |
1413 | ||
1414 | static struct i386_insn * | |
1415 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1416 | { | |
1417 | struct i386_insn *pattern; | |
1418 | ||
1419 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1420 | { | |
1421 | if (i386_match_pattern (pc, *pattern)) | |
1422 | return pattern; | |
37bdc87e MK |
1423 | } |
1424 | ||
1425 | return NULL; | |
1426 | } | |
1427 | ||
a3fcb948 JG |
1428 | /* Return whether PC points inside a sequence of instructions that |
1429 | matches INSN_PATTERNS. */ | |
1430 | ||
1431 | static int | |
1432 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1433 | { | |
1434 | CORE_ADDR current_pc; | |
1435 | int ix, i; | |
a3fcb948 JG |
1436 | struct i386_insn *insn; |
1437 | ||
1438 | insn = i386_match_insn (pc, insn_patterns); | |
1439 | if (insn == NULL) | |
1440 | return 0; | |
1441 | ||
8bbdd3f4 | 1442 | current_pc = pc; |
a3fcb948 JG |
1443 | ix = insn - insn_patterns; |
1444 | for (i = ix - 1; i >= 0; i--) | |
1445 | { | |
8bbdd3f4 MK |
1446 | current_pc -= insn_patterns[i].len; |
1447 | ||
a3fcb948 JG |
1448 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1449 | return 0; | |
a3fcb948 JG |
1450 | } |
1451 | ||
1452 | current_pc = pc + insn->len; | |
1453 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1454 | { | |
1455 | if (!i386_match_pattern (current_pc, *insn)) | |
1456 | return 0; | |
1457 | ||
1458 | current_pc += insn->len; | |
1459 | } | |
1460 | ||
1461 | return 1; | |
1462 | } | |
1463 | ||
37bdc87e MK |
1464 | /* Some special instructions that might be migrated by GCC into the |
1465 | part of the prologue that sets up the new stack frame. Because the | |
1466 | stack frame hasn't been setup yet, no registers have been saved | |
1467 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1468 | touched. */ | |
1469 | ||
1470 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1471 | { | |
1777feb0 | 1472 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1473 | |
1474 | ??? Should we handle 16-bit operand-sizes here? */ | |
1475 | ||
1476 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1477 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1478 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1479 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1480 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1481 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1482 | { 5, { 0xb8 }, { 0xfe } }, | |
1483 | /* `movl imm32, %edx' */ | |
1484 | { 5, { 0xba }, { 0xff } }, | |
1485 | ||
1486 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1487 | encoding for `mov m32, %eax'. | |
1488 | ||
85102364 | 1489 | ??? Should we handle SIB addressing here? |
37bdc87e MK |
1490 | ??? Should we handle 16-bit operand-sizes here? */ |
1491 | ||
1492 | /* `movl m32, %eax' */ | |
1493 | { 5, { 0xa1 }, { 0xff } }, | |
1494 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1495 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1496 | /* `movl m32, %edx' */ | |
1497 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1498 | ||
1499 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1500 | Because of the symmetry, there are actually two ways to encode | |
1501 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1502 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1503 | ||
1504 | /* `subl %eax, %eax' */ | |
1505 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1506 | /* `subl %ecx, %ecx' */ | |
1507 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1508 | /* `subl %edx, %edx' */ | |
1509 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1510 | /* `xorl %eax, %eax' */ | |
1511 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1512 | /* `xorl %ecx, %ecx' */ | |
1513 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1514 | /* `xorl %edx, %edx' */ | |
1515 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1516 | { 0 } | |
1517 | }; | |
1518 | ||
14f9473c VC |
1519 | /* Check whether PC points to an endbr32 instruction. */ |
1520 | static CORE_ADDR | |
1521 | i386_skip_endbr (CORE_ADDR pc) | |
1522 | { | |
1523 | static const gdb_byte endbr32[] = { 0xf3, 0x0f, 0x1e, 0xfb }; | |
1524 | ||
1525 | gdb_byte buf[sizeof (endbr32)]; | |
1526 | ||
1527 | /* Stop there if we can't read the code */ | |
1528 | if (target_read_code (pc, buf, sizeof (endbr32))) | |
1529 | return pc; | |
1530 | ||
1531 | /* If the instruction isn't an endbr32, stop */ | |
1532 | if (memcmp (buf, endbr32, sizeof (endbr32)) != 0) | |
1533 | return pc; | |
1534 | ||
1535 | return pc + sizeof (endbr32); | |
1536 | } | |
e11481da PM |
1537 | |
1538 | /* Check whether PC points to a no-op instruction. */ | |
1539 | static CORE_ADDR | |
1540 | i386_skip_noop (CORE_ADDR pc) | |
1541 | { | |
1542 | gdb_byte op; | |
1543 | int check = 1; | |
1544 | ||
0865b04a | 1545 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1546 | return pc; |
e11481da PM |
1547 | |
1548 | while (check) | |
1549 | { | |
1550 | check = 0; | |
1551 | /* Ignore `nop' instruction. */ | |
1552 | if (op == 0x90) | |
1553 | { | |
1554 | pc += 1; | |
0865b04a | 1555 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1556 | return pc; |
e11481da PM |
1557 | check = 1; |
1558 | } | |
1559 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1560 | Microsoft system dlls often start with | |
1561 | a `mov %edi,%edi' instruction. | |
1562 | The 5 bytes before the function start are | |
1563 | filled with `nop' instructions. | |
1564 | This pattern can be used for hot-patching: | |
1565 | The `mov %edi, %edi' instruction can be replaced by a | |
1566 | near jump to the location of the 5 `nop' instructions | |
1567 | which can be replaced by a 32-bit jump to anywhere | |
1568 | in the 32-bit address space. */ | |
1569 | ||
1570 | else if (op == 0x8b) | |
1571 | { | |
0865b04a | 1572 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1573 | return pc; |
1574 | ||
e11481da PM |
1575 | if (op == 0xff) |
1576 | { | |
1577 | pc += 2; | |
0865b04a | 1578 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1579 | return pc; |
1580 | ||
e11481da PM |
1581 | check = 1; |
1582 | } | |
1583 | } | |
1584 | } | |
1585 | return pc; | |
1586 | } | |
1587 | ||
acd5c798 MK |
1588 | /* Check whether PC points at a code that sets up a new stack frame. |
1589 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1590 | instruction after the sequence that sets up the frame or LIMIT, |
1591 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1592 | |
1593 | static CORE_ADDR | |
e17a4113 UW |
1594 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1595 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1596 | struct i386_frame_cache *cache) |
1597 | { | |
e17a4113 | 1598 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1599 | struct i386_insn *insn; |
63c0089f | 1600 | gdb_byte op; |
26604a34 | 1601 | int skip = 0; |
acd5c798 | 1602 | |
37bdc87e MK |
1603 | if (limit <= pc) |
1604 | return limit; | |
acd5c798 | 1605 | |
0865b04a | 1606 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1607 | return pc; |
acd5c798 | 1608 | |
c906108c | 1609 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1610 | { |
acd5c798 MK |
1611 | /* Take into account that we've executed the `pushl %ebp' that |
1612 | starts this instruction sequence. */ | |
fd13a04a | 1613 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1614 | cache->sp_offset += 4; |
37bdc87e | 1615 | pc++; |
acd5c798 MK |
1616 | |
1617 | /* If that's all, return now. */ | |
37bdc87e MK |
1618 | if (limit <= pc) |
1619 | return limit; | |
26604a34 | 1620 | |
b4632131 | 1621 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1622 | GCC into the prologue and skip them. At this point in the |
1623 | prologue, code should only touch the scratch registers %eax, | |
30baf67b | 1624 | %ecx and %edx, so while the number of possibilities is sheer, |
37bdc87e | 1625 | it is limited. |
5daa5b4e | 1626 | |
26604a34 MK |
1627 | Make sure we only skip these instructions if we later see the |
1628 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1629 | while (pc + skip < limit) |
26604a34 | 1630 | { |
37bdc87e MK |
1631 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1632 | if (insn == NULL) | |
1633 | break; | |
b4632131 | 1634 | |
37bdc87e | 1635 | skip += insn->len; |
26604a34 MK |
1636 | } |
1637 | ||
37bdc87e MK |
1638 | /* If that's all, return now. */ |
1639 | if (limit <= pc + skip) | |
1640 | return limit; | |
1641 | ||
0865b04a | 1642 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1643 | return pc + skip; |
37bdc87e | 1644 | |
30f8135b YQ |
1645 | /* The i386 prologue looks like |
1646 | ||
1647 | push %ebp | |
1648 | mov %esp,%ebp | |
1649 | sub $0x10,%esp | |
1650 | ||
1651 | and a different prologue can be generated for atom. | |
1652 | ||
1653 | push %ebp | |
1654 | lea (%esp),%ebp | |
1655 | lea -0x10(%esp),%esp | |
1656 | ||
1657 | We handle both of them here. */ | |
1658 | ||
acd5c798 | 1659 | switch (op) |
c906108c | 1660 | { |
30f8135b | 1661 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1662 | case 0x8b: |
0865b04a | 1663 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1664 | != 0xec) |
37bdc87e | 1665 | return pc; |
30f8135b | 1666 | pc += (skip + 2); |
c906108c SS |
1667 | break; |
1668 | case 0x89: | |
0865b04a | 1669 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1670 | != 0xe5) |
37bdc87e | 1671 | return pc; |
30f8135b YQ |
1672 | pc += (skip + 2); |
1673 | break; | |
1674 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1675 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1676 | != 0x242c) |
1677 | return pc; | |
1678 | pc += (skip + 3); | |
c906108c SS |
1679 | break; |
1680 | default: | |
37bdc87e | 1681 | return pc; |
c906108c | 1682 | } |
acd5c798 | 1683 | |
26604a34 MK |
1684 | /* OK, we actually have a frame. We just don't know how large |
1685 | it is yet. Set its size to zero. We'll adjust it if | |
1686 | necessary. We also now commit to skipping the special | |
1687 | instructions mentioned before. */ | |
acd5c798 MK |
1688 | cache->locals = 0; |
1689 | ||
1690 | /* If that's all, return now. */ | |
37bdc87e MK |
1691 | if (limit <= pc) |
1692 | return limit; | |
acd5c798 | 1693 | |
fc338970 MK |
1694 | /* Check for stack adjustment |
1695 | ||
acd5c798 | 1696 | subl $XXX, %esp |
30f8135b YQ |
1697 | or |
1698 | lea -XXX(%esp),%esp | |
fc338970 | 1699 | |
fd35795f | 1700 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1701 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1702 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1703 | return pc; |
c906108c SS |
1704 | if (op == 0x83) |
1705 | { | |
fd35795f | 1706 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1707 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1708 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1709 | return pc; |
acd5c798 | 1710 | |
37bdc87e MK |
1711 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1712 | make sense to be negative). */ | |
0865b04a | 1713 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1714 | return pc + 3; |
c906108c SS |
1715 | } |
1716 | else if (op == 0x81) | |
1717 | { | |
fd35795f | 1718 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1719 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1720 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1721 | return pc; |
acd5c798 | 1722 | |
fd35795f | 1723 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1724 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1725 | return pc + 6; |
c906108c | 1726 | } |
30f8135b YQ |
1727 | else if (op == 0x8d) |
1728 | { | |
1729 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1730 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1731 | return pc; |
1732 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1733 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1734 | return pc + 4; |
1735 | } | |
c906108c SS |
1736 | else |
1737 | { | |
30f8135b | 1738 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1739 | return pc; |
c906108c SS |
1740 | } |
1741 | } | |
37bdc87e | 1742 | else if (op == 0xc8) /* enter */ |
c906108c | 1743 | { |
0865b04a | 1744 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1745 | return pc + 4; |
c906108c | 1746 | } |
21d0e8a4 | 1747 | |
acd5c798 | 1748 | return pc; |
21d0e8a4 MK |
1749 | } |
1750 | ||
acd5c798 MK |
1751 | /* Check whether PC points at code that saves registers on the stack. |
1752 | If so, it updates CACHE and returns the address of the first | |
1753 | instruction after the register saves or CURRENT_PC, whichever is | |
1754 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1755 | |
1756 | static CORE_ADDR | |
acd5c798 MK |
1757 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1758 | struct i386_frame_cache *cache) | |
6bff26de | 1759 | { |
99ab4326 | 1760 | CORE_ADDR offset = 0; |
63c0089f | 1761 | gdb_byte op; |
99ab4326 | 1762 | int i; |
c0d1d883 | 1763 | |
99ab4326 MK |
1764 | if (cache->locals > 0) |
1765 | offset -= cache->locals; | |
1766 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1767 | { | |
0865b04a | 1768 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1769 | return pc; |
99ab4326 MK |
1770 | if (op < 0x50 || op > 0x57) |
1771 | break; | |
0d17c81d | 1772 | |
99ab4326 MK |
1773 | offset -= 4; |
1774 | cache->saved_regs[op - 0x50] = offset; | |
1775 | cache->sp_offset += 4; | |
1776 | pc++; | |
6bff26de MK |
1777 | } |
1778 | ||
acd5c798 | 1779 | return pc; |
22797942 AC |
1780 | } |
1781 | ||
acd5c798 MK |
1782 | /* Do a full analysis of the prologue at PC and update CACHE |
1783 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1784 | address where the analysis stopped. | |
ed84f6c1 | 1785 | |
fc338970 MK |
1786 | We handle these cases: |
1787 | ||
1788 | The startup sequence can be at the start of the function, or the | |
1789 | function can start with a branch to startup code at the end. | |
1790 | ||
1791 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1792 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1793 | once used in the System V compiler). | |
1794 | ||
1795 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1796 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1797 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1798 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1799 | |
1800 | Next, the registers used by this function are pushed. With the | |
1801 | System V compiler they will always be in the order: %edi, %esi, | |
1802 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1803 | restore %eax); however, the code below is willing to see the pushes | |
1804 | in any order, and will handle up to 8 of them. | |
1805 | ||
1806 | If the setup sequence is at the end of the function, then the next | |
1807 | instruction will be a branch back to the start. */ | |
c906108c | 1808 | |
acd5c798 | 1809 | static CORE_ADDR |
e17a4113 UW |
1810 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1811 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1812 | struct i386_frame_cache *cache) |
c906108c | 1813 | { |
14f9473c | 1814 | pc = i386_skip_endbr (pc); |
e11481da | 1815 | pc = i386_skip_noop (pc); |
e17a4113 | 1816 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1817 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1818 | pc = i386_skip_probe (pc); | |
92dd43fa | 1819 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1820 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1821 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1822 | } |
1823 | ||
fc338970 | 1824 | /* Return PC of first real instruction. */ |
c906108c | 1825 | |
3a1e71e3 | 1826 | static CORE_ADDR |
6093d2eb | 1827 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1828 | { |
e17a4113 UW |
1829 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1830 | ||
63c0089f | 1831 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1832 | { |
1833 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1834 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1835 | }; |
acd5c798 MK |
1836 | struct i386_frame_cache cache; |
1837 | CORE_ADDR pc; | |
63c0089f | 1838 | gdb_byte op; |
acd5c798 | 1839 | int i; |
56bf0743 | 1840 | CORE_ADDR func_addr; |
4e879fc2 | 1841 | |
56bf0743 KB |
1842 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1843 | { | |
1844 | CORE_ADDR post_prologue_pc | |
1845 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1846 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 | 1847 | |
c2fd7fae | 1848 | /* LLVM backend (Clang/Flang) always emits a line note before the |
dda83cd7 SM |
1849 | prologue and another one after. We trust clang to emit usable |
1850 | line notes. */ | |
56bf0743 | 1851 | if (post_prologue_pc |
43f3e411 DE |
1852 | && (cust != NULL |
1853 | && COMPUNIT_PRODUCER (cust) != NULL | |
c2fd7fae | 1854 | && producer_is_llvm (COMPUNIT_PRODUCER (cust)))) |
dda83cd7 | 1855 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1856 | } |
1857 | ||
e0f33b1f | 1858 | cache.locals = -1; |
e17a4113 | 1859 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1860 | if (cache.locals < 0) |
1861 | return start_pc; | |
c5aa993b | 1862 | |
acd5c798 | 1863 | /* Found valid frame setup. */ |
c906108c | 1864 | |
fc338970 MK |
1865 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1866 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1867 | %ebx: |
1868 | ||
dda83cd7 | 1869 | call 0x0 |
fc338970 | 1870 | popl %ebx |
dda83cd7 SM |
1871 | movl %ebx,x(%ebp) (optional) |
1872 | addl y,%ebx | |
fc338970 | 1873 | |
c906108c SS |
1874 | This code is with the rest of the prologue (at the end of the |
1875 | function), so we have to skip it to get to the first real | |
1876 | instruction at the start of the function. */ | |
c5aa993b | 1877 | |
c906108c SS |
1878 | for (i = 0; i < 6; i++) |
1879 | { | |
0865b04a | 1880 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1881 | return pc; |
1882 | ||
c5aa993b | 1883 | if (pic_pat[i] != op) |
c906108c SS |
1884 | break; |
1885 | } | |
1886 | if (i == 6) | |
1887 | { | |
acd5c798 MK |
1888 | int delta = 6; |
1889 | ||
0865b04a | 1890 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1891 | return pc; |
c906108c | 1892 | |
c5aa993b | 1893 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1894 | { |
0865b04a | 1895 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1896 | |
fc338970 | 1897 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1898 | delta += 3; |
fc338970 | 1899 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1900 | delta += 6; |
fc338970 | 1901 | else /* Unexpected instruction. */ |
acd5c798 MK |
1902 | delta = 0; |
1903 | ||
dda83cd7 | 1904 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1905 | return pc; |
c906108c | 1906 | } |
acd5c798 | 1907 | |
c5aa993b | 1908 | /* addl y,%ebx */ |
acd5c798 | 1909 | if (delta > 0 && op == 0x81 |
0865b04a | 1910 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1911 | == 0xc3) |
c906108c | 1912 | { |
acd5c798 | 1913 | pc += delta + 6; |
c906108c SS |
1914 | } |
1915 | } | |
c5aa993b | 1916 | |
e63bbc88 MK |
1917 | /* If the function starts with a branch (to startup code at the end) |
1918 | the last instruction should bring us back to the first | |
1919 | instruction of the real code. */ | |
e17a4113 UW |
1920 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1921 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1922 | |
1923 | return pc; | |
c906108c SS |
1924 | } |
1925 | ||
4309257c PM |
1926 | /* Check that the code pointed to by PC corresponds to a call to |
1927 | __main, skip it if so. Return PC otherwise. */ | |
1928 | ||
1929 | CORE_ADDR | |
1930 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1931 | { | |
e17a4113 | 1932 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1933 | gdb_byte op; |
1934 | ||
0865b04a | 1935 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1936 | return pc; |
4309257c PM |
1937 | if (op == 0xe8) |
1938 | { | |
1939 | gdb_byte buf[4]; | |
1940 | ||
0865b04a | 1941 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1942 | { |
1943 | /* Make sure address is computed correctly as a 32bit | |
1944 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1945 | struct bound_minimal_symbol s; |
e17a4113 | 1946 | CORE_ADDR call_dest; |
4309257c | 1947 | |
e17a4113 | 1948 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1949 | call_dest = call_dest & 0xffffffffU; |
1950 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1951 | if (s.minsym != NULL |
c9d95fa3 CB |
1952 | && s.minsym->linkage_name () != NULL |
1953 | && strcmp (s.minsym->linkage_name (), "__main") == 0) | |
4309257c PM |
1954 | pc += 5; |
1955 | } | |
1956 | } | |
1957 | ||
1958 | return pc; | |
1959 | } | |
1960 | ||
acd5c798 | 1961 | /* This function is 64-bit safe. */ |
93924b6b | 1962 | |
acd5c798 MK |
1963 | static CORE_ADDR |
1964 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1965 | { |
63c0089f | 1966 | gdb_byte buf[8]; |
acd5c798 | 1967 | |
875f8d0e | 1968 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1969 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1970 | } |
acd5c798 | 1971 | \f |
93924b6b | 1972 | |
acd5c798 | 1973 | /* Normal frames. */ |
c5aa993b | 1974 | |
8fbca658 PA |
1975 | static void |
1976 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1977 | struct i386_frame_cache *cache) | |
a7769679 | 1978 | { |
e17a4113 UW |
1979 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1980 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1981 | gdb_byte buf[4]; |
acd5c798 MK |
1982 | int i; |
1983 | ||
8fbca658 | 1984 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1985 | |
1986 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1987 | which holds the base address for the current stack frame. | |
1988 | However, for functions that don't need it, the frame pointer is | |
1989 | optional. For these "frameless" functions the frame pointer is | |
1990 | actually the frame pointer of the calling frame. Signal | |
1991 | trampolines are just a special case of a "frameless" function. | |
1992 | They (usually) share their frame pointer with the frame that was | |
1993 | in progress when the signal occurred. */ | |
1994 | ||
10458914 | 1995 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1996 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1997 | if (cache->base == 0) |
620fa63a PA |
1998 | { |
1999 | cache->base_p = 1; | |
2000 | return; | |
2001 | } | |
acd5c798 MK |
2002 | |
2003 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 2004 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2005 | |
acd5c798 | 2006 | if (cache->pc != 0) |
e17a4113 UW |
2007 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2008 | cache); | |
acd5c798 MK |
2009 | |
2010 | if (cache->locals < 0) | |
2011 | { | |
2012 | /* We didn't find a valid frame, which means that CACHE->base | |
2013 | currently holds the frame pointer for our calling frame. If | |
2014 | we're at the start of a function, or somewhere half-way its | |
2015 | prologue, the function's frame probably hasn't been fully | |
2016 | setup yet. Try to reconstruct the base address for the stack | |
2017 | frame by looking at the stack pointer. For truly "frameless" | |
2018 | functions this might work too. */ | |
2019 | ||
e0c62198 | 2020 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2021 | { |
8fbca658 PA |
2022 | /* Saved stack pointer has been saved. */ |
2023 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2024 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2025 | ||
92dd43fa MK |
2026 | /* We're halfway aligning the stack. */ |
2027 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2028 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2029 | ||
2030 | /* This will be added back below. */ | |
2031 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2032 | } | |
7618e12b | 2033 | else if (cache->pc != 0 |
0865b04a | 2034 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2035 | { |
7618e12b DJ |
2036 | /* We're in a known function, but did not find a frame |
2037 | setup. Assume that the function does not use %ebp. | |
2038 | Alternatively, we may have jumped to an invalid | |
2039 | address; in that case there is definitely no new | |
2040 | frame in %ebp. */ | |
10458914 | 2041 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2042 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2043 | + cache->sp_offset; | |
92dd43fa | 2044 | } |
7618e12b DJ |
2045 | else |
2046 | /* We're in an unknown function. We could not find the start | |
2047 | of the function to analyze the prologue; our best option is | |
2048 | to assume a typical frame layout with the caller's %ebp | |
2049 | saved. */ | |
2050 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2051 | } |
2052 | ||
8fbca658 PA |
2053 | if (cache->saved_sp_reg != -1) |
2054 | { | |
2055 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2056 | register may be unavailable). */ | |
2057 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2058 | && deprecated_frame_register_read (this_frame, |
2059 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2060 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2061 | } | |
acd5c798 MK |
2062 | /* Now that we have the base address for the stack frame we can |
2063 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2064 | else if (cache->saved_sp == 0) |
92dd43fa | 2065 | cache->saved_sp = cache->base + 8; |
a7769679 | 2066 | |
acd5c798 MK |
2067 | /* Adjust all the saved registers such that they contain addresses |
2068 | instead of offsets. */ | |
2069 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2070 | if (cache->saved_regs[i] != -1) |
2071 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2072 | |
8fbca658 PA |
2073 | cache->base_p = 1; |
2074 | } | |
2075 | ||
2076 | static struct i386_frame_cache * | |
2077 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2078 | { | |
8fbca658 PA |
2079 | struct i386_frame_cache *cache; |
2080 | ||
2081 | if (*this_cache) | |
9a3c8263 | 2082 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2083 | |
2084 | cache = i386_alloc_frame_cache (); | |
2085 | *this_cache = cache; | |
2086 | ||
a70b8144 | 2087 | try |
8fbca658 PA |
2088 | { |
2089 | i386_frame_cache_1 (this_frame, cache); | |
2090 | } | |
230d2906 | 2091 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2092 | { |
2093 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2094 | throw; |
7556d4a4 | 2095 | } |
8fbca658 | 2096 | |
acd5c798 | 2097 | return cache; |
a7769679 MK |
2098 | } |
2099 | ||
3a1e71e3 | 2100 | static void |
10458914 | 2101 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2102 | struct frame_id *this_id) |
c906108c | 2103 | { |
10458914 | 2104 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2105 | |
5ce0145d PA |
2106 | if (!cache->base_p) |
2107 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2108 | else if (cache->base == 0) | |
2109 | { | |
2110 | /* This marks the outermost frame. */ | |
2111 | } | |
2112 | else | |
2113 | { | |
2114 | /* See the end of i386_push_dummy_call. */ | |
2115 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2116 | } | |
acd5c798 MK |
2117 | } |
2118 | ||
8fbca658 PA |
2119 | static enum unwind_stop_reason |
2120 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2121 | void **this_cache) | |
2122 | { | |
2123 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2124 | ||
2125 | if (!cache->base_p) | |
2126 | return UNWIND_UNAVAILABLE; | |
2127 | ||
2128 | /* This marks the outermost frame. */ | |
2129 | if (cache->base == 0) | |
2130 | return UNWIND_OUTERMOST; | |
2131 | ||
2132 | return UNWIND_NO_REASON; | |
2133 | } | |
2134 | ||
10458914 DJ |
2135 | static struct value * |
2136 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2137 | int regnum) | |
acd5c798 | 2138 | { |
10458914 | 2139 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2140 | |
2141 | gdb_assert (regnum >= 0); | |
2142 | ||
2143 | /* The System V ABI says that: | |
2144 | ||
2145 | "The flags register contains the system flags, such as the | |
2146 | direction flag and the carry flag. The direction flag must be | |
2147 | set to the forward (that is, zero) direction before entry and | |
2148 | upon exit from a function. Other user flags have no specified | |
2149 | role in the standard calling sequence and are not preserved." | |
2150 | ||
2151 | To guarantee the "upon exit" part of that statement we fake a | |
2152 | saved flags register that has its direction flag cleared. | |
2153 | ||
2154 | Note that GCC doesn't seem to rely on the fact that the direction | |
2155 | flag is cleared after a function return; it always explicitly | |
2156 | clears the flag before operations where it matters. | |
2157 | ||
2158 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2159 | right thing to do. The way we fake the flags register here makes | |
2160 | it impossible to change it. */ | |
2161 | ||
2162 | if (regnum == I386_EFLAGS_REGNUM) | |
2163 | { | |
10458914 | 2164 | ULONGEST val; |
c5aa993b | 2165 | |
10458914 DJ |
2166 | val = get_frame_register_unsigned (this_frame, regnum); |
2167 | val &= ~(1 << 10); | |
2168 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2169 | } |
1211c4e4 | 2170 | |
acd5c798 | 2171 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2172 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2173 | |
fcf250e2 UW |
2174 | if (regnum == I386_ESP_REGNUM |
2175 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2176 | { |
2177 | /* If the SP has been saved, but we don't know where, then this | |
2178 | means that SAVED_SP_REG register was found unavailable back | |
2179 | when we built the cache. */ | |
fcf250e2 | 2180 | if (cache->saved_sp == 0) |
8fbca658 PA |
2181 | return frame_unwind_got_register (this_frame, regnum, |
2182 | cache->saved_sp_reg); | |
2183 | else | |
2184 | return frame_unwind_got_constant (this_frame, regnum, | |
2185 | cache->saved_sp); | |
2186 | } | |
acd5c798 | 2187 | |
fd13a04a | 2188 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2189 | return frame_unwind_got_memory (this_frame, regnum, |
2190 | cache->saved_regs[regnum]); | |
fd13a04a | 2191 | |
10458914 | 2192 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2193 | } |
2194 | ||
2195 | static const struct frame_unwind i386_frame_unwind = | |
2196 | { | |
2197 | NORMAL_FRAME, | |
8fbca658 | 2198 | i386_frame_unwind_stop_reason, |
acd5c798 | 2199 | i386_frame_this_id, |
10458914 DJ |
2200 | i386_frame_prev_register, |
2201 | NULL, | |
2202 | default_frame_sniffer | |
acd5c798 | 2203 | }; |
06da04c6 MS |
2204 | |
2205 | /* Normal frames, but in a function epilogue. */ | |
2206 | ||
c9cf6e20 MG |
2207 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2208 | ||
2209 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2210 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2211 | the function's stack frame. */ | |
2212 | ||
2213 | static int | |
c9cf6e20 | 2214 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2215 | { |
2216 | gdb_byte insn; | |
43f3e411 | 2217 | struct compunit_symtab *cust; |
e0d00bc7 | 2218 | |
43f3e411 DE |
2219 | cust = find_pc_compunit_symtab (pc); |
2220 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2221 | return 0; |
06da04c6 MS |
2222 | |
2223 | if (target_read_memory (pc, &insn, 1)) | |
2224 | return 0; /* Can't read memory at pc. */ | |
2225 | ||
2226 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2227 | return 0; | |
2228 | ||
2229 | return 1; | |
2230 | } | |
2231 | ||
2232 | static int | |
2233 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2234 | struct frame_info *this_frame, | |
2235 | void **this_prologue_cache) | |
2236 | { | |
2237 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2238 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2239 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2240 | else |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | static struct i386_frame_cache * | |
2245 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2246 | { | |
06da04c6 | 2247 | struct i386_frame_cache *cache; |
0d6c2135 | 2248 | CORE_ADDR sp; |
06da04c6 MS |
2249 | |
2250 | if (*this_cache) | |
9a3c8263 | 2251 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2252 | |
2253 | cache = i386_alloc_frame_cache (); | |
2254 | *this_cache = cache; | |
2255 | ||
a70b8144 | 2256 | try |
8fbca658 | 2257 | { |
0d6c2135 | 2258 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2259 | |
0d6c2135 MK |
2260 | /* At this point the stack looks as if we just entered the |
2261 | function, with the return address at the top of the | |
2262 | stack. */ | |
2263 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2264 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2265 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2266 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2267 | |
8fbca658 PA |
2268 | cache->base_p = 1; |
2269 | } | |
230d2906 | 2270 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2271 | { |
2272 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2273 | throw; |
7556d4a4 | 2274 | } |
06da04c6 MS |
2275 | |
2276 | return cache; | |
2277 | } | |
2278 | ||
8fbca658 PA |
2279 | static enum unwind_stop_reason |
2280 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2281 | void **this_cache) | |
2282 | { | |
0d6c2135 MK |
2283 | struct i386_frame_cache *cache = |
2284 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2285 | |
2286 | if (!cache->base_p) | |
2287 | return UNWIND_UNAVAILABLE; | |
2288 | ||
2289 | return UNWIND_NO_REASON; | |
2290 | } | |
2291 | ||
06da04c6 MS |
2292 | static void |
2293 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2294 | void **this_cache, | |
2295 | struct frame_id *this_id) | |
2296 | { | |
0d6c2135 MK |
2297 | struct i386_frame_cache *cache = |
2298 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2299 | |
8fbca658 | 2300 | if (!cache->base_p) |
5ce0145d PA |
2301 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2302 | else | |
2303 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2304 | } |
2305 | ||
0d6c2135 MK |
2306 | static struct value * |
2307 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2308 | void **this_cache, int regnum) | |
2309 | { | |
2310 | /* Make sure we've initialized the cache. */ | |
2311 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2312 | ||
2313 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2314 | } | |
2315 | ||
06da04c6 MS |
2316 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2317 | { | |
2318 | NORMAL_FRAME, | |
8fbca658 | 2319 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2320 | i386_epilogue_frame_this_id, |
0d6c2135 | 2321 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2322 | NULL, |
2323 | i386_epilogue_frame_sniffer | |
2324 | }; | |
acd5c798 MK |
2325 | \f |
2326 | ||
a3fcb948 JG |
2327 | /* Stack-based trampolines. */ |
2328 | ||
2329 | /* These trampolines are used on cross x86 targets, when taking the | |
2330 | address of a nested function. When executing these trampolines, | |
2331 | no stack frame is set up, so we are in a similar situation as in | |
2332 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2333 | ||
2334 | /* Static chain passed in register. */ | |
2335 | ||
2336 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2337 | { | |
2338 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2339 | { 5, { 0xb8 }, { 0xfe } }, | |
2340 | ||
2341 | /* `jmp imm32' */ | |
2342 | { 5, { 0xe9 }, { 0xff } }, | |
2343 | ||
2344 | {0} | |
2345 | }; | |
2346 | ||
2347 | /* Static chain passed on stack (when regparm=3). */ | |
2348 | ||
2349 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2350 | { | |
2351 | /* `push imm32' */ | |
2352 | { 5, { 0x68 }, { 0xff } }, | |
2353 | ||
2354 | /* `jmp imm32' */ | |
2355 | { 5, { 0xe9 }, { 0xff } }, | |
2356 | ||
2357 | {0} | |
2358 | }; | |
2359 | ||
2360 | /* Return whether PC points inside a stack trampoline. */ | |
2361 | ||
2362 | static int | |
6df81a63 | 2363 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2364 | { |
2365 | gdb_byte insn; | |
2c02bd72 | 2366 | const char *name; |
a3fcb948 JG |
2367 | |
2368 | /* A stack trampoline is detected if no name is associated | |
2369 | to the current pc and if it points inside a trampoline | |
2370 | sequence. */ | |
2371 | ||
2372 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2373 | if (name) | |
2374 | return 0; | |
2375 | ||
2376 | if (target_read_memory (pc, &insn, 1)) | |
2377 | return 0; | |
2378 | ||
2379 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2380 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2381 | return 0; | |
2382 | ||
2383 | return 1; | |
2384 | } | |
2385 | ||
2386 | static int | |
2387 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2388 | struct frame_info *this_frame, |
2389 | void **this_cache) | |
a3fcb948 JG |
2390 | { |
2391 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2392 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2393 | else |
2394 | return 0; | |
2395 | } | |
2396 | ||
2397 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2398 | { | |
2399 | NORMAL_FRAME, | |
2400 | i386_epilogue_frame_unwind_stop_reason, | |
2401 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2402 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2403 | NULL, |
2404 | i386_stack_tramp_frame_sniffer | |
2405 | }; | |
2406 | \f | |
6710bf39 SS |
2407 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2408 | ||
2409 | static void | |
2410 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2411 | struct agent_expr *ax, struct axs_value *value, | |
2412 | CORE_ADDR scope) | |
2413 | { | |
2414 | /* The following sequence assumes the traditional use of the base | |
2415 | register. */ | |
2416 | ax_reg (ax, I386_EBP_REGNUM); | |
2417 | ax_const_l (ax, 4); | |
2418 | ax_simple (ax, aop_add); | |
2419 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2420 | value->kind = axs_lvalue_memory; | |
2421 | } | |
2422 | \f | |
a3fcb948 | 2423 | |
acd5c798 MK |
2424 | /* Signal trampolines. */ |
2425 | ||
2426 | static struct i386_frame_cache * | |
10458914 | 2427 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2428 | { |
e17a4113 UW |
2429 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2430 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2431 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2432 | struct i386_frame_cache *cache; |
acd5c798 | 2433 | CORE_ADDR addr; |
63c0089f | 2434 | gdb_byte buf[4]; |
acd5c798 MK |
2435 | |
2436 | if (*this_cache) | |
9a3c8263 | 2437 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2438 | |
fd13a04a | 2439 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2440 | |
a70b8144 | 2441 | try |
a3386186 | 2442 | { |
8fbca658 PA |
2443 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2444 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2445 | |
8fbca658 PA |
2446 | addr = tdep->sigcontext_addr (this_frame); |
2447 | if (tdep->sc_reg_offset) | |
2448 | { | |
2449 | int i; | |
a3386186 | 2450 | |
8fbca658 PA |
2451 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2452 | ||
2453 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2454 | if (tdep->sc_reg_offset[i] != -1) | |
2455 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2456 | } | |
2457 | else | |
2458 | { | |
2459 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2460 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2461 | } | |
2462 | ||
2463 | cache->base_p = 1; | |
a3386186 | 2464 | } |
230d2906 | 2465 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2466 | { |
2467 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2468 | throw; |
7556d4a4 | 2469 | } |
acd5c798 MK |
2470 | |
2471 | *this_cache = cache; | |
2472 | return cache; | |
2473 | } | |
2474 | ||
8fbca658 PA |
2475 | static enum unwind_stop_reason |
2476 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2477 | void **this_cache) | |
2478 | { | |
2479 | struct i386_frame_cache *cache = | |
2480 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2481 | ||
2482 | if (!cache->base_p) | |
2483 | return UNWIND_UNAVAILABLE; | |
2484 | ||
2485 | return UNWIND_NO_REASON; | |
2486 | } | |
2487 | ||
acd5c798 | 2488 | static void |
10458914 | 2489 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2490 | struct frame_id *this_id) |
2491 | { | |
2492 | struct i386_frame_cache *cache = | |
10458914 | 2493 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2494 | |
8fbca658 | 2495 | if (!cache->base_p) |
5ce0145d PA |
2496 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2497 | else | |
2498 | { | |
2499 | /* See the end of i386_push_dummy_call. */ | |
2500 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2501 | } | |
acd5c798 MK |
2502 | } |
2503 | ||
10458914 DJ |
2504 | static struct value * |
2505 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2506 | void **this_cache, int regnum) | |
acd5c798 MK |
2507 | { |
2508 | /* Make sure we've initialized the cache. */ | |
10458914 | 2509 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2510 | |
10458914 | 2511 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2512 | } |
c0d1d883 | 2513 | |
10458914 DJ |
2514 | static int |
2515 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2516 | struct frame_info *this_frame, | |
2517 | void **this_prologue_cache) | |
acd5c798 | 2518 | { |
10458914 | 2519 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2520 | |
911bc6ee MK |
2521 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2522 | handler. */ | |
2523 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2524 | return 0; |
1c3545ae | 2525 | |
911bc6ee MK |
2526 | if (tdep->sigtramp_p != NULL) |
2527 | { | |
10458914 DJ |
2528 | if (tdep->sigtramp_p (this_frame)) |
2529 | return 1; | |
911bc6ee MK |
2530 | } |
2531 | ||
2532 | if (tdep->sigtramp_start != 0) | |
2533 | { | |
10458914 | 2534 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2535 | |
2536 | gdb_assert (tdep->sigtramp_end != 0); | |
2537 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2538 | return 1; |
911bc6ee | 2539 | } |
acd5c798 | 2540 | |
10458914 | 2541 | return 0; |
acd5c798 | 2542 | } |
10458914 DJ |
2543 | |
2544 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2545 | { | |
2546 | SIGTRAMP_FRAME, | |
8fbca658 | 2547 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2548 | i386_sigtramp_frame_this_id, |
2549 | i386_sigtramp_frame_prev_register, | |
2550 | NULL, | |
2551 | i386_sigtramp_frame_sniffer | |
2552 | }; | |
acd5c798 MK |
2553 | \f |
2554 | ||
2555 | static CORE_ADDR | |
10458914 | 2556 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2557 | { |
10458914 | 2558 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2559 | |
2560 | return cache->base; | |
2561 | } | |
2562 | ||
2563 | static const struct frame_base i386_frame_base = | |
2564 | { | |
2565 | &i386_frame_unwind, | |
2566 | i386_frame_base_address, | |
2567 | i386_frame_base_address, | |
2568 | i386_frame_base_address | |
2569 | }; | |
2570 | ||
acd5c798 | 2571 | static struct frame_id |
10458914 | 2572 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2573 | { |
acd5c798 MK |
2574 | CORE_ADDR fp; |
2575 | ||
10458914 | 2576 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2577 | |
3e210248 | 2578 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2579 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2580 | } |
e04e5beb JM |
2581 | |
2582 | /* _Decimal128 function return values need 16-byte alignment on the | |
2583 | stack. */ | |
2584 | ||
2585 | static CORE_ADDR | |
2586 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2587 | { | |
2588 | return sp & -(CORE_ADDR)16; | |
2589 | } | |
fc338970 | 2590 | \f |
c906108c | 2591 | |
fc338970 MK |
2592 | /* Figure out where the longjmp will land. Slurp the args out of the |
2593 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2594 | structure from which we extract the address that we will land at. |
28bcfd30 | 2595 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2596 | success. */ |
c906108c | 2597 | |
8201327c | 2598 | static int |
60ade65d | 2599 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2600 | { |
436675d3 | 2601 | gdb_byte buf[4]; |
c906108c | 2602 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2603 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2604 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2605 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2606 | |
8201327c MK |
2607 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2608 | longjmp will land. */ | |
2609 | if (jb_pc_offset == -1) | |
c906108c SS |
2610 | return 0; |
2611 | ||
436675d3 | 2612 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2613 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2614 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2615 | return 0; |
2616 | ||
e17a4113 | 2617 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2618 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2619 | return 0; |
c906108c | 2620 | |
e17a4113 | 2621 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2622 | return 1; |
2623 | } | |
fc338970 | 2624 | \f |
c906108c | 2625 | |
7ccc1c74 JM |
2626 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2627 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2628 | unions containing such types must be 16-byte-aligned; other | |
2629 | arguments are 4-byte-aligned. */ | |
2630 | ||
2631 | static int | |
2632 | i386_16_byte_align_p (struct type *type) | |
2633 | { | |
2634 | type = check_typedef (type); | |
78134374 | 2635 | if ((type->code () == TYPE_CODE_DECFLOAT |
bd63c870 | 2636 | || (type->code () == TYPE_CODE_ARRAY && type->is_vector ())) |
7ccc1c74 JM |
2637 | && TYPE_LENGTH (type) == 16) |
2638 | return 1; | |
78134374 | 2639 | if (type->code () == TYPE_CODE_ARRAY) |
7ccc1c74 | 2640 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); |
78134374 SM |
2641 | if (type->code () == TYPE_CODE_STRUCT |
2642 | || type->code () == TYPE_CODE_UNION) | |
7ccc1c74 JM |
2643 | { |
2644 | int i; | |
1f704f76 | 2645 | for (i = 0; i < type->num_fields (); i++) |
7ccc1c74 | 2646 | { |
b6a6aa07 TV |
2647 | if (field_is_static (&type->field (i))) |
2648 | continue; | |
940da03e | 2649 | if (i386_16_byte_align_p (type->field (i).type ())) |
7ccc1c74 JM |
2650 | return 1; |
2651 | } | |
2652 | } | |
2653 | return 0; | |
2654 | } | |
2655 | ||
a9b8d892 JK |
2656 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2657 | ||
2658 | static CORE_ADDR | |
2659 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2660 | struct value **args, int nargs, struct type *value_type, | |
2661 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2662 | struct regcache *regcache) | |
2663 | { | |
2664 | /* Use 0xcc breakpoint - 1 byte. */ | |
2665 | *bp_addr = sp - 1; | |
2666 | *real_pc = funaddr; | |
2667 | ||
2668 | /* Keep the stack aligned. */ | |
2669 | return sp - 16; | |
2670 | } | |
2671 | ||
627c7fb8 HD |
2672 | /* The "push_dummy_call" gdbarch method, optionally with the thiscall |
2673 | calling convention. */ | |
2674 | ||
2675 | CORE_ADDR | |
2676 | i386_thiscall_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2677 | struct regcache *regcache, CORE_ADDR bp_addr, | |
2678 | int nargs, struct value **args, CORE_ADDR sp, | |
2679 | function_call_return_method return_method, | |
2680 | CORE_ADDR struct_addr, bool thiscall) | |
22f8ba57 | 2681 | { |
e17a4113 | 2682 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2683 | gdb_byte buf[4]; |
acd5c798 | 2684 | int i; |
7ccc1c74 JM |
2685 | int write_pass; |
2686 | int args_space = 0; | |
acd5c798 | 2687 | |
4a612d6f WT |
2688 | /* BND registers can be in arbitrary values at the moment of the |
2689 | inferior call. This can cause boundary violations that are not | |
2690 | due to a real bug or even desired by the user. The best to be done | |
2691 | is set the BND registers to allow access to the whole memory, INIT | |
2692 | state, before pushing the inferior call. */ | |
2693 | i387_reset_bnd_regs (gdbarch, regcache); | |
2694 | ||
7ccc1c74 JM |
2695 | /* Determine the total space required for arguments and struct |
2696 | return address in a first pass (allowing for 16-byte-aligned | |
2697 | arguments), then push arguments in a second pass. */ | |
2698 | ||
2699 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2700 | { |
7ccc1c74 | 2701 | int args_space_used = 0; |
7ccc1c74 | 2702 | |
cf84fa6b | 2703 | if (return_method == return_method_struct) |
7ccc1c74 JM |
2704 | { |
2705 | if (write_pass) | |
2706 | { | |
2707 | /* Push value address. */ | |
e17a4113 | 2708 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2709 | write_memory (sp, buf, 4); |
2710 | args_space_used += 4; | |
2711 | } | |
2712 | else | |
2713 | args_space += 4; | |
2714 | } | |
2715 | ||
627c7fb8 | 2716 | for (i = thiscall ? 1 : 0; i < nargs; i++) |
7ccc1c74 JM |
2717 | { |
2718 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2719 | |
7ccc1c74 JM |
2720 | if (write_pass) |
2721 | { | |
2722 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2723 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2724 | |
7ccc1c74 JM |
2725 | write_memory (sp + args_space_used, |
2726 | value_contents_all (args[i]), len); | |
2727 | /* The System V ABI says that: | |
acd5c798 | 2728 | |
7ccc1c74 JM |
2729 | "An argument's size is increased, if necessary, to make it a |
2730 | multiple of [32-bit] words. This may require tail padding, | |
2731 | depending on the size of the argument." | |
22f8ba57 | 2732 | |
7ccc1c74 JM |
2733 | This makes sure the stack stays word-aligned. */ |
2734 | args_space_used += align_up (len, 4); | |
2735 | } | |
2736 | else | |
2737 | { | |
2738 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2739 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2740 | args_space += align_up (len, 4); |
2741 | } | |
2742 | } | |
2743 | ||
2744 | if (!write_pass) | |
2745 | { | |
7ccc1c74 | 2746 | sp -= args_space; |
284c5a60 MK |
2747 | |
2748 | /* The original System V ABI only requires word alignment, | |
2749 | but modern incarnations need 16-byte alignment in order | |
2750 | to support SSE. Since wasting a few bytes here isn't | |
2751 | harmful we unconditionally enforce 16-byte alignment. */ | |
2752 | sp &= ~0xf; | |
7ccc1c74 | 2753 | } |
22f8ba57 MK |
2754 | } |
2755 | ||
acd5c798 MK |
2756 | /* Store return address. */ |
2757 | sp -= 4; | |
e17a4113 | 2758 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2759 | write_memory (sp, buf, 4); |
2760 | ||
2761 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2762 | store_unsigned_integer (buf, 4, byte_order, sp); |
b66f5587 | 2763 | regcache->cooked_write (I386_ESP_REGNUM, buf); |
acd5c798 MK |
2764 | |
2765 | /* ...and fake a frame pointer. */ | |
b66f5587 | 2766 | regcache->cooked_write (I386_EBP_REGNUM, buf); |
acd5c798 | 2767 | |
627c7fb8 HD |
2768 | /* The 'this' pointer needs to be in ECX. */ |
2769 | if (thiscall) | |
2770 | regcache->cooked_write (I386_ECX_REGNUM, value_contents_all (args[0])); | |
2771 | ||
3e210248 AC |
2772 | /* MarkK wrote: This "+ 8" is all over the place: |
2773 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2774 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2775 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2776 | definition of the stack address of a frame. Otherwise frame id |
2777 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2778 | stack address *before* the function call as a frame's CFA. On |
2779 | the i386, when %ebp is used as a frame pointer, the offset | |
2780 | between the contents %ebp and the CFA as defined by GCC. */ | |
2781 | return sp + 8; | |
22f8ba57 MK |
2782 | } |
2783 | ||
627c7fb8 HD |
2784 | /* Implement the "push_dummy_call" gdbarch method. */ |
2785 | ||
2786 | static CORE_ADDR | |
2787 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2788 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2789 | struct value **args, CORE_ADDR sp, | |
2790 | function_call_return_method return_method, | |
2791 | CORE_ADDR struct_addr) | |
2792 | { | |
2793 | return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr, | |
2794 | nargs, args, sp, return_method, | |
2795 | struct_addr, false); | |
2796 | } | |
2797 | ||
1a309862 MK |
2798 | /* These registers are used for returning integers (and on some |
2799 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2800 | size and alignment match an integer type). */ |
acd5c798 MK |
2801 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2802 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2803 | |
c5e656c1 MK |
2804 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2805 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2806 | |
3a1e71e3 | 2807 | static void |
c5e656c1 | 2808 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2809 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2810 | { |
c5e656c1 | 2811 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2812 | int len = TYPE_LENGTH (type); |
63c0089f | 2813 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2814 | |
78134374 | 2815 | if (type->code () == TYPE_CODE_FLT) |
c906108c | 2816 | { |
5716833c | 2817 | if (tdep->st0_regnum < 0) |
1a309862 | 2818 | { |
8a3fe4f8 | 2819 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2820 | memset (valbuf, 0, len); |
ef9dff19 | 2821 | return; |
1a309862 MK |
2822 | } |
2823 | ||
c6ba6f0d MK |
2824 | /* Floating-point return values can be found in %st(0). Convert |
2825 | its contents to the desired type. This is probably not | |
2826 | exactly how it would happen on the target itself, but it is | |
2827 | the best we can do. */ | |
0b883586 | 2828 | regcache->raw_read (I386_ST0_REGNUM, buf); |
3b2ca824 | 2829 | target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2830 | } |
2831 | else | |
c5aa993b | 2832 | { |
875f8d0e UW |
2833 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2834 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2835 | |
2836 | if (len <= low_size) | |
00f8375e | 2837 | { |
0b883586 | 2838 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2839 | memcpy (valbuf, buf, len); |
2840 | } | |
d4f3574e SS |
2841 | else if (len <= (low_size + high_size)) |
2842 | { | |
0b883586 | 2843 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e | 2844 | memcpy (valbuf, buf, low_size); |
0b883586 | 2845 | regcache->raw_read (HIGH_RETURN_REGNUM, buf); |
63c0089f | 2846 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2847 | } |
2848 | else | |
8e65ff28 | 2849 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2850 | _("Cannot extract return value of %d bytes long."), |
2851 | len); | |
c906108c SS |
2852 | } |
2853 | } | |
2854 | ||
c5e656c1 MK |
2855 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2856 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2857 | |
3a1e71e3 | 2858 | static void |
c5e656c1 | 2859 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2860 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2861 | { |
c5e656c1 | 2862 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2863 | int len = TYPE_LENGTH (type); |
2864 | ||
78134374 | 2865 | if (type->code () == TYPE_CODE_FLT) |
ef9dff19 | 2866 | { |
3d7f4f49 | 2867 | ULONGEST fstat; |
63c0089f | 2868 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2869 | |
5716833c | 2870 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2871 | { |
8a3fe4f8 | 2872 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2873 | return; |
2874 | } | |
2875 | ||
635b0cc1 | 2876 | /* Returning floating-point values is a bit tricky. Apart from |
dda83cd7 SM |
2877 | storing the return value in %st(0), we have to simulate the |
2878 | state of the FPU at function return point. */ | |
635b0cc1 | 2879 | |
c6ba6f0d MK |
2880 | /* Convert the value found in VALBUF to the extended |
2881 | floating-point format used by the FPU. This is probably | |
2882 | not exactly how it would happen on the target itself, but | |
2883 | it is the best we can do. */ | |
3b2ca824 | 2884 | target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch)); |
10eaee5f | 2885 | regcache->raw_write (I386_ST0_REGNUM, buf); |
ccb945b8 | 2886 | |
635b0cc1 | 2887 | /* Set the top of the floating-point register stack to 7. The |
dda83cd7 SM |
2888 | actual value doesn't really matter, but 7 is what a normal |
2889 | function return would end up with if the program started out | |
2890 | with a freshly initialized FPU. */ | |
20a6ec49 | 2891 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2892 | fstat |= (7 << 11); |
20a6ec49 | 2893 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2894 | |
635b0cc1 | 2895 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
dda83cd7 SM |
2896 | the floating-point register stack to 7, the appropriate value |
2897 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2898 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2899 | } |
2900 | else | |
2901 | { | |
875f8d0e UW |
2902 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2903 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2904 | |
2905 | if (len <= low_size) | |
4f0420fd | 2906 | regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2907 | else if (len <= (low_size + high_size)) |
2908 | { | |
10eaee5f | 2909 | regcache->raw_write (LOW_RETURN_REGNUM, valbuf); |
4f0420fd SM |
2910 | regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size, |
2911 | valbuf + low_size); | |
ef9dff19 MK |
2912 | } |
2913 | else | |
8e65ff28 | 2914 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2915 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2916 | } |
2917 | } | |
fc338970 | 2918 | \f |
ef9dff19 | 2919 | |
8201327c MK |
2920 | /* This is the variable that is set with "set struct-convention", and |
2921 | its legitimate values. */ | |
2922 | static const char default_struct_convention[] = "default"; | |
2923 | static const char pcc_struct_convention[] = "pcc"; | |
2924 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2925 | static const char *const valid_conventions[] = |
8201327c MK |
2926 | { |
2927 | default_struct_convention, | |
2928 | pcc_struct_convention, | |
2929 | reg_struct_convention, | |
2930 | NULL | |
2931 | }; | |
2932 | static const char *struct_convention = default_struct_convention; | |
2933 | ||
0e4377e1 JB |
2934 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2935 | a union type, or an array type, should be returned in registers | |
2936 | for architecture GDBARCH. */ | |
c5e656c1 | 2937 | |
8201327c | 2938 | static int |
c5e656c1 | 2939 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2940 | { |
c5e656c1 | 2941 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
78134374 | 2942 | enum type_code code = type->code (); |
c5e656c1 | 2943 | int len = TYPE_LENGTH (type); |
8201327c | 2944 | |
0e4377e1 | 2945 | gdb_assert (code == TYPE_CODE_STRUCT |
dda83cd7 SM |
2946 | || code == TYPE_CODE_UNION |
2947 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2948 | |
2949 | if (struct_convention == pcc_struct_convention | |
2950 | || (struct_convention == default_struct_convention | |
2951 | && tdep->struct_return == pcc_struct_return)) | |
2952 | return 0; | |
2953 | ||
9edde48e MK |
2954 | /* Structures consisting of a single `float', `double' or 'long |
2955 | double' member are returned in %st(0). */ | |
1f704f76 | 2956 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
9edde48e | 2957 | { |
940da03e | 2958 | type = check_typedef (type->field (0).type ()); |
78134374 | 2959 | if (type->code () == TYPE_CODE_FLT) |
9edde48e MK |
2960 | return (len == 4 || len == 8 || len == 12); |
2961 | } | |
2962 | ||
c5e656c1 MK |
2963 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2964 | } | |
2965 | ||
2966 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2967 | should be returned. If it is supposed to be returned in registers, | |
2968 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2969 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2970 | from WRITEBUF into REGCACHE. */ | |
2971 | ||
2972 | static enum return_value_convention | |
6a3a010b | 2973 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2974 | struct type *type, struct regcache *regcache, |
2975 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 | 2976 | { |
78134374 | 2977 | enum type_code code = type->code (); |
c5e656c1 | 2978 | |
5daa78cc TJB |
2979 | if (((code == TYPE_CODE_STRUCT |
2980 | || code == TYPE_CODE_UNION | |
2981 | || code == TYPE_CODE_ARRAY) | |
2982 | && !i386_reg_struct_return_p (gdbarch, type)) | |
405feb71 | 2983 | /* Complex double and long double uses the struct return convention. */ |
2445fd7b MK |
2984 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) |
2985 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2986 | /* 128-bit decimal float uses the struct return convention. */ |
2987 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2988 | { |
2989 | /* The System V ABI says that: | |
2990 | ||
2991 | "A function that returns a structure or union also sets %eax | |
2992 | to the value of the original address of the caller's area | |
2993 | before it returns. Thus when the caller receives control | |
2994 | again, the address of the returned object resides in register | |
2995 | %eax and can be used to access the object." | |
2996 | ||
2997 | So the ABI guarantees that we can always find the return | |
2998 | value just after the function has returned. */ | |
2999 | ||
0e4377e1 | 3000 | /* Note that the ABI doesn't mention functions returning arrays, |
dda83cd7 SM |
3001 | which is something possible in certain languages such as Ada. |
3002 | In this case, the value is returned as if it was wrapped in | |
3003 | a record, so the convention applied to records also applies | |
3004 | to arrays. */ | |
0e4377e1 | 3005 | |
31db7b6c MK |
3006 | if (readbuf) |
3007 | { | |
3008 | ULONGEST addr; | |
3009 | ||
3010 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
3011 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
3012 | } | |
3013 | ||
3014 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
3015 | } | |
c5e656c1 MK |
3016 | |
3017 | /* This special case is for structures consisting of a single | |
9edde48e MK |
3018 | `float', `double' or 'long double' member. These structures are |
3019 | returned in %st(0). For these structures, we call ourselves | |
3020 | recursively, changing TYPE into the type of the first member of | |
3021 | the structure. Since that should work for all structures that | |
3022 | have only one member, we don't bother to check the member's type | |
3023 | here. */ | |
1f704f76 | 3024 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
c5e656c1 | 3025 | { |
940da03e | 3026 | type = check_typedef (type->field (0).type ()); |
6a3a010b | 3027 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 3028 | readbuf, writebuf); |
c5e656c1 MK |
3029 | } |
3030 | ||
3031 | if (readbuf) | |
3032 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
3033 | if (writebuf) | |
3034 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3035 | |
c5e656c1 | 3036 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3037 | } |
3038 | \f | |
3039 | ||
27067745 UW |
3040 | struct type * |
3041 | i387_ext_type (struct gdbarch *gdbarch) | |
3042 | { | |
3043 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3044 | ||
3045 | if (!tdep->i387_ext_type) | |
90884b2b L |
3046 | { |
3047 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3048 | gdb_assert (tdep->i387_ext_type != NULL); | |
3049 | } | |
27067745 UW |
3050 | |
3051 | return tdep->i387_ext_type; | |
3052 | } | |
3053 | ||
1dbcd68c WT |
3054 | /* Construct type for pseudo BND registers. We can't use |
3055 | tdesc_find_type since a complement of one value has to be used | |
3056 | to describe the upper bound. */ | |
3057 | ||
3058 | static struct type * | |
3059 | i386_bnd_type (struct gdbarch *gdbarch) | |
3060 | { | |
3061 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3062 | ||
3063 | ||
3064 | if (!tdep->i386_bnd_type) | |
3065 | { | |
870f88f7 | 3066 | struct type *t; |
1dbcd68c WT |
3067 | const struct builtin_type *bt = builtin_type (gdbarch); |
3068 | ||
3069 | /* The type we're building is described bellow: */ | |
3070 | #if 0 | |
3071 | struct __bound128 | |
3072 | { | |
3073 | void *lbound; | |
3074 | void *ubound; /* One complement of raw ubound field. */ | |
3075 | }; | |
3076 | #endif | |
3077 | ||
3078 | t = arch_composite_type (gdbarch, | |
3079 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3080 | ||
3081 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3082 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3083 | ||
d0e39ea2 | 3084 | t->set_name ("builtin_type_bound128"); |
1dbcd68c WT |
3085 | tdep->i386_bnd_type = t; |
3086 | } | |
3087 | ||
3088 | return tdep->i386_bnd_type; | |
3089 | } | |
3090 | ||
01f9f808 MS |
3091 | /* Construct vector type for pseudo ZMM registers. We can't use |
3092 | tdesc_find_type since ZMM isn't described in target description. */ | |
3093 | ||
3094 | static struct type * | |
3095 | i386_zmm_type (struct gdbarch *gdbarch) | |
3096 | { | |
3097 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3098 | ||
3099 | if (!tdep->i386_zmm_type) | |
3100 | { | |
3101 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3102 | ||
3103 | /* The type we're building is this: */ | |
3104 | #if 0 | |
3105 | union __gdb_builtin_type_vec512i | |
3106 | { | |
1347d111 FW |
3107 | int128_t v4_int128[4]; |
3108 | int64_t v8_int64[8]; | |
3109 | int32_t v16_int32[16]; | |
3110 | int16_t v32_int16[32]; | |
3111 | int8_t v64_int8[64]; | |
3112 | double v8_double[8]; | |
3113 | float v16_float[16]; | |
2a67f09d | 3114 | bfloat16_t v32_bfloat16[32]; |
01f9f808 MS |
3115 | }; |
3116 | #endif | |
3117 | ||
3118 | struct type *t; | |
3119 | ||
3120 | t = arch_composite_type (gdbarch, | |
3121 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
2a67f09d FW |
3122 | append_composite_type_field (t, "v32_bfloat16", |
3123 | init_vector_type (bt->builtin_bfloat16, 32)); | |
01f9f808 MS |
3124 | append_composite_type_field (t, "v16_float", |
3125 | init_vector_type (bt->builtin_float, 16)); | |
3126 | append_composite_type_field (t, "v8_double", | |
3127 | init_vector_type (bt->builtin_double, 8)); | |
3128 | append_composite_type_field (t, "v64_int8", | |
3129 | init_vector_type (bt->builtin_int8, 64)); | |
3130 | append_composite_type_field (t, "v32_int16", | |
3131 | init_vector_type (bt->builtin_int16, 32)); | |
3132 | append_composite_type_field (t, "v16_int32", | |
3133 | init_vector_type (bt->builtin_int32, 16)); | |
3134 | append_composite_type_field (t, "v8_int64", | |
3135 | init_vector_type (bt->builtin_int64, 8)); | |
3136 | append_composite_type_field (t, "v4_int128", | |
3137 | init_vector_type (bt->builtin_int128, 4)); | |
3138 | ||
2062087b | 3139 | t->set_is_vector (true); |
d0e39ea2 | 3140 | t->set_name ("builtin_type_vec512i"); |
01f9f808 MS |
3141 | tdep->i386_zmm_type = t; |
3142 | } | |
3143 | ||
3144 | return tdep->i386_zmm_type; | |
3145 | } | |
3146 | ||
c131fcee L |
3147 | /* Construct vector type for pseudo YMM registers. We can't use |
3148 | tdesc_find_type since YMM isn't described in target description. */ | |
3149 | ||
3150 | static struct type * | |
3151 | i386_ymm_type (struct gdbarch *gdbarch) | |
3152 | { | |
3153 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3154 | ||
3155 | if (!tdep->i386_ymm_type) | |
3156 | { | |
3157 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3158 | ||
3159 | /* The type we're building is this: */ | |
3160 | #if 0 | |
3161 | union __gdb_builtin_type_vec256i | |
3162 | { | |
dda83cd7 SM |
3163 | int128_t v2_int128[2]; |
3164 | int64_t v4_int64[4]; | |
3165 | int32_t v8_int32[8]; | |
3166 | int16_t v16_int16[16]; | |
3167 | int8_t v32_int8[32]; | |
3168 | double v4_double[4]; | |
3169 | float v8_float[8]; | |
3170 | bfloat16_t v16_bfloat16[16]; | |
c131fcee L |
3171 | }; |
3172 | #endif | |
3173 | ||
3174 | struct type *t; | |
3175 | ||
3176 | t = arch_composite_type (gdbarch, | |
3177 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2a67f09d FW |
3178 | append_composite_type_field (t, "v16_bfloat16", |
3179 | init_vector_type (bt->builtin_bfloat16, 16)); | |
c131fcee L |
3180 | append_composite_type_field (t, "v8_float", |
3181 | init_vector_type (bt->builtin_float, 8)); | |
3182 | append_composite_type_field (t, "v4_double", | |
3183 | init_vector_type (bt->builtin_double, 4)); | |
3184 | append_composite_type_field (t, "v32_int8", | |
3185 | init_vector_type (bt->builtin_int8, 32)); | |
3186 | append_composite_type_field (t, "v16_int16", | |
3187 | init_vector_type (bt->builtin_int16, 16)); | |
3188 | append_composite_type_field (t, "v8_int32", | |
3189 | init_vector_type (bt->builtin_int32, 8)); | |
3190 | append_composite_type_field (t, "v4_int64", | |
3191 | init_vector_type (bt->builtin_int64, 4)); | |
3192 | append_composite_type_field (t, "v2_int128", | |
3193 | init_vector_type (bt->builtin_int128, 2)); | |
3194 | ||
2062087b | 3195 | t->set_is_vector (true); |
d0e39ea2 | 3196 | t->set_name ("builtin_type_vec256i"); |
c131fcee L |
3197 | tdep->i386_ymm_type = t; |
3198 | } | |
3199 | ||
3200 | return tdep->i386_ymm_type; | |
3201 | } | |
3202 | ||
794ac428 | 3203 | /* Construct vector type for MMX registers. */ |
90884b2b | 3204 | static struct type * |
794ac428 UW |
3205 | i386_mmx_type (struct gdbarch *gdbarch) |
3206 | { | |
3207 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3208 | ||
3209 | if (!tdep->i386_mmx_type) | |
3210 | { | |
df4df182 UW |
3211 | const struct builtin_type *bt = builtin_type (gdbarch); |
3212 | ||
794ac428 UW |
3213 | /* The type we're building is this: */ |
3214 | #if 0 | |
3215 | union __gdb_builtin_type_vec64i | |
3216 | { | |
dda83cd7 SM |
3217 | int64_t uint64; |
3218 | int32_t v2_int32[2]; | |
3219 | int16_t v4_int16[4]; | |
3220 | int8_t v8_int8[8]; | |
794ac428 UW |
3221 | }; |
3222 | #endif | |
3223 | ||
3224 | struct type *t; | |
3225 | ||
e9bb382b UW |
3226 | t = arch_composite_type (gdbarch, |
3227 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3228 | |
3229 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3230 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3231 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3232 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3233 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3234 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3235 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3236 | |
2062087b | 3237 | t->set_is_vector (true); |
d0e39ea2 | 3238 | t->set_name ("builtin_type_vec64i"); |
794ac428 UW |
3239 | tdep->i386_mmx_type = t; |
3240 | } | |
3241 | ||
3242 | return tdep->i386_mmx_type; | |
3243 | } | |
3244 | ||
d7a0d72c | 3245 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3246 | register REGNUM. */ |
d7a0d72c | 3247 | |
fff4548b | 3248 | struct type * |
90884b2b | 3249 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3250 | { |
1dbcd68c WT |
3251 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3252 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3253 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3254 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3255 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3256 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3257 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3258 | return i386_ymm_type (gdbarch); | |
3259 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3260 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3261 | else |
3262 | { | |
3263 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3264 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3265 | return bt->builtin_int8; | |
3266 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3267 | return bt->builtin_int16; | |
3268 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3269 | return bt->builtin_int32; | |
01f9f808 MS |
3270 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3271 | return bt->builtin_int64; | |
1ba53b71 L |
3272 | } |
3273 | ||
3274 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3275 | } |
3276 | ||
28fc6740 | 3277 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3278 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3279 | |
3280 | static int | |
849d0ba8 | 3281 | i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum) |
28fc6740 | 3282 | { |
ac7936df | 3283 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
5716833c | 3284 | int mmxreg, fpreg; |
28fc6740 AC |
3285 | ULONGEST fstat; |
3286 | int tos; | |
c86c27af | 3287 | |
5716833c | 3288 | mmxreg = regnum - tdep->mm0_regnum; |
03f50fc8 | 3289 | regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3290 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3291 | fpreg = (mmxreg + tos) % 8; |
3292 | ||
20a6ec49 | 3293 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3294 | } |
3295 | ||
3543a589 TT |
3296 | /* A helper function for us by i386_pseudo_register_read_value and |
3297 | amd64_pseudo_register_read_value. It does all the work but reads | |
3298 | the data into an already-allocated value. */ | |
3299 | ||
3300 | void | |
3301 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3302 | readable_regcache *regcache, |
3543a589 TT |
3303 | int regnum, |
3304 | struct value *result_value) | |
28fc6740 | 3305 | { |
975c21ab | 3306 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3307 | enum register_status status; |
3543a589 | 3308 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3309 | |
5716833c | 3310 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3311 | { |
c86c27af MK |
3312 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3313 | ||
28fc6740 | 3314 | /* Extract (always little endian). */ |
03f50fc8 | 3315 | status = regcache->raw_read (fpnum, raw_buf); |
05d1431c | 3316 | if (status != REG_VALID) |
3543a589 TT |
3317 | mark_value_bytes_unavailable (result_value, 0, |
3318 | TYPE_LENGTH (value_type (result_value))); | |
3319 | else | |
3320 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3321 | } |
3322 | else | |
1ba53b71 L |
3323 | { |
3324 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3325 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3326 | { | |
3327 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3328 | |
1dbcd68c | 3329 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3330 | status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3331 | raw_buf); | |
1dbcd68c WT |
3332 | if (status != REG_VALID) |
3333 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3334 | else | |
3335 | { | |
3336 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3337 | LONGEST upper, lower; | |
3338 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3339 | ||
3340 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3341 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3342 | upper = ~upper; | |
3343 | ||
3344 | memcpy (buf, &lower, size); | |
3345 | memcpy (buf + size, &upper, size); | |
3346 | } | |
3347 | } | |
01f9f808 MS |
3348 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3349 | { | |
3350 | regnum -= tdep->k0_regnum; | |
3351 | ||
3352 | /* Extract (always little endian). */ | |
03f50fc8 | 3353 | status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf); |
01f9f808 MS |
3354 | if (status != REG_VALID) |
3355 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3356 | else | |
3357 | memcpy (buf, raw_buf, 8); | |
3358 | } | |
3359 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3360 | { | |
3361 | regnum -= tdep->zmm0_regnum; | |
3362 | ||
3363 | if (regnum < num_lower_zmm_regs) | |
3364 | { | |
3365 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3366 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3367 | raw_buf); | |
01f9f808 MS |
3368 | if (status != REG_VALID) |
3369 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3370 | else | |
3371 | memcpy (buf, raw_buf, 16); | |
3372 | ||
3373 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3374 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3375 | raw_buf); | |
01f9f808 MS |
3376 | if (status != REG_VALID) |
3377 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3378 | else | |
3379 | memcpy (buf + 16, raw_buf, 16); | |
3380 | } | |
3381 | else | |
3382 | { | |
3383 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3384 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum |
3385 | - num_lower_zmm_regs, | |
3386 | raw_buf); | |
01f9f808 MS |
3387 | if (status != REG_VALID) |
3388 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3389 | else | |
3390 | memcpy (buf, raw_buf, 16); | |
3391 | ||
3392 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3393 | status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum |
3394 | - num_lower_zmm_regs, | |
3395 | raw_buf); | |
01f9f808 MS |
3396 | if (status != REG_VALID) |
3397 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3398 | else | |
3399 | memcpy (buf + 16, raw_buf, 16); | |
3400 | } | |
3401 | ||
3402 | /* Read upper 256bits. */ | |
03f50fc8 YQ |
3403 | status = regcache->raw_read (tdep->zmm0h_regnum + regnum, |
3404 | raw_buf); | |
01f9f808 MS |
3405 | if (status != REG_VALID) |
3406 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3407 | else | |
3408 | memcpy (buf + 32, raw_buf, 32); | |
3409 | } | |
1dbcd68c | 3410 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3411 | { |
3412 | regnum -= tdep->ymm0_regnum; | |
3413 | ||
1777feb0 | 3414 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3415 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3416 | raw_buf); | |
05d1431c | 3417 | if (status != REG_VALID) |
3543a589 TT |
3418 | mark_value_bytes_unavailable (result_value, 0, 16); |
3419 | else | |
3420 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3421 | /* Read upper 128bits. */ |
03f50fc8 YQ |
3422 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3423 | raw_buf); | |
05d1431c | 3424 | if (status != REG_VALID) |
3543a589 TT |
3425 | mark_value_bytes_unavailable (result_value, 16, 32); |
3426 | else | |
3427 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3428 | } |
01f9f808 MS |
3429 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3430 | { | |
3431 | regnum -= tdep->ymm16_regnum; | |
3432 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3433 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum, |
3434 | raw_buf); | |
01f9f808 MS |
3435 | if (status != REG_VALID) |
3436 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3437 | else | |
3438 | memcpy (buf, raw_buf, 16); | |
3439 | /* Read upper 128bits. */ | |
03f50fc8 YQ |
3440 | status = regcache->raw_read (tdep->ymm16h_regnum + regnum, |
3441 | raw_buf); | |
01f9f808 MS |
3442 | if (status != REG_VALID) |
3443 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3444 | else | |
3445 | memcpy (buf + 16, raw_buf, 16); | |
3446 | } | |
c131fcee | 3447 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3448 | { |
3449 | int gpnum = regnum - tdep->ax_regnum; | |
3450 | ||
3451 | /* Extract (always little endian). */ | |
03f50fc8 | 3452 | status = regcache->raw_read (gpnum, raw_buf); |
05d1431c | 3453 | if (status != REG_VALID) |
3543a589 TT |
3454 | mark_value_bytes_unavailable (result_value, 0, |
3455 | TYPE_LENGTH (value_type (result_value))); | |
3456 | else | |
3457 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3458 | } |
3459 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3460 | { | |
1ba53b71 L |
3461 | int gpnum = regnum - tdep->al_regnum; |
3462 | ||
3463 | /* Extract (always little endian). We read both lower and | |
3464 | upper registers. */ | |
03f50fc8 | 3465 | status = regcache->raw_read (gpnum % 4, raw_buf); |
05d1431c | 3466 | if (status != REG_VALID) |
3543a589 TT |
3467 | mark_value_bytes_unavailable (result_value, 0, |
3468 | TYPE_LENGTH (value_type (result_value))); | |
3469 | else if (gpnum >= 4) | |
1ba53b71 L |
3470 | memcpy (buf, raw_buf + 1, 1); |
3471 | else | |
3472 | memcpy (buf, raw_buf, 1); | |
3473 | } | |
3474 | else | |
3475 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3476 | } | |
3543a589 TT |
3477 | } |
3478 | ||
3479 | static struct value * | |
3480 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3481 | readable_regcache *regcache, |
3543a589 TT |
3482 | int regnum) |
3483 | { | |
3484 | struct value *result; | |
3485 | ||
3486 | result = allocate_value (register_type (gdbarch, regnum)); | |
3487 | VALUE_LVAL (result) = lval_register; | |
3488 | VALUE_REGNUM (result) = regnum; | |
3489 | ||
3490 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3491 | |
3543a589 | 3492 | return result; |
28fc6740 AC |
3493 | } |
3494 | ||
1ba53b71 | 3495 | void |
28fc6740 | 3496 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3497 | int regnum, const gdb_byte *buf) |
28fc6740 | 3498 | { |
975c21ab | 3499 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3500 | |
5716833c | 3501 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3502 | { |
c86c27af MK |
3503 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3504 | ||
28fc6740 | 3505 | /* Read ... */ |
0b883586 | 3506 | regcache->raw_read (fpnum, raw_buf); |
28fc6740 | 3507 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3508 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3509 | /* ... Write. */ |
10eaee5f | 3510 | regcache->raw_write (fpnum, raw_buf); |
28fc6740 AC |
3511 | } |
3512 | else | |
1ba53b71 L |
3513 | { |
3514 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3515 | ||
1dbcd68c WT |
3516 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3517 | { | |
3518 | ULONGEST upper, lower; | |
3519 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3520 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3521 | ||
3522 | /* New values from input value. */ | |
3523 | regnum -= tdep->bnd0_regnum; | |
3524 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3525 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3526 | ||
3527 | /* Fetching register buffer. */ | |
0b883586 SM |
3528 | regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3529 | raw_buf); | |
1dbcd68c WT |
3530 | |
3531 | upper = ~upper; | |
3532 | ||
3533 | /* Set register bits. */ | |
3534 | memcpy (raw_buf, &lower, 8); | |
3535 | memcpy (raw_buf + 8, &upper, 8); | |
3536 | ||
10eaee5f | 3537 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf); |
1dbcd68c | 3538 | } |
01f9f808 MS |
3539 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3540 | { | |
3541 | regnum -= tdep->k0_regnum; | |
3542 | ||
10eaee5f | 3543 | regcache->raw_write (tdep->k0_regnum + regnum, buf); |
01f9f808 MS |
3544 | } |
3545 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3546 | { | |
3547 | regnum -= tdep->zmm0_regnum; | |
3548 | ||
3549 | if (regnum < num_lower_zmm_regs) | |
3550 | { | |
3551 | /* Write lower 128bits. */ | |
10eaee5f | 3552 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3553 | /* Write upper 128bits. */ |
10eaee5f | 3554 | regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16); |
01f9f808 MS |
3555 | } |
3556 | else | |
3557 | { | |
3558 | /* Write lower 128bits. */ | |
10eaee5f SM |
3559 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum |
3560 | - num_lower_zmm_regs, buf); | |
01f9f808 | 3561 | /* Write upper 128bits. */ |
10eaee5f SM |
3562 | regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum |
3563 | - num_lower_zmm_regs, buf + 16); | |
01f9f808 MS |
3564 | } |
3565 | /* Write upper 256bits. */ | |
10eaee5f | 3566 | regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32); |
01f9f808 | 3567 | } |
1dbcd68c | 3568 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3569 | { |
3570 | regnum -= tdep->ymm0_regnum; | |
3571 | ||
3572 | /* ... Write lower 128bits. */ | |
10eaee5f | 3573 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
c131fcee | 3574 | /* ... Write upper 128bits. */ |
10eaee5f | 3575 | regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16); |
c131fcee | 3576 | } |
01f9f808 MS |
3577 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3578 | { | |
3579 | regnum -= tdep->ymm16_regnum; | |
3580 | ||
3581 | /* ... Write lower 128bits. */ | |
10eaee5f | 3582 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3583 | /* ... Write upper 128bits. */ |
10eaee5f | 3584 | regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16); |
01f9f808 | 3585 | } |
c131fcee | 3586 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3587 | { |
3588 | int gpnum = regnum - tdep->ax_regnum; | |
3589 | ||
3590 | /* Read ... */ | |
0b883586 | 3591 | regcache->raw_read (gpnum, raw_buf); |
1ba53b71 L |
3592 | /* ... Modify ... (always little endian). */ |
3593 | memcpy (raw_buf, buf, 2); | |
3594 | /* ... Write. */ | |
10eaee5f | 3595 | regcache->raw_write (gpnum, raw_buf); |
1ba53b71 L |
3596 | } |
3597 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3598 | { | |
1ba53b71 L |
3599 | int gpnum = regnum - tdep->al_regnum; |
3600 | ||
3601 | /* Read ... We read both lower and upper registers. */ | |
0b883586 | 3602 | regcache->raw_read (gpnum % 4, raw_buf); |
1ba53b71 L |
3603 | /* ... Modify ... (always little endian). */ |
3604 | if (gpnum >= 4) | |
3605 | memcpy (raw_buf + 1, buf, 1); | |
3606 | else | |
3607 | memcpy (raw_buf, buf, 1); | |
3608 | /* ... Write. */ | |
10eaee5f | 3609 | regcache->raw_write (gpnum % 4, raw_buf); |
1ba53b71 L |
3610 | } |
3611 | else | |
3612 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3613 | } | |
28fc6740 | 3614 | } |
62e5fd57 MK |
3615 | |
3616 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3617 | ||
3618 | int | |
3619 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3620 | struct agent_expr *ax, int regnum) | |
3621 | { | |
3622 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3623 | ||
3624 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3625 | { | |
3626 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3627 | not care and collect everything... */ | |
3628 | int i; | |
3629 | ||
3630 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3631 | for (i = 0; i < 8; i++) | |
3632 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3633 | return 0; | |
3634 | } | |
3635 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3636 | { | |
3637 | regnum -= tdep->bnd0_regnum; | |
3638 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3639 | return 0; | |
3640 | } | |
3641 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3642 | { | |
3643 | regnum -= tdep->k0_regnum; | |
3644 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3645 | return 0; | |
3646 | } | |
3647 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3648 | { | |
3649 | regnum -= tdep->zmm0_regnum; | |
3650 | if (regnum < num_lower_zmm_regs) | |
3651 | { | |
3652 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3653 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3654 | } | |
3655 | else | |
3656 | { | |
3657 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3658 | - num_lower_zmm_regs); | |
3659 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3660 | - num_lower_zmm_regs); | |
3661 | } | |
3662 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3663 | return 0; | |
3664 | } | |
3665 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3666 | { | |
3667 | regnum -= tdep->ymm0_regnum; | |
3668 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3669 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3670 | return 0; | |
3671 | } | |
3672 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3673 | { | |
3674 | regnum -= tdep->ymm16_regnum; | |
3675 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3676 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3677 | return 0; | |
3678 | } | |
3679 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3680 | { | |
3681 | int gpnum = regnum - tdep->ax_regnum; | |
3682 | ||
3683 | ax_reg_mask (ax, gpnum); | |
3684 | return 0; | |
3685 | } | |
3686 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3687 | { | |
3688 | int gpnum = regnum - tdep->al_regnum; | |
3689 | ||
3690 | ax_reg_mask (ax, gpnum % 4); | |
3691 | return 0; | |
3692 | } | |
3693 | else | |
3694 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3695 | return 1; | |
3696 | } | |
ff2e87ac AC |
3697 | \f |
3698 | ||
ff2e87ac AC |
3699 | /* Return the register number of the register allocated by GCC after |
3700 | REGNUM, or -1 if there is no such register. */ | |
3701 | ||
3702 | static int | |
3703 | i386_next_regnum (int regnum) | |
3704 | { | |
3705 | /* GCC allocates the registers in the order: | |
3706 | ||
3707 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3708 | ||
3709 | Since storing a variable in %esp doesn't make any sense we return | |
3710 | -1 for %ebp and for %esp itself. */ | |
3711 | static int next_regnum[] = | |
3712 | { | |
3713 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3714 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3715 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3716 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3717 | -1, -1, /* Slots for %esp and %ebp. */ | |
3718 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3719 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3720 | }; | |
3721 | ||
de5b9bb9 | 3722 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3723 | return next_regnum[regnum]; |
28fc6740 | 3724 | |
ff2e87ac AC |
3725 | return -1; |
3726 | } | |
3727 | ||
3728 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3729 | needs any special handling. */ | |
d7a0d72c | 3730 | |
3a1e71e3 | 3731 | static int |
1777feb0 MS |
3732 | i386_convert_register_p (struct gdbarch *gdbarch, |
3733 | int regnum, struct type *type) | |
d7a0d72c | 3734 | { |
de5b9bb9 MK |
3735 | int len = TYPE_LENGTH (type); |
3736 | ||
ff2e87ac AC |
3737 | /* Values may be spread across multiple registers. Most debugging |
3738 | formats aren't expressive enough to specify the locations, so | |
3739 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3740 | have a length that is a multiple of the word size, since GCC |
3741 | doesn't seem to put any other types into registers. */ | |
3742 | if (len > 4 && len % 4 == 0) | |
3743 | { | |
3744 | int last_regnum = regnum; | |
3745 | ||
3746 | while (len > 4) | |
3747 | { | |
3748 | last_regnum = i386_next_regnum (last_regnum); | |
3749 | len -= 4; | |
3750 | } | |
3751 | ||
3752 | if (last_regnum != -1) | |
3753 | return 1; | |
3754 | } | |
ff2e87ac | 3755 | |
0abe36f5 | 3756 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3757 | } |
3758 | ||
ff2e87ac AC |
3759 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3760 | return its contents in TO. */ | |
ac27f131 | 3761 | |
8dccd430 | 3762 | static int |
ff2e87ac | 3763 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3764 | struct type *type, gdb_byte *to, |
3765 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3766 | { |
20a6ec49 | 3767 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3768 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3769 | |
20a6ec49 | 3770 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3771 | return i387_register_to_value (frame, regnum, type, to, |
3772 | optimizedp, unavailablep); | |
ff2e87ac | 3773 | |
fd35795f | 3774 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3775 | |
3776 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3777 | |
de5b9bb9 MK |
3778 | while (len > 0) |
3779 | { | |
3780 | gdb_assert (regnum != -1); | |
20a6ec49 | 3781 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3782 | |
8dccd430 PA |
3783 | if (!get_frame_register_bytes (frame, regnum, 0, |
3784 | register_size (gdbarch, regnum), | |
3785 | to, optimizedp, unavailablep)) | |
3786 | return 0; | |
3787 | ||
de5b9bb9 MK |
3788 | regnum = i386_next_regnum (regnum); |
3789 | len -= 4; | |
42835c2b | 3790 | to += 4; |
de5b9bb9 | 3791 | } |
8dccd430 PA |
3792 | |
3793 | *optimizedp = *unavailablep = 0; | |
3794 | return 1; | |
ac27f131 MK |
3795 | } |
3796 | ||
ff2e87ac AC |
3797 | /* Write the contents FROM of a value of type TYPE into register |
3798 | REGNUM in frame FRAME. */ | |
ac27f131 | 3799 | |
3a1e71e3 | 3800 | static void |
ff2e87ac | 3801 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3802 | struct type *type, const gdb_byte *from) |
ac27f131 | 3803 | { |
de5b9bb9 | 3804 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3805 | |
20a6ec49 | 3806 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3807 | { |
d532c08f MK |
3808 | i387_value_to_register (frame, regnum, type, from); |
3809 | return; | |
3810 | } | |
3d261580 | 3811 | |
fd35795f | 3812 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3813 | |
3814 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3815 | |
de5b9bb9 MK |
3816 | while (len > 0) |
3817 | { | |
3818 | gdb_assert (regnum != -1); | |
875f8d0e | 3819 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3820 | |
42835c2b | 3821 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3822 | regnum = i386_next_regnum (regnum); |
3823 | len -= 4; | |
42835c2b | 3824 | from += 4; |
de5b9bb9 | 3825 | } |
ac27f131 | 3826 | } |
ff2e87ac | 3827 | \f |
7fdafb5a MK |
3828 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3829 | in the general-purpose register set REGSET to register cache | |
3830 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3831 | |
20187ed5 | 3832 | void |
473f17b0 MK |
3833 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3834 | int regnum, const void *gregs, size_t len) | |
3835 | { | |
ac7936df | 3836 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3837 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3838 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3839 | int i; |
3840 | ||
1528345d | 3841 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3842 | |
3843 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3844 | { | |
3845 | if ((regnum == i || regnum == -1) | |
3846 | && tdep->gregset_reg_offset[i] != -1) | |
73e1c03f | 3847 | regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]); |
473f17b0 MK |
3848 | } |
3849 | } | |
3850 | ||
7fdafb5a MK |
3851 | /* Collect register REGNUM from the register cache REGCACHE and store |
3852 | it in the buffer specified by GREGS and LEN as described by the | |
3853 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3854 | all registers in REGSET. */ | |
3855 | ||
ecc37a5a | 3856 | static void |
7fdafb5a MK |
3857 | i386_collect_gregset (const struct regset *regset, |
3858 | const struct regcache *regcache, | |
3859 | int regnum, void *gregs, size_t len) | |
3860 | { | |
ac7936df | 3861 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3862 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9a3c8263 | 3863 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3864 | int i; |
3865 | ||
1528345d | 3866 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3867 | |
3868 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3869 | { | |
3870 | if ((regnum == i || regnum == -1) | |
3871 | && tdep->gregset_reg_offset[i] != -1) | |
34a79281 | 3872 | regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]); |
7fdafb5a MK |
3873 | } |
3874 | } | |
3875 | ||
3876 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3877 | in the floating-point register set REGSET to register cache | |
3878 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3879 | |
3880 | static void | |
3881 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3882 | int regnum, const void *fpregs, size_t len) | |
3883 | { | |
ac7936df | 3884 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3885 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
473f17b0 | 3886 | |
66a72d25 MK |
3887 | if (len == I387_SIZEOF_FXSAVE) |
3888 | { | |
3889 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3890 | return; | |
3891 | } | |
3892 | ||
1528345d | 3893 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3894 | i387_supply_fsave (regcache, regnum, fpregs); |
3895 | } | |
8446b36a | 3896 | |
2f305df1 MK |
3897 | /* Collect register REGNUM from the register cache REGCACHE and store |
3898 | it in the buffer specified by FPREGS and LEN as described by the | |
3899 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3900 | all registers in REGSET. */ | |
7fdafb5a MK |
3901 | |
3902 | static void | |
3903 | i386_collect_fpregset (const struct regset *regset, | |
3904 | const struct regcache *regcache, | |
3905 | int regnum, void *fpregs, size_t len) | |
3906 | { | |
ac7936df | 3907 | struct gdbarch *gdbarch = regcache->arch (); |
09424cff | 3908 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7fdafb5a MK |
3909 | |
3910 | if (len == I387_SIZEOF_FXSAVE) | |
3911 | { | |
3912 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3913 | return; | |
3914 | } | |
3915 | ||
1528345d | 3916 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3917 | i387_collect_fsave (regcache, regnum, fpregs); |
3918 | } | |
3919 | ||
ecc37a5a AA |
3920 | /* Register set definitions. */ |
3921 | ||
3922 | const struct regset i386_gregset = | |
3923 | { | |
3924 | NULL, i386_supply_gregset, i386_collect_gregset | |
3925 | }; | |
3926 | ||
8f0435f7 | 3927 | const struct regset i386_fpregset = |
ecc37a5a AA |
3928 | { |
3929 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3930 | }; | |
3931 | ||
490496c3 | 3932 | /* Default iterator over core file register note sections. */ |
8446b36a | 3933 | |
490496c3 AA |
3934 | void |
3935 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3936 | iterate_over_regset_sections_cb *cb, | |
3937 | void *cb_data, | |
3938 | const struct regcache *regcache) | |
8446b36a MK |
3939 | { |
3940 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3941 | ||
a616bb94 AH |
3942 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL, |
3943 | cb_data); | |
490496c3 | 3944 | if (tdep->sizeof_fpregset) |
a616bb94 AH |
3945 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, |
3946 | NULL, cb_data); | |
8446b36a | 3947 | } |
473f17b0 | 3948 | \f |
fc338970 | 3949 | |
fc338970 | 3950 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3951 | |
3952 | CORE_ADDR | |
e17a4113 UW |
3953 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3954 | CORE_ADDR pc, char *name) | |
c906108c | 3955 | { |
e17a4113 UW |
3956 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3957 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3958 | ||
3959 | /* jmp *(dest) */ | |
3960 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3961 | { |
e17a4113 UW |
3962 | unsigned long indirect = |
3963 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3964 | struct minimal_symbol *indsym = |
7cbd4a93 | 3965 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
c9d95fa3 | 3966 | const char *symname = indsym ? indsym->linkage_name () : 0; |
c906108c | 3967 | |
c5aa993b | 3968 | if (symname) |
c906108c | 3969 | { |
61012eef GB |
3970 | if (startswith (symname, "__imp_") |
3971 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3972 | return name ? 1 : |
3973 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3974 | } |
3975 | } | |
fc338970 | 3976 | return 0; /* Not a trampoline. */ |
c906108c | 3977 | } |
fc338970 MK |
3978 | \f |
3979 | ||
10458914 DJ |
3980 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3981 | routine. */ | |
8201327c | 3982 | |
4bd207ef | 3983 | int |
10458914 | 3984 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3985 | { |
10458914 | 3986 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3987 | const char *name; |
911bc6ee MK |
3988 | |
3989 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3990 | return (name && strcmp ("_sigtramp", name) == 0); |
3991 | } | |
3992 | \f | |
3993 | ||
fc338970 MK |
3994 | /* We have two flavours of disassembly. The machinery on this page |
3995 | deals with switching between those. */ | |
c906108c SS |
3996 | |
3997 | static int | |
a89aa300 | 3998 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3999 | { |
5e3397bb MK |
4000 | gdb_assert (disassembly_flavor == att_flavor |
4001 | || disassembly_flavor == intel_flavor); | |
4002 | ||
f995bbe8 | 4003 | info->disassembler_options = disassembly_flavor; |
5e3397bb | 4004 | |
6394c606 | 4005 | return default_print_insn (pc, info); |
7a292a7a | 4006 | } |
fc338970 | 4007 | \f |
3ce1502b | 4008 | |
8201327c MK |
4009 | /* There are a few i386 architecture variants that differ only |
4010 | slightly from the generic i386 target. For now, we don't give them | |
4011 | their own source file, but include them here. As a consequence, | |
4012 | they'll always be included. */ | |
3ce1502b | 4013 | |
8201327c | 4014 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4015 | |
10458914 DJ |
4016 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4017 | routine. */ | |
911bc6ee | 4018 | |
8201327c | 4019 | static int |
10458914 | 4020 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 4021 | { |
10458914 | 4022 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4023 | const char *name; |
911bc6ee | 4024 | |
05b4bd79 | 4025 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4026 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4027 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4028 | || strcmp ("sigvechandler", name) == 0)); |
4029 | } | |
d2a7c97a | 4030 | |
10458914 DJ |
4031 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4032 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4033 | |
3a1e71e3 | 4034 | static CORE_ADDR |
10458914 | 4035 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4036 | { |
e17a4113 UW |
4037 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4038 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4039 | gdb_byte buf[4]; |
acd5c798 | 4040 | CORE_ADDR sp; |
3ce1502b | 4041 | |
10458914 | 4042 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4043 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4044 | |
e17a4113 | 4045 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4046 | } |
55aa24fb SDJ |
4047 | |
4048 | \f | |
4049 | ||
4050 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4051 | gdbarch.h. */ | |
4052 | ||
4053 | int | |
4054 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4055 | { | |
4056 | return (*s == '$' /* Literal number. */ | |
4057 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4058 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4059 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4060 | } | |
4061 | ||
5acfdbae SDJ |
4062 | /* Helper function for i386_stap_parse_special_token. |
4063 | ||
4064 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4065 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4066 | ||
af2d9bee | 4067 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4068 | otherwise. */ |
4069 | ||
af2d9bee | 4070 | static bool |
5acfdbae SDJ |
4071 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, |
4072 | struct stap_parse_info *p) | |
4073 | { | |
4074 | const char *s = p->arg; | |
4075 | ||
4076 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4077 | { | |
af2d9bee | 4078 | bool got_minus[3]; |
5acfdbae SDJ |
4079 | int i; |
4080 | long displacements[3]; | |
4081 | const char *start; | |
4082 | char *regname; | |
4083 | int len; | |
4084 | struct stoken str; | |
4085 | char *endp; | |
4086 | ||
af2d9bee | 4087 | got_minus[0] = false; |
5acfdbae SDJ |
4088 | if (*s == '+') |
4089 | ++s; | |
4090 | else if (*s == '-') | |
4091 | { | |
4092 | ++s; | |
af2d9bee | 4093 | got_minus[0] = true; |
5acfdbae SDJ |
4094 | } |
4095 | ||
d7b30f67 | 4096 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4097 | return false; |
d7b30f67 | 4098 | |
5acfdbae SDJ |
4099 | displacements[0] = strtol (s, &endp, 10); |
4100 | s = endp; | |
4101 | ||
4102 | if (*s != '+' && *s != '-') | |
4103 | { | |
4104 | /* We are not dealing with a triplet. */ | |
af2d9bee | 4105 | return false; |
5acfdbae SDJ |
4106 | } |
4107 | ||
af2d9bee | 4108 | got_minus[1] = false; |
5acfdbae SDJ |
4109 | if (*s == '+') |
4110 | ++s; | |
4111 | else | |
4112 | { | |
4113 | ++s; | |
af2d9bee | 4114 | got_minus[1] = true; |
5acfdbae SDJ |
4115 | } |
4116 | ||
d7b30f67 | 4117 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4118 | return false; |
d7b30f67 | 4119 | |
5acfdbae SDJ |
4120 | displacements[1] = strtol (s, &endp, 10); |
4121 | s = endp; | |
4122 | ||
4123 | if (*s != '+' && *s != '-') | |
4124 | { | |
4125 | /* We are not dealing with a triplet. */ | |
af2d9bee | 4126 | return false; |
5acfdbae SDJ |
4127 | } |
4128 | ||
af2d9bee | 4129 | got_minus[2] = false; |
5acfdbae SDJ |
4130 | if (*s == '+') |
4131 | ++s; | |
4132 | else | |
4133 | { | |
4134 | ++s; | |
af2d9bee | 4135 | got_minus[2] = true; |
5acfdbae SDJ |
4136 | } |
4137 | ||
d7b30f67 | 4138 | if (!isdigit ((unsigned char) *s)) |
af2d9bee | 4139 | return false; |
d7b30f67 | 4140 | |
5acfdbae SDJ |
4141 | displacements[2] = strtol (s, &endp, 10); |
4142 | s = endp; | |
4143 | ||
4144 | if (*s != '(' || s[1] != '%') | |
af2d9bee | 4145 | return false; |
5acfdbae SDJ |
4146 | |
4147 | s += 2; | |
4148 | start = s; | |
4149 | ||
4150 | while (isalnum (*s)) | |
4151 | ++s; | |
4152 | ||
4153 | if (*s++ != ')') | |
af2d9bee | 4154 | return false; |
5acfdbae | 4155 | |
d7b30f67 | 4156 | len = s - start - 1; |
224c3ddb | 4157 | regname = (char *) alloca (len + 1); |
5acfdbae SDJ |
4158 | |
4159 | strncpy (regname, start, len); | |
4160 | regname[len] = '\0'; | |
4161 | ||
4162 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4163 | error (_("Invalid register name `%s' on expression `%s'."), | |
4164 | regname, p->saved_arg); | |
4165 | ||
4166 | for (i = 0; i < 3; i++) | |
4167 | { | |
410a0ff2 SDJ |
4168 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4169 | write_exp_elt_type | |
4170 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4171 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4172 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4173 | if (got_minus[i]) |
410a0ff2 | 4174 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4175 | } |
4176 | ||
410a0ff2 | 4177 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4178 | str.ptr = regname; |
4179 | str.length = len; | |
410a0ff2 SDJ |
4180 | write_exp_string (&p->pstate, str); |
4181 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4182 | |
410a0ff2 SDJ |
4183 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4184 | write_exp_elt_type (&p->pstate, | |
4185 | builtin_type (gdbarch)->builtin_data_ptr); | |
4186 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4187 | |
410a0ff2 SDJ |
4188 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4189 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4190 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4191 | |
410a0ff2 SDJ |
4192 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4193 | write_exp_elt_type (&p->pstate, | |
4194 | lookup_pointer_type (p->arg_type)); | |
4195 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4196 | |
410a0ff2 | 4197 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4198 | |
4199 | p->arg = s; | |
4200 | ||
af2d9bee | 4201 | return true; |
5acfdbae SDJ |
4202 | } |
4203 | ||
af2d9bee | 4204 | return false; |
5acfdbae SDJ |
4205 | } |
4206 | ||
4207 | /* Helper function for i386_stap_parse_special_token. | |
4208 | ||
4209 | This function parses operands of the form `register base + | |
4210 | (register index * size) + offset', as represented in | |
4211 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4212 | ||
af2d9bee | 4213 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4214 | otherwise. */ |
4215 | ||
af2d9bee | 4216 | static bool |
5acfdbae SDJ |
4217 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, |
4218 | struct stap_parse_info *p) | |
4219 | { | |
4220 | const char *s = p->arg; | |
4221 | ||
4222 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4223 | { | |
af2d9bee | 4224 | bool offset_minus = false; |
5acfdbae | 4225 | long offset = 0; |
af2d9bee | 4226 | bool size_minus = false; |
5acfdbae SDJ |
4227 | long size = 0; |
4228 | const char *start; | |
4229 | char *base; | |
4230 | int len_base; | |
4231 | char *index; | |
4232 | int len_index; | |
4233 | struct stoken base_token, index_token; | |
4234 | ||
4235 | if (*s == '+') | |
4236 | ++s; | |
4237 | else if (*s == '-') | |
4238 | { | |
4239 | ++s; | |
af2d9bee | 4240 | offset_minus = true; |
5acfdbae SDJ |
4241 | } |
4242 | ||
4243 | if (offset_minus && !isdigit (*s)) | |
af2d9bee | 4244 | return false; |
5acfdbae SDJ |
4245 | |
4246 | if (isdigit (*s)) | |
4247 | { | |
4248 | char *endp; | |
4249 | ||
4250 | offset = strtol (s, &endp, 10); | |
4251 | s = endp; | |
4252 | } | |
4253 | ||
4254 | if (*s != '(' || s[1] != '%') | |
af2d9bee | 4255 | return false; |
5acfdbae SDJ |
4256 | |
4257 | s += 2; | |
4258 | start = s; | |
4259 | ||
4260 | while (isalnum (*s)) | |
4261 | ++s; | |
4262 | ||
4263 | if (*s != ',' || s[1] != '%') | |
af2d9bee | 4264 | return false; |
5acfdbae SDJ |
4265 | |
4266 | len_base = s - start; | |
224c3ddb | 4267 | base = (char *) alloca (len_base + 1); |
5acfdbae SDJ |
4268 | strncpy (base, start, len_base); |
4269 | base[len_base] = '\0'; | |
4270 | ||
4271 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4272 | error (_("Invalid register name `%s' on expression `%s'."), | |
4273 | base, p->saved_arg); | |
4274 | ||
4275 | s += 2; | |
4276 | start = s; | |
4277 | ||
4278 | while (isalnum (*s)) | |
4279 | ++s; | |
4280 | ||
4281 | len_index = s - start; | |
224c3ddb | 4282 | index = (char *) alloca (len_index + 1); |
5acfdbae SDJ |
4283 | strncpy (index, start, len_index); |
4284 | index[len_index] = '\0'; | |
4285 | ||
4286 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4287 | error (_("Invalid register name `%s' on expression `%s'."), | |
4288 | index, p->saved_arg); | |
4289 | ||
4290 | if (*s != ',' && *s != ')') | |
af2d9bee | 4291 | return false; |
5acfdbae SDJ |
4292 | |
4293 | if (*s == ',') | |
4294 | { | |
4295 | char *endp; | |
4296 | ||
4297 | ++s; | |
4298 | if (*s == '+') | |
4299 | ++s; | |
4300 | else if (*s == '-') | |
4301 | { | |
4302 | ++s; | |
af2d9bee | 4303 | size_minus = true; |
5acfdbae SDJ |
4304 | } |
4305 | ||
4306 | size = strtol (s, &endp, 10); | |
4307 | s = endp; | |
4308 | ||
4309 | if (*s != ')') | |
af2d9bee | 4310 | return false; |
5acfdbae SDJ |
4311 | } |
4312 | ||
4313 | ++s; | |
4314 | ||
4315 | if (offset) | |
4316 | { | |
410a0ff2 SDJ |
4317 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4318 | write_exp_elt_type (&p->pstate, | |
4319 | builtin_type (gdbarch)->builtin_long); | |
4320 | write_exp_elt_longcst (&p->pstate, offset); | |
4321 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4322 | if (offset_minus) |
410a0ff2 | 4323 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4324 | } |
4325 | ||
410a0ff2 | 4326 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4327 | base_token.ptr = base; |
4328 | base_token.length = len_base; | |
410a0ff2 SDJ |
4329 | write_exp_string (&p->pstate, base_token); |
4330 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4331 | |
4332 | if (offset) | |
410a0ff2 | 4333 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4334 | |
410a0ff2 | 4335 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4336 | index_token.ptr = index; |
4337 | index_token.length = len_index; | |
410a0ff2 SDJ |
4338 | write_exp_string (&p->pstate, index_token); |
4339 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4340 | |
4341 | if (size) | |
4342 | { | |
410a0ff2 SDJ |
4343 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4344 | write_exp_elt_type (&p->pstate, | |
4345 | builtin_type (gdbarch)->builtin_long); | |
4346 | write_exp_elt_longcst (&p->pstate, size); | |
4347 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4348 | if (size_minus) |
410a0ff2 SDJ |
4349 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4350 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4351 | } |
4352 | ||
410a0ff2 | 4353 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4354 | |
410a0ff2 SDJ |
4355 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4356 | write_exp_elt_type (&p->pstate, | |
4357 | lookup_pointer_type (p->arg_type)); | |
4358 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4359 | |
410a0ff2 | 4360 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4361 | |
4362 | p->arg = s; | |
4363 | ||
af2d9bee | 4364 | return true; |
5acfdbae SDJ |
4365 | } |
4366 | ||
af2d9bee | 4367 | return false; |
5acfdbae SDJ |
4368 | } |
4369 | ||
55aa24fb SDJ |
4370 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4371 | gdbarch.h. */ | |
4372 | ||
4373 | int | |
4374 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4375 | struct stap_parse_info *p) | |
4376 | { | |
55aa24fb SDJ |
4377 | /* In order to parse special tokens, we use a state-machine that go |
4378 | through every known token and try to get a match. */ | |
4379 | enum | |
4380 | { | |
4381 | TRIPLET, | |
4382 | THREE_ARG_DISPLACEMENT, | |
4383 | DONE | |
570dc176 TT |
4384 | }; |
4385 | int current_state; | |
55aa24fb SDJ |
4386 | |
4387 | current_state = TRIPLET; | |
4388 | ||
4389 | /* The special tokens to be parsed here are: | |
4390 | ||
4391 | - `register base + (register index * size) + offset', as represented | |
4392 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4393 | ||
4394 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4395 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4396 | ||
4397 | while (current_state != DONE) | |
4398 | { | |
55aa24fb SDJ |
4399 | switch (current_state) |
4400 | { | |
4401 | case TRIPLET: | |
5acfdbae SDJ |
4402 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4403 | return 1; | |
4404 | break; | |
4405 | ||
55aa24fb | 4406 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4407 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4408 | return 1; | |
4409 | break; | |
55aa24fb SDJ |
4410 | } |
4411 | ||
4412 | /* Advancing to the next state. */ | |
4413 | ++current_state; | |
4414 | } | |
4415 | ||
4416 | return 0; | |
4417 | } | |
4418 | ||
7d7571f0 SDJ |
4419 | /* Implementation of 'gdbarch_stap_adjust_register', as defined in |
4420 | gdbarch.h. */ | |
4421 | ||
6b78c3f8 | 4422 | static std::string |
7d7571f0 | 4423 | i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p, |
6b78c3f8 | 4424 | const std::string ®name, int regnum) |
7d7571f0 SDJ |
4425 | { |
4426 | static const std::unordered_set<std::string> reg_assoc | |
4427 | = { "ax", "bx", "cx", "dx", | |
4428 | "si", "di", "bp", "sp" }; | |
4429 | ||
6b78c3f8 AB |
4430 | /* If we are dealing with a register whose size is less than the size |
4431 | specified by the "[-]N@" prefix, and it is one of the registers that | |
4432 | we know has an extended variant available, then use the extended | |
4433 | version of the register instead. */ | |
4434 | if (register_size (gdbarch, regnum) < TYPE_LENGTH (p->arg_type) | |
4435 | && reg_assoc.find (regname) != reg_assoc.end ()) | |
4436 | return "e" + regname; | |
7d7571f0 | 4437 | |
6b78c3f8 AB |
4438 | /* Otherwise, just use the requested register. */ |
4439 | return regname; | |
7d7571f0 SDJ |
4440 | } |
4441 | ||
8201327c | 4442 | \f |
3ce1502b | 4443 | |
ac04f72b TT |
4444 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4445 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4446 | ||
4447 | static const char * | |
4448 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4449 | { | |
4450 | return "(x86_64|i.86)"; | |
4451 | } | |
4452 | ||
4453 | \f | |
4454 | ||
1d509aa6 MM |
4455 | /* Implement the "in_indirect_branch_thunk" gdbarch function. */ |
4456 | ||
4457 | static bool | |
4458 | i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4459 | { | |
4460 | return x86_in_indirect_branch_thunk (pc, i386_register_names, | |
4461 | I386_EAX_REGNUM, I386_EIP_REGNUM); | |
4462 | } | |
4463 | ||
8201327c | 4464 | /* Generic ELF. */ |
d2a7c97a | 4465 | |
8201327c MK |
4466 | void |
4467 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4468 | { | |
05c0465e SDJ |
4469 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4470 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4471 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4472 | NULL }; | |
4473 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4474 | NULL }; | |
4475 | ||
c4fc7f1b MK |
4476 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4477 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4478 | |
4479 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4480 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4481 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4482 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4483 | stap_register_indirection_prefixes); | |
4484 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4485 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4486 | set_gdbarch_stap_is_single_operand (gdbarch, |
4487 | i386_stap_is_single_operand); | |
4488 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4489 | i386_stap_parse_special_token); | |
7d7571f0 SDJ |
4490 | set_gdbarch_stap_adjust_register (gdbarch, |
4491 | i386_stap_adjust_register); | |
1d509aa6 MM |
4492 | |
4493 | set_gdbarch_in_indirect_branch_thunk (gdbarch, | |
4494 | i386_in_indirect_branch_thunk); | |
8201327c | 4495 | } |
3ce1502b | 4496 | |
8201327c | 4497 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4498 | |
8201327c MK |
4499 | void |
4500 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4501 | { | |
4502 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4503 | |
8201327c MK |
4504 | /* System V Release 4 uses ELF. */ |
4505 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4506 | |
dfe01d39 | 4507 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4508 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4509 | ||
911bc6ee | 4510 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4511 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4512 | tdep->sc_pc_offset = 36 + 14 * 4; |
4513 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4514 | |
8201327c | 4515 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4516 | } |
4517 | ||
8201327c | 4518 | \f |
2acceee2 | 4519 | |
38c968cf AC |
4520 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4521 | and "sse". */ | |
4522 | ||
4523 | static struct reggroup *i386_sse_reggroup; | |
4524 | static struct reggroup *i386_mmx_reggroup; | |
4525 | ||
4526 | static void | |
4527 | i386_init_reggroups (void) | |
4528 | { | |
4529 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4530 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4531 | } | |
4532 | ||
4533 | static void | |
4534 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4535 | { | |
4536 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4537 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4538 | reggroup_add (gdbarch, general_reggroup); | |
4539 | reggroup_add (gdbarch, float_reggroup); | |
4540 | reggroup_add (gdbarch, all_reggroup); | |
4541 | reggroup_add (gdbarch, save_reggroup); | |
4542 | reggroup_add (gdbarch, restore_reggroup); | |
4543 | reggroup_add (gdbarch, vector_reggroup); | |
4544 | reggroup_add (gdbarch, system_reggroup); | |
4545 | } | |
4546 | ||
4547 | int | |
4548 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4549 | struct reggroup *group) | |
4550 | { | |
c131fcee L |
4551 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4552 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 | 4553 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
798a7429 SM |
4554 | bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p, |
4555 | mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4556 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4557 | |
1ba53b71 L |
4558 | /* Don't include pseudo registers, except for MMX, in any register |
4559 | groups. */ | |
c131fcee | 4560 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4561 | return 0; |
4562 | ||
c131fcee | 4563 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4564 | return 0; |
4565 | ||
c131fcee | 4566 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4567 | return 0; |
4568 | ||
4569 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4570 | if (group == i386_mmx_reggroup) |
4571 | return mmx_regnum_p; | |
1ba53b71 | 4572 | |
51547df6 | 4573 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4574 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4575 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4576 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4577 | if (group == i386_sse_reggroup) |
01f9f808 | 4578 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4579 | |
4580 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4581 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4582 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4583 | ||
22049425 MS |
4584 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4585 | == X86_XSTATE_AVX_AVX512_MASK); | |
4586 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4587 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4588 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4589 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4590 | |
38c968cf | 4591 | if (group == vector_reggroup) |
c131fcee | 4592 | return (mmx_regnum_p |
01f9f808 MS |
4593 | || (zmm_regnum_p && avx512_p) |
4594 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4595 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4596 | || mxcsr_regnum_p); | |
1ba53b71 L |
4597 | |
4598 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4599 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4600 | if (group == float_reggroup) |
4601 | return fp_regnum_p; | |
1ba53b71 | 4602 | |
c131fcee L |
4603 | /* For "info reg all", don't include upper YMM registers nor XMM |
4604 | registers when AVX is supported. */ | |
4605 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4606 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4607 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4608 | if (group == all_reggroup |
01f9f808 MS |
4609 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4610 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4611 | || ymmh_regnum_p | |
4612 | || ymmh_avx512_regnum_p | |
4613 | || zmmh_regnum_p)) | |
c131fcee L |
4614 | return 0; |
4615 | ||
1dbcd68c WT |
4616 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4617 | if (group == all_reggroup | |
df7e5265 | 4618 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4619 | return bnd_regnum_p; |
4620 | ||
4621 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4622 | if (group == all_reggroup | |
df7e5265 | 4623 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4624 | return 0; |
4625 | ||
4626 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4627 | if (group == all_reggroup | |
df7e5265 | 4628 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4629 | return mpx_ctrl_regnum_p; |
4630 | ||
38c968cf | 4631 | if (group == general_reggroup) |
1ba53b71 L |
4632 | return (!fp_regnum_p |
4633 | && !mmx_regnum_p | |
c131fcee L |
4634 | && !mxcsr_regnum_p |
4635 | && !xmm_regnum_p | |
01f9f808 | 4636 | && !xmm_avx512_regnum_p |
c131fcee | 4637 | && !ymm_regnum_p |
1dbcd68c | 4638 | && !ymmh_regnum_p |
01f9f808 MS |
4639 | && !ymm_avx512_regnum_p |
4640 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4641 | && !bndr_regnum_p |
4642 | && !bnd_regnum_p | |
01f9f808 MS |
4643 | && !mpx_ctrl_regnum_p |
4644 | && !zmm_regnum_p | |
51547df6 MS |
4645 | && !zmmh_regnum_p |
4646 | && !pkru_regnum_p); | |
acd5c798 | 4647 | |
38c968cf AC |
4648 | return default_register_reggroup_p (gdbarch, regnum, group); |
4649 | } | |
38c968cf | 4650 | \f |
acd5c798 | 4651 | |
f837910f MK |
4652 | /* Get the ARGIth function argument for the current function. */ |
4653 | ||
42c466d7 | 4654 | static CORE_ADDR |
143985b7 AF |
4655 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4656 | struct type *type) | |
4657 | { | |
e17a4113 UW |
4658 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4659 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4660 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4661 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4662 | } |
4663 | ||
7ad10968 HZ |
4664 | #define PREFIX_REPZ 0x01 |
4665 | #define PREFIX_REPNZ 0x02 | |
4666 | #define PREFIX_LOCK 0x04 | |
4667 | #define PREFIX_DATA 0x08 | |
4668 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4669 | |
7ad10968 HZ |
4670 | /* operand size */ |
4671 | enum | |
4672 | { | |
4673 | OT_BYTE = 0, | |
4674 | OT_WORD, | |
4675 | OT_LONG, | |
cf648174 | 4676 | OT_QUAD, |
a3c4230a | 4677 | OT_DQUAD, |
7ad10968 | 4678 | }; |
473f17b0 | 4679 | |
7ad10968 HZ |
4680 | /* i386 arith/logic operations */ |
4681 | enum | |
4682 | { | |
4683 | OP_ADDL, | |
4684 | OP_ORL, | |
4685 | OP_ADCL, | |
4686 | OP_SBBL, | |
4687 | OP_ANDL, | |
4688 | OP_SUBL, | |
4689 | OP_XORL, | |
4690 | OP_CMPL, | |
4691 | }; | |
5716833c | 4692 | |
7ad10968 HZ |
4693 | struct i386_record_s |
4694 | { | |
cf648174 | 4695 | struct gdbarch *gdbarch; |
7ad10968 | 4696 | struct regcache *regcache; |
df61f520 | 4697 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4698 | CORE_ADDR addr; |
4699 | int aflag; | |
4700 | int dflag; | |
4701 | int override; | |
4702 | uint8_t modrm; | |
4703 | uint8_t mod, reg, rm; | |
4704 | int ot; | |
cf648174 HZ |
4705 | uint8_t rex_x; |
4706 | uint8_t rex_b; | |
4707 | int rip_offset; | |
4708 | int popl_esp_hack; | |
4709 | const int *regmap; | |
7ad10968 | 4710 | }; |
5716833c | 4711 | |
99c1624c PA |
4712 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4713 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4714 | |
7ad10968 HZ |
4715 | static int |
4716 | i386_record_modrm (struct i386_record_s *irp) | |
4717 | { | |
cf648174 | 4718 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4719 | |
4ffa4fc7 PA |
4720 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4721 | return -1; | |
4722 | ||
7ad10968 HZ |
4723 | irp->addr++; |
4724 | irp->mod = (irp->modrm >> 6) & 3; | |
4725 | irp->reg = (irp->modrm >> 3) & 7; | |
4726 | irp->rm = irp->modrm & 7; | |
5716833c | 4727 | |
7ad10968 HZ |
4728 | return 0; |
4729 | } | |
d2a7c97a | 4730 | |
99c1624c PA |
4731 | /* Extract the memory address that the current instruction writes to, |
4732 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4733 | |
7ad10968 | 4734 | static int |
cf648174 | 4735 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4736 | { |
cf648174 | 4737 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4738 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4739 | gdb_byte buf[4]; | |
4740 | ULONGEST offset64; | |
21d0e8a4 | 4741 | |
7ad10968 | 4742 | *addr = 0; |
1e87984a | 4743 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4744 | { |
1e87984a | 4745 | /* 32/64 bits */ |
7ad10968 HZ |
4746 | int havesib = 0; |
4747 | uint8_t scale = 0; | |
648d0c8b | 4748 | uint8_t byte; |
7ad10968 HZ |
4749 | uint8_t index = 0; |
4750 | uint8_t base = irp->rm; | |
896fb97d | 4751 | |
7ad10968 HZ |
4752 | if (base == 4) |
4753 | { | |
4754 | havesib = 1; | |
4ffa4fc7 PA |
4755 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4756 | return -1; | |
7ad10968 | 4757 | irp->addr++; |
648d0c8b MS |
4758 | scale = (byte >> 6) & 3; |
4759 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4760 | base = (byte & 7); | |
7ad10968 | 4761 | } |
cf648174 | 4762 | base |= irp->rex_b; |
21d0e8a4 | 4763 | |
7ad10968 HZ |
4764 | switch (irp->mod) |
4765 | { | |
4766 | case 0: | |
4767 | if ((base & 7) == 5) | |
4768 | { | |
4769 | base = 0xff; | |
4ffa4fc7 PA |
4770 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4771 | return -1; | |
7ad10968 | 4772 | irp->addr += 4; |
60a1502a | 4773 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4774 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4775 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4776 | } |
7ad10968 HZ |
4777 | break; |
4778 | case 1: | |
4ffa4fc7 PA |
4779 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4780 | return -1; | |
7ad10968 | 4781 | irp->addr++; |
60a1502a | 4782 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4783 | break; |
4784 | case 2: | |
4ffa4fc7 PA |
4785 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4786 | return -1; | |
60a1502a | 4787 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4788 | irp->addr += 4; |
4789 | break; | |
4790 | } | |
356a6b3e | 4791 | |
60a1502a | 4792 | offset64 = 0; |
7ad10968 | 4793 | if (base != 0xff) |
dda83cd7 | 4794 | { |
cf648174 HZ |
4795 | if (base == 4 && irp->popl_esp_hack) |
4796 | *addr += irp->popl_esp_hack; | |
4797 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
dda83cd7 | 4798 | &offset64); |
7ad10968 | 4799 | } |
cf648174 | 4800 | if (irp->aflag == 2) |
dda83cd7 | 4801 | { |
60a1502a | 4802 | *addr += offset64; |
dda83cd7 | 4803 | } |
cf648174 | 4804 | else |
dda83cd7 | 4805 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4806 | |
7ad10968 HZ |
4807 | if (havesib && (index != 4 || scale != 0)) |
4808 | { | |
cf648174 | 4809 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
dda83cd7 | 4810 | &offset64); |
cf648174 | 4811 | if (irp->aflag == 2) |
60a1502a | 4812 | *addr += offset64 << scale; |
cf648174 | 4813 | else |
60a1502a | 4814 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4815 | } |
e85596e0 L |
4816 | |
4817 | if (!irp->aflag) | |
4818 | { | |
4819 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4820 | address from 32-bit to 64-bit. */ | |
4821 | *addr = (uint32_t) *addr; | |
4822 | } | |
7ad10968 HZ |
4823 | } |
4824 | else | |
4825 | { | |
4826 | /* 16 bits */ | |
4827 | switch (irp->mod) | |
4828 | { | |
4829 | case 0: | |
4830 | if (irp->rm == 6) | |
4831 | { | |
4ffa4fc7 PA |
4832 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4833 | return -1; | |
7ad10968 | 4834 | irp->addr += 2; |
60a1502a | 4835 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4836 | irp->rm = 0; |
4837 | goto no_rm; | |
4838 | } | |
7ad10968 HZ |
4839 | break; |
4840 | case 1: | |
4ffa4fc7 PA |
4841 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4842 | return -1; | |
7ad10968 | 4843 | irp->addr++; |
60a1502a | 4844 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4845 | break; |
4846 | case 2: | |
4ffa4fc7 PA |
4847 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4848 | return -1; | |
7ad10968 | 4849 | irp->addr += 2; |
60a1502a | 4850 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4851 | break; |
4852 | } | |
c4fc7f1b | 4853 | |
7ad10968 HZ |
4854 | switch (irp->rm) |
4855 | { | |
4856 | case 0: | |
cf648174 HZ |
4857 | regcache_raw_read_unsigned (irp->regcache, |
4858 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4859 | &offset64); |
60a1502a | 4860 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4861 | regcache_raw_read_unsigned (irp->regcache, |
4862 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4863 | &offset64); |
60a1502a | 4864 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4865 | break; |
4866 | case 1: | |
cf648174 HZ |
4867 | regcache_raw_read_unsigned (irp->regcache, |
4868 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4869 | &offset64); |
60a1502a | 4870 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4871 | regcache_raw_read_unsigned (irp->regcache, |
4872 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4873 | &offset64); |
60a1502a | 4874 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4875 | break; |
4876 | case 2: | |
cf648174 HZ |
4877 | regcache_raw_read_unsigned (irp->regcache, |
4878 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4879 | &offset64); |
60a1502a | 4880 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4881 | regcache_raw_read_unsigned (irp->regcache, |
4882 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4883 | &offset64); |
60a1502a | 4884 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4885 | break; |
4886 | case 3: | |
cf648174 HZ |
4887 | regcache_raw_read_unsigned (irp->regcache, |
4888 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4889 | &offset64); |
60a1502a | 4890 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4891 | regcache_raw_read_unsigned (irp->regcache, |
4892 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4893 | &offset64); |
60a1502a | 4894 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4895 | break; |
4896 | case 4: | |
cf648174 HZ |
4897 | regcache_raw_read_unsigned (irp->regcache, |
4898 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4899 | &offset64); |
60a1502a | 4900 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4901 | break; |
4902 | case 5: | |
cf648174 HZ |
4903 | regcache_raw_read_unsigned (irp->regcache, |
4904 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4905 | &offset64); |
60a1502a | 4906 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4907 | break; |
4908 | case 6: | |
cf648174 HZ |
4909 | regcache_raw_read_unsigned (irp->regcache, |
4910 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4911 | &offset64); |
60a1502a | 4912 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4913 | break; |
4914 | case 7: | |
cf648174 HZ |
4915 | regcache_raw_read_unsigned (irp->regcache, |
4916 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4917 | &offset64); |
60a1502a | 4918 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4919 | break; |
4920 | } | |
4921 | *addr &= 0xffff; | |
4922 | } | |
c4fc7f1b | 4923 | |
01fe1b41 | 4924 | no_rm: |
7ad10968 HZ |
4925 | return 0; |
4926 | } | |
c4fc7f1b | 4927 | |
99c1624c PA |
4928 | /* Record the address and contents of the memory that will be changed |
4929 | by the current instruction. Return -1 if something goes wrong, 0 | |
4930 | otherwise. */ | |
356a6b3e | 4931 | |
7ad10968 HZ |
4932 | static int |
4933 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4934 | { | |
cf648174 HZ |
4935 | struct gdbarch *gdbarch = irp->gdbarch; |
4936 | uint64_t addr; | |
356a6b3e | 4937 | |
d7877f7e | 4938 | if (irp->override >= 0) |
7ad10968 | 4939 | { |
25ea693b | 4940 | if (record_full_memory_query) |
dda83cd7 SM |
4941 | { |
4942 | if (yquery (_("\ | |
bb08c432 HZ |
4943 | Process record ignores the memory change of instruction at address %s\n\ |
4944 | because it can't get the value of the segment register.\n\ | |
4945 | Do you want to stop the program?"), | |
dda83cd7 | 4946 | paddress (gdbarch, irp->orig_addr))) |
651ce16a | 4947 | return -1; |
dda83cd7 | 4948 | } |
bb08c432 | 4949 | |
7ad10968 HZ |
4950 | return 0; |
4951 | } | |
61113f8b | 4952 | |
7ad10968 HZ |
4953 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4954 | return -1; | |
96297dab | 4955 | |
25ea693b | 4956 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4957 | return -1; |
a62cc96e | 4958 | |
7ad10968 HZ |
4959 | return 0; |
4960 | } | |
b6197528 | 4961 | |
99c1624c PA |
4962 | /* Record the effects of a push operation. Return -1 if something |
4963 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4964 | |
4965 | static int | |
4966 | i386_record_push (struct i386_record_s *irp, int size) | |
4967 | { | |
648d0c8b | 4968 | ULONGEST addr; |
cf648174 | 4969 | |
25ea693b MM |
4970 | if (record_full_arch_list_add_reg (irp->regcache, |
4971 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4972 | return -1; |
4973 | regcache_raw_read_unsigned (irp->regcache, | |
4974 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4975 | &addr); |
25ea693b | 4976 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4977 | return -1; |
4978 | ||
4979 | return 0; | |
4980 | } | |
4981 | ||
0289bdd7 MS |
4982 | |
4983 | /* Defines contents to record. */ | |
4984 | #define I386_SAVE_FPU_REGS 0xfffd | |
4985 | #define I386_SAVE_FPU_ENV 0xfffe | |
4986 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4987 | ||
99c1624c PA |
4988 | /* Record the values of the floating point registers which will be |
4989 | changed by the current instruction. Returns -1 if something is | |
4990 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4991 | |
4992 | static int i386_record_floats (struct gdbarch *gdbarch, | |
dda83cd7 SM |
4993 | struct i386_record_s *ir, |
4994 | uint32_t iregnum) | |
0289bdd7 MS |
4995 | { |
4996 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4997 | int i; | |
4998 | ||
4999 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
5000 | happen. Currently we store st0-st7 registers, but we need not store all | |
5001 | registers all the time, in future we use ftag register and record only | |
5002 | those who are not marked as an empty. */ | |
5003 | ||
5004 | if (I386_SAVE_FPU_REGS == iregnum) | |
5005 | { | |
5006 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
dda83cd7 SM |
5007 | { |
5008 | if (record_full_arch_list_add_reg (ir->regcache, i)) | |
5009 | return -1; | |
5010 | } | |
0289bdd7 MS |
5011 | } |
5012 | else if (I386_SAVE_FPU_ENV == iregnum) | |
5013 | { | |
5014 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5015 | { | |
25ea693b | 5016 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 5017 | return -1; |
0289bdd7 MS |
5018 | } |
5019 | } | |
5020 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
5021 | { | |
5022 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5023 | { | |
dda83cd7 SM |
5024 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
5025 | return -1; | |
0289bdd7 MS |
5026 | } |
5027 | } | |
5028 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
dda83cd7 | 5029 | (iregnum <= I387_FOP_REGNUM (tdep))) |
0289bdd7 | 5030 | { |
25ea693b | 5031 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
dda83cd7 | 5032 | return -1; |
0289bdd7 MS |
5033 | } |
5034 | else | |
5035 | { | |
5036 | /* Parameter error. */ | |
5037 | return -1; | |
5038 | } | |
5039 | if(I386_SAVE_FPU_ENV != iregnum) | |
5040 | { | |
5041 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5042 | { | |
25ea693b | 5043 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 5044 | return -1; |
0289bdd7 MS |
5045 | } |
5046 | } | |
5047 | return 0; | |
5048 | } | |
5049 | ||
99c1624c PA |
5050 | /* Parse the current instruction, and record the values of the |
5051 | registers and memory that will be changed by the current | |
5052 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5053 | |
25ea693b MM |
5054 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5055 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5056 | |
a6b808b4 | 5057 | int |
7ad10968 | 5058 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5059 | CORE_ADDR input_addr) |
7ad10968 | 5060 | { |
60a1502a | 5061 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5062 | int prefixes = 0; |
580879fc | 5063 | int regnum = 0; |
425b824a | 5064 | uint32_t opcode; |
f4644a3f | 5065 | uint8_t opcode8; |
648d0c8b | 5066 | ULONGEST addr; |
975c21ab | 5067 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5068 | struct i386_record_s ir; |
0289bdd7 | 5069 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5070 | uint8_t rex_w = -1; |
5071 | uint8_t rex_r = 0; | |
7ad10968 | 5072 | |
8408d274 | 5073 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5074 | ir.regcache = regcache; |
648d0c8b MS |
5075 | ir.addr = input_addr; |
5076 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5077 | ir.aflag = 1; |
5078 | ir.dflag = 1; | |
cf648174 HZ |
5079 | ir.override = -1; |
5080 | ir.popl_esp_hack = 0; | |
a3c4230a | 5081 | ir.regmap = tdep->record_regmap; |
cf648174 | 5082 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5083 | |
5084 | if (record_debug > 1) | |
5085 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
dda83cd7 | 5086 | "addr = %s\n", |
5af949e3 | 5087 | paddress (gdbarch, ir.addr)); |
7ad10968 HZ |
5088 | |
5089 | /* prefixes */ | |
5090 | while (1) | |
5091 | { | |
4ffa4fc7 PA |
5092 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5093 | return -1; | |
7ad10968 | 5094 | ir.addr++; |
425b824a | 5095 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5096 | { |
01fe1b41 | 5097 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5098 | prefixes |= PREFIX_REPZ; |
5099 | break; | |
01fe1b41 | 5100 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5101 | prefixes |= PREFIX_REPNZ; |
5102 | break; | |
01fe1b41 | 5103 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5104 | prefixes |= PREFIX_LOCK; |
5105 | break; | |
01fe1b41 | 5106 | case CS_PREFIX_OPCODE: |
cf648174 | 5107 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5108 | break; |
01fe1b41 | 5109 | case SS_PREFIX_OPCODE: |
cf648174 | 5110 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5111 | break; |
01fe1b41 | 5112 | case DS_PREFIX_OPCODE: |
cf648174 | 5113 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5114 | break; |
01fe1b41 | 5115 | case ES_PREFIX_OPCODE: |
cf648174 | 5116 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5117 | break; |
01fe1b41 | 5118 | case FS_PREFIX_OPCODE: |
cf648174 | 5119 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5120 | break; |
01fe1b41 | 5121 | case GS_PREFIX_OPCODE: |
cf648174 | 5122 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5123 | break; |
01fe1b41 | 5124 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5125 | prefixes |= PREFIX_DATA; |
5126 | break; | |
01fe1b41 | 5127 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5128 | prefixes |= PREFIX_ADDR; |
5129 | break; | |
dda83cd7 SM |
5130 | case 0x40: /* i386 inc %eax */ |
5131 | case 0x41: /* i386 inc %ecx */ | |
5132 | case 0x42: /* i386 inc %edx */ | |
5133 | case 0x43: /* i386 inc %ebx */ | |
5134 | case 0x44: /* i386 inc %esp */ | |
5135 | case 0x45: /* i386 inc %ebp */ | |
5136 | case 0x46: /* i386 inc %esi */ | |
5137 | case 0x47: /* i386 inc %edi */ | |
5138 | case 0x48: /* i386 dec %eax */ | |
5139 | case 0x49: /* i386 dec %ecx */ | |
5140 | case 0x4a: /* i386 dec %edx */ | |
5141 | case 0x4b: /* i386 dec %ebx */ | |
5142 | case 0x4c: /* i386 dec %esp */ | |
5143 | case 0x4d: /* i386 dec %ebp */ | |
5144 | case 0x4e: /* i386 dec %esi */ | |
5145 | case 0x4f: /* i386 dec %edi */ | |
5146 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
5147 | { | |
5148 | /* REX */ | |
5149 | rex_w = (opcode8 >> 3) & 1; | |
5150 | rex_r = (opcode8 & 0x4) << 1; | |
5151 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5152 | ir.rex_b = (opcode8 & 0x1) << 3; | |
5153 | } | |
d691bec7 MS |
5154 | else /* 32 bit target */ |
5155 | goto out_prefixes; | |
dda83cd7 | 5156 | break; |
7ad10968 HZ |
5157 | default: |
5158 | goto out_prefixes; | |
5159 | break; | |
5160 | } | |
5161 | } | |
01fe1b41 | 5162 | out_prefixes: |
cf648174 HZ |
5163 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5164 | { | |
5165 | ir.dflag = 2; | |
5166 | } | |
5167 | else | |
5168 | { | |
5169 | if (prefixes & PREFIX_DATA) | |
dda83cd7 | 5170 | ir.dflag ^= 1; |
cf648174 | 5171 | } |
7ad10968 HZ |
5172 | if (prefixes & PREFIX_ADDR) |
5173 | ir.aflag ^= 1; | |
cf648174 HZ |
5174 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5175 | ir.aflag = 2; | |
7ad10968 | 5176 | |
1777feb0 | 5177 | /* Now check op code. */ |
425b824a | 5178 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5179 | reswitch: |
7ad10968 HZ |
5180 | switch (opcode) |
5181 | { | |
5182 | case 0x0f: | |
4ffa4fc7 PA |
5183 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5184 | return -1; | |
7ad10968 | 5185 | ir.addr++; |
a3c4230a | 5186 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5187 | goto reswitch; |
5188 | break; | |
93924b6b | 5189 | |
a38bba38 | 5190 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5191 | case 0x01: |
5192 | case 0x02: | |
5193 | case 0x03: | |
5194 | case 0x04: | |
5195 | case 0x05: | |
5196 | case 0x08: | |
5197 | case 0x09: | |
5198 | case 0x0a: | |
5199 | case 0x0b: | |
5200 | case 0x0c: | |
5201 | case 0x0d: | |
5202 | case 0x10: | |
5203 | case 0x11: | |
5204 | case 0x12: | |
5205 | case 0x13: | |
5206 | case 0x14: | |
5207 | case 0x15: | |
5208 | case 0x18: | |
5209 | case 0x19: | |
5210 | case 0x1a: | |
5211 | case 0x1b: | |
5212 | case 0x1c: | |
5213 | case 0x1d: | |
5214 | case 0x20: | |
5215 | case 0x21: | |
5216 | case 0x22: | |
5217 | case 0x23: | |
5218 | case 0x24: | |
5219 | case 0x25: | |
5220 | case 0x28: | |
5221 | case 0x29: | |
5222 | case 0x2a: | |
5223 | case 0x2b: | |
5224 | case 0x2c: | |
5225 | case 0x2d: | |
5226 | case 0x30: | |
5227 | case 0x31: | |
5228 | case 0x32: | |
5229 | case 0x33: | |
5230 | case 0x34: | |
5231 | case 0x35: | |
5232 | case 0x38: | |
5233 | case 0x39: | |
5234 | case 0x3a: | |
5235 | case 0x3b: | |
5236 | case 0x3c: | |
5237 | case 0x3d: | |
5238 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5239 | { | |
5240 | if ((opcode & 1) == 0) | |
5241 | ir.ot = OT_BYTE; | |
5242 | else | |
5243 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5244 | |
7ad10968 HZ |
5245 | switch ((opcode >> 1) & 3) |
5246 | { | |
a38bba38 | 5247 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5248 | if (i386_record_modrm (&ir)) |
5249 | return -1; | |
5250 | if (ir.mod != 3) | |
5251 | { | |
5252 | if (i386_record_lea_modrm (&ir)) | |
5253 | return -1; | |
5254 | } | |
5255 | else | |
5256 | { | |
dda83cd7 | 5257 | ir.rm |= ir.rex_b; |
cf648174 | 5258 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5259 | ir.rm &= 0x3; |
25ea693b | 5260 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5261 | } |
5262 | break; | |
a38bba38 | 5263 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5264 | if (i386_record_modrm (&ir)) |
5265 | return -1; | |
dda83cd7 | 5266 | ir.reg |= rex_r; |
cf648174 | 5267 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5268 | ir.reg &= 0x3; |
25ea693b | 5269 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5270 | break; |
a38bba38 | 5271 | case 2: /* OP A, Iv */ |
25ea693b | 5272 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5273 | break; |
5274 | } | |
5275 | } | |
25ea693b | 5276 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5277 | break; |
42fdc8df | 5278 | |
a38bba38 | 5279 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5280 | case 0x81: |
5281 | case 0x82: | |
5282 | case 0x83: | |
5283 | if (i386_record_modrm (&ir)) | |
5284 | return -1; | |
8201327c | 5285 | |
7ad10968 HZ |
5286 | if (ir.reg != OP_CMPL) |
5287 | { | |
5288 | if ((opcode & 1) == 0) | |
5289 | ir.ot = OT_BYTE; | |
5290 | else | |
5291 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5292 | |
7ad10968 HZ |
5293 | if (ir.mod != 3) |
5294 | { | |
dda83cd7 SM |
5295 | if (opcode == 0x83) |
5296 | ir.rip_offset = 1; | |
5297 | else | |
5298 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5299 | if (i386_record_lea_modrm (&ir)) |
5300 | return -1; | |
5301 | } | |
5302 | else | |
25ea693b | 5303 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5304 | } |
25ea693b | 5305 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5306 | break; |
5e3397bb | 5307 | |
a38bba38 | 5308 | case 0x40: /* inc */ |
7ad10968 HZ |
5309 | case 0x41: |
5310 | case 0x42: | |
5311 | case 0x43: | |
5312 | case 0x44: | |
5313 | case 0x45: | |
5314 | case 0x46: | |
5315 | case 0x47: | |
a38bba38 MS |
5316 | |
5317 | case 0x48: /* dec */ | |
7ad10968 HZ |
5318 | case 0x49: |
5319 | case 0x4a: | |
5320 | case 0x4b: | |
5321 | case 0x4c: | |
5322 | case 0x4d: | |
5323 | case 0x4e: | |
5324 | case 0x4f: | |
a38bba38 | 5325 | |
25ea693b MM |
5326 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5327 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5328 | break; |
acd5c798 | 5329 | |
a38bba38 | 5330 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5331 | case 0xf7: |
5332 | if ((opcode & 1) == 0) | |
5333 | ir.ot = OT_BYTE; | |
5334 | else | |
5335 | ir.ot = ir.dflag + OT_WORD; | |
5336 | if (i386_record_modrm (&ir)) | |
5337 | return -1; | |
acd5c798 | 5338 | |
cf648174 | 5339 | if (ir.mod != 3 && ir.reg == 0) |
dda83cd7 | 5340 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5341 | |
7ad10968 HZ |
5342 | switch (ir.reg) |
5343 | { | |
a38bba38 | 5344 | case 0: /* test */ |
25ea693b | 5345 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5346 | break; |
a38bba38 MS |
5347 | case 2: /* not */ |
5348 | case 3: /* neg */ | |
7ad10968 HZ |
5349 | if (ir.mod != 3) |
5350 | { | |
5351 | if (i386_record_lea_modrm (&ir)) | |
5352 | return -1; | |
5353 | } | |
5354 | else | |
5355 | { | |
dda83cd7 | 5356 | ir.rm |= ir.rex_b; |
cf648174 | 5357 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5358 | ir.rm &= 0x3; |
25ea693b | 5359 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5360 | } |
a38bba38 | 5361 | if (ir.reg == 3) /* neg */ |
25ea693b | 5362 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5363 | break; |
a38bba38 MS |
5364 | case 4: /* mul */ |
5365 | case 5: /* imul */ | |
5366 | case 6: /* div */ | |
5367 | case 7: /* idiv */ | |
25ea693b | 5368 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5369 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5370 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5371 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5372 | break; |
5373 | default: | |
5374 | ir.addr -= 2; | |
5375 | opcode = opcode << 8 | ir.modrm; | |
5376 | goto no_support; | |
5377 | break; | |
5378 | } | |
5379 | break; | |
5380 | ||
a38bba38 MS |
5381 | case 0xfe: /* GRP4 */ |
5382 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5383 | if (i386_record_modrm (&ir)) |
5384 | return -1; | |
5385 | if (ir.reg >= 2 && opcode == 0xfe) | |
5386 | { | |
5387 | ir.addr -= 2; | |
5388 | opcode = opcode << 8 | ir.modrm; | |
5389 | goto no_support; | |
5390 | } | |
7ad10968 HZ |
5391 | switch (ir.reg) |
5392 | { | |
a38bba38 MS |
5393 | case 0: /* inc */ |
5394 | case 1: /* dec */ | |
dda83cd7 | 5395 | if ((opcode & 1) == 0) |
cf648174 | 5396 | ir.ot = OT_BYTE; |
dda83cd7 | 5397 | else |
cf648174 | 5398 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5399 | if (ir.mod != 3) |
5400 | { | |
5401 | if (i386_record_lea_modrm (&ir)) | |
5402 | return -1; | |
5403 | } | |
5404 | else | |
5405 | { | |
cf648174 HZ |
5406 | ir.rm |= ir.rex_b; |
5407 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5408 | ir.rm &= 0x3; |
25ea693b | 5409 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5410 | } |
25ea693b | 5411 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5412 | break; |
a38bba38 | 5413 | case 2: /* call */ |
dda83cd7 SM |
5414 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5415 | ir.dflag = 2; | |
cf648174 | 5416 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5417 | return -1; |
25ea693b | 5418 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5419 | break; |
a38bba38 | 5420 | case 3: /* lcall */ |
25ea693b | 5421 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5422 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5423 | return -1; |
25ea693b | 5424 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5425 | break; |
a38bba38 MS |
5426 | case 4: /* jmp */ |
5427 | case 5: /* ljmp */ | |
25ea693b | 5428 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5429 | break; |
a38bba38 | 5430 | case 6: /* push */ |
dda83cd7 SM |
5431 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5432 | ir.dflag = 2; | |
cf648174 HZ |
5433 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5434 | return -1; | |
7ad10968 HZ |
5435 | break; |
5436 | default: | |
5437 | ir.addr -= 2; | |
5438 | opcode = opcode << 8 | ir.modrm; | |
5439 | goto no_support; | |
5440 | break; | |
5441 | } | |
5442 | break; | |
5443 | ||
a38bba38 | 5444 | case 0x84: /* test */ |
7ad10968 HZ |
5445 | case 0x85: |
5446 | case 0xa8: | |
5447 | case 0xa9: | |
25ea693b | 5448 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5449 | break; |
5450 | ||
a38bba38 | 5451 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5452 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5453 | break; |
5454 | ||
a38bba38 | 5455 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5456 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5457 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5458 | break; |
5459 | ||
a38bba38 | 5460 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5461 | case 0x69: |
5462 | case 0x6b: | |
5463 | ir.ot = ir.dflag + OT_WORD; | |
5464 | if (i386_record_modrm (&ir)) | |
5465 | return -1; | |
cf648174 | 5466 | if (opcode == 0x69) |
dda83cd7 | 5467 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5468 | else if (opcode == 0x6b) |
dda83cd7 | 5469 | ir.rip_offset = 1; |
cf648174 HZ |
5470 | ir.reg |= rex_r; |
5471 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5472 | ir.reg &= 0x3; |
25ea693b MM |
5473 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5474 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5475 | break; |
5476 | ||
a38bba38 | 5477 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5478 | case 0x0fc1: |
5479 | if ((opcode & 1) == 0) | |
5480 | ir.ot = OT_BYTE; | |
5481 | else | |
5482 | ir.ot = ir.dflag + OT_WORD; | |
5483 | if (i386_record_modrm (&ir)) | |
5484 | return -1; | |
cf648174 | 5485 | ir.reg |= rex_r; |
7ad10968 HZ |
5486 | if (ir.mod == 3) |
5487 | { | |
cf648174 | 5488 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5489 | ir.reg &= 0x3; |
25ea693b | 5490 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5491 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5492 | ir.rm &= 0x3; |
25ea693b | 5493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5494 | } |
5495 | else | |
5496 | { | |
5497 | if (i386_record_lea_modrm (&ir)) | |
5498 | return -1; | |
cf648174 | 5499 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5500 | ir.reg &= 0x3; |
25ea693b | 5501 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5502 | } |
25ea693b | 5503 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5504 | break; |
5505 | ||
a38bba38 | 5506 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5507 | case 0x0fb1: |
5508 | if ((opcode & 1) == 0) | |
5509 | ir.ot = OT_BYTE; | |
5510 | else | |
5511 | ir.ot = ir.dflag + OT_WORD; | |
5512 | if (i386_record_modrm (&ir)) | |
5513 | return -1; | |
5514 | if (ir.mod == 3) | |
5515 | { | |
dda83cd7 | 5516 | ir.reg |= rex_r; |
25ea693b | 5517 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5518 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5519 | ir.reg &= 0x3; |
25ea693b | 5520 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5521 | } |
5522 | else | |
5523 | { | |
25ea693b | 5524 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5525 | if (i386_record_lea_modrm (&ir)) |
5526 | return -1; | |
5527 | } | |
25ea693b | 5528 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5529 | break; |
5530 | ||
20b477a7 | 5531 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5532 | if (i386_record_modrm (&ir)) |
5533 | return -1; | |
5534 | if (ir.mod == 3) | |
5535 | { | |
20b477a7 LM |
5536 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5537 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5538 | has bits 111 (/7). */ | |
5539 | if (ir.reg == 6 || ir.reg == 7) | |
5540 | { | |
5541 | /* The storage register is described by the 3 R/M bits, but the | |
5542 | REX.B prefix may be used to give access to registers | |
5543 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5544 | in the range R8~R15. | |
5545 | ||
5546 | REX.W may also be used to access 64-bit registers, but we | |
5547 | already record entire registers and not just partial bits | |
5548 | of them. */ | |
5549 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5550 | /* These instructions also set conditional bits. */ | |
5551 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5552 | break; | |
5553 | } | |
5554 | else | |
5555 | { | |
5556 | /* We don't handle this particular instruction yet. */ | |
5557 | ir.addr -= 2; | |
5558 | opcode = opcode << 8 | ir.modrm; | |
5559 | goto no_support; | |
5560 | } | |
7ad10968 | 5561 | } |
25ea693b MM |
5562 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5563 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5564 | if (i386_record_lea_modrm (&ir)) |
5565 | return -1; | |
25ea693b | 5566 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5567 | break; |
5568 | ||
a38bba38 | 5569 | case 0x50: /* push */ |
7ad10968 HZ |
5570 | case 0x51: |
5571 | case 0x52: | |
5572 | case 0x53: | |
5573 | case 0x54: | |
5574 | case 0x55: | |
5575 | case 0x56: | |
5576 | case 0x57: | |
5577 | case 0x68: | |
5578 | case 0x6a: | |
cf648174 | 5579 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5580 | ir.dflag = 2; |
cf648174 HZ |
5581 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5582 | return -1; | |
5583 | break; | |
5584 | ||
a38bba38 MS |
5585 | case 0x06: /* push es */ |
5586 | case 0x0e: /* push cs */ | |
5587 | case 0x16: /* push ss */ | |
5588 | case 0x1e: /* push ds */ | |
cf648174 | 5589 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5590 | { |
cf648174 HZ |
5591 | ir.addr -= 1; |
5592 | goto no_support; | |
5593 | } | |
5594 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5595 | return -1; | |
5596 | break; | |
5597 | ||
a38bba38 MS |
5598 | case 0x0fa0: /* push fs */ |
5599 | case 0x0fa8: /* push gs */ | |
cf648174 | 5600 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5601 | { |
cf648174 HZ |
5602 | ir.addr -= 2; |
5603 | goto no_support; | |
5604 | } | |
5605 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5606 | return -1; |
cf648174 HZ |
5607 | break; |
5608 | ||
a38bba38 | 5609 | case 0x60: /* pusha */ |
cf648174 | 5610 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5611 | { |
cf648174 HZ |
5612 | ir.addr -= 1; |
5613 | goto no_support; | |
5614 | } | |
5615 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5616 | return -1; |
5617 | break; | |
5618 | ||
a38bba38 | 5619 | case 0x58: /* pop */ |
7ad10968 HZ |
5620 | case 0x59: |
5621 | case 0x5a: | |
5622 | case 0x5b: | |
5623 | case 0x5c: | |
5624 | case 0x5d: | |
5625 | case 0x5e: | |
5626 | case 0x5f: | |
25ea693b MM |
5627 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5628 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5629 | break; |
5630 | ||
a38bba38 | 5631 | case 0x61: /* popa */ |
cf648174 | 5632 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5633 | { |
cf648174 HZ |
5634 | ir.addr -= 1; |
5635 | goto no_support; | |
7ad10968 | 5636 | } |
425b824a MS |
5637 | for (regnum = X86_RECORD_REAX_REGNUM; |
5638 | regnum <= X86_RECORD_REDI_REGNUM; | |
5639 | regnum++) | |
25ea693b | 5640 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5641 | break; |
5642 | ||
a38bba38 | 5643 | case 0x8f: /* pop */ |
cf648174 HZ |
5644 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5645 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5646 | else | |
dda83cd7 | 5647 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5648 | if (i386_record_modrm (&ir)) |
5649 | return -1; | |
5650 | if (ir.mod == 3) | |
25ea693b | 5651 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5652 | else |
5653 | { | |
dda83cd7 | 5654 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5655 | if (i386_record_lea_modrm (&ir)) |
5656 | return -1; | |
5657 | } | |
25ea693b | 5658 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5659 | break; |
5660 | ||
a38bba38 | 5661 | case 0xc8: /* enter */ |
25ea693b | 5662 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 | 5663 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5664 | ir.dflag = 2; |
cf648174 | 5665 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 HZ |
5666 | return -1; |
5667 | break; | |
5668 | ||
a38bba38 | 5669 | case 0xc9: /* leave */ |
25ea693b MM |
5670 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5671 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5672 | break; |
5673 | ||
a38bba38 | 5674 | case 0x07: /* pop es */ |
cf648174 | 5675 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5676 | { |
cf648174 HZ |
5677 | ir.addr -= 1; |
5678 | goto no_support; | |
5679 | } | |
25ea693b MM |
5680 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5682 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5683 | break; |
5684 | ||
a38bba38 | 5685 | case 0x17: /* pop ss */ |
cf648174 | 5686 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5687 | { |
cf648174 HZ |
5688 | ir.addr -= 1; |
5689 | goto no_support; | |
5690 | } | |
25ea693b MM |
5691 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5692 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5693 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5694 | break; |
5695 | ||
a38bba38 | 5696 | case 0x1f: /* pop ds */ |
cf648174 | 5697 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5698 | { |
cf648174 HZ |
5699 | ir.addr -= 1; |
5700 | goto no_support; | |
5701 | } | |
25ea693b MM |
5702 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5703 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5704 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5705 | break; |
5706 | ||
a38bba38 | 5707 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5708 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5709 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5710 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5711 | break; |
5712 | ||
a38bba38 | 5713 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5714 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5715 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5716 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5717 | break; |
5718 | ||
a38bba38 | 5719 | case 0x88: /* mov */ |
7ad10968 HZ |
5720 | case 0x89: |
5721 | case 0xc6: | |
5722 | case 0xc7: | |
5723 | if ((opcode & 1) == 0) | |
5724 | ir.ot = OT_BYTE; | |
5725 | else | |
5726 | ir.ot = ir.dflag + OT_WORD; | |
5727 | ||
5728 | if (i386_record_modrm (&ir)) | |
5729 | return -1; | |
5730 | ||
5731 | if (ir.mod != 3) | |
5732 | { | |
dda83cd7 | 5733 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 | 5734 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
7ad10968 HZ |
5735 | if (i386_record_lea_modrm (&ir)) |
5736 | return -1; | |
5737 | } | |
5738 | else | |
5739 | { | |
dda83cd7 | 5740 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 HZ |
5741 | ir.rm |= ir.rex_b; |
5742 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5743 | ir.rm &= 0x3; |
25ea693b | 5744 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5745 | } |
7ad10968 | 5746 | break; |
cf648174 | 5747 | |
a38bba38 | 5748 | case 0x8a: /* mov */ |
7ad10968 HZ |
5749 | case 0x8b: |
5750 | if ((opcode & 1) == 0) | |
5751 | ir.ot = OT_BYTE; | |
5752 | else | |
5753 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5754 | if (i386_record_modrm (&ir)) |
5755 | return -1; | |
cf648174 HZ |
5756 | ir.reg |= rex_r; |
5757 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5758 | ir.reg &= 0x3; |
25ea693b | 5759 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5760 | break; |
7ad10968 | 5761 | |
a38bba38 | 5762 | case 0x8c: /* mov seg */ |
cf648174 | 5763 | if (i386_record_modrm (&ir)) |
7ad10968 | 5764 | return -1; |
cf648174 HZ |
5765 | if (ir.reg > 5) |
5766 | { | |
5767 | ir.addr -= 2; | |
5768 | opcode = opcode << 8 | ir.modrm; | |
5769 | goto no_support; | |
5770 | } | |
5771 | ||
5772 | if (ir.mod == 3) | |
25ea693b | 5773 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5774 | else |
5775 | { | |
5776 | ir.ot = OT_WORD; | |
5777 | if (i386_record_lea_modrm (&ir)) | |
5778 | return -1; | |
5779 | } | |
7ad10968 HZ |
5780 | break; |
5781 | ||
a38bba38 | 5782 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5783 | if (i386_record_modrm (&ir)) |
5784 | return -1; | |
7ad10968 HZ |
5785 | switch (ir.reg) |
5786 | { | |
5787 | case 0: | |
425b824a | 5788 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5789 | break; |
5790 | case 2: | |
425b824a | 5791 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5792 | break; |
5793 | case 3: | |
425b824a | 5794 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5795 | break; |
5796 | case 4: | |
425b824a | 5797 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5798 | break; |
5799 | case 5: | |
425b824a | 5800 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5801 | break; |
5802 | default: | |
5803 | ir.addr -= 2; | |
5804 | opcode = opcode << 8 | ir.modrm; | |
5805 | goto no_support; | |
5806 | break; | |
5807 | } | |
25ea693b MM |
5808 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5809 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5810 | break; |
5811 | ||
a38bba38 MS |
5812 | case 0x0fb6: /* movzbS */ |
5813 | case 0x0fb7: /* movzwS */ | |
5814 | case 0x0fbe: /* movsbS */ | |
5815 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5816 | if (i386_record_modrm (&ir)) |
5817 | return -1; | |
25ea693b | 5818 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5819 | break; |
5820 | ||
a38bba38 | 5821 | case 0x8d: /* lea */ |
7ad10968 HZ |
5822 | if (i386_record_modrm (&ir)) |
5823 | return -1; | |
5824 | if (ir.mod == 3) | |
5825 | { | |
5826 | ir.addr -= 2; | |
5827 | opcode = opcode << 8 | ir.modrm; | |
5828 | goto no_support; | |
5829 | } | |
7ad10968 | 5830 | ir.ot = ir.dflag; |
cf648174 HZ |
5831 | ir.reg |= rex_r; |
5832 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5833 | ir.reg &= 0x3; |
25ea693b | 5834 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5835 | break; |
5836 | ||
a38bba38 | 5837 | case 0xa0: /* mov EAX */ |
7ad10968 | 5838 | case 0xa1: |
a38bba38 MS |
5839 | |
5840 | case 0xd7: /* xlat */ | |
25ea693b | 5841 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5842 | break; |
5843 | ||
a38bba38 | 5844 | case 0xa2: /* mov EAX */ |
7ad10968 | 5845 | case 0xa3: |
d7877f7e | 5846 | if (ir.override >= 0) |
dda83cd7 SM |
5847 | { |
5848 | if (record_full_memory_query) | |
5849 | { | |
5850 | if (yquery (_("\ | |
bb08c432 HZ |
5851 | Process record ignores the memory change of instruction at address %s\n\ |
5852 | because it can't get the value of the segment register.\n\ | |
5853 | Do you want to stop the program?"), | |
dda83cd7 SM |
5854 | paddress (gdbarch, ir.orig_addr))) |
5855 | return -1; | |
5856 | } | |
cf648174 HZ |
5857 | } |
5858 | else | |
5859 | { | |
dda83cd7 | 5860 | if ((opcode & 1) == 0) |
cf648174 HZ |
5861 | ir.ot = OT_BYTE; |
5862 | else | |
5863 | ir.ot = ir.dflag + OT_WORD; | |
5864 | if (ir.aflag == 2) | |
5865 | { | |
dda83cd7 | 5866 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
4ffa4fc7 | 5867 | return -1; |
cf648174 | 5868 | ir.addr += 8; |
60a1502a | 5869 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 | 5870 | } |
dda83cd7 | 5871 | else if (ir.aflag) |
cf648174 | 5872 | { |
dda83cd7 | 5873 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
4ffa4fc7 | 5874 | return -1; |
cf648174 | 5875 | ir.addr += 4; |
dda83cd7 | 5876 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 | 5877 | } |
dda83cd7 | 5878 | else |
cf648174 | 5879 | { |
dda83cd7 | 5880 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
4ffa4fc7 | 5881 | return -1; |
cf648174 | 5882 | ir.addr += 2; |
dda83cd7 | 5883 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5884 | } |
25ea693b | 5885 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 | 5886 | return -1; |
dda83cd7 | 5887 | } |
7ad10968 HZ |
5888 | break; |
5889 | ||
a38bba38 | 5890 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5891 | case 0xb1: |
5892 | case 0xb2: | |
5893 | case 0xb3: | |
5894 | case 0xb4: | |
5895 | case 0xb5: | |
5896 | case 0xb6: | |
5897 | case 0xb7: | |
25ea693b MM |
5898 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5899 | ? ((opcode & 0x7) | ir.rex_b) | |
5900 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5901 | break; |
5902 | ||
a38bba38 | 5903 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5904 | case 0xb9: |
5905 | case 0xba: | |
5906 | case 0xbb: | |
5907 | case 0xbc: | |
5908 | case 0xbd: | |
5909 | case 0xbe: | |
5910 | case 0xbf: | |
25ea693b | 5911 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5912 | break; |
5913 | ||
a38bba38 | 5914 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5915 | case 0x92: |
5916 | case 0x93: | |
5917 | case 0x94: | |
5918 | case 0x95: | |
5919 | case 0x96: | |
5920 | case 0x97: | |
25ea693b MM |
5921 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5922 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5923 | break; |
5924 | ||
a38bba38 | 5925 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5926 | case 0x87: |
5927 | if ((opcode & 1) == 0) | |
5928 | ir.ot = OT_BYTE; | |
5929 | else | |
5930 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5931 | if (i386_record_modrm (&ir)) |
5932 | return -1; | |
7ad10968 HZ |
5933 | if (ir.mod == 3) |
5934 | { | |
86839d38 | 5935 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5936 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5937 | ir.rm &= 0x3; | |
25ea693b | 5938 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5939 | } |
5940 | else | |
5941 | { | |
5942 | if (i386_record_lea_modrm (&ir)) | |
5943 | return -1; | |
5944 | } | |
cf648174 HZ |
5945 | ir.reg |= rex_r; |
5946 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5947 | ir.reg &= 0x3; |
25ea693b | 5948 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5949 | break; |
5950 | ||
a38bba38 MS |
5951 | case 0xc4: /* les Gv */ |
5952 | case 0xc5: /* lds Gv */ | |
cf648174 | 5953 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5954 | { |
cf648174 HZ |
5955 | ir.addr -= 1; |
5956 | goto no_support; | |
5957 | } | |
d3f323f3 | 5958 | /* FALLTHROUGH */ |
a38bba38 MS |
5959 | case 0x0fb2: /* lss Gv */ |
5960 | case 0x0fb4: /* lfs Gv */ | |
5961 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5962 | if (i386_record_modrm (&ir)) |
5963 | return -1; | |
5964 | if (ir.mod == 3) | |
5965 | { | |
5966 | if (opcode > 0xff) | |
5967 | ir.addr -= 3; | |
5968 | else | |
5969 | ir.addr -= 2; | |
5970 | opcode = opcode << 8 | ir.modrm; | |
5971 | goto no_support; | |
5972 | } | |
7ad10968 HZ |
5973 | switch (opcode) |
5974 | { | |
a38bba38 | 5975 | case 0xc4: /* les Gv */ |
425b824a | 5976 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5977 | break; |
a38bba38 | 5978 | case 0xc5: /* lds Gv */ |
425b824a | 5979 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5980 | break; |
a38bba38 | 5981 | case 0x0fb2: /* lss Gv */ |
425b824a | 5982 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5983 | break; |
a38bba38 | 5984 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5985 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5986 | break; |
a38bba38 | 5987 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5988 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5989 | break; |
5990 | } | |
25ea693b MM |
5991 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5992 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5993 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5994 | break; |
5995 | ||
a38bba38 | 5996 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5997 | case 0xc1: |
5998 | case 0xd0: | |
5999 | case 0xd1: | |
6000 | case 0xd2: | |
6001 | case 0xd3: | |
6002 | if ((opcode & 1) == 0) | |
6003 | ir.ot = OT_BYTE; | |
6004 | else | |
6005 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
6006 | if (i386_record_modrm (&ir)) |
6007 | return -1; | |
7ad10968 HZ |
6008 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
6009 | { | |
6010 | if (i386_record_lea_modrm (&ir)) | |
6011 | return -1; | |
6012 | } | |
6013 | else | |
6014 | { | |
cf648174 HZ |
6015 | ir.rm |= ir.rex_b; |
6016 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 6017 | ir.rm &= 0x3; |
25ea693b | 6018 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 6019 | } |
25ea693b | 6020 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6021 | break; |
6022 | ||
6023 | case 0x0fa4: | |
6024 | case 0x0fa5: | |
6025 | case 0x0fac: | |
6026 | case 0x0fad: | |
6027 | if (i386_record_modrm (&ir)) | |
6028 | return -1; | |
6029 | if (ir.mod == 3) | |
6030 | { | |
25ea693b | 6031 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
6032 | return -1; |
6033 | } | |
6034 | else | |
6035 | { | |
6036 | if (i386_record_lea_modrm (&ir)) | |
6037 | return -1; | |
6038 | } | |
6039 | break; | |
6040 | ||
a38bba38 | 6041 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
6042 | case 0xd9: |
6043 | case 0xda: | |
6044 | case 0xdb: | |
6045 | case 0xdc: | |
6046 | case 0xdd: | |
6047 | case 0xde: | |
6048 | case 0xdf: | |
6049 | if (i386_record_modrm (&ir)) | |
6050 | return -1; | |
6051 | ir.reg |= ((opcode & 7) << 3); | |
6052 | if (ir.mod != 3) | |
6053 | { | |
1777feb0 | 6054 | /* Memory. */ |
955db0c0 | 6055 | uint64_t addr64; |
7ad10968 | 6056 | |
955db0c0 | 6057 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6058 | return -1; |
6059 | switch (ir.reg) | |
6060 | { | |
7ad10968 | 6061 | case 0x02: |
dda83cd7 SM |
6062 | case 0x12: |
6063 | case 0x22: | |
6064 | case 0x32: | |
0289bdd7 | 6065 | /* For fcom, ficom nothing to do. */ |
dda83cd7 | 6066 | break; |
7ad10968 | 6067 | case 0x03: |
dda83cd7 SM |
6068 | case 0x13: |
6069 | case 0x23: | |
6070 | case 0x33: | |
0289bdd7 | 6071 | /* For fcomp, ficomp pop FPU stack, store all. */ |
dda83cd7 SM |
6072 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6073 | return -1; | |
6074 | break; | |
6075 | case 0x00: | |
6076 | case 0x01: | |
7ad10968 HZ |
6077 | case 0x04: |
6078 | case 0x05: | |
6079 | case 0x06: | |
6080 | case 0x07: | |
6081 | case 0x10: | |
6082 | case 0x11: | |
7ad10968 HZ |
6083 | case 0x14: |
6084 | case 0x15: | |
6085 | case 0x16: | |
6086 | case 0x17: | |
6087 | case 0x20: | |
6088 | case 0x21: | |
7ad10968 HZ |
6089 | case 0x24: |
6090 | case 0x25: | |
6091 | case 0x26: | |
6092 | case 0x27: | |
6093 | case 0x30: | |
6094 | case 0x31: | |
7ad10968 HZ |
6095 | case 0x34: |
6096 | case 0x35: | |
6097 | case 0x36: | |
6098 | case 0x37: | |
dda83cd7 SM |
6099 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6100 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6101 | of code, always affects st(0) register. */ | |
6102 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6103 | return -1; | |
7ad10968 HZ |
6104 | break; |
6105 | case 0x08: | |
6106 | case 0x0a: | |
6107 | case 0x0b: | |
6108 | case 0x18: | |
6109 | case 0x19: | |
6110 | case 0x1a: | |
6111 | case 0x1b: | |
dda83cd7 | 6112 | case 0x1d: |
7ad10968 HZ |
6113 | case 0x28: |
6114 | case 0x29: | |
6115 | case 0x2a: | |
6116 | case 0x2b: | |
6117 | case 0x38: | |
6118 | case 0x39: | |
6119 | case 0x3a: | |
6120 | case 0x3b: | |
dda83cd7 SM |
6121 | case 0x3c: |
6122 | case 0x3d: | |
7ad10968 HZ |
6123 | switch (ir.reg & 7) |
6124 | { | |
6125 | case 0: | |
0289bdd7 MS |
6126 | /* Handling fld, fild. */ |
6127 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6128 | return -1; | |
7ad10968 HZ |
6129 | break; |
6130 | case 1: | |
6131 | switch (ir.reg >> 4) | |
6132 | { | |
6133 | case 0: | |
25ea693b | 6134 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6135 | return -1; |
6136 | break; | |
6137 | case 2: | |
25ea693b | 6138 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6139 | return -1; |
6140 | break; | |
6141 | case 3: | |
0289bdd7 | 6142 | break; |
7ad10968 | 6143 | default: |
25ea693b | 6144 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6145 | return -1; |
6146 | break; | |
6147 | } | |
6148 | break; | |
6149 | default: | |
6150 | switch (ir.reg >> 4) | |
6151 | { | |
6152 | case 0: | |
25ea693b | 6153 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6154 | return -1; |
6155 | if (3 == (ir.reg & 7)) | |
6156 | { | |
6157 | /* For fstp m32fp. */ | |
6158 | if (i386_record_floats (gdbarch, &ir, | |
6159 | I386_SAVE_FPU_REGS)) | |
6160 | return -1; | |
6161 | } | |
6162 | break; | |
7ad10968 | 6163 | case 1: |
25ea693b | 6164 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6165 | return -1; |
0289bdd7 MS |
6166 | if ((3 == (ir.reg & 7)) |
6167 | || (5 == (ir.reg & 7)) | |
6168 | || (7 == (ir.reg & 7))) | |
6169 | { | |
6170 | /* For fstp insn. */ | |
6171 | if (i386_record_floats (gdbarch, &ir, | |
6172 | I386_SAVE_FPU_REGS)) | |
6173 | return -1; | |
6174 | } | |
7ad10968 HZ |
6175 | break; |
6176 | case 2: | |
25ea693b | 6177 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6178 | return -1; |
0289bdd7 MS |
6179 | if (3 == (ir.reg & 7)) |
6180 | { | |
6181 | /* For fstp m64fp. */ | |
6182 | if (i386_record_floats (gdbarch, &ir, | |
6183 | I386_SAVE_FPU_REGS)) | |
6184 | return -1; | |
6185 | } | |
7ad10968 HZ |
6186 | break; |
6187 | case 3: | |
0289bdd7 MS |
6188 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6189 | { | |
6190 | /* For fistp, fbld, fild, fbstp. */ | |
6191 | if (i386_record_floats (gdbarch, &ir, | |
6192 | I386_SAVE_FPU_REGS)) | |
6193 | return -1; | |
6194 | } | |
6195 | /* Fall through */ | |
7ad10968 | 6196 | default: |
25ea693b | 6197 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6198 | return -1; |
6199 | break; | |
6200 | } | |
6201 | break; | |
6202 | } | |
6203 | break; | |
6204 | case 0x0c: | |
dda83cd7 SM |
6205 | /* Insn fldenv. */ |
6206 | if (i386_record_floats (gdbarch, &ir, | |
6207 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6208 | return -1; | |
6209 | break; | |
7ad10968 | 6210 | case 0x0d: |
dda83cd7 SM |
6211 | /* Insn fldcw. */ |
6212 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6213 | return -1; | |
6214 | break; | |
7ad10968 | 6215 | case 0x2c: |
dda83cd7 SM |
6216 | /* Insn frstor. */ |
6217 | if (i386_record_floats (gdbarch, &ir, | |
6218 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6219 | return -1; | |
7ad10968 HZ |
6220 | break; |
6221 | case 0x0e: | |
6222 | if (ir.dflag) | |
6223 | { | |
25ea693b | 6224 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6225 | return -1; |
6226 | } | |
6227 | else | |
6228 | { | |
25ea693b | 6229 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6230 | return -1; |
6231 | } | |
6232 | break; | |
6233 | case 0x0f: | |
6234 | case 0x2f: | |
25ea693b | 6235 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6236 | return -1; |
dda83cd7 SM |
6237 | /* Insn fstp, fbstp. */ |
6238 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6239 | return -1; | |
7ad10968 HZ |
6240 | break; |
6241 | case 0x1f: | |
6242 | case 0x3e: | |
25ea693b | 6243 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6244 | return -1; |
6245 | break; | |
6246 | case 0x2e: | |
6247 | if (ir.dflag) | |
6248 | { | |
25ea693b | 6249 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6250 | return -1; |
955db0c0 | 6251 | addr64 += 28; |
7ad10968 HZ |
6252 | } |
6253 | else | |
6254 | { | |
25ea693b | 6255 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6256 | return -1; |
955db0c0 | 6257 | addr64 += 14; |
7ad10968 | 6258 | } |
25ea693b | 6259 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6260 | return -1; |
0289bdd7 MS |
6261 | /* Insn fsave. */ |
6262 | if (i386_record_floats (gdbarch, &ir, | |
6263 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6264 | return -1; | |
7ad10968 HZ |
6265 | break; |
6266 | case 0x3f: | |
25ea693b | 6267 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6268 | return -1; |
0289bdd7 MS |
6269 | /* Insn fistp. */ |
6270 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6271 | return -1; | |
7ad10968 HZ |
6272 | break; |
6273 | default: | |
6274 | ir.addr -= 2; | |
6275 | opcode = opcode << 8 | ir.modrm; | |
6276 | goto no_support; | |
6277 | break; | |
6278 | } | |
6279 | } | |
0289bdd7 MS |
6280 | /* Opcode is an extension of modR/M byte. */ |
6281 | else | |
dda83cd7 | 6282 | { |
0289bdd7 MS |
6283 | switch (opcode) |
6284 | { | |
6285 | case 0xd8: | |
6286 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6287 | return -1; | |
6288 | break; | |
6289 | case 0xd9: | |
6290 | if (0x0c == (ir.modrm >> 4)) | |
6291 | { | |
6292 | if ((ir.modrm & 0x0f) <= 7) | |
6293 | { | |
6294 | if (i386_record_floats (gdbarch, &ir, | |
6295 | I386_SAVE_FPU_REGS)) | |
6296 | return -1; | |
6297 | } | |
dda83cd7 | 6298 | else |
0289bdd7 MS |
6299 | { |
6300 | if (i386_record_floats (gdbarch, &ir, | |
6301 | I387_ST0_REGNUM (tdep))) | |
6302 | return -1; | |
6303 | /* If only st(0) is changing, then we have already | |
6304 | recorded. */ | |
6305 | if ((ir.modrm & 0x0f) - 0x08) | |
6306 | { | |
6307 | if (i386_record_floats (gdbarch, &ir, | |
6308 | I387_ST0_REGNUM (tdep) + | |
6309 | ((ir.modrm & 0x0f) - 0x08))) | |
6310 | return -1; | |
6311 | } | |
6312 | } | |
6313 | } | |
dda83cd7 SM |
6314 | else |
6315 | { | |
0289bdd7 MS |
6316 | switch (ir.modrm) |
6317 | { | |
6318 | case 0xe0: | |
6319 | case 0xe1: | |
6320 | case 0xf0: | |
6321 | case 0xf5: | |
6322 | case 0xf8: | |
6323 | case 0xfa: | |
6324 | case 0xfc: | |
6325 | case 0xfe: | |
6326 | case 0xff: | |
6327 | if (i386_record_floats (gdbarch, &ir, | |
6328 | I387_ST0_REGNUM (tdep))) | |
6329 | return -1; | |
6330 | break; | |
6331 | case 0xf1: | |
6332 | case 0xf2: | |
6333 | case 0xf3: | |
6334 | case 0xf4: | |
6335 | case 0xf6: | |
6336 | case 0xf7: | |
6337 | case 0xe8: | |
6338 | case 0xe9: | |
6339 | case 0xea: | |
6340 | case 0xeb: | |
6341 | case 0xec: | |
6342 | case 0xed: | |
6343 | case 0xee: | |
6344 | case 0xf9: | |
6345 | case 0xfb: | |
6346 | if (i386_record_floats (gdbarch, &ir, | |
6347 | I386_SAVE_FPU_REGS)) | |
6348 | return -1; | |
6349 | break; | |
6350 | case 0xfd: | |
6351 | if (i386_record_floats (gdbarch, &ir, | |
6352 | I387_ST0_REGNUM (tdep))) | |
6353 | return -1; | |
6354 | if (i386_record_floats (gdbarch, &ir, | |
6355 | I387_ST0_REGNUM (tdep) + 1)) | |
6356 | return -1; | |
6357 | break; | |
6358 | } | |
6359 | } | |
dda83cd7 SM |
6360 | break; |
6361 | case 0xda: | |
6362 | if (0xe9 == ir.modrm) | |
6363 | { | |
0289bdd7 MS |
6364 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6365 | return -1; | |
dda83cd7 SM |
6366 | } |
6367 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6368 | { | |
0289bdd7 MS |
6369 | if (i386_record_floats (gdbarch, &ir, |
6370 | I387_ST0_REGNUM (tdep))) | |
6371 | return -1; | |
6372 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6373 | { | |
6374 | if (i386_record_floats (gdbarch, &ir, | |
6375 | I387_ST0_REGNUM (tdep) + | |
6376 | (ir.modrm & 0x0f))) | |
6377 | return -1; | |
6378 | } | |
6379 | else if ((ir.modrm & 0x0f) - 0x08) | |
6380 | { | |
6381 | if (i386_record_floats (gdbarch, &ir, | |
6382 | I387_ST0_REGNUM (tdep) + | |
6383 | ((ir.modrm & 0x0f) - 0x08))) | |
6384 | return -1; | |
6385 | } | |
dda83cd7 SM |
6386 | } |
6387 | break; | |
6388 | case 0xdb: | |
6389 | if (0xe3 == ir.modrm) | |
6390 | { | |
0289bdd7 MS |
6391 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) |
6392 | return -1; | |
dda83cd7 SM |
6393 | } |
6394 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6395 | { | |
0289bdd7 MS |
6396 | if (i386_record_floats (gdbarch, &ir, |
6397 | I387_ST0_REGNUM (tdep))) | |
6398 | return -1; | |
6399 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6400 | { | |
6401 | if (i386_record_floats (gdbarch, &ir, | |
6402 | I387_ST0_REGNUM (tdep) + | |
6403 | (ir.modrm & 0x0f))) | |
6404 | return -1; | |
6405 | } | |
6406 | else if ((ir.modrm & 0x0f) - 0x08) | |
6407 | { | |
6408 | if (i386_record_floats (gdbarch, &ir, | |
6409 | I387_ST0_REGNUM (tdep) + | |
6410 | ((ir.modrm & 0x0f) - 0x08))) | |
6411 | return -1; | |
6412 | } | |
dda83cd7 SM |
6413 | } |
6414 | break; | |
6415 | case 0xdc: | |
6416 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6417 | || (0x0d == ir.modrm >> 4) |
6418 | || (0x0f == ir.modrm >> 4)) | |
dda83cd7 | 6419 | { |
0289bdd7 MS |
6420 | if ((ir.modrm & 0x0f) <= 7) |
6421 | { | |
6422 | if (i386_record_floats (gdbarch, &ir, | |
6423 | I387_ST0_REGNUM (tdep) + | |
6424 | (ir.modrm & 0x0f))) | |
6425 | return -1; | |
6426 | } | |
6427 | else | |
6428 | { | |
6429 | if (i386_record_floats (gdbarch, &ir, | |
6430 | I387_ST0_REGNUM (tdep) + | |
6431 | ((ir.modrm & 0x0f) - 0x08))) | |
6432 | return -1; | |
6433 | } | |
dda83cd7 | 6434 | } |
0289bdd7 | 6435 | break; |
dda83cd7 SM |
6436 | case 0xdd: |
6437 | if (0x0c == ir.modrm >> 4) | |
6438 | { | |
6439 | if (i386_record_floats (gdbarch, &ir, | |
6440 | I387_FTAG_REGNUM (tdep))) | |
6441 | return -1; | |
6442 | } | |
6443 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6444 | { | |
6445 | if ((ir.modrm & 0x0f) <= 7) | |
6446 | { | |
0289bdd7 MS |
6447 | if (i386_record_floats (gdbarch, &ir, |
6448 | I387_ST0_REGNUM (tdep) + | |
6449 | (ir.modrm & 0x0f))) | |
6450 | return -1; | |
dda83cd7 SM |
6451 | } |
6452 | else | |
6453 | { | |
6454 | if (i386_record_floats (gdbarch, &ir, | |
0289bdd7 | 6455 | I386_SAVE_FPU_REGS)) |
dda83cd7 SM |
6456 | return -1; |
6457 | } | |
6458 | } | |
6459 | break; | |
6460 | case 0xde: | |
6461 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6462 | || (0x0e == ir.modrm >> 4) |
6463 | || (0x0f == ir.modrm >> 4) | |
6464 | || (0xd9 == ir.modrm)) | |
dda83cd7 | 6465 | { |
0289bdd7 MS |
6466 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6467 | return -1; | |
dda83cd7 SM |
6468 | } |
6469 | break; | |
6470 | case 0xdf: | |
6471 | if (0xe0 == ir.modrm) | |
6472 | { | |
25ea693b MM |
6473 | if (record_full_arch_list_add_reg (ir.regcache, |
6474 | I386_EAX_REGNUM)) | |
0289bdd7 | 6475 | return -1; |
dda83cd7 SM |
6476 | } |
6477 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6478 | { | |
0289bdd7 MS |
6479 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6480 | return -1; | |
dda83cd7 SM |
6481 | } |
6482 | break; | |
0289bdd7 MS |
6483 | } |
6484 | } | |
7ad10968 | 6485 | break; |
7ad10968 | 6486 | /* string ops */ |
a38bba38 | 6487 | case 0xa4: /* movsS */ |
7ad10968 | 6488 | case 0xa5: |
a38bba38 | 6489 | case 0xaa: /* stosS */ |
7ad10968 | 6490 | case 0xab: |
a38bba38 | 6491 | case 0x6c: /* insS */ |
7ad10968 | 6492 | case 0x6d: |
cf648174 | 6493 | regcache_raw_read_unsigned (ir.regcache, |
dda83cd7 SM |
6494 | ir.regmap[X86_RECORD_RECX_REGNUM], |
6495 | &addr); | |
648d0c8b | 6496 | if (addr) |
dda83cd7 SM |
6497 | { |
6498 | ULONGEST es, ds; | |
77d7dc92 | 6499 | |
dda83cd7 | 6500 | if ((opcode & 1) == 0) |
77d7dc92 | 6501 | ir.ot = OT_BYTE; |
dda83cd7 | 6502 | else |
77d7dc92 | 6503 | ir.ot = ir.dflag + OT_WORD; |
dda83cd7 SM |
6504 | regcache_raw_read_unsigned (ir.regcache, |
6505 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6506 | &addr); | |
6507 | ||
6508 | regcache_raw_read_unsigned (ir.regcache, | |
6509 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6510 | &es); | |
6511 | regcache_raw_read_unsigned (ir.regcache, | |
6512 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6513 | &ds); | |
6514 | if (ir.aflag && (es != ds)) | |
6515 | { | |
6516 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
6517 | if (record_full_memory_query) | |
6518 | { | |
6519 | if (yquery (_("\ | |
bb08c432 HZ |
6520 | Process record ignores the memory change of instruction at address %s\n\ |
6521 | because it can't get the value of the segment register.\n\ | |
6522 | Do you want to stop the program?"), | |
dda83cd7 SM |
6523 | paddress (gdbarch, ir.orig_addr))) |
6524 | return -1; | |
6525 | } | |
6526 | } | |
6527 | else | |
6528 | { | |
6529 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) | |
6530 | return -1; | |
6531 | } | |
6532 | ||
6533 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
6534 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6535 | if (opcode == 0xa4 || opcode == 0xa5) | |
6536 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6537 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6538 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6539 | } |
cf648174 | 6540 | break; |
7ad10968 | 6541 | |
a38bba38 | 6542 | case 0xa6: /* cmpsS */ |
cf648174 | 6543 | case 0xa7: |
25ea693b MM |
6544 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6546 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6547 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6548 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6549 | break; |
6550 | ||
a38bba38 | 6551 | case 0xac: /* lodsS */ |
7ad10968 | 6552 | case 0xad: |
25ea693b MM |
6553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6554 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6555 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6556 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6557 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6558 | break; |
6559 | ||
a38bba38 | 6560 | case 0xae: /* scasS */ |
7ad10968 | 6561 | case 0xaf: |
25ea693b | 6562 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6563 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6564 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6566 | break; |
6567 | ||
a38bba38 | 6568 | case 0x6e: /* outsS */ |
cf648174 | 6569 | case 0x6f: |
25ea693b | 6570 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6571 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6572 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6574 | break; |
6575 | ||
a38bba38 | 6576 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6577 | case 0xe5: |
6578 | case 0xec: | |
6579 | case 0xed: | |
25ea693b MM |
6580 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6581 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6582 | break; |
6583 | ||
6584 | case 0xe6: | |
6585 | case 0xe7: | |
6586 | case 0xee: | |
6587 | case 0xef: | |
6588 | break; | |
6589 | ||
6590 | /* control */ | |
a38bba38 MS |
6591 | case 0xc2: /* ret im */ |
6592 | case 0xc3: /* ret */ | |
25ea693b MM |
6593 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6594 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6595 | break; |
6596 | ||
a38bba38 MS |
6597 | case 0xca: /* lret im */ |
6598 | case 0xcb: /* lret */ | |
6599 | case 0xcf: /* iret */ | |
25ea693b MM |
6600 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6601 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6602 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6603 | break; |
6604 | ||
a38bba38 | 6605 | case 0xe8: /* call im */ |
cf648174 | 6606 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6607 | ir.dflag = 2; |
cf648174 | 6608 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6609 | return -1; |
7ad10968 HZ |
6610 | break; |
6611 | ||
a38bba38 | 6612 | case 0x9a: /* lcall im */ |
cf648174 | 6613 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6614 | { |
6615 | ir.addr -= 1; | |
6616 | goto no_support; | |
6617 | } | |
25ea693b | 6618 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 6619 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6620 | return -1; |
7ad10968 HZ |
6621 | break; |
6622 | ||
a38bba38 MS |
6623 | case 0xe9: /* jmp im */ |
6624 | case 0xea: /* ljmp im */ | |
6625 | case 0xeb: /* jmp Jb */ | |
6626 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6627 | case 0x71: |
6628 | case 0x72: | |
6629 | case 0x73: | |
6630 | case 0x74: | |
6631 | case 0x75: | |
6632 | case 0x76: | |
6633 | case 0x77: | |
6634 | case 0x78: | |
6635 | case 0x79: | |
6636 | case 0x7a: | |
6637 | case 0x7b: | |
6638 | case 0x7c: | |
6639 | case 0x7d: | |
6640 | case 0x7e: | |
6641 | case 0x7f: | |
a38bba38 | 6642 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6643 | case 0x0f81: |
6644 | case 0x0f82: | |
6645 | case 0x0f83: | |
6646 | case 0x0f84: | |
6647 | case 0x0f85: | |
6648 | case 0x0f86: | |
6649 | case 0x0f87: | |
6650 | case 0x0f88: | |
6651 | case 0x0f89: | |
6652 | case 0x0f8a: | |
6653 | case 0x0f8b: | |
6654 | case 0x0f8c: | |
6655 | case 0x0f8d: | |
6656 | case 0x0f8e: | |
6657 | case 0x0f8f: | |
6658 | break; | |
6659 | ||
a38bba38 | 6660 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6661 | case 0x0f91: |
6662 | case 0x0f92: | |
6663 | case 0x0f93: | |
6664 | case 0x0f94: | |
6665 | case 0x0f95: | |
6666 | case 0x0f96: | |
6667 | case 0x0f97: | |
6668 | case 0x0f98: | |
6669 | case 0x0f99: | |
6670 | case 0x0f9a: | |
6671 | case 0x0f9b: | |
6672 | case 0x0f9c: | |
6673 | case 0x0f9d: | |
6674 | case 0x0f9e: | |
6675 | case 0x0f9f: | |
25ea693b | 6676 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6677 | ir.ot = OT_BYTE; |
6678 | if (i386_record_modrm (&ir)) | |
6679 | return -1; | |
6680 | if (ir.mod == 3) | |
dda83cd7 | 6681 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
25ea693b | 6682 | : (ir.rm & 0x3)); |
7ad10968 HZ |
6683 | else |
6684 | { | |
6685 | if (i386_record_lea_modrm (&ir)) | |
6686 | return -1; | |
6687 | } | |
6688 | break; | |
6689 | ||
a38bba38 | 6690 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6691 | case 0x0f41: |
6692 | case 0x0f42: | |
6693 | case 0x0f43: | |
6694 | case 0x0f44: | |
6695 | case 0x0f45: | |
6696 | case 0x0f46: | |
6697 | case 0x0f47: | |
6698 | case 0x0f48: | |
6699 | case 0x0f49: | |
6700 | case 0x0f4a: | |
6701 | case 0x0f4b: | |
6702 | case 0x0f4c: | |
6703 | case 0x0f4d: | |
6704 | case 0x0f4e: | |
6705 | case 0x0f4f: | |
6706 | if (i386_record_modrm (&ir)) | |
6707 | return -1; | |
cf648174 | 6708 | ir.reg |= rex_r; |
7ad10968 HZ |
6709 | if (ir.dflag == OT_BYTE) |
6710 | ir.reg &= 0x3; | |
25ea693b | 6711 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6712 | break; |
6713 | ||
6714 | /* flags */ | |
a38bba38 | 6715 | case 0x9c: /* pushf */ |
25ea693b | 6716 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 6717 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6718 | ir.dflag = 2; |
cf648174 | 6719 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6720 | return -1; |
7ad10968 HZ |
6721 | break; |
6722 | ||
a38bba38 | 6723 | case 0x9d: /* popf */ |
25ea693b MM |
6724 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6725 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6726 | break; |
6727 | ||
a38bba38 | 6728 | case 0x9e: /* sahf */ |
cf648174 | 6729 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6730 | { |
6731 | ir.addr -= 1; | |
6732 | goto no_support; | |
6733 | } | |
d3f323f3 | 6734 | /* FALLTHROUGH */ |
a38bba38 MS |
6735 | case 0xf5: /* cmc */ |
6736 | case 0xf8: /* clc */ | |
6737 | case 0xf9: /* stc */ | |
6738 | case 0xfc: /* cld */ | |
6739 | case 0xfd: /* std */ | |
25ea693b | 6740 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6741 | break; |
6742 | ||
a38bba38 | 6743 | case 0x9f: /* lahf */ |
cf648174 | 6744 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6745 | { |
6746 | ir.addr -= 1; | |
6747 | goto no_support; | |
6748 | } | |
25ea693b MM |
6749 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6750 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6751 | break; |
6752 | ||
6753 | /* bit operations */ | |
a38bba38 | 6754 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6755 | ir.ot = ir.dflag + OT_WORD; |
6756 | if (i386_record_modrm (&ir)) | |
6757 | return -1; | |
6758 | if (ir.reg < 4) | |
6759 | { | |
cf648174 | 6760 | ir.addr -= 2; |
7ad10968 HZ |
6761 | opcode = opcode << 8 | ir.modrm; |
6762 | goto no_support; | |
6763 | } | |
cf648174 | 6764 | if (ir.reg != 4) |
7ad10968 | 6765 | { |
dda83cd7 SM |
6766 | if (ir.mod == 3) |
6767 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
6768 | else |
6769 | { | |
cf648174 | 6770 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6771 | return -1; |
6772 | } | |
6773 | } | |
25ea693b | 6774 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6775 | break; |
6776 | ||
a38bba38 | 6777 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6778 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6779 | break; |
6780 | ||
a38bba38 MS |
6781 | case 0x0fab: /* bts */ |
6782 | case 0x0fb3: /* btr */ | |
6783 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6784 | ir.ot = ir.dflag + OT_WORD; |
6785 | if (i386_record_modrm (&ir)) | |
dda83cd7 | 6786 | return -1; |
cf648174 | 6787 | if (ir.mod == 3) |
dda83cd7 | 6788 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 | 6789 | else |
dda83cd7 SM |
6790 | { |
6791 | uint64_t addr64; | |
6792 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
6793 | return -1; | |
6794 | regcache_raw_read_unsigned (ir.regcache, | |
6795 | ir.regmap[ir.reg | rex_r], | |
6796 | &addr); | |
6797 | switch (ir.dflag) | |
6798 | { | |
6799 | case 0: | |
6800 | addr64 += ((int16_t) addr >> 4) << 4; | |
6801 | break; | |
6802 | case 1: | |
6803 | addr64 += ((int32_t) addr >> 5) << 5; | |
6804 | break; | |
6805 | case 2: | |
6806 | addr64 += ((int64_t) addr >> 6) << 6; | |
6807 | break; | |
6808 | } | |
6809 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) | |
6810 | return -1; | |
6811 | if (i386_record_lea_modrm (&ir)) | |
6812 | return -1; | |
6813 | } | |
25ea693b | 6814 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6815 | break; |
6816 | ||
a38bba38 MS |
6817 | case 0x0fbc: /* bsf */ |
6818 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6819 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6820 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6821 | break; |
6822 | ||
6823 | /* bcd */ | |
a38bba38 MS |
6824 | case 0x27: /* daa */ |
6825 | case 0x2f: /* das */ | |
6826 | case 0x37: /* aaa */ | |
6827 | case 0x3f: /* aas */ | |
6828 | case 0xd4: /* aam */ | |
6829 | case 0xd5: /* aad */ | |
cf648174 | 6830 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6831 | { |
6832 | ir.addr -= 1; | |
6833 | goto no_support; | |
6834 | } | |
25ea693b MM |
6835 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6836 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6837 | break; |
6838 | ||
6839 | /* misc */ | |
a38bba38 | 6840 | case 0x90: /* nop */ |
7ad10968 HZ |
6841 | if (prefixes & PREFIX_LOCK) |
6842 | { | |
6843 | ir.addr -= 1; | |
6844 | goto no_support; | |
6845 | } | |
6846 | break; | |
6847 | ||
a38bba38 | 6848 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6849 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6850 | return -1; | |
425b824a | 6851 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6852 | ir.addr++; |
6853 | goto reswitch; | |
7ad10968 HZ |
6854 | break; |
6855 | ||
7ad10968 | 6856 | /* XXX */ |
a38bba38 | 6857 | case 0xcc: /* int3 */ |
a3c4230a | 6858 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6859 | "int3.\n")); |
6860 | ir.addr -= 1; | |
6861 | goto no_support; | |
6862 | break; | |
6863 | ||
7ad10968 | 6864 | /* XXX */ |
a38bba38 | 6865 | case 0xcd: /* int */ |
7ad10968 HZ |
6866 | { |
6867 | int ret; | |
425b824a | 6868 | uint8_t interrupt; |
4ffa4fc7 PA |
6869 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6870 | return -1; | |
7ad10968 | 6871 | ir.addr++; |
425b824a | 6872 | if (interrupt != 0x80 |
a3c4230a | 6873 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6874 | { |
a3c4230a | 6875 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6876 | "instruction int 0x%02x.\n"), |
425b824a | 6877 | interrupt); |
7ad10968 HZ |
6878 | ir.addr -= 2; |
6879 | goto no_support; | |
6880 | } | |
a3c4230a | 6881 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6882 | if (ret) |
6883 | return ret; | |
6884 | } | |
6885 | break; | |
6886 | ||
7ad10968 | 6887 | /* XXX */ |
a38bba38 | 6888 | case 0xce: /* into */ |
a3c4230a | 6889 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6890 | "instruction into.\n")); |
6891 | ir.addr -= 1; | |
6892 | goto no_support; | |
6893 | break; | |
6894 | ||
a38bba38 MS |
6895 | case 0xfa: /* cli */ |
6896 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6897 | break; |
6898 | ||
a38bba38 | 6899 | case 0x62: /* bound */ |
a3c4230a | 6900 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6901 | "instruction bound.\n")); |
6902 | ir.addr -= 1; | |
6903 | goto no_support; | |
6904 | break; | |
6905 | ||
a38bba38 | 6906 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6907 | case 0x0fc9: |
6908 | case 0x0fca: | |
6909 | case 0x0fcb: | |
6910 | case 0x0fcc: | |
6911 | case 0x0fcd: | |
6912 | case 0x0fce: | |
6913 | case 0x0fcf: | |
25ea693b | 6914 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6915 | break; |
6916 | ||
a38bba38 | 6917 | case 0xd6: /* salc */ |
cf648174 | 6918 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6919 | { |
6920 | ir.addr -= 1; | |
6921 | goto no_support; | |
6922 | } | |
25ea693b MM |
6923 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6924 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6925 | break; |
6926 | ||
a38bba38 MS |
6927 | case 0xe0: /* loopnz */ |
6928 | case 0xe1: /* loopz */ | |
6929 | case 0xe2: /* loop */ | |
6930 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6931 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6932 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6933 | break; |
6934 | ||
a38bba38 | 6935 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6936 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6937 | "instruction wrmsr.\n")); |
6938 | ir.addr -= 2; | |
6939 | goto no_support; | |
6940 | break; | |
6941 | ||
a38bba38 | 6942 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6943 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6944 | "instruction rdmsr.\n")); |
6945 | ir.addr -= 2; | |
6946 | goto no_support; | |
6947 | break; | |
6948 | ||
a38bba38 | 6949 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6950 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6951 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6952 | break; |
6953 | ||
a38bba38 | 6954 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6955 | { |
6956 | int ret; | |
dda83cd7 SM |
6957 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6958 | { | |
6959 | ir.addr -= 2; | |
6960 | goto no_support; | |
6961 | } | |
a3c4230a | 6962 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6963 | { |
a3c4230a | 6964 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6965 | "instruction sysenter.\n")); |
6966 | ir.addr -= 2; | |
6967 | goto no_support; | |
6968 | } | |
a3c4230a | 6969 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6970 | if (ret) |
6971 | return ret; | |
6972 | } | |
6973 | break; | |
6974 | ||
a38bba38 | 6975 | case 0x0f35: /* sysexit */ |
a3c4230a | 6976 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6977 | "instruction sysexit.\n")); |
6978 | ir.addr -= 2; | |
6979 | goto no_support; | |
6980 | break; | |
6981 | ||
a38bba38 | 6982 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6983 | { |
6984 | int ret; | |
a3c4230a | 6985 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6986 | { |
a3c4230a | 6987 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6988 | "instruction syscall.\n")); |
6989 | ir.addr -= 2; | |
6990 | goto no_support; | |
6991 | } | |
a3c4230a | 6992 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6993 | if (ret) |
6994 | return ret; | |
6995 | } | |
6996 | break; | |
6997 | ||
a38bba38 | 6998 | case 0x0f07: /* sysret */ |
a3c4230a | 6999 | printf_unfiltered (_("Process record does not support " |
dda83cd7 | 7000 | "instruction sysret.\n")); |
cf648174 HZ |
7001 | ir.addr -= 2; |
7002 | goto no_support; | |
7003 | break; | |
7004 | ||
a38bba38 | 7005 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
7006 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7007 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7008 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7009 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
7010 | break; |
7011 | ||
a38bba38 | 7012 | case 0xf4: /* hlt */ |
a3c4230a | 7013 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
7014 | "instruction hlt.\n")); |
7015 | ir.addr -= 1; | |
7016 | goto no_support; | |
7017 | break; | |
7018 | ||
7019 | case 0x0f00: | |
7020 | if (i386_record_modrm (&ir)) | |
7021 | return -1; | |
7022 | switch (ir.reg) | |
7023 | { | |
a38bba38 MS |
7024 | case 0: /* sldt */ |
7025 | case 1: /* str */ | |
7ad10968 | 7026 | if (ir.mod == 3) |
dda83cd7 | 7027 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7028 | else |
7029 | { | |
7030 | ir.ot = OT_WORD; | |
7031 | if (i386_record_lea_modrm (&ir)) | |
7032 | return -1; | |
7033 | } | |
7034 | break; | |
a38bba38 MS |
7035 | case 2: /* lldt */ |
7036 | case 3: /* ltr */ | |
7ad10968 | 7037 | break; |
a38bba38 MS |
7038 | case 4: /* verr */ |
7039 | case 5: /* verw */ | |
dda83cd7 | 7040 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7041 | break; |
7042 | default: | |
7043 | ir.addr -= 3; | |
7044 | opcode = opcode << 8 | ir.modrm; | |
7045 | goto no_support; | |
7046 | break; | |
7047 | } | |
7048 | break; | |
7049 | ||
7050 | case 0x0f01: | |
7051 | if (i386_record_modrm (&ir)) | |
7052 | return -1; | |
7053 | switch (ir.reg) | |
7054 | { | |
a38bba38 | 7055 | case 0: /* sgdt */ |
7ad10968 | 7056 | { |
955db0c0 | 7057 | uint64_t addr64; |
7ad10968 HZ |
7058 | |
7059 | if (ir.mod == 3) | |
7060 | { | |
7061 | ir.addr -= 3; | |
7062 | opcode = opcode << 8 | ir.modrm; | |
7063 | goto no_support; | |
7064 | } | |
d7877f7e | 7065 | if (ir.override >= 0) |
7ad10968 | 7066 | { |
dda83cd7 SM |
7067 | if (record_full_memory_query) |
7068 | { | |
7069 | if (yquery (_("\ | |
bb08c432 HZ |
7070 | Process record ignores the memory change of instruction at address %s\n\ |
7071 | because it can't get the value of the segment register.\n\ | |
7072 | Do you want to stop the program?"), | |
dda83cd7 | 7073 | paddress (gdbarch, ir.orig_addr))) |
651ce16a | 7074 | return -1; |
dda83cd7 | 7075 | } |
7ad10968 HZ |
7076 | } |
7077 | else | |
7078 | { | |
955db0c0 | 7079 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7080 | return -1; |
25ea693b | 7081 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7082 | return -1; |
955db0c0 | 7083 | addr64 += 2; |
dda83cd7 SM |
7084 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7085 | { | |
7086 | if (record_full_arch_list_add_mem (addr64, 8)) | |
cf648174 | 7087 | return -1; |
dda83cd7 SM |
7088 | } |
7089 | else | |
7090 | { | |
7091 | if (record_full_arch_list_add_mem (addr64, 4)) | |
cf648174 | 7092 | return -1; |
dda83cd7 | 7093 | } |
7ad10968 HZ |
7094 | } |
7095 | } | |
7096 | break; | |
7097 | case 1: | |
7098 | if (ir.mod == 3) | |
7099 | { | |
7100 | switch (ir.rm) | |
7101 | { | |
a38bba38 | 7102 | case 0: /* monitor */ |
7ad10968 | 7103 | break; |
a38bba38 | 7104 | case 1: /* mwait */ |
25ea693b | 7105 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7106 | break; |
7107 | default: | |
7108 | ir.addr -= 3; | |
7109 | opcode = opcode << 8 | ir.modrm; | |
7110 | goto no_support; | |
7111 | break; | |
7112 | } | |
7113 | } | |
7114 | else | |
7115 | { | |
7116 | /* sidt */ | |
d7877f7e | 7117 | if (ir.override >= 0) |
7ad10968 | 7118 | { |
dda83cd7 SM |
7119 | if (record_full_memory_query) |
7120 | { | |
7121 | if (yquery (_("\ | |
bb08c432 HZ |
7122 | Process record ignores the memory change of instruction at address %s\n\ |
7123 | because it can't get the value of the segment register.\n\ | |
7124 | Do you want to stop the program?"), | |
dda83cd7 SM |
7125 | paddress (gdbarch, ir.orig_addr))) |
7126 | return -1; | |
7127 | } | |
7ad10968 HZ |
7128 | } |
7129 | else | |
7130 | { | |
955db0c0 | 7131 | uint64_t addr64; |
7ad10968 | 7132 | |
955db0c0 | 7133 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7134 | return -1; |
25ea693b | 7135 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7136 | return -1; |
955db0c0 | 7137 | addr64 += 2; |
dda83cd7 SM |
7138 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7139 | { | |
7140 | if (record_full_arch_list_add_mem (addr64, 8)) | |
7141 | return -1; | |
7142 | } | |
7143 | else | |
7144 | { | |
7145 | if (record_full_arch_list_add_mem (addr64, 4)) | |
7146 | return -1; | |
7147 | } | |
7ad10968 HZ |
7148 | } |
7149 | } | |
7150 | break; | |
a38bba38 | 7151 | case 2: /* lgdt */ |
3800e645 MS |
7152 | if (ir.mod == 3) |
7153 | { | |
7154 | /* xgetbv */ | |
7155 | if (ir.rm == 0) | |
7156 | { | |
25ea693b MM |
7157 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7158 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7159 | break; |
7160 | } | |
7161 | /* xsetbv */ | |
7162 | else if (ir.rm == 1) | |
7163 | break; | |
7164 | } | |
da0e1563 | 7165 | /* Fall through. */ |
a38bba38 | 7166 | case 3: /* lidt */ |
7ad10968 HZ |
7167 | if (ir.mod == 3) |
7168 | { | |
7169 | ir.addr -= 3; | |
7170 | opcode = opcode << 8 | ir.modrm; | |
7171 | goto no_support; | |
7172 | } | |
7173 | break; | |
a38bba38 | 7174 | case 4: /* smsw */ |
7ad10968 HZ |
7175 | if (ir.mod == 3) |
7176 | { | |
25ea693b | 7177 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7178 | return -1; |
7179 | } | |
7180 | else | |
7181 | { | |
7182 | ir.ot = OT_WORD; | |
7183 | if (i386_record_lea_modrm (&ir)) | |
7184 | return -1; | |
7185 | } | |
25ea693b | 7186 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7187 | break; |
a38bba38 | 7188 | case 6: /* lmsw */ |
25ea693b | 7189 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7190 | break; |
a38bba38 | 7191 | case 7: /* invlpg */ |
cf648174 HZ |
7192 | if (ir.mod == 3) |
7193 | { | |
7194 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
dda83cd7 | 7195 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 | 7196 | else |
dda83cd7 SM |
7197 | { |
7198 | ir.addr -= 3; | |
7199 | opcode = opcode << 8 | ir.modrm; | |
7200 | goto no_support; | |
7201 | } | |
cf648174 HZ |
7202 | } |
7203 | else | |
25ea693b | 7204 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7205 | break; |
7206 | default: | |
7207 | ir.addr -= 3; | |
7208 | opcode = opcode << 8 | ir.modrm; | |
7209 | goto no_support; | |
7ad10968 HZ |
7210 | break; |
7211 | } | |
7212 | break; | |
7213 | ||
a38bba38 MS |
7214 | case 0x0f08: /* invd */ |
7215 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7216 | break; |
7217 | ||
a38bba38 | 7218 | case 0x63: /* arpl */ |
7ad10968 HZ |
7219 | if (i386_record_modrm (&ir)) |
7220 | return -1; | |
cf648174 | 7221 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
7222 | { |
7223 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
25ea693b | 7224 | ? (ir.reg | rex_r) : ir.rm); |
dda83cd7 | 7225 | } |
7ad10968 | 7226 | else |
dda83cd7 SM |
7227 | { |
7228 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7229 | if (i386_record_lea_modrm (&ir)) | |
7230 | return -1; | |
7231 | } | |
cf648174 | 7232 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 7233 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7234 | break; |
7235 | ||
a38bba38 MS |
7236 | case 0x0f02: /* lar */ |
7237 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7238 | if (i386_record_modrm (&ir)) |
7239 | return -1; | |
25ea693b MM |
7240 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7241 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7242 | break; |
7243 | ||
7244 | case 0x0f18: | |
cf648174 HZ |
7245 | if (i386_record_modrm (&ir)) |
7246 | return -1; | |
7247 | if (ir.mod == 3 && ir.reg == 3) | |
dda83cd7 | 7248 | { |
cf648174 HZ |
7249 | ir.addr -= 3; |
7250 | opcode = opcode << 8 | ir.modrm; | |
7251 | goto no_support; | |
7252 | } | |
7ad10968 HZ |
7253 | break; |
7254 | ||
7ad10968 HZ |
7255 | case 0x0f19: |
7256 | case 0x0f1a: | |
7257 | case 0x0f1b: | |
7258 | case 0x0f1c: | |
7259 | case 0x0f1d: | |
7260 | case 0x0f1e: | |
7261 | case 0x0f1f: | |
a38bba38 | 7262 | /* nop (multi byte) */ |
7ad10968 HZ |
7263 | break; |
7264 | ||
a38bba38 MS |
7265 | case 0x0f20: /* mov reg, crN */ |
7266 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7267 | if (i386_record_modrm (&ir)) |
7268 | return -1; | |
7269 | if ((ir.modrm & 0xc0) != 0xc0) | |
7270 | { | |
cf648174 | 7271 | ir.addr -= 3; |
7ad10968 HZ |
7272 | opcode = opcode << 8 | ir.modrm; |
7273 | goto no_support; | |
7274 | } | |
7275 | switch (ir.reg) | |
7276 | { | |
7277 | case 0: | |
7278 | case 2: | |
7279 | case 3: | |
7280 | case 4: | |
7281 | case 8: | |
7282 | if (opcode & 2) | |
25ea693b | 7283 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7284 | else |
dda83cd7 | 7285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7286 | break; |
7287 | default: | |
cf648174 | 7288 | ir.addr -= 3; |
7ad10968 HZ |
7289 | opcode = opcode << 8 | ir.modrm; |
7290 | goto no_support; | |
7291 | break; | |
7292 | } | |
7293 | break; | |
7294 | ||
a38bba38 MS |
7295 | case 0x0f21: /* mov reg, drN */ |
7296 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7297 | if (i386_record_modrm (&ir)) |
7298 | return -1; | |
7299 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7300 | || ir.reg == 5 || ir.reg >= 8) | |
7301 | { | |
cf648174 | 7302 | ir.addr -= 3; |
7ad10968 HZ |
7303 | opcode = opcode << 8 | ir.modrm; |
7304 | goto no_support; | |
7305 | } | |
7306 | if (opcode & 2) | |
dda83cd7 | 7307 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7308 | else |
25ea693b | 7309 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7310 | break; |
7311 | ||
a38bba38 | 7312 | case 0x0f06: /* clts */ |
25ea693b | 7313 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7314 | break; |
7315 | ||
a3c4230a HZ |
7316 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7317 | ||
7318 | case 0x0f0d: /* 3DNow! prefetch */ | |
7319 | break; | |
7320 | ||
7321 | case 0x0f0e: /* 3DNow! femms */ | |
7322 | case 0x0f77: /* emms */ | |
7323 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
dda83cd7 | 7324 | goto no_support; |
25ea693b | 7325 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7326 | break; |
7327 | ||
7328 | case 0x0f0f: /* 3DNow! data */ | |
7329 | if (i386_record_modrm (&ir)) | |
7330 | return -1; | |
4ffa4fc7 PA |
7331 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7332 | return -1; | |
a3c4230a HZ |
7333 | ir.addr++; |
7334 | switch (opcode8) | |
dda83cd7 SM |
7335 | { |
7336 | case 0x0c: /* 3DNow! pi2fw */ | |
7337 | case 0x0d: /* 3DNow! pi2fd */ | |
7338 | case 0x1c: /* 3DNow! pf2iw */ | |
7339 | case 0x1d: /* 3DNow! pf2id */ | |
7340 | case 0x8a: /* 3DNow! pfnacc */ | |
7341 | case 0x8e: /* 3DNow! pfpnacc */ | |
7342 | case 0x90: /* 3DNow! pfcmpge */ | |
7343 | case 0x94: /* 3DNow! pfmin */ | |
7344 | case 0x96: /* 3DNow! pfrcp */ | |
7345 | case 0x97: /* 3DNow! pfrsqrt */ | |
7346 | case 0x9a: /* 3DNow! pfsub */ | |
7347 | case 0x9e: /* 3DNow! pfadd */ | |
7348 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7349 | case 0xa4: /* 3DNow! pfmax */ | |
7350 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7351 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7352 | case 0xaa: /* 3DNow! pfsubr */ | |
7353 | case 0xae: /* 3DNow! pfacc */ | |
7354 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7355 | case 0xb4: /* 3DNow! pfmul */ | |
7356 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7357 | case 0xb7: /* 3DNow! pmulhrw */ | |
7358 | case 0xbb: /* 3DNow! pswapd */ | |
7359 | case 0xbf: /* 3DNow! pavgusb */ | |
7360 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7361 | goto no_support_3dnow_data; | |
7362 | record_full_arch_list_add_reg (ir.regcache, ir.reg); | |
7363 | break; | |
7364 | ||
7365 | default: | |
a3c4230a | 7366 | no_support_3dnow_data: |
dda83cd7 SM |
7367 | opcode = (opcode << 8) | opcode8; |
7368 | goto no_support; | |
7369 | break; | |
7370 | } | |
a3c4230a HZ |
7371 | break; |
7372 | ||
7373 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7374 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7375 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7376 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7377 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7378 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7379 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7380 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7381 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7382 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7383 | break; |
7384 | ||
7385 | case 0x0fae: | |
7386 | if (i386_record_modrm (&ir)) | |
7387 | return -1; | |
7388 | switch(ir.reg) | |
dda83cd7 SM |
7389 | { |
7390 | case 0: /* fxsave */ | |
7391 | { | |
7392 | uint64_t tmpu64; | |
a3c4230a | 7393 | |
dda83cd7 | 7394 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7395 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7396 | return -1; | |
dda83cd7 SM |
7397 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
7398 | return -1; | |
7399 | } | |
7400 | break; | |
a3c4230a | 7401 | |
dda83cd7 SM |
7402 | case 1: /* fxrstor */ |
7403 | { | |
7404 | int i; | |
a3c4230a | 7405 | |
dda83cd7 | 7406 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a | 7407 | |
dda83cd7 SM |
7408 | for (i = I387_MM0_REGNUM (tdep); |
7409 | i386_mmx_regnum_p (gdbarch, i); i++) | |
7410 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7411 | |
dda83cd7 SM |
7412 | for (i = I387_XMM0_REGNUM (tdep); |
7413 | i386_xmm_regnum_p (gdbarch, i); i++) | |
7414 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7415 | |
dda83cd7 SM |
7416 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) |
7417 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7418 | I387_MXCSR_REGNUM(tdep)); |
a3c4230a | 7419 | |
dda83cd7 SM |
7420 | for (i = I387_ST0_REGNUM (tdep); |
7421 | i386_fp_regnum_p (gdbarch, i); i++) | |
7422 | record_full_arch_list_add_reg (ir.regcache, i); | |
7423 | ||
7424 | for (i = I387_FCTRL_REGNUM (tdep); | |
7425 | i386_fpc_regnum_p (gdbarch, i); i++) | |
7426 | record_full_arch_list_add_reg (ir.regcache, i); | |
7427 | } | |
7428 | break; | |
7429 | ||
7430 | case 2: /* ldmxcsr */ | |
7431 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7432 | goto no_support; | |
7433 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
7434 | break; | |
7435 | ||
7436 | case 3: /* stmxcsr */ | |
7437 | ir.ot = OT_LONG; | |
7438 | if (i386_record_lea_modrm (&ir)) | |
7439 | return -1; | |
7440 | break; | |
7441 | ||
7442 | case 5: /* lfence */ | |
7443 | case 6: /* mfence */ | |
7444 | case 7: /* sfence clflush */ | |
7445 | break; | |
7446 | ||
7447 | default: | |
7448 | opcode = (opcode << 8) | ir.modrm; | |
7449 | goto no_support; | |
7450 | break; | |
7451 | } | |
a3c4230a HZ |
7452 | break; |
7453 | ||
7454 | case 0x0fc3: /* movnti */ | |
7455 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7456 | if (i386_record_modrm (&ir)) | |
7457 | return -1; | |
7458 | if (ir.mod == 3) | |
dda83cd7 | 7459 | goto no_support; |
a3c4230a HZ |
7460 | ir.reg |= rex_r; |
7461 | if (i386_record_lea_modrm (&ir)) | |
dda83cd7 | 7462 | return -1; |
a3c4230a HZ |
7463 | break; |
7464 | ||
7465 | /* Add prefix to opcode. */ | |
7466 | case 0x0f10: | |
7467 | case 0x0f11: | |
7468 | case 0x0f12: | |
7469 | case 0x0f13: | |
7470 | case 0x0f14: | |
7471 | case 0x0f15: | |
7472 | case 0x0f16: | |
7473 | case 0x0f17: | |
7474 | case 0x0f28: | |
7475 | case 0x0f29: | |
7476 | case 0x0f2a: | |
7477 | case 0x0f2b: | |
7478 | case 0x0f2c: | |
7479 | case 0x0f2d: | |
7480 | case 0x0f2e: | |
7481 | case 0x0f2f: | |
7482 | case 0x0f38: | |
7483 | case 0x0f39: | |
7484 | case 0x0f3a: | |
7485 | case 0x0f50: | |
7486 | case 0x0f51: | |
7487 | case 0x0f52: | |
7488 | case 0x0f53: | |
7489 | case 0x0f54: | |
7490 | case 0x0f55: | |
7491 | case 0x0f56: | |
7492 | case 0x0f57: | |
7493 | case 0x0f58: | |
7494 | case 0x0f59: | |
7495 | case 0x0f5a: | |
7496 | case 0x0f5b: | |
7497 | case 0x0f5c: | |
7498 | case 0x0f5d: | |
7499 | case 0x0f5e: | |
7500 | case 0x0f5f: | |
7501 | case 0x0f60: | |
7502 | case 0x0f61: | |
7503 | case 0x0f62: | |
7504 | case 0x0f63: | |
7505 | case 0x0f64: | |
7506 | case 0x0f65: | |
7507 | case 0x0f66: | |
7508 | case 0x0f67: | |
7509 | case 0x0f68: | |
7510 | case 0x0f69: | |
7511 | case 0x0f6a: | |
7512 | case 0x0f6b: | |
7513 | case 0x0f6c: | |
7514 | case 0x0f6d: | |
7515 | case 0x0f6e: | |
7516 | case 0x0f6f: | |
7517 | case 0x0f70: | |
7518 | case 0x0f71: | |
7519 | case 0x0f72: | |
7520 | case 0x0f73: | |
7521 | case 0x0f74: | |
7522 | case 0x0f75: | |
7523 | case 0x0f76: | |
7524 | case 0x0f7c: | |
7525 | case 0x0f7d: | |
7526 | case 0x0f7e: | |
7527 | case 0x0f7f: | |
7528 | case 0x0fb8: | |
7529 | case 0x0fc2: | |
7530 | case 0x0fc4: | |
7531 | case 0x0fc5: | |
7532 | case 0x0fc6: | |
7533 | case 0x0fd0: | |
7534 | case 0x0fd1: | |
7535 | case 0x0fd2: | |
7536 | case 0x0fd3: | |
7537 | case 0x0fd4: | |
7538 | case 0x0fd5: | |
7539 | case 0x0fd6: | |
7540 | case 0x0fd7: | |
7541 | case 0x0fd8: | |
7542 | case 0x0fd9: | |
7543 | case 0x0fda: | |
7544 | case 0x0fdb: | |
7545 | case 0x0fdc: | |
7546 | case 0x0fdd: | |
7547 | case 0x0fde: | |
7548 | case 0x0fdf: | |
7549 | case 0x0fe0: | |
7550 | case 0x0fe1: | |
7551 | case 0x0fe2: | |
7552 | case 0x0fe3: | |
7553 | case 0x0fe4: | |
7554 | case 0x0fe5: | |
7555 | case 0x0fe6: | |
7556 | case 0x0fe7: | |
7557 | case 0x0fe8: | |
7558 | case 0x0fe9: | |
7559 | case 0x0fea: | |
7560 | case 0x0feb: | |
7561 | case 0x0fec: | |
7562 | case 0x0fed: | |
7563 | case 0x0fee: | |
7564 | case 0x0fef: | |
7565 | case 0x0ff0: | |
7566 | case 0x0ff1: | |
7567 | case 0x0ff2: | |
7568 | case 0x0ff3: | |
7569 | case 0x0ff4: | |
7570 | case 0x0ff5: | |
7571 | case 0x0ff6: | |
7572 | case 0x0ff7: | |
7573 | case 0x0ff8: | |
7574 | case 0x0ff9: | |
7575 | case 0x0ffa: | |
7576 | case 0x0ffb: | |
7577 | case 0x0ffc: | |
7578 | case 0x0ffd: | |
7579 | case 0x0ffe: | |
f9fda3f5 L |
7580 | /* Mask out PREFIX_ADDR. */ |
7581 | switch ((prefixes & ~PREFIX_ADDR)) | |
dda83cd7 SM |
7582 | { |
7583 | case PREFIX_REPNZ: | |
7584 | opcode |= 0xf20000; | |
7585 | break; | |
7586 | case PREFIX_DATA: | |
7587 | opcode |= 0x660000; | |
7588 | break; | |
7589 | case PREFIX_REPZ: | |
7590 | opcode |= 0xf30000; | |
7591 | break; | |
7592 | } | |
a3c4230a HZ |
7593 | reswitch_prefix_add: |
7594 | switch (opcode) | |
dda83cd7 SM |
7595 | { |
7596 | case 0x0f38: | |
7597 | case 0x660f38: | |
7598 | case 0xf20f38: | |
7599 | case 0x0f3a: | |
7600 | case 0x660f3a: | |
7601 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) | |
4ffa4fc7 | 7602 | return -1; |
dda83cd7 SM |
7603 | ir.addr++; |
7604 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7605 | goto reswitch_prefix_add; | |
7606 | break; | |
7607 | ||
7608 | case 0x0f10: /* movups */ | |
7609 | case 0x660f10: /* movupd */ | |
7610 | case 0xf30f10: /* movss */ | |
7611 | case 0xf20f10: /* movsd */ | |
7612 | case 0x0f12: /* movlps */ | |
7613 | case 0x660f12: /* movlpd */ | |
7614 | case 0xf30f12: /* movsldup */ | |
7615 | case 0xf20f12: /* movddup */ | |
7616 | case 0x0f14: /* unpcklps */ | |
7617 | case 0x660f14: /* unpcklpd */ | |
7618 | case 0x0f15: /* unpckhps */ | |
7619 | case 0x660f15: /* unpckhpd */ | |
7620 | case 0x0f16: /* movhps */ | |
7621 | case 0x660f16: /* movhpd */ | |
7622 | case 0xf30f16: /* movshdup */ | |
7623 | case 0x0f28: /* movaps */ | |
7624 | case 0x660f28: /* movapd */ | |
7625 | case 0x0f2a: /* cvtpi2ps */ | |
7626 | case 0x660f2a: /* cvtpi2pd */ | |
7627 | case 0xf30f2a: /* cvtsi2ss */ | |
7628 | case 0xf20f2a: /* cvtsi2sd */ | |
7629 | case 0x0f2c: /* cvttps2pi */ | |
7630 | case 0x660f2c: /* cvttpd2pi */ | |
7631 | case 0x0f2d: /* cvtps2pi */ | |
7632 | case 0x660f2d: /* cvtpd2pi */ | |
7633 | case 0x660f3800: /* pshufb */ | |
7634 | case 0x660f3801: /* phaddw */ | |
7635 | case 0x660f3802: /* phaddd */ | |
7636 | case 0x660f3803: /* phaddsw */ | |
7637 | case 0x660f3804: /* pmaddubsw */ | |
7638 | case 0x660f3805: /* phsubw */ | |
7639 | case 0x660f3806: /* phsubd */ | |
7640 | case 0x660f3807: /* phsubsw */ | |
7641 | case 0x660f3808: /* psignb */ | |
7642 | case 0x660f3809: /* psignw */ | |
7643 | case 0x660f380a: /* psignd */ | |
7644 | case 0x660f380b: /* pmulhrsw */ | |
7645 | case 0x660f3810: /* pblendvb */ | |
7646 | case 0x660f3814: /* blendvps */ | |
7647 | case 0x660f3815: /* blendvpd */ | |
7648 | case 0x660f381c: /* pabsb */ | |
7649 | case 0x660f381d: /* pabsw */ | |
7650 | case 0x660f381e: /* pabsd */ | |
7651 | case 0x660f3820: /* pmovsxbw */ | |
7652 | case 0x660f3821: /* pmovsxbd */ | |
7653 | case 0x660f3822: /* pmovsxbq */ | |
7654 | case 0x660f3823: /* pmovsxwd */ | |
7655 | case 0x660f3824: /* pmovsxwq */ | |
7656 | case 0x660f3825: /* pmovsxdq */ | |
7657 | case 0x660f3828: /* pmuldq */ | |
7658 | case 0x660f3829: /* pcmpeqq */ | |
7659 | case 0x660f382a: /* movntdqa */ | |
7660 | case 0x660f3a08: /* roundps */ | |
7661 | case 0x660f3a09: /* roundpd */ | |
7662 | case 0x660f3a0a: /* roundss */ | |
7663 | case 0x660f3a0b: /* roundsd */ | |
7664 | case 0x660f3a0c: /* blendps */ | |
7665 | case 0x660f3a0d: /* blendpd */ | |
7666 | case 0x660f3a0e: /* pblendw */ | |
7667 | case 0x660f3a0f: /* palignr */ | |
7668 | case 0x660f3a20: /* pinsrb */ | |
7669 | case 0x660f3a21: /* insertps */ | |
7670 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7671 | case 0x660f3a40: /* dpps */ | |
7672 | case 0x660f3a41: /* dppd */ | |
7673 | case 0x660f3a42: /* mpsadbw */ | |
7674 | case 0x660f3a60: /* pcmpestrm */ | |
7675 | case 0x660f3a61: /* pcmpestri */ | |
7676 | case 0x660f3a62: /* pcmpistrm */ | |
7677 | case 0x660f3a63: /* pcmpistri */ | |
7678 | case 0x0f51: /* sqrtps */ | |
7679 | case 0x660f51: /* sqrtpd */ | |
7680 | case 0xf20f51: /* sqrtsd */ | |
7681 | case 0xf30f51: /* sqrtss */ | |
7682 | case 0x0f52: /* rsqrtps */ | |
7683 | case 0xf30f52: /* rsqrtss */ | |
7684 | case 0x0f53: /* rcpps */ | |
7685 | case 0xf30f53: /* rcpss */ | |
7686 | case 0x0f54: /* andps */ | |
7687 | case 0x660f54: /* andpd */ | |
7688 | case 0x0f55: /* andnps */ | |
7689 | case 0x660f55: /* andnpd */ | |
7690 | case 0x0f56: /* orps */ | |
7691 | case 0x660f56: /* orpd */ | |
7692 | case 0x0f57: /* xorps */ | |
7693 | case 0x660f57: /* xorpd */ | |
7694 | case 0x0f58: /* addps */ | |
7695 | case 0x660f58: /* addpd */ | |
7696 | case 0xf20f58: /* addsd */ | |
7697 | case 0xf30f58: /* addss */ | |
7698 | case 0x0f59: /* mulps */ | |
7699 | case 0x660f59: /* mulpd */ | |
7700 | case 0xf20f59: /* mulsd */ | |
7701 | case 0xf30f59: /* mulss */ | |
7702 | case 0x0f5a: /* cvtps2pd */ | |
7703 | case 0x660f5a: /* cvtpd2ps */ | |
7704 | case 0xf20f5a: /* cvtsd2ss */ | |
7705 | case 0xf30f5a: /* cvtss2sd */ | |
7706 | case 0x0f5b: /* cvtdq2ps */ | |
7707 | case 0x660f5b: /* cvtps2dq */ | |
7708 | case 0xf30f5b: /* cvttps2dq */ | |
7709 | case 0x0f5c: /* subps */ | |
7710 | case 0x660f5c: /* subpd */ | |
7711 | case 0xf20f5c: /* subsd */ | |
7712 | case 0xf30f5c: /* subss */ | |
7713 | case 0x0f5d: /* minps */ | |
7714 | case 0x660f5d: /* minpd */ | |
7715 | case 0xf20f5d: /* minsd */ | |
7716 | case 0xf30f5d: /* minss */ | |
7717 | case 0x0f5e: /* divps */ | |
7718 | case 0x660f5e: /* divpd */ | |
7719 | case 0xf20f5e: /* divsd */ | |
7720 | case 0xf30f5e: /* divss */ | |
7721 | case 0x0f5f: /* maxps */ | |
7722 | case 0x660f5f: /* maxpd */ | |
7723 | case 0xf20f5f: /* maxsd */ | |
7724 | case 0xf30f5f: /* maxss */ | |
7725 | case 0x660f60: /* punpcklbw */ | |
7726 | case 0x660f61: /* punpcklwd */ | |
7727 | case 0x660f62: /* punpckldq */ | |
7728 | case 0x660f63: /* packsswb */ | |
7729 | case 0x660f64: /* pcmpgtb */ | |
7730 | case 0x660f65: /* pcmpgtw */ | |
7731 | case 0x660f66: /* pcmpgtd */ | |
7732 | case 0x660f67: /* packuswb */ | |
7733 | case 0x660f68: /* punpckhbw */ | |
7734 | case 0x660f69: /* punpckhwd */ | |
7735 | case 0x660f6a: /* punpckhdq */ | |
7736 | case 0x660f6b: /* packssdw */ | |
7737 | case 0x660f6c: /* punpcklqdq */ | |
7738 | case 0x660f6d: /* punpckhqdq */ | |
7739 | case 0x660f6e: /* movd */ | |
7740 | case 0x660f6f: /* movdqa */ | |
7741 | case 0xf30f6f: /* movdqu */ | |
7742 | case 0x660f70: /* pshufd */ | |
7743 | case 0xf20f70: /* pshuflw */ | |
7744 | case 0xf30f70: /* pshufhw */ | |
7745 | case 0x660f74: /* pcmpeqb */ | |
7746 | case 0x660f75: /* pcmpeqw */ | |
7747 | case 0x660f76: /* pcmpeqd */ | |
7748 | case 0x660f7c: /* haddpd */ | |
7749 | case 0xf20f7c: /* haddps */ | |
7750 | case 0x660f7d: /* hsubpd */ | |
7751 | case 0xf20f7d: /* hsubps */ | |
7752 | case 0xf30f7e: /* movq */ | |
7753 | case 0x0fc2: /* cmpps */ | |
7754 | case 0x660fc2: /* cmppd */ | |
7755 | case 0xf20fc2: /* cmpsd */ | |
7756 | case 0xf30fc2: /* cmpss */ | |
7757 | case 0x660fc4: /* pinsrw */ | |
7758 | case 0x0fc6: /* shufps */ | |
7759 | case 0x660fc6: /* shufpd */ | |
7760 | case 0x660fd0: /* addsubpd */ | |
7761 | case 0xf20fd0: /* addsubps */ | |
7762 | case 0x660fd1: /* psrlw */ | |
7763 | case 0x660fd2: /* psrld */ | |
7764 | case 0x660fd3: /* psrlq */ | |
7765 | case 0x660fd4: /* paddq */ | |
7766 | case 0x660fd5: /* pmullw */ | |
7767 | case 0xf30fd6: /* movq2dq */ | |
7768 | case 0x660fd8: /* psubusb */ | |
7769 | case 0x660fd9: /* psubusw */ | |
7770 | case 0x660fda: /* pminub */ | |
7771 | case 0x660fdb: /* pand */ | |
7772 | case 0x660fdc: /* paddusb */ | |
7773 | case 0x660fdd: /* paddusw */ | |
7774 | case 0x660fde: /* pmaxub */ | |
7775 | case 0x660fdf: /* pandn */ | |
7776 | case 0x660fe0: /* pavgb */ | |
7777 | case 0x660fe1: /* psraw */ | |
7778 | case 0x660fe2: /* psrad */ | |
7779 | case 0x660fe3: /* pavgw */ | |
7780 | case 0x660fe4: /* pmulhuw */ | |
7781 | case 0x660fe5: /* pmulhw */ | |
7782 | case 0x660fe6: /* cvttpd2dq */ | |
7783 | case 0xf20fe6: /* cvtpd2dq */ | |
7784 | case 0xf30fe6: /* cvtdq2pd */ | |
7785 | case 0x660fe8: /* psubsb */ | |
7786 | case 0x660fe9: /* psubsw */ | |
7787 | case 0x660fea: /* pminsw */ | |
7788 | case 0x660feb: /* por */ | |
7789 | case 0x660fec: /* paddsb */ | |
7790 | case 0x660fed: /* paddsw */ | |
7791 | case 0x660fee: /* pmaxsw */ | |
7792 | case 0x660fef: /* pxor */ | |
7793 | case 0xf20ff0: /* lddqu */ | |
7794 | case 0x660ff1: /* psllw */ | |
7795 | case 0x660ff2: /* pslld */ | |
7796 | case 0x660ff3: /* psllq */ | |
7797 | case 0x660ff4: /* pmuludq */ | |
7798 | case 0x660ff5: /* pmaddwd */ | |
7799 | case 0x660ff6: /* psadbw */ | |
7800 | case 0x660ff8: /* psubb */ | |
7801 | case 0x660ff9: /* psubw */ | |
7802 | case 0x660ffa: /* psubd */ | |
7803 | case 0x660ffb: /* psubq */ | |
7804 | case 0x660ffc: /* paddb */ | |
7805 | case 0x660ffd: /* paddw */ | |
7806 | case 0x660ffe: /* paddd */ | |
7807 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7808 | return -1; |
dda83cd7 SM |
7809 | ir.reg |= rex_r; |
7810 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) | |
7811 | goto no_support; | |
7812 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7813 | I387_XMM0_REGNUM (tdep) + ir.reg); |
dda83cd7 SM |
7814 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
7815 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7816 | break; | |
7817 | ||
7818 | case 0x0f11: /* movups */ | |
7819 | case 0x660f11: /* movupd */ | |
7820 | case 0xf30f11: /* movss */ | |
7821 | case 0xf20f11: /* movsd */ | |
7822 | case 0x0f13: /* movlps */ | |
7823 | case 0x660f13: /* movlpd */ | |
7824 | case 0x0f17: /* movhps */ | |
7825 | case 0x660f17: /* movhpd */ | |
7826 | case 0x0f29: /* movaps */ | |
7827 | case 0x660f29: /* movapd */ | |
7828 | case 0x660f3a14: /* pextrb */ | |
7829 | case 0x660f3a15: /* pextrw */ | |
7830 | case 0x660f3a16: /* pextrd pextrq */ | |
7831 | case 0x660f3a17: /* extractps */ | |
7832 | case 0x660f7f: /* movdqa */ | |
7833 | case 0xf30f7f: /* movdqu */ | |
7834 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7835 | return -1; |
dda83cd7 SM |
7836 | if (ir.mod == 3) |
7837 | { | |
7838 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7839 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7840 | goto no_support; | |
7841 | ir.rm |= ir.rex_b; | |
7842 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 7843 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
7844 | goto no_support; |
7845 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7846 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
7847 | } |
7848 | else | |
7849 | { | |
7850 | switch (opcode) | |
7851 | { | |
7852 | case 0x660f3a14: | |
7853 | ir.ot = OT_BYTE; | |
7854 | break; | |
7855 | case 0x660f3a15: | |
7856 | ir.ot = OT_WORD; | |
7857 | break; | |
7858 | case 0x660f3a16: | |
7859 | ir.ot = OT_LONG; | |
7860 | break; | |
7861 | case 0x660f3a17: | |
7862 | ir.ot = OT_QUAD; | |
7863 | break; | |
7864 | default: | |
7865 | ir.ot = OT_DQUAD; | |
7866 | break; | |
7867 | } | |
7868 | if (i386_record_lea_modrm (&ir)) | |
7869 | return -1; | |
7870 | } | |
7871 | break; | |
7872 | ||
7873 | case 0x0f2b: /* movntps */ | |
7874 | case 0x660f2b: /* movntpd */ | |
7875 | case 0x0fe7: /* movntq */ | |
7876 | case 0x660fe7: /* movntdq */ | |
7877 | if (ir.mod == 3) | |
7878 | goto no_support; | |
7879 | if (opcode == 0x0fe7) | |
7880 | ir.ot = OT_QUAD; | |
7881 | else | |
7882 | ir.ot = OT_DQUAD; | |
7883 | if (i386_record_lea_modrm (&ir)) | |
a3c4230a | 7884 | return -1; |
dda83cd7 SM |
7885 | break; |
7886 | ||
7887 | case 0xf30f2c: /* cvttss2si */ | |
7888 | case 0xf20f2c: /* cvttsd2si */ | |
7889 | case 0xf30f2d: /* cvtss2si */ | |
7890 | case 0xf20f2d: /* cvtsd2si */ | |
7891 | case 0xf20f38f0: /* crc32 */ | |
7892 | case 0xf20f38f1: /* crc32 */ | |
7893 | case 0x0f50: /* movmskps */ | |
7894 | case 0x660f50: /* movmskpd */ | |
7895 | case 0x0fc5: /* pextrw */ | |
7896 | case 0x660fc5: /* pextrw */ | |
7897 | case 0x0fd7: /* pmovmskb */ | |
7898 | case 0x660fd7: /* pmovmskb */ | |
7899 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
7900 | break; | |
7901 | ||
7902 | case 0x0f3800: /* pshufb */ | |
7903 | case 0x0f3801: /* phaddw */ | |
7904 | case 0x0f3802: /* phaddd */ | |
7905 | case 0x0f3803: /* phaddsw */ | |
7906 | case 0x0f3804: /* pmaddubsw */ | |
7907 | case 0x0f3805: /* phsubw */ | |
7908 | case 0x0f3806: /* phsubd */ | |
7909 | case 0x0f3807: /* phsubsw */ | |
7910 | case 0x0f3808: /* psignb */ | |
7911 | case 0x0f3809: /* psignw */ | |
7912 | case 0x0f380a: /* psignd */ | |
7913 | case 0x0f380b: /* pmulhrsw */ | |
7914 | case 0x0f381c: /* pabsb */ | |
7915 | case 0x0f381d: /* pabsw */ | |
7916 | case 0x0f381e: /* pabsd */ | |
7917 | case 0x0f382b: /* packusdw */ | |
7918 | case 0x0f3830: /* pmovzxbw */ | |
7919 | case 0x0f3831: /* pmovzxbd */ | |
7920 | case 0x0f3832: /* pmovzxbq */ | |
7921 | case 0x0f3833: /* pmovzxwd */ | |
7922 | case 0x0f3834: /* pmovzxwq */ | |
7923 | case 0x0f3835: /* pmovzxdq */ | |
7924 | case 0x0f3837: /* pcmpgtq */ | |
7925 | case 0x0f3838: /* pminsb */ | |
7926 | case 0x0f3839: /* pminsd */ | |
7927 | case 0x0f383a: /* pminuw */ | |
7928 | case 0x0f383b: /* pminud */ | |
7929 | case 0x0f383c: /* pmaxsb */ | |
7930 | case 0x0f383d: /* pmaxsd */ | |
7931 | case 0x0f383e: /* pmaxuw */ | |
7932 | case 0x0f383f: /* pmaxud */ | |
7933 | case 0x0f3840: /* pmulld */ | |
7934 | case 0x0f3841: /* phminposuw */ | |
7935 | case 0x0f3a0f: /* palignr */ | |
7936 | case 0x0f60: /* punpcklbw */ | |
7937 | case 0x0f61: /* punpcklwd */ | |
7938 | case 0x0f62: /* punpckldq */ | |
7939 | case 0x0f63: /* packsswb */ | |
7940 | case 0x0f64: /* pcmpgtb */ | |
7941 | case 0x0f65: /* pcmpgtw */ | |
7942 | case 0x0f66: /* pcmpgtd */ | |
7943 | case 0x0f67: /* packuswb */ | |
7944 | case 0x0f68: /* punpckhbw */ | |
7945 | case 0x0f69: /* punpckhwd */ | |
7946 | case 0x0f6a: /* punpckhdq */ | |
7947 | case 0x0f6b: /* packssdw */ | |
7948 | case 0x0f6e: /* movd */ | |
7949 | case 0x0f6f: /* movq */ | |
7950 | case 0x0f70: /* pshufw */ | |
7951 | case 0x0f74: /* pcmpeqb */ | |
7952 | case 0x0f75: /* pcmpeqw */ | |
7953 | case 0x0f76: /* pcmpeqd */ | |
7954 | case 0x0fc4: /* pinsrw */ | |
7955 | case 0x0fd1: /* psrlw */ | |
7956 | case 0x0fd2: /* psrld */ | |
7957 | case 0x0fd3: /* psrlq */ | |
7958 | case 0x0fd4: /* paddq */ | |
7959 | case 0x0fd5: /* pmullw */ | |
7960 | case 0xf20fd6: /* movdq2q */ | |
7961 | case 0x0fd8: /* psubusb */ | |
7962 | case 0x0fd9: /* psubusw */ | |
7963 | case 0x0fda: /* pminub */ | |
7964 | case 0x0fdb: /* pand */ | |
7965 | case 0x0fdc: /* paddusb */ | |
7966 | case 0x0fdd: /* paddusw */ | |
7967 | case 0x0fde: /* pmaxub */ | |
7968 | case 0x0fdf: /* pandn */ | |
7969 | case 0x0fe0: /* pavgb */ | |
7970 | case 0x0fe1: /* psraw */ | |
7971 | case 0x0fe2: /* psrad */ | |
7972 | case 0x0fe3: /* pavgw */ | |
7973 | case 0x0fe4: /* pmulhuw */ | |
7974 | case 0x0fe5: /* pmulhw */ | |
7975 | case 0x0fe8: /* psubsb */ | |
7976 | case 0x0fe9: /* psubsw */ | |
7977 | case 0x0fea: /* pminsw */ | |
7978 | case 0x0feb: /* por */ | |
7979 | case 0x0fec: /* paddsb */ | |
7980 | case 0x0fed: /* paddsw */ | |
7981 | case 0x0fee: /* pmaxsw */ | |
7982 | case 0x0fef: /* pxor */ | |
7983 | case 0x0ff1: /* psllw */ | |
7984 | case 0x0ff2: /* pslld */ | |
7985 | case 0x0ff3: /* psllq */ | |
7986 | case 0x0ff4: /* pmuludq */ | |
7987 | case 0x0ff5: /* pmaddwd */ | |
7988 | case 0x0ff6: /* psadbw */ | |
7989 | case 0x0ff8: /* psubb */ | |
7990 | case 0x0ff9: /* psubw */ | |
7991 | case 0x0ffa: /* psubd */ | |
7992 | case 0x0ffb: /* psubq */ | |
7993 | case 0x0ffc: /* paddb */ | |
7994 | case 0x0ffd: /* paddw */ | |
7995 | case 0x0ffe: /* paddd */ | |
7996 | if (i386_record_modrm (&ir)) | |
7997 | return -1; | |
7998 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7999 | goto no_support; | |
8000 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8001 | I387_MM0_REGNUM (tdep) + ir.reg); |
dda83cd7 | 8002 | break; |
a3c4230a | 8003 | |
dda83cd7 SM |
8004 | case 0x0f71: /* psllw */ |
8005 | case 0x0f72: /* pslld */ | |
8006 | case 0x0f73: /* psllq */ | |
8007 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8008 | return -1; |
dda83cd7 SM |
8009 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) |
8010 | goto no_support; | |
8011 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8012 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 8013 | break; |
a3c4230a | 8014 | |
dda83cd7 SM |
8015 | case 0x660f71: /* psllw */ |
8016 | case 0x660f72: /* pslld */ | |
8017 | case 0x660f73: /* psllq */ | |
8018 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8019 | return -1; |
dda83cd7 SM |
8020 | ir.rm |= ir.rex_b; |
8021 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) | |
8022 | goto no_support; | |
8023 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8024 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 8025 | break; |
a3c4230a | 8026 | |
dda83cd7 SM |
8027 | case 0x0f7e: /* movd */ |
8028 | case 0x660f7e: /* movd */ | |
8029 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8030 | return -1; |
dda83cd7 SM |
8031 | if (ir.mod == 3) |
8032 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
8033 | else | |
8034 | { | |
8035 | if (ir.dflag == 2) | |
8036 | ir.ot = OT_QUAD; | |
8037 | else | |
8038 | ir.ot = OT_LONG; | |
8039 | if (i386_record_lea_modrm (&ir)) | |
8040 | return -1; | |
8041 | } | |
8042 | break; | |
8043 | ||
8044 | case 0x0f7f: /* movq */ | |
8045 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8046 | return -1; |
dda83cd7 SM |
8047 | if (ir.mod == 3) |
8048 | { | |
8049 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8050 | goto no_support; | |
8051 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8052 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8053 | } |
8054 | else | |
8055 | { | |
8056 | ir.ot = OT_QUAD; | |
8057 | if (i386_record_lea_modrm (&ir)) | |
8058 | return -1; | |
8059 | } | |
8060 | break; | |
8061 | ||
8062 | case 0xf30fb8: /* popcnt */ | |
8063 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8064 | return -1; |
dda83cd7 SM |
8065 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8066 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8067 | break; | |
a3c4230a | 8068 | |
dda83cd7 SM |
8069 | case 0x660fd6: /* movq */ |
8070 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8071 | return -1; |
dda83cd7 SM |
8072 | if (ir.mod == 3) |
8073 | { | |
8074 | ir.rm |= ir.rex_b; | |
8075 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 8076 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
8077 | goto no_support; |
8078 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8079 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8080 | } |
8081 | else | |
8082 | { | |
8083 | ir.ot = OT_QUAD; | |
8084 | if (i386_record_lea_modrm (&ir)) | |
8085 | return -1; | |
8086 | } | |
8087 | break; | |
8088 | ||
8089 | case 0x660f3817: /* ptest */ | |
8090 | case 0x0f2e: /* ucomiss */ | |
8091 | case 0x660f2e: /* ucomisd */ | |
8092 | case 0x0f2f: /* comiss */ | |
8093 | case 0x660f2f: /* comisd */ | |
8094 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8095 | break; | |
8096 | ||
8097 | case 0x0ff7: /* maskmovq */ | |
8098 | regcache_raw_read_unsigned (ir.regcache, | |
8099 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8100 | &addr); | |
8101 | if (record_full_arch_list_add_mem (addr, 64)) | |
8102 | return -1; | |
8103 | break; | |
8104 | ||
8105 | case 0x660ff7: /* maskmovdqu */ | |
8106 | regcache_raw_read_unsigned (ir.regcache, | |
8107 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8108 | &addr); | |
8109 | if (record_full_arch_list_add_mem (addr, 128)) | |
8110 | return -1; | |
8111 | break; | |
8112 | ||
8113 | default: | |
8114 | goto no_support; | |
8115 | break; | |
8116 | } | |
a3c4230a | 8117 | break; |
7ad10968 HZ |
8118 | |
8119 | default: | |
7ad10968 HZ |
8120 | goto no_support; |
8121 | break; | |
8122 | } | |
8123 | ||
cf648174 | 8124 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8125 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8126 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8127 | return -1; |
8128 | ||
8129 | return 0; | |
8130 | ||
01fe1b41 | 8131 | no_support: |
a3c4230a | 8132 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
dda83cd7 SM |
8133 | "at address %s.\n"), |
8134 | (unsigned int) (opcode), | |
8135 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8136 | return -1; |
8137 | } | |
8138 | ||
cf648174 HZ |
8139 | static const int i386_record_regmap[] = |
8140 | { | |
8141 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8142 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8143 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8144 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8145 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8146 | }; | |
8147 | ||
7a697b8d | 8148 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8149 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8150 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8151 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8152 | middle of the tracepoint jump. On x86, it may be possible to use |
8153 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8154 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8155 | of instruction to replace, and 0 if not, plus an explanatory |
8156 | string. */ | |
8157 | ||
8158 | static int | |
6b940e6a | 8159 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
281d762b | 8160 | std::string *msg) |
7a697b8d SS |
8161 | { |
8162 | int len, jumplen; | |
7a697b8d | 8163 | |
405f8e94 SS |
8164 | /* Ask the target for the minimum instruction length supported. */ |
8165 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8166 | ||
8167 | if (jumplen < 0) | |
8168 | { | |
8169 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8170 | operation, assume that fast tracepoints will always be implemented | |
8171 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8172 | jumplen = 5; | |
8173 | } | |
8174 | else if (jumplen == 0) | |
8175 | { | |
8176 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8177 | returns zero, then the IPA has not loaded yet. In this case, | |
8178 | we optimistically assume that truncated 2-byte relative jumps | |
8179 | will be available on x86, and compensate later if this assumption | |
8180 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8181 | jumps will always be used. */ | |
8182 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8183 | } | |
7a697b8d | 8184 | |
7a697b8d | 8185 | /* Check for fit. */ |
be85ce7d | 8186 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8187 | |
7a697b8d SS |
8188 | if (len < jumplen) |
8189 | { | |
8190 | /* Return a bit of target-specific detail to add to the caller's | |
8191 | generic failure message. */ | |
8192 | if (msg) | |
281d762b TT |
8193 | *msg = string_printf (_("; instruction is only %d bytes long, " |
8194 | "need at least %d bytes for the jump"), | |
8195 | len, jumplen); | |
7a697b8d SS |
8196 | return 0; |
8197 | } | |
405f8e94 SS |
8198 | else |
8199 | { | |
8200 | if (msg) | |
281d762b | 8201 | msg->clear (); |
405f8e94 SS |
8202 | return 1; |
8203 | } | |
7a697b8d SS |
8204 | } |
8205 | ||
00d5215e UW |
8206 | /* Return a floating-point format for a floating-point variable of |
8207 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8208 | If no suitable type is found, return NULL. */ | |
8209 | ||
cb8c24b6 | 8210 | static const struct floatformat ** |
00d5215e UW |
8211 | i386_floatformat_for_type (struct gdbarch *gdbarch, |
8212 | const char *name, int len) | |
8213 | { | |
8214 | if (len == 128 && name) | |
8215 | if (strcmp (name, "__float128") == 0 | |
8216 | || strcmp (name, "_Float128") == 0 | |
34d11c68 AB |
8217 | || strcmp (name, "complex _Float128") == 0 |
8218 | || strcmp (name, "complex(kind=16)") == 0 | |
e56798df AKS |
8219 | || strcmp (name, "quad complex") == 0 |
8220 | || strcmp (name, "real(kind=16)") == 0 | |
8221 | || strcmp (name, "real*16") == 0) | |
00d5215e UW |
8222 | return floatformats_ia64_quad; |
8223 | ||
8224 | return default_floatformat_for_type (gdbarch, name, len); | |
8225 | } | |
8226 | ||
90884b2b L |
8227 | static int |
8228 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8229 | struct tdesc_arch_data *tdesc_data) | |
8230 | { | |
8231 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8232 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8233 | |
8234 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
1163a4b7 | 8235 | *feature_avx512, *feature_pkeys, *feature_segments; |
90884b2b L |
8236 | int i, num_regs, valid_p; |
8237 | ||
8238 | if (! tdesc_has_registers (tdesc)) | |
8239 | return 0; | |
8240 | ||
8241 | /* Get core registers. */ | |
8242 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8243 | if (feature_core == NULL) |
8244 | return 0; | |
90884b2b L |
8245 | |
8246 | /* Get SSE registers. */ | |
c131fcee | 8247 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8248 | |
c131fcee L |
8249 | /* Try AVX registers. */ |
8250 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8251 | ||
1dbcd68c WT |
8252 | /* Try MPX registers. */ |
8253 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8254 | ||
01f9f808 MS |
8255 | /* Try AVX512 registers. */ |
8256 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8257 | ||
1163a4b7 JB |
8258 | /* Try segment base registers. */ |
8259 | feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); | |
8260 | ||
51547df6 MS |
8261 | /* Try PKEYS */ |
8262 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8263 | ||
90884b2b L |
8264 | valid_p = 1; |
8265 | ||
c131fcee | 8266 | /* The XCR0 bits. */ |
01f9f808 MS |
8267 | if (feature_avx512) |
8268 | { | |
8269 | /* AVX512 register description requires AVX register description. */ | |
8270 | if (!feature_avx) | |
8271 | return 0; | |
8272 | ||
a1fa17ee | 8273 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8274 | |
8275 | /* It may have been set by OSABI initialization function. */ | |
8276 | if (tdep->k0_regnum < 0) | |
8277 | { | |
8278 | tdep->k_register_names = i386_k_names; | |
8279 | tdep->k0_regnum = I386_K0_REGNUM; | |
8280 | } | |
8281 | ||
8282 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8283 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8284 | tdep->k0_regnum + i, | |
8285 | i386_k_names[i]); | |
8286 | ||
8287 | if (tdep->num_zmm_regs == 0) | |
8288 | { | |
8289 | tdep->zmmh_register_names = i386_zmmh_names; | |
8290 | tdep->num_zmm_regs = 8; | |
8291 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8292 | } | |
8293 | ||
8294 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8295 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8296 | tdep->zmm0h_regnum + i, | |
8297 | tdep->zmmh_register_names[i]); | |
8298 | ||
8299 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8300 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8301 | tdep->xmm16_regnum + i, | |
8302 | tdep->xmm_avx512_register_names[i]); | |
8303 | ||
8304 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8305 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8306 | tdep->ymm16h_regnum + i, | |
8307 | tdep->ymm16h_register_names[i]); | |
8308 | } | |
c131fcee L |
8309 | if (feature_avx) |
8310 | { | |
3a13a53b L |
8311 | /* AVX register description requires SSE register description. */ |
8312 | if (!feature_sse) | |
8313 | return 0; | |
8314 | ||
01f9f808 | 8315 | if (!feature_avx512) |
df7e5265 | 8316 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8317 | |
8318 | /* It may have been set by OSABI initialization function. */ | |
8319 | if (tdep->num_ymm_regs == 0) | |
8320 | { | |
8321 | tdep->ymmh_register_names = i386_ymmh_names; | |
8322 | tdep->num_ymm_regs = 8; | |
8323 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8324 | } | |
8325 | ||
8326 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8327 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8328 | tdep->ymm0h_regnum + i, | |
8329 | tdep->ymmh_register_names[i]); | |
8330 | } | |
3a13a53b | 8331 | else if (feature_sse) |
df7e5265 | 8332 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8333 | else |
8334 | { | |
df7e5265 | 8335 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8336 | tdep->num_xmm_regs = 0; |
8337 | } | |
c131fcee | 8338 | |
90884b2b L |
8339 | num_regs = tdep->num_core_regs; |
8340 | for (i = 0; i < num_regs; i++) | |
8341 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8342 | tdep->register_names[i]); | |
8343 | ||
3a13a53b L |
8344 | if (feature_sse) |
8345 | { | |
8346 | /* Need to include %mxcsr, so add one. */ | |
8347 | num_regs += tdep->num_xmm_regs + 1; | |
8348 | for (; i < num_regs; i++) | |
8349 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8350 | tdep->register_names[i]); | |
8351 | } | |
90884b2b | 8352 | |
1dbcd68c WT |
8353 | if (feature_mpx) |
8354 | { | |
df7e5265 | 8355 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8356 | |
8357 | if (tdep->bnd0r_regnum < 0) | |
8358 | { | |
8359 | tdep->mpx_register_names = i386_mpx_names; | |
8360 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8361 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8362 | } | |
8363 | ||
8364 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8365 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8366 | I387_BND0R_REGNUM (tdep) + i, | |
8367 | tdep->mpx_register_names[i]); | |
8368 | } | |
8369 | ||
1163a4b7 JB |
8370 | if (feature_segments) |
8371 | { | |
8372 | if (tdep->fsbase_regnum < 0) | |
8373 | tdep->fsbase_regnum = I386_FSBASE_REGNUM; | |
8374 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8375 | tdep->fsbase_regnum, "fs_base"); | |
8376 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8377 | tdep->fsbase_regnum + 1, "gs_base"); | |
8378 | } | |
8379 | ||
51547df6 MS |
8380 | if (feature_pkeys) |
8381 | { | |
8382 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8383 | if (tdep->pkru_regnum < 0) | |
8384 | { | |
8385 | tdep->pkeys_register_names = i386_pkeys_names; | |
8386 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8387 | tdep->num_pkeys_regs = 1; | |
8388 | } | |
8389 | ||
8390 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8391 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8392 | I387_PKRU_REGNUM (tdep) + i, | |
8393 | tdep->pkeys_register_names[i]); | |
8394 | } | |
8395 | ||
90884b2b L |
8396 | return valid_p; |
8397 | } | |
8398 | ||
2b4424c3 TT |
8399 | \f |
8400 | ||
8401 | /* Implement the type_align gdbarch function. */ | |
8402 | ||
8403 | static ULONGEST | |
8404 | i386_type_align (struct gdbarch *gdbarch, struct type *type) | |
8405 | { | |
8406 | type = check_typedef (type); | |
8407 | ||
8408 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
8409 | { | |
78134374 SM |
8410 | if ((type->code () == TYPE_CODE_INT |
8411 | || type->code () == TYPE_CODE_FLT) | |
2b4424c3 TT |
8412 | && TYPE_LENGTH (type) > 4) |
8413 | return 4; | |
8414 | ||
8415 | /* Handle x86's funny long double. */ | |
78134374 | 8416 | if (type->code () == TYPE_CODE_FLT |
2b4424c3 TT |
8417 | && gdbarch_long_double_bit (gdbarch) == TYPE_LENGTH (type) * 8) |
8418 | return 4; | |
8419 | } | |
8420 | ||
5561fc30 | 8421 | return 0; |
2b4424c3 TT |
8422 | } |
8423 | ||
7ad10968 | 8424 | \f |
ad9eb1fd DE |
8425 | /* Note: This is called for both i386 and amd64. */ |
8426 | ||
7ad10968 HZ |
8427 | static struct gdbarch * |
8428 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8429 | { | |
8430 | struct gdbarch_tdep *tdep; | |
8431 | struct gdbarch *gdbarch; | |
90884b2b | 8432 | const struct target_desc *tdesc; |
1ba53b71 | 8433 | int mm0_regnum; |
c131fcee | 8434 | int ymm0_regnum; |
1dbcd68c WT |
8435 | int bnd0_regnum; |
8436 | int num_bnd_cooked; | |
7ad10968 HZ |
8437 | |
8438 | /* If there is already a candidate, use it. */ | |
8439 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8440 | if (arches != NULL) | |
8441 | return arches->gdbarch; | |
8442 | ||
ad9eb1fd | 8443 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8444 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8445 | gdbarch = gdbarch_alloc (&info, tdep); |
8446 | ||
8447 | /* General-purpose registers. */ | |
7ad10968 HZ |
8448 | tdep->gregset_reg_offset = NULL; |
8449 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8450 | tdep->sizeof_gregset = 0; | |
8451 | ||
8452 | /* Floating-point registers. */ | |
7ad10968 | 8453 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8454 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8455 | |
8456 | /* The default settings include the FPU registers, the MMX registers | |
8457 | and the SSE registers. This can be overridden for a specific ABI | |
8458 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8459 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8460 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8461 | |
8462 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8463 | ||
7ad10968 HZ |
8464 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8465 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8466 | ||
8467 | tdep->jb_pc_offset = -1; | |
8468 | tdep->struct_return = pcc_struct_return; | |
8469 | tdep->sigtramp_start = 0; | |
8470 | tdep->sigtramp_end = 0; | |
8471 | tdep->sigtramp_p = i386_sigtramp_p; | |
8472 | tdep->sigcontext_addr = NULL; | |
8473 | tdep->sc_reg_offset = NULL; | |
8474 | tdep->sc_pc_offset = -1; | |
8475 | tdep->sc_sp_offset = -1; | |
8476 | ||
c131fcee L |
8477 | tdep->xsave_xcr0_offset = -1; |
8478 | ||
cf648174 HZ |
8479 | tdep->record_regmap = i386_record_regmap; |
8480 | ||
2b4424c3 | 8481 | set_gdbarch_type_align (gdbarch, i386_type_align); |
205c306f | 8482 | |
7ad10968 HZ |
8483 | /* The format used for `long double' on almost all i386 targets is |
8484 | the i387 extended floating-point format. In fact, of all targets | |
8485 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8486 | on having a `long double' that's not `long' at all. */ | |
8487 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8488 | ||
8489 | /* Although the i387 extended floating-point has only 80 significant | |
8490 | bits, a `long double' actually takes up 96, probably to enforce | |
8491 | alignment. */ | |
8492 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8493 | ||
2a67f09d FW |
8494 | /* Support of bfloat16 format. */ |
8495 | set_gdbarch_bfloat16_format (gdbarch, floatformats_bfloat16); | |
8496 | ||
00d5215e UW |
8497 | /* Support for floating-point data type variants. */ |
8498 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8499 | ||
7ad10968 HZ |
8500 | /* Register numbers of various important registers. */ |
8501 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8502 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8503 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8504 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8505 | ||
8506 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8507 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8508 | differ in how they number %ebp, %esp, %eflags, and the | |
8509 | floating-point registers, and are implemented by the arrays | |
8510 | dbx_register_map[] and svr4_dbx_register_map in | |
8511 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8512 | gcc/config/i386.c, which it designates as the "default" register | |
8513 | map used in 64bit mode. This last register numbering scheme is | |
8514 | implemented in dbx64_register_map, and is used for AMD64; see | |
8515 | amd64-tdep.c. | |
8516 | ||
8517 | Currently, each GCC i386 target always uses the same register | |
8518 | numbering scheme across all its supported debugging formats | |
8519 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8520 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8521 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8522 | respective config header in a manner independent of the requested | |
8523 | output debugging format. | |
8524 | ||
8525 | This does not match the arrangement below, which presumes that | |
8526 | the SDB and stabs numbering schemes differ from the DWARF and | |
8527 | DWARF 2 ones. The reason for this arrangement is that it is | |
8528 | likely to get the numbering scheme for the target's | |
8529 | default/native debug format right. For targets where GCC is the | |
8530 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8531 | targets where the native toolchain uses a different numbering | |
8532 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8533 | the defaults below will have to be overridden, like | |
8534 | i386_elf_init_abi() does. */ | |
8535 | ||
8536 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8537 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8538 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8539 | ||
8540 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8541 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8542 | |
8543 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8544 | be in use on any of the supported i386 targets. */ | |
8545 | ||
8546 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8547 | ||
8548 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8549 | ||
8550 | /* Call dummy code. */ | |
a9b8d892 JK |
8551 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8552 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8553 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8554 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8555 | |
8556 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8557 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8558 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8559 | ||
8560 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8561 | ||
8562 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8563 | ||
8564 | /* Stack grows downward. */ | |
8565 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8566 | ||
04180708 YQ |
8567 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8568 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8569 | ||
7ad10968 HZ |
8570 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8571 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8572 | ||
8573 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8574 | ||
7ad10968 HZ |
8575 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8576 | ||
8577 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8578 | ||
8579 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8580 | ||
8581 | /* Add the i386 register groups. */ | |
8582 | i386_add_reggroups (gdbarch); | |
90884b2b | 8583 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8584 | |
143985b7 AF |
8585 | /* Helper for function argument information. */ |
8586 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8587 | ||
06da04c6 | 8588 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8589 | appended to the list first, so that it supercedes the DWARF |
8590 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8591 | currently fails). */ |
8592 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8593 | ||
8594 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8595 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8596 | CFI info will be used if it is available. */ |
10458914 | 8597 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8598 | |
acd5c798 | 8599 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8600 | |
1ba53b71 | 8601 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8602 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8603 | i386_pseudo_register_read_value); | |
90884b2b | 8604 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8605 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8606 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8607 | |
8608 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8609 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8610 | ||
c131fcee L |
8611 | /* Override the normal target description method to make the AVX |
8612 | upper halves anonymous. */ | |
8613 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8614 | ||
8615 | /* Even though the default ABI only includes general-purpose registers, | |
8616 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8617 | gap for the upper AVX, MPX and AVX512 registers. */ |
1163a4b7 | 8618 | set_gdbarch_num_regs (gdbarch, I386_NUM_REGS); |
90884b2b | 8619 | |
ac04f72b TT |
8620 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8621 | ||
90884b2b L |
8622 | /* Get the x86 target description from INFO. */ |
8623 | tdesc = info.target_desc; | |
8624 | if (! tdesc_has_registers (tdesc)) | |
1163a4b7 | 8625 | tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false); |
90884b2b L |
8626 | tdep->tdesc = tdesc; |
8627 | ||
8628 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8629 | tdep->register_names = i386_register_names; | |
8630 | ||
c131fcee L |
8631 | /* No upper YMM registers. */ |
8632 | tdep->ymmh_register_names = NULL; | |
8633 | tdep->ymm0h_regnum = -1; | |
8634 | ||
01f9f808 MS |
8635 | /* No upper ZMM registers. */ |
8636 | tdep->zmmh_register_names = NULL; | |
8637 | tdep->zmm0h_regnum = -1; | |
8638 | ||
8639 | /* No high XMM registers. */ | |
8640 | tdep->xmm_avx512_register_names = NULL; | |
8641 | tdep->xmm16_regnum = -1; | |
8642 | ||
8643 | /* No upper YMM16-31 registers. */ | |
8644 | tdep->ymm16h_register_names = NULL; | |
8645 | tdep->ymm16h_regnum = -1; | |
8646 | ||
1ba53b71 L |
8647 | tdep->num_byte_regs = 8; |
8648 | tdep->num_word_regs = 8; | |
8649 | tdep->num_dword_regs = 0; | |
8650 | tdep->num_mmx_regs = 8; | |
c131fcee | 8651 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8652 | |
1dbcd68c WT |
8653 | /* No MPX registers. */ |
8654 | tdep->bnd0r_regnum = -1; | |
8655 | tdep->bndcfgu_regnum = -1; | |
8656 | ||
01f9f808 MS |
8657 | /* No AVX512 registers. */ |
8658 | tdep->k0_regnum = -1; | |
8659 | tdep->num_zmm_regs = 0; | |
8660 | tdep->num_ymm_avx512_regs = 0; | |
8661 | tdep->num_xmm_avx512_regs = 0; | |
8662 | ||
51547df6 MS |
8663 | /* No PKEYS registers */ |
8664 | tdep->pkru_regnum = -1; | |
8665 | tdep->num_pkeys_regs = 0; | |
8666 | ||
1163a4b7 JB |
8667 | /* No segment base registers. */ |
8668 | tdep->fsbase_regnum = -1; | |
8669 | ||
c1e1314d | 8670 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
90884b2b | 8671 | |
dde08ee1 PA |
8672 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8673 | ||
6710bf39 SS |
8674 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8675 | ||
c2170eef MM |
8676 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8677 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8678 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8679 | ||
ad9eb1fd DE |
8680 | /* Hook in ABI-specific overrides, if they have been registered. |
8681 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8682 | a 32-bit i386 into a 64-bit amd64. */ | |
c1e1314d | 8683 | info.tdesc_data = tdesc_data.get (); |
4be87837 | 8684 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8685 | |
c1e1314d | 8686 | if (!i386_validate_tdesc_p (tdep, tdesc_data.get ())) |
c131fcee | 8687 | { |
c131fcee L |
8688 | xfree (tdep); |
8689 | gdbarch_free (gdbarch); | |
8690 | return NULL; | |
8691 | } | |
8692 | ||
1dbcd68c WT |
8693 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8694 | ||
1ba53b71 L |
8695 | /* Wire in pseudo registers. Number of pseudo registers may be |
8696 | changed. */ | |
8697 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8698 | + tdep->num_word_regs | |
8699 | + tdep->num_dword_regs | |
c131fcee | 8700 | + tdep->num_mmx_regs |
1dbcd68c | 8701 | + tdep->num_ymm_regs |
01f9f808 MS |
8702 | + num_bnd_cooked |
8703 | + tdep->num_ymm_avx512_regs | |
8704 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8705 | |
90884b2b L |
8706 | /* Target description may be changed. */ |
8707 | tdesc = tdep->tdesc; | |
8708 | ||
c1e1314d | 8709 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
90884b2b L |
8710 | |
8711 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8712 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8713 | ||
1ba53b71 L |
8714 | /* Make %al the first pseudo-register. */ |
8715 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8716 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8717 | ||
c131fcee | 8718 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8719 | if (tdep->num_dword_regs) |
8720 | { | |
1c6272a6 | 8721 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8722 | tdep->eax_regnum = ymm0_regnum; |
8723 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8724 | } |
8725 | else | |
8726 | tdep->eax_regnum = -1; | |
8727 | ||
c131fcee L |
8728 | mm0_regnum = ymm0_regnum; |
8729 | if (tdep->num_ymm_regs) | |
8730 | { | |
1c6272a6 | 8731 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8732 | tdep->ymm0_regnum = ymm0_regnum; |
8733 | mm0_regnum += tdep->num_ymm_regs; | |
8734 | } | |
8735 | else | |
8736 | tdep->ymm0_regnum = -1; | |
8737 | ||
01f9f808 MS |
8738 | if (tdep->num_ymm_avx512_regs) |
8739 | { | |
8740 | /* Support YMM16-31 pseudo registers if available. */ | |
8741 | tdep->ymm16_regnum = mm0_regnum; | |
8742 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8743 | } | |
8744 | else | |
8745 | tdep->ymm16_regnum = -1; | |
8746 | ||
8747 | if (tdep->num_zmm_regs) | |
8748 | { | |
8749 | /* Support ZMM pseudo-register if it is available. */ | |
8750 | tdep->zmm0_regnum = mm0_regnum; | |
8751 | mm0_regnum += tdep->num_zmm_regs; | |
8752 | } | |
8753 | else | |
8754 | tdep->zmm0_regnum = -1; | |
8755 | ||
1dbcd68c | 8756 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8757 | if (tdep->num_mmx_regs != 0) |
8758 | { | |
1c6272a6 | 8759 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8760 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8761 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8762 | } |
8763 | else | |
8764 | tdep->mm0_regnum = -1; | |
8765 | ||
1dbcd68c WT |
8766 | if (tdep->bnd0r_regnum > 0) |
8767 | tdep->bnd0_regnum = bnd0_regnum; | |
8768 | else | |
8769 | tdep-> bnd0_regnum = -1; | |
8770 | ||
06da04c6 | 8771 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8772 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8773 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8774 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8775 | |
8446b36a MK |
8776 | /* If we have a register mapping, enable the generic core file |
8777 | support, unless it has already been enabled. */ | |
8778 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8779 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8780 | set_gdbarch_iterate_over_regset_sections |
8781 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8782 | |
7a697b8d SS |
8783 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8784 | i386_fast_tracepoint_valid_at); | |
8785 | ||
a62cc96e AC |
8786 | return gdbarch; |
8787 | } | |
8788 | ||
8201327c MK |
8789 | \f |
8790 | ||
97de3545 JB |
8791 | /* Return the target description for a specified XSAVE feature mask. */ |
8792 | ||
8793 | const struct target_desc * | |
1163a4b7 | 8794 | i386_target_description (uint64_t xcr0, bool segments) |
97de3545 | 8795 | { |
22916b07 | 8796 | static target_desc *i386_tdescs \ |
1163a4b7 | 8797 | [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; |
22916b07 YQ |
8798 | target_desc **tdesc; |
8799 | ||
8800 | tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] | |
8801 | [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
8802 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
8803 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
1163a4b7 JB |
8804 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] |
8805 | [segments ? 1 : 0]; | |
22916b07 YQ |
8806 | |
8807 | if (*tdesc == NULL) | |
1163a4b7 | 8808 | *tdesc = i386_create_target_description (xcr0, false, segments); |
22916b07 YQ |
8809 | |
8810 | return *tdesc; | |
97de3545 JB |
8811 | } |
8812 | ||
29c1c244 WT |
8813 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8814 | ||
8815 | /* Find the bound directory base address. */ | |
8816 | ||
8817 | static unsigned long | |
8818 | i386_mpx_bd_base (void) | |
8819 | { | |
8820 | struct regcache *rcache; | |
8821 | struct gdbarch_tdep *tdep; | |
8822 | ULONGEST ret; | |
8823 | enum register_status regstatus; | |
29c1c244 WT |
8824 | |
8825 | rcache = get_current_regcache (); | |
ac7936df | 8826 | tdep = gdbarch_tdep (rcache->arch ()); |
29c1c244 WT |
8827 | |
8828 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8829 | ||
8830 | if (regstatus != REG_VALID) | |
8831 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8832 | ||
8833 | return ret & MPX_BASE_MASK; | |
8834 | } | |
8835 | ||
012b3a21 | 8836 | int |
29c1c244 WT |
8837 | i386_mpx_enabled (void) |
8838 | { | |
8839 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8840 | const struct target_desc *tdesc = tdep->tdesc; | |
8841 | ||
8842 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8843 | } | |
8844 | ||
8845 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8846 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8847 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8848 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8849 | ||
8850 | /* Find the bound table entry given the pointer location and the base | |
8851 | address of the table. */ | |
8852 | ||
8853 | static CORE_ADDR | |
8854 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8855 | { | |
8856 | CORE_ADDR offset1; | |
8857 | CORE_ADDR offset2; | |
8858 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8859 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8860 | CORE_ADDR bd_entry_addr; | |
8861 | CORE_ADDR bt_addr; | |
8862 | CORE_ADDR bd_entry; | |
8863 | struct gdbarch *gdbarch = get_current_arch (); | |
8864 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8865 | ||
8866 | ||
8867 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8868 | { | |
966f0aef | 8869 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8870 | bd_ptr_r_shift = 20; |
8871 | bd_ptr_l_shift = 3; | |
8872 | bt_select_r_shift = 3; | |
8873 | bt_select_l_shift = 5; | |
966f0aef WT |
8874 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8875 | ||
8876 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8877 | error (_("bound table examination not supported\ |
8878 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8879 | } |
8880 | else | |
8881 | { | |
8882 | mpx_bd_mask = MPX_BD_MASK_32; | |
8883 | bd_ptr_r_shift = 12; | |
8884 | bd_ptr_l_shift = 2; | |
8885 | bt_select_r_shift = 2; | |
8886 | bt_select_l_shift = 4; | |
8887 | bt_mask = MPX_BT_MASK_32; | |
8888 | } | |
8889 | ||
8890 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8891 | bd_entry_addr = bd_base + offset1; | |
8892 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8893 | ||
8894 | if ((bd_entry & 0x1) == 0) | |
8895 | error (_("Invalid bounds directory entry at %s."), | |
8896 | paddress (get_current_arch (), bd_entry_addr)); | |
8897 | ||
8898 | /* Clearing status bit. */ | |
8899 | bd_entry--; | |
8900 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8901 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8902 | ||
8903 | return bt_addr + offset2; | |
8904 | } | |
8905 | ||
8906 | /* Print routine for the mpx bounds. */ | |
8907 | ||
8908 | static void | |
8909 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8910 | { | |
8911 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8912 | LONGEST size; |
29c1c244 WT |
8913 | struct gdbarch *gdbarch = get_current_arch (); |
8914 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8915 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8916 | ||
8917 | if (bounds_in_map == 1) | |
8918 | { | |
112e8700 SM |
8919 | uiout->text ("Null bounds on map:"); |
8920 | uiout->text (" pointer value = "); | |
8921 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8922 | uiout->text ("."); | |
8923 | uiout->text ("\n"); | |
29c1c244 WT |
8924 | } |
8925 | else | |
8926 | { | |
112e8700 SM |
8927 | uiout->text ("{lbound = "); |
8928 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8929 | uiout->text (", ubound = "); | |
29c1c244 WT |
8930 | |
8931 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8932 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8933 | uiout->text ("}: pointer value = "); | |
8934 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8935 | |
8936 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8937 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8938 | else | |
8939 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8940 | ||
8941 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8942 | -1 represents in this sense full memory access, and there is no need | |
8943 | one to the size. */ | |
8944 | ||
8945 | size = (size > -1 ? size + 1 : size); | |
112e8700 | 8946 | uiout->text (", size = "); |
33eca680 | 8947 | uiout->field_string ("size", plongest (size)); |
29c1c244 | 8948 | |
112e8700 SM |
8949 | uiout->text (", metadata = "); |
8950 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8951 | uiout->text ("\n"); | |
29c1c244 WT |
8952 | } |
8953 | } | |
8954 | ||
8955 | /* Implement the command "show mpx bound". */ | |
8956 | ||
8957 | static void | |
c4a3e68e | 8958 | i386_mpx_info_bounds (const char *args, int from_tty) |
29c1c244 WT |
8959 | { |
8960 | CORE_ADDR bd_base = 0; | |
8961 | CORE_ADDR addr; | |
8962 | CORE_ADDR bt_entry_addr = 0; | |
8963 | CORE_ADDR bt_entry[4]; | |
8964 | int i; | |
8965 | struct gdbarch *gdbarch = get_current_arch (); | |
8966 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8967 | ||
ae71e7b5 MR |
8968 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8969 | || !i386_mpx_enabled ()) | |
118ca224 | 8970 | { |
bc504a31 | 8971 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8972 | "supported on this target.\n")); |
8973 | return; | |
8974 | } | |
29c1c244 WT |
8975 | |
8976 | if (args == NULL) | |
118ca224 PP |
8977 | { |
8978 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8979 | return; | |
8980 | } | |
29c1c244 WT |
8981 | |
8982 | addr = parse_and_eval_address (args); | |
8983 | ||
8984 | bd_base = i386_mpx_bd_base (); | |
8985 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8986 | ||
8987 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8988 | ||
8989 | for (i = 0; i < 4; i++) | |
8990 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8991 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8992 | data_ptr_type); |
8993 | ||
8994 | i386_mpx_print_bounds (bt_entry); | |
8995 | } | |
8996 | ||
8997 | /* Implement the command "set mpx bound". */ | |
8998 | ||
8999 | static void | |
c4a3e68e | 9000 | i386_mpx_set_bounds (const char *args, int from_tty) |
29c1c244 WT |
9001 | { |
9002 | CORE_ADDR bd_base = 0; | |
9003 | CORE_ADDR addr, lower, upper; | |
9004 | CORE_ADDR bt_entry_addr = 0; | |
9005 | CORE_ADDR bt_entry[2]; | |
9006 | const char *input = args; | |
9007 | int i; | |
9008 | struct gdbarch *gdbarch = get_current_arch (); | |
9009 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9010 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
9011 | ||
ae71e7b5 MR |
9012 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
9013 | || !i386_mpx_enabled ()) | |
bc504a31 | 9014 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
9015 | on this target.")); |
9016 | ||
9017 | if (args == NULL) | |
9018 | error (_("Pointer value expected.")); | |
9019 | ||
9020 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
9021 | ||
9022 | if (input[0] == ',') | |
9023 | ++input; | |
9024 | if (input[0] == '\0') | |
9025 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
9026 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
9027 | ||
9028 | if (input[0] == ',') | |
9029 | ++input; | |
9030 | if (input[0] == '\0') | |
9031 | error (_("Wrong number of arguments; Missing upper bound.")); | |
9032 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
9033 | ||
9034 | bd_base = i386_mpx_bd_base (); | |
9035 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
9036 | for (i = 0; i < 2; i++) | |
9037 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 9038 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
9039 | data_ptr_type); |
9040 | bt_entry[0] = (uint64_t) lower; | |
9041 | bt_entry[1] = ~(uint64_t) upper; | |
9042 | ||
9043 | for (i = 0; i < 2; i++) | |
132874d7 AB |
9044 | write_memory_unsigned_integer (bt_entry_addr |
9045 | + i * TYPE_LENGTH (data_ptr_type), | |
9046 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
9047 | bt_entry[i]); |
9048 | } | |
9049 | ||
9050 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
9051 | ||
6c265988 | 9052 | void _initialize_i386_tdep (); |
c906108c | 9053 | void |
6c265988 | 9054 | _initialize_i386_tdep () |
c906108c | 9055 | { |
a62cc96e AC |
9056 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
9057 | ||
fc338970 | 9058 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
9059 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
9060 | &disassembly_flavor, _("\ | |
9061 | Set the disassembly flavor."), _("\ | |
9062 | Show the disassembly flavor."), _("\ | |
9063 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
9064 | NULL, | |
9065 | NULL, /* FIXME: i18n: */ | |
9066 | &setlist, &showlist); | |
8201327c MK |
9067 | |
9068 | /* Add the variable that controls the convention for returning | |
9069 | structs. */ | |
7ab04401 AC |
9070 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9071 | &struct_convention, _("\ | |
9072 | Set the convention for returning small structs."), _("\ | |
9073 | Show the convention for returning small structs."), _("\ | |
9074 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9075 | is \"default\"."), | |
9076 | NULL, | |
9077 | NULL, /* FIXME: i18n: */ | |
9078 | &setlist, &showlist); | |
8201327c | 9079 | |
29c1c244 WT |
9080 | /* Add "mpx" prefix for the set commands. */ |
9081 | ||
0743fc83 | 9082 | add_basic_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9083 | Set Intel Memory Protection Extensions specific variables."), |
0743fc83 TT |
9084 | &mpx_set_cmdlist, "set mpx ", |
9085 | 0 /* allow-unknown */, &setlist); | |
29c1c244 WT |
9086 | |
9087 | /* Add "mpx" prefix for the show commands. */ | |
9088 | ||
0743fc83 | 9089 | add_show_prefix_cmd ("mpx", class_support, _("\ |
bc504a31 | 9090 | Show Intel Memory Protection Extensions specific variables."), |
0743fc83 TT |
9091 | &mpx_show_cmdlist, "show mpx ", |
9092 | 0 /* allow-unknown */, &showlist); | |
29c1c244 WT |
9093 | |
9094 | /* Add "bound" command for the show mpx commands list. */ | |
9095 | ||
9096 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9097 | "Show the memory bounds for a given array/pointer storage\ | |
9098 | in the bound table.", | |
9099 | &mpx_show_cmdlist); | |
9100 | ||
9101 | /* Add "bound" command for the set mpx commands list. */ | |
9102 | ||
9103 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9104 | "Set the memory bounds for a given array/pointer storage\ | |
9105 | in the bound table.", | |
9106 | &mpx_set_cmdlist); | |
9107 | ||
05816f70 | 9108 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9109 | i386_svr4_init_abi); |
38c968cf | 9110 | |
209bd28e | 9111 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9112 | i386_init_reggroups (); |
90884b2b | 9113 | |
c8d5aac9 L |
9114 | /* Tell remote stub that we support XML target description. */ |
9115 | register_remote_support_xml ("i386"); | |
c906108c | 9116 | } |