Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
61baf725 | 3 | Copyright (C) 1988-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
45741a9c | 31 | #include "infrun.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
df7e5265 | 49 | #include "x86-xstate.h" |
d2a7c97a | 50 | |
7ad10968 | 51 | #include "record.h" |
d02ed0bb | 52 | #include "record-full.h" |
90884b2b | 53 | #include "features/i386/i386.c" |
c131fcee | 54 | #include "features/i386/i386-avx.c" |
1dbcd68c | 55 | #include "features/i386/i386-mpx.c" |
2b863f51 | 56 | #include "features/i386/i386-avx-mpx.c" |
a1fa17ee | 57 | #include "features/i386/i386-avx-avx512.c" |
51547df6 | 58 | #include "features/i386/i386-avx-mpx-avx512-pku.c" |
3a13a53b | 59 | #include "features/i386/i386-mmx.c" |
90884b2b | 60 | |
6710bf39 SS |
61 | #include "ax.h" |
62 | #include "ax-gdb.h" | |
63 | ||
55aa24fb SDJ |
64 | #include "stap-probe.h" |
65 | #include "user-regs.h" | |
66 | #include "cli/cli-utils.h" | |
67 | #include "expression.h" | |
68 | #include "parser-defs.h" | |
69 | #include <ctype.h> | |
325fac50 | 70 | #include <algorithm> |
55aa24fb | 71 | |
c4fc7f1b | 72 | /* Register names. */ |
c40e1eab | 73 | |
90884b2b | 74 | static const char *i386_register_names[] = |
fc633446 MK |
75 | { |
76 | "eax", "ecx", "edx", "ebx", | |
77 | "esp", "ebp", "esi", "edi", | |
78 | "eip", "eflags", "cs", "ss", | |
79 | "ds", "es", "fs", "gs", | |
80 | "st0", "st1", "st2", "st3", | |
81 | "st4", "st5", "st6", "st7", | |
82 | "fctrl", "fstat", "ftag", "fiseg", | |
83 | "fioff", "foseg", "fooff", "fop", | |
84 | "xmm0", "xmm1", "xmm2", "xmm3", | |
85 | "xmm4", "xmm5", "xmm6", "xmm7", | |
86 | "mxcsr" | |
87 | }; | |
88 | ||
01f9f808 MS |
89 | static const char *i386_zmm_names[] = |
90 | { | |
91 | "zmm0", "zmm1", "zmm2", "zmm3", | |
92 | "zmm4", "zmm5", "zmm6", "zmm7" | |
93 | }; | |
94 | ||
95 | static const char *i386_zmmh_names[] = | |
96 | { | |
97 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
98 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
99 | }; | |
100 | ||
101 | static const char *i386_k_names[] = | |
102 | { | |
103 | "k0", "k1", "k2", "k3", | |
104 | "k4", "k5", "k6", "k7" | |
105 | }; | |
106 | ||
c131fcee L |
107 | static const char *i386_ymm_names[] = |
108 | { | |
109 | "ymm0", "ymm1", "ymm2", "ymm3", | |
110 | "ymm4", "ymm5", "ymm6", "ymm7", | |
111 | }; | |
112 | ||
113 | static const char *i386_ymmh_names[] = | |
114 | { | |
115 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
116 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
117 | }; | |
118 | ||
1dbcd68c WT |
119 | static const char *i386_mpx_names[] = |
120 | { | |
121 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
122 | }; | |
123 | ||
51547df6 MS |
124 | static const char* i386_pkeys_names[] = |
125 | { | |
126 | "pkru" | |
127 | }; | |
128 | ||
1dbcd68c WT |
129 | /* Register names for MPX pseudo-registers. */ |
130 | ||
131 | static const char *i386_bnd_names[] = | |
132 | { | |
133 | "bnd0", "bnd1", "bnd2", "bnd3" | |
134 | }; | |
135 | ||
c4fc7f1b | 136 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 137 | |
90884b2b | 138 | static const char *i386_mmx_names[] = |
28fc6740 AC |
139 | { |
140 | "mm0", "mm1", "mm2", "mm3", | |
141 | "mm4", "mm5", "mm6", "mm7" | |
142 | }; | |
c40e1eab | 143 | |
1ba53b71 L |
144 | /* Register names for byte pseudo-registers. */ |
145 | ||
146 | static const char *i386_byte_names[] = | |
147 | { | |
148 | "al", "cl", "dl", "bl", | |
149 | "ah", "ch", "dh", "bh" | |
150 | }; | |
151 | ||
152 | /* Register names for word pseudo-registers. */ | |
153 | ||
154 | static const char *i386_word_names[] = | |
155 | { | |
156 | "ax", "cx", "dx", "bx", | |
9cad29ac | 157 | "", "bp", "si", "di" |
1ba53b71 L |
158 | }; |
159 | ||
01f9f808 MS |
160 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
161 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
162 | we have 16 upper ZMM regs that have to be handled differently. */ | |
163 | ||
164 | const int num_lower_zmm_regs = 16; | |
165 | ||
1ba53b71 | 166 | /* MMX register? */ |
c40e1eab | 167 | |
28fc6740 | 168 | static int |
5716833c | 169 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 170 | { |
1ba53b71 L |
171 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
172 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
173 | |
174 | if (mm0_regnum < 0) | |
175 | return 0; | |
176 | ||
1ba53b71 L |
177 | regnum -= mm0_regnum; |
178 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
179 | } | |
180 | ||
181 | /* Byte register? */ | |
182 | ||
183 | int | |
184 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
185 | { | |
186 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
187 | ||
188 | regnum -= tdep->al_regnum; | |
189 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
190 | } | |
191 | ||
192 | /* Word register? */ | |
193 | ||
194 | int | |
195 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
196 | { | |
197 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
198 | ||
199 | regnum -= tdep->ax_regnum; | |
200 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
201 | } | |
202 | ||
203 | /* Dword register? */ | |
204 | ||
205 | int | |
206 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
207 | { | |
208 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
209 | int eax_regnum = tdep->eax_regnum; | |
210 | ||
211 | if (eax_regnum < 0) | |
212 | return 0; | |
213 | ||
214 | regnum -= eax_regnum; | |
215 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
216 | } |
217 | ||
01f9f808 MS |
218 | /* AVX512 register? */ |
219 | ||
220 | int | |
221 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
222 | { | |
223 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
224 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
225 | ||
226 | if (zmm0h_regnum < 0) | |
227 | return 0; | |
228 | ||
229 | regnum -= zmm0h_regnum; | |
230 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
231 | } | |
232 | ||
233 | int | |
234 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
235 | { | |
236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
237 | int zmm0_regnum = tdep->zmm0_regnum; | |
238 | ||
239 | if (zmm0_regnum < 0) | |
240 | return 0; | |
241 | ||
242 | regnum -= zmm0_regnum; | |
243 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
244 | } | |
245 | ||
246 | int | |
247 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
248 | { | |
249 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
250 | int k0_regnum = tdep->k0_regnum; | |
251 | ||
252 | if (k0_regnum < 0) | |
253 | return 0; | |
254 | ||
255 | regnum -= k0_regnum; | |
256 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
257 | } | |
258 | ||
9191d390 | 259 | static int |
c131fcee L |
260 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
261 | { | |
262 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
263 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
264 | ||
265 | if (ymm0h_regnum < 0) | |
266 | return 0; | |
267 | ||
268 | regnum -= ymm0h_regnum; | |
269 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
270 | } | |
271 | ||
272 | /* AVX register? */ | |
273 | ||
274 | int | |
275 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
276 | { | |
277 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
278 | int ymm0_regnum = tdep->ymm0_regnum; | |
279 | ||
280 | if (ymm0_regnum < 0) | |
281 | return 0; | |
282 | ||
283 | regnum -= ymm0_regnum; | |
284 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
285 | } | |
286 | ||
01f9f808 MS |
287 | static int |
288 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
289 | { | |
290 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
291 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
292 | ||
293 | if (ymm16h_regnum < 0) | |
294 | return 0; | |
295 | ||
296 | regnum -= ymm16h_regnum; | |
297 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
298 | } | |
299 | ||
300 | int | |
301 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
302 | { | |
303 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
304 | int ymm16_regnum = tdep->ymm16_regnum; | |
305 | ||
306 | if (ymm16_regnum < 0) | |
307 | return 0; | |
308 | ||
309 | regnum -= ymm16_regnum; | |
310 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
311 | } | |
312 | ||
1dbcd68c WT |
313 | /* BND register? */ |
314 | ||
315 | int | |
316 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
317 | { | |
318 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
319 | int bnd0_regnum = tdep->bnd0_regnum; | |
320 | ||
321 | if (bnd0_regnum < 0) | |
322 | return 0; | |
323 | ||
324 | regnum -= bnd0_regnum; | |
325 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
326 | } | |
327 | ||
5716833c | 328 | /* SSE register? */ |
23a34459 | 329 | |
c131fcee L |
330 | int |
331 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 332 | { |
5716833c | 333 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 334 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 335 | |
c131fcee | 336 | if (num_xmm_regs == 0) |
5716833c MK |
337 | return 0; |
338 | ||
c131fcee L |
339 | regnum -= I387_XMM0_REGNUM (tdep); |
340 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
341 | } |
342 | ||
01f9f808 MS |
343 | /* XMM_512 register? */ |
344 | ||
345 | int | |
346 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
347 | { | |
348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
349 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
350 | ||
351 | if (num_xmm_avx512_regs == 0) | |
352 | return 0; | |
353 | ||
354 | regnum -= I387_XMM16_REGNUM (tdep); | |
355 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
356 | } | |
357 | ||
5716833c MK |
358 | static int |
359 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 360 | { |
5716833c MK |
361 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
362 | ||
20a6ec49 | 363 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
364 | return 0; |
365 | ||
20a6ec49 | 366 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
367 | } |
368 | ||
5716833c | 369 | /* FP register? */ |
23a34459 AC |
370 | |
371 | int | |
20a6ec49 | 372 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 373 | { |
20a6ec49 MD |
374 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
375 | ||
376 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
377 | return 0; |
378 | ||
20a6ec49 MD |
379 | return (I387_ST0_REGNUM (tdep) <= regnum |
380 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
381 | } |
382 | ||
383 | int | |
20a6ec49 | 384 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 385 | { |
20a6ec49 MD |
386 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
387 | ||
388 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
389 | return 0; |
390 | ||
20a6ec49 MD |
391 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
392 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
393 | } |
394 | ||
1dbcd68c WT |
395 | /* BNDr (raw) register? */ |
396 | ||
397 | static int | |
398 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
399 | { | |
400 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
401 | ||
402 | if (I387_BND0R_REGNUM (tdep) < 0) | |
403 | return 0; | |
404 | ||
405 | regnum -= tdep->bnd0r_regnum; | |
406 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
407 | } | |
408 | ||
409 | /* BND control register? */ | |
410 | ||
411 | static int | |
412 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
413 | { | |
414 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
415 | ||
416 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
417 | return 0; | |
418 | ||
419 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
420 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
421 | } | |
422 | ||
51547df6 MS |
423 | /* PKRU register? */ |
424 | ||
425 | bool | |
426 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
427 | { | |
428 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
429 | int pkru_regnum = tdep->pkru_regnum; | |
430 | ||
431 | if (pkru_regnum < 0) | |
432 | return false; | |
433 | ||
434 | regnum -= pkru_regnum; | |
435 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
436 | } | |
437 | ||
c131fcee L |
438 | /* Return the name of register REGNUM, or the empty string if it is |
439 | an anonymous register. */ | |
440 | ||
441 | static const char * | |
442 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
443 | { | |
444 | /* Hide the upper YMM registers. */ | |
445 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
446 | return ""; | |
447 | ||
01f9f808 MS |
448 | /* Hide the upper YMM16-31 registers. */ |
449 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
450 | return ""; | |
451 | ||
452 | /* Hide the upper ZMM registers. */ | |
453 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
454 | return ""; | |
455 | ||
c131fcee L |
456 | return tdesc_register_name (gdbarch, regnum); |
457 | } | |
458 | ||
30b0e2d8 | 459 | /* Return the name of register REGNUM. */ |
fc633446 | 460 | |
1ba53b71 | 461 | const char * |
90884b2b | 462 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 463 | { |
1ba53b71 | 464 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
465 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
466 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
467 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
468 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
469 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
470 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
471 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
472 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
473 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
474 | return i386_byte_names[regnum - tdep->al_regnum]; | |
475 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
476 | return i386_word_names[regnum - tdep->ax_regnum]; | |
477 | ||
478 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
479 | } |
480 | ||
c4fc7f1b | 481 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
482 | number used by GDB. */ |
483 | ||
8201327c | 484 | static int |
d3f73121 | 485 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 486 | { |
20a6ec49 MD |
487 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
488 | ||
c4fc7f1b MK |
489 | /* This implements what GCC calls the "default" register map |
490 | (dbx_register_map[]). */ | |
491 | ||
85540d8c MK |
492 | if (reg >= 0 && reg <= 7) |
493 | { | |
9872ad24 JB |
494 | /* General-purpose registers. The debug info calls %ebp |
495 | register 4, and %esp register 5. */ | |
496 | if (reg == 4) | |
497 | return 5; | |
498 | else if (reg == 5) | |
499 | return 4; | |
500 | else return reg; | |
85540d8c MK |
501 | } |
502 | else if (reg >= 12 && reg <= 19) | |
503 | { | |
504 | /* Floating-point registers. */ | |
20a6ec49 | 505 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
506 | } |
507 | else if (reg >= 21 && reg <= 28) | |
508 | { | |
509 | /* SSE registers. */ | |
c131fcee L |
510 | int ymm0_regnum = tdep->ymm0_regnum; |
511 | ||
512 | if (ymm0_regnum >= 0 | |
513 | && i386_xmm_regnum_p (gdbarch, reg)) | |
514 | return reg - 21 + ymm0_regnum; | |
515 | else | |
516 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
517 | } |
518 | else if (reg >= 29 && reg <= 36) | |
519 | { | |
520 | /* MMX registers. */ | |
20a6ec49 | 521 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
522 | } |
523 | ||
524 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 525 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
526 | } |
527 | ||
0fde2c53 | 528 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 529 | used by GDB. */ |
85540d8c | 530 | |
8201327c | 531 | static int |
0fde2c53 | 532 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 533 | { |
20a6ec49 MD |
534 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
535 | ||
c4fc7f1b MK |
536 | /* This implements the GCC register map that tries to be compatible |
537 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
538 | ||
539 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
540 | numbers the floating point registers differently. */ |
541 | if (reg >= 0 && reg <= 9) | |
542 | { | |
acd5c798 | 543 | /* General-purpose registers. */ |
85540d8c MK |
544 | return reg; |
545 | } | |
546 | else if (reg >= 11 && reg <= 18) | |
547 | { | |
548 | /* Floating-point registers. */ | |
20a6ec49 | 549 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 550 | } |
c6f4c129 | 551 | else if (reg >= 21 && reg <= 36) |
85540d8c | 552 | { |
c4fc7f1b | 553 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 554 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
555 | } |
556 | ||
c6f4c129 JB |
557 | switch (reg) |
558 | { | |
20a6ec49 MD |
559 | case 37: return I387_FCTRL_REGNUM (tdep); |
560 | case 38: return I387_FSTAT_REGNUM (tdep); | |
561 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
562 | case 40: return I386_ES_REGNUM; |
563 | case 41: return I386_CS_REGNUM; | |
564 | case 42: return I386_SS_REGNUM; | |
565 | case 43: return I386_DS_REGNUM; | |
566 | case 44: return I386_FS_REGNUM; | |
567 | case 45: return I386_GS_REGNUM; | |
568 | } | |
569 | ||
0fde2c53 DE |
570 | return -1; |
571 | } | |
572 | ||
573 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
574 | num_regs + num_pseudo_regs for other debug formats. */ | |
575 | ||
576 | static int | |
577 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
578 | { | |
579 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
580 | ||
581 | if (regnum == -1) | |
582 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
583 | return regnum; | |
85540d8c | 584 | } |
5716833c | 585 | |
fc338970 | 586 | \f |
917317f4 | 587 | |
fc338970 MK |
588 | /* This is the variable that is set with "set disassembly-flavor", and |
589 | its legitimate values. */ | |
53904c9e AC |
590 | static const char att_flavor[] = "att"; |
591 | static const char intel_flavor[] = "intel"; | |
40478521 | 592 | static const char *const valid_flavors[] = |
c5aa993b | 593 | { |
c906108c SS |
594 | att_flavor, |
595 | intel_flavor, | |
596 | NULL | |
597 | }; | |
53904c9e | 598 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 599 | \f |
c906108c | 600 | |
acd5c798 MK |
601 | /* Use the program counter to determine the contents and size of a |
602 | breakpoint instruction. Return a pointer to a string of bytes that | |
603 | encode a breakpoint instruction, store the length of the string in | |
604 | *LEN and optionally adjust *PC to point to the correct memory | |
605 | location for inserting the breakpoint. | |
c906108c | 606 | |
acd5c798 MK |
607 | On the i386 we have a single breakpoint that fits in a single byte |
608 | and can be inserted anywhere. | |
c906108c | 609 | |
acd5c798 | 610 | This function is 64-bit safe. */ |
63c0089f | 611 | |
04180708 YQ |
612 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
613 | ||
614 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 615 | |
237fc4c9 PA |
616 | \f |
617 | /* Displaced instruction handling. */ | |
618 | ||
1903f0e6 DE |
619 | /* Skip the legacy instruction prefixes in INSN. |
620 | Not all prefixes are valid for any particular insn | |
621 | but we needn't care, the insn will fault if it's invalid. | |
622 | The result is a pointer to the first opcode byte, | |
623 | or NULL if we run off the end of the buffer. */ | |
624 | ||
625 | static gdb_byte * | |
626 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
627 | { | |
628 | gdb_byte *end = insn + max_len; | |
629 | ||
630 | while (insn < end) | |
631 | { | |
632 | switch (*insn) | |
633 | { | |
634 | case DATA_PREFIX_OPCODE: | |
635 | case ADDR_PREFIX_OPCODE: | |
636 | case CS_PREFIX_OPCODE: | |
637 | case DS_PREFIX_OPCODE: | |
638 | case ES_PREFIX_OPCODE: | |
639 | case FS_PREFIX_OPCODE: | |
640 | case GS_PREFIX_OPCODE: | |
641 | case SS_PREFIX_OPCODE: | |
642 | case LOCK_PREFIX_OPCODE: | |
643 | case REPE_PREFIX_OPCODE: | |
644 | case REPNE_PREFIX_OPCODE: | |
645 | ++insn; | |
646 | continue; | |
647 | default: | |
648 | return insn; | |
649 | } | |
650 | } | |
651 | ||
652 | return NULL; | |
653 | } | |
237fc4c9 PA |
654 | |
655 | static int | |
1903f0e6 | 656 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 657 | { |
1777feb0 | 658 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
659 | if (insn[0] == 0xea) |
660 | return 1; | |
661 | ||
662 | if (insn[0] == 0xff) | |
663 | { | |
1777feb0 | 664 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
665 | if ((insn[1] & 0x38) == 0x20) |
666 | return 1; | |
667 | ||
1777feb0 | 668 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
669 | if ((insn[1] & 0x38) == 0x28) |
670 | return 1; | |
671 | } | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
c2170eef MM |
676 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
677 | ||
678 | static int | |
679 | i386_jmp_p (const gdb_byte *insn) | |
680 | { | |
681 | /* jump short, relative. */ | |
682 | if (insn[0] == 0xeb) | |
683 | return 1; | |
684 | ||
685 | /* jump near, relative. */ | |
686 | if (insn[0] == 0xe9) | |
687 | return 1; | |
688 | ||
689 | return i386_absolute_jmp_p (insn); | |
690 | } | |
691 | ||
237fc4c9 | 692 | static int |
1903f0e6 | 693 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 694 | { |
1777feb0 | 695 | /* call far, absolute. */ |
237fc4c9 PA |
696 | if (insn[0] == 0x9a) |
697 | return 1; | |
698 | ||
699 | if (insn[0] == 0xff) | |
700 | { | |
1777feb0 | 701 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
702 | if ((insn[1] & 0x38) == 0x10) |
703 | return 1; | |
704 | ||
1777feb0 | 705 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
706 | if ((insn[1] & 0x38) == 0x18) |
707 | return 1; | |
708 | } | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int | |
1903f0e6 | 714 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
715 | { |
716 | switch (insn[0]) | |
717 | { | |
1777feb0 | 718 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 719 | case 0xc3: /* ret near */ |
1777feb0 | 720 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
721 | case 0xcb: /* ret far */ |
722 | case 0xcf: /* iret */ | |
723 | return 1; | |
724 | ||
725 | default: | |
726 | return 0; | |
727 | } | |
728 | } | |
729 | ||
730 | static int | |
1903f0e6 | 731 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
732 | { |
733 | if (i386_absolute_call_p (insn)) | |
734 | return 1; | |
735 | ||
1777feb0 | 736 | /* call near, relative. */ |
237fc4c9 PA |
737 | if (insn[0] == 0xe8) |
738 | return 1; | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
237fc4c9 PA |
743 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
744 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 745 | |
237fc4c9 | 746 | static int |
b55078be | 747 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 748 | { |
9a7f938f JK |
749 | /* Is it 'int $0x80'? */ |
750 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
751 | /* Or is it 'sysenter'? */ | |
752 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
753 | /* Or is it 'syscall'? */ | |
754 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
755 | { |
756 | *lengthp = 2; | |
757 | return 1; | |
758 | } | |
759 | ||
760 | return 0; | |
761 | } | |
762 | ||
c2170eef MM |
763 | /* The gdbarch insn_is_call method. */ |
764 | ||
765 | static int | |
766 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
767 | { | |
768 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
769 | ||
770 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
771 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
772 | ||
773 | return i386_call_p (insn); | |
774 | } | |
775 | ||
776 | /* The gdbarch insn_is_ret method. */ | |
777 | ||
778 | static int | |
779 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
780 | { | |
781 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
782 | ||
783 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
784 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
785 | ||
786 | return i386_ret_p (insn); | |
787 | } | |
788 | ||
789 | /* The gdbarch insn_is_jump method. */ | |
790 | ||
791 | static int | |
792 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
793 | { | |
794 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
795 | ||
796 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
797 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
798 | ||
799 | return i386_jmp_p (insn); | |
800 | } | |
801 | ||
b55078be DE |
802 | /* Some kernels may run one past a syscall insn, so we have to cope. |
803 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
804 | ||
805 | struct displaced_step_closure * | |
806 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
807 | CORE_ADDR from, CORE_ADDR to, | |
808 | struct regcache *regs) | |
809 | { | |
810 | size_t len = gdbarch_max_insn_length (gdbarch); | |
224c3ddb | 811 | gdb_byte *buf = (gdb_byte *) xmalloc (len); |
b55078be DE |
812 | |
813 | read_memory (from, buf, len); | |
814 | ||
815 | /* GDB may get control back after the insn after the syscall. | |
816 | Presumably this is a kernel bug. | |
817 | If this is a syscall, make sure there's a nop afterwards. */ | |
818 | { | |
819 | int syscall_length; | |
820 | gdb_byte *insn; | |
821 | ||
822 | insn = i386_skip_prefixes (buf, len); | |
823 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
824 | insn[syscall_length] = NOP_OPCODE; | |
825 | } | |
826 | ||
827 | write_memory (to, buf, len); | |
828 | ||
829 | if (debug_displaced) | |
830 | { | |
831 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
832 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
833 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
834 | } | |
835 | ||
836 | return (struct displaced_step_closure *) buf; | |
837 | } | |
838 | ||
237fc4c9 PA |
839 | /* Fix up the state of registers and memory after having single-stepped |
840 | a displaced instruction. */ | |
1903f0e6 | 841 | |
237fc4c9 PA |
842 | void |
843 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
844 | struct displaced_step_closure *closure, | |
845 | CORE_ADDR from, CORE_ADDR to, | |
846 | struct regcache *regs) | |
847 | { | |
e17a4113 UW |
848 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
849 | ||
237fc4c9 PA |
850 | /* The offset we applied to the instruction's address. |
851 | This could well be negative (when viewed as a signed 32-bit | |
852 | value), but ULONGEST won't reflect that, so take care when | |
853 | applying it. */ | |
854 | ULONGEST insn_offset = to - from; | |
855 | ||
856 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
857 | copy of the instruction. */ | |
858 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
859 | /* The start of the insn, needed in case we see some prefixes. */ |
860 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
861 | |
862 | if (debug_displaced) | |
863 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 864 | "displaced: fixup (%s, %s), " |
237fc4c9 | 865 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
866 | paddress (gdbarch, from), paddress (gdbarch, to), |
867 | insn[0], insn[1]); | |
237fc4c9 PA |
868 | |
869 | /* The list of issues to contend with here is taken from | |
870 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
871 | Yay for Free Software! */ | |
872 | ||
873 | /* Relocate the %eip, if necessary. */ | |
874 | ||
1903f0e6 DE |
875 | /* The instruction recognizers we use assume any leading prefixes |
876 | have been skipped. */ | |
877 | { | |
878 | /* This is the size of the buffer in closure. */ | |
879 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
880 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
881 | /* If there are too many prefixes, just ignore the insn. | |
882 | It will fault when run. */ | |
883 | if (opcode != NULL) | |
884 | insn = opcode; | |
885 | } | |
886 | ||
237fc4c9 PA |
887 | /* Except in the case of absolute or indirect jump or call |
888 | instructions, or a return instruction, the new eip is relative to | |
889 | the displaced instruction; make it relative. Well, signal | |
890 | handler returns don't need relocation either, but we use the | |
891 | value of %eip to recognize those; see below. */ | |
892 | if (! i386_absolute_jmp_p (insn) | |
893 | && ! i386_absolute_call_p (insn) | |
894 | && ! i386_ret_p (insn)) | |
895 | { | |
896 | ULONGEST orig_eip; | |
b55078be | 897 | int insn_len; |
237fc4c9 PA |
898 | |
899 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
900 | ||
901 | /* A signal trampoline system call changes the %eip, resuming | |
902 | execution of the main program after the signal handler has | |
903 | returned. That makes them like 'return' instructions; we | |
904 | shouldn't relocate %eip. | |
905 | ||
906 | But most system calls don't, and we do need to relocate %eip. | |
907 | ||
908 | Our heuristic for distinguishing these cases: if stepping | |
909 | over the system call instruction left control directly after | |
910 | the instruction, the we relocate --- control almost certainly | |
911 | doesn't belong in the displaced copy. Otherwise, we assume | |
912 | the instruction has put control where it belongs, and leave | |
913 | it unrelocated. Goodness help us if there are PC-relative | |
914 | system calls. */ | |
915 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
916 | && orig_eip != to + (insn - insn_start) + insn_len |
917 | /* GDB can get control back after the insn after the syscall. | |
918 | Presumably this is a kernel bug. | |
919 | i386_displaced_step_copy_insn ensures its a nop, | |
920 | we add one to the length for it. */ | |
921 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
922 | { |
923 | if (debug_displaced) | |
924 | fprintf_unfiltered (gdb_stdlog, | |
925 | "displaced: syscall changed %%eip; " | |
926 | "not relocating\n"); | |
927 | } | |
928 | else | |
929 | { | |
930 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
931 | ||
1903f0e6 DE |
932 | /* If we just stepped over a breakpoint insn, we don't backup |
933 | the pc on purpose; this is to match behaviour without | |
934 | stepping. */ | |
237fc4c9 PA |
935 | |
936 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
937 | ||
938 | if (debug_displaced) | |
939 | fprintf_unfiltered (gdb_stdlog, | |
940 | "displaced: " | |
5af949e3 UW |
941 | "relocated %%eip from %s to %s\n", |
942 | paddress (gdbarch, orig_eip), | |
943 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
944 | } |
945 | } | |
946 | ||
947 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
948 | pushed value, and should be cleared. We'll leave this for later, | |
949 | since GDB already messes up the TF flag when stepping over a | |
950 | pushfl. */ | |
951 | ||
952 | /* If the instruction was a call, the return address now atop the | |
953 | stack is the address following the copied instruction. We need | |
954 | to make it the address following the original instruction. */ | |
955 | if (i386_call_p (insn)) | |
956 | { | |
957 | ULONGEST esp; | |
958 | ULONGEST retaddr; | |
959 | const ULONGEST retaddr_len = 4; | |
960 | ||
961 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 962 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 963 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 964 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
965 | |
966 | if (debug_displaced) | |
967 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
968 | "displaced: relocated return addr at %s to %s\n", |
969 | paddress (gdbarch, esp), | |
970 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
971 | } |
972 | } | |
dde08ee1 PA |
973 | |
974 | static void | |
975 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
976 | { | |
977 | target_write_memory (*to, buf, len); | |
978 | *to += len; | |
979 | } | |
980 | ||
981 | static void | |
982 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
983 | CORE_ADDR *to, CORE_ADDR oldloc) | |
984 | { | |
985 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
986 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
987 | int offset = 0, rel32, newrel; | |
988 | int insn_length; | |
989 | gdb_byte *insn = buf; | |
990 | ||
991 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
992 | ||
993 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
994 | I386_MAX_INSN_LEN, oldloc); | |
995 | ||
996 | /* Get past the prefixes. */ | |
997 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
998 | ||
999 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
1000 | the address pushed being the location where the original call in | |
1001 | the user program would return to. */ | |
1002 | if (insn[0] == 0xe8) | |
1003 | { | |
1004 | gdb_byte push_buf[16]; | |
1005 | unsigned int ret_addr; | |
1006 | ||
1007 | /* Where "ret" in the original code will return to. */ | |
1008 | ret_addr = oldloc + insn_length; | |
1777feb0 | 1009 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 1010 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
1011 | /* Push the push. */ |
1012 | append_insns (to, 5, push_buf); | |
1013 | ||
1014 | /* Convert the relative call to a relative jump. */ | |
1015 | insn[0] = 0xe9; | |
1016 | ||
1017 | /* Adjust the destination offset. */ | |
1018 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1019 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1020 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1021 | ||
1022 | if (debug_displaced) | |
1023 | fprintf_unfiltered (gdb_stdlog, | |
1024 | "Adjusted insn rel32=%s at %s to" | |
1025 | " rel32=%s at %s\n", | |
1026 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1027 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1028 | |
1029 | /* Write the adjusted jump into its displaced location. */ | |
1030 | append_insns (to, 5, insn); | |
1031 | return; | |
1032 | } | |
1033 | ||
1034 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1035 | handled above. */ | |
1036 | if (insn[0] == 0xe9) | |
1037 | offset = 1; | |
1038 | /* Adjust conditional jumps. */ | |
1039 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1040 | offset = 2; | |
1041 | ||
1042 | if (offset) | |
1043 | { | |
1044 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1045 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1046 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1047 | if (debug_displaced) |
1048 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1049 | "Adjusted insn rel32=%s at %s to" |
1050 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1051 | hex_string (rel32), paddress (gdbarch, oldloc), |
1052 | hex_string (newrel), paddress (gdbarch, *to)); | |
1053 | } | |
1054 | ||
1055 | /* Write the adjusted instructions into their displaced | |
1056 | location. */ | |
1057 | append_insns (to, insn_length, buf); | |
1058 | } | |
1059 | ||
fc338970 | 1060 | \f |
acd5c798 MK |
1061 | #ifdef I386_REGNO_TO_SYMMETRY |
1062 | #error "The Sequent Symmetry is no longer supported." | |
1063 | #endif | |
c906108c | 1064 | |
acd5c798 MK |
1065 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1066 | and %esp "belong" to the calling function. Therefore these | |
1067 | registers should be saved if they're going to be modified. */ | |
c906108c | 1068 | |
acd5c798 MK |
1069 | /* The maximum number of saved registers. This should include all |
1070 | registers mentioned above, and %eip. */ | |
a3386186 | 1071 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1072 | |
1073 | struct i386_frame_cache | |
c906108c | 1074 | { |
acd5c798 MK |
1075 | /* Base address. */ |
1076 | CORE_ADDR base; | |
8fbca658 | 1077 | int base_p; |
772562f8 | 1078 | LONGEST sp_offset; |
acd5c798 MK |
1079 | CORE_ADDR pc; |
1080 | ||
fd13a04a AC |
1081 | /* Saved registers. */ |
1082 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1083 | CORE_ADDR saved_sp; |
e0c62198 | 1084 | int saved_sp_reg; |
acd5c798 MK |
1085 | int pc_in_eax; |
1086 | ||
1087 | /* Stack space reserved for local variables. */ | |
1088 | long locals; | |
1089 | }; | |
1090 | ||
1091 | /* Allocate and initialize a frame cache. */ | |
1092 | ||
1093 | static struct i386_frame_cache * | |
fd13a04a | 1094 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1095 | { |
1096 | struct i386_frame_cache *cache; | |
1097 | int i; | |
1098 | ||
1099 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1100 | ||
1101 | /* Base address. */ | |
8fbca658 | 1102 | cache->base_p = 0; |
acd5c798 MK |
1103 | cache->base = 0; |
1104 | cache->sp_offset = -4; | |
1105 | cache->pc = 0; | |
1106 | ||
fd13a04a AC |
1107 | /* Saved registers. We initialize these to -1 since zero is a valid |
1108 | offset (that's where %ebp is supposed to be stored). */ | |
1109 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1110 | cache->saved_regs[i] = -1; | |
acd5c798 | 1111 | cache->saved_sp = 0; |
e0c62198 | 1112 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1113 | cache->pc_in_eax = 0; |
1114 | ||
1115 | /* Frameless until proven otherwise. */ | |
1116 | cache->locals = -1; | |
1117 | ||
1118 | return cache; | |
1119 | } | |
c906108c | 1120 | |
acd5c798 MK |
1121 | /* If the instruction at PC is a jump, return the address of its |
1122 | target. Otherwise, return PC. */ | |
c906108c | 1123 | |
acd5c798 | 1124 | static CORE_ADDR |
e17a4113 | 1125 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1126 | { |
e17a4113 | 1127 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1128 | gdb_byte op; |
acd5c798 MK |
1129 | long delta = 0; |
1130 | int data16 = 0; | |
c906108c | 1131 | |
0865b04a | 1132 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1133 | return pc; |
1134 | ||
acd5c798 | 1135 | if (op == 0x66) |
c906108c | 1136 | { |
c906108c | 1137 | data16 = 1; |
0865b04a YQ |
1138 | |
1139 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1140 | } |
1141 | ||
acd5c798 | 1142 | switch (op) |
c906108c SS |
1143 | { |
1144 | case 0xe9: | |
fc338970 | 1145 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1146 | if (data16) |
1147 | { | |
e17a4113 | 1148 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1149 | |
fc338970 MK |
1150 | /* Include the size of the jmp instruction (including the |
1151 | 0x66 prefix). */ | |
acd5c798 | 1152 | delta += 4; |
c906108c SS |
1153 | } |
1154 | else | |
1155 | { | |
e17a4113 | 1156 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1157 | |
acd5c798 MK |
1158 | /* Include the size of the jmp instruction. */ |
1159 | delta += 5; | |
c906108c SS |
1160 | } |
1161 | break; | |
1162 | case 0xeb: | |
fc338970 | 1163 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1164 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1165 | |
acd5c798 | 1166 | delta += data16 + 2; |
c906108c SS |
1167 | break; |
1168 | } | |
c906108c | 1169 | |
acd5c798 MK |
1170 | return pc + delta; |
1171 | } | |
fc338970 | 1172 | |
acd5c798 MK |
1173 | /* Check whether PC points at a prologue for a function returning a |
1174 | structure or union. If so, it updates CACHE and returns the | |
1175 | address of the first instruction after the code sequence that | |
1176 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1177 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1178 | |
acd5c798 MK |
1179 | static CORE_ADDR |
1180 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1181 | struct i386_frame_cache *cache) | |
c906108c | 1182 | { |
acd5c798 MK |
1183 | /* Functions that return a structure or union start with: |
1184 | ||
1185 | popl %eax 0x58 | |
1186 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1187 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1188 | ||
1189 | (the System V compiler puts out the second `xchg' instruction, | |
1190 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1191 | gets generated). This sequence is used to get the address of the | |
1192 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1193 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1194 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1195 | gdb_byte buf[4]; | |
1196 | gdb_byte op; | |
c906108c | 1197 | |
acd5c798 MK |
1198 | if (current_pc <= pc) |
1199 | return pc; | |
1200 | ||
0865b04a | 1201 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1202 | return pc; |
c906108c | 1203 | |
acd5c798 MK |
1204 | if (op != 0x58) /* popl %eax */ |
1205 | return pc; | |
c906108c | 1206 | |
0865b04a | 1207 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1208 | return pc; |
1209 | ||
acd5c798 MK |
1210 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1211 | return pc; | |
c906108c | 1212 | |
acd5c798 | 1213 | if (current_pc == pc) |
c906108c | 1214 | { |
acd5c798 MK |
1215 | cache->sp_offset += 4; |
1216 | return current_pc; | |
c906108c SS |
1217 | } |
1218 | ||
acd5c798 | 1219 | if (current_pc == pc + 1) |
c906108c | 1220 | { |
acd5c798 MK |
1221 | cache->pc_in_eax = 1; |
1222 | return current_pc; | |
1223 | } | |
1224 | ||
1225 | if (buf[1] == proto1[1]) | |
1226 | return pc + 4; | |
1227 | else | |
1228 | return pc + 5; | |
1229 | } | |
1230 | ||
1231 | static CORE_ADDR | |
1232 | i386_skip_probe (CORE_ADDR pc) | |
1233 | { | |
1234 | /* A function may start with | |
fc338970 | 1235 | |
acd5c798 MK |
1236 | pushl constant |
1237 | call _probe | |
1238 | addl $4, %esp | |
fc338970 | 1239 | |
acd5c798 MK |
1240 | followed by |
1241 | ||
1242 | pushl %ebp | |
fc338970 | 1243 | |
acd5c798 | 1244 | etc. */ |
63c0089f MK |
1245 | gdb_byte buf[8]; |
1246 | gdb_byte op; | |
fc338970 | 1247 | |
0865b04a | 1248 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1249 | return pc; |
acd5c798 MK |
1250 | |
1251 | if (op == 0x68 || op == 0x6a) | |
1252 | { | |
1253 | int delta; | |
c906108c | 1254 | |
acd5c798 MK |
1255 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1256 | four-byte operand, depending on the opcode. */ | |
c906108c | 1257 | if (op == 0x68) |
acd5c798 | 1258 | delta = 5; |
c906108c | 1259 | else |
acd5c798 | 1260 | delta = 2; |
c906108c | 1261 | |
acd5c798 MK |
1262 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1263 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1264 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1265 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1266 | pc += delta + sizeof (buf); |
c906108c SS |
1267 | } |
1268 | ||
acd5c798 MK |
1269 | return pc; |
1270 | } | |
1271 | ||
92dd43fa MK |
1272 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1273 | stack pointer. Check whether PC points to such code, and update | |
1274 | CACHE accordingly. Return the first instruction after the code | |
1275 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1276 | recognize the code, return PC. */ | |
1277 | ||
1278 | static CORE_ADDR | |
1279 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1280 | struct i386_frame_cache *cache) | |
1281 | { | |
e0c62198 L |
1282 | /* There are 2 code sequences to re-align stack before the frame |
1283 | gets set up: | |
1284 | ||
1285 | 1. Use a caller-saved saved register: | |
1286 | ||
1287 | leal 4(%esp), %reg | |
1288 | andl $-XXX, %esp | |
1289 | pushl -4(%reg) | |
1290 | ||
1291 | 2. Use a callee-saved saved register: | |
1292 | ||
1293 | pushl %reg | |
1294 | leal 8(%esp), %reg | |
1295 | andl $-XXX, %esp | |
1296 | pushl -4(%reg) | |
1297 | ||
1298 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1299 | ||
1300 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1301 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1302 | */ | |
1303 | ||
1304 | gdb_byte buf[14]; | |
1305 | int reg; | |
1306 | int offset, offset_and; | |
1307 | static int regnums[8] = { | |
1308 | I386_EAX_REGNUM, /* %eax */ | |
1309 | I386_ECX_REGNUM, /* %ecx */ | |
1310 | I386_EDX_REGNUM, /* %edx */ | |
1311 | I386_EBX_REGNUM, /* %ebx */ | |
1312 | I386_ESP_REGNUM, /* %esp */ | |
1313 | I386_EBP_REGNUM, /* %ebp */ | |
1314 | I386_ESI_REGNUM, /* %esi */ | |
1315 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1316 | }; |
92dd43fa | 1317 | |
0865b04a | 1318 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1319 | return pc; |
1320 | ||
1321 | /* Check caller-saved saved register. The first instruction has | |
1322 | to be "leal 4(%esp), %reg". */ | |
1323 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1324 | { | |
1325 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1326 | if ((buf[1] & 0xc7) != 0x44) | |
1327 | return pc; | |
1328 | ||
1329 | /* REG has register number. */ | |
1330 | reg = (buf[1] >> 3) & 7; | |
1331 | offset = 4; | |
1332 | } | |
1333 | else | |
1334 | { | |
1335 | /* Check callee-saved saved register. The first instruction | |
1336 | has to be "pushl %reg". */ | |
1337 | if ((buf[0] & 0xf8) != 0x50) | |
1338 | return pc; | |
1339 | ||
1340 | /* Get register. */ | |
1341 | reg = buf[0] & 0x7; | |
1342 | ||
1343 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1344 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1345 | return pc; | |
1346 | ||
1347 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1348 | if ((buf[2] & 0xc7) != 0x44) | |
1349 | return pc; | |
1350 | ||
1351 | /* REG has register number. Registers in pushl and leal have to | |
1352 | be the same. */ | |
1353 | if (reg != ((buf[2] >> 3) & 7)) | |
1354 | return pc; | |
1355 | ||
1356 | offset = 5; | |
1357 | } | |
1358 | ||
1359 | /* Rigister can't be %esp nor %ebp. */ | |
1360 | if (reg == 4 || reg == 5) | |
1361 | return pc; | |
1362 | ||
1363 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1364 | if (buf[offset + 1] != 0xe4 | |
1365 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1366 | return pc; | |
1367 | ||
1368 | offset_and = offset; | |
1369 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1370 | ||
1371 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1372 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1373 | if (buf[offset] != 0xff | |
1374 | || buf[offset + 2] != 0xfc | |
1375 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1376 | return pc; | |
1377 | ||
1378 | /* R/M has register. Registers in leal and pushl have to be the | |
1379 | same. */ | |
1380 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1381 | return pc; |
1382 | ||
e0c62198 L |
1383 | if (current_pc > pc + offset_and) |
1384 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1385 | |
325fac50 | 1386 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1387 | } |
1388 | ||
37bdc87e | 1389 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1390 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1391 | |
1392 | /* Instruction description. */ | |
1393 | struct i386_insn | |
1394 | { | |
1395 | size_t len; | |
237fc4c9 PA |
1396 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1397 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1398 | }; |
1399 | ||
a3fcb948 | 1400 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1401 | |
a3fcb948 JG |
1402 | static int |
1403 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1404 | { |
63c0089f | 1405 | gdb_byte op; |
37bdc87e | 1406 | |
0865b04a | 1407 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1408 | return 0; |
37bdc87e | 1409 | |
a3fcb948 | 1410 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1411 | { |
a3fcb948 JG |
1412 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1413 | int insn_matched = 1; | |
1414 | size_t i; | |
37bdc87e | 1415 | |
a3fcb948 JG |
1416 | gdb_assert (pattern.len > 1); |
1417 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1418 | |
0865b04a | 1419 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1420 | return 0; |
613e8135 | 1421 | |
a3fcb948 JG |
1422 | for (i = 1; i < pattern.len; i++) |
1423 | { | |
1424 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1425 | insn_matched = 0; | |
37bdc87e | 1426 | } |
a3fcb948 JG |
1427 | return insn_matched; |
1428 | } | |
1429 | return 0; | |
1430 | } | |
1431 | ||
1432 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1433 | the first instruction description that matches. Otherwise, return | |
1434 | NULL. */ | |
1435 | ||
1436 | static struct i386_insn * | |
1437 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1438 | { | |
1439 | struct i386_insn *pattern; | |
1440 | ||
1441 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1442 | { | |
1443 | if (i386_match_pattern (pc, *pattern)) | |
1444 | return pattern; | |
37bdc87e MK |
1445 | } |
1446 | ||
1447 | return NULL; | |
1448 | } | |
1449 | ||
a3fcb948 JG |
1450 | /* Return whether PC points inside a sequence of instructions that |
1451 | matches INSN_PATTERNS. */ | |
1452 | ||
1453 | static int | |
1454 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1455 | { | |
1456 | CORE_ADDR current_pc; | |
1457 | int ix, i; | |
a3fcb948 JG |
1458 | struct i386_insn *insn; |
1459 | ||
1460 | insn = i386_match_insn (pc, insn_patterns); | |
1461 | if (insn == NULL) | |
1462 | return 0; | |
1463 | ||
8bbdd3f4 | 1464 | current_pc = pc; |
a3fcb948 JG |
1465 | ix = insn - insn_patterns; |
1466 | for (i = ix - 1; i >= 0; i--) | |
1467 | { | |
8bbdd3f4 MK |
1468 | current_pc -= insn_patterns[i].len; |
1469 | ||
a3fcb948 JG |
1470 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1471 | return 0; | |
a3fcb948 JG |
1472 | } |
1473 | ||
1474 | current_pc = pc + insn->len; | |
1475 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1476 | { | |
1477 | if (!i386_match_pattern (current_pc, *insn)) | |
1478 | return 0; | |
1479 | ||
1480 | current_pc += insn->len; | |
1481 | } | |
1482 | ||
1483 | return 1; | |
1484 | } | |
1485 | ||
37bdc87e MK |
1486 | /* Some special instructions that might be migrated by GCC into the |
1487 | part of the prologue that sets up the new stack frame. Because the | |
1488 | stack frame hasn't been setup yet, no registers have been saved | |
1489 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1490 | touched. */ | |
1491 | ||
1492 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1493 | { | |
1777feb0 | 1494 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1495 | |
1496 | ??? Should we handle 16-bit operand-sizes here? */ | |
1497 | ||
1498 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1499 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1500 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1501 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1502 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1503 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1504 | { 5, { 0xb8 }, { 0xfe } }, | |
1505 | /* `movl imm32, %edx' */ | |
1506 | { 5, { 0xba }, { 0xff } }, | |
1507 | ||
1508 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1509 | encoding for `mov m32, %eax'. | |
1510 | ||
1511 | ??? Should we handle SIB adressing here? | |
1512 | ??? Should we handle 16-bit operand-sizes here? */ | |
1513 | ||
1514 | /* `movl m32, %eax' */ | |
1515 | { 5, { 0xa1 }, { 0xff } }, | |
1516 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1517 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1518 | /* `movl m32, %edx' */ | |
1519 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1520 | ||
1521 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1522 | Because of the symmetry, there are actually two ways to encode | |
1523 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1524 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1525 | ||
1526 | /* `subl %eax, %eax' */ | |
1527 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1528 | /* `subl %ecx, %ecx' */ | |
1529 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1530 | /* `subl %edx, %edx' */ | |
1531 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1532 | /* `xorl %eax, %eax' */ | |
1533 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1534 | /* `xorl %ecx, %ecx' */ | |
1535 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1536 | /* `xorl %edx, %edx' */ | |
1537 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1538 | { 0 } | |
1539 | }; | |
1540 | ||
e11481da PM |
1541 | |
1542 | /* Check whether PC points to a no-op instruction. */ | |
1543 | static CORE_ADDR | |
1544 | i386_skip_noop (CORE_ADDR pc) | |
1545 | { | |
1546 | gdb_byte op; | |
1547 | int check = 1; | |
1548 | ||
0865b04a | 1549 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1550 | return pc; |
e11481da PM |
1551 | |
1552 | while (check) | |
1553 | { | |
1554 | check = 0; | |
1555 | /* Ignore `nop' instruction. */ | |
1556 | if (op == 0x90) | |
1557 | { | |
1558 | pc += 1; | |
0865b04a | 1559 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1560 | return pc; |
e11481da PM |
1561 | check = 1; |
1562 | } | |
1563 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1564 | Microsoft system dlls often start with | |
1565 | a `mov %edi,%edi' instruction. | |
1566 | The 5 bytes before the function start are | |
1567 | filled with `nop' instructions. | |
1568 | This pattern can be used for hot-patching: | |
1569 | The `mov %edi, %edi' instruction can be replaced by a | |
1570 | near jump to the location of the 5 `nop' instructions | |
1571 | which can be replaced by a 32-bit jump to anywhere | |
1572 | in the 32-bit address space. */ | |
1573 | ||
1574 | else if (op == 0x8b) | |
1575 | { | |
0865b04a | 1576 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1577 | return pc; |
1578 | ||
e11481da PM |
1579 | if (op == 0xff) |
1580 | { | |
1581 | pc += 2; | |
0865b04a | 1582 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1583 | return pc; |
1584 | ||
e11481da PM |
1585 | check = 1; |
1586 | } | |
1587 | } | |
1588 | } | |
1589 | return pc; | |
1590 | } | |
1591 | ||
acd5c798 MK |
1592 | /* Check whether PC points at a code that sets up a new stack frame. |
1593 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1594 | instruction after the sequence that sets up the frame or LIMIT, |
1595 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1596 | |
1597 | static CORE_ADDR | |
e17a4113 UW |
1598 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1599 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1600 | struct i386_frame_cache *cache) |
1601 | { | |
e17a4113 | 1602 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1603 | struct i386_insn *insn; |
63c0089f | 1604 | gdb_byte op; |
26604a34 | 1605 | int skip = 0; |
acd5c798 | 1606 | |
37bdc87e MK |
1607 | if (limit <= pc) |
1608 | return limit; | |
acd5c798 | 1609 | |
0865b04a | 1610 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1611 | return pc; |
acd5c798 | 1612 | |
c906108c | 1613 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1614 | { |
acd5c798 MK |
1615 | /* Take into account that we've executed the `pushl %ebp' that |
1616 | starts this instruction sequence. */ | |
fd13a04a | 1617 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1618 | cache->sp_offset += 4; |
37bdc87e | 1619 | pc++; |
acd5c798 MK |
1620 | |
1621 | /* If that's all, return now. */ | |
37bdc87e MK |
1622 | if (limit <= pc) |
1623 | return limit; | |
26604a34 | 1624 | |
b4632131 | 1625 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1626 | GCC into the prologue and skip them. At this point in the |
1627 | prologue, code should only touch the scratch registers %eax, | |
1628 | %ecx and %edx, so while the number of posibilities is sheer, | |
1629 | it is limited. | |
5daa5b4e | 1630 | |
26604a34 MK |
1631 | Make sure we only skip these instructions if we later see the |
1632 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1633 | while (pc + skip < limit) |
26604a34 | 1634 | { |
37bdc87e MK |
1635 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1636 | if (insn == NULL) | |
1637 | break; | |
b4632131 | 1638 | |
37bdc87e | 1639 | skip += insn->len; |
26604a34 MK |
1640 | } |
1641 | ||
37bdc87e MK |
1642 | /* If that's all, return now. */ |
1643 | if (limit <= pc + skip) | |
1644 | return limit; | |
1645 | ||
0865b04a | 1646 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1647 | return pc + skip; |
37bdc87e | 1648 | |
30f8135b YQ |
1649 | /* The i386 prologue looks like |
1650 | ||
1651 | push %ebp | |
1652 | mov %esp,%ebp | |
1653 | sub $0x10,%esp | |
1654 | ||
1655 | and a different prologue can be generated for atom. | |
1656 | ||
1657 | push %ebp | |
1658 | lea (%esp),%ebp | |
1659 | lea -0x10(%esp),%esp | |
1660 | ||
1661 | We handle both of them here. */ | |
1662 | ||
acd5c798 | 1663 | switch (op) |
c906108c | 1664 | { |
30f8135b | 1665 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1666 | case 0x8b: |
0865b04a | 1667 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1668 | != 0xec) |
37bdc87e | 1669 | return pc; |
30f8135b | 1670 | pc += (skip + 2); |
c906108c SS |
1671 | break; |
1672 | case 0x89: | |
0865b04a | 1673 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1674 | != 0xe5) |
37bdc87e | 1675 | return pc; |
30f8135b YQ |
1676 | pc += (skip + 2); |
1677 | break; | |
1678 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1679 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1680 | != 0x242c) |
1681 | return pc; | |
1682 | pc += (skip + 3); | |
c906108c SS |
1683 | break; |
1684 | default: | |
37bdc87e | 1685 | return pc; |
c906108c | 1686 | } |
acd5c798 | 1687 | |
26604a34 MK |
1688 | /* OK, we actually have a frame. We just don't know how large |
1689 | it is yet. Set its size to zero. We'll adjust it if | |
1690 | necessary. We also now commit to skipping the special | |
1691 | instructions mentioned before. */ | |
acd5c798 MK |
1692 | cache->locals = 0; |
1693 | ||
1694 | /* If that's all, return now. */ | |
37bdc87e MK |
1695 | if (limit <= pc) |
1696 | return limit; | |
acd5c798 | 1697 | |
fc338970 MK |
1698 | /* Check for stack adjustment |
1699 | ||
acd5c798 | 1700 | subl $XXX, %esp |
30f8135b YQ |
1701 | or |
1702 | lea -XXX(%esp),%esp | |
fc338970 | 1703 | |
fd35795f | 1704 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1705 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1706 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1707 | return pc; |
c906108c SS |
1708 | if (op == 0x83) |
1709 | { | |
fd35795f | 1710 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1711 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1712 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1713 | return pc; |
acd5c798 | 1714 | |
37bdc87e MK |
1715 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1716 | make sense to be negative). */ | |
0865b04a | 1717 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1718 | return pc + 3; |
c906108c SS |
1719 | } |
1720 | else if (op == 0x81) | |
1721 | { | |
fd35795f | 1722 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1723 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1724 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1725 | return pc; |
acd5c798 | 1726 | |
fd35795f | 1727 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1728 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1729 | return pc + 6; |
c906108c | 1730 | } |
30f8135b YQ |
1731 | else if (op == 0x8d) |
1732 | { | |
1733 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1734 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1735 | return pc; |
1736 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1737 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1738 | return pc + 4; |
1739 | } | |
c906108c SS |
1740 | else |
1741 | { | |
30f8135b | 1742 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1743 | return pc; |
c906108c SS |
1744 | } |
1745 | } | |
37bdc87e | 1746 | else if (op == 0xc8) /* enter */ |
c906108c | 1747 | { |
0865b04a | 1748 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1749 | return pc + 4; |
c906108c | 1750 | } |
21d0e8a4 | 1751 | |
acd5c798 | 1752 | return pc; |
21d0e8a4 MK |
1753 | } |
1754 | ||
acd5c798 MK |
1755 | /* Check whether PC points at code that saves registers on the stack. |
1756 | If so, it updates CACHE and returns the address of the first | |
1757 | instruction after the register saves or CURRENT_PC, whichever is | |
1758 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1759 | |
1760 | static CORE_ADDR | |
acd5c798 MK |
1761 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1762 | struct i386_frame_cache *cache) | |
6bff26de | 1763 | { |
99ab4326 | 1764 | CORE_ADDR offset = 0; |
63c0089f | 1765 | gdb_byte op; |
99ab4326 | 1766 | int i; |
c0d1d883 | 1767 | |
99ab4326 MK |
1768 | if (cache->locals > 0) |
1769 | offset -= cache->locals; | |
1770 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1771 | { | |
0865b04a | 1772 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1773 | return pc; |
99ab4326 MK |
1774 | if (op < 0x50 || op > 0x57) |
1775 | break; | |
0d17c81d | 1776 | |
99ab4326 MK |
1777 | offset -= 4; |
1778 | cache->saved_regs[op - 0x50] = offset; | |
1779 | cache->sp_offset += 4; | |
1780 | pc++; | |
6bff26de MK |
1781 | } |
1782 | ||
acd5c798 | 1783 | return pc; |
22797942 AC |
1784 | } |
1785 | ||
acd5c798 MK |
1786 | /* Do a full analysis of the prologue at PC and update CACHE |
1787 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1788 | address where the analysis stopped. | |
ed84f6c1 | 1789 | |
fc338970 MK |
1790 | We handle these cases: |
1791 | ||
1792 | The startup sequence can be at the start of the function, or the | |
1793 | function can start with a branch to startup code at the end. | |
1794 | ||
1795 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1796 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1797 | once used in the System V compiler). | |
1798 | ||
1799 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1800 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1801 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1802 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1803 | |
1804 | Next, the registers used by this function are pushed. With the | |
1805 | System V compiler they will always be in the order: %edi, %esi, | |
1806 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1807 | restore %eax); however, the code below is willing to see the pushes | |
1808 | in any order, and will handle up to 8 of them. | |
1809 | ||
1810 | If the setup sequence is at the end of the function, then the next | |
1811 | instruction will be a branch back to the start. */ | |
c906108c | 1812 | |
acd5c798 | 1813 | static CORE_ADDR |
e17a4113 UW |
1814 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1815 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1816 | struct i386_frame_cache *cache) |
c906108c | 1817 | { |
e11481da | 1818 | pc = i386_skip_noop (pc); |
e17a4113 | 1819 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1820 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1821 | pc = i386_skip_probe (pc); | |
92dd43fa | 1822 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1823 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1824 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1825 | } |
1826 | ||
fc338970 | 1827 | /* Return PC of first real instruction. */ |
c906108c | 1828 | |
3a1e71e3 | 1829 | static CORE_ADDR |
6093d2eb | 1830 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1831 | { |
e17a4113 UW |
1832 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1833 | ||
63c0089f | 1834 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1835 | { |
1836 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1837 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1838 | }; |
acd5c798 MK |
1839 | struct i386_frame_cache cache; |
1840 | CORE_ADDR pc; | |
63c0089f | 1841 | gdb_byte op; |
acd5c798 | 1842 | int i; |
56bf0743 | 1843 | CORE_ADDR func_addr; |
4e879fc2 | 1844 | |
56bf0743 KB |
1845 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1846 | { | |
1847 | CORE_ADDR post_prologue_pc | |
1848 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1849 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
1850 | |
1851 | /* Clang always emits a line note before the prologue and another | |
1852 | one after. We trust clang to emit usable line notes. */ | |
1853 | if (post_prologue_pc | |
43f3e411 DE |
1854 | && (cust != NULL |
1855 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 1856 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
325fac50 | 1857 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1858 | } |
1859 | ||
e0f33b1f | 1860 | cache.locals = -1; |
e17a4113 | 1861 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1862 | if (cache.locals < 0) |
1863 | return start_pc; | |
c5aa993b | 1864 | |
acd5c798 | 1865 | /* Found valid frame setup. */ |
c906108c | 1866 | |
fc338970 MK |
1867 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1868 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1869 | %ebx: |
1870 | ||
fc338970 MK |
1871 | call 0x0 |
1872 | popl %ebx | |
1873 | movl %ebx,x(%ebp) (optional) | |
1874 | addl y,%ebx | |
1875 | ||
c906108c SS |
1876 | This code is with the rest of the prologue (at the end of the |
1877 | function), so we have to skip it to get to the first real | |
1878 | instruction at the start of the function. */ | |
c5aa993b | 1879 | |
c906108c SS |
1880 | for (i = 0; i < 6; i++) |
1881 | { | |
0865b04a | 1882 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1883 | return pc; |
1884 | ||
c5aa993b | 1885 | if (pic_pat[i] != op) |
c906108c SS |
1886 | break; |
1887 | } | |
1888 | if (i == 6) | |
1889 | { | |
acd5c798 MK |
1890 | int delta = 6; |
1891 | ||
0865b04a | 1892 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1893 | return pc; |
c906108c | 1894 | |
c5aa993b | 1895 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1896 | { |
0865b04a | 1897 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1898 | |
fc338970 | 1899 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1900 | delta += 3; |
fc338970 | 1901 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1902 | delta += 6; |
fc338970 | 1903 | else /* Unexpected instruction. */ |
acd5c798 MK |
1904 | delta = 0; |
1905 | ||
0865b04a | 1906 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1907 | return pc; |
c906108c | 1908 | } |
acd5c798 | 1909 | |
c5aa993b | 1910 | /* addl y,%ebx */ |
acd5c798 | 1911 | if (delta > 0 && op == 0x81 |
0865b04a | 1912 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1913 | == 0xc3) |
c906108c | 1914 | { |
acd5c798 | 1915 | pc += delta + 6; |
c906108c SS |
1916 | } |
1917 | } | |
c5aa993b | 1918 | |
e63bbc88 MK |
1919 | /* If the function starts with a branch (to startup code at the end) |
1920 | the last instruction should bring us back to the first | |
1921 | instruction of the real code. */ | |
e17a4113 UW |
1922 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1923 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1924 | |
1925 | return pc; | |
c906108c SS |
1926 | } |
1927 | ||
4309257c PM |
1928 | /* Check that the code pointed to by PC corresponds to a call to |
1929 | __main, skip it if so. Return PC otherwise. */ | |
1930 | ||
1931 | CORE_ADDR | |
1932 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1933 | { | |
e17a4113 | 1934 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1935 | gdb_byte op; |
1936 | ||
0865b04a | 1937 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1938 | return pc; |
4309257c PM |
1939 | if (op == 0xe8) |
1940 | { | |
1941 | gdb_byte buf[4]; | |
1942 | ||
0865b04a | 1943 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1944 | { |
1945 | /* Make sure address is computed correctly as a 32bit | |
1946 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1947 | struct bound_minimal_symbol s; |
e17a4113 | 1948 | CORE_ADDR call_dest; |
4309257c | 1949 | |
e17a4113 | 1950 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1951 | call_dest = call_dest & 0xffffffffU; |
1952 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1953 | if (s.minsym != NULL |
efd66ac6 TT |
1954 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1955 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1956 | pc += 5; |
1957 | } | |
1958 | } | |
1959 | ||
1960 | return pc; | |
1961 | } | |
1962 | ||
acd5c798 | 1963 | /* This function is 64-bit safe. */ |
93924b6b | 1964 | |
acd5c798 MK |
1965 | static CORE_ADDR |
1966 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1967 | { |
63c0089f | 1968 | gdb_byte buf[8]; |
acd5c798 | 1969 | |
875f8d0e | 1970 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1971 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1972 | } |
acd5c798 | 1973 | \f |
93924b6b | 1974 | |
acd5c798 | 1975 | /* Normal frames. */ |
c5aa993b | 1976 | |
8fbca658 PA |
1977 | static void |
1978 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1979 | struct i386_frame_cache *cache) | |
a7769679 | 1980 | { |
e17a4113 UW |
1981 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1982 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1983 | gdb_byte buf[4]; |
acd5c798 MK |
1984 | int i; |
1985 | ||
8fbca658 | 1986 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1987 | |
1988 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1989 | which holds the base address for the current stack frame. | |
1990 | However, for functions that don't need it, the frame pointer is | |
1991 | optional. For these "frameless" functions the frame pointer is | |
1992 | actually the frame pointer of the calling frame. Signal | |
1993 | trampolines are just a special case of a "frameless" function. | |
1994 | They (usually) share their frame pointer with the frame that was | |
1995 | in progress when the signal occurred. */ | |
1996 | ||
10458914 | 1997 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1998 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1999 | if (cache->base == 0) |
620fa63a PA |
2000 | { |
2001 | cache->base_p = 1; | |
2002 | return; | |
2003 | } | |
acd5c798 MK |
2004 | |
2005 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 2006 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2007 | |
acd5c798 | 2008 | if (cache->pc != 0) |
e17a4113 UW |
2009 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2010 | cache); | |
acd5c798 MK |
2011 | |
2012 | if (cache->locals < 0) | |
2013 | { | |
2014 | /* We didn't find a valid frame, which means that CACHE->base | |
2015 | currently holds the frame pointer for our calling frame. If | |
2016 | we're at the start of a function, or somewhere half-way its | |
2017 | prologue, the function's frame probably hasn't been fully | |
2018 | setup yet. Try to reconstruct the base address for the stack | |
2019 | frame by looking at the stack pointer. For truly "frameless" | |
2020 | functions this might work too. */ | |
2021 | ||
e0c62198 | 2022 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2023 | { |
8fbca658 PA |
2024 | /* Saved stack pointer has been saved. */ |
2025 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2026 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2027 | ||
92dd43fa MK |
2028 | /* We're halfway aligning the stack. */ |
2029 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2030 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2031 | ||
2032 | /* This will be added back below. */ | |
2033 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2034 | } | |
7618e12b | 2035 | else if (cache->pc != 0 |
0865b04a | 2036 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2037 | { |
7618e12b DJ |
2038 | /* We're in a known function, but did not find a frame |
2039 | setup. Assume that the function does not use %ebp. | |
2040 | Alternatively, we may have jumped to an invalid | |
2041 | address; in that case there is definitely no new | |
2042 | frame in %ebp. */ | |
10458914 | 2043 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2044 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2045 | + cache->sp_offset; | |
92dd43fa | 2046 | } |
7618e12b DJ |
2047 | else |
2048 | /* We're in an unknown function. We could not find the start | |
2049 | of the function to analyze the prologue; our best option is | |
2050 | to assume a typical frame layout with the caller's %ebp | |
2051 | saved. */ | |
2052 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2053 | } |
2054 | ||
8fbca658 PA |
2055 | if (cache->saved_sp_reg != -1) |
2056 | { | |
2057 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2058 | register may be unavailable). */ | |
2059 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2060 | && deprecated_frame_register_read (this_frame, |
2061 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2062 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2063 | } | |
acd5c798 MK |
2064 | /* Now that we have the base address for the stack frame we can |
2065 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2066 | else if (cache->saved_sp == 0) |
92dd43fa | 2067 | cache->saved_sp = cache->base + 8; |
a7769679 | 2068 | |
acd5c798 MK |
2069 | /* Adjust all the saved registers such that they contain addresses |
2070 | instead of offsets. */ | |
2071 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2072 | if (cache->saved_regs[i] != -1) |
2073 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2074 | |
8fbca658 PA |
2075 | cache->base_p = 1; |
2076 | } | |
2077 | ||
2078 | static struct i386_frame_cache * | |
2079 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2080 | { | |
8fbca658 PA |
2081 | struct i386_frame_cache *cache; |
2082 | ||
2083 | if (*this_cache) | |
9a3c8263 | 2084 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2085 | |
2086 | cache = i386_alloc_frame_cache (); | |
2087 | *this_cache = cache; | |
2088 | ||
492d29ea | 2089 | TRY |
8fbca658 PA |
2090 | { |
2091 | i386_frame_cache_1 (this_frame, cache); | |
2092 | } | |
492d29ea | 2093 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2094 | { |
2095 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2096 | throw_exception (ex); | |
2097 | } | |
492d29ea | 2098 | END_CATCH |
8fbca658 | 2099 | |
acd5c798 | 2100 | return cache; |
a7769679 MK |
2101 | } |
2102 | ||
3a1e71e3 | 2103 | static void |
10458914 | 2104 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2105 | struct frame_id *this_id) |
c906108c | 2106 | { |
10458914 | 2107 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2108 | |
5ce0145d PA |
2109 | if (!cache->base_p) |
2110 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2111 | else if (cache->base == 0) | |
2112 | { | |
2113 | /* This marks the outermost frame. */ | |
2114 | } | |
2115 | else | |
2116 | { | |
2117 | /* See the end of i386_push_dummy_call. */ | |
2118 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2119 | } | |
acd5c798 MK |
2120 | } |
2121 | ||
8fbca658 PA |
2122 | static enum unwind_stop_reason |
2123 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2124 | void **this_cache) | |
2125 | { | |
2126 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2127 | ||
2128 | if (!cache->base_p) | |
2129 | return UNWIND_UNAVAILABLE; | |
2130 | ||
2131 | /* This marks the outermost frame. */ | |
2132 | if (cache->base == 0) | |
2133 | return UNWIND_OUTERMOST; | |
2134 | ||
2135 | return UNWIND_NO_REASON; | |
2136 | } | |
2137 | ||
10458914 DJ |
2138 | static struct value * |
2139 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2140 | int regnum) | |
acd5c798 | 2141 | { |
10458914 | 2142 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2143 | |
2144 | gdb_assert (regnum >= 0); | |
2145 | ||
2146 | /* The System V ABI says that: | |
2147 | ||
2148 | "The flags register contains the system flags, such as the | |
2149 | direction flag and the carry flag. The direction flag must be | |
2150 | set to the forward (that is, zero) direction before entry and | |
2151 | upon exit from a function. Other user flags have no specified | |
2152 | role in the standard calling sequence and are not preserved." | |
2153 | ||
2154 | To guarantee the "upon exit" part of that statement we fake a | |
2155 | saved flags register that has its direction flag cleared. | |
2156 | ||
2157 | Note that GCC doesn't seem to rely on the fact that the direction | |
2158 | flag is cleared after a function return; it always explicitly | |
2159 | clears the flag before operations where it matters. | |
2160 | ||
2161 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2162 | right thing to do. The way we fake the flags register here makes | |
2163 | it impossible to change it. */ | |
2164 | ||
2165 | if (regnum == I386_EFLAGS_REGNUM) | |
2166 | { | |
10458914 | 2167 | ULONGEST val; |
c5aa993b | 2168 | |
10458914 DJ |
2169 | val = get_frame_register_unsigned (this_frame, regnum); |
2170 | val &= ~(1 << 10); | |
2171 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2172 | } |
1211c4e4 | 2173 | |
acd5c798 | 2174 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2175 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2176 | |
fcf250e2 UW |
2177 | if (regnum == I386_ESP_REGNUM |
2178 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2179 | { |
2180 | /* If the SP has been saved, but we don't know where, then this | |
2181 | means that SAVED_SP_REG register was found unavailable back | |
2182 | when we built the cache. */ | |
fcf250e2 | 2183 | if (cache->saved_sp == 0) |
8fbca658 PA |
2184 | return frame_unwind_got_register (this_frame, regnum, |
2185 | cache->saved_sp_reg); | |
2186 | else | |
2187 | return frame_unwind_got_constant (this_frame, regnum, | |
2188 | cache->saved_sp); | |
2189 | } | |
acd5c798 | 2190 | |
fd13a04a | 2191 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2192 | return frame_unwind_got_memory (this_frame, regnum, |
2193 | cache->saved_regs[regnum]); | |
fd13a04a | 2194 | |
10458914 | 2195 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2196 | } |
2197 | ||
2198 | static const struct frame_unwind i386_frame_unwind = | |
2199 | { | |
2200 | NORMAL_FRAME, | |
8fbca658 | 2201 | i386_frame_unwind_stop_reason, |
acd5c798 | 2202 | i386_frame_this_id, |
10458914 DJ |
2203 | i386_frame_prev_register, |
2204 | NULL, | |
2205 | default_frame_sniffer | |
acd5c798 | 2206 | }; |
06da04c6 MS |
2207 | |
2208 | /* Normal frames, but in a function epilogue. */ | |
2209 | ||
c9cf6e20 MG |
2210 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2211 | ||
2212 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2213 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2214 | the function's stack frame. */ | |
2215 | ||
2216 | static int | |
c9cf6e20 | 2217 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2218 | { |
2219 | gdb_byte insn; | |
43f3e411 | 2220 | struct compunit_symtab *cust; |
e0d00bc7 | 2221 | |
43f3e411 DE |
2222 | cust = find_pc_compunit_symtab (pc); |
2223 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2224 | return 0; |
06da04c6 MS |
2225 | |
2226 | if (target_read_memory (pc, &insn, 1)) | |
2227 | return 0; /* Can't read memory at pc. */ | |
2228 | ||
2229 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2230 | return 0; | |
2231 | ||
2232 | return 1; | |
2233 | } | |
2234 | ||
2235 | static int | |
2236 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2237 | struct frame_info *this_frame, | |
2238 | void **this_prologue_cache) | |
2239 | { | |
2240 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2241 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2242 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2243 | else |
2244 | return 0; | |
2245 | } | |
2246 | ||
2247 | static struct i386_frame_cache * | |
2248 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2249 | { | |
06da04c6 | 2250 | struct i386_frame_cache *cache; |
0d6c2135 | 2251 | CORE_ADDR sp; |
06da04c6 MS |
2252 | |
2253 | if (*this_cache) | |
9a3c8263 | 2254 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2255 | |
2256 | cache = i386_alloc_frame_cache (); | |
2257 | *this_cache = cache; | |
2258 | ||
492d29ea | 2259 | TRY |
8fbca658 | 2260 | { |
0d6c2135 | 2261 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2262 | |
0d6c2135 MK |
2263 | /* At this point the stack looks as if we just entered the |
2264 | function, with the return address at the top of the | |
2265 | stack. */ | |
2266 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2267 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2268 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2269 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2270 | |
8fbca658 PA |
2271 | cache->base_p = 1; |
2272 | } | |
492d29ea | 2273 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2274 | { |
2275 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2276 | throw_exception (ex); | |
2277 | } | |
492d29ea | 2278 | END_CATCH |
06da04c6 MS |
2279 | |
2280 | return cache; | |
2281 | } | |
2282 | ||
8fbca658 PA |
2283 | static enum unwind_stop_reason |
2284 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2285 | void **this_cache) | |
2286 | { | |
0d6c2135 MK |
2287 | struct i386_frame_cache *cache = |
2288 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2289 | |
2290 | if (!cache->base_p) | |
2291 | return UNWIND_UNAVAILABLE; | |
2292 | ||
2293 | return UNWIND_NO_REASON; | |
2294 | } | |
2295 | ||
06da04c6 MS |
2296 | static void |
2297 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2298 | void **this_cache, | |
2299 | struct frame_id *this_id) | |
2300 | { | |
0d6c2135 MK |
2301 | struct i386_frame_cache *cache = |
2302 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2303 | |
8fbca658 | 2304 | if (!cache->base_p) |
5ce0145d PA |
2305 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2306 | else | |
2307 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2308 | } |
2309 | ||
0d6c2135 MK |
2310 | static struct value * |
2311 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2312 | void **this_cache, int regnum) | |
2313 | { | |
2314 | /* Make sure we've initialized the cache. */ | |
2315 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2316 | ||
2317 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2318 | } | |
2319 | ||
06da04c6 MS |
2320 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2321 | { | |
2322 | NORMAL_FRAME, | |
8fbca658 | 2323 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2324 | i386_epilogue_frame_this_id, |
0d6c2135 | 2325 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2326 | NULL, |
2327 | i386_epilogue_frame_sniffer | |
2328 | }; | |
acd5c798 MK |
2329 | \f |
2330 | ||
a3fcb948 JG |
2331 | /* Stack-based trampolines. */ |
2332 | ||
2333 | /* These trampolines are used on cross x86 targets, when taking the | |
2334 | address of a nested function. When executing these trampolines, | |
2335 | no stack frame is set up, so we are in a similar situation as in | |
2336 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2337 | ||
2338 | /* Static chain passed in register. */ | |
2339 | ||
2340 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2341 | { | |
2342 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2343 | { 5, { 0xb8 }, { 0xfe } }, | |
2344 | ||
2345 | /* `jmp imm32' */ | |
2346 | { 5, { 0xe9 }, { 0xff } }, | |
2347 | ||
2348 | {0} | |
2349 | }; | |
2350 | ||
2351 | /* Static chain passed on stack (when regparm=3). */ | |
2352 | ||
2353 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2354 | { | |
2355 | /* `push imm32' */ | |
2356 | { 5, { 0x68 }, { 0xff } }, | |
2357 | ||
2358 | /* `jmp imm32' */ | |
2359 | { 5, { 0xe9 }, { 0xff } }, | |
2360 | ||
2361 | {0} | |
2362 | }; | |
2363 | ||
2364 | /* Return whether PC points inside a stack trampoline. */ | |
2365 | ||
2366 | static int | |
6df81a63 | 2367 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2368 | { |
2369 | gdb_byte insn; | |
2c02bd72 | 2370 | const char *name; |
a3fcb948 JG |
2371 | |
2372 | /* A stack trampoline is detected if no name is associated | |
2373 | to the current pc and if it points inside a trampoline | |
2374 | sequence. */ | |
2375 | ||
2376 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2377 | if (name) | |
2378 | return 0; | |
2379 | ||
2380 | if (target_read_memory (pc, &insn, 1)) | |
2381 | return 0; | |
2382 | ||
2383 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2384 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2385 | return 0; | |
2386 | ||
2387 | return 1; | |
2388 | } | |
2389 | ||
2390 | static int | |
2391 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2392 | struct frame_info *this_frame, |
2393 | void **this_cache) | |
a3fcb948 JG |
2394 | { |
2395 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2396 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2397 | else |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2402 | { | |
2403 | NORMAL_FRAME, | |
2404 | i386_epilogue_frame_unwind_stop_reason, | |
2405 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2406 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2407 | NULL, |
2408 | i386_stack_tramp_frame_sniffer | |
2409 | }; | |
2410 | \f | |
6710bf39 SS |
2411 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2412 | ||
2413 | static void | |
2414 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2415 | struct agent_expr *ax, struct axs_value *value, | |
2416 | CORE_ADDR scope) | |
2417 | { | |
2418 | /* The following sequence assumes the traditional use of the base | |
2419 | register. */ | |
2420 | ax_reg (ax, I386_EBP_REGNUM); | |
2421 | ax_const_l (ax, 4); | |
2422 | ax_simple (ax, aop_add); | |
2423 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2424 | value->kind = axs_lvalue_memory; | |
2425 | } | |
2426 | \f | |
a3fcb948 | 2427 | |
acd5c798 MK |
2428 | /* Signal trampolines. */ |
2429 | ||
2430 | static struct i386_frame_cache * | |
10458914 | 2431 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2432 | { |
e17a4113 UW |
2433 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2434 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2435 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2436 | struct i386_frame_cache *cache; |
acd5c798 | 2437 | CORE_ADDR addr; |
63c0089f | 2438 | gdb_byte buf[4]; |
acd5c798 MK |
2439 | |
2440 | if (*this_cache) | |
9a3c8263 | 2441 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2442 | |
fd13a04a | 2443 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2444 | |
492d29ea | 2445 | TRY |
a3386186 | 2446 | { |
8fbca658 PA |
2447 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2448 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2449 | |
8fbca658 PA |
2450 | addr = tdep->sigcontext_addr (this_frame); |
2451 | if (tdep->sc_reg_offset) | |
2452 | { | |
2453 | int i; | |
a3386186 | 2454 | |
8fbca658 PA |
2455 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2456 | ||
2457 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2458 | if (tdep->sc_reg_offset[i] != -1) | |
2459 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2460 | } | |
2461 | else | |
2462 | { | |
2463 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2464 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2465 | } | |
2466 | ||
2467 | cache->base_p = 1; | |
a3386186 | 2468 | } |
492d29ea | 2469 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2470 | { |
2471 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2472 | throw_exception (ex); | |
2473 | } | |
492d29ea | 2474 | END_CATCH |
acd5c798 MK |
2475 | |
2476 | *this_cache = cache; | |
2477 | return cache; | |
2478 | } | |
2479 | ||
8fbca658 PA |
2480 | static enum unwind_stop_reason |
2481 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2482 | void **this_cache) | |
2483 | { | |
2484 | struct i386_frame_cache *cache = | |
2485 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2486 | ||
2487 | if (!cache->base_p) | |
2488 | return UNWIND_UNAVAILABLE; | |
2489 | ||
2490 | return UNWIND_NO_REASON; | |
2491 | } | |
2492 | ||
acd5c798 | 2493 | static void |
10458914 | 2494 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2495 | struct frame_id *this_id) |
2496 | { | |
2497 | struct i386_frame_cache *cache = | |
10458914 | 2498 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2499 | |
8fbca658 | 2500 | if (!cache->base_p) |
5ce0145d PA |
2501 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2502 | else | |
2503 | { | |
2504 | /* See the end of i386_push_dummy_call. */ | |
2505 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2506 | } | |
acd5c798 MK |
2507 | } |
2508 | ||
10458914 DJ |
2509 | static struct value * |
2510 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2511 | void **this_cache, int regnum) | |
acd5c798 MK |
2512 | { |
2513 | /* Make sure we've initialized the cache. */ | |
10458914 | 2514 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2515 | |
10458914 | 2516 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2517 | } |
c0d1d883 | 2518 | |
10458914 DJ |
2519 | static int |
2520 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2521 | struct frame_info *this_frame, | |
2522 | void **this_prologue_cache) | |
acd5c798 | 2523 | { |
10458914 | 2524 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2525 | |
911bc6ee MK |
2526 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2527 | handler. */ | |
2528 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2529 | return 0; |
1c3545ae | 2530 | |
911bc6ee MK |
2531 | if (tdep->sigtramp_p != NULL) |
2532 | { | |
10458914 DJ |
2533 | if (tdep->sigtramp_p (this_frame)) |
2534 | return 1; | |
911bc6ee MK |
2535 | } |
2536 | ||
2537 | if (tdep->sigtramp_start != 0) | |
2538 | { | |
10458914 | 2539 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2540 | |
2541 | gdb_assert (tdep->sigtramp_end != 0); | |
2542 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2543 | return 1; |
911bc6ee | 2544 | } |
acd5c798 | 2545 | |
10458914 | 2546 | return 0; |
acd5c798 | 2547 | } |
10458914 DJ |
2548 | |
2549 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2550 | { | |
2551 | SIGTRAMP_FRAME, | |
8fbca658 | 2552 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2553 | i386_sigtramp_frame_this_id, |
2554 | i386_sigtramp_frame_prev_register, | |
2555 | NULL, | |
2556 | i386_sigtramp_frame_sniffer | |
2557 | }; | |
acd5c798 MK |
2558 | \f |
2559 | ||
2560 | static CORE_ADDR | |
10458914 | 2561 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2562 | { |
10458914 | 2563 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2564 | |
2565 | return cache->base; | |
2566 | } | |
2567 | ||
2568 | static const struct frame_base i386_frame_base = | |
2569 | { | |
2570 | &i386_frame_unwind, | |
2571 | i386_frame_base_address, | |
2572 | i386_frame_base_address, | |
2573 | i386_frame_base_address | |
2574 | }; | |
2575 | ||
acd5c798 | 2576 | static struct frame_id |
10458914 | 2577 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2578 | { |
acd5c798 MK |
2579 | CORE_ADDR fp; |
2580 | ||
10458914 | 2581 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2582 | |
3e210248 | 2583 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2584 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2585 | } |
e04e5beb JM |
2586 | |
2587 | /* _Decimal128 function return values need 16-byte alignment on the | |
2588 | stack. */ | |
2589 | ||
2590 | static CORE_ADDR | |
2591 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2592 | { | |
2593 | return sp & -(CORE_ADDR)16; | |
2594 | } | |
fc338970 | 2595 | \f |
c906108c | 2596 | |
fc338970 MK |
2597 | /* Figure out where the longjmp will land. Slurp the args out of the |
2598 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2599 | structure from which we extract the address that we will land at. |
28bcfd30 | 2600 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2601 | success. */ |
c906108c | 2602 | |
8201327c | 2603 | static int |
60ade65d | 2604 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2605 | { |
436675d3 | 2606 | gdb_byte buf[4]; |
c906108c | 2607 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2608 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2609 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2610 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2611 | |
8201327c MK |
2612 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2613 | longjmp will land. */ | |
2614 | if (jb_pc_offset == -1) | |
c906108c SS |
2615 | return 0; |
2616 | ||
436675d3 | 2617 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2618 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2619 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2620 | return 0; |
2621 | ||
e17a4113 | 2622 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2623 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2624 | return 0; |
c906108c | 2625 | |
e17a4113 | 2626 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2627 | return 1; |
2628 | } | |
fc338970 | 2629 | \f |
c906108c | 2630 | |
7ccc1c74 JM |
2631 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2632 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2633 | unions containing such types must be 16-byte-aligned; other | |
2634 | arguments are 4-byte-aligned. */ | |
2635 | ||
2636 | static int | |
2637 | i386_16_byte_align_p (struct type *type) | |
2638 | { | |
2639 | type = check_typedef (type); | |
2640 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2641 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2642 | && TYPE_LENGTH (type) == 16) | |
2643 | return 1; | |
2644 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2645 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2646 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2647 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2648 | { | |
2649 | int i; | |
2650 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2651 | { | |
2652 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2653 | return 1; | |
2654 | } | |
2655 | } | |
2656 | return 0; | |
2657 | } | |
2658 | ||
a9b8d892 JK |
2659 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2660 | ||
2661 | static CORE_ADDR | |
2662 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2663 | struct value **args, int nargs, struct type *value_type, | |
2664 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2665 | struct regcache *regcache) | |
2666 | { | |
2667 | /* Use 0xcc breakpoint - 1 byte. */ | |
2668 | *bp_addr = sp - 1; | |
2669 | *real_pc = funaddr; | |
2670 | ||
2671 | /* Keep the stack aligned. */ | |
2672 | return sp - 16; | |
2673 | } | |
2674 | ||
3a1e71e3 | 2675 | static CORE_ADDR |
7d9b040b | 2676 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2677 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2678 | struct value **args, CORE_ADDR sp, int struct_return, | |
2679 | CORE_ADDR struct_addr) | |
22f8ba57 | 2680 | { |
e17a4113 | 2681 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2682 | gdb_byte buf[4]; |
acd5c798 | 2683 | int i; |
7ccc1c74 JM |
2684 | int write_pass; |
2685 | int args_space = 0; | |
acd5c798 | 2686 | |
4a612d6f WT |
2687 | /* BND registers can be in arbitrary values at the moment of the |
2688 | inferior call. This can cause boundary violations that are not | |
2689 | due to a real bug or even desired by the user. The best to be done | |
2690 | is set the BND registers to allow access to the whole memory, INIT | |
2691 | state, before pushing the inferior call. */ | |
2692 | i387_reset_bnd_regs (gdbarch, regcache); | |
2693 | ||
7ccc1c74 JM |
2694 | /* Determine the total space required for arguments and struct |
2695 | return address in a first pass (allowing for 16-byte-aligned | |
2696 | arguments), then push arguments in a second pass. */ | |
2697 | ||
2698 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2699 | { |
7ccc1c74 | 2700 | int args_space_used = 0; |
7ccc1c74 JM |
2701 | |
2702 | if (struct_return) | |
2703 | { | |
2704 | if (write_pass) | |
2705 | { | |
2706 | /* Push value address. */ | |
e17a4113 | 2707 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2708 | write_memory (sp, buf, 4); |
2709 | args_space_used += 4; | |
2710 | } | |
2711 | else | |
2712 | args_space += 4; | |
2713 | } | |
2714 | ||
2715 | for (i = 0; i < nargs; i++) | |
2716 | { | |
2717 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2718 | |
7ccc1c74 JM |
2719 | if (write_pass) |
2720 | { | |
2721 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2722 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2723 | |
7ccc1c74 JM |
2724 | write_memory (sp + args_space_used, |
2725 | value_contents_all (args[i]), len); | |
2726 | /* The System V ABI says that: | |
acd5c798 | 2727 | |
7ccc1c74 JM |
2728 | "An argument's size is increased, if necessary, to make it a |
2729 | multiple of [32-bit] words. This may require tail padding, | |
2730 | depending on the size of the argument." | |
22f8ba57 | 2731 | |
7ccc1c74 JM |
2732 | This makes sure the stack stays word-aligned. */ |
2733 | args_space_used += align_up (len, 4); | |
2734 | } | |
2735 | else | |
2736 | { | |
2737 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2738 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2739 | args_space += align_up (len, 4); |
2740 | } | |
2741 | } | |
2742 | ||
2743 | if (!write_pass) | |
2744 | { | |
7ccc1c74 | 2745 | sp -= args_space; |
284c5a60 MK |
2746 | |
2747 | /* The original System V ABI only requires word alignment, | |
2748 | but modern incarnations need 16-byte alignment in order | |
2749 | to support SSE. Since wasting a few bytes here isn't | |
2750 | harmful we unconditionally enforce 16-byte alignment. */ | |
2751 | sp &= ~0xf; | |
7ccc1c74 | 2752 | } |
22f8ba57 MK |
2753 | } |
2754 | ||
acd5c798 MK |
2755 | /* Store return address. */ |
2756 | sp -= 4; | |
e17a4113 | 2757 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2758 | write_memory (sp, buf, 4); |
2759 | ||
2760 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2761 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2762 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2763 | ||
2764 | /* ...and fake a frame pointer. */ | |
2765 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2766 | ||
3e210248 AC |
2767 | /* MarkK wrote: This "+ 8" is all over the place: |
2768 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2769 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2770 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2771 | definition of the stack address of a frame. Otherwise frame id |
2772 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2773 | stack address *before* the function call as a frame's CFA. On |
2774 | the i386, when %ebp is used as a frame pointer, the offset | |
2775 | between the contents %ebp and the CFA as defined by GCC. */ | |
2776 | return sp + 8; | |
22f8ba57 MK |
2777 | } |
2778 | ||
1a309862 MK |
2779 | /* These registers are used for returning integers (and on some |
2780 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2781 | size and alignment match an integer type). */ |
acd5c798 MK |
2782 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2783 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2784 | |
c5e656c1 MK |
2785 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2786 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2787 | |
3a1e71e3 | 2788 | static void |
c5e656c1 | 2789 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2790 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2791 | { |
c5e656c1 | 2792 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2793 | int len = TYPE_LENGTH (type); |
63c0089f | 2794 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2795 | |
1e8d0a7b | 2796 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2797 | { |
5716833c | 2798 | if (tdep->st0_regnum < 0) |
1a309862 | 2799 | { |
8a3fe4f8 | 2800 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2801 | memset (valbuf, 0, len); |
ef9dff19 | 2802 | return; |
1a309862 MK |
2803 | } |
2804 | ||
c6ba6f0d MK |
2805 | /* Floating-point return values can be found in %st(0). Convert |
2806 | its contents to the desired type. This is probably not | |
2807 | exactly how it would happen on the target itself, but it is | |
2808 | the best we can do. */ | |
acd5c798 | 2809 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2810 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2811 | } |
2812 | else | |
c5aa993b | 2813 | { |
875f8d0e UW |
2814 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2815 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2816 | |
2817 | if (len <= low_size) | |
00f8375e | 2818 | { |
0818c12a | 2819 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2820 | memcpy (valbuf, buf, len); |
2821 | } | |
d4f3574e SS |
2822 | else if (len <= (low_size + high_size)) |
2823 | { | |
0818c12a | 2824 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2825 | memcpy (valbuf, buf, low_size); |
0818c12a | 2826 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2827 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2828 | } |
2829 | else | |
8e65ff28 | 2830 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2831 | _("Cannot extract return value of %d bytes long."), |
2832 | len); | |
c906108c SS |
2833 | } |
2834 | } | |
2835 | ||
c5e656c1 MK |
2836 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2837 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2838 | |
3a1e71e3 | 2839 | static void |
c5e656c1 | 2840 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2841 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2842 | { |
c5e656c1 | 2843 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2844 | int len = TYPE_LENGTH (type); |
2845 | ||
1e8d0a7b | 2846 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2847 | { |
3d7f4f49 | 2848 | ULONGEST fstat; |
63c0089f | 2849 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2850 | |
5716833c | 2851 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2852 | { |
8a3fe4f8 | 2853 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2854 | return; |
2855 | } | |
2856 | ||
635b0cc1 MK |
2857 | /* Returning floating-point values is a bit tricky. Apart from |
2858 | storing the return value in %st(0), we have to simulate the | |
2859 | state of the FPU at function return point. */ | |
2860 | ||
c6ba6f0d MK |
2861 | /* Convert the value found in VALBUF to the extended |
2862 | floating-point format used by the FPU. This is probably | |
2863 | not exactly how it would happen on the target itself, but | |
2864 | it is the best we can do. */ | |
27067745 | 2865 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2866 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2867 | |
635b0cc1 MK |
2868 | /* Set the top of the floating-point register stack to 7. The |
2869 | actual value doesn't really matter, but 7 is what a normal | |
2870 | function return would end up with if the program started out | |
2871 | with a freshly initialized FPU. */ | |
20a6ec49 | 2872 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2873 | fstat |= (7 << 11); |
20a6ec49 | 2874 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2875 | |
635b0cc1 MK |
2876 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2877 | the floating-point register stack to 7, the appropriate value | |
2878 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2879 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2880 | } |
2881 | else | |
2882 | { | |
875f8d0e UW |
2883 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2884 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2885 | |
2886 | if (len <= low_size) | |
3d7f4f49 | 2887 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2888 | else if (len <= (low_size + high_size)) |
2889 | { | |
3d7f4f49 MK |
2890 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2891 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2892 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2893 | } |
2894 | else | |
8e65ff28 | 2895 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2896 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2897 | } |
2898 | } | |
fc338970 | 2899 | \f |
ef9dff19 | 2900 | |
8201327c MK |
2901 | /* This is the variable that is set with "set struct-convention", and |
2902 | its legitimate values. */ | |
2903 | static const char default_struct_convention[] = "default"; | |
2904 | static const char pcc_struct_convention[] = "pcc"; | |
2905 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2906 | static const char *const valid_conventions[] = |
8201327c MK |
2907 | { |
2908 | default_struct_convention, | |
2909 | pcc_struct_convention, | |
2910 | reg_struct_convention, | |
2911 | NULL | |
2912 | }; | |
2913 | static const char *struct_convention = default_struct_convention; | |
2914 | ||
0e4377e1 JB |
2915 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2916 | a union type, or an array type, should be returned in registers | |
2917 | for architecture GDBARCH. */ | |
c5e656c1 | 2918 | |
8201327c | 2919 | static int |
c5e656c1 | 2920 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2921 | { |
c5e656c1 MK |
2922 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2923 | enum type_code code = TYPE_CODE (type); | |
2924 | int len = TYPE_LENGTH (type); | |
8201327c | 2925 | |
0e4377e1 JB |
2926 | gdb_assert (code == TYPE_CODE_STRUCT |
2927 | || code == TYPE_CODE_UNION | |
2928 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2929 | |
2930 | if (struct_convention == pcc_struct_convention | |
2931 | || (struct_convention == default_struct_convention | |
2932 | && tdep->struct_return == pcc_struct_return)) | |
2933 | return 0; | |
2934 | ||
9edde48e MK |
2935 | /* Structures consisting of a single `float', `double' or 'long |
2936 | double' member are returned in %st(0). */ | |
2937 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2938 | { | |
2939 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2940 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2941 | return (len == 4 || len == 8 || len == 12); | |
2942 | } | |
2943 | ||
c5e656c1 MK |
2944 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2945 | } | |
2946 | ||
2947 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2948 | should be returned. If it is supposed to be returned in registers, | |
2949 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2950 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2951 | from WRITEBUF into REGCACHE. */ | |
2952 | ||
2953 | static enum return_value_convention | |
6a3a010b | 2954 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2955 | struct type *type, struct regcache *regcache, |
2956 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2957 | { |
2958 | enum type_code code = TYPE_CODE (type); | |
2959 | ||
5daa78cc TJB |
2960 | if (((code == TYPE_CODE_STRUCT |
2961 | || code == TYPE_CODE_UNION | |
2962 | || code == TYPE_CODE_ARRAY) | |
2963 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2964 | /* Complex double and long double uses the struct return covention. */ |
2965 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2966 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2967 | /* 128-bit decimal float uses the struct return convention. */ |
2968 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2969 | { |
2970 | /* The System V ABI says that: | |
2971 | ||
2972 | "A function that returns a structure or union also sets %eax | |
2973 | to the value of the original address of the caller's area | |
2974 | before it returns. Thus when the caller receives control | |
2975 | again, the address of the returned object resides in register | |
2976 | %eax and can be used to access the object." | |
2977 | ||
2978 | So the ABI guarantees that we can always find the return | |
2979 | value just after the function has returned. */ | |
2980 | ||
0e4377e1 JB |
2981 | /* Note that the ABI doesn't mention functions returning arrays, |
2982 | which is something possible in certain languages such as Ada. | |
2983 | In this case, the value is returned as if it was wrapped in | |
2984 | a record, so the convention applied to records also applies | |
2985 | to arrays. */ | |
2986 | ||
31db7b6c MK |
2987 | if (readbuf) |
2988 | { | |
2989 | ULONGEST addr; | |
2990 | ||
2991 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2992 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2993 | } | |
2994 | ||
2995 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2996 | } | |
c5e656c1 MK |
2997 | |
2998 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2999 | `float', `double' or 'long double' member. These structures are |
3000 | returned in %st(0). For these structures, we call ourselves | |
3001 | recursively, changing TYPE into the type of the first member of | |
3002 | the structure. Since that should work for all structures that | |
3003 | have only one member, we don't bother to check the member's type | |
3004 | here. */ | |
c5e656c1 MK |
3005 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
3006 | { | |
3007 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 3008 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 3009 | readbuf, writebuf); |
c5e656c1 MK |
3010 | } |
3011 | ||
3012 | if (readbuf) | |
3013 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
3014 | if (writebuf) | |
3015 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3016 | |
c5e656c1 | 3017 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3018 | } |
3019 | \f | |
3020 | ||
27067745 UW |
3021 | struct type * |
3022 | i387_ext_type (struct gdbarch *gdbarch) | |
3023 | { | |
3024 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3025 | ||
3026 | if (!tdep->i387_ext_type) | |
90884b2b L |
3027 | { |
3028 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3029 | gdb_assert (tdep->i387_ext_type != NULL); | |
3030 | } | |
27067745 UW |
3031 | |
3032 | return tdep->i387_ext_type; | |
3033 | } | |
3034 | ||
1dbcd68c WT |
3035 | /* Construct type for pseudo BND registers. We can't use |
3036 | tdesc_find_type since a complement of one value has to be used | |
3037 | to describe the upper bound. */ | |
3038 | ||
3039 | static struct type * | |
3040 | i386_bnd_type (struct gdbarch *gdbarch) | |
3041 | { | |
3042 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3043 | ||
3044 | ||
3045 | if (!tdep->i386_bnd_type) | |
3046 | { | |
870f88f7 | 3047 | struct type *t; |
1dbcd68c WT |
3048 | const struct builtin_type *bt = builtin_type (gdbarch); |
3049 | ||
3050 | /* The type we're building is described bellow: */ | |
3051 | #if 0 | |
3052 | struct __bound128 | |
3053 | { | |
3054 | void *lbound; | |
3055 | void *ubound; /* One complement of raw ubound field. */ | |
3056 | }; | |
3057 | #endif | |
3058 | ||
3059 | t = arch_composite_type (gdbarch, | |
3060 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3061 | ||
3062 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3063 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3064 | ||
3065 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3066 | tdep->i386_bnd_type = t; | |
3067 | } | |
3068 | ||
3069 | return tdep->i386_bnd_type; | |
3070 | } | |
3071 | ||
01f9f808 MS |
3072 | /* Construct vector type for pseudo ZMM registers. We can't use |
3073 | tdesc_find_type since ZMM isn't described in target description. */ | |
3074 | ||
3075 | static struct type * | |
3076 | i386_zmm_type (struct gdbarch *gdbarch) | |
3077 | { | |
3078 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3079 | ||
3080 | if (!tdep->i386_zmm_type) | |
3081 | { | |
3082 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3083 | ||
3084 | /* The type we're building is this: */ | |
3085 | #if 0 | |
3086 | union __gdb_builtin_type_vec512i | |
3087 | { | |
3088 | int128_t uint128[4]; | |
3089 | int64_t v4_int64[8]; | |
3090 | int32_t v8_int32[16]; | |
3091 | int16_t v16_int16[32]; | |
3092 | int8_t v32_int8[64]; | |
3093 | double v4_double[8]; | |
3094 | float v8_float[16]; | |
3095 | }; | |
3096 | #endif | |
3097 | ||
3098 | struct type *t; | |
3099 | ||
3100 | t = arch_composite_type (gdbarch, | |
3101 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3102 | append_composite_type_field (t, "v16_float", | |
3103 | init_vector_type (bt->builtin_float, 16)); | |
3104 | append_composite_type_field (t, "v8_double", | |
3105 | init_vector_type (bt->builtin_double, 8)); | |
3106 | append_composite_type_field (t, "v64_int8", | |
3107 | init_vector_type (bt->builtin_int8, 64)); | |
3108 | append_composite_type_field (t, "v32_int16", | |
3109 | init_vector_type (bt->builtin_int16, 32)); | |
3110 | append_composite_type_field (t, "v16_int32", | |
3111 | init_vector_type (bt->builtin_int32, 16)); | |
3112 | append_composite_type_field (t, "v8_int64", | |
3113 | init_vector_type (bt->builtin_int64, 8)); | |
3114 | append_composite_type_field (t, "v4_int128", | |
3115 | init_vector_type (bt->builtin_int128, 4)); | |
3116 | ||
3117 | TYPE_VECTOR (t) = 1; | |
3118 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3119 | tdep->i386_zmm_type = t; | |
3120 | } | |
3121 | ||
3122 | return tdep->i386_zmm_type; | |
3123 | } | |
3124 | ||
c131fcee L |
3125 | /* Construct vector type for pseudo YMM registers. We can't use |
3126 | tdesc_find_type since YMM isn't described in target description. */ | |
3127 | ||
3128 | static struct type * | |
3129 | i386_ymm_type (struct gdbarch *gdbarch) | |
3130 | { | |
3131 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3132 | ||
3133 | if (!tdep->i386_ymm_type) | |
3134 | { | |
3135 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3136 | ||
3137 | /* The type we're building is this: */ | |
3138 | #if 0 | |
3139 | union __gdb_builtin_type_vec256i | |
3140 | { | |
3141 | int128_t uint128[2]; | |
3142 | int64_t v2_int64[4]; | |
3143 | int32_t v4_int32[8]; | |
3144 | int16_t v8_int16[16]; | |
3145 | int8_t v16_int8[32]; | |
3146 | double v2_double[4]; | |
3147 | float v4_float[8]; | |
3148 | }; | |
3149 | #endif | |
3150 | ||
3151 | struct type *t; | |
3152 | ||
3153 | t = arch_composite_type (gdbarch, | |
3154 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3155 | append_composite_type_field (t, "v8_float", | |
3156 | init_vector_type (bt->builtin_float, 8)); | |
3157 | append_composite_type_field (t, "v4_double", | |
3158 | init_vector_type (bt->builtin_double, 4)); | |
3159 | append_composite_type_field (t, "v32_int8", | |
3160 | init_vector_type (bt->builtin_int8, 32)); | |
3161 | append_composite_type_field (t, "v16_int16", | |
3162 | init_vector_type (bt->builtin_int16, 16)); | |
3163 | append_composite_type_field (t, "v8_int32", | |
3164 | init_vector_type (bt->builtin_int32, 8)); | |
3165 | append_composite_type_field (t, "v4_int64", | |
3166 | init_vector_type (bt->builtin_int64, 4)); | |
3167 | append_composite_type_field (t, "v2_int128", | |
3168 | init_vector_type (bt->builtin_int128, 2)); | |
3169 | ||
3170 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3171 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3172 | tdep->i386_ymm_type = t; |
3173 | } | |
3174 | ||
3175 | return tdep->i386_ymm_type; | |
3176 | } | |
3177 | ||
794ac428 | 3178 | /* Construct vector type for MMX registers. */ |
90884b2b | 3179 | static struct type * |
794ac428 UW |
3180 | i386_mmx_type (struct gdbarch *gdbarch) |
3181 | { | |
3182 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3183 | ||
3184 | if (!tdep->i386_mmx_type) | |
3185 | { | |
df4df182 UW |
3186 | const struct builtin_type *bt = builtin_type (gdbarch); |
3187 | ||
794ac428 UW |
3188 | /* The type we're building is this: */ |
3189 | #if 0 | |
3190 | union __gdb_builtin_type_vec64i | |
3191 | { | |
3192 | int64_t uint64; | |
3193 | int32_t v2_int32[2]; | |
3194 | int16_t v4_int16[4]; | |
3195 | int8_t v8_int8[8]; | |
3196 | }; | |
3197 | #endif | |
3198 | ||
3199 | struct type *t; | |
3200 | ||
e9bb382b UW |
3201 | t = arch_composite_type (gdbarch, |
3202 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3203 | |
3204 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3205 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3206 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3207 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3208 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3209 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3210 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3211 | |
876cecd0 | 3212 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3213 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3214 | tdep->i386_mmx_type = t; | |
3215 | } | |
3216 | ||
3217 | return tdep->i386_mmx_type; | |
3218 | } | |
3219 | ||
d7a0d72c | 3220 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3221 | register REGNUM. */ |
d7a0d72c | 3222 | |
fff4548b | 3223 | struct type * |
90884b2b | 3224 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3225 | { |
1dbcd68c WT |
3226 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3227 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3228 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3229 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3230 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3231 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3232 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3233 | return i386_ymm_type (gdbarch); | |
3234 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3235 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3236 | else |
3237 | { | |
3238 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3239 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3240 | return bt->builtin_int8; | |
3241 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3242 | return bt->builtin_int16; | |
3243 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3244 | return bt->builtin_int32; | |
01f9f808 MS |
3245 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3246 | return bt->builtin_int64; | |
1ba53b71 L |
3247 | } |
3248 | ||
3249 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3250 | } |
3251 | ||
28fc6740 | 3252 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3253 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3254 | |
3255 | static int | |
c86c27af | 3256 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3257 | { |
5716833c MK |
3258 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3259 | int mmxreg, fpreg; | |
28fc6740 AC |
3260 | ULONGEST fstat; |
3261 | int tos; | |
c86c27af | 3262 | |
5716833c | 3263 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3264 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3265 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3266 | fpreg = (mmxreg + tos) % 8; |
3267 | ||
20a6ec49 | 3268 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3269 | } |
3270 | ||
3543a589 TT |
3271 | /* A helper function for us by i386_pseudo_register_read_value and |
3272 | amd64_pseudo_register_read_value. It does all the work but reads | |
3273 | the data into an already-allocated value. */ | |
3274 | ||
3275 | void | |
3276 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3277 | struct regcache *regcache, | |
3278 | int regnum, | |
3279 | struct value *result_value) | |
28fc6740 | 3280 | { |
975c21ab | 3281 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3282 | enum register_status status; |
3543a589 | 3283 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3284 | |
5716833c | 3285 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3286 | { |
c86c27af MK |
3287 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3288 | ||
28fc6740 | 3289 | /* Extract (always little endian). */ |
05d1431c PA |
3290 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3291 | if (status != REG_VALID) | |
3543a589 TT |
3292 | mark_value_bytes_unavailable (result_value, 0, |
3293 | TYPE_LENGTH (value_type (result_value))); | |
3294 | else | |
3295 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3296 | } |
3297 | else | |
1ba53b71 L |
3298 | { |
3299 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3300 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3301 | { | |
3302 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3303 | |
1dbcd68c WT |
3304 | /* Extract (always little endian). Read lower 128bits. */ |
3305 | status = regcache_raw_read (regcache, | |
3306 | I387_BND0R_REGNUM (tdep) + regnum, | |
3307 | raw_buf); | |
3308 | if (status != REG_VALID) | |
3309 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3310 | else | |
3311 | { | |
3312 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3313 | LONGEST upper, lower; | |
3314 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3315 | ||
3316 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3317 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3318 | upper = ~upper; | |
3319 | ||
3320 | memcpy (buf, &lower, size); | |
3321 | memcpy (buf + size, &upper, size); | |
3322 | } | |
3323 | } | |
01f9f808 MS |
3324 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3325 | { | |
3326 | regnum -= tdep->k0_regnum; | |
3327 | ||
3328 | /* Extract (always little endian). */ | |
3329 | status = regcache_raw_read (regcache, | |
3330 | tdep->k0_regnum + regnum, | |
3331 | raw_buf); | |
3332 | if (status != REG_VALID) | |
3333 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3334 | else | |
3335 | memcpy (buf, raw_buf, 8); | |
3336 | } | |
3337 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3338 | { | |
3339 | regnum -= tdep->zmm0_regnum; | |
3340 | ||
3341 | if (regnum < num_lower_zmm_regs) | |
3342 | { | |
3343 | /* Extract (always little endian). Read lower 128bits. */ | |
3344 | status = regcache_raw_read (regcache, | |
3345 | I387_XMM0_REGNUM (tdep) + regnum, | |
3346 | raw_buf); | |
3347 | if (status != REG_VALID) | |
3348 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3349 | else | |
3350 | memcpy (buf, raw_buf, 16); | |
3351 | ||
3352 | /* Extract (always little endian). Read upper 128bits. */ | |
3353 | status = regcache_raw_read (regcache, | |
3354 | tdep->ymm0h_regnum + regnum, | |
3355 | raw_buf); | |
3356 | if (status != REG_VALID) | |
3357 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3358 | else | |
3359 | memcpy (buf + 16, raw_buf, 16); | |
3360 | } | |
3361 | else | |
3362 | { | |
3363 | /* Extract (always little endian). Read lower 128bits. */ | |
3364 | status = regcache_raw_read (regcache, | |
3365 | I387_XMM16_REGNUM (tdep) + regnum | |
3366 | - num_lower_zmm_regs, | |
3367 | raw_buf); | |
3368 | if (status != REG_VALID) | |
3369 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3370 | else | |
3371 | memcpy (buf, raw_buf, 16); | |
3372 | ||
3373 | /* Extract (always little endian). Read upper 128bits. */ | |
3374 | status = regcache_raw_read (regcache, | |
3375 | I387_YMM16H_REGNUM (tdep) + regnum | |
3376 | - num_lower_zmm_regs, | |
3377 | raw_buf); | |
3378 | if (status != REG_VALID) | |
3379 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3380 | else | |
3381 | memcpy (buf + 16, raw_buf, 16); | |
3382 | } | |
3383 | ||
3384 | /* Read upper 256bits. */ | |
3385 | status = regcache_raw_read (regcache, | |
3386 | tdep->zmm0h_regnum + regnum, | |
3387 | raw_buf); | |
3388 | if (status != REG_VALID) | |
3389 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3390 | else | |
3391 | memcpy (buf + 32, raw_buf, 32); | |
3392 | } | |
1dbcd68c | 3393 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3394 | { |
3395 | regnum -= tdep->ymm0_regnum; | |
3396 | ||
1777feb0 | 3397 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3398 | status = regcache_raw_read (regcache, |
3399 | I387_XMM0_REGNUM (tdep) + regnum, | |
3400 | raw_buf); | |
3401 | if (status != REG_VALID) | |
3543a589 TT |
3402 | mark_value_bytes_unavailable (result_value, 0, 16); |
3403 | else | |
3404 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3405 | /* Read upper 128bits. */ |
05d1431c PA |
3406 | status = regcache_raw_read (regcache, |
3407 | tdep->ymm0h_regnum + regnum, | |
3408 | raw_buf); | |
3409 | if (status != REG_VALID) | |
3543a589 TT |
3410 | mark_value_bytes_unavailable (result_value, 16, 32); |
3411 | else | |
3412 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3413 | } |
01f9f808 MS |
3414 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3415 | { | |
3416 | regnum -= tdep->ymm16_regnum; | |
3417 | /* Extract (always little endian). Read lower 128bits. */ | |
3418 | status = regcache_raw_read (regcache, | |
3419 | I387_XMM16_REGNUM (tdep) + regnum, | |
3420 | raw_buf); | |
3421 | if (status != REG_VALID) | |
3422 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3423 | else | |
3424 | memcpy (buf, raw_buf, 16); | |
3425 | /* Read upper 128bits. */ | |
3426 | status = regcache_raw_read (regcache, | |
3427 | tdep->ymm16h_regnum + regnum, | |
3428 | raw_buf); | |
3429 | if (status != REG_VALID) | |
3430 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3431 | else | |
3432 | memcpy (buf + 16, raw_buf, 16); | |
3433 | } | |
c131fcee | 3434 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3435 | { |
3436 | int gpnum = regnum - tdep->ax_regnum; | |
3437 | ||
3438 | /* Extract (always little endian). */ | |
05d1431c PA |
3439 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3440 | if (status != REG_VALID) | |
3543a589 TT |
3441 | mark_value_bytes_unavailable (result_value, 0, |
3442 | TYPE_LENGTH (value_type (result_value))); | |
3443 | else | |
3444 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3445 | } |
3446 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3447 | { | |
1ba53b71 L |
3448 | int gpnum = regnum - tdep->al_regnum; |
3449 | ||
3450 | /* Extract (always little endian). We read both lower and | |
3451 | upper registers. */ | |
05d1431c PA |
3452 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3453 | if (status != REG_VALID) | |
3543a589 TT |
3454 | mark_value_bytes_unavailable (result_value, 0, |
3455 | TYPE_LENGTH (value_type (result_value))); | |
3456 | else if (gpnum >= 4) | |
1ba53b71 L |
3457 | memcpy (buf, raw_buf + 1, 1); |
3458 | else | |
3459 | memcpy (buf, raw_buf, 1); | |
3460 | } | |
3461 | else | |
3462 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3463 | } | |
3543a589 TT |
3464 | } |
3465 | ||
3466 | static struct value * | |
3467 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3468 | struct regcache *regcache, | |
3469 | int regnum) | |
3470 | { | |
3471 | struct value *result; | |
3472 | ||
3473 | result = allocate_value (register_type (gdbarch, regnum)); | |
3474 | VALUE_LVAL (result) = lval_register; | |
3475 | VALUE_REGNUM (result) = regnum; | |
3476 | ||
3477 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3478 | |
3543a589 | 3479 | return result; |
28fc6740 AC |
3480 | } |
3481 | ||
1ba53b71 | 3482 | void |
28fc6740 | 3483 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3484 | int regnum, const gdb_byte *buf) |
28fc6740 | 3485 | { |
975c21ab | 3486 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3487 | |
5716833c | 3488 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3489 | { |
c86c27af MK |
3490 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3491 | ||
28fc6740 | 3492 | /* Read ... */ |
1ba53b71 | 3493 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3494 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3495 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3496 | /* ... Write. */ |
1ba53b71 | 3497 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3498 | } |
3499 | else | |
1ba53b71 L |
3500 | { |
3501 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3502 | ||
1dbcd68c WT |
3503 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3504 | { | |
3505 | ULONGEST upper, lower; | |
3506 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3507 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3508 | ||
3509 | /* New values from input value. */ | |
3510 | regnum -= tdep->bnd0_regnum; | |
3511 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3512 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3513 | ||
3514 | /* Fetching register buffer. */ | |
3515 | regcache_raw_read (regcache, | |
3516 | I387_BND0R_REGNUM (tdep) + regnum, | |
3517 | raw_buf); | |
3518 | ||
3519 | upper = ~upper; | |
3520 | ||
3521 | /* Set register bits. */ | |
3522 | memcpy (raw_buf, &lower, 8); | |
3523 | memcpy (raw_buf + 8, &upper, 8); | |
3524 | ||
3525 | ||
3526 | regcache_raw_write (regcache, | |
3527 | I387_BND0R_REGNUM (tdep) + regnum, | |
3528 | raw_buf); | |
3529 | } | |
01f9f808 MS |
3530 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3531 | { | |
3532 | regnum -= tdep->k0_regnum; | |
3533 | ||
3534 | regcache_raw_write (regcache, | |
3535 | tdep->k0_regnum + regnum, | |
3536 | buf); | |
3537 | } | |
3538 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3539 | { | |
3540 | regnum -= tdep->zmm0_regnum; | |
3541 | ||
3542 | if (regnum < num_lower_zmm_regs) | |
3543 | { | |
3544 | /* Write lower 128bits. */ | |
3545 | regcache_raw_write (regcache, | |
3546 | I387_XMM0_REGNUM (tdep) + regnum, | |
3547 | buf); | |
3548 | /* Write upper 128bits. */ | |
3549 | regcache_raw_write (regcache, | |
3550 | I387_YMM0_REGNUM (tdep) + regnum, | |
3551 | buf + 16); | |
3552 | } | |
3553 | else | |
3554 | { | |
3555 | /* Write lower 128bits. */ | |
3556 | regcache_raw_write (regcache, | |
3557 | I387_XMM16_REGNUM (tdep) + regnum | |
3558 | - num_lower_zmm_regs, | |
3559 | buf); | |
3560 | /* Write upper 128bits. */ | |
3561 | regcache_raw_write (regcache, | |
3562 | I387_YMM16H_REGNUM (tdep) + regnum | |
3563 | - num_lower_zmm_regs, | |
3564 | buf + 16); | |
3565 | } | |
3566 | /* Write upper 256bits. */ | |
3567 | regcache_raw_write (regcache, | |
3568 | tdep->zmm0h_regnum + regnum, | |
3569 | buf + 32); | |
3570 | } | |
1dbcd68c | 3571 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3572 | { |
3573 | regnum -= tdep->ymm0_regnum; | |
3574 | ||
3575 | /* ... Write lower 128bits. */ | |
3576 | regcache_raw_write (regcache, | |
3577 | I387_XMM0_REGNUM (tdep) + regnum, | |
3578 | buf); | |
3579 | /* ... Write upper 128bits. */ | |
3580 | regcache_raw_write (regcache, | |
3581 | tdep->ymm0h_regnum + regnum, | |
3582 | buf + 16); | |
3583 | } | |
01f9f808 MS |
3584 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3585 | { | |
3586 | regnum -= tdep->ymm16_regnum; | |
3587 | ||
3588 | /* ... Write lower 128bits. */ | |
3589 | regcache_raw_write (regcache, | |
3590 | I387_XMM16_REGNUM (tdep) + regnum, | |
3591 | buf); | |
3592 | /* ... Write upper 128bits. */ | |
3593 | regcache_raw_write (regcache, | |
3594 | tdep->ymm16h_regnum + regnum, | |
3595 | buf + 16); | |
3596 | } | |
c131fcee | 3597 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3598 | { |
3599 | int gpnum = regnum - tdep->ax_regnum; | |
3600 | ||
3601 | /* Read ... */ | |
3602 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3603 | /* ... Modify ... (always little endian). */ | |
3604 | memcpy (raw_buf, buf, 2); | |
3605 | /* ... Write. */ | |
3606 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3607 | } | |
3608 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3609 | { | |
1ba53b71 L |
3610 | int gpnum = regnum - tdep->al_regnum; |
3611 | ||
3612 | /* Read ... We read both lower and upper registers. */ | |
3613 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3614 | /* ... Modify ... (always little endian). */ | |
3615 | if (gpnum >= 4) | |
3616 | memcpy (raw_buf + 1, buf, 1); | |
3617 | else | |
3618 | memcpy (raw_buf, buf, 1); | |
3619 | /* ... Write. */ | |
3620 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3621 | } | |
3622 | else | |
3623 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3624 | } | |
28fc6740 | 3625 | } |
62e5fd57 MK |
3626 | |
3627 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3628 | ||
3629 | int | |
3630 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3631 | struct agent_expr *ax, int regnum) | |
3632 | { | |
3633 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3634 | ||
3635 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3636 | { | |
3637 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3638 | not care and collect everything... */ | |
3639 | int i; | |
3640 | ||
3641 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3642 | for (i = 0; i < 8; i++) | |
3643 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3644 | return 0; | |
3645 | } | |
3646 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3647 | { | |
3648 | regnum -= tdep->bnd0_regnum; | |
3649 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3650 | return 0; | |
3651 | } | |
3652 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3653 | { | |
3654 | regnum -= tdep->k0_regnum; | |
3655 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3656 | return 0; | |
3657 | } | |
3658 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3659 | { | |
3660 | regnum -= tdep->zmm0_regnum; | |
3661 | if (regnum < num_lower_zmm_regs) | |
3662 | { | |
3663 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3664 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3665 | } | |
3666 | else | |
3667 | { | |
3668 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3669 | - num_lower_zmm_regs); | |
3670 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3671 | - num_lower_zmm_regs); | |
3672 | } | |
3673 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3674 | return 0; | |
3675 | } | |
3676 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3677 | { | |
3678 | regnum -= tdep->ymm0_regnum; | |
3679 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3680 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3681 | return 0; | |
3682 | } | |
3683 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3684 | { | |
3685 | regnum -= tdep->ymm16_regnum; | |
3686 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3687 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3688 | return 0; | |
3689 | } | |
3690 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3691 | { | |
3692 | int gpnum = regnum - tdep->ax_regnum; | |
3693 | ||
3694 | ax_reg_mask (ax, gpnum); | |
3695 | return 0; | |
3696 | } | |
3697 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3698 | { | |
3699 | int gpnum = regnum - tdep->al_regnum; | |
3700 | ||
3701 | ax_reg_mask (ax, gpnum % 4); | |
3702 | return 0; | |
3703 | } | |
3704 | else | |
3705 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3706 | return 1; | |
3707 | } | |
ff2e87ac AC |
3708 | \f |
3709 | ||
ff2e87ac AC |
3710 | /* Return the register number of the register allocated by GCC after |
3711 | REGNUM, or -1 if there is no such register. */ | |
3712 | ||
3713 | static int | |
3714 | i386_next_regnum (int regnum) | |
3715 | { | |
3716 | /* GCC allocates the registers in the order: | |
3717 | ||
3718 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3719 | ||
3720 | Since storing a variable in %esp doesn't make any sense we return | |
3721 | -1 for %ebp and for %esp itself. */ | |
3722 | static int next_regnum[] = | |
3723 | { | |
3724 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3725 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3726 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3727 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3728 | -1, -1, /* Slots for %esp and %ebp. */ | |
3729 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3730 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3731 | }; | |
3732 | ||
de5b9bb9 | 3733 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3734 | return next_regnum[regnum]; |
28fc6740 | 3735 | |
ff2e87ac AC |
3736 | return -1; |
3737 | } | |
3738 | ||
3739 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3740 | needs any special handling. */ | |
d7a0d72c | 3741 | |
3a1e71e3 | 3742 | static int |
1777feb0 MS |
3743 | i386_convert_register_p (struct gdbarch *gdbarch, |
3744 | int regnum, struct type *type) | |
d7a0d72c | 3745 | { |
de5b9bb9 MK |
3746 | int len = TYPE_LENGTH (type); |
3747 | ||
ff2e87ac AC |
3748 | /* Values may be spread across multiple registers. Most debugging |
3749 | formats aren't expressive enough to specify the locations, so | |
3750 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3751 | have a length that is a multiple of the word size, since GCC |
3752 | doesn't seem to put any other types into registers. */ | |
3753 | if (len > 4 && len % 4 == 0) | |
3754 | { | |
3755 | int last_regnum = regnum; | |
3756 | ||
3757 | while (len > 4) | |
3758 | { | |
3759 | last_regnum = i386_next_regnum (last_regnum); | |
3760 | len -= 4; | |
3761 | } | |
3762 | ||
3763 | if (last_regnum != -1) | |
3764 | return 1; | |
3765 | } | |
ff2e87ac | 3766 | |
0abe36f5 | 3767 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3768 | } |
3769 | ||
ff2e87ac AC |
3770 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3771 | return its contents in TO. */ | |
ac27f131 | 3772 | |
8dccd430 | 3773 | static int |
ff2e87ac | 3774 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3775 | struct type *type, gdb_byte *to, |
3776 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3777 | { |
20a6ec49 | 3778 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3779 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3780 | |
20a6ec49 | 3781 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3782 | return i387_register_to_value (frame, regnum, type, to, |
3783 | optimizedp, unavailablep); | |
ff2e87ac | 3784 | |
fd35795f | 3785 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3786 | |
3787 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3788 | |
de5b9bb9 MK |
3789 | while (len > 0) |
3790 | { | |
3791 | gdb_assert (regnum != -1); | |
20a6ec49 | 3792 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3793 | |
8dccd430 PA |
3794 | if (!get_frame_register_bytes (frame, regnum, 0, |
3795 | register_size (gdbarch, regnum), | |
3796 | to, optimizedp, unavailablep)) | |
3797 | return 0; | |
3798 | ||
de5b9bb9 MK |
3799 | regnum = i386_next_regnum (regnum); |
3800 | len -= 4; | |
42835c2b | 3801 | to += 4; |
de5b9bb9 | 3802 | } |
8dccd430 PA |
3803 | |
3804 | *optimizedp = *unavailablep = 0; | |
3805 | return 1; | |
ac27f131 MK |
3806 | } |
3807 | ||
ff2e87ac AC |
3808 | /* Write the contents FROM of a value of type TYPE into register |
3809 | REGNUM in frame FRAME. */ | |
ac27f131 | 3810 | |
3a1e71e3 | 3811 | static void |
ff2e87ac | 3812 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3813 | struct type *type, const gdb_byte *from) |
ac27f131 | 3814 | { |
de5b9bb9 | 3815 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3816 | |
20a6ec49 | 3817 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3818 | { |
d532c08f MK |
3819 | i387_value_to_register (frame, regnum, type, from); |
3820 | return; | |
3821 | } | |
3d261580 | 3822 | |
fd35795f | 3823 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3824 | |
3825 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3826 | |
de5b9bb9 MK |
3827 | while (len > 0) |
3828 | { | |
3829 | gdb_assert (regnum != -1); | |
875f8d0e | 3830 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3831 | |
42835c2b | 3832 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3833 | regnum = i386_next_regnum (regnum); |
3834 | len -= 4; | |
42835c2b | 3835 | from += 4; |
de5b9bb9 | 3836 | } |
ac27f131 | 3837 | } |
ff2e87ac | 3838 | \f |
7fdafb5a MK |
3839 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3840 | in the general-purpose register set REGSET to register cache | |
3841 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3842 | |
20187ed5 | 3843 | void |
473f17b0 MK |
3844 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3845 | int regnum, const void *gregs, size_t len) | |
3846 | { | |
09424cff AA |
3847 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3848 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3849 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3850 | int i; |
3851 | ||
1528345d | 3852 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3853 | |
3854 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3855 | { | |
3856 | if ((regnum == i || regnum == -1) | |
3857 | && tdep->gregset_reg_offset[i] != -1) | |
3858 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3859 | } | |
3860 | } | |
3861 | ||
7fdafb5a MK |
3862 | /* Collect register REGNUM from the register cache REGCACHE and store |
3863 | it in the buffer specified by GREGS and LEN as described by the | |
3864 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3865 | all registers in REGSET. */ | |
3866 | ||
ecc37a5a | 3867 | static void |
7fdafb5a MK |
3868 | i386_collect_gregset (const struct regset *regset, |
3869 | const struct regcache *regcache, | |
3870 | int regnum, void *gregs, size_t len) | |
3871 | { | |
09424cff AA |
3872 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3873 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3874 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3875 | int i; |
3876 | ||
1528345d | 3877 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3878 | |
3879 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3880 | { | |
3881 | if ((regnum == i || regnum == -1) | |
3882 | && tdep->gregset_reg_offset[i] != -1) | |
3883 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3888 | in the floating-point register set REGSET to register cache | |
3889 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3890 | |
3891 | static void | |
3892 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3893 | int regnum, const void *fpregs, size_t len) | |
3894 | { | |
09424cff AA |
3895 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3896 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3897 | |
66a72d25 MK |
3898 | if (len == I387_SIZEOF_FXSAVE) |
3899 | { | |
3900 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3901 | return; | |
3902 | } | |
3903 | ||
1528345d | 3904 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3905 | i387_supply_fsave (regcache, regnum, fpregs); |
3906 | } | |
8446b36a | 3907 | |
2f305df1 MK |
3908 | /* Collect register REGNUM from the register cache REGCACHE and store |
3909 | it in the buffer specified by FPREGS and LEN as described by the | |
3910 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3911 | all registers in REGSET. */ | |
7fdafb5a MK |
3912 | |
3913 | static void | |
3914 | i386_collect_fpregset (const struct regset *regset, | |
3915 | const struct regcache *regcache, | |
3916 | int regnum, void *fpregs, size_t len) | |
3917 | { | |
09424cff AA |
3918 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3919 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3920 | |
3921 | if (len == I387_SIZEOF_FXSAVE) | |
3922 | { | |
3923 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3924 | return; | |
3925 | } | |
3926 | ||
1528345d | 3927 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3928 | i387_collect_fsave (regcache, regnum, fpregs); |
3929 | } | |
3930 | ||
ecc37a5a AA |
3931 | /* Register set definitions. */ |
3932 | ||
3933 | const struct regset i386_gregset = | |
3934 | { | |
3935 | NULL, i386_supply_gregset, i386_collect_gregset | |
3936 | }; | |
3937 | ||
8f0435f7 | 3938 | const struct regset i386_fpregset = |
ecc37a5a AA |
3939 | { |
3940 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3941 | }; | |
3942 | ||
490496c3 | 3943 | /* Default iterator over core file register note sections. */ |
8446b36a | 3944 | |
490496c3 AA |
3945 | void |
3946 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3947 | iterate_over_regset_sections_cb *cb, | |
3948 | void *cb_data, | |
3949 | const struct regcache *regcache) | |
8446b36a MK |
3950 | { |
3951 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3952 | ||
490496c3 AA |
3953 | cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data); |
3954 | if (tdep->sizeof_fpregset) | |
3955 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
8446b36a | 3956 | } |
473f17b0 | 3957 | \f |
fc338970 | 3958 | |
fc338970 | 3959 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3960 | |
3961 | CORE_ADDR | |
e17a4113 UW |
3962 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3963 | CORE_ADDR pc, char *name) | |
c906108c | 3964 | { |
e17a4113 UW |
3965 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3966 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3967 | ||
3968 | /* jmp *(dest) */ | |
3969 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3970 | { |
e17a4113 UW |
3971 | unsigned long indirect = |
3972 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3973 | struct minimal_symbol *indsym = |
7cbd4a93 | 3974 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3975 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3976 | |
c5aa993b | 3977 | if (symname) |
c906108c | 3978 | { |
61012eef GB |
3979 | if (startswith (symname, "__imp_") |
3980 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3981 | return name ? 1 : |
3982 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3983 | } |
3984 | } | |
fc338970 | 3985 | return 0; /* Not a trampoline. */ |
c906108c | 3986 | } |
fc338970 MK |
3987 | \f |
3988 | ||
10458914 DJ |
3989 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3990 | routine. */ | |
8201327c | 3991 | |
4bd207ef | 3992 | int |
10458914 | 3993 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3994 | { |
10458914 | 3995 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3996 | const char *name; |
911bc6ee MK |
3997 | |
3998 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3999 | return (name && strcmp ("_sigtramp", name) == 0); |
4000 | } | |
4001 | \f | |
4002 | ||
fc338970 MK |
4003 | /* We have two flavours of disassembly. The machinery on this page |
4004 | deals with switching between those. */ | |
c906108c SS |
4005 | |
4006 | static int | |
a89aa300 | 4007 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 4008 | { |
5e3397bb MK |
4009 | gdb_assert (disassembly_flavor == att_flavor |
4010 | || disassembly_flavor == intel_flavor); | |
4011 | ||
4012 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
4013 | constified, cast to prevent a compiler warning. */ | |
4014 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
4015 | |
4016 | return print_insn_i386 (pc, info); | |
7a292a7a | 4017 | } |
fc338970 | 4018 | \f |
3ce1502b | 4019 | |
8201327c MK |
4020 | /* There are a few i386 architecture variants that differ only |
4021 | slightly from the generic i386 target. For now, we don't give them | |
4022 | their own source file, but include them here. As a consequence, | |
4023 | they'll always be included. */ | |
3ce1502b | 4024 | |
8201327c | 4025 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4026 | |
10458914 DJ |
4027 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4028 | routine. */ | |
911bc6ee | 4029 | |
8201327c | 4030 | static int |
10458914 | 4031 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 4032 | { |
10458914 | 4033 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4034 | const char *name; |
911bc6ee | 4035 | |
05b4bd79 | 4036 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4037 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4038 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4039 | || strcmp ("sigvechandler", name) == 0)); |
4040 | } | |
d2a7c97a | 4041 | |
10458914 DJ |
4042 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4043 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4044 | |
3a1e71e3 | 4045 | static CORE_ADDR |
10458914 | 4046 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4047 | { |
e17a4113 UW |
4048 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4049 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4050 | gdb_byte buf[4]; |
acd5c798 | 4051 | CORE_ADDR sp; |
3ce1502b | 4052 | |
10458914 | 4053 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4054 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4055 | |
e17a4113 | 4056 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4057 | } |
55aa24fb SDJ |
4058 | |
4059 | \f | |
4060 | ||
4061 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4062 | gdbarch.h. */ | |
4063 | ||
4064 | int | |
4065 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4066 | { | |
4067 | return (*s == '$' /* Literal number. */ | |
4068 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4069 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4070 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4071 | } | |
4072 | ||
5acfdbae SDJ |
4073 | /* Helper function for i386_stap_parse_special_token. |
4074 | ||
4075 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4076 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4077 | ||
4078 | Return 1 if the operand was parsed successfully, zero | |
4079 | otherwise. */ | |
4080 | ||
4081 | static int | |
4082 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
4083 | struct stap_parse_info *p) | |
4084 | { | |
4085 | const char *s = p->arg; | |
4086 | ||
4087 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4088 | { | |
4089 | int got_minus[3]; | |
4090 | int i; | |
4091 | long displacements[3]; | |
4092 | const char *start; | |
4093 | char *regname; | |
4094 | int len; | |
4095 | struct stoken str; | |
4096 | char *endp; | |
4097 | ||
4098 | got_minus[0] = 0; | |
4099 | if (*s == '+') | |
4100 | ++s; | |
4101 | else if (*s == '-') | |
4102 | { | |
4103 | ++s; | |
4104 | got_minus[0] = 1; | |
4105 | } | |
4106 | ||
d7b30f67 SDJ |
4107 | if (!isdigit ((unsigned char) *s)) |
4108 | return 0; | |
4109 | ||
5acfdbae SDJ |
4110 | displacements[0] = strtol (s, &endp, 10); |
4111 | s = endp; | |
4112 | ||
4113 | if (*s != '+' && *s != '-') | |
4114 | { | |
4115 | /* We are not dealing with a triplet. */ | |
4116 | return 0; | |
4117 | } | |
4118 | ||
4119 | got_minus[1] = 0; | |
4120 | if (*s == '+') | |
4121 | ++s; | |
4122 | else | |
4123 | { | |
4124 | ++s; | |
4125 | got_minus[1] = 1; | |
4126 | } | |
4127 | ||
d7b30f67 SDJ |
4128 | if (!isdigit ((unsigned char) *s)) |
4129 | return 0; | |
4130 | ||
5acfdbae SDJ |
4131 | displacements[1] = strtol (s, &endp, 10); |
4132 | s = endp; | |
4133 | ||
4134 | if (*s != '+' && *s != '-') | |
4135 | { | |
4136 | /* We are not dealing with a triplet. */ | |
4137 | return 0; | |
4138 | } | |
4139 | ||
4140 | got_minus[2] = 0; | |
4141 | if (*s == '+') | |
4142 | ++s; | |
4143 | else | |
4144 | { | |
4145 | ++s; | |
4146 | got_minus[2] = 1; | |
4147 | } | |
4148 | ||
d7b30f67 SDJ |
4149 | if (!isdigit ((unsigned char) *s)) |
4150 | return 0; | |
4151 | ||
5acfdbae SDJ |
4152 | displacements[2] = strtol (s, &endp, 10); |
4153 | s = endp; | |
4154 | ||
4155 | if (*s != '(' || s[1] != '%') | |
4156 | return 0; | |
4157 | ||
4158 | s += 2; | |
4159 | start = s; | |
4160 | ||
4161 | while (isalnum (*s)) | |
4162 | ++s; | |
4163 | ||
4164 | if (*s++ != ')') | |
4165 | return 0; | |
4166 | ||
d7b30f67 | 4167 | len = s - start - 1; |
224c3ddb | 4168 | regname = (char *) alloca (len + 1); |
5acfdbae SDJ |
4169 | |
4170 | strncpy (regname, start, len); | |
4171 | regname[len] = '\0'; | |
4172 | ||
4173 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4174 | error (_("Invalid register name `%s' on expression `%s'."), | |
4175 | regname, p->saved_arg); | |
4176 | ||
4177 | for (i = 0; i < 3; i++) | |
4178 | { | |
410a0ff2 SDJ |
4179 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4180 | write_exp_elt_type | |
4181 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4182 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4183 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4184 | if (got_minus[i]) |
410a0ff2 | 4185 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4186 | } |
4187 | ||
410a0ff2 | 4188 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4189 | str.ptr = regname; |
4190 | str.length = len; | |
410a0ff2 SDJ |
4191 | write_exp_string (&p->pstate, str); |
4192 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4193 | |
410a0ff2 SDJ |
4194 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4195 | write_exp_elt_type (&p->pstate, | |
4196 | builtin_type (gdbarch)->builtin_data_ptr); | |
4197 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4198 | |
410a0ff2 SDJ |
4199 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4200 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4201 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4202 | |
410a0ff2 SDJ |
4203 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4204 | write_exp_elt_type (&p->pstate, | |
4205 | lookup_pointer_type (p->arg_type)); | |
4206 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4207 | |
410a0ff2 | 4208 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4209 | |
4210 | p->arg = s; | |
4211 | ||
4212 | return 1; | |
4213 | } | |
4214 | ||
4215 | return 0; | |
4216 | } | |
4217 | ||
4218 | /* Helper function for i386_stap_parse_special_token. | |
4219 | ||
4220 | This function parses operands of the form `register base + | |
4221 | (register index * size) + offset', as represented in | |
4222 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4223 | ||
4224 | Return 1 if the operand was parsed successfully, zero | |
4225 | otherwise. */ | |
4226 | ||
4227 | static int | |
4228 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4229 | struct stap_parse_info *p) | |
4230 | { | |
4231 | const char *s = p->arg; | |
4232 | ||
4233 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4234 | { | |
4235 | int offset_minus = 0; | |
4236 | long offset = 0; | |
4237 | int size_minus = 0; | |
4238 | long size = 0; | |
4239 | const char *start; | |
4240 | char *base; | |
4241 | int len_base; | |
4242 | char *index; | |
4243 | int len_index; | |
4244 | struct stoken base_token, index_token; | |
4245 | ||
4246 | if (*s == '+') | |
4247 | ++s; | |
4248 | else if (*s == '-') | |
4249 | { | |
4250 | ++s; | |
4251 | offset_minus = 1; | |
4252 | } | |
4253 | ||
4254 | if (offset_minus && !isdigit (*s)) | |
4255 | return 0; | |
4256 | ||
4257 | if (isdigit (*s)) | |
4258 | { | |
4259 | char *endp; | |
4260 | ||
4261 | offset = strtol (s, &endp, 10); | |
4262 | s = endp; | |
4263 | } | |
4264 | ||
4265 | if (*s != '(' || s[1] != '%') | |
4266 | return 0; | |
4267 | ||
4268 | s += 2; | |
4269 | start = s; | |
4270 | ||
4271 | while (isalnum (*s)) | |
4272 | ++s; | |
4273 | ||
4274 | if (*s != ',' || s[1] != '%') | |
4275 | return 0; | |
4276 | ||
4277 | len_base = s - start; | |
224c3ddb | 4278 | base = (char *) alloca (len_base + 1); |
5acfdbae SDJ |
4279 | strncpy (base, start, len_base); |
4280 | base[len_base] = '\0'; | |
4281 | ||
4282 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4283 | error (_("Invalid register name `%s' on expression `%s'."), | |
4284 | base, p->saved_arg); | |
4285 | ||
4286 | s += 2; | |
4287 | start = s; | |
4288 | ||
4289 | while (isalnum (*s)) | |
4290 | ++s; | |
4291 | ||
4292 | len_index = s - start; | |
224c3ddb | 4293 | index = (char *) alloca (len_index + 1); |
5acfdbae SDJ |
4294 | strncpy (index, start, len_index); |
4295 | index[len_index] = '\0'; | |
4296 | ||
4297 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4298 | error (_("Invalid register name `%s' on expression `%s'."), | |
4299 | index, p->saved_arg); | |
4300 | ||
4301 | if (*s != ',' && *s != ')') | |
4302 | return 0; | |
4303 | ||
4304 | if (*s == ',') | |
4305 | { | |
4306 | char *endp; | |
4307 | ||
4308 | ++s; | |
4309 | if (*s == '+') | |
4310 | ++s; | |
4311 | else if (*s == '-') | |
4312 | { | |
4313 | ++s; | |
4314 | size_minus = 1; | |
4315 | } | |
4316 | ||
4317 | size = strtol (s, &endp, 10); | |
4318 | s = endp; | |
4319 | ||
4320 | if (*s != ')') | |
4321 | return 0; | |
4322 | } | |
4323 | ||
4324 | ++s; | |
4325 | ||
4326 | if (offset) | |
4327 | { | |
410a0ff2 SDJ |
4328 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4329 | write_exp_elt_type (&p->pstate, | |
4330 | builtin_type (gdbarch)->builtin_long); | |
4331 | write_exp_elt_longcst (&p->pstate, offset); | |
4332 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4333 | if (offset_minus) |
410a0ff2 | 4334 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4335 | } |
4336 | ||
410a0ff2 | 4337 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4338 | base_token.ptr = base; |
4339 | base_token.length = len_base; | |
410a0ff2 SDJ |
4340 | write_exp_string (&p->pstate, base_token); |
4341 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4342 | |
4343 | if (offset) | |
410a0ff2 | 4344 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4345 | |
410a0ff2 | 4346 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4347 | index_token.ptr = index; |
4348 | index_token.length = len_index; | |
410a0ff2 SDJ |
4349 | write_exp_string (&p->pstate, index_token); |
4350 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4351 | |
4352 | if (size) | |
4353 | { | |
410a0ff2 SDJ |
4354 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4355 | write_exp_elt_type (&p->pstate, | |
4356 | builtin_type (gdbarch)->builtin_long); | |
4357 | write_exp_elt_longcst (&p->pstate, size); | |
4358 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4359 | if (size_minus) |
410a0ff2 SDJ |
4360 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4361 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4362 | } |
4363 | ||
410a0ff2 | 4364 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4365 | |
410a0ff2 SDJ |
4366 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4367 | write_exp_elt_type (&p->pstate, | |
4368 | lookup_pointer_type (p->arg_type)); | |
4369 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4370 | |
410a0ff2 | 4371 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4372 | |
4373 | p->arg = s; | |
4374 | ||
4375 | return 1; | |
4376 | } | |
4377 | ||
4378 | return 0; | |
4379 | } | |
4380 | ||
55aa24fb SDJ |
4381 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4382 | gdbarch.h. */ | |
4383 | ||
4384 | int | |
4385 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4386 | struct stap_parse_info *p) | |
4387 | { | |
55aa24fb SDJ |
4388 | /* In order to parse special tokens, we use a state-machine that go |
4389 | through every known token and try to get a match. */ | |
4390 | enum | |
4391 | { | |
4392 | TRIPLET, | |
4393 | THREE_ARG_DISPLACEMENT, | |
4394 | DONE | |
570dc176 TT |
4395 | }; |
4396 | int current_state; | |
55aa24fb SDJ |
4397 | |
4398 | current_state = TRIPLET; | |
4399 | ||
4400 | /* The special tokens to be parsed here are: | |
4401 | ||
4402 | - `register base + (register index * size) + offset', as represented | |
4403 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4404 | ||
4405 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4406 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4407 | ||
4408 | while (current_state != DONE) | |
4409 | { | |
55aa24fb SDJ |
4410 | switch (current_state) |
4411 | { | |
4412 | case TRIPLET: | |
5acfdbae SDJ |
4413 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4414 | return 1; | |
4415 | break; | |
4416 | ||
55aa24fb | 4417 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4418 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4419 | return 1; | |
4420 | break; | |
55aa24fb SDJ |
4421 | } |
4422 | ||
4423 | /* Advancing to the next state. */ | |
4424 | ++current_state; | |
4425 | } | |
4426 | ||
4427 | return 0; | |
4428 | } | |
4429 | ||
8201327c | 4430 | \f |
3ce1502b | 4431 | |
ac04f72b TT |
4432 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4433 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4434 | ||
4435 | static const char * | |
4436 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4437 | { | |
4438 | return "(x86_64|i.86)"; | |
4439 | } | |
4440 | ||
4441 | \f | |
4442 | ||
8201327c | 4443 | /* Generic ELF. */ |
d2a7c97a | 4444 | |
8201327c MK |
4445 | void |
4446 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4447 | { | |
05c0465e SDJ |
4448 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4449 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4450 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4451 | NULL }; | |
4452 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4453 | NULL }; | |
4454 | ||
c4fc7f1b MK |
4455 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4456 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4457 | |
4458 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4459 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4460 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4461 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4462 | stap_register_indirection_prefixes); | |
4463 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4464 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4465 | set_gdbarch_stap_is_single_operand (gdbarch, |
4466 | i386_stap_is_single_operand); | |
4467 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4468 | i386_stap_parse_special_token); | |
ac04f72b TT |
4469 | |
4470 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
8201327c | 4471 | } |
3ce1502b | 4472 | |
8201327c | 4473 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4474 | |
8201327c MK |
4475 | void |
4476 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4477 | { | |
4478 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4479 | |
8201327c MK |
4480 | /* System V Release 4 uses ELF. */ |
4481 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4482 | |
dfe01d39 | 4483 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4484 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4485 | ||
911bc6ee | 4486 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4487 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4488 | tdep->sc_pc_offset = 36 + 14 * 4; |
4489 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4490 | |
8201327c | 4491 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4492 | } |
4493 | ||
8201327c | 4494 | /* DJGPP. */ |
3ce1502b | 4495 | |
3a1e71e3 | 4496 | static void |
8201327c | 4497 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 4498 | { |
8201327c | 4499 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 4500 | |
911bc6ee MK |
4501 | /* DJGPP doesn't have any special frames for signal handlers. */ |
4502 | tdep->sigtramp_p = NULL; | |
3ce1502b | 4503 | |
8201327c | 4504 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
4505 | |
4506 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
4507 | if (! tdesc_has_registers (info.target_desc)) |
4508 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
4509 | |
4510 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
4511 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
4512 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
4513 | set_gdbarch_sdb_reg_to_regnum. */ | |
4514 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
4515 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
4516 | |
4517 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
ac04f72b TT |
4518 | |
4519 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
3ce1502b | 4520 | } |
8201327c | 4521 | \f |
2acceee2 | 4522 | |
38c968cf AC |
4523 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4524 | and "sse". */ | |
4525 | ||
4526 | static struct reggroup *i386_sse_reggroup; | |
4527 | static struct reggroup *i386_mmx_reggroup; | |
4528 | ||
4529 | static void | |
4530 | i386_init_reggroups (void) | |
4531 | { | |
4532 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4533 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4534 | } | |
4535 | ||
4536 | static void | |
4537 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4538 | { | |
4539 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4540 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4541 | reggroup_add (gdbarch, general_reggroup); | |
4542 | reggroup_add (gdbarch, float_reggroup); | |
4543 | reggroup_add (gdbarch, all_reggroup); | |
4544 | reggroup_add (gdbarch, save_reggroup); | |
4545 | reggroup_add (gdbarch, restore_reggroup); | |
4546 | reggroup_add (gdbarch, vector_reggroup); | |
4547 | reggroup_add (gdbarch, system_reggroup); | |
4548 | } | |
4549 | ||
4550 | int | |
4551 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4552 | struct reggroup *group) | |
4553 | { | |
c131fcee L |
4554 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4555 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4556 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4557 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4558 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4559 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4560 | |
1ba53b71 L |
4561 | /* Don't include pseudo registers, except for MMX, in any register |
4562 | groups. */ | |
c131fcee | 4563 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4564 | return 0; |
4565 | ||
c131fcee | 4566 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4567 | return 0; |
4568 | ||
c131fcee | 4569 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4570 | return 0; |
4571 | ||
4572 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4573 | if (group == i386_mmx_reggroup) |
4574 | return mmx_regnum_p; | |
1ba53b71 | 4575 | |
51547df6 | 4576 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4577 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4578 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4579 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4580 | if (group == i386_sse_reggroup) |
01f9f808 | 4581 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4582 | |
4583 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4584 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4585 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4586 | ||
22049425 MS |
4587 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4588 | == X86_XSTATE_AVX_AVX512_MASK); | |
4589 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4590 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4591 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4592 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4593 | |
38c968cf | 4594 | if (group == vector_reggroup) |
c131fcee | 4595 | return (mmx_regnum_p |
01f9f808 MS |
4596 | || (zmm_regnum_p && avx512_p) |
4597 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4598 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4599 | || mxcsr_regnum_p); | |
1ba53b71 L |
4600 | |
4601 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4602 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4603 | if (group == float_reggroup) |
4604 | return fp_regnum_p; | |
1ba53b71 | 4605 | |
c131fcee L |
4606 | /* For "info reg all", don't include upper YMM registers nor XMM |
4607 | registers when AVX is supported. */ | |
4608 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4609 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4610 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4611 | if (group == all_reggroup |
01f9f808 MS |
4612 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4613 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4614 | || ymmh_regnum_p | |
4615 | || ymmh_avx512_regnum_p | |
4616 | || zmmh_regnum_p)) | |
c131fcee L |
4617 | return 0; |
4618 | ||
1dbcd68c WT |
4619 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4620 | if (group == all_reggroup | |
df7e5265 | 4621 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4622 | return bnd_regnum_p; |
4623 | ||
4624 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4625 | if (group == all_reggroup | |
df7e5265 | 4626 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4627 | return 0; |
4628 | ||
4629 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4630 | if (group == all_reggroup | |
df7e5265 | 4631 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4632 | return mpx_ctrl_regnum_p; |
4633 | ||
38c968cf | 4634 | if (group == general_reggroup) |
1ba53b71 L |
4635 | return (!fp_regnum_p |
4636 | && !mmx_regnum_p | |
c131fcee L |
4637 | && !mxcsr_regnum_p |
4638 | && !xmm_regnum_p | |
01f9f808 | 4639 | && !xmm_avx512_regnum_p |
c131fcee | 4640 | && !ymm_regnum_p |
1dbcd68c | 4641 | && !ymmh_regnum_p |
01f9f808 MS |
4642 | && !ymm_avx512_regnum_p |
4643 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4644 | && !bndr_regnum_p |
4645 | && !bnd_regnum_p | |
01f9f808 MS |
4646 | && !mpx_ctrl_regnum_p |
4647 | && !zmm_regnum_p | |
51547df6 MS |
4648 | && !zmmh_regnum_p |
4649 | && !pkru_regnum_p); | |
acd5c798 | 4650 | |
38c968cf AC |
4651 | return default_register_reggroup_p (gdbarch, regnum, group); |
4652 | } | |
38c968cf | 4653 | \f |
acd5c798 | 4654 | |
f837910f MK |
4655 | /* Get the ARGIth function argument for the current function. */ |
4656 | ||
42c466d7 | 4657 | static CORE_ADDR |
143985b7 AF |
4658 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4659 | struct type *type) | |
4660 | { | |
e17a4113 UW |
4661 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4662 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4663 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4664 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4665 | } |
4666 | ||
7ad10968 HZ |
4667 | #define PREFIX_REPZ 0x01 |
4668 | #define PREFIX_REPNZ 0x02 | |
4669 | #define PREFIX_LOCK 0x04 | |
4670 | #define PREFIX_DATA 0x08 | |
4671 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4672 | |
7ad10968 HZ |
4673 | /* operand size */ |
4674 | enum | |
4675 | { | |
4676 | OT_BYTE = 0, | |
4677 | OT_WORD, | |
4678 | OT_LONG, | |
cf648174 | 4679 | OT_QUAD, |
a3c4230a | 4680 | OT_DQUAD, |
7ad10968 | 4681 | }; |
473f17b0 | 4682 | |
7ad10968 HZ |
4683 | /* i386 arith/logic operations */ |
4684 | enum | |
4685 | { | |
4686 | OP_ADDL, | |
4687 | OP_ORL, | |
4688 | OP_ADCL, | |
4689 | OP_SBBL, | |
4690 | OP_ANDL, | |
4691 | OP_SUBL, | |
4692 | OP_XORL, | |
4693 | OP_CMPL, | |
4694 | }; | |
5716833c | 4695 | |
7ad10968 HZ |
4696 | struct i386_record_s |
4697 | { | |
cf648174 | 4698 | struct gdbarch *gdbarch; |
7ad10968 | 4699 | struct regcache *regcache; |
df61f520 | 4700 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4701 | CORE_ADDR addr; |
4702 | int aflag; | |
4703 | int dflag; | |
4704 | int override; | |
4705 | uint8_t modrm; | |
4706 | uint8_t mod, reg, rm; | |
4707 | int ot; | |
cf648174 HZ |
4708 | uint8_t rex_x; |
4709 | uint8_t rex_b; | |
4710 | int rip_offset; | |
4711 | int popl_esp_hack; | |
4712 | const int *regmap; | |
7ad10968 | 4713 | }; |
5716833c | 4714 | |
99c1624c PA |
4715 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4716 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4717 | |
7ad10968 HZ |
4718 | static int |
4719 | i386_record_modrm (struct i386_record_s *irp) | |
4720 | { | |
cf648174 | 4721 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4722 | |
4ffa4fc7 PA |
4723 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4724 | return -1; | |
4725 | ||
7ad10968 HZ |
4726 | irp->addr++; |
4727 | irp->mod = (irp->modrm >> 6) & 3; | |
4728 | irp->reg = (irp->modrm >> 3) & 7; | |
4729 | irp->rm = irp->modrm & 7; | |
5716833c | 4730 | |
7ad10968 HZ |
4731 | return 0; |
4732 | } | |
d2a7c97a | 4733 | |
99c1624c PA |
4734 | /* Extract the memory address that the current instruction writes to, |
4735 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4736 | |
7ad10968 | 4737 | static int |
cf648174 | 4738 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4739 | { |
cf648174 | 4740 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4741 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4742 | gdb_byte buf[4]; | |
4743 | ULONGEST offset64; | |
21d0e8a4 | 4744 | |
7ad10968 | 4745 | *addr = 0; |
1e87984a | 4746 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4747 | { |
1e87984a | 4748 | /* 32/64 bits */ |
7ad10968 HZ |
4749 | int havesib = 0; |
4750 | uint8_t scale = 0; | |
648d0c8b | 4751 | uint8_t byte; |
7ad10968 HZ |
4752 | uint8_t index = 0; |
4753 | uint8_t base = irp->rm; | |
896fb97d | 4754 | |
7ad10968 HZ |
4755 | if (base == 4) |
4756 | { | |
4757 | havesib = 1; | |
4ffa4fc7 PA |
4758 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4759 | return -1; | |
7ad10968 | 4760 | irp->addr++; |
648d0c8b MS |
4761 | scale = (byte >> 6) & 3; |
4762 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4763 | base = (byte & 7); | |
7ad10968 | 4764 | } |
cf648174 | 4765 | base |= irp->rex_b; |
21d0e8a4 | 4766 | |
7ad10968 HZ |
4767 | switch (irp->mod) |
4768 | { | |
4769 | case 0: | |
4770 | if ((base & 7) == 5) | |
4771 | { | |
4772 | base = 0xff; | |
4ffa4fc7 PA |
4773 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4774 | return -1; | |
7ad10968 | 4775 | irp->addr += 4; |
60a1502a | 4776 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4777 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4778 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4779 | } |
7ad10968 HZ |
4780 | break; |
4781 | case 1: | |
4ffa4fc7 PA |
4782 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4783 | return -1; | |
7ad10968 | 4784 | irp->addr++; |
60a1502a | 4785 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4786 | break; |
4787 | case 2: | |
4ffa4fc7 PA |
4788 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4789 | return -1; | |
60a1502a | 4790 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4791 | irp->addr += 4; |
4792 | break; | |
4793 | } | |
356a6b3e | 4794 | |
60a1502a | 4795 | offset64 = 0; |
7ad10968 | 4796 | if (base != 0xff) |
cf648174 HZ |
4797 | { |
4798 | if (base == 4 && irp->popl_esp_hack) | |
4799 | *addr += irp->popl_esp_hack; | |
4800 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4801 | &offset64); |
7ad10968 | 4802 | } |
cf648174 HZ |
4803 | if (irp->aflag == 2) |
4804 | { | |
60a1502a | 4805 | *addr += offset64; |
cf648174 HZ |
4806 | } |
4807 | else | |
60a1502a | 4808 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4809 | |
7ad10968 HZ |
4810 | if (havesib && (index != 4 || scale != 0)) |
4811 | { | |
cf648174 | 4812 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4813 | &offset64); |
cf648174 | 4814 | if (irp->aflag == 2) |
60a1502a | 4815 | *addr += offset64 << scale; |
cf648174 | 4816 | else |
60a1502a | 4817 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4818 | } |
e85596e0 L |
4819 | |
4820 | if (!irp->aflag) | |
4821 | { | |
4822 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4823 | address from 32-bit to 64-bit. */ | |
4824 | *addr = (uint32_t) *addr; | |
4825 | } | |
7ad10968 HZ |
4826 | } |
4827 | else | |
4828 | { | |
4829 | /* 16 bits */ | |
4830 | switch (irp->mod) | |
4831 | { | |
4832 | case 0: | |
4833 | if (irp->rm == 6) | |
4834 | { | |
4ffa4fc7 PA |
4835 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4836 | return -1; | |
7ad10968 | 4837 | irp->addr += 2; |
60a1502a | 4838 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4839 | irp->rm = 0; |
4840 | goto no_rm; | |
4841 | } | |
7ad10968 HZ |
4842 | break; |
4843 | case 1: | |
4ffa4fc7 PA |
4844 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4845 | return -1; | |
7ad10968 | 4846 | irp->addr++; |
60a1502a | 4847 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4848 | break; |
4849 | case 2: | |
4ffa4fc7 PA |
4850 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4851 | return -1; | |
7ad10968 | 4852 | irp->addr += 2; |
60a1502a | 4853 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4854 | break; |
4855 | } | |
c4fc7f1b | 4856 | |
7ad10968 HZ |
4857 | switch (irp->rm) |
4858 | { | |
4859 | case 0: | |
cf648174 HZ |
4860 | regcache_raw_read_unsigned (irp->regcache, |
4861 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4862 | &offset64); |
4863 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4864 | regcache_raw_read_unsigned (irp->regcache, |
4865 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4866 | &offset64); |
4867 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4868 | break; |
4869 | case 1: | |
cf648174 HZ |
4870 | regcache_raw_read_unsigned (irp->regcache, |
4871 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4872 | &offset64); |
4873 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4874 | regcache_raw_read_unsigned (irp->regcache, |
4875 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4876 | &offset64); |
4877 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4878 | break; |
4879 | case 2: | |
cf648174 HZ |
4880 | regcache_raw_read_unsigned (irp->regcache, |
4881 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4882 | &offset64); |
4883 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4884 | regcache_raw_read_unsigned (irp->regcache, |
4885 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4886 | &offset64); |
4887 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4888 | break; |
4889 | case 3: | |
cf648174 HZ |
4890 | regcache_raw_read_unsigned (irp->regcache, |
4891 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4892 | &offset64); |
4893 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4894 | regcache_raw_read_unsigned (irp->regcache, |
4895 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4896 | &offset64); |
4897 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4898 | break; |
4899 | case 4: | |
cf648174 HZ |
4900 | regcache_raw_read_unsigned (irp->regcache, |
4901 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4902 | &offset64); |
4903 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4904 | break; |
4905 | case 5: | |
cf648174 HZ |
4906 | regcache_raw_read_unsigned (irp->regcache, |
4907 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4908 | &offset64); |
4909 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4910 | break; |
4911 | case 6: | |
cf648174 HZ |
4912 | regcache_raw_read_unsigned (irp->regcache, |
4913 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4914 | &offset64); |
4915 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4916 | break; |
4917 | case 7: | |
cf648174 HZ |
4918 | regcache_raw_read_unsigned (irp->regcache, |
4919 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4920 | &offset64); |
4921 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4922 | break; |
4923 | } | |
4924 | *addr &= 0xffff; | |
4925 | } | |
c4fc7f1b | 4926 | |
01fe1b41 | 4927 | no_rm: |
7ad10968 HZ |
4928 | return 0; |
4929 | } | |
c4fc7f1b | 4930 | |
99c1624c PA |
4931 | /* Record the address and contents of the memory that will be changed |
4932 | by the current instruction. Return -1 if something goes wrong, 0 | |
4933 | otherwise. */ | |
356a6b3e | 4934 | |
7ad10968 HZ |
4935 | static int |
4936 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4937 | { | |
cf648174 HZ |
4938 | struct gdbarch *gdbarch = irp->gdbarch; |
4939 | uint64_t addr; | |
356a6b3e | 4940 | |
d7877f7e | 4941 | if (irp->override >= 0) |
7ad10968 | 4942 | { |
25ea693b | 4943 | if (record_full_memory_query) |
bb08c432 | 4944 | { |
651ce16a | 4945 | if (yquery (_("\ |
bb08c432 HZ |
4946 | Process record ignores the memory change of instruction at address %s\n\ |
4947 | because it can't get the value of the segment register.\n\ | |
4948 | Do you want to stop the program?"), | |
651ce16a PA |
4949 | paddress (gdbarch, irp->orig_addr))) |
4950 | return -1; | |
bb08c432 HZ |
4951 | } |
4952 | ||
7ad10968 HZ |
4953 | return 0; |
4954 | } | |
61113f8b | 4955 | |
7ad10968 HZ |
4956 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4957 | return -1; | |
96297dab | 4958 | |
25ea693b | 4959 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4960 | return -1; |
a62cc96e | 4961 | |
7ad10968 HZ |
4962 | return 0; |
4963 | } | |
b6197528 | 4964 | |
99c1624c PA |
4965 | /* Record the effects of a push operation. Return -1 if something |
4966 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4967 | |
4968 | static int | |
4969 | i386_record_push (struct i386_record_s *irp, int size) | |
4970 | { | |
648d0c8b | 4971 | ULONGEST addr; |
cf648174 | 4972 | |
25ea693b MM |
4973 | if (record_full_arch_list_add_reg (irp->regcache, |
4974 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4975 | return -1; |
4976 | regcache_raw_read_unsigned (irp->regcache, | |
4977 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4978 | &addr); |
25ea693b | 4979 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4980 | return -1; |
4981 | ||
4982 | return 0; | |
4983 | } | |
4984 | ||
0289bdd7 MS |
4985 | |
4986 | /* Defines contents to record. */ | |
4987 | #define I386_SAVE_FPU_REGS 0xfffd | |
4988 | #define I386_SAVE_FPU_ENV 0xfffe | |
4989 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4990 | ||
99c1624c PA |
4991 | /* Record the values of the floating point registers which will be |
4992 | changed by the current instruction. Returns -1 if something is | |
4993 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4994 | |
4995 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4996 | struct i386_record_s *ir, | |
4997 | uint32_t iregnum) | |
4998 | { | |
4999 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5000 | int i; | |
5001 | ||
5002 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
5003 | happen. Currently we store st0-st7 registers, but we need not store all | |
5004 | registers all the time, in future we use ftag register and record only | |
5005 | those who are not marked as an empty. */ | |
5006 | ||
5007 | if (I386_SAVE_FPU_REGS == iregnum) | |
5008 | { | |
5009 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
5010 | { | |
25ea693b | 5011 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5012 | return -1; |
5013 | } | |
5014 | } | |
5015 | else if (I386_SAVE_FPU_ENV == iregnum) | |
5016 | { | |
5017 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5018 | { | |
25ea693b | 5019 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5020 | return -1; |
5021 | } | |
5022 | } | |
5023 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
5024 | { | |
5025 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5026 | { | |
25ea693b | 5027 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5028 | return -1; |
5029 | } | |
5030 | } | |
5031 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
5032 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
5033 | { | |
25ea693b | 5034 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
5035 | return -1; |
5036 | } | |
5037 | else | |
5038 | { | |
5039 | /* Parameter error. */ | |
5040 | return -1; | |
5041 | } | |
5042 | if(I386_SAVE_FPU_ENV != iregnum) | |
5043 | { | |
5044 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5045 | { | |
25ea693b | 5046 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5047 | return -1; |
5048 | } | |
5049 | } | |
5050 | return 0; | |
5051 | } | |
5052 | ||
99c1624c PA |
5053 | /* Parse the current instruction, and record the values of the |
5054 | registers and memory that will be changed by the current | |
5055 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5056 | |
25ea693b MM |
5057 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5058 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5059 | |
a6b808b4 | 5060 | int |
7ad10968 | 5061 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5062 | CORE_ADDR input_addr) |
7ad10968 | 5063 | { |
60a1502a | 5064 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5065 | int prefixes = 0; |
580879fc | 5066 | int regnum = 0; |
425b824a | 5067 | uint32_t opcode; |
f4644a3f | 5068 | uint8_t opcode8; |
648d0c8b | 5069 | ULONGEST addr; |
975c21ab | 5070 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5071 | struct i386_record_s ir; |
0289bdd7 | 5072 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5073 | uint8_t rex_w = -1; |
5074 | uint8_t rex_r = 0; | |
7ad10968 | 5075 | |
8408d274 | 5076 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5077 | ir.regcache = regcache; |
648d0c8b MS |
5078 | ir.addr = input_addr; |
5079 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5080 | ir.aflag = 1; |
5081 | ir.dflag = 1; | |
cf648174 HZ |
5082 | ir.override = -1; |
5083 | ir.popl_esp_hack = 0; | |
a3c4230a | 5084 | ir.regmap = tdep->record_regmap; |
cf648174 | 5085 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5086 | |
5087 | if (record_debug > 1) | |
5088 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
5089 | "addr = %s\n", |
5090 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5091 | |
5092 | /* prefixes */ | |
5093 | while (1) | |
5094 | { | |
4ffa4fc7 PA |
5095 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5096 | return -1; | |
7ad10968 | 5097 | ir.addr++; |
425b824a | 5098 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5099 | { |
01fe1b41 | 5100 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5101 | prefixes |= PREFIX_REPZ; |
5102 | break; | |
01fe1b41 | 5103 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5104 | prefixes |= PREFIX_REPNZ; |
5105 | break; | |
01fe1b41 | 5106 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5107 | prefixes |= PREFIX_LOCK; |
5108 | break; | |
01fe1b41 | 5109 | case CS_PREFIX_OPCODE: |
cf648174 | 5110 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5111 | break; |
01fe1b41 | 5112 | case SS_PREFIX_OPCODE: |
cf648174 | 5113 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5114 | break; |
01fe1b41 | 5115 | case DS_PREFIX_OPCODE: |
cf648174 | 5116 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5117 | break; |
01fe1b41 | 5118 | case ES_PREFIX_OPCODE: |
cf648174 | 5119 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5120 | break; |
01fe1b41 | 5121 | case FS_PREFIX_OPCODE: |
cf648174 | 5122 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5123 | break; |
01fe1b41 | 5124 | case GS_PREFIX_OPCODE: |
cf648174 | 5125 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5126 | break; |
01fe1b41 | 5127 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5128 | prefixes |= PREFIX_DATA; |
5129 | break; | |
01fe1b41 | 5130 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5131 | prefixes |= PREFIX_ADDR; |
5132 | break; | |
d691bec7 MS |
5133 | case 0x40: /* i386 inc %eax */ |
5134 | case 0x41: /* i386 inc %ecx */ | |
5135 | case 0x42: /* i386 inc %edx */ | |
5136 | case 0x43: /* i386 inc %ebx */ | |
5137 | case 0x44: /* i386 inc %esp */ | |
5138 | case 0x45: /* i386 inc %ebp */ | |
5139 | case 0x46: /* i386 inc %esi */ | |
5140 | case 0x47: /* i386 inc %edi */ | |
5141 | case 0x48: /* i386 dec %eax */ | |
5142 | case 0x49: /* i386 dec %ecx */ | |
5143 | case 0x4a: /* i386 dec %edx */ | |
5144 | case 0x4b: /* i386 dec %ebx */ | |
5145 | case 0x4c: /* i386 dec %esp */ | |
5146 | case 0x4d: /* i386 dec %ebp */ | |
5147 | case 0x4e: /* i386 dec %esi */ | |
5148 | case 0x4f: /* i386 dec %edi */ | |
5149 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5150 | { |
5151 | /* REX */ | |
425b824a MS |
5152 | rex_w = (opcode8 >> 3) & 1; |
5153 | rex_r = (opcode8 & 0x4) << 1; | |
5154 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5155 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5156 | } |
d691bec7 MS |
5157 | else /* 32 bit target */ |
5158 | goto out_prefixes; | |
cf648174 | 5159 | break; |
7ad10968 HZ |
5160 | default: |
5161 | goto out_prefixes; | |
5162 | break; | |
5163 | } | |
5164 | } | |
01fe1b41 | 5165 | out_prefixes: |
cf648174 HZ |
5166 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5167 | { | |
5168 | ir.dflag = 2; | |
5169 | } | |
5170 | else | |
5171 | { | |
5172 | if (prefixes & PREFIX_DATA) | |
5173 | ir.dflag ^= 1; | |
5174 | } | |
7ad10968 HZ |
5175 | if (prefixes & PREFIX_ADDR) |
5176 | ir.aflag ^= 1; | |
cf648174 HZ |
5177 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5178 | ir.aflag = 2; | |
7ad10968 | 5179 | |
1777feb0 | 5180 | /* Now check op code. */ |
425b824a | 5181 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5182 | reswitch: |
7ad10968 HZ |
5183 | switch (opcode) |
5184 | { | |
5185 | case 0x0f: | |
4ffa4fc7 PA |
5186 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5187 | return -1; | |
7ad10968 | 5188 | ir.addr++; |
a3c4230a | 5189 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5190 | goto reswitch; |
5191 | break; | |
93924b6b | 5192 | |
a38bba38 | 5193 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5194 | case 0x01: |
5195 | case 0x02: | |
5196 | case 0x03: | |
5197 | case 0x04: | |
5198 | case 0x05: | |
5199 | case 0x08: | |
5200 | case 0x09: | |
5201 | case 0x0a: | |
5202 | case 0x0b: | |
5203 | case 0x0c: | |
5204 | case 0x0d: | |
5205 | case 0x10: | |
5206 | case 0x11: | |
5207 | case 0x12: | |
5208 | case 0x13: | |
5209 | case 0x14: | |
5210 | case 0x15: | |
5211 | case 0x18: | |
5212 | case 0x19: | |
5213 | case 0x1a: | |
5214 | case 0x1b: | |
5215 | case 0x1c: | |
5216 | case 0x1d: | |
5217 | case 0x20: | |
5218 | case 0x21: | |
5219 | case 0x22: | |
5220 | case 0x23: | |
5221 | case 0x24: | |
5222 | case 0x25: | |
5223 | case 0x28: | |
5224 | case 0x29: | |
5225 | case 0x2a: | |
5226 | case 0x2b: | |
5227 | case 0x2c: | |
5228 | case 0x2d: | |
5229 | case 0x30: | |
5230 | case 0x31: | |
5231 | case 0x32: | |
5232 | case 0x33: | |
5233 | case 0x34: | |
5234 | case 0x35: | |
5235 | case 0x38: | |
5236 | case 0x39: | |
5237 | case 0x3a: | |
5238 | case 0x3b: | |
5239 | case 0x3c: | |
5240 | case 0x3d: | |
5241 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5242 | { | |
5243 | if ((opcode & 1) == 0) | |
5244 | ir.ot = OT_BYTE; | |
5245 | else | |
5246 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5247 | |
7ad10968 HZ |
5248 | switch ((opcode >> 1) & 3) |
5249 | { | |
a38bba38 | 5250 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5251 | if (i386_record_modrm (&ir)) |
5252 | return -1; | |
5253 | if (ir.mod != 3) | |
5254 | { | |
5255 | if (i386_record_lea_modrm (&ir)) | |
5256 | return -1; | |
5257 | } | |
5258 | else | |
5259 | { | |
cf648174 HZ |
5260 | ir.rm |= ir.rex_b; |
5261 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5262 | ir.rm &= 0x3; |
25ea693b | 5263 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5264 | } |
5265 | break; | |
a38bba38 | 5266 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5267 | if (i386_record_modrm (&ir)) |
5268 | return -1; | |
cf648174 HZ |
5269 | ir.reg |= rex_r; |
5270 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5271 | ir.reg &= 0x3; |
25ea693b | 5272 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5273 | break; |
a38bba38 | 5274 | case 2: /* OP A, Iv */ |
25ea693b | 5275 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5276 | break; |
5277 | } | |
5278 | } | |
25ea693b | 5279 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5280 | break; |
42fdc8df | 5281 | |
a38bba38 | 5282 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5283 | case 0x81: |
5284 | case 0x82: | |
5285 | case 0x83: | |
5286 | if (i386_record_modrm (&ir)) | |
5287 | return -1; | |
8201327c | 5288 | |
7ad10968 HZ |
5289 | if (ir.reg != OP_CMPL) |
5290 | { | |
5291 | if ((opcode & 1) == 0) | |
5292 | ir.ot = OT_BYTE; | |
5293 | else | |
5294 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5295 | |
7ad10968 HZ |
5296 | if (ir.mod != 3) |
5297 | { | |
cf648174 HZ |
5298 | if (opcode == 0x83) |
5299 | ir.rip_offset = 1; | |
5300 | else | |
5301 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5302 | if (i386_record_lea_modrm (&ir)) |
5303 | return -1; | |
5304 | } | |
5305 | else | |
25ea693b | 5306 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5307 | } |
25ea693b | 5308 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5309 | break; |
5e3397bb | 5310 | |
a38bba38 | 5311 | case 0x40: /* inc */ |
7ad10968 HZ |
5312 | case 0x41: |
5313 | case 0x42: | |
5314 | case 0x43: | |
5315 | case 0x44: | |
5316 | case 0x45: | |
5317 | case 0x46: | |
5318 | case 0x47: | |
a38bba38 MS |
5319 | |
5320 | case 0x48: /* dec */ | |
7ad10968 HZ |
5321 | case 0x49: |
5322 | case 0x4a: | |
5323 | case 0x4b: | |
5324 | case 0x4c: | |
5325 | case 0x4d: | |
5326 | case 0x4e: | |
5327 | case 0x4f: | |
a38bba38 | 5328 | |
25ea693b MM |
5329 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5330 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5331 | break; |
acd5c798 | 5332 | |
a38bba38 | 5333 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5334 | case 0xf7: |
5335 | if ((opcode & 1) == 0) | |
5336 | ir.ot = OT_BYTE; | |
5337 | else | |
5338 | ir.ot = ir.dflag + OT_WORD; | |
5339 | if (i386_record_modrm (&ir)) | |
5340 | return -1; | |
acd5c798 | 5341 | |
cf648174 HZ |
5342 | if (ir.mod != 3 && ir.reg == 0) |
5343 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5344 | ||
7ad10968 HZ |
5345 | switch (ir.reg) |
5346 | { | |
a38bba38 | 5347 | case 0: /* test */ |
25ea693b | 5348 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5349 | break; |
a38bba38 MS |
5350 | case 2: /* not */ |
5351 | case 3: /* neg */ | |
7ad10968 HZ |
5352 | if (ir.mod != 3) |
5353 | { | |
5354 | if (i386_record_lea_modrm (&ir)) | |
5355 | return -1; | |
5356 | } | |
5357 | else | |
5358 | { | |
cf648174 HZ |
5359 | ir.rm |= ir.rex_b; |
5360 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5361 | ir.rm &= 0x3; |
25ea693b | 5362 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5363 | } |
a38bba38 | 5364 | if (ir.reg == 3) /* neg */ |
25ea693b | 5365 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5366 | break; |
a38bba38 MS |
5367 | case 4: /* mul */ |
5368 | case 5: /* imul */ | |
5369 | case 6: /* div */ | |
5370 | case 7: /* idiv */ | |
25ea693b | 5371 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5372 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5373 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5374 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5375 | break; |
5376 | default: | |
5377 | ir.addr -= 2; | |
5378 | opcode = opcode << 8 | ir.modrm; | |
5379 | goto no_support; | |
5380 | break; | |
5381 | } | |
5382 | break; | |
5383 | ||
a38bba38 MS |
5384 | case 0xfe: /* GRP4 */ |
5385 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5386 | if (i386_record_modrm (&ir)) |
5387 | return -1; | |
5388 | if (ir.reg >= 2 && opcode == 0xfe) | |
5389 | { | |
5390 | ir.addr -= 2; | |
5391 | opcode = opcode << 8 | ir.modrm; | |
5392 | goto no_support; | |
5393 | } | |
7ad10968 HZ |
5394 | switch (ir.reg) |
5395 | { | |
a38bba38 MS |
5396 | case 0: /* inc */ |
5397 | case 1: /* dec */ | |
cf648174 HZ |
5398 | if ((opcode & 1) == 0) |
5399 | ir.ot = OT_BYTE; | |
5400 | else | |
5401 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5402 | if (ir.mod != 3) |
5403 | { | |
5404 | if (i386_record_lea_modrm (&ir)) | |
5405 | return -1; | |
5406 | } | |
5407 | else | |
5408 | { | |
cf648174 HZ |
5409 | ir.rm |= ir.rex_b; |
5410 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5411 | ir.rm &= 0x3; |
25ea693b | 5412 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5413 | } |
25ea693b | 5414 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5415 | break; |
a38bba38 | 5416 | case 2: /* call */ |
cf648174 HZ |
5417 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5418 | ir.dflag = 2; | |
5419 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5420 | return -1; |
25ea693b | 5421 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5422 | break; |
a38bba38 | 5423 | case 3: /* lcall */ |
25ea693b | 5424 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5425 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5426 | return -1; |
25ea693b | 5427 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5428 | break; |
a38bba38 MS |
5429 | case 4: /* jmp */ |
5430 | case 5: /* ljmp */ | |
25ea693b | 5431 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5432 | break; |
a38bba38 | 5433 | case 6: /* push */ |
cf648174 HZ |
5434 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5435 | ir.dflag = 2; | |
5436 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5437 | return -1; | |
7ad10968 HZ |
5438 | break; |
5439 | default: | |
5440 | ir.addr -= 2; | |
5441 | opcode = opcode << 8 | ir.modrm; | |
5442 | goto no_support; | |
5443 | break; | |
5444 | } | |
5445 | break; | |
5446 | ||
a38bba38 | 5447 | case 0x84: /* test */ |
7ad10968 HZ |
5448 | case 0x85: |
5449 | case 0xa8: | |
5450 | case 0xa9: | |
25ea693b | 5451 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5452 | break; |
5453 | ||
a38bba38 | 5454 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5455 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5456 | break; |
5457 | ||
a38bba38 | 5458 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5459 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5460 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5461 | break; |
5462 | ||
a38bba38 | 5463 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5464 | case 0x69: |
5465 | case 0x6b: | |
5466 | ir.ot = ir.dflag + OT_WORD; | |
5467 | if (i386_record_modrm (&ir)) | |
5468 | return -1; | |
cf648174 HZ |
5469 | if (opcode == 0x69) |
5470 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5471 | else if (opcode == 0x6b) | |
5472 | ir.rip_offset = 1; | |
5473 | ir.reg |= rex_r; | |
5474 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5475 | ir.reg &= 0x3; |
25ea693b MM |
5476 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5477 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5478 | break; |
5479 | ||
a38bba38 | 5480 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5481 | case 0x0fc1: |
5482 | if ((opcode & 1) == 0) | |
5483 | ir.ot = OT_BYTE; | |
5484 | else | |
5485 | ir.ot = ir.dflag + OT_WORD; | |
5486 | if (i386_record_modrm (&ir)) | |
5487 | return -1; | |
cf648174 | 5488 | ir.reg |= rex_r; |
7ad10968 HZ |
5489 | if (ir.mod == 3) |
5490 | { | |
cf648174 | 5491 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5492 | ir.reg &= 0x3; |
25ea693b | 5493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5494 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5495 | ir.rm &= 0x3; |
25ea693b | 5496 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5497 | } |
5498 | else | |
5499 | { | |
5500 | if (i386_record_lea_modrm (&ir)) | |
5501 | return -1; | |
cf648174 | 5502 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5503 | ir.reg &= 0x3; |
25ea693b | 5504 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5505 | } |
25ea693b | 5506 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5507 | break; |
5508 | ||
a38bba38 | 5509 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5510 | case 0x0fb1: |
5511 | if ((opcode & 1) == 0) | |
5512 | ir.ot = OT_BYTE; | |
5513 | else | |
5514 | ir.ot = ir.dflag + OT_WORD; | |
5515 | if (i386_record_modrm (&ir)) | |
5516 | return -1; | |
5517 | if (ir.mod == 3) | |
5518 | { | |
cf648174 | 5519 | ir.reg |= rex_r; |
25ea693b | 5520 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5521 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5522 | ir.reg &= 0x3; |
25ea693b | 5523 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5524 | } |
5525 | else | |
5526 | { | |
25ea693b | 5527 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5528 | if (i386_record_lea_modrm (&ir)) |
5529 | return -1; | |
5530 | } | |
25ea693b | 5531 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5532 | break; |
5533 | ||
20b477a7 | 5534 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5535 | if (i386_record_modrm (&ir)) |
5536 | return -1; | |
5537 | if (ir.mod == 3) | |
5538 | { | |
20b477a7 LM |
5539 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5540 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5541 | has bits 111 (/7). */ | |
5542 | if (ir.reg == 6 || ir.reg == 7) | |
5543 | { | |
5544 | /* The storage register is described by the 3 R/M bits, but the | |
5545 | REX.B prefix may be used to give access to registers | |
5546 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5547 | in the range R8~R15. | |
5548 | ||
5549 | REX.W may also be used to access 64-bit registers, but we | |
5550 | already record entire registers and not just partial bits | |
5551 | of them. */ | |
5552 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5553 | /* These instructions also set conditional bits. */ | |
5554 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5555 | break; | |
5556 | } | |
5557 | else | |
5558 | { | |
5559 | /* We don't handle this particular instruction yet. */ | |
5560 | ir.addr -= 2; | |
5561 | opcode = opcode << 8 | ir.modrm; | |
5562 | goto no_support; | |
5563 | } | |
7ad10968 | 5564 | } |
25ea693b MM |
5565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5566 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5567 | if (i386_record_lea_modrm (&ir)) |
5568 | return -1; | |
25ea693b | 5569 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5570 | break; |
5571 | ||
a38bba38 | 5572 | case 0x50: /* push */ |
7ad10968 HZ |
5573 | case 0x51: |
5574 | case 0x52: | |
5575 | case 0x53: | |
5576 | case 0x54: | |
5577 | case 0x55: | |
5578 | case 0x56: | |
5579 | case 0x57: | |
5580 | case 0x68: | |
5581 | case 0x6a: | |
cf648174 HZ |
5582 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5583 | ir.dflag = 2; | |
5584 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5585 | return -1; | |
5586 | break; | |
5587 | ||
a38bba38 MS |
5588 | case 0x06: /* push es */ |
5589 | case 0x0e: /* push cs */ | |
5590 | case 0x16: /* push ss */ | |
5591 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5592 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5593 | { | |
5594 | ir.addr -= 1; | |
5595 | goto no_support; | |
5596 | } | |
5597 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5598 | return -1; | |
5599 | break; | |
5600 | ||
a38bba38 MS |
5601 | case 0x0fa0: /* push fs */ |
5602 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5603 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5604 | { | |
5605 | ir.addr -= 2; | |
5606 | goto no_support; | |
5607 | } | |
5608 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5609 | return -1; |
cf648174 HZ |
5610 | break; |
5611 | ||
a38bba38 | 5612 | case 0x60: /* pusha */ |
cf648174 HZ |
5613 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5614 | { | |
5615 | ir.addr -= 1; | |
5616 | goto no_support; | |
5617 | } | |
5618 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5619 | return -1; |
5620 | break; | |
5621 | ||
a38bba38 | 5622 | case 0x58: /* pop */ |
7ad10968 HZ |
5623 | case 0x59: |
5624 | case 0x5a: | |
5625 | case 0x5b: | |
5626 | case 0x5c: | |
5627 | case 0x5d: | |
5628 | case 0x5e: | |
5629 | case 0x5f: | |
25ea693b MM |
5630 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5631 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5632 | break; |
5633 | ||
a38bba38 | 5634 | case 0x61: /* popa */ |
cf648174 HZ |
5635 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5636 | { | |
5637 | ir.addr -= 1; | |
5638 | goto no_support; | |
7ad10968 | 5639 | } |
425b824a MS |
5640 | for (regnum = X86_RECORD_REAX_REGNUM; |
5641 | regnum <= X86_RECORD_REDI_REGNUM; | |
5642 | regnum++) | |
25ea693b | 5643 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5644 | break; |
5645 | ||
a38bba38 | 5646 | case 0x8f: /* pop */ |
cf648174 HZ |
5647 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5648 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5649 | else | |
5650 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5651 | if (i386_record_modrm (&ir)) |
5652 | return -1; | |
5653 | if (ir.mod == 3) | |
25ea693b | 5654 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5655 | else |
5656 | { | |
cf648174 | 5657 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5658 | if (i386_record_lea_modrm (&ir)) |
5659 | return -1; | |
5660 | } | |
25ea693b | 5661 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5662 | break; |
5663 | ||
a38bba38 | 5664 | case 0xc8: /* enter */ |
25ea693b | 5665 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5666 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5667 | ir.dflag = 2; | |
5668 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5669 | return -1; |
5670 | break; | |
5671 | ||
a38bba38 | 5672 | case 0xc9: /* leave */ |
25ea693b MM |
5673 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5674 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5675 | break; |
5676 | ||
a38bba38 | 5677 | case 0x07: /* pop es */ |
cf648174 HZ |
5678 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5679 | { | |
5680 | ir.addr -= 1; | |
5681 | goto no_support; | |
5682 | } | |
25ea693b MM |
5683 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5684 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5685 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5686 | break; |
5687 | ||
a38bba38 | 5688 | case 0x17: /* pop ss */ |
cf648174 HZ |
5689 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5690 | { | |
5691 | ir.addr -= 1; | |
5692 | goto no_support; | |
5693 | } | |
25ea693b MM |
5694 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5695 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5696 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5697 | break; |
5698 | ||
a38bba38 | 5699 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5700 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5701 | { | |
5702 | ir.addr -= 1; | |
5703 | goto no_support; | |
5704 | } | |
25ea693b MM |
5705 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5706 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5707 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5708 | break; |
5709 | ||
a38bba38 | 5710 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5711 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5712 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5713 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5714 | break; |
5715 | ||
a38bba38 | 5716 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5717 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5718 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5719 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5720 | break; |
5721 | ||
a38bba38 | 5722 | case 0x88: /* mov */ |
7ad10968 HZ |
5723 | case 0x89: |
5724 | case 0xc6: | |
5725 | case 0xc7: | |
5726 | if ((opcode & 1) == 0) | |
5727 | ir.ot = OT_BYTE; | |
5728 | else | |
5729 | ir.ot = ir.dflag + OT_WORD; | |
5730 | ||
5731 | if (i386_record_modrm (&ir)) | |
5732 | return -1; | |
5733 | ||
5734 | if (ir.mod != 3) | |
5735 | { | |
cf648174 HZ |
5736 | if (opcode == 0xc6 || opcode == 0xc7) |
5737 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5738 | if (i386_record_lea_modrm (&ir)) |
5739 | return -1; | |
5740 | } | |
5741 | else | |
5742 | { | |
cf648174 HZ |
5743 | if (opcode == 0xc6 || opcode == 0xc7) |
5744 | ir.rm |= ir.rex_b; | |
5745 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5746 | ir.rm &= 0x3; |
25ea693b | 5747 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5748 | } |
7ad10968 | 5749 | break; |
cf648174 | 5750 | |
a38bba38 | 5751 | case 0x8a: /* mov */ |
7ad10968 HZ |
5752 | case 0x8b: |
5753 | if ((opcode & 1) == 0) | |
5754 | ir.ot = OT_BYTE; | |
5755 | else | |
5756 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5757 | if (i386_record_modrm (&ir)) |
5758 | return -1; | |
cf648174 HZ |
5759 | ir.reg |= rex_r; |
5760 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5761 | ir.reg &= 0x3; |
25ea693b | 5762 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5763 | break; |
7ad10968 | 5764 | |
a38bba38 | 5765 | case 0x8c: /* mov seg */ |
cf648174 | 5766 | if (i386_record_modrm (&ir)) |
7ad10968 | 5767 | return -1; |
cf648174 HZ |
5768 | if (ir.reg > 5) |
5769 | { | |
5770 | ir.addr -= 2; | |
5771 | opcode = opcode << 8 | ir.modrm; | |
5772 | goto no_support; | |
5773 | } | |
5774 | ||
5775 | if (ir.mod == 3) | |
25ea693b | 5776 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5777 | else |
5778 | { | |
5779 | ir.ot = OT_WORD; | |
5780 | if (i386_record_lea_modrm (&ir)) | |
5781 | return -1; | |
5782 | } | |
7ad10968 HZ |
5783 | break; |
5784 | ||
a38bba38 | 5785 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5786 | if (i386_record_modrm (&ir)) |
5787 | return -1; | |
7ad10968 HZ |
5788 | switch (ir.reg) |
5789 | { | |
5790 | case 0: | |
425b824a | 5791 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5792 | break; |
5793 | case 2: | |
425b824a | 5794 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5795 | break; |
5796 | case 3: | |
425b824a | 5797 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5798 | break; |
5799 | case 4: | |
425b824a | 5800 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5801 | break; |
5802 | case 5: | |
425b824a | 5803 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5804 | break; |
5805 | default: | |
5806 | ir.addr -= 2; | |
5807 | opcode = opcode << 8 | ir.modrm; | |
5808 | goto no_support; | |
5809 | break; | |
5810 | } | |
25ea693b MM |
5811 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5812 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5813 | break; |
5814 | ||
a38bba38 MS |
5815 | case 0x0fb6: /* movzbS */ |
5816 | case 0x0fb7: /* movzwS */ | |
5817 | case 0x0fbe: /* movsbS */ | |
5818 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5819 | if (i386_record_modrm (&ir)) |
5820 | return -1; | |
25ea693b | 5821 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5822 | break; |
5823 | ||
a38bba38 | 5824 | case 0x8d: /* lea */ |
7ad10968 HZ |
5825 | if (i386_record_modrm (&ir)) |
5826 | return -1; | |
5827 | if (ir.mod == 3) | |
5828 | { | |
5829 | ir.addr -= 2; | |
5830 | opcode = opcode << 8 | ir.modrm; | |
5831 | goto no_support; | |
5832 | } | |
7ad10968 | 5833 | ir.ot = ir.dflag; |
cf648174 HZ |
5834 | ir.reg |= rex_r; |
5835 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5836 | ir.reg &= 0x3; |
25ea693b | 5837 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5838 | break; |
5839 | ||
a38bba38 | 5840 | case 0xa0: /* mov EAX */ |
7ad10968 | 5841 | case 0xa1: |
a38bba38 MS |
5842 | |
5843 | case 0xd7: /* xlat */ | |
25ea693b | 5844 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5845 | break; |
5846 | ||
a38bba38 | 5847 | case 0xa2: /* mov EAX */ |
7ad10968 | 5848 | case 0xa3: |
d7877f7e | 5849 | if (ir.override >= 0) |
cf648174 | 5850 | { |
25ea693b | 5851 | if (record_full_memory_query) |
bb08c432 | 5852 | { |
651ce16a | 5853 | if (yquery (_("\ |
bb08c432 HZ |
5854 | Process record ignores the memory change of instruction at address %s\n\ |
5855 | because it can't get the value of the segment register.\n\ | |
5856 | Do you want to stop the program?"), | |
651ce16a | 5857 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
5858 | return -1; |
5859 | } | |
cf648174 HZ |
5860 | } |
5861 | else | |
5862 | { | |
5863 | if ((opcode & 1) == 0) | |
5864 | ir.ot = OT_BYTE; | |
5865 | else | |
5866 | ir.ot = ir.dflag + OT_WORD; | |
5867 | if (ir.aflag == 2) | |
5868 | { | |
4ffa4fc7 PA |
5869 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5870 | return -1; | |
cf648174 | 5871 | ir.addr += 8; |
60a1502a | 5872 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5873 | } |
5874 | else if (ir.aflag) | |
5875 | { | |
4ffa4fc7 PA |
5876 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5877 | return -1; | |
cf648174 | 5878 | ir.addr += 4; |
60a1502a | 5879 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5880 | } |
5881 | else | |
5882 | { | |
4ffa4fc7 PA |
5883 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5884 | return -1; | |
cf648174 | 5885 | ir.addr += 2; |
60a1502a | 5886 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5887 | } |
25ea693b | 5888 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5889 | return -1; |
5890 | } | |
7ad10968 HZ |
5891 | break; |
5892 | ||
a38bba38 | 5893 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5894 | case 0xb1: |
5895 | case 0xb2: | |
5896 | case 0xb3: | |
5897 | case 0xb4: | |
5898 | case 0xb5: | |
5899 | case 0xb6: | |
5900 | case 0xb7: | |
25ea693b MM |
5901 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5902 | ? ((opcode & 0x7) | ir.rex_b) | |
5903 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5904 | break; |
5905 | ||
a38bba38 | 5906 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5907 | case 0xb9: |
5908 | case 0xba: | |
5909 | case 0xbb: | |
5910 | case 0xbc: | |
5911 | case 0xbd: | |
5912 | case 0xbe: | |
5913 | case 0xbf: | |
25ea693b | 5914 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5915 | break; |
5916 | ||
a38bba38 | 5917 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5918 | case 0x92: |
5919 | case 0x93: | |
5920 | case 0x94: | |
5921 | case 0x95: | |
5922 | case 0x96: | |
5923 | case 0x97: | |
25ea693b MM |
5924 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5925 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5926 | break; |
5927 | ||
a38bba38 | 5928 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5929 | case 0x87: |
5930 | if ((opcode & 1) == 0) | |
5931 | ir.ot = OT_BYTE; | |
5932 | else | |
5933 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5934 | if (i386_record_modrm (&ir)) |
5935 | return -1; | |
7ad10968 HZ |
5936 | if (ir.mod == 3) |
5937 | { | |
86839d38 | 5938 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5939 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5940 | ir.rm &= 0x3; | |
25ea693b | 5941 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5942 | } |
5943 | else | |
5944 | { | |
5945 | if (i386_record_lea_modrm (&ir)) | |
5946 | return -1; | |
5947 | } | |
cf648174 HZ |
5948 | ir.reg |= rex_r; |
5949 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5950 | ir.reg &= 0x3; |
25ea693b | 5951 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5952 | break; |
5953 | ||
a38bba38 MS |
5954 | case 0xc4: /* les Gv */ |
5955 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5956 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5957 | { | |
5958 | ir.addr -= 1; | |
5959 | goto no_support; | |
5960 | } | |
d3f323f3 | 5961 | /* FALLTHROUGH */ |
a38bba38 MS |
5962 | case 0x0fb2: /* lss Gv */ |
5963 | case 0x0fb4: /* lfs Gv */ | |
5964 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5965 | if (i386_record_modrm (&ir)) |
5966 | return -1; | |
5967 | if (ir.mod == 3) | |
5968 | { | |
5969 | if (opcode > 0xff) | |
5970 | ir.addr -= 3; | |
5971 | else | |
5972 | ir.addr -= 2; | |
5973 | opcode = opcode << 8 | ir.modrm; | |
5974 | goto no_support; | |
5975 | } | |
7ad10968 HZ |
5976 | switch (opcode) |
5977 | { | |
a38bba38 | 5978 | case 0xc4: /* les Gv */ |
425b824a | 5979 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5980 | break; |
a38bba38 | 5981 | case 0xc5: /* lds Gv */ |
425b824a | 5982 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5983 | break; |
a38bba38 | 5984 | case 0x0fb2: /* lss Gv */ |
425b824a | 5985 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5986 | break; |
a38bba38 | 5987 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5988 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5989 | break; |
a38bba38 | 5990 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5991 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5992 | break; |
5993 | } | |
25ea693b MM |
5994 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5995 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5996 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5997 | break; |
5998 | ||
a38bba38 | 5999 | case 0xc0: /* shifts */ |
7ad10968 HZ |
6000 | case 0xc1: |
6001 | case 0xd0: | |
6002 | case 0xd1: | |
6003 | case 0xd2: | |
6004 | case 0xd3: | |
6005 | if ((opcode & 1) == 0) | |
6006 | ir.ot = OT_BYTE; | |
6007 | else | |
6008 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
6009 | if (i386_record_modrm (&ir)) |
6010 | return -1; | |
7ad10968 HZ |
6011 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
6012 | { | |
6013 | if (i386_record_lea_modrm (&ir)) | |
6014 | return -1; | |
6015 | } | |
6016 | else | |
6017 | { | |
cf648174 HZ |
6018 | ir.rm |= ir.rex_b; |
6019 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 6020 | ir.rm &= 0x3; |
25ea693b | 6021 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 6022 | } |
25ea693b | 6023 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6024 | break; |
6025 | ||
6026 | case 0x0fa4: | |
6027 | case 0x0fa5: | |
6028 | case 0x0fac: | |
6029 | case 0x0fad: | |
6030 | if (i386_record_modrm (&ir)) | |
6031 | return -1; | |
6032 | if (ir.mod == 3) | |
6033 | { | |
25ea693b | 6034 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
6035 | return -1; |
6036 | } | |
6037 | else | |
6038 | { | |
6039 | if (i386_record_lea_modrm (&ir)) | |
6040 | return -1; | |
6041 | } | |
6042 | break; | |
6043 | ||
a38bba38 | 6044 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
6045 | case 0xd9: |
6046 | case 0xda: | |
6047 | case 0xdb: | |
6048 | case 0xdc: | |
6049 | case 0xdd: | |
6050 | case 0xde: | |
6051 | case 0xdf: | |
6052 | if (i386_record_modrm (&ir)) | |
6053 | return -1; | |
6054 | ir.reg |= ((opcode & 7) << 3); | |
6055 | if (ir.mod != 3) | |
6056 | { | |
1777feb0 | 6057 | /* Memory. */ |
955db0c0 | 6058 | uint64_t addr64; |
7ad10968 | 6059 | |
955db0c0 | 6060 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6061 | return -1; |
6062 | switch (ir.reg) | |
6063 | { | |
7ad10968 | 6064 | case 0x02: |
0289bdd7 MS |
6065 | case 0x12: |
6066 | case 0x22: | |
6067 | case 0x32: | |
6068 | /* For fcom, ficom nothing to do. */ | |
6069 | break; | |
7ad10968 | 6070 | case 0x03: |
0289bdd7 MS |
6071 | case 0x13: |
6072 | case 0x23: | |
6073 | case 0x33: | |
6074 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
6075 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6076 | return -1; | |
6077 | break; | |
6078 | case 0x00: | |
6079 | case 0x01: | |
7ad10968 HZ |
6080 | case 0x04: |
6081 | case 0x05: | |
6082 | case 0x06: | |
6083 | case 0x07: | |
6084 | case 0x10: | |
6085 | case 0x11: | |
7ad10968 HZ |
6086 | case 0x14: |
6087 | case 0x15: | |
6088 | case 0x16: | |
6089 | case 0x17: | |
6090 | case 0x20: | |
6091 | case 0x21: | |
7ad10968 HZ |
6092 | case 0x24: |
6093 | case 0x25: | |
6094 | case 0x26: | |
6095 | case 0x27: | |
6096 | case 0x30: | |
6097 | case 0x31: | |
7ad10968 HZ |
6098 | case 0x34: |
6099 | case 0x35: | |
6100 | case 0x36: | |
6101 | case 0x37: | |
0289bdd7 MS |
6102 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6103 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6104 | of code, always affects st(0) register. */ | |
6105 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6106 | return -1; | |
7ad10968 HZ |
6107 | break; |
6108 | case 0x08: | |
6109 | case 0x0a: | |
6110 | case 0x0b: | |
6111 | case 0x18: | |
6112 | case 0x19: | |
6113 | case 0x1a: | |
6114 | case 0x1b: | |
0289bdd7 | 6115 | case 0x1d: |
7ad10968 HZ |
6116 | case 0x28: |
6117 | case 0x29: | |
6118 | case 0x2a: | |
6119 | case 0x2b: | |
6120 | case 0x38: | |
6121 | case 0x39: | |
6122 | case 0x3a: | |
6123 | case 0x3b: | |
0289bdd7 MS |
6124 | case 0x3c: |
6125 | case 0x3d: | |
7ad10968 HZ |
6126 | switch (ir.reg & 7) |
6127 | { | |
6128 | case 0: | |
0289bdd7 MS |
6129 | /* Handling fld, fild. */ |
6130 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6131 | return -1; | |
7ad10968 HZ |
6132 | break; |
6133 | case 1: | |
6134 | switch (ir.reg >> 4) | |
6135 | { | |
6136 | case 0: | |
25ea693b | 6137 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6138 | return -1; |
6139 | break; | |
6140 | case 2: | |
25ea693b | 6141 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6142 | return -1; |
6143 | break; | |
6144 | case 3: | |
0289bdd7 | 6145 | break; |
7ad10968 | 6146 | default: |
25ea693b | 6147 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6148 | return -1; |
6149 | break; | |
6150 | } | |
6151 | break; | |
6152 | default: | |
6153 | switch (ir.reg >> 4) | |
6154 | { | |
6155 | case 0: | |
25ea693b | 6156 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6157 | return -1; |
6158 | if (3 == (ir.reg & 7)) | |
6159 | { | |
6160 | /* For fstp m32fp. */ | |
6161 | if (i386_record_floats (gdbarch, &ir, | |
6162 | I386_SAVE_FPU_REGS)) | |
6163 | return -1; | |
6164 | } | |
6165 | break; | |
7ad10968 | 6166 | case 1: |
25ea693b | 6167 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6168 | return -1; |
0289bdd7 MS |
6169 | if ((3 == (ir.reg & 7)) |
6170 | || (5 == (ir.reg & 7)) | |
6171 | || (7 == (ir.reg & 7))) | |
6172 | { | |
6173 | /* For fstp insn. */ | |
6174 | if (i386_record_floats (gdbarch, &ir, | |
6175 | I386_SAVE_FPU_REGS)) | |
6176 | return -1; | |
6177 | } | |
7ad10968 HZ |
6178 | break; |
6179 | case 2: | |
25ea693b | 6180 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6181 | return -1; |
0289bdd7 MS |
6182 | if (3 == (ir.reg & 7)) |
6183 | { | |
6184 | /* For fstp m64fp. */ | |
6185 | if (i386_record_floats (gdbarch, &ir, | |
6186 | I386_SAVE_FPU_REGS)) | |
6187 | return -1; | |
6188 | } | |
7ad10968 HZ |
6189 | break; |
6190 | case 3: | |
0289bdd7 MS |
6191 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6192 | { | |
6193 | /* For fistp, fbld, fild, fbstp. */ | |
6194 | if (i386_record_floats (gdbarch, &ir, | |
6195 | I386_SAVE_FPU_REGS)) | |
6196 | return -1; | |
6197 | } | |
6198 | /* Fall through */ | |
7ad10968 | 6199 | default: |
25ea693b | 6200 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6201 | return -1; |
6202 | break; | |
6203 | } | |
6204 | break; | |
6205 | } | |
6206 | break; | |
6207 | case 0x0c: | |
0289bdd7 MS |
6208 | /* Insn fldenv. */ |
6209 | if (i386_record_floats (gdbarch, &ir, | |
6210 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6211 | return -1; | |
6212 | break; | |
7ad10968 | 6213 | case 0x0d: |
0289bdd7 MS |
6214 | /* Insn fldcw. */ |
6215 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6216 | return -1; | |
6217 | break; | |
7ad10968 | 6218 | case 0x2c: |
0289bdd7 MS |
6219 | /* Insn frstor. */ |
6220 | if (i386_record_floats (gdbarch, &ir, | |
6221 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6222 | return -1; | |
7ad10968 HZ |
6223 | break; |
6224 | case 0x0e: | |
6225 | if (ir.dflag) | |
6226 | { | |
25ea693b | 6227 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6228 | return -1; |
6229 | } | |
6230 | else | |
6231 | { | |
25ea693b | 6232 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6233 | return -1; |
6234 | } | |
6235 | break; | |
6236 | case 0x0f: | |
6237 | case 0x2f: | |
25ea693b | 6238 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6239 | return -1; |
0289bdd7 MS |
6240 | /* Insn fstp, fbstp. */ |
6241 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6242 | return -1; | |
7ad10968 HZ |
6243 | break; |
6244 | case 0x1f: | |
6245 | case 0x3e: | |
25ea693b | 6246 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6247 | return -1; |
6248 | break; | |
6249 | case 0x2e: | |
6250 | if (ir.dflag) | |
6251 | { | |
25ea693b | 6252 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6253 | return -1; |
955db0c0 | 6254 | addr64 += 28; |
7ad10968 HZ |
6255 | } |
6256 | else | |
6257 | { | |
25ea693b | 6258 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6259 | return -1; |
955db0c0 | 6260 | addr64 += 14; |
7ad10968 | 6261 | } |
25ea693b | 6262 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6263 | return -1; |
0289bdd7 MS |
6264 | /* Insn fsave. */ |
6265 | if (i386_record_floats (gdbarch, &ir, | |
6266 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6267 | return -1; | |
7ad10968 HZ |
6268 | break; |
6269 | case 0x3f: | |
25ea693b | 6270 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6271 | return -1; |
0289bdd7 MS |
6272 | /* Insn fistp. */ |
6273 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6274 | return -1; | |
7ad10968 HZ |
6275 | break; |
6276 | default: | |
6277 | ir.addr -= 2; | |
6278 | opcode = opcode << 8 | ir.modrm; | |
6279 | goto no_support; | |
6280 | break; | |
6281 | } | |
6282 | } | |
0289bdd7 MS |
6283 | /* Opcode is an extension of modR/M byte. */ |
6284 | else | |
6285 | { | |
6286 | switch (opcode) | |
6287 | { | |
6288 | case 0xd8: | |
6289 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6290 | return -1; | |
6291 | break; | |
6292 | case 0xd9: | |
6293 | if (0x0c == (ir.modrm >> 4)) | |
6294 | { | |
6295 | if ((ir.modrm & 0x0f) <= 7) | |
6296 | { | |
6297 | if (i386_record_floats (gdbarch, &ir, | |
6298 | I386_SAVE_FPU_REGS)) | |
6299 | return -1; | |
6300 | } | |
6301 | else | |
6302 | { | |
6303 | if (i386_record_floats (gdbarch, &ir, | |
6304 | I387_ST0_REGNUM (tdep))) | |
6305 | return -1; | |
6306 | /* If only st(0) is changing, then we have already | |
6307 | recorded. */ | |
6308 | if ((ir.modrm & 0x0f) - 0x08) | |
6309 | { | |
6310 | if (i386_record_floats (gdbarch, &ir, | |
6311 | I387_ST0_REGNUM (tdep) + | |
6312 | ((ir.modrm & 0x0f) - 0x08))) | |
6313 | return -1; | |
6314 | } | |
6315 | } | |
6316 | } | |
6317 | else | |
6318 | { | |
6319 | switch (ir.modrm) | |
6320 | { | |
6321 | case 0xe0: | |
6322 | case 0xe1: | |
6323 | case 0xf0: | |
6324 | case 0xf5: | |
6325 | case 0xf8: | |
6326 | case 0xfa: | |
6327 | case 0xfc: | |
6328 | case 0xfe: | |
6329 | case 0xff: | |
6330 | if (i386_record_floats (gdbarch, &ir, | |
6331 | I387_ST0_REGNUM (tdep))) | |
6332 | return -1; | |
6333 | break; | |
6334 | case 0xf1: | |
6335 | case 0xf2: | |
6336 | case 0xf3: | |
6337 | case 0xf4: | |
6338 | case 0xf6: | |
6339 | case 0xf7: | |
6340 | case 0xe8: | |
6341 | case 0xe9: | |
6342 | case 0xea: | |
6343 | case 0xeb: | |
6344 | case 0xec: | |
6345 | case 0xed: | |
6346 | case 0xee: | |
6347 | case 0xf9: | |
6348 | case 0xfb: | |
6349 | if (i386_record_floats (gdbarch, &ir, | |
6350 | I386_SAVE_FPU_REGS)) | |
6351 | return -1; | |
6352 | break; | |
6353 | case 0xfd: | |
6354 | if (i386_record_floats (gdbarch, &ir, | |
6355 | I387_ST0_REGNUM (tdep))) | |
6356 | return -1; | |
6357 | if (i386_record_floats (gdbarch, &ir, | |
6358 | I387_ST0_REGNUM (tdep) + 1)) | |
6359 | return -1; | |
6360 | break; | |
6361 | } | |
6362 | } | |
6363 | break; | |
6364 | case 0xda: | |
6365 | if (0xe9 == ir.modrm) | |
6366 | { | |
6367 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6368 | return -1; | |
6369 | } | |
6370 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6371 | { | |
6372 | if (i386_record_floats (gdbarch, &ir, | |
6373 | I387_ST0_REGNUM (tdep))) | |
6374 | return -1; | |
6375 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6376 | { | |
6377 | if (i386_record_floats (gdbarch, &ir, | |
6378 | I387_ST0_REGNUM (tdep) + | |
6379 | (ir.modrm & 0x0f))) | |
6380 | return -1; | |
6381 | } | |
6382 | else if ((ir.modrm & 0x0f) - 0x08) | |
6383 | { | |
6384 | if (i386_record_floats (gdbarch, &ir, | |
6385 | I387_ST0_REGNUM (tdep) + | |
6386 | ((ir.modrm & 0x0f) - 0x08))) | |
6387 | return -1; | |
6388 | } | |
6389 | } | |
6390 | break; | |
6391 | case 0xdb: | |
6392 | if (0xe3 == ir.modrm) | |
6393 | { | |
6394 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6395 | return -1; | |
6396 | } | |
6397 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6398 | { | |
6399 | if (i386_record_floats (gdbarch, &ir, | |
6400 | I387_ST0_REGNUM (tdep))) | |
6401 | return -1; | |
6402 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6403 | { | |
6404 | if (i386_record_floats (gdbarch, &ir, | |
6405 | I387_ST0_REGNUM (tdep) + | |
6406 | (ir.modrm & 0x0f))) | |
6407 | return -1; | |
6408 | } | |
6409 | else if ((ir.modrm & 0x0f) - 0x08) | |
6410 | { | |
6411 | if (i386_record_floats (gdbarch, &ir, | |
6412 | I387_ST0_REGNUM (tdep) + | |
6413 | ((ir.modrm & 0x0f) - 0x08))) | |
6414 | return -1; | |
6415 | } | |
6416 | } | |
6417 | break; | |
6418 | case 0xdc: | |
6419 | if ((0x0c == ir.modrm >> 4) | |
6420 | || (0x0d == ir.modrm >> 4) | |
6421 | || (0x0f == ir.modrm >> 4)) | |
6422 | { | |
6423 | if ((ir.modrm & 0x0f) <= 7) | |
6424 | { | |
6425 | if (i386_record_floats (gdbarch, &ir, | |
6426 | I387_ST0_REGNUM (tdep) + | |
6427 | (ir.modrm & 0x0f))) | |
6428 | return -1; | |
6429 | } | |
6430 | else | |
6431 | { | |
6432 | if (i386_record_floats (gdbarch, &ir, | |
6433 | I387_ST0_REGNUM (tdep) + | |
6434 | ((ir.modrm & 0x0f) - 0x08))) | |
6435 | return -1; | |
6436 | } | |
6437 | } | |
6438 | break; | |
6439 | case 0xdd: | |
6440 | if (0x0c == ir.modrm >> 4) | |
6441 | { | |
6442 | if (i386_record_floats (gdbarch, &ir, | |
6443 | I387_FTAG_REGNUM (tdep))) | |
6444 | return -1; | |
6445 | } | |
6446 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6447 | { | |
6448 | if ((ir.modrm & 0x0f) <= 7) | |
6449 | { | |
6450 | if (i386_record_floats (gdbarch, &ir, | |
6451 | I387_ST0_REGNUM (tdep) + | |
6452 | (ir.modrm & 0x0f))) | |
6453 | return -1; | |
6454 | } | |
6455 | else | |
6456 | { | |
6457 | if (i386_record_floats (gdbarch, &ir, | |
6458 | I386_SAVE_FPU_REGS)) | |
6459 | return -1; | |
6460 | } | |
6461 | } | |
6462 | break; | |
6463 | case 0xde: | |
6464 | if ((0x0c == ir.modrm >> 4) | |
6465 | || (0x0e == ir.modrm >> 4) | |
6466 | || (0x0f == ir.modrm >> 4) | |
6467 | || (0xd9 == ir.modrm)) | |
6468 | { | |
6469 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6470 | return -1; | |
6471 | } | |
6472 | break; | |
6473 | case 0xdf: | |
6474 | if (0xe0 == ir.modrm) | |
6475 | { | |
25ea693b MM |
6476 | if (record_full_arch_list_add_reg (ir.regcache, |
6477 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6478 | return -1; |
6479 | } | |
6480 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6481 | { | |
6482 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6483 | return -1; | |
6484 | } | |
6485 | break; | |
6486 | } | |
6487 | } | |
7ad10968 | 6488 | break; |
7ad10968 | 6489 | /* string ops */ |
a38bba38 | 6490 | case 0xa4: /* movsS */ |
7ad10968 | 6491 | case 0xa5: |
a38bba38 | 6492 | case 0xaa: /* stosS */ |
7ad10968 | 6493 | case 0xab: |
a38bba38 | 6494 | case 0x6c: /* insS */ |
7ad10968 | 6495 | case 0x6d: |
cf648174 | 6496 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6497 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6498 | &addr); |
6499 | if (addr) | |
cf648174 | 6500 | { |
77d7dc92 HZ |
6501 | ULONGEST es, ds; |
6502 | ||
6503 | if ((opcode & 1) == 0) | |
6504 | ir.ot = OT_BYTE; | |
6505 | else | |
6506 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6507 | regcache_raw_read_unsigned (ir.regcache, |
6508 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6509 | &addr); |
77d7dc92 | 6510 | |
d7877f7e HZ |
6511 | regcache_raw_read_unsigned (ir.regcache, |
6512 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6513 | &es); | |
6514 | regcache_raw_read_unsigned (ir.regcache, | |
6515 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6516 | &ds); | |
6517 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6518 | { |
6519 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6520 | if (record_full_memory_query) |
bb08c432 | 6521 | { |
651ce16a | 6522 | if (yquery (_("\ |
bb08c432 HZ |
6523 | Process record ignores the memory change of instruction at address %s\n\ |
6524 | because it can't get the value of the segment register.\n\ | |
6525 | Do you want to stop the program?"), | |
651ce16a | 6526 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
6527 | return -1; |
6528 | } | |
df61f520 HZ |
6529 | } |
6530 | else | |
6531 | { | |
25ea693b | 6532 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6533 | return -1; |
77d7dc92 HZ |
6534 | } |
6535 | ||
6536 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6537 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6538 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6539 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6540 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6541 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6542 | } |
cf648174 | 6543 | break; |
7ad10968 | 6544 | |
a38bba38 | 6545 | case 0xa6: /* cmpsS */ |
cf648174 | 6546 | case 0xa7: |
25ea693b MM |
6547 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6548 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6549 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6550 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6551 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6552 | break; |
6553 | ||
a38bba38 | 6554 | case 0xac: /* lodsS */ |
7ad10968 | 6555 | case 0xad: |
25ea693b MM |
6556 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6557 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6558 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6559 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6560 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6561 | break; |
6562 | ||
a38bba38 | 6563 | case 0xae: /* scasS */ |
7ad10968 | 6564 | case 0xaf: |
25ea693b | 6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6566 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6567 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6568 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6569 | break; |
6570 | ||
a38bba38 | 6571 | case 0x6e: /* outsS */ |
cf648174 | 6572 | case 0x6f: |
25ea693b | 6573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6574 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6575 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6576 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6577 | break; |
6578 | ||
a38bba38 | 6579 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6580 | case 0xe5: |
6581 | case 0xec: | |
6582 | case 0xed: | |
25ea693b MM |
6583 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6584 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6585 | break; |
6586 | ||
6587 | case 0xe6: | |
6588 | case 0xe7: | |
6589 | case 0xee: | |
6590 | case 0xef: | |
6591 | break; | |
6592 | ||
6593 | /* control */ | |
a38bba38 MS |
6594 | case 0xc2: /* ret im */ |
6595 | case 0xc3: /* ret */ | |
25ea693b MM |
6596 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6597 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6598 | break; |
6599 | ||
a38bba38 MS |
6600 | case 0xca: /* lret im */ |
6601 | case 0xcb: /* lret */ | |
6602 | case 0xcf: /* iret */ | |
25ea693b MM |
6603 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6604 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6605 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6606 | break; |
6607 | ||
a38bba38 | 6608 | case 0xe8: /* call im */ |
cf648174 HZ |
6609 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6610 | ir.dflag = 2; | |
6611 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6612 | return -1; | |
7ad10968 HZ |
6613 | break; |
6614 | ||
a38bba38 | 6615 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6616 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6617 | { | |
6618 | ir.addr -= 1; | |
6619 | goto no_support; | |
6620 | } | |
25ea693b | 6621 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6622 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6623 | return -1; | |
7ad10968 HZ |
6624 | break; |
6625 | ||
a38bba38 MS |
6626 | case 0xe9: /* jmp im */ |
6627 | case 0xea: /* ljmp im */ | |
6628 | case 0xeb: /* jmp Jb */ | |
6629 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6630 | case 0x71: |
6631 | case 0x72: | |
6632 | case 0x73: | |
6633 | case 0x74: | |
6634 | case 0x75: | |
6635 | case 0x76: | |
6636 | case 0x77: | |
6637 | case 0x78: | |
6638 | case 0x79: | |
6639 | case 0x7a: | |
6640 | case 0x7b: | |
6641 | case 0x7c: | |
6642 | case 0x7d: | |
6643 | case 0x7e: | |
6644 | case 0x7f: | |
a38bba38 | 6645 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6646 | case 0x0f81: |
6647 | case 0x0f82: | |
6648 | case 0x0f83: | |
6649 | case 0x0f84: | |
6650 | case 0x0f85: | |
6651 | case 0x0f86: | |
6652 | case 0x0f87: | |
6653 | case 0x0f88: | |
6654 | case 0x0f89: | |
6655 | case 0x0f8a: | |
6656 | case 0x0f8b: | |
6657 | case 0x0f8c: | |
6658 | case 0x0f8d: | |
6659 | case 0x0f8e: | |
6660 | case 0x0f8f: | |
6661 | break; | |
6662 | ||
a38bba38 | 6663 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6664 | case 0x0f91: |
6665 | case 0x0f92: | |
6666 | case 0x0f93: | |
6667 | case 0x0f94: | |
6668 | case 0x0f95: | |
6669 | case 0x0f96: | |
6670 | case 0x0f97: | |
6671 | case 0x0f98: | |
6672 | case 0x0f99: | |
6673 | case 0x0f9a: | |
6674 | case 0x0f9b: | |
6675 | case 0x0f9c: | |
6676 | case 0x0f9d: | |
6677 | case 0x0f9e: | |
6678 | case 0x0f9f: | |
25ea693b | 6679 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6680 | ir.ot = OT_BYTE; |
6681 | if (i386_record_modrm (&ir)) | |
6682 | return -1; | |
6683 | if (ir.mod == 3) | |
25ea693b MM |
6684 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6685 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6686 | else |
6687 | { | |
6688 | if (i386_record_lea_modrm (&ir)) | |
6689 | return -1; | |
6690 | } | |
6691 | break; | |
6692 | ||
a38bba38 | 6693 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6694 | case 0x0f41: |
6695 | case 0x0f42: | |
6696 | case 0x0f43: | |
6697 | case 0x0f44: | |
6698 | case 0x0f45: | |
6699 | case 0x0f46: | |
6700 | case 0x0f47: | |
6701 | case 0x0f48: | |
6702 | case 0x0f49: | |
6703 | case 0x0f4a: | |
6704 | case 0x0f4b: | |
6705 | case 0x0f4c: | |
6706 | case 0x0f4d: | |
6707 | case 0x0f4e: | |
6708 | case 0x0f4f: | |
6709 | if (i386_record_modrm (&ir)) | |
6710 | return -1; | |
cf648174 | 6711 | ir.reg |= rex_r; |
7ad10968 HZ |
6712 | if (ir.dflag == OT_BYTE) |
6713 | ir.reg &= 0x3; | |
25ea693b | 6714 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6715 | break; |
6716 | ||
6717 | /* flags */ | |
a38bba38 | 6718 | case 0x9c: /* pushf */ |
25ea693b | 6719 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6720 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6721 | ir.dflag = 2; | |
6722 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6723 | return -1; | |
7ad10968 HZ |
6724 | break; |
6725 | ||
a38bba38 | 6726 | case 0x9d: /* popf */ |
25ea693b MM |
6727 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6728 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6729 | break; |
6730 | ||
a38bba38 | 6731 | case 0x9e: /* sahf */ |
cf648174 HZ |
6732 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6733 | { | |
6734 | ir.addr -= 1; | |
6735 | goto no_support; | |
6736 | } | |
d3f323f3 | 6737 | /* FALLTHROUGH */ |
a38bba38 MS |
6738 | case 0xf5: /* cmc */ |
6739 | case 0xf8: /* clc */ | |
6740 | case 0xf9: /* stc */ | |
6741 | case 0xfc: /* cld */ | |
6742 | case 0xfd: /* std */ | |
25ea693b | 6743 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6744 | break; |
6745 | ||
a38bba38 | 6746 | case 0x9f: /* lahf */ |
cf648174 HZ |
6747 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6748 | { | |
6749 | ir.addr -= 1; | |
6750 | goto no_support; | |
6751 | } | |
25ea693b MM |
6752 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6753 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6754 | break; |
6755 | ||
6756 | /* bit operations */ | |
a38bba38 | 6757 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6758 | ir.ot = ir.dflag + OT_WORD; |
6759 | if (i386_record_modrm (&ir)) | |
6760 | return -1; | |
6761 | if (ir.reg < 4) | |
6762 | { | |
cf648174 | 6763 | ir.addr -= 2; |
7ad10968 HZ |
6764 | opcode = opcode << 8 | ir.modrm; |
6765 | goto no_support; | |
6766 | } | |
cf648174 | 6767 | if (ir.reg != 4) |
7ad10968 | 6768 | { |
cf648174 | 6769 | if (ir.mod == 3) |
25ea693b | 6770 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6771 | else |
6772 | { | |
cf648174 | 6773 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6774 | return -1; |
6775 | } | |
6776 | } | |
25ea693b | 6777 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6778 | break; |
6779 | ||
a38bba38 | 6780 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6781 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6782 | break; |
6783 | ||
a38bba38 MS |
6784 | case 0x0fab: /* bts */ |
6785 | case 0x0fb3: /* btr */ | |
6786 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6787 | ir.ot = ir.dflag + OT_WORD; |
6788 | if (i386_record_modrm (&ir)) | |
6789 | return -1; | |
6790 | if (ir.mod == 3) | |
25ea693b | 6791 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6792 | else |
6793 | { | |
955db0c0 MS |
6794 | uint64_t addr64; |
6795 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6796 | return -1; |
6797 | regcache_raw_read_unsigned (ir.regcache, | |
6798 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6799 | &addr); |
cf648174 HZ |
6800 | switch (ir.dflag) |
6801 | { | |
6802 | case 0: | |
648d0c8b | 6803 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6804 | break; |
6805 | case 1: | |
648d0c8b | 6806 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6807 | break; |
6808 | case 2: | |
648d0c8b | 6809 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6810 | break; |
6811 | } | |
25ea693b | 6812 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6813 | return -1; |
6814 | if (i386_record_lea_modrm (&ir)) | |
6815 | return -1; | |
6816 | } | |
25ea693b | 6817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6818 | break; |
6819 | ||
a38bba38 MS |
6820 | case 0x0fbc: /* bsf */ |
6821 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6822 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6823 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6824 | break; |
6825 | ||
6826 | /* bcd */ | |
a38bba38 MS |
6827 | case 0x27: /* daa */ |
6828 | case 0x2f: /* das */ | |
6829 | case 0x37: /* aaa */ | |
6830 | case 0x3f: /* aas */ | |
6831 | case 0xd4: /* aam */ | |
6832 | case 0xd5: /* aad */ | |
cf648174 HZ |
6833 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6834 | { | |
6835 | ir.addr -= 1; | |
6836 | goto no_support; | |
6837 | } | |
25ea693b MM |
6838 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6839 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6840 | break; |
6841 | ||
6842 | /* misc */ | |
a38bba38 | 6843 | case 0x90: /* nop */ |
7ad10968 HZ |
6844 | if (prefixes & PREFIX_LOCK) |
6845 | { | |
6846 | ir.addr -= 1; | |
6847 | goto no_support; | |
6848 | } | |
6849 | break; | |
6850 | ||
a38bba38 | 6851 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6852 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6853 | return -1; | |
425b824a | 6854 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6855 | ir.addr++; |
6856 | goto reswitch; | |
7ad10968 HZ |
6857 | break; |
6858 | ||
7ad10968 | 6859 | /* XXX */ |
a38bba38 | 6860 | case 0xcc: /* int3 */ |
a3c4230a | 6861 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6862 | "int3.\n")); |
6863 | ir.addr -= 1; | |
6864 | goto no_support; | |
6865 | break; | |
6866 | ||
7ad10968 | 6867 | /* XXX */ |
a38bba38 | 6868 | case 0xcd: /* int */ |
7ad10968 HZ |
6869 | { |
6870 | int ret; | |
425b824a | 6871 | uint8_t interrupt; |
4ffa4fc7 PA |
6872 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6873 | return -1; | |
7ad10968 | 6874 | ir.addr++; |
425b824a | 6875 | if (interrupt != 0x80 |
a3c4230a | 6876 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6877 | { |
a3c4230a | 6878 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6879 | "instruction int 0x%02x.\n"), |
425b824a | 6880 | interrupt); |
7ad10968 HZ |
6881 | ir.addr -= 2; |
6882 | goto no_support; | |
6883 | } | |
a3c4230a | 6884 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6885 | if (ret) |
6886 | return ret; | |
6887 | } | |
6888 | break; | |
6889 | ||
7ad10968 | 6890 | /* XXX */ |
a38bba38 | 6891 | case 0xce: /* into */ |
a3c4230a | 6892 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6893 | "instruction into.\n")); |
6894 | ir.addr -= 1; | |
6895 | goto no_support; | |
6896 | break; | |
6897 | ||
a38bba38 MS |
6898 | case 0xfa: /* cli */ |
6899 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6900 | break; |
6901 | ||
a38bba38 | 6902 | case 0x62: /* bound */ |
a3c4230a | 6903 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6904 | "instruction bound.\n")); |
6905 | ir.addr -= 1; | |
6906 | goto no_support; | |
6907 | break; | |
6908 | ||
a38bba38 | 6909 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6910 | case 0x0fc9: |
6911 | case 0x0fca: | |
6912 | case 0x0fcb: | |
6913 | case 0x0fcc: | |
6914 | case 0x0fcd: | |
6915 | case 0x0fce: | |
6916 | case 0x0fcf: | |
25ea693b | 6917 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6918 | break; |
6919 | ||
a38bba38 | 6920 | case 0xd6: /* salc */ |
cf648174 HZ |
6921 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6922 | { | |
6923 | ir.addr -= 1; | |
6924 | goto no_support; | |
6925 | } | |
25ea693b MM |
6926 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6927 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6928 | break; |
6929 | ||
a38bba38 MS |
6930 | case 0xe0: /* loopnz */ |
6931 | case 0xe1: /* loopz */ | |
6932 | case 0xe2: /* loop */ | |
6933 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6934 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6935 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6936 | break; |
6937 | ||
a38bba38 | 6938 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6939 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6940 | "instruction wrmsr.\n")); |
6941 | ir.addr -= 2; | |
6942 | goto no_support; | |
6943 | break; | |
6944 | ||
a38bba38 | 6945 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6946 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6947 | "instruction rdmsr.\n")); |
6948 | ir.addr -= 2; | |
6949 | goto no_support; | |
6950 | break; | |
6951 | ||
a38bba38 | 6952 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6953 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6954 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6955 | break; |
6956 | ||
a38bba38 | 6957 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6958 | { |
6959 | int ret; | |
cf648174 HZ |
6960 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6961 | { | |
6962 | ir.addr -= 2; | |
6963 | goto no_support; | |
6964 | } | |
a3c4230a | 6965 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6966 | { |
a3c4230a | 6967 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6968 | "instruction sysenter.\n")); |
6969 | ir.addr -= 2; | |
6970 | goto no_support; | |
6971 | } | |
a3c4230a | 6972 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6973 | if (ret) |
6974 | return ret; | |
6975 | } | |
6976 | break; | |
6977 | ||
a38bba38 | 6978 | case 0x0f35: /* sysexit */ |
a3c4230a | 6979 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6980 | "instruction sysexit.\n")); |
6981 | ir.addr -= 2; | |
6982 | goto no_support; | |
6983 | break; | |
6984 | ||
a38bba38 | 6985 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6986 | { |
6987 | int ret; | |
a3c4230a | 6988 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6989 | { |
a3c4230a | 6990 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6991 | "instruction syscall.\n")); |
6992 | ir.addr -= 2; | |
6993 | goto no_support; | |
6994 | } | |
a3c4230a | 6995 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6996 | if (ret) |
6997 | return ret; | |
6998 | } | |
6999 | break; | |
7000 | ||
a38bba38 | 7001 | case 0x0f07: /* sysret */ |
a3c4230a | 7002 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
7003 | "instruction sysret.\n")); |
7004 | ir.addr -= 2; | |
7005 | goto no_support; | |
7006 | break; | |
7007 | ||
a38bba38 | 7008 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
7009 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7010 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7011 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7012 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
7013 | break; |
7014 | ||
a38bba38 | 7015 | case 0xf4: /* hlt */ |
a3c4230a | 7016 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
7017 | "instruction hlt.\n")); |
7018 | ir.addr -= 1; | |
7019 | goto no_support; | |
7020 | break; | |
7021 | ||
7022 | case 0x0f00: | |
7023 | if (i386_record_modrm (&ir)) | |
7024 | return -1; | |
7025 | switch (ir.reg) | |
7026 | { | |
a38bba38 MS |
7027 | case 0: /* sldt */ |
7028 | case 1: /* str */ | |
7ad10968 | 7029 | if (ir.mod == 3) |
25ea693b | 7030 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7031 | else |
7032 | { | |
7033 | ir.ot = OT_WORD; | |
7034 | if (i386_record_lea_modrm (&ir)) | |
7035 | return -1; | |
7036 | } | |
7037 | break; | |
a38bba38 MS |
7038 | case 2: /* lldt */ |
7039 | case 3: /* ltr */ | |
7ad10968 | 7040 | break; |
a38bba38 MS |
7041 | case 4: /* verr */ |
7042 | case 5: /* verw */ | |
25ea693b | 7043 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7044 | break; |
7045 | default: | |
7046 | ir.addr -= 3; | |
7047 | opcode = opcode << 8 | ir.modrm; | |
7048 | goto no_support; | |
7049 | break; | |
7050 | } | |
7051 | break; | |
7052 | ||
7053 | case 0x0f01: | |
7054 | if (i386_record_modrm (&ir)) | |
7055 | return -1; | |
7056 | switch (ir.reg) | |
7057 | { | |
a38bba38 | 7058 | case 0: /* sgdt */ |
7ad10968 | 7059 | { |
955db0c0 | 7060 | uint64_t addr64; |
7ad10968 HZ |
7061 | |
7062 | if (ir.mod == 3) | |
7063 | { | |
7064 | ir.addr -= 3; | |
7065 | opcode = opcode << 8 | ir.modrm; | |
7066 | goto no_support; | |
7067 | } | |
d7877f7e | 7068 | if (ir.override >= 0) |
7ad10968 | 7069 | { |
25ea693b | 7070 | if (record_full_memory_query) |
bb08c432 | 7071 | { |
651ce16a | 7072 | if (yquery (_("\ |
bb08c432 HZ |
7073 | Process record ignores the memory change of instruction at address %s\n\ |
7074 | because it can't get the value of the segment register.\n\ | |
7075 | Do you want to stop the program?"), | |
651ce16a PA |
7076 | paddress (gdbarch, ir.orig_addr))) |
7077 | return -1; | |
bb08c432 | 7078 | } |
7ad10968 HZ |
7079 | } |
7080 | else | |
7081 | { | |
955db0c0 | 7082 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7083 | return -1; |
25ea693b | 7084 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7085 | return -1; |
955db0c0 | 7086 | addr64 += 2; |
cf648174 HZ |
7087 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7088 | { | |
25ea693b | 7089 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7090 | return -1; |
7091 | } | |
7092 | else | |
7093 | { | |
25ea693b | 7094 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7095 | return -1; |
7096 | } | |
7ad10968 HZ |
7097 | } |
7098 | } | |
7099 | break; | |
7100 | case 1: | |
7101 | if (ir.mod == 3) | |
7102 | { | |
7103 | switch (ir.rm) | |
7104 | { | |
a38bba38 | 7105 | case 0: /* monitor */ |
7ad10968 | 7106 | break; |
a38bba38 | 7107 | case 1: /* mwait */ |
25ea693b | 7108 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7109 | break; |
7110 | default: | |
7111 | ir.addr -= 3; | |
7112 | opcode = opcode << 8 | ir.modrm; | |
7113 | goto no_support; | |
7114 | break; | |
7115 | } | |
7116 | } | |
7117 | else | |
7118 | { | |
7119 | /* sidt */ | |
d7877f7e | 7120 | if (ir.override >= 0) |
7ad10968 | 7121 | { |
25ea693b | 7122 | if (record_full_memory_query) |
bb08c432 | 7123 | { |
651ce16a | 7124 | if (yquery (_("\ |
bb08c432 HZ |
7125 | Process record ignores the memory change of instruction at address %s\n\ |
7126 | because it can't get the value of the segment register.\n\ | |
7127 | Do you want to stop the program?"), | |
651ce16a | 7128 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
7129 | return -1; |
7130 | } | |
7ad10968 HZ |
7131 | } |
7132 | else | |
7133 | { | |
955db0c0 | 7134 | uint64_t addr64; |
7ad10968 | 7135 | |
955db0c0 | 7136 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7137 | return -1; |
25ea693b | 7138 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7139 | return -1; |
955db0c0 | 7140 | addr64 += 2; |
cf648174 HZ |
7141 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7142 | { | |
25ea693b | 7143 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7144 | return -1; |
7145 | } | |
7146 | else | |
7147 | { | |
25ea693b | 7148 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7149 | return -1; |
7150 | } | |
7ad10968 HZ |
7151 | } |
7152 | } | |
7153 | break; | |
a38bba38 | 7154 | case 2: /* lgdt */ |
3800e645 MS |
7155 | if (ir.mod == 3) |
7156 | { | |
7157 | /* xgetbv */ | |
7158 | if (ir.rm == 0) | |
7159 | { | |
25ea693b MM |
7160 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7161 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7162 | break; |
7163 | } | |
7164 | /* xsetbv */ | |
7165 | else if (ir.rm == 1) | |
7166 | break; | |
7167 | } | |
a38bba38 | 7168 | case 3: /* lidt */ |
7ad10968 HZ |
7169 | if (ir.mod == 3) |
7170 | { | |
7171 | ir.addr -= 3; | |
7172 | opcode = opcode << 8 | ir.modrm; | |
7173 | goto no_support; | |
7174 | } | |
7175 | break; | |
a38bba38 | 7176 | case 4: /* smsw */ |
7ad10968 HZ |
7177 | if (ir.mod == 3) |
7178 | { | |
25ea693b | 7179 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7180 | return -1; |
7181 | } | |
7182 | else | |
7183 | { | |
7184 | ir.ot = OT_WORD; | |
7185 | if (i386_record_lea_modrm (&ir)) | |
7186 | return -1; | |
7187 | } | |
25ea693b | 7188 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7189 | break; |
a38bba38 | 7190 | case 6: /* lmsw */ |
25ea693b | 7191 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7192 | break; |
a38bba38 | 7193 | case 7: /* invlpg */ |
cf648174 HZ |
7194 | if (ir.mod == 3) |
7195 | { | |
7196 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7197 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7198 | else |
7199 | { | |
7200 | ir.addr -= 3; | |
7201 | opcode = opcode << 8 | ir.modrm; | |
7202 | goto no_support; | |
7203 | } | |
7204 | } | |
7205 | else | |
25ea693b | 7206 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7207 | break; |
7208 | default: | |
7209 | ir.addr -= 3; | |
7210 | opcode = opcode << 8 | ir.modrm; | |
7211 | goto no_support; | |
7ad10968 HZ |
7212 | break; |
7213 | } | |
7214 | break; | |
7215 | ||
a38bba38 MS |
7216 | case 0x0f08: /* invd */ |
7217 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7218 | break; |
7219 | ||
a38bba38 | 7220 | case 0x63: /* arpl */ |
7ad10968 HZ |
7221 | if (i386_record_modrm (&ir)) |
7222 | return -1; | |
cf648174 HZ |
7223 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7224 | { | |
25ea693b MM |
7225 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7226 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7227 | } |
7ad10968 | 7228 | else |
cf648174 HZ |
7229 | { |
7230 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7231 | if (i386_record_lea_modrm (&ir)) | |
7232 | return -1; | |
7233 | } | |
7234 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7235 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7236 | break; |
7237 | ||
a38bba38 MS |
7238 | case 0x0f02: /* lar */ |
7239 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7240 | if (i386_record_modrm (&ir)) |
7241 | return -1; | |
25ea693b MM |
7242 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7243 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7244 | break; |
7245 | ||
7246 | case 0x0f18: | |
cf648174 HZ |
7247 | if (i386_record_modrm (&ir)) |
7248 | return -1; | |
7249 | if (ir.mod == 3 && ir.reg == 3) | |
7250 | { | |
7251 | ir.addr -= 3; | |
7252 | opcode = opcode << 8 | ir.modrm; | |
7253 | goto no_support; | |
7254 | } | |
7ad10968 HZ |
7255 | break; |
7256 | ||
7ad10968 HZ |
7257 | case 0x0f19: |
7258 | case 0x0f1a: | |
7259 | case 0x0f1b: | |
7260 | case 0x0f1c: | |
7261 | case 0x0f1d: | |
7262 | case 0x0f1e: | |
7263 | case 0x0f1f: | |
a38bba38 | 7264 | /* nop (multi byte) */ |
7ad10968 HZ |
7265 | break; |
7266 | ||
a38bba38 MS |
7267 | case 0x0f20: /* mov reg, crN */ |
7268 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7269 | if (i386_record_modrm (&ir)) |
7270 | return -1; | |
7271 | if ((ir.modrm & 0xc0) != 0xc0) | |
7272 | { | |
cf648174 | 7273 | ir.addr -= 3; |
7ad10968 HZ |
7274 | opcode = opcode << 8 | ir.modrm; |
7275 | goto no_support; | |
7276 | } | |
7277 | switch (ir.reg) | |
7278 | { | |
7279 | case 0: | |
7280 | case 2: | |
7281 | case 3: | |
7282 | case 4: | |
7283 | case 8: | |
7284 | if (opcode & 2) | |
25ea693b | 7285 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7286 | else |
25ea693b | 7287 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7288 | break; |
7289 | default: | |
cf648174 | 7290 | ir.addr -= 3; |
7ad10968 HZ |
7291 | opcode = opcode << 8 | ir.modrm; |
7292 | goto no_support; | |
7293 | break; | |
7294 | } | |
7295 | break; | |
7296 | ||
a38bba38 MS |
7297 | case 0x0f21: /* mov reg, drN */ |
7298 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7299 | if (i386_record_modrm (&ir)) |
7300 | return -1; | |
7301 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7302 | || ir.reg == 5 || ir.reg >= 8) | |
7303 | { | |
cf648174 | 7304 | ir.addr -= 3; |
7ad10968 HZ |
7305 | opcode = opcode << 8 | ir.modrm; |
7306 | goto no_support; | |
7307 | } | |
7308 | if (opcode & 2) | |
25ea693b | 7309 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7310 | else |
25ea693b | 7311 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7312 | break; |
7313 | ||
a38bba38 | 7314 | case 0x0f06: /* clts */ |
25ea693b | 7315 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7316 | break; |
7317 | ||
a3c4230a HZ |
7318 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7319 | ||
7320 | case 0x0f0d: /* 3DNow! prefetch */ | |
7321 | break; | |
7322 | ||
7323 | case 0x0f0e: /* 3DNow! femms */ | |
7324 | case 0x0f77: /* emms */ | |
7325 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7326 | goto no_support; | |
25ea693b | 7327 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7328 | break; |
7329 | ||
7330 | case 0x0f0f: /* 3DNow! data */ | |
7331 | if (i386_record_modrm (&ir)) | |
7332 | return -1; | |
4ffa4fc7 PA |
7333 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7334 | return -1; | |
a3c4230a HZ |
7335 | ir.addr++; |
7336 | switch (opcode8) | |
7337 | { | |
7338 | case 0x0c: /* 3DNow! pi2fw */ | |
7339 | case 0x0d: /* 3DNow! pi2fd */ | |
7340 | case 0x1c: /* 3DNow! pf2iw */ | |
7341 | case 0x1d: /* 3DNow! pf2id */ | |
7342 | case 0x8a: /* 3DNow! pfnacc */ | |
7343 | case 0x8e: /* 3DNow! pfpnacc */ | |
7344 | case 0x90: /* 3DNow! pfcmpge */ | |
7345 | case 0x94: /* 3DNow! pfmin */ | |
7346 | case 0x96: /* 3DNow! pfrcp */ | |
7347 | case 0x97: /* 3DNow! pfrsqrt */ | |
7348 | case 0x9a: /* 3DNow! pfsub */ | |
7349 | case 0x9e: /* 3DNow! pfadd */ | |
7350 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7351 | case 0xa4: /* 3DNow! pfmax */ | |
7352 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7353 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7354 | case 0xaa: /* 3DNow! pfsubr */ | |
7355 | case 0xae: /* 3DNow! pfacc */ | |
7356 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7357 | case 0xb4: /* 3DNow! pfmul */ | |
7358 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7359 | case 0xb7: /* 3DNow! pmulhrw */ | |
7360 | case 0xbb: /* 3DNow! pswapd */ | |
7361 | case 0xbf: /* 3DNow! pavgusb */ | |
7362 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7363 | goto no_support_3dnow_data; | |
25ea693b | 7364 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7365 | break; |
7366 | ||
7367 | default: | |
7368 | no_support_3dnow_data: | |
7369 | opcode = (opcode << 8) | opcode8; | |
7370 | goto no_support; | |
7371 | break; | |
7372 | } | |
7373 | break; | |
7374 | ||
7375 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7376 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7377 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7378 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7379 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7380 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7381 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7382 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7383 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7384 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7385 | break; |
7386 | ||
7387 | case 0x0fae: | |
7388 | if (i386_record_modrm (&ir)) | |
7389 | return -1; | |
7390 | switch(ir.reg) | |
7391 | { | |
7392 | case 0: /* fxsave */ | |
7393 | { | |
7394 | uint64_t tmpu64; | |
7395 | ||
25ea693b | 7396 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7397 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7398 | return -1; | |
25ea693b | 7399 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7400 | return -1; |
7401 | } | |
7402 | break; | |
7403 | ||
7404 | case 1: /* fxrstor */ | |
7405 | { | |
7406 | int i; | |
7407 | ||
25ea693b | 7408 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7409 | |
7410 | for (i = I387_MM0_REGNUM (tdep); | |
7411 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7412 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7413 | |
7414 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7415 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7416 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7417 | |
7418 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7419 | record_full_arch_list_add_reg (ir.regcache, |
7420 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7421 | |
7422 | for (i = I387_ST0_REGNUM (tdep); | |
7423 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7424 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7425 | |
7426 | for (i = I387_FCTRL_REGNUM (tdep); | |
7427 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7428 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7429 | } |
7430 | break; | |
7431 | ||
7432 | case 2: /* ldmxcsr */ | |
7433 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7434 | goto no_support; | |
25ea693b | 7435 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7436 | break; |
7437 | ||
7438 | case 3: /* stmxcsr */ | |
7439 | ir.ot = OT_LONG; | |
7440 | if (i386_record_lea_modrm (&ir)) | |
7441 | return -1; | |
7442 | break; | |
7443 | ||
7444 | case 5: /* lfence */ | |
7445 | case 6: /* mfence */ | |
7446 | case 7: /* sfence clflush */ | |
7447 | break; | |
7448 | ||
7449 | default: | |
7450 | opcode = (opcode << 8) | ir.modrm; | |
7451 | goto no_support; | |
7452 | break; | |
7453 | } | |
7454 | break; | |
7455 | ||
7456 | case 0x0fc3: /* movnti */ | |
7457 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7458 | if (i386_record_modrm (&ir)) | |
7459 | return -1; | |
7460 | if (ir.mod == 3) | |
7461 | goto no_support; | |
7462 | ir.reg |= rex_r; | |
7463 | if (i386_record_lea_modrm (&ir)) | |
7464 | return -1; | |
7465 | break; | |
7466 | ||
7467 | /* Add prefix to opcode. */ | |
7468 | case 0x0f10: | |
7469 | case 0x0f11: | |
7470 | case 0x0f12: | |
7471 | case 0x0f13: | |
7472 | case 0x0f14: | |
7473 | case 0x0f15: | |
7474 | case 0x0f16: | |
7475 | case 0x0f17: | |
7476 | case 0x0f28: | |
7477 | case 0x0f29: | |
7478 | case 0x0f2a: | |
7479 | case 0x0f2b: | |
7480 | case 0x0f2c: | |
7481 | case 0x0f2d: | |
7482 | case 0x0f2e: | |
7483 | case 0x0f2f: | |
7484 | case 0x0f38: | |
7485 | case 0x0f39: | |
7486 | case 0x0f3a: | |
7487 | case 0x0f50: | |
7488 | case 0x0f51: | |
7489 | case 0x0f52: | |
7490 | case 0x0f53: | |
7491 | case 0x0f54: | |
7492 | case 0x0f55: | |
7493 | case 0x0f56: | |
7494 | case 0x0f57: | |
7495 | case 0x0f58: | |
7496 | case 0x0f59: | |
7497 | case 0x0f5a: | |
7498 | case 0x0f5b: | |
7499 | case 0x0f5c: | |
7500 | case 0x0f5d: | |
7501 | case 0x0f5e: | |
7502 | case 0x0f5f: | |
7503 | case 0x0f60: | |
7504 | case 0x0f61: | |
7505 | case 0x0f62: | |
7506 | case 0x0f63: | |
7507 | case 0x0f64: | |
7508 | case 0x0f65: | |
7509 | case 0x0f66: | |
7510 | case 0x0f67: | |
7511 | case 0x0f68: | |
7512 | case 0x0f69: | |
7513 | case 0x0f6a: | |
7514 | case 0x0f6b: | |
7515 | case 0x0f6c: | |
7516 | case 0x0f6d: | |
7517 | case 0x0f6e: | |
7518 | case 0x0f6f: | |
7519 | case 0x0f70: | |
7520 | case 0x0f71: | |
7521 | case 0x0f72: | |
7522 | case 0x0f73: | |
7523 | case 0x0f74: | |
7524 | case 0x0f75: | |
7525 | case 0x0f76: | |
7526 | case 0x0f7c: | |
7527 | case 0x0f7d: | |
7528 | case 0x0f7e: | |
7529 | case 0x0f7f: | |
7530 | case 0x0fb8: | |
7531 | case 0x0fc2: | |
7532 | case 0x0fc4: | |
7533 | case 0x0fc5: | |
7534 | case 0x0fc6: | |
7535 | case 0x0fd0: | |
7536 | case 0x0fd1: | |
7537 | case 0x0fd2: | |
7538 | case 0x0fd3: | |
7539 | case 0x0fd4: | |
7540 | case 0x0fd5: | |
7541 | case 0x0fd6: | |
7542 | case 0x0fd7: | |
7543 | case 0x0fd8: | |
7544 | case 0x0fd9: | |
7545 | case 0x0fda: | |
7546 | case 0x0fdb: | |
7547 | case 0x0fdc: | |
7548 | case 0x0fdd: | |
7549 | case 0x0fde: | |
7550 | case 0x0fdf: | |
7551 | case 0x0fe0: | |
7552 | case 0x0fe1: | |
7553 | case 0x0fe2: | |
7554 | case 0x0fe3: | |
7555 | case 0x0fe4: | |
7556 | case 0x0fe5: | |
7557 | case 0x0fe6: | |
7558 | case 0x0fe7: | |
7559 | case 0x0fe8: | |
7560 | case 0x0fe9: | |
7561 | case 0x0fea: | |
7562 | case 0x0feb: | |
7563 | case 0x0fec: | |
7564 | case 0x0fed: | |
7565 | case 0x0fee: | |
7566 | case 0x0fef: | |
7567 | case 0x0ff0: | |
7568 | case 0x0ff1: | |
7569 | case 0x0ff2: | |
7570 | case 0x0ff3: | |
7571 | case 0x0ff4: | |
7572 | case 0x0ff5: | |
7573 | case 0x0ff6: | |
7574 | case 0x0ff7: | |
7575 | case 0x0ff8: | |
7576 | case 0x0ff9: | |
7577 | case 0x0ffa: | |
7578 | case 0x0ffb: | |
7579 | case 0x0ffc: | |
7580 | case 0x0ffd: | |
7581 | case 0x0ffe: | |
f9fda3f5 L |
7582 | /* Mask out PREFIX_ADDR. */ |
7583 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7584 | { |
7585 | case PREFIX_REPNZ: | |
7586 | opcode |= 0xf20000; | |
7587 | break; | |
7588 | case PREFIX_DATA: | |
7589 | opcode |= 0x660000; | |
7590 | break; | |
7591 | case PREFIX_REPZ: | |
7592 | opcode |= 0xf30000; | |
7593 | break; | |
7594 | } | |
7595 | reswitch_prefix_add: | |
7596 | switch (opcode) | |
7597 | { | |
7598 | case 0x0f38: | |
7599 | case 0x660f38: | |
7600 | case 0xf20f38: | |
7601 | case 0x0f3a: | |
7602 | case 0x660f3a: | |
4ffa4fc7 PA |
7603 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7604 | return -1; | |
a3c4230a HZ |
7605 | ir.addr++; |
7606 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7607 | goto reswitch_prefix_add; | |
7608 | break; | |
7609 | ||
7610 | case 0x0f10: /* movups */ | |
7611 | case 0x660f10: /* movupd */ | |
7612 | case 0xf30f10: /* movss */ | |
7613 | case 0xf20f10: /* movsd */ | |
7614 | case 0x0f12: /* movlps */ | |
7615 | case 0x660f12: /* movlpd */ | |
7616 | case 0xf30f12: /* movsldup */ | |
7617 | case 0xf20f12: /* movddup */ | |
7618 | case 0x0f14: /* unpcklps */ | |
7619 | case 0x660f14: /* unpcklpd */ | |
7620 | case 0x0f15: /* unpckhps */ | |
7621 | case 0x660f15: /* unpckhpd */ | |
7622 | case 0x0f16: /* movhps */ | |
7623 | case 0x660f16: /* movhpd */ | |
7624 | case 0xf30f16: /* movshdup */ | |
7625 | case 0x0f28: /* movaps */ | |
7626 | case 0x660f28: /* movapd */ | |
7627 | case 0x0f2a: /* cvtpi2ps */ | |
7628 | case 0x660f2a: /* cvtpi2pd */ | |
7629 | case 0xf30f2a: /* cvtsi2ss */ | |
7630 | case 0xf20f2a: /* cvtsi2sd */ | |
7631 | case 0x0f2c: /* cvttps2pi */ | |
7632 | case 0x660f2c: /* cvttpd2pi */ | |
7633 | case 0x0f2d: /* cvtps2pi */ | |
7634 | case 0x660f2d: /* cvtpd2pi */ | |
7635 | case 0x660f3800: /* pshufb */ | |
7636 | case 0x660f3801: /* phaddw */ | |
7637 | case 0x660f3802: /* phaddd */ | |
7638 | case 0x660f3803: /* phaddsw */ | |
7639 | case 0x660f3804: /* pmaddubsw */ | |
7640 | case 0x660f3805: /* phsubw */ | |
7641 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7642 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7643 | case 0x660f3808: /* psignb */ |
7644 | case 0x660f3809: /* psignw */ | |
7645 | case 0x660f380a: /* psignd */ | |
7646 | case 0x660f380b: /* pmulhrsw */ | |
7647 | case 0x660f3810: /* pblendvb */ | |
7648 | case 0x660f3814: /* blendvps */ | |
7649 | case 0x660f3815: /* blendvpd */ | |
7650 | case 0x660f381c: /* pabsb */ | |
7651 | case 0x660f381d: /* pabsw */ | |
7652 | case 0x660f381e: /* pabsd */ | |
7653 | case 0x660f3820: /* pmovsxbw */ | |
7654 | case 0x660f3821: /* pmovsxbd */ | |
7655 | case 0x660f3822: /* pmovsxbq */ | |
7656 | case 0x660f3823: /* pmovsxwd */ | |
7657 | case 0x660f3824: /* pmovsxwq */ | |
7658 | case 0x660f3825: /* pmovsxdq */ | |
7659 | case 0x660f3828: /* pmuldq */ | |
7660 | case 0x660f3829: /* pcmpeqq */ | |
7661 | case 0x660f382a: /* movntdqa */ | |
7662 | case 0x660f3a08: /* roundps */ | |
7663 | case 0x660f3a09: /* roundpd */ | |
7664 | case 0x660f3a0a: /* roundss */ | |
7665 | case 0x660f3a0b: /* roundsd */ | |
7666 | case 0x660f3a0c: /* blendps */ | |
7667 | case 0x660f3a0d: /* blendpd */ | |
7668 | case 0x660f3a0e: /* pblendw */ | |
7669 | case 0x660f3a0f: /* palignr */ | |
7670 | case 0x660f3a20: /* pinsrb */ | |
7671 | case 0x660f3a21: /* insertps */ | |
7672 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7673 | case 0x660f3a40: /* dpps */ | |
7674 | case 0x660f3a41: /* dppd */ | |
7675 | case 0x660f3a42: /* mpsadbw */ | |
7676 | case 0x660f3a60: /* pcmpestrm */ | |
7677 | case 0x660f3a61: /* pcmpestri */ | |
7678 | case 0x660f3a62: /* pcmpistrm */ | |
7679 | case 0x660f3a63: /* pcmpistri */ | |
7680 | case 0x0f51: /* sqrtps */ | |
7681 | case 0x660f51: /* sqrtpd */ | |
7682 | case 0xf20f51: /* sqrtsd */ | |
7683 | case 0xf30f51: /* sqrtss */ | |
7684 | case 0x0f52: /* rsqrtps */ | |
7685 | case 0xf30f52: /* rsqrtss */ | |
7686 | case 0x0f53: /* rcpps */ | |
7687 | case 0xf30f53: /* rcpss */ | |
7688 | case 0x0f54: /* andps */ | |
7689 | case 0x660f54: /* andpd */ | |
7690 | case 0x0f55: /* andnps */ | |
7691 | case 0x660f55: /* andnpd */ | |
7692 | case 0x0f56: /* orps */ | |
7693 | case 0x660f56: /* orpd */ | |
7694 | case 0x0f57: /* xorps */ | |
7695 | case 0x660f57: /* xorpd */ | |
7696 | case 0x0f58: /* addps */ | |
7697 | case 0x660f58: /* addpd */ | |
7698 | case 0xf20f58: /* addsd */ | |
7699 | case 0xf30f58: /* addss */ | |
7700 | case 0x0f59: /* mulps */ | |
7701 | case 0x660f59: /* mulpd */ | |
7702 | case 0xf20f59: /* mulsd */ | |
7703 | case 0xf30f59: /* mulss */ | |
7704 | case 0x0f5a: /* cvtps2pd */ | |
7705 | case 0x660f5a: /* cvtpd2ps */ | |
7706 | case 0xf20f5a: /* cvtsd2ss */ | |
7707 | case 0xf30f5a: /* cvtss2sd */ | |
7708 | case 0x0f5b: /* cvtdq2ps */ | |
7709 | case 0x660f5b: /* cvtps2dq */ | |
7710 | case 0xf30f5b: /* cvttps2dq */ | |
7711 | case 0x0f5c: /* subps */ | |
7712 | case 0x660f5c: /* subpd */ | |
7713 | case 0xf20f5c: /* subsd */ | |
7714 | case 0xf30f5c: /* subss */ | |
7715 | case 0x0f5d: /* minps */ | |
7716 | case 0x660f5d: /* minpd */ | |
7717 | case 0xf20f5d: /* minsd */ | |
7718 | case 0xf30f5d: /* minss */ | |
7719 | case 0x0f5e: /* divps */ | |
7720 | case 0x660f5e: /* divpd */ | |
7721 | case 0xf20f5e: /* divsd */ | |
7722 | case 0xf30f5e: /* divss */ | |
7723 | case 0x0f5f: /* maxps */ | |
7724 | case 0x660f5f: /* maxpd */ | |
7725 | case 0xf20f5f: /* maxsd */ | |
7726 | case 0xf30f5f: /* maxss */ | |
7727 | case 0x660f60: /* punpcklbw */ | |
7728 | case 0x660f61: /* punpcklwd */ | |
7729 | case 0x660f62: /* punpckldq */ | |
7730 | case 0x660f63: /* packsswb */ | |
7731 | case 0x660f64: /* pcmpgtb */ | |
7732 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7733 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7734 | case 0x660f67: /* packuswb */ |
7735 | case 0x660f68: /* punpckhbw */ | |
7736 | case 0x660f69: /* punpckhwd */ | |
7737 | case 0x660f6a: /* punpckhdq */ | |
7738 | case 0x660f6b: /* packssdw */ | |
7739 | case 0x660f6c: /* punpcklqdq */ | |
7740 | case 0x660f6d: /* punpckhqdq */ | |
7741 | case 0x660f6e: /* movd */ | |
7742 | case 0x660f6f: /* movdqa */ | |
7743 | case 0xf30f6f: /* movdqu */ | |
7744 | case 0x660f70: /* pshufd */ | |
7745 | case 0xf20f70: /* pshuflw */ | |
7746 | case 0xf30f70: /* pshufhw */ | |
7747 | case 0x660f74: /* pcmpeqb */ | |
7748 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7749 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7750 | case 0x660f7c: /* haddpd */ |
7751 | case 0xf20f7c: /* haddps */ | |
7752 | case 0x660f7d: /* hsubpd */ | |
7753 | case 0xf20f7d: /* hsubps */ | |
7754 | case 0xf30f7e: /* movq */ | |
7755 | case 0x0fc2: /* cmpps */ | |
7756 | case 0x660fc2: /* cmppd */ | |
7757 | case 0xf20fc2: /* cmpsd */ | |
7758 | case 0xf30fc2: /* cmpss */ | |
7759 | case 0x660fc4: /* pinsrw */ | |
7760 | case 0x0fc6: /* shufps */ | |
7761 | case 0x660fc6: /* shufpd */ | |
7762 | case 0x660fd0: /* addsubpd */ | |
7763 | case 0xf20fd0: /* addsubps */ | |
7764 | case 0x660fd1: /* psrlw */ | |
7765 | case 0x660fd2: /* psrld */ | |
7766 | case 0x660fd3: /* psrlq */ | |
7767 | case 0x660fd4: /* paddq */ | |
7768 | case 0x660fd5: /* pmullw */ | |
7769 | case 0xf30fd6: /* movq2dq */ | |
7770 | case 0x660fd8: /* psubusb */ | |
7771 | case 0x660fd9: /* psubusw */ | |
7772 | case 0x660fda: /* pminub */ | |
7773 | case 0x660fdb: /* pand */ | |
7774 | case 0x660fdc: /* paddusb */ | |
7775 | case 0x660fdd: /* paddusw */ | |
7776 | case 0x660fde: /* pmaxub */ | |
7777 | case 0x660fdf: /* pandn */ | |
7778 | case 0x660fe0: /* pavgb */ | |
7779 | case 0x660fe1: /* psraw */ | |
7780 | case 0x660fe2: /* psrad */ | |
7781 | case 0x660fe3: /* pavgw */ | |
7782 | case 0x660fe4: /* pmulhuw */ | |
7783 | case 0x660fe5: /* pmulhw */ | |
7784 | case 0x660fe6: /* cvttpd2dq */ | |
7785 | case 0xf20fe6: /* cvtpd2dq */ | |
7786 | case 0xf30fe6: /* cvtdq2pd */ | |
7787 | case 0x660fe8: /* psubsb */ | |
7788 | case 0x660fe9: /* psubsw */ | |
7789 | case 0x660fea: /* pminsw */ | |
7790 | case 0x660feb: /* por */ | |
7791 | case 0x660fec: /* paddsb */ | |
7792 | case 0x660fed: /* paddsw */ | |
7793 | case 0x660fee: /* pmaxsw */ | |
7794 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7795 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7796 | case 0x660ff1: /* psllw */ |
7797 | case 0x660ff2: /* pslld */ | |
7798 | case 0x660ff3: /* psllq */ | |
7799 | case 0x660ff4: /* pmuludq */ | |
7800 | case 0x660ff5: /* pmaddwd */ | |
7801 | case 0x660ff6: /* psadbw */ | |
7802 | case 0x660ff8: /* psubb */ | |
7803 | case 0x660ff9: /* psubw */ | |
56d2815c | 7804 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7805 | case 0x660ffb: /* psubq */ |
7806 | case 0x660ffc: /* paddb */ | |
7807 | case 0x660ffd: /* paddw */ | |
56d2815c | 7808 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7809 | if (i386_record_modrm (&ir)) |
7810 | return -1; | |
7811 | ir.reg |= rex_r; | |
c131fcee | 7812 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7813 | goto no_support; |
25ea693b MM |
7814 | record_full_arch_list_add_reg (ir.regcache, |
7815 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7816 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7818 | break; |
7819 | ||
7820 | case 0x0f11: /* movups */ | |
7821 | case 0x660f11: /* movupd */ | |
7822 | case 0xf30f11: /* movss */ | |
7823 | case 0xf20f11: /* movsd */ | |
7824 | case 0x0f13: /* movlps */ | |
7825 | case 0x660f13: /* movlpd */ | |
7826 | case 0x0f17: /* movhps */ | |
7827 | case 0x660f17: /* movhpd */ | |
7828 | case 0x0f29: /* movaps */ | |
7829 | case 0x660f29: /* movapd */ | |
7830 | case 0x660f3a14: /* pextrb */ | |
7831 | case 0x660f3a15: /* pextrw */ | |
7832 | case 0x660f3a16: /* pextrd pextrq */ | |
7833 | case 0x660f3a17: /* extractps */ | |
7834 | case 0x660f7f: /* movdqa */ | |
7835 | case 0xf30f7f: /* movdqu */ | |
7836 | if (i386_record_modrm (&ir)) | |
7837 | return -1; | |
7838 | if (ir.mod == 3) | |
7839 | { | |
7840 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7841 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7842 | goto no_support; | |
7843 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7844 | if (!i386_xmm_regnum_p (gdbarch, |
7845 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7846 | goto no_support; |
25ea693b MM |
7847 | record_full_arch_list_add_reg (ir.regcache, |
7848 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7849 | } |
7850 | else | |
7851 | { | |
7852 | switch (opcode) | |
7853 | { | |
7854 | case 0x660f3a14: | |
7855 | ir.ot = OT_BYTE; | |
7856 | break; | |
7857 | case 0x660f3a15: | |
7858 | ir.ot = OT_WORD; | |
7859 | break; | |
7860 | case 0x660f3a16: | |
7861 | ir.ot = OT_LONG; | |
7862 | break; | |
7863 | case 0x660f3a17: | |
7864 | ir.ot = OT_QUAD; | |
7865 | break; | |
7866 | default: | |
7867 | ir.ot = OT_DQUAD; | |
7868 | break; | |
7869 | } | |
7870 | if (i386_record_lea_modrm (&ir)) | |
7871 | return -1; | |
7872 | } | |
7873 | break; | |
7874 | ||
7875 | case 0x0f2b: /* movntps */ | |
7876 | case 0x660f2b: /* movntpd */ | |
7877 | case 0x0fe7: /* movntq */ | |
7878 | case 0x660fe7: /* movntdq */ | |
7879 | if (ir.mod == 3) | |
7880 | goto no_support; | |
7881 | if (opcode == 0x0fe7) | |
7882 | ir.ot = OT_QUAD; | |
7883 | else | |
7884 | ir.ot = OT_DQUAD; | |
7885 | if (i386_record_lea_modrm (&ir)) | |
7886 | return -1; | |
7887 | break; | |
7888 | ||
7889 | case 0xf30f2c: /* cvttss2si */ | |
7890 | case 0xf20f2c: /* cvttsd2si */ | |
7891 | case 0xf30f2d: /* cvtss2si */ | |
7892 | case 0xf20f2d: /* cvtsd2si */ | |
7893 | case 0xf20f38f0: /* crc32 */ | |
7894 | case 0xf20f38f1: /* crc32 */ | |
7895 | case 0x0f50: /* movmskps */ | |
7896 | case 0x660f50: /* movmskpd */ | |
7897 | case 0x0fc5: /* pextrw */ | |
7898 | case 0x660fc5: /* pextrw */ | |
7899 | case 0x0fd7: /* pmovmskb */ | |
7900 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7901 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7902 | break; |
7903 | ||
7904 | case 0x0f3800: /* pshufb */ | |
7905 | case 0x0f3801: /* phaddw */ | |
7906 | case 0x0f3802: /* phaddd */ | |
7907 | case 0x0f3803: /* phaddsw */ | |
7908 | case 0x0f3804: /* pmaddubsw */ | |
7909 | case 0x0f3805: /* phsubw */ | |
7910 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7911 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7912 | case 0x0f3808: /* psignb */ |
7913 | case 0x0f3809: /* psignw */ | |
7914 | case 0x0f380a: /* psignd */ | |
7915 | case 0x0f380b: /* pmulhrsw */ | |
7916 | case 0x0f381c: /* pabsb */ | |
7917 | case 0x0f381d: /* pabsw */ | |
7918 | case 0x0f381e: /* pabsd */ | |
7919 | case 0x0f382b: /* packusdw */ | |
7920 | case 0x0f3830: /* pmovzxbw */ | |
7921 | case 0x0f3831: /* pmovzxbd */ | |
7922 | case 0x0f3832: /* pmovzxbq */ | |
7923 | case 0x0f3833: /* pmovzxwd */ | |
7924 | case 0x0f3834: /* pmovzxwq */ | |
7925 | case 0x0f3835: /* pmovzxdq */ | |
7926 | case 0x0f3837: /* pcmpgtq */ | |
7927 | case 0x0f3838: /* pminsb */ | |
7928 | case 0x0f3839: /* pminsd */ | |
7929 | case 0x0f383a: /* pminuw */ | |
7930 | case 0x0f383b: /* pminud */ | |
7931 | case 0x0f383c: /* pmaxsb */ | |
7932 | case 0x0f383d: /* pmaxsd */ | |
7933 | case 0x0f383e: /* pmaxuw */ | |
7934 | case 0x0f383f: /* pmaxud */ | |
7935 | case 0x0f3840: /* pmulld */ | |
7936 | case 0x0f3841: /* phminposuw */ | |
7937 | case 0x0f3a0f: /* palignr */ | |
7938 | case 0x0f60: /* punpcklbw */ | |
7939 | case 0x0f61: /* punpcklwd */ | |
7940 | case 0x0f62: /* punpckldq */ | |
7941 | case 0x0f63: /* packsswb */ | |
7942 | case 0x0f64: /* pcmpgtb */ | |
7943 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7944 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7945 | case 0x0f67: /* packuswb */ |
7946 | case 0x0f68: /* punpckhbw */ | |
7947 | case 0x0f69: /* punpckhwd */ | |
7948 | case 0x0f6a: /* punpckhdq */ | |
7949 | case 0x0f6b: /* packssdw */ | |
7950 | case 0x0f6e: /* movd */ | |
7951 | case 0x0f6f: /* movq */ | |
7952 | case 0x0f70: /* pshufw */ | |
7953 | case 0x0f74: /* pcmpeqb */ | |
7954 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7955 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7956 | case 0x0fc4: /* pinsrw */ |
7957 | case 0x0fd1: /* psrlw */ | |
7958 | case 0x0fd2: /* psrld */ | |
7959 | case 0x0fd3: /* psrlq */ | |
7960 | case 0x0fd4: /* paddq */ | |
7961 | case 0x0fd5: /* pmullw */ | |
7962 | case 0xf20fd6: /* movdq2q */ | |
7963 | case 0x0fd8: /* psubusb */ | |
7964 | case 0x0fd9: /* psubusw */ | |
7965 | case 0x0fda: /* pminub */ | |
7966 | case 0x0fdb: /* pand */ | |
7967 | case 0x0fdc: /* paddusb */ | |
7968 | case 0x0fdd: /* paddusw */ | |
7969 | case 0x0fde: /* pmaxub */ | |
7970 | case 0x0fdf: /* pandn */ | |
7971 | case 0x0fe0: /* pavgb */ | |
7972 | case 0x0fe1: /* psraw */ | |
7973 | case 0x0fe2: /* psrad */ | |
7974 | case 0x0fe3: /* pavgw */ | |
7975 | case 0x0fe4: /* pmulhuw */ | |
7976 | case 0x0fe5: /* pmulhw */ | |
7977 | case 0x0fe8: /* psubsb */ | |
7978 | case 0x0fe9: /* psubsw */ | |
7979 | case 0x0fea: /* pminsw */ | |
7980 | case 0x0feb: /* por */ | |
7981 | case 0x0fec: /* paddsb */ | |
7982 | case 0x0fed: /* paddsw */ | |
7983 | case 0x0fee: /* pmaxsw */ | |
7984 | case 0x0fef: /* pxor */ | |
7985 | case 0x0ff1: /* psllw */ | |
7986 | case 0x0ff2: /* pslld */ | |
7987 | case 0x0ff3: /* psllq */ | |
7988 | case 0x0ff4: /* pmuludq */ | |
7989 | case 0x0ff5: /* pmaddwd */ | |
7990 | case 0x0ff6: /* psadbw */ | |
7991 | case 0x0ff8: /* psubb */ | |
7992 | case 0x0ff9: /* psubw */ | |
56d2815c | 7993 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7994 | case 0x0ffb: /* psubq */ |
7995 | case 0x0ffc: /* paddb */ | |
7996 | case 0x0ffd: /* paddw */ | |
56d2815c | 7997 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7998 | if (i386_record_modrm (&ir)) |
7999 | return -1; | |
8000 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
8001 | goto no_support; | |
25ea693b MM |
8002 | record_full_arch_list_add_reg (ir.regcache, |
8003 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
8004 | break; |
8005 | ||
8006 | case 0x0f71: /* psllw */ | |
8007 | case 0x0f72: /* pslld */ | |
8008 | case 0x0f73: /* psllq */ | |
8009 | if (i386_record_modrm (&ir)) | |
8010 | return -1; | |
8011 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8012 | goto no_support; | |
25ea693b MM |
8013 | record_full_arch_list_add_reg (ir.regcache, |
8014 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8015 | break; |
8016 | ||
8017 | case 0x660f71: /* psllw */ | |
8018 | case 0x660f72: /* pslld */ | |
8019 | case 0x660f73: /* psllq */ | |
8020 | if (i386_record_modrm (&ir)) | |
8021 | return -1; | |
8022 | ir.rm |= ir.rex_b; | |
c131fcee | 8023 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 8024 | goto no_support; |
25ea693b MM |
8025 | record_full_arch_list_add_reg (ir.regcache, |
8026 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8027 | break; |
8028 | ||
8029 | case 0x0f7e: /* movd */ | |
8030 | case 0x660f7e: /* movd */ | |
8031 | if (i386_record_modrm (&ir)) | |
8032 | return -1; | |
8033 | if (ir.mod == 3) | |
25ea693b | 8034 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
8035 | else |
8036 | { | |
8037 | if (ir.dflag == 2) | |
8038 | ir.ot = OT_QUAD; | |
8039 | else | |
8040 | ir.ot = OT_LONG; | |
8041 | if (i386_record_lea_modrm (&ir)) | |
8042 | return -1; | |
8043 | } | |
8044 | break; | |
8045 | ||
8046 | case 0x0f7f: /* movq */ | |
8047 | if (i386_record_modrm (&ir)) | |
8048 | return -1; | |
8049 | if (ir.mod == 3) | |
8050 | { | |
8051 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8052 | goto no_support; | |
25ea693b MM |
8053 | record_full_arch_list_add_reg (ir.regcache, |
8054 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8055 | } |
8056 | else | |
8057 | { | |
8058 | ir.ot = OT_QUAD; | |
8059 | if (i386_record_lea_modrm (&ir)) | |
8060 | return -1; | |
8061 | } | |
8062 | break; | |
8063 | ||
8064 | case 0xf30fb8: /* popcnt */ | |
8065 | if (i386_record_modrm (&ir)) | |
8066 | return -1; | |
25ea693b MM |
8067 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8068 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
8069 | break; |
8070 | ||
8071 | case 0x660fd6: /* movq */ | |
8072 | if (i386_record_modrm (&ir)) | |
8073 | return -1; | |
8074 | if (ir.mod == 3) | |
8075 | { | |
8076 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
8077 | if (!i386_xmm_regnum_p (gdbarch, |
8078 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 8079 | goto no_support; |
25ea693b MM |
8080 | record_full_arch_list_add_reg (ir.regcache, |
8081 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8082 | } |
8083 | else | |
8084 | { | |
8085 | ir.ot = OT_QUAD; | |
8086 | if (i386_record_lea_modrm (&ir)) | |
8087 | return -1; | |
8088 | } | |
8089 | break; | |
8090 | ||
8091 | case 0x660f3817: /* ptest */ | |
8092 | case 0x0f2e: /* ucomiss */ | |
8093 | case 0x660f2e: /* ucomisd */ | |
8094 | case 0x0f2f: /* comiss */ | |
8095 | case 0x660f2f: /* comisd */ | |
25ea693b | 8096 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8097 | break; |
8098 | ||
8099 | case 0x0ff7: /* maskmovq */ | |
8100 | regcache_raw_read_unsigned (ir.regcache, | |
8101 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8102 | &addr); | |
25ea693b | 8103 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8104 | return -1; |
8105 | break; | |
8106 | ||
8107 | case 0x660ff7: /* maskmovdqu */ | |
8108 | regcache_raw_read_unsigned (ir.regcache, | |
8109 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8110 | &addr); | |
25ea693b | 8111 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8112 | return -1; |
8113 | break; | |
8114 | ||
8115 | default: | |
8116 | goto no_support; | |
8117 | break; | |
8118 | } | |
8119 | break; | |
7ad10968 HZ |
8120 | |
8121 | default: | |
7ad10968 HZ |
8122 | goto no_support; |
8123 | break; | |
8124 | } | |
8125 | ||
cf648174 | 8126 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8127 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8128 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8129 | return -1; |
8130 | ||
8131 | return 0; | |
8132 | ||
01fe1b41 | 8133 | no_support: |
a3c4230a HZ |
8134 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8135 | "at address %s.\n"), | |
8136 | (unsigned int) (opcode), | |
8137 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8138 | return -1; |
8139 | } | |
8140 | ||
cf648174 HZ |
8141 | static const int i386_record_regmap[] = |
8142 | { | |
8143 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8144 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8145 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8146 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8147 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8148 | }; | |
8149 | ||
7a697b8d | 8150 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8151 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8152 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8153 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8154 | middle of the tracepoint jump. On x86, it may be possible to use |
8155 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8156 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8157 | of instruction to replace, and 0 if not, plus an explanatory |
8158 | string. */ | |
8159 | ||
8160 | static int | |
6b940e6a PL |
8161 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
8162 | char **msg) | |
7a697b8d SS |
8163 | { |
8164 | int len, jumplen; | |
7a697b8d | 8165 | |
405f8e94 SS |
8166 | /* Ask the target for the minimum instruction length supported. */ |
8167 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8168 | ||
8169 | if (jumplen < 0) | |
8170 | { | |
8171 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8172 | operation, assume that fast tracepoints will always be implemented | |
8173 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8174 | jumplen = 5; | |
8175 | } | |
8176 | else if (jumplen == 0) | |
8177 | { | |
8178 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8179 | returns zero, then the IPA has not loaded yet. In this case, | |
8180 | we optimistically assume that truncated 2-byte relative jumps | |
8181 | will be available on x86, and compensate later if this assumption | |
8182 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8183 | jumps will always be used. */ | |
8184 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8185 | } | |
7a697b8d | 8186 | |
7a697b8d | 8187 | /* Check for fit. */ |
be85ce7d | 8188 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8189 | |
7a697b8d SS |
8190 | if (len < jumplen) |
8191 | { | |
8192 | /* Return a bit of target-specific detail to add to the caller's | |
8193 | generic failure message. */ | |
8194 | if (msg) | |
1777feb0 MS |
8195 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8196 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8197 | len, jumplen); |
8198 | return 0; | |
8199 | } | |
405f8e94 SS |
8200 | else |
8201 | { | |
8202 | if (msg) | |
8203 | *msg = NULL; | |
8204 | return 1; | |
8205 | } | |
7a697b8d SS |
8206 | } |
8207 | ||
00d5215e UW |
8208 | /* Return a floating-point format for a floating-point variable of |
8209 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8210 | If no suitable type is found, return NULL. */ | |
8211 | ||
8212 | const struct floatformat ** | |
8213 | i386_floatformat_for_type (struct gdbarch *gdbarch, | |
8214 | const char *name, int len) | |
8215 | { | |
8216 | if (len == 128 && name) | |
8217 | if (strcmp (name, "__float128") == 0 | |
8218 | || strcmp (name, "_Float128") == 0 | |
8219 | || strcmp (name, "complex _Float128") == 0) | |
8220 | return floatformats_ia64_quad; | |
8221 | ||
8222 | return default_floatformat_for_type (gdbarch, name, len); | |
8223 | } | |
8224 | ||
90884b2b L |
8225 | static int |
8226 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8227 | struct tdesc_arch_data *tdesc_data) | |
8228 | { | |
8229 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8230 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8231 | |
8232 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
51547df6 | 8233 | *feature_avx512, *feature_pkeys; |
90884b2b L |
8234 | int i, num_regs, valid_p; |
8235 | ||
8236 | if (! tdesc_has_registers (tdesc)) | |
8237 | return 0; | |
8238 | ||
8239 | /* Get core registers. */ | |
8240 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8241 | if (feature_core == NULL) |
8242 | return 0; | |
90884b2b L |
8243 | |
8244 | /* Get SSE registers. */ | |
c131fcee | 8245 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8246 | |
c131fcee L |
8247 | /* Try AVX registers. */ |
8248 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8249 | ||
1dbcd68c WT |
8250 | /* Try MPX registers. */ |
8251 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8252 | ||
01f9f808 MS |
8253 | /* Try AVX512 registers. */ |
8254 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8255 | ||
51547df6 MS |
8256 | /* Try PKEYS */ |
8257 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8258 | ||
90884b2b L |
8259 | valid_p = 1; |
8260 | ||
c131fcee | 8261 | /* The XCR0 bits. */ |
01f9f808 MS |
8262 | if (feature_avx512) |
8263 | { | |
8264 | /* AVX512 register description requires AVX register description. */ | |
8265 | if (!feature_avx) | |
8266 | return 0; | |
8267 | ||
a1fa17ee | 8268 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8269 | |
8270 | /* It may have been set by OSABI initialization function. */ | |
8271 | if (tdep->k0_regnum < 0) | |
8272 | { | |
8273 | tdep->k_register_names = i386_k_names; | |
8274 | tdep->k0_regnum = I386_K0_REGNUM; | |
8275 | } | |
8276 | ||
8277 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8278 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8279 | tdep->k0_regnum + i, | |
8280 | i386_k_names[i]); | |
8281 | ||
8282 | if (tdep->num_zmm_regs == 0) | |
8283 | { | |
8284 | tdep->zmmh_register_names = i386_zmmh_names; | |
8285 | tdep->num_zmm_regs = 8; | |
8286 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8287 | } | |
8288 | ||
8289 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8290 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8291 | tdep->zmm0h_regnum + i, | |
8292 | tdep->zmmh_register_names[i]); | |
8293 | ||
8294 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8295 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8296 | tdep->xmm16_regnum + i, | |
8297 | tdep->xmm_avx512_register_names[i]); | |
8298 | ||
8299 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8300 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8301 | tdep->ymm16h_regnum + i, | |
8302 | tdep->ymm16h_register_names[i]); | |
8303 | } | |
c131fcee L |
8304 | if (feature_avx) |
8305 | { | |
3a13a53b L |
8306 | /* AVX register description requires SSE register description. */ |
8307 | if (!feature_sse) | |
8308 | return 0; | |
8309 | ||
01f9f808 | 8310 | if (!feature_avx512) |
df7e5265 | 8311 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8312 | |
8313 | /* It may have been set by OSABI initialization function. */ | |
8314 | if (tdep->num_ymm_regs == 0) | |
8315 | { | |
8316 | tdep->ymmh_register_names = i386_ymmh_names; | |
8317 | tdep->num_ymm_regs = 8; | |
8318 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8319 | } | |
8320 | ||
8321 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8322 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8323 | tdep->ymm0h_regnum + i, | |
8324 | tdep->ymmh_register_names[i]); | |
8325 | } | |
3a13a53b | 8326 | else if (feature_sse) |
df7e5265 | 8327 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8328 | else |
8329 | { | |
df7e5265 | 8330 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8331 | tdep->num_xmm_regs = 0; |
8332 | } | |
c131fcee | 8333 | |
90884b2b L |
8334 | num_regs = tdep->num_core_regs; |
8335 | for (i = 0; i < num_regs; i++) | |
8336 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8337 | tdep->register_names[i]); | |
8338 | ||
3a13a53b L |
8339 | if (feature_sse) |
8340 | { | |
8341 | /* Need to include %mxcsr, so add one. */ | |
8342 | num_regs += tdep->num_xmm_regs + 1; | |
8343 | for (; i < num_regs; i++) | |
8344 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8345 | tdep->register_names[i]); | |
8346 | } | |
90884b2b | 8347 | |
1dbcd68c WT |
8348 | if (feature_mpx) |
8349 | { | |
df7e5265 | 8350 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8351 | |
8352 | if (tdep->bnd0r_regnum < 0) | |
8353 | { | |
8354 | tdep->mpx_register_names = i386_mpx_names; | |
8355 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8356 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8357 | } | |
8358 | ||
8359 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8360 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8361 | I387_BND0R_REGNUM (tdep) + i, | |
8362 | tdep->mpx_register_names[i]); | |
8363 | } | |
8364 | ||
51547df6 MS |
8365 | if (feature_pkeys) |
8366 | { | |
8367 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8368 | if (tdep->pkru_regnum < 0) | |
8369 | { | |
8370 | tdep->pkeys_register_names = i386_pkeys_names; | |
8371 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8372 | tdep->num_pkeys_regs = 1; | |
8373 | } | |
8374 | ||
8375 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8376 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8377 | I387_PKRU_REGNUM (tdep) + i, | |
8378 | tdep->pkeys_register_names[i]); | |
8379 | } | |
8380 | ||
90884b2b L |
8381 | return valid_p; |
8382 | } | |
8383 | ||
7ad10968 | 8384 | \f |
ad9eb1fd DE |
8385 | /* Note: This is called for both i386 and amd64. */ |
8386 | ||
7ad10968 HZ |
8387 | static struct gdbarch * |
8388 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8389 | { | |
8390 | struct gdbarch_tdep *tdep; | |
8391 | struct gdbarch *gdbarch; | |
90884b2b L |
8392 | struct tdesc_arch_data *tdesc_data; |
8393 | const struct target_desc *tdesc; | |
1ba53b71 | 8394 | int mm0_regnum; |
c131fcee | 8395 | int ymm0_regnum; |
1dbcd68c WT |
8396 | int bnd0_regnum; |
8397 | int num_bnd_cooked; | |
7ad10968 HZ |
8398 | |
8399 | /* If there is already a candidate, use it. */ | |
8400 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8401 | if (arches != NULL) | |
8402 | return arches->gdbarch; | |
8403 | ||
ad9eb1fd | 8404 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8405 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8406 | gdbarch = gdbarch_alloc (&info, tdep); |
8407 | ||
8408 | /* General-purpose registers. */ | |
7ad10968 HZ |
8409 | tdep->gregset_reg_offset = NULL; |
8410 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8411 | tdep->sizeof_gregset = 0; | |
8412 | ||
8413 | /* Floating-point registers. */ | |
7ad10968 | 8414 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8415 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8416 | |
8417 | /* The default settings include the FPU registers, the MMX registers | |
8418 | and the SSE registers. This can be overridden for a specific ABI | |
8419 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8420 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8421 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8422 | |
8423 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8424 | ||
7ad10968 HZ |
8425 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8426 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8427 | ||
8428 | tdep->jb_pc_offset = -1; | |
8429 | tdep->struct_return = pcc_struct_return; | |
8430 | tdep->sigtramp_start = 0; | |
8431 | tdep->sigtramp_end = 0; | |
8432 | tdep->sigtramp_p = i386_sigtramp_p; | |
8433 | tdep->sigcontext_addr = NULL; | |
8434 | tdep->sc_reg_offset = NULL; | |
8435 | tdep->sc_pc_offset = -1; | |
8436 | tdep->sc_sp_offset = -1; | |
8437 | ||
c131fcee L |
8438 | tdep->xsave_xcr0_offset = -1; |
8439 | ||
cf648174 HZ |
8440 | tdep->record_regmap = i386_record_regmap; |
8441 | ||
205c306f DM |
8442 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8443 | ||
7ad10968 HZ |
8444 | /* The format used for `long double' on almost all i386 targets is |
8445 | the i387 extended floating-point format. In fact, of all targets | |
8446 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8447 | on having a `long double' that's not `long' at all. */ | |
8448 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8449 | ||
8450 | /* Although the i387 extended floating-point has only 80 significant | |
8451 | bits, a `long double' actually takes up 96, probably to enforce | |
8452 | alignment. */ | |
8453 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8454 | ||
00d5215e UW |
8455 | /* Support for floating-point data type variants. */ |
8456 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8457 | ||
7ad10968 HZ |
8458 | /* Register numbers of various important registers. */ |
8459 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8460 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8461 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8462 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8463 | ||
8464 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8465 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8466 | differ in how they number %ebp, %esp, %eflags, and the | |
8467 | floating-point registers, and are implemented by the arrays | |
8468 | dbx_register_map[] and svr4_dbx_register_map in | |
8469 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8470 | gcc/config/i386.c, which it designates as the "default" register | |
8471 | map used in 64bit mode. This last register numbering scheme is | |
8472 | implemented in dbx64_register_map, and is used for AMD64; see | |
8473 | amd64-tdep.c. | |
8474 | ||
8475 | Currently, each GCC i386 target always uses the same register | |
8476 | numbering scheme across all its supported debugging formats | |
8477 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8478 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8479 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8480 | respective config header in a manner independent of the requested | |
8481 | output debugging format. | |
8482 | ||
8483 | This does not match the arrangement below, which presumes that | |
8484 | the SDB and stabs numbering schemes differ from the DWARF and | |
8485 | DWARF 2 ones. The reason for this arrangement is that it is | |
8486 | likely to get the numbering scheme for the target's | |
8487 | default/native debug format right. For targets where GCC is the | |
8488 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8489 | targets where the native toolchain uses a different numbering | |
8490 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8491 | the defaults below will have to be overridden, like | |
8492 | i386_elf_init_abi() does. */ | |
8493 | ||
8494 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8495 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8496 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8497 | ||
8498 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8499 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8500 | |
8501 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8502 | be in use on any of the supported i386 targets. */ | |
8503 | ||
8504 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8505 | ||
8506 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8507 | ||
8508 | /* Call dummy code. */ | |
a9b8d892 JK |
8509 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8510 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8511 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8512 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8513 | |
8514 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8515 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8516 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8517 | ||
8518 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8519 | ||
8520 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8521 | ||
8522 | /* Stack grows downward. */ | |
8523 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8524 | ||
04180708 YQ |
8525 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8526 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8527 | ||
7ad10968 HZ |
8528 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8529 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8530 | ||
8531 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8532 | ||
7ad10968 HZ |
8533 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8534 | ||
8535 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8536 | ||
8537 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8538 | ||
8539 | /* Add the i386 register groups. */ | |
8540 | i386_add_reggroups (gdbarch); | |
90884b2b | 8541 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8542 | |
143985b7 AF |
8543 | /* Helper for function argument information. */ |
8544 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8545 | ||
06da04c6 | 8546 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8547 | appended to the list first, so that it supercedes the DWARF |
8548 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8549 | currently fails). */ |
8550 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8551 | ||
8552 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8553 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8554 | CFI info will be used if it is available. */ |
10458914 | 8555 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8556 | |
acd5c798 | 8557 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8558 | |
1ba53b71 | 8559 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8560 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8561 | i386_pseudo_register_read_value); | |
90884b2b | 8562 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8563 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8564 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8565 | |
8566 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8567 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8568 | ||
c131fcee L |
8569 | /* Override the normal target description method to make the AVX |
8570 | upper halves anonymous. */ | |
8571 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8572 | ||
8573 | /* Even though the default ABI only includes general-purpose registers, | |
8574 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8575 | gap for the upper AVX, MPX and AVX512 registers. */ |
51547df6 | 8576 | set_gdbarch_num_regs (gdbarch, I386_PKEYS_NUM_REGS); |
90884b2b | 8577 | |
ac04f72b TT |
8578 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8579 | ||
90884b2b L |
8580 | /* Get the x86 target description from INFO. */ |
8581 | tdesc = info.target_desc; | |
8582 | if (! tdesc_has_registers (tdesc)) | |
8583 | tdesc = tdesc_i386; | |
8584 | tdep->tdesc = tdesc; | |
8585 | ||
8586 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8587 | tdep->register_names = i386_register_names; | |
8588 | ||
c131fcee L |
8589 | /* No upper YMM registers. */ |
8590 | tdep->ymmh_register_names = NULL; | |
8591 | tdep->ymm0h_regnum = -1; | |
8592 | ||
01f9f808 MS |
8593 | /* No upper ZMM registers. */ |
8594 | tdep->zmmh_register_names = NULL; | |
8595 | tdep->zmm0h_regnum = -1; | |
8596 | ||
8597 | /* No high XMM registers. */ | |
8598 | tdep->xmm_avx512_register_names = NULL; | |
8599 | tdep->xmm16_regnum = -1; | |
8600 | ||
8601 | /* No upper YMM16-31 registers. */ | |
8602 | tdep->ymm16h_register_names = NULL; | |
8603 | tdep->ymm16h_regnum = -1; | |
8604 | ||
1ba53b71 L |
8605 | tdep->num_byte_regs = 8; |
8606 | tdep->num_word_regs = 8; | |
8607 | tdep->num_dword_regs = 0; | |
8608 | tdep->num_mmx_regs = 8; | |
c131fcee | 8609 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8610 | |
1dbcd68c WT |
8611 | /* No MPX registers. */ |
8612 | tdep->bnd0r_regnum = -1; | |
8613 | tdep->bndcfgu_regnum = -1; | |
8614 | ||
01f9f808 MS |
8615 | /* No AVX512 registers. */ |
8616 | tdep->k0_regnum = -1; | |
8617 | tdep->num_zmm_regs = 0; | |
8618 | tdep->num_ymm_avx512_regs = 0; | |
8619 | tdep->num_xmm_avx512_regs = 0; | |
8620 | ||
51547df6 MS |
8621 | /* No PKEYS registers */ |
8622 | tdep->pkru_regnum = -1; | |
8623 | tdep->num_pkeys_regs = 0; | |
8624 | ||
90884b2b L |
8625 | tdesc_data = tdesc_data_alloc (); |
8626 | ||
dde08ee1 PA |
8627 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8628 | ||
6710bf39 SS |
8629 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8630 | ||
c2170eef MM |
8631 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8632 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8633 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8634 | ||
ad9eb1fd DE |
8635 | /* Hook in ABI-specific overrides, if they have been registered. |
8636 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8637 | a 32-bit i386 into a 64-bit amd64. */ | |
ede5f151 | 8638 | info.tdep_info = tdesc_data; |
4be87837 | 8639 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8640 | |
c131fcee L |
8641 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8642 | { | |
8643 | tdesc_data_cleanup (tdesc_data); | |
8644 | xfree (tdep); | |
8645 | gdbarch_free (gdbarch); | |
8646 | return NULL; | |
8647 | } | |
8648 | ||
1dbcd68c WT |
8649 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8650 | ||
1ba53b71 L |
8651 | /* Wire in pseudo registers. Number of pseudo registers may be |
8652 | changed. */ | |
8653 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8654 | + tdep->num_word_regs | |
8655 | + tdep->num_dword_regs | |
c131fcee | 8656 | + tdep->num_mmx_regs |
1dbcd68c | 8657 | + tdep->num_ymm_regs |
01f9f808 MS |
8658 | + num_bnd_cooked |
8659 | + tdep->num_ymm_avx512_regs | |
8660 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8661 | |
90884b2b L |
8662 | /* Target description may be changed. */ |
8663 | tdesc = tdep->tdesc; | |
8664 | ||
90884b2b L |
8665 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8666 | ||
8667 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8668 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8669 | ||
1ba53b71 L |
8670 | /* Make %al the first pseudo-register. */ |
8671 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8672 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8673 | ||
c131fcee | 8674 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8675 | if (tdep->num_dword_regs) |
8676 | { | |
1c6272a6 | 8677 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8678 | tdep->eax_regnum = ymm0_regnum; |
8679 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8680 | } |
8681 | else | |
8682 | tdep->eax_regnum = -1; | |
8683 | ||
c131fcee L |
8684 | mm0_regnum = ymm0_regnum; |
8685 | if (tdep->num_ymm_regs) | |
8686 | { | |
1c6272a6 | 8687 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8688 | tdep->ymm0_regnum = ymm0_regnum; |
8689 | mm0_regnum += tdep->num_ymm_regs; | |
8690 | } | |
8691 | else | |
8692 | tdep->ymm0_regnum = -1; | |
8693 | ||
01f9f808 MS |
8694 | if (tdep->num_ymm_avx512_regs) |
8695 | { | |
8696 | /* Support YMM16-31 pseudo registers if available. */ | |
8697 | tdep->ymm16_regnum = mm0_regnum; | |
8698 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8699 | } | |
8700 | else | |
8701 | tdep->ymm16_regnum = -1; | |
8702 | ||
8703 | if (tdep->num_zmm_regs) | |
8704 | { | |
8705 | /* Support ZMM pseudo-register if it is available. */ | |
8706 | tdep->zmm0_regnum = mm0_regnum; | |
8707 | mm0_regnum += tdep->num_zmm_regs; | |
8708 | } | |
8709 | else | |
8710 | tdep->zmm0_regnum = -1; | |
8711 | ||
1dbcd68c | 8712 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8713 | if (tdep->num_mmx_regs != 0) |
8714 | { | |
1c6272a6 | 8715 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8716 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8717 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8718 | } |
8719 | else | |
8720 | tdep->mm0_regnum = -1; | |
8721 | ||
1dbcd68c WT |
8722 | if (tdep->bnd0r_regnum > 0) |
8723 | tdep->bnd0_regnum = bnd0_regnum; | |
8724 | else | |
8725 | tdep-> bnd0_regnum = -1; | |
8726 | ||
06da04c6 | 8727 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8728 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8729 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8730 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8731 | |
8446b36a MK |
8732 | /* If we have a register mapping, enable the generic core file |
8733 | support, unless it has already been enabled. */ | |
8734 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8735 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8736 | set_gdbarch_iterate_over_regset_sections |
8737 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8738 | |
7a697b8d SS |
8739 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8740 | i386_fast_tracepoint_valid_at); | |
8741 | ||
a62cc96e AC |
8742 | return gdbarch; |
8743 | } | |
8744 | ||
8201327c MK |
8745 | static enum gdb_osabi |
8746 | i386_coff_osabi_sniffer (bfd *abfd) | |
8747 | { | |
762c5349 MK |
8748 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8749 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8750 | return GDB_OSABI_GO32; |
8751 | ||
8752 | return GDB_OSABI_UNKNOWN; | |
8753 | } | |
8201327c MK |
8754 | \f |
8755 | ||
97de3545 JB |
8756 | /* Return the target description for a specified XSAVE feature mask. */ |
8757 | ||
8758 | const struct target_desc * | |
8759 | i386_target_description (uint64_t xcr0) | |
8760 | { | |
8761 | switch (xcr0 & X86_XSTATE_ALL_MASK) | |
8762 | { | |
51547df6 MS |
8763 | case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: |
8764 | return tdesc_i386_avx_mpx_avx512_pku; | |
a1fa17ee MS |
8765 | case X86_XSTATE_AVX_AVX512_MASK: |
8766 | return tdesc_i386_avx_avx512; | |
2b863f51 WT |
8767 | case X86_XSTATE_AVX_MPX_MASK: |
8768 | return tdesc_i386_avx_mpx; | |
97de3545 JB |
8769 | case X86_XSTATE_MPX_MASK: |
8770 | return tdesc_i386_mpx; | |
8771 | case X86_XSTATE_AVX_MASK: | |
8772 | return tdesc_i386_avx; | |
8773 | default: | |
8774 | return tdesc_i386; | |
8775 | } | |
8776 | } | |
8777 | ||
29c1c244 WT |
8778 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8779 | ||
8780 | /* Find the bound directory base address. */ | |
8781 | ||
8782 | static unsigned long | |
8783 | i386_mpx_bd_base (void) | |
8784 | { | |
8785 | struct regcache *rcache; | |
8786 | struct gdbarch_tdep *tdep; | |
8787 | ULONGEST ret; | |
8788 | enum register_status regstatus; | |
29c1c244 WT |
8789 | |
8790 | rcache = get_current_regcache (); | |
8791 | tdep = gdbarch_tdep (get_regcache_arch (rcache)); | |
8792 | ||
8793 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8794 | ||
8795 | if (regstatus != REG_VALID) | |
8796 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8797 | ||
8798 | return ret & MPX_BASE_MASK; | |
8799 | } | |
8800 | ||
012b3a21 | 8801 | int |
29c1c244 WT |
8802 | i386_mpx_enabled (void) |
8803 | { | |
8804 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8805 | const struct target_desc *tdesc = tdep->tdesc; | |
8806 | ||
8807 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8808 | } | |
8809 | ||
8810 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8811 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8812 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8813 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8814 | ||
8815 | /* Find the bound table entry given the pointer location and the base | |
8816 | address of the table. */ | |
8817 | ||
8818 | static CORE_ADDR | |
8819 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8820 | { | |
8821 | CORE_ADDR offset1; | |
8822 | CORE_ADDR offset2; | |
8823 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8824 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8825 | CORE_ADDR bd_entry_addr; | |
8826 | CORE_ADDR bt_addr; | |
8827 | CORE_ADDR bd_entry; | |
8828 | struct gdbarch *gdbarch = get_current_arch (); | |
8829 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8830 | ||
8831 | ||
8832 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8833 | { | |
966f0aef | 8834 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8835 | bd_ptr_r_shift = 20; |
8836 | bd_ptr_l_shift = 3; | |
8837 | bt_select_r_shift = 3; | |
8838 | bt_select_l_shift = 5; | |
966f0aef WT |
8839 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8840 | ||
8841 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8842 | error (_("bound table examination not supported\ |
8843 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8844 | } |
8845 | else | |
8846 | { | |
8847 | mpx_bd_mask = MPX_BD_MASK_32; | |
8848 | bd_ptr_r_shift = 12; | |
8849 | bd_ptr_l_shift = 2; | |
8850 | bt_select_r_shift = 2; | |
8851 | bt_select_l_shift = 4; | |
8852 | bt_mask = MPX_BT_MASK_32; | |
8853 | } | |
8854 | ||
8855 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8856 | bd_entry_addr = bd_base + offset1; | |
8857 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8858 | ||
8859 | if ((bd_entry & 0x1) == 0) | |
8860 | error (_("Invalid bounds directory entry at %s."), | |
8861 | paddress (get_current_arch (), bd_entry_addr)); | |
8862 | ||
8863 | /* Clearing status bit. */ | |
8864 | bd_entry--; | |
8865 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8866 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8867 | ||
8868 | return bt_addr + offset2; | |
8869 | } | |
8870 | ||
8871 | /* Print routine for the mpx bounds. */ | |
8872 | ||
8873 | static void | |
8874 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8875 | { | |
8876 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8877 | LONGEST size; |
29c1c244 WT |
8878 | struct gdbarch *gdbarch = get_current_arch (); |
8879 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8880 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8881 | ||
8882 | if (bounds_in_map == 1) | |
8883 | { | |
112e8700 SM |
8884 | uiout->text ("Null bounds on map:"); |
8885 | uiout->text (" pointer value = "); | |
8886 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8887 | uiout->text ("."); | |
8888 | uiout->text ("\n"); | |
29c1c244 WT |
8889 | } |
8890 | else | |
8891 | { | |
112e8700 SM |
8892 | uiout->text ("{lbound = "); |
8893 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8894 | uiout->text (", ubound = "); | |
29c1c244 WT |
8895 | |
8896 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8897 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8898 | uiout->text ("}: pointer value = "); | |
8899 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8900 | |
8901 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8902 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8903 | else | |
8904 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8905 | ||
8906 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8907 | -1 represents in this sense full memory access, and there is no need | |
8908 | one to the size. */ | |
8909 | ||
8910 | size = (size > -1 ? size + 1 : size); | |
112e8700 SM |
8911 | uiout->text (", size = "); |
8912 | uiout->field_fmt ("size", "%s", plongest (size)); | |
29c1c244 | 8913 | |
112e8700 SM |
8914 | uiout->text (", metadata = "); |
8915 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8916 | uiout->text ("\n"); | |
29c1c244 WT |
8917 | } |
8918 | } | |
8919 | ||
8920 | /* Implement the command "show mpx bound". */ | |
8921 | ||
8922 | static void | |
8923 | i386_mpx_info_bounds (char *args, int from_tty) | |
8924 | { | |
8925 | CORE_ADDR bd_base = 0; | |
8926 | CORE_ADDR addr; | |
8927 | CORE_ADDR bt_entry_addr = 0; | |
8928 | CORE_ADDR bt_entry[4]; | |
8929 | int i; | |
8930 | struct gdbarch *gdbarch = get_current_arch (); | |
8931 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8932 | ||
ae71e7b5 MR |
8933 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8934 | || !i386_mpx_enabled ()) | |
118ca224 | 8935 | { |
bc504a31 | 8936 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8937 | "supported on this target.\n")); |
8938 | return; | |
8939 | } | |
29c1c244 WT |
8940 | |
8941 | if (args == NULL) | |
118ca224 PP |
8942 | { |
8943 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8944 | return; | |
8945 | } | |
29c1c244 WT |
8946 | |
8947 | addr = parse_and_eval_address (args); | |
8948 | ||
8949 | bd_base = i386_mpx_bd_base (); | |
8950 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8951 | ||
8952 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8953 | ||
8954 | for (i = 0; i < 4; i++) | |
8955 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8956 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8957 | data_ptr_type); |
8958 | ||
8959 | i386_mpx_print_bounds (bt_entry); | |
8960 | } | |
8961 | ||
8962 | /* Implement the command "set mpx bound". */ | |
8963 | ||
8964 | static void | |
8965 | i386_mpx_set_bounds (char *args, int from_tty) | |
8966 | { | |
8967 | CORE_ADDR bd_base = 0; | |
8968 | CORE_ADDR addr, lower, upper; | |
8969 | CORE_ADDR bt_entry_addr = 0; | |
8970 | CORE_ADDR bt_entry[2]; | |
8971 | const char *input = args; | |
8972 | int i; | |
8973 | struct gdbarch *gdbarch = get_current_arch (); | |
8974 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8975 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8976 | ||
ae71e7b5 MR |
8977 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8978 | || !i386_mpx_enabled ()) | |
bc504a31 | 8979 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
8980 | on this target.")); |
8981 | ||
8982 | if (args == NULL) | |
8983 | error (_("Pointer value expected.")); | |
8984 | ||
8985 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8986 | ||
8987 | if (input[0] == ',') | |
8988 | ++input; | |
8989 | if (input[0] == '\0') | |
8990 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8991 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8992 | ||
8993 | if (input[0] == ',') | |
8994 | ++input; | |
8995 | if (input[0] == '\0') | |
8996 | error (_("Wrong number of arguments; Missing upper bound.")); | |
8997 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
8998 | ||
8999 | bd_base = i386_mpx_bd_base (); | |
9000 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
9001 | for (i = 0; i < 2; i++) | |
9002 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 9003 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
9004 | data_ptr_type); |
9005 | bt_entry[0] = (uint64_t) lower; | |
9006 | bt_entry[1] = ~(uint64_t) upper; | |
9007 | ||
9008 | for (i = 0; i < 2; i++) | |
132874d7 AB |
9009 | write_memory_unsigned_integer (bt_entry_addr |
9010 | + i * TYPE_LENGTH (data_ptr_type), | |
9011 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
9012 | bt_entry[i]); |
9013 | } | |
9014 | ||
9015 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
9016 | ||
9017 | /* Helper function for the CLI commands. */ | |
9018 | ||
9019 | static void | |
9020 | set_mpx_cmd (char *args, int from_tty) | |
9021 | { | |
118ca224 | 9022 | help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout); |
29c1c244 WT |
9023 | } |
9024 | ||
9025 | /* Helper function for the CLI commands. */ | |
9026 | ||
9027 | static void | |
9028 | show_mpx_cmd (char *args, int from_tty) | |
9029 | { | |
9030 | cmd_show_list (mpx_show_cmdlist, from_tty, ""); | |
9031 | } | |
9032 | ||
28e9e0f0 MK |
9033 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
9034 | void _initialize_i386_tdep (void); | |
9035 | ||
c906108c | 9036 | void |
fba45db2 | 9037 | _initialize_i386_tdep (void) |
c906108c | 9038 | { |
a62cc96e AC |
9039 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
9040 | ||
fc338970 | 9041 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
9042 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
9043 | &disassembly_flavor, _("\ | |
9044 | Set the disassembly flavor."), _("\ | |
9045 | Show the disassembly flavor."), _("\ | |
9046 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
9047 | NULL, | |
9048 | NULL, /* FIXME: i18n: */ | |
9049 | &setlist, &showlist); | |
8201327c MK |
9050 | |
9051 | /* Add the variable that controls the convention for returning | |
9052 | structs. */ | |
7ab04401 AC |
9053 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9054 | &struct_convention, _("\ | |
9055 | Set the convention for returning small structs."), _("\ | |
9056 | Show the convention for returning small structs."), _("\ | |
9057 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9058 | is \"default\"."), | |
9059 | NULL, | |
9060 | NULL, /* FIXME: i18n: */ | |
9061 | &setlist, &showlist); | |
8201327c | 9062 | |
29c1c244 WT |
9063 | /* Add "mpx" prefix for the set commands. */ |
9064 | ||
9065 | add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\ | |
bc504a31 | 9066 | Set Intel Memory Protection Extensions specific variables."), |
118ca224 | 9067 | &mpx_set_cmdlist, "set mpx ", |
29c1c244 WT |
9068 | 0 /* allow-unknown */, &setlist); |
9069 | ||
9070 | /* Add "mpx" prefix for the show commands. */ | |
9071 | ||
9072 | add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\ | |
bc504a31 | 9073 | Show Intel Memory Protection Extensions specific variables."), |
29c1c244 WT |
9074 | &mpx_show_cmdlist, "show mpx ", |
9075 | 0 /* allow-unknown */, &showlist); | |
9076 | ||
9077 | /* Add "bound" command for the show mpx commands list. */ | |
9078 | ||
9079 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9080 | "Show the memory bounds for a given array/pointer storage\ | |
9081 | in the bound table.", | |
9082 | &mpx_show_cmdlist); | |
9083 | ||
9084 | /* Add "bound" command for the set mpx commands list. */ | |
9085 | ||
9086 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9087 | "Set the memory bounds for a given array/pointer storage\ | |
9088 | in the bound table.", | |
9089 | &mpx_set_cmdlist); | |
9090 | ||
8201327c MK |
9091 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, |
9092 | i386_coff_osabi_sniffer); | |
8201327c | 9093 | |
05816f70 | 9094 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9095 | i386_svr4_init_abi); |
05816f70 | 9096 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 9097 | i386_go32_init_abi); |
38c968cf | 9098 | |
209bd28e | 9099 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9100 | i386_init_reggroups (); |
90884b2b L |
9101 | |
9102 | /* Initialize the standard target descriptions. */ | |
9103 | initialize_tdesc_i386 (); | |
3a13a53b | 9104 | initialize_tdesc_i386_mmx (); |
c131fcee | 9105 | initialize_tdesc_i386_avx (); |
1dbcd68c | 9106 | initialize_tdesc_i386_mpx (); |
2b863f51 | 9107 | initialize_tdesc_i386_avx_mpx (); |
a1fa17ee | 9108 | initialize_tdesc_i386_avx_avx512 (); |
51547df6 | 9109 | initialize_tdesc_i386_avx_mpx_avx512_pku (); |
c8d5aac9 L |
9110 | |
9111 | /* Tell remote stub that we support XML target description. */ | |
9112 | register_remote_support_xml ("i386"); | |
c906108c | 9113 | } |