Commit | Line | Data |
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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
618f726f | 3 | Copyright (C) 1988-2016 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
6405b0a6 | 25 | #include "dwarf2-frame.h" |
acd5c798 | 26 | #include "doublest.h" |
c906108c | 27 | #include "frame.h" |
acd5c798 MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
c906108c | 30 | #include "inferior.h" |
45741a9c | 31 | #include "infrun.h" |
acd5c798 | 32 | #include "gdbcmd.h" |
c906108c | 33 | #include "gdbcore.h" |
e6bb342a | 34 | #include "gdbtypes.h" |
dfe01d39 | 35 | #include "objfiles.h" |
acd5c798 MK |
36 | #include "osabi.h" |
37 | #include "regcache.h" | |
38 | #include "reggroups.h" | |
473f17b0 | 39 | #include "regset.h" |
c0d1d883 | 40 | #include "symfile.h" |
c906108c | 41 | #include "symtab.h" |
acd5c798 | 42 | #include "target.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
df7e5265 | 49 | #include "x86-xstate.h" |
d2a7c97a | 50 | |
7ad10968 | 51 | #include "record.h" |
d02ed0bb | 52 | #include "record-full.h" |
90884b2b | 53 | #include "features/i386/i386.c" |
c131fcee | 54 | #include "features/i386/i386-avx.c" |
1dbcd68c | 55 | #include "features/i386/i386-mpx.c" |
2b863f51 | 56 | #include "features/i386/i386-avx-mpx.c" |
01f9f808 | 57 | #include "features/i386/i386-avx512.c" |
3a13a53b | 58 | #include "features/i386/i386-mmx.c" |
90884b2b | 59 | |
6710bf39 SS |
60 | #include "ax.h" |
61 | #include "ax-gdb.h" | |
62 | ||
55aa24fb SDJ |
63 | #include "stap-probe.h" |
64 | #include "user-regs.h" | |
65 | #include "cli/cli-utils.h" | |
66 | #include "expression.h" | |
67 | #include "parser-defs.h" | |
68 | #include <ctype.h> | |
325fac50 | 69 | #include <algorithm> |
55aa24fb | 70 | |
c4fc7f1b | 71 | /* Register names. */ |
c40e1eab | 72 | |
90884b2b | 73 | static const char *i386_register_names[] = |
fc633446 MK |
74 | { |
75 | "eax", "ecx", "edx", "ebx", | |
76 | "esp", "ebp", "esi", "edi", | |
77 | "eip", "eflags", "cs", "ss", | |
78 | "ds", "es", "fs", "gs", | |
79 | "st0", "st1", "st2", "st3", | |
80 | "st4", "st5", "st6", "st7", | |
81 | "fctrl", "fstat", "ftag", "fiseg", | |
82 | "fioff", "foseg", "fooff", "fop", | |
83 | "xmm0", "xmm1", "xmm2", "xmm3", | |
84 | "xmm4", "xmm5", "xmm6", "xmm7", | |
85 | "mxcsr" | |
86 | }; | |
87 | ||
01f9f808 MS |
88 | static const char *i386_zmm_names[] = |
89 | { | |
90 | "zmm0", "zmm1", "zmm2", "zmm3", | |
91 | "zmm4", "zmm5", "zmm6", "zmm7" | |
92 | }; | |
93 | ||
94 | static const char *i386_zmmh_names[] = | |
95 | { | |
96 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
97 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
98 | }; | |
99 | ||
100 | static const char *i386_k_names[] = | |
101 | { | |
102 | "k0", "k1", "k2", "k3", | |
103 | "k4", "k5", "k6", "k7" | |
104 | }; | |
105 | ||
c131fcee L |
106 | static const char *i386_ymm_names[] = |
107 | { | |
108 | "ymm0", "ymm1", "ymm2", "ymm3", | |
109 | "ymm4", "ymm5", "ymm6", "ymm7", | |
110 | }; | |
111 | ||
112 | static const char *i386_ymmh_names[] = | |
113 | { | |
114 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
115 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
116 | }; | |
117 | ||
1dbcd68c WT |
118 | static const char *i386_mpx_names[] = |
119 | { | |
120 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
121 | }; | |
122 | ||
123 | /* Register names for MPX pseudo-registers. */ | |
124 | ||
125 | static const char *i386_bnd_names[] = | |
126 | { | |
127 | "bnd0", "bnd1", "bnd2", "bnd3" | |
128 | }; | |
129 | ||
c4fc7f1b | 130 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 131 | |
90884b2b | 132 | static const char *i386_mmx_names[] = |
28fc6740 AC |
133 | { |
134 | "mm0", "mm1", "mm2", "mm3", | |
135 | "mm4", "mm5", "mm6", "mm7" | |
136 | }; | |
c40e1eab | 137 | |
1ba53b71 L |
138 | /* Register names for byte pseudo-registers. */ |
139 | ||
140 | static const char *i386_byte_names[] = | |
141 | { | |
142 | "al", "cl", "dl", "bl", | |
143 | "ah", "ch", "dh", "bh" | |
144 | }; | |
145 | ||
146 | /* Register names for word pseudo-registers. */ | |
147 | ||
148 | static const char *i386_word_names[] = | |
149 | { | |
150 | "ax", "cx", "dx", "bx", | |
9cad29ac | 151 | "", "bp", "si", "di" |
1ba53b71 L |
152 | }; |
153 | ||
01f9f808 MS |
154 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
155 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
156 | we have 16 upper ZMM regs that have to be handled differently. */ | |
157 | ||
158 | const int num_lower_zmm_regs = 16; | |
159 | ||
1ba53b71 | 160 | /* MMX register? */ |
c40e1eab | 161 | |
28fc6740 | 162 | static int |
5716833c | 163 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 164 | { |
1ba53b71 L |
165 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
166 | int mm0_regnum = tdep->mm0_regnum; | |
5716833c MK |
167 | |
168 | if (mm0_regnum < 0) | |
169 | return 0; | |
170 | ||
1ba53b71 L |
171 | regnum -= mm0_regnum; |
172 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
173 | } | |
174 | ||
175 | /* Byte register? */ | |
176 | ||
177 | int | |
178 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
179 | { | |
180 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
181 | ||
182 | regnum -= tdep->al_regnum; | |
183 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
184 | } | |
185 | ||
186 | /* Word register? */ | |
187 | ||
188 | int | |
189 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
190 | { | |
191 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
192 | ||
193 | regnum -= tdep->ax_regnum; | |
194 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
195 | } | |
196 | ||
197 | /* Dword register? */ | |
198 | ||
199 | int | |
200 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
201 | { | |
202 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
203 | int eax_regnum = tdep->eax_regnum; | |
204 | ||
205 | if (eax_regnum < 0) | |
206 | return 0; | |
207 | ||
208 | regnum -= eax_regnum; | |
209 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
210 | } |
211 | ||
01f9f808 MS |
212 | /* AVX512 register? */ |
213 | ||
214 | int | |
215 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
216 | { | |
217 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
218 | int zmm0h_regnum = tdep->zmm0h_regnum; | |
219 | ||
220 | if (zmm0h_regnum < 0) | |
221 | return 0; | |
222 | ||
223 | regnum -= zmm0h_regnum; | |
224 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
225 | } | |
226 | ||
227 | int | |
228 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
229 | { | |
230 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
231 | int zmm0_regnum = tdep->zmm0_regnum; | |
232 | ||
233 | if (zmm0_regnum < 0) | |
234 | return 0; | |
235 | ||
236 | regnum -= zmm0_regnum; | |
237 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
238 | } | |
239 | ||
240 | int | |
241 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
242 | { | |
243 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
244 | int k0_regnum = tdep->k0_regnum; | |
245 | ||
246 | if (k0_regnum < 0) | |
247 | return 0; | |
248 | ||
249 | regnum -= k0_regnum; | |
250 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
251 | } | |
252 | ||
9191d390 | 253 | static int |
c131fcee L |
254 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
255 | { | |
256 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
257 | int ymm0h_regnum = tdep->ymm0h_regnum; | |
258 | ||
259 | if (ymm0h_regnum < 0) | |
260 | return 0; | |
261 | ||
262 | regnum -= ymm0h_regnum; | |
263 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
264 | } | |
265 | ||
266 | /* AVX register? */ | |
267 | ||
268 | int | |
269 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
270 | { | |
271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
272 | int ymm0_regnum = tdep->ymm0_regnum; | |
273 | ||
274 | if (ymm0_regnum < 0) | |
275 | return 0; | |
276 | ||
277 | regnum -= ymm0_regnum; | |
278 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
279 | } | |
280 | ||
01f9f808 MS |
281 | static int |
282 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
283 | { | |
284 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
285 | int ymm16h_regnum = tdep->ymm16h_regnum; | |
286 | ||
287 | if (ymm16h_regnum < 0) | |
288 | return 0; | |
289 | ||
290 | regnum -= ymm16h_regnum; | |
291 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
292 | } | |
293 | ||
294 | int | |
295 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
296 | { | |
297 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
298 | int ymm16_regnum = tdep->ymm16_regnum; | |
299 | ||
300 | if (ymm16_regnum < 0) | |
301 | return 0; | |
302 | ||
303 | regnum -= ymm16_regnum; | |
304 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
305 | } | |
306 | ||
1dbcd68c WT |
307 | /* BND register? */ |
308 | ||
309 | int | |
310 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
311 | { | |
312 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
313 | int bnd0_regnum = tdep->bnd0_regnum; | |
314 | ||
315 | if (bnd0_regnum < 0) | |
316 | return 0; | |
317 | ||
318 | regnum -= bnd0_regnum; | |
319 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
320 | } | |
321 | ||
5716833c | 322 | /* SSE register? */ |
23a34459 | 323 | |
c131fcee L |
324 | int |
325 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 326 | { |
5716833c | 327 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c131fcee | 328 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 329 | |
c131fcee | 330 | if (num_xmm_regs == 0) |
5716833c MK |
331 | return 0; |
332 | ||
c131fcee L |
333 | regnum -= I387_XMM0_REGNUM (tdep); |
334 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
335 | } |
336 | ||
01f9f808 MS |
337 | /* XMM_512 register? */ |
338 | ||
339 | int | |
340 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
341 | { | |
342 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
343 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); | |
344 | ||
345 | if (num_xmm_avx512_regs == 0) | |
346 | return 0; | |
347 | ||
348 | regnum -= I387_XMM16_REGNUM (tdep); | |
349 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
350 | } | |
351 | ||
5716833c MK |
352 | static int |
353 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 354 | { |
5716833c MK |
355 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
356 | ||
20a6ec49 | 357 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
358 | return 0; |
359 | ||
20a6ec49 | 360 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
361 | } |
362 | ||
5716833c | 363 | /* FP register? */ |
23a34459 AC |
364 | |
365 | int | |
20a6ec49 | 366 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 367 | { |
20a6ec49 MD |
368 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
369 | ||
370 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
371 | return 0; |
372 | ||
20a6ec49 MD |
373 | return (I387_ST0_REGNUM (tdep) <= regnum |
374 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
375 | } |
376 | ||
377 | int | |
20a6ec49 | 378 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 379 | { |
20a6ec49 MD |
380 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
381 | ||
382 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
383 | return 0; |
384 | ||
20a6ec49 MD |
385 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
386 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
387 | } |
388 | ||
1dbcd68c WT |
389 | /* BNDr (raw) register? */ |
390 | ||
391 | static int | |
392 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
393 | { | |
394 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
395 | ||
396 | if (I387_BND0R_REGNUM (tdep) < 0) | |
397 | return 0; | |
398 | ||
399 | regnum -= tdep->bnd0r_regnum; | |
400 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
401 | } | |
402 | ||
403 | /* BND control register? */ | |
404 | ||
405 | static int | |
406 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
407 | { | |
408 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
409 | ||
410 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
411 | return 0; | |
412 | ||
413 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
414 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
415 | } | |
416 | ||
c131fcee L |
417 | /* Return the name of register REGNUM, or the empty string if it is |
418 | an anonymous register. */ | |
419 | ||
420 | static const char * | |
421 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
422 | { | |
423 | /* Hide the upper YMM registers. */ | |
424 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
425 | return ""; | |
426 | ||
01f9f808 MS |
427 | /* Hide the upper YMM16-31 registers. */ |
428 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
429 | return ""; | |
430 | ||
431 | /* Hide the upper ZMM registers. */ | |
432 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
433 | return ""; | |
434 | ||
c131fcee L |
435 | return tdesc_register_name (gdbarch, regnum); |
436 | } | |
437 | ||
30b0e2d8 | 438 | /* Return the name of register REGNUM. */ |
fc633446 | 439 | |
1ba53b71 | 440 | const char * |
90884b2b | 441 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 442 | { |
1ba53b71 | 443 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1dbcd68c WT |
444 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
445 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
446 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
447 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
448 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
449 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
450 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
451 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
452 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
453 | return i386_byte_names[regnum - tdep->al_regnum]; | |
454 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
455 | return i386_word_names[regnum - tdep->ax_regnum]; | |
456 | ||
457 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
fc633446 MK |
458 | } |
459 | ||
c4fc7f1b | 460 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
461 | number used by GDB. */ |
462 | ||
8201327c | 463 | static int |
d3f73121 | 464 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 465 | { |
20a6ec49 MD |
466 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
467 | ||
c4fc7f1b MK |
468 | /* This implements what GCC calls the "default" register map |
469 | (dbx_register_map[]). */ | |
470 | ||
85540d8c MK |
471 | if (reg >= 0 && reg <= 7) |
472 | { | |
9872ad24 JB |
473 | /* General-purpose registers. The debug info calls %ebp |
474 | register 4, and %esp register 5. */ | |
475 | if (reg == 4) | |
476 | return 5; | |
477 | else if (reg == 5) | |
478 | return 4; | |
479 | else return reg; | |
85540d8c MK |
480 | } |
481 | else if (reg >= 12 && reg <= 19) | |
482 | { | |
483 | /* Floating-point registers. */ | |
20a6ec49 | 484 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
485 | } |
486 | else if (reg >= 21 && reg <= 28) | |
487 | { | |
488 | /* SSE registers. */ | |
c131fcee L |
489 | int ymm0_regnum = tdep->ymm0_regnum; |
490 | ||
491 | if (ymm0_regnum >= 0 | |
492 | && i386_xmm_regnum_p (gdbarch, reg)) | |
493 | return reg - 21 + ymm0_regnum; | |
494 | else | |
495 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
496 | } |
497 | else if (reg >= 29 && reg <= 36) | |
498 | { | |
499 | /* MMX registers. */ | |
20a6ec49 | 500 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
501 | } |
502 | ||
503 | /* This will hopefully provoke a warning. */ | |
d3f73121 | 504 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
85540d8c MK |
505 | } |
506 | ||
0fde2c53 | 507 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 508 | used by GDB. */ |
85540d8c | 509 | |
8201327c | 510 | static int |
0fde2c53 | 511 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 512 | { |
20a6ec49 MD |
513 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
514 | ||
c4fc7f1b MK |
515 | /* This implements the GCC register map that tries to be compatible |
516 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
517 | ||
518 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
519 | numbers the floating point registers differently. */ |
520 | if (reg >= 0 && reg <= 9) | |
521 | { | |
acd5c798 | 522 | /* General-purpose registers. */ |
85540d8c MK |
523 | return reg; |
524 | } | |
525 | else if (reg >= 11 && reg <= 18) | |
526 | { | |
527 | /* Floating-point registers. */ | |
20a6ec49 | 528 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 529 | } |
c6f4c129 | 530 | else if (reg >= 21 && reg <= 36) |
85540d8c | 531 | { |
c4fc7f1b | 532 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 533 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
534 | } |
535 | ||
c6f4c129 JB |
536 | switch (reg) |
537 | { | |
20a6ec49 MD |
538 | case 37: return I387_FCTRL_REGNUM (tdep); |
539 | case 38: return I387_FSTAT_REGNUM (tdep); | |
540 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
541 | case 40: return I386_ES_REGNUM; |
542 | case 41: return I386_CS_REGNUM; | |
543 | case 42: return I386_SS_REGNUM; | |
544 | case 43: return I386_DS_REGNUM; | |
545 | case 44: return I386_FS_REGNUM; | |
546 | case 45: return I386_GS_REGNUM; | |
547 | } | |
548 | ||
0fde2c53 DE |
549 | return -1; |
550 | } | |
551 | ||
552 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
553 | num_regs + num_pseudo_regs for other debug formats. */ | |
554 | ||
555 | static int | |
556 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
557 | { | |
558 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
559 | ||
560 | if (regnum == -1) | |
561 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
562 | return regnum; | |
85540d8c | 563 | } |
5716833c | 564 | |
fc338970 | 565 | \f |
917317f4 | 566 | |
fc338970 MK |
567 | /* This is the variable that is set with "set disassembly-flavor", and |
568 | its legitimate values. */ | |
53904c9e AC |
569 | static const char att_flavor[] = "att"; |
570 | static const char intel_flavor[] = "intel"; | |
40478521 | 571 | static const char *const valid_flavors[] = |
c5aa993b | 572 | { |
c906108c SS |
573 | att_flavor, |
574 | intel_flavor, | |
575 | NULL | |
576 | }; | |
53904c9e | 577 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 578 | \f |
c906108c | 579 | |
acd5c798 MK |
580 | /* Use the program counter to determine the contents and size of a |
581 | breakpoint instruction. Return a pointer to a string of bytes that | |
582 | encode a breakpoint instruction, store the length of the string in | |
583 | *LEN and optionally adjust *PC to point to the correct memory | |
584 | location for inserting the breakpoint. | |
c906108c | 585 | |
acd5c798 MK |
586 | On the i386 we have a single breakpoint that fits in a single byte |
587 | and can be inserted anywhere. | |
c906108c | 588 | |
acd5c798 | 589 | This function is 64-bit safe. */ |
63c0089f | 590 | |
04180708 YQ |
591 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
592 | ||
593 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 594 | |
237fc4c9 PA |
595 | \f |
596 | /* Displaced instruction handling. */ | |
597 | ||
1903f0e6 DE |
598 | /* Skip the legacy instruction prefixes in INSN. |
599 | Not all prefixes are valid for any particular insn | |
600 | but we needn't care, the insn will fault if it's invalid. | |
601 | The result is a pointer to the first opcode byte, | |
602 | or NULL if we run off the end of the buffer. */ | |
603 | ||
604 | static gdb_byte * | |
605 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
606 | { | |
607 | gdb_byte *end = insn + max_len; | |
608 | ||
609 | while (insn < end) | |
610 | { | |
611 | switch (*insn) | |
612 | { | |
613 | case DATA_PREFIX_OPCODE: | |
614 | case ADDR_PREFIX_OPCODE: | |
615 | case CS_PREFIX_OPCODE: | |
616 | case DS_PREFIX_OPCODE: | |
617 | case ES_PREFIX_OPCODE: | |
618 | case FS_PREFIX_OPCODE: | |
619 | case GS_PREFIX_OPCODE: | |
620 | case SS_PREFIX_OPCODE: | |
621 | case LOCK_PREFIX_OPCODE: | |
622 | case REPE_PREFIX_OPCODE: | |
623 | case REPNE_PREFIX_OPCODE: | |
624 | ++insn; | |
625 | continue; | |
626 | default: | |
627 | return insn; | |
628 | } | |
629 | } | |
630 | ||
631 | return NULL; | |
632 | } | |
237fc4c9 PA |
633 | |
634 | static int | |
1903f0e6 | 635 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 636 | { |
1777feb0 | 637 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
638 | if (insn[0] == 0xea) |
639 | return 1; | |
640 | ||
641 | if (insn[0] == 0xff) | |
642 | { | |
1777feb0 | 643 | /* jump near, absolute indirect (/4). */ |
237fc4c9 PA |
644 | if ((insn[1] & 0x38) == 0x20) |
645 | return 1; | |
646 | ||
1777feb0 | 647 | /* jump far, absolute indirect (/5). */ |
237fc4c9 PA |
648 | if ((insn[1] & 0x38) == 0x28) |
649 | return 1; | |
650 | } | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
c2170eef MM |
655 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
656 | ||
657 | static int | |
658 | i386_jmp_p (const gdb_byte *insn) | |
659 | { | |
660 | /* jump short, relative. */ | |
661 | if (insn[0] == 0xeb) | |
662 | return 1; | |
663 | ||
664 | /* jump near, relative. */ | |
665 | if (insn[0] == 0xe9) | |
666 | return 1; | |
667 | ||
668 | return i386_absolute_jmp_p (insn); | |
669 | } | |
670 | ||
237fc4c9 | 671 | static int |
1903f0e6 | 672 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 673 | { |
1777feb0 | 674 | /* call far, absolute. */ |
237fc4c9 PA |
675 | if (insn[0] == 0x9a) |
676 | return 1; | |
677 | ||
678 | if (insn[0] == 0xff) | |
679 | { | |
1777feb0 | 680 | /* Call near, absolute indirect (/2). */ |
237fc4c9 PA |
681 | if ((insn[1] & 0x38) == 0x10) |
682 | return 1; | |
683 | ||
1777feb0 | 684 | /* Call far, absolute indirect (/3). */ |
237fc4c9 PA |
685 | if ((insn[1] & 0x38) == 0x18) |
686 | return 1; | |
687 | } | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | static int | |
1903f0e6 | 693 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
694 | { |
695 | switch (insn[0]) | |
696 | { | |
1777feb0 | 697 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 698 | case 0xc3: /* ret near */ |
1777feb0 | 699 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
700 | case 0xcb: /* ret far */ |
701 | case 0xcf: /* iret */ | |
702 | return 1; | |
703 | ||
704 | default: | |
705 | return 0; | |
706 | } | |
707 | } | |
708 | ||
709 | static int | |
1903f0e6 | 710 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
711 | { |
712 | if (i386_absolute_call_p (insn)) | |
713 | return 1; | |
714 | ||
1777feb0 | 715 | /* call near, relative. */ |
237fc4c9 PA |
716 | if (insn[0] == 0xe8) |
717 | return 1; | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
237fc4c9 PA |
722 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
723 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 724 | |
237fc4c9 | 725 | static int |
b55078be | 726 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 727 | { |
9a7f938f JK |
728 | /* Is it 'int $0x80'? */ |
729 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
730 | /* Or is it 'sysenter'? */ | |
731 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
732 | /* Or is it 'syscall'? */ | |
733 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
734 | { |
735 | *lengthp = 2; | |
736 | return 1; | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
c2170eef MM |
742 | /* The gdbarch insn_is_call method. */ |
743 | ||
744 | static int | |
745 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
746 | { | |
747 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
748 | ||
749 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
750 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
751 | ||
752 | return i386_call_p (insn); | |
753 | } | |
754 | ||
755 | /* The gdbarch insn_is_ret method. */ | |
756 | ||
757 | static int | |
758 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
759 | { | |
760 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
761 | ||
762 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
763 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
764 | ||
765 | return i386_ret_p (insn); | |
766 | } | |
767 | ||
768 | /* The gdbarch insn_is_jump method. */ | |
769 | ||
770 | static int | |
771 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
772 | { | |
773 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
774 | ||
775 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
776 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
777 | ||
778 | return i386_jmp_p (insn); | |
779 | } | |
780 | ||
b55078be DE |
781 | /* Some kernels may run one past a syscall insn, so we have to cope. |
782 | Otherwise this is just simple_displaced_step_copy_insn. */ | |
783 | ||
784 | struct displaced_step_closure * | |
785 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
786 | CORE_ADDR from, CORE_ADDR to, | |
787 | struct regcache *regs) | |
788 | { | |
789 | size_t len = gdbarch_max_insn_length (gdbarch); | |
224c3ddb | 790 | gdb_byte *buf = (gdb_byte *) xmalloc (len); |
b55078be DE |
791 | |
792 | read_memory (from, buf, len); | |
793 | ||
794 | /* GDB may get control back after the insn after the syscall. | |
795 | Presumably this is a kernel bug. | |
796 | If this is a syscall, make sure there's a nop afterwards. */ | |
797 | { | |
798 | int syscall_length; | |
799 | gdb_byte *insn; | |
800 | ||
801 | insn = i386_skip_prefixes (buf, len); | |
802 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
803 | insn[syscall_length] = NOP_OPCODE; | |
804 | } | |
805 | ||
806 | write_memory (to, buf, len); | |
807 | ||
808 | if (debug_displaced) | |
809 | { | |
810 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
811 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
812 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
813 | } | |
814 | ||
815 | return (struct displaced_step_closure *) buf; | |
816 | } | |
817 | ||
237fc4c9 PA |
818 | /* Fix up the state of registers and memory after having single-stepped |
819 | a displaced instruction. */ | |
1903f0e6 | 820 | |
237fc4c9 PA |
821 | void |
822 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
823 | struct displaced_step_closure *closure, | |
824 | CORE_ADDR from, CORE_ADDR to, | |
825 | struct regcache *regs) | |
826 | { | |
e17a4113 UW |
827 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
828 | ||
237fc4c9 PA |
829 | /* The offset we applied to the instruction's address. |
830 | This could well be negative (when viewed as a signed 32-bit | |
831 | value), but ULONGEST won't reflect that, so take care when | |
832 | applying it. */ | |
833 | ULONGEST insn_offset = to - from; | |
834 | ||
835 | /* Since we use simple_displaced_step_copy_insn, our closure is a | |
836 | copy of the instruction. */ | |
837 | gdb_byte *insn = (gdb_byte *) closure; | |
1903f0e6 DE |
838 | /* The start of the insn, needed in case we see some prefixes. */ |
839 | gdb_byte *insn_start = insn; | |
237fc4c9 PA |
840 | |
841 | if (debug_displaced) | |
842 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 | 843 | "displaced: fixup (%s, %s), " |
237fc4c9 | 844 | "insn = 0x%02x 0x%02x ...\n", |
5af949e3 UW |
845 | paddress (gdbarch, from), paddress (gdbarch, to), |
846 | insn[0], insn[1]); | |
237fc4c9 PA |
847 | |
848 | /* The list of issues to contend with here is taken from | |
849 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
850 | Yay for Free Software! */ | |
851 | ||
852 | /* Relocate the %eip, if necessary. */ | |
853 | ||
1903f0e6 DE |
854 | /* The instruction recognizers we use assume any leading prefixes |
855 | have been skipped. */ | |
856 | { | |
857 | /* This is the size of the buffer in closure. */ | |
858 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
859 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
860 | /* If there are too many prefixes, just ignore the insn. | |
861 | It will fault when run. */ | |
862 | if (opcode != NULL) | |
863 | insn = opcode; | |
864 | } | |
865 | ||
237fc4c9 PA |
866 | /* Except in the case of absolute or indirect jump or call |
867 | instructions, or a return instruction, the new eip is relative to | |
868 | the displaced instruction; make it relative. Well, signal | |
869 | handler returns don't need relocation either, but we use the | |
870 | value of %eip to recognize those; see below. */ | |
871 | if (! i386_absolute_jmp_p (insn) | |
872 | && ! i386_absolute_call_p (insn) | |
873 | && ! i386_ret_p (insn)) | |
874 | { | |
875 | ULONGEST orig_eip; | |
b55078be | 876 | int insn_len; |
237fc4c9 PA |
877 | |
878 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
879 | ||
880 | /* A signal trampoline system call changes the %eip, resuming | |
881 | execution of the main program after the signal handler has | |
882 | returned. That makes them like 'return' instructions; we | |
883 | shouldn't relocate %eip. | |
884 | ||
885 | But most system calls don't, and we do need to relocate %eip. | |
886 | ||
887 | Our heuristic for distinguishing these cases: if stepping | |
888 | over the system call instruction left control directly after | |
889 | the instruction, the we relocate --- control almost certainly | |
890 | doesn't belong in the displaced copy. Otherwise, we assume | |
891 | the instruction has put control where it belongs, and leave | |
892 | it unrelocated. Goodness help us if there are PC-relative | |
893 | system calls. */ | |
894 | if (i386_syscall_p (insn, &insn_len) | |
b55078be DE |
895 | && orig_eip != to + (insn - insn_start) + insn_len |
896 | /* GDB can get control back after the insn after the syscall. | |
897 | Presumably this is a kernel bug. | |
898 | i386_displaced_step_copy_insn ensures its a nop, | |
899 | we add one to the length for it. */ | |
900 | && orig_eip != to + (insn - insn_start) + insn_len + 1) | |
237fc4c9 PA |
901 | { |
902 | if (debug_displaced) | |
903 | fprintf_unfiltered (gdb_stdlog, | |
904 | "displaced: syscall changed %%eip; " | |
905 | "not relocating\n"); | |
906 | } | |
907 | else | |
908 | { | |
909 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
910 | ||
1903f0e6 DE |
911 | /* If we just stepped over a breakpoint insn, we don't backup |
912 | the pc on purpose; this is to match behaviour without | |
913 | stepping. */ | |
237fc4c9 PA |
914 | |
915 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); | |
916 | ||
917 | if (debug_displaced) | |
918 | fprintf_unfiltered (gdb_stdlog, | |
919 | "displaced: " | |
5af949e3 UW |
920 | "relocated %%eip from %s to %s\n", |
921 | paddress (gdbarch, orig_eip), | |
922 | paddress (gdbarch, eip)); | |
237fc4c9 PA |
923 | } |
924 | } | |
925 | ||
926 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
927 | pushed value, and should be cleared. We'll leave this for later, | |
928 | since GDB already messes up the TF flag when stepping over a | |
929 | pushfl. */ | |
930 | ||
931 | /* If the instruction was a call, the return address now atop the | |
932 | stack is the address following the copied instruction. We need | |
933 | to make it the address following the original instruction. */ | |
934 | if (i386_call_p (insn)) | |
935 | { | |
936 | ULONGEST esp; | |
937 | ULONGEST retaddr; | |
938 | const ULONGEST retaddr_len = 4; | |
939 | ||
940 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 941 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 942 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 943 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 PA |
944 | |
945 | if (debug_displaced) | |
946 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
947 | "displaced: relocated return addr at %s to %s\n", |
948 | paddress (gdbarch, esp), | |
949 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
950 | } |
951 | } | |
dde08ee1 PA |
952 | |
953 | static void | |
954 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
955 | { | |
956 | target_write_memory (*to, buf, len); | |
957 | *to += len; | |
958 | } | |
959 | ||
960 | static void | |
961 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
962 | CORE_ADDR *to, CORE_ADDR oldloc) | |
963 | { | |
964 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
965 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
966 | int offset = 0, rel32, newrel; | |
967 | int insn_length; | |
968 | gdb_byte *insn = buf; | |
969 | ||
970 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
971 | ||
972 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
973 | I386_MAX_INSN_LEN, oldloc); | |
974 | ||
975 | /* Get past the prefixes. */ | |
976 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
977 | ||
978 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
979 | the address pushed being the location where the original call in | |
980 | the user program would return to. */ | |
981 | if (insn[0] == 0xe8) | |
982 | { | |
983 | gdb_byte push_buf[16]; | |
984 | unsigned int ret_addr; | |
985 | ||
986 | /* Where "ret" in the original code will return to. */ | |
987 | ret_addr = oldloc + insn_length; | |
1777feb0 | 988 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 989 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
990 | /* Push the push. */ |
991 | append_insns (to, 5, push_buf); | |
992 | ||
993 | /* Convert the relative call to a relative jump. */ | |
994 | insn[0] = 0xe9; | |
995 | ||
996 | /* Adjust the destination offset. */ | |
997 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
998 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
999 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1000 | ||
1001 | if (debug_displaced) | |
1002 | fprintf_unfiltered (gdb_stdlog, | |
1003 | "Adjusted insn rel32=%s at %s to" | |
1004 | " rel32=%s at %s\n", | |
1005 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1006 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1007 | |
1008 | /* Write the adjusted jump into its displaced location. */ | |
1009 | append_insns (to, 5, insn); | |
1010 | return; | |
1011 | } | |
1012 | ||
1013 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1014 | handled above. */ | |
1015 | if (insn[0] == 0xe9) | |
1016 | offset = 1; | |
1017 | /* Adjust conditional jumps. */ | |
1018 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1019 | offset = 2; | |
1020 | ||
1021 | if (offset) | |
1022 | { | |
1023 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1024 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1025 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
dde08ee1 PA |
1026 | if (debug_displaced) |
1027 | fprintf_unfiltered (gdb_stdlog, | |
f4a1794a KY |
1028 | "Adjusted insn rel32=%s at %s to" |
1029 | " rel32=%s at %s\n", | |
dde08ee1 PA |
1030 | hex_string (rel32), paddress (gdbarch, oldloc), |
1031 | hex_string (newrel), paddress (gdbarch, *to)); | |
1032 | } | |
1033 | ||
1034 | /* Write the adjusted instructions into their displaced | |
1035 | location. */ | |
1036 | append_insns (to, insn_length, buf); | |
1037 | } | |
1038 | ||
fc338970 | 1039 | \f |
acd5c798 MK |
1040 | #ifdef I386_REGNO_TO_SYMMETRY |
1041 | #error "The Sequent Symmetry is no longer supported." | |
1042 | #endif | |
c906108c | 1043 | |
acd5c798 MK |
1044 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1045 | and %esp "belong" to the calling function. Therefore these | |
1046 | registers should be saved if they're going to be modified. */ | |
c906108c | 1047 | |
acd5c798 MK |
1048 | /* The maximum number of saved registers. This should include all |
1049 | registers mentioned above, and %eip. */ | |
a3386186 | 1050 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1051 | |
1052 | struct i386_frame_cache | |
c906108c | 1053 | { |
acd5c798 MK |
1054 | /* Base address. */ |
1055 | CORE_ADDR base; | |
8fbca658 | 1056 | int base_p; |
772562f8 | 1057 | LONGEST sp_offset; |
acd5c798 MK |
1058 | CORE_ADDR pc; |
1059 | ||
fd13a04a AC |
1060 | /* Saved registers. */ |
1061 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1062 | CORE_ADDR saved_sp; |
e0c62198 | 1063 | int saved_sp_reg; |
acd5c798 MK |
1064 | int pc_in_eax; |
1065 | ||
1066 | /* Stack space reserved for local variables. */ | |
1067 | long locals; | |
1068 | }; | |
1069 | ||
1070 | /* Allocate and initialize a frame cache. */ | |
1071 | ||
1072 | static struct i386_frame_cache * | |
fd13a04a | 1073 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1074 | { |
1075 | struct i386_frame_cache *cache; | |
1076 | int i; | |
1077 | ||
1078 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1079 | ||
1080 | /* Base address. */ | |
8fbca658 | 1081 | cache->base_p = 0; |
acd5c798 MK |
1082 | cache->base = 0; |
1083 | cache->sp_offset = -4; | |
1084 | cache->pc = 0; | |
1085 | ||
fd13a04a AC |
1086 | /* Saved registers. We initialize these to -1 since zero is a valid |
1087 | offset (that's where %ebp is supposed to be stored). */ | |
1088 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1089 | cache->saved_regs[i] = -1; | |
acd5c798 | 1090 | cache->saved_sp = 0; |
e0c62198 | 1091 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1092 | cache->pc_in_eax = 0; |
1093 | ||
1094 | /* Frameless until proven otherwise. */ | |
1095 | cache->locals = -1; | |
1096 | ||
1097 | return cache; | |
1098 | } | |
c906108c | 1099 | |
acd5c798 MK |
1100 | /* If the instruction at PC is a jump, return the address of its |
1101 | target. Otherwise, return PC. */ | |
c906108c | 1102 | |
acd5c798 | 1103 | static CORE_ADDR |
e17a4113 | 1104 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1105 | { |
e17a4113 | 1106 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1107 | gdb_byte op; |
acd5c798 MK |
1108 | long delta = 0; |
1109 | int data16 = 0; | |
c906108c | 1110 | |
0865b04a | 1111 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1112 | return pc; |
1113 | ||
acd5c798 | 1114 | if (op == 0x66) |
c906108c | 1115 | { |
c906108c | 1116 | data16 = 1; |
0865b04a YQ |
1117 | |
1118 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1119 | } |
1120 | ||
acd5c798 | 1121 | switch (op) |
c906108c SS |
1122 | { |
1123 | case 0xe9: | |
fc338970 | 1124 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1125 | if (data16) |
1126 | { | |
e17a4113 | 1127 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1128 | |
fc338970 MK |
1129 | /* Include the size of the jmp instruction (including the |
1130 | 0x66 prefix). */ | |
acd5c798 | 1131 | delta += 4; |
c906108c SS |
1132 | } |
1133 | else | |
1134 | { | |
e17a4113 | 1135 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1136 | |
acd5c798 MK |
1137 | /* Include the size of the jmp instruction. */ |
1138 | delta += 5; | |
c906108c SS |
1139 | } |
1140 | break; | |
1141 | case 0xeb: | |
fc338970 | 1142 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1143 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1144 | |
acd5c798 | 1145 | delta += data16 + 2; |
c906108c SS |
1146 | break; |
1147 | } | |
c906108c | 1148 | |
acd5c798 MK |
1149 | return pc + delta; |
1150 | } | |
fc338970 | 1151 | |
acd5c798 MK |
1152 | /* Check whether PC points at a prologue for a function returning a |
1153 | structure or union. If so, it updates CACHE and returns the | |
1154 | address of the first instruction after the code sequence that | |
1155 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1156 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1157 | |
acd5c798 MK |
1158 | static CORE_ADDR |
1159 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1160 | struct i386_frame_cache *cache) | |
c906108c | 1161 | { |
acd5c798 MK |
1162 | /* Functions that return a structure or union start with: |
1163 | ||
1164 | popl %eax 0x58 | |
1165 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
1166 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 | |
1167 | ||
1168 | (the System V compiler puts out the second `xchg' instruction, | |
1169 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1170 | gets generated). This sequence is used to get the address of the | |
1171 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1172 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1173 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1174 | gdb_byte buf[4]; | |
1175 | gdb_byte op; | |
c906108c | 1176 | |
acd5c798 MK |
1177 | if (current_pc <= pc) |
1178 | return pc; | |
1179 | ||
0865b04a | 1180 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1181 | return pc; |
c906108c | 1182 | |
acd5c798 MK |
1183 | if (op != 0x58) /* popl %eax */ |
1184 | return pc; | |
c906108c | 1185 | |
0865b04a | 1186 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1187 | return pc; |
1188 | ||
acd5c798 MK |
1189 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1190 | return pc; | |
c906108c | 1191 | |
acd5c798 | 1192 | if (current_pc == pc) |
c906108c | 1193 | { |
acd5c798 MK |
1194 | cache->sp_offset += 4; |
1195 | return current_pc; | |
c906108c SS |
1196 | } |
1197 | ||
acd5c798 | 1198 | if (current_pc == pc + 1) |
c906108c | 1199 | { |
acd5c798 MK |
1200 | cache->pc_in_eax = 1; |
1201 | return current_pc; | |
1202 | } | |
1203 | ||
1204 | if (buf[1] == proto1[1]) | |
1205 | return pc + 4; | |
1206 | else | |
1207 | return pc + 5; | |
1208 | } | |
1209 | ||
1210 | static CORE_ADDR | |
1211 | i386_skip_probe (CORE_ADDR pc) | |
1212 | { | |
1213 | /* A function may start with | |
fc338970 | 1214 | |
acd5c798 MK |
1215 | pushl constant |
1216 | call _probe | |
1217 | addl $4, %esp | |
fc338970 | 1218 | |
acd5c798 MK |
1219 | followed by |
1220 | ||
1221 | pushl %ebp | |
fc338970 | 1222 | |
acd5c798 | 1223 | etc. */ |
63c0089f MK |
1224 | gdb_byte buf[8]; |
1225 | gdb_byte op; | |
fc338970 | 1226 | |
0865b04a | 1227 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1228 | return pc; |
acd5c798 MK |
1229 | |
1230 | if (op == 0x68 || op == 0x6a) | |
1231 | { | |
1232 | int delta; | |
c906108c | 1233 | |
acd5c798 MK |
1234 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1235 | four-byte operand, depending on the opcode. */ | |
c906108c | 1236 | if (op == 0x68) |
acd5c798 | 1237 | delta = 5; |
c906108c | 1238 | else |
acd5c798 | 1239 | delta = 2; |
c906108c | 1240 | |
acd5c798 MK |
1241 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1242 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1243 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1244 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1245 | pc += delta + sizeof (buf); |
c906108c SS |
1246 | } |
1247 | ||
acd5c798 MK |
1248 | return pc; |
1249 | } | |
1250 | ||
92dd43fa MK |
1251 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1252 | stack pointer. Check whether PC points to such code, and update | |
1253 | CACHE accordingly. Return the first instruction after the code | |
1254 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1255 | recognize the code, return PC. */ | |
1256 | ||
1257 | static CORE_ADDR | |
1258 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1259 | struct i386_frame_cache *cache) | |
1260 | { | |
e0c62198 L |
1261 | /* There are 2 code sequences to re-align stack before the frame |
1262 | gets set up: | |
1263 | ||
1264 | 1. Use a caller-saved saved register: | |
1265 | ||
1266 | leal 4(%esp), %reg | |
1267 | andl $-XXX, %esp | |
1268 | pushl -4(%reg) | |
1269 | ||
1270 | 2. Use a callee-saved saved register: | |
1271 | ||
1272 | pushl %reg | |
1273 | leal 8(%esp), %reg | |
1274 | andl $-XXX, %esp | |
1275 | pushl -4(%reg) | |
1276 | ||
1277 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1278 | ||
1279 | 0x83 0xe4 0xf0 andl $-16, %esp | |
1280 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
1281 | */ | |
1282 | ||
1283 | gdb_byte buf[14]; | |
1284 | int reg; | |
1285 | int offset, offset_and; | |
1286 | static int regnums[8] = { | |
1287 | I386_EAX_REGNUM, /* %eax */ | |
1288 | I386_ECX_REGNUM, /* %ecx */ | |
1289 | I386_EDX_REGNUM, /* %edx */ | |
1290 | I386_EBX_REGNUM, /* %ebx */ | |
1291 | I386_ESP_REGNUM, /* %esp */ | |
1292 | I386_EBP_REGNUM, /* %ebp */ | |
1293 | I386_ESI_REGNUM, /* %esi */ | |
1294 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1295 | }; |
92dd43fa | 1296 | |
0865b04a | 1297 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1298 | return pc; |
1299 | ||
1300 | /* Check caller-saved saved register. The first instruction has | |
1301 | to be "leal 4(%esp), %reg". */ | |
1302 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1303 | { | |
1304 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1305 | if ((buf[1] & 0xc7) != 0x44) | |
1306 | return pc; | |
1307 | ||
1308 | /* REG has register number. */ | |
1309 | reg = (buf[1] >> 3) & 7; | |
1310 | offset = 4; | |
1311 | } | |
1312 | else | |
1313 | { | |
1314 | /* Check callee-saved saved register. The first instruction | |
1315 | has to be "pushl %reg". */ | |
1316 | if ((buf[0] & 0xf8) != 0x50) | |
1317 | return pc; | |
1318 | ||
1319 | /* Get register. */ | |
1320 | reg = buf[0] & 0x7; | |
1321 | ||
1322 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1323 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1324 | return pc; | |
1325 | ||
1326 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1327 | if ((buf[2] & 0xc7) != 0x44) | |
1328 | return pc; | |
1329 | ||
1330 | /* REG has register number. Registers in pushl and leal have to | |
1331 | be the same. */ | |
1332 | if (reg != ((buf[2] >> 3) & 7)) | |
1333 | return pc; | |
1334 | ||
1335 | offset = 5; | |
1336 | } | |
1337 | ||
1338 | /* Rigister can't be %esp nor %ebp. */ | |
1339 | if (reg == 4 || reg == 5) | |
1340 | return pc; | |
1341 | ||
1342 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1343 | if (buf[offset + 1] != 0xe4 | |
1344 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1345 | return pc; | |
1346 | ||
1347 | offset_and = offset; | |
1348 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1349 | ||
1350 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1351 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1352 | if (buf[offset] != 0xff | |
1353 | || buf[offset + 2] != 0xfc | |
1354 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1355 | return pc; | |
1356 | ||
1357 | /* R/M has register. Registers in leal and pushl have to be the | |
1358 | same. */ | |
1359 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1360 | return pc; |
1361 | ||
e0c62198 L |
1362 | if (current_pc > pc + offset_and) |
1363 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1364 | |
325fac50 | 1365 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1366 | } |
1367 | ||
37bdc87e | 1368 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1369 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1370 | |
1371 | /* Instruction description. */ | |
1372 | struct i386_insn | |
1373 | { | |
1374 | size_t len; | |
237fc4c9 PA |
1375 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1376 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1377 | }; |
1378 | ||
a3fcb948 | 1379 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1380 | |
a3fcb948 JG |
1381 | static int |
1382 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1383 | { |
63c0089f | 1384 | gdb_byte op; |
37bdc87e | 1385 | |
0865b04a | 1386 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1387 | return 0; |
37bdc87e | 1388 | |
a3fcb948 | 1389 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1390 | { |
a3fcb948 JG |
1391 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1392 | int insn_matched = 1; | |
1393 | size_t i; | |
37bdc87e | 1394 | |
a3fcb948 JG |
1395 | gdb_assert (pattern.len > 1); |
1396 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1397 | |
0865b04a | 1398 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1399 | return 0; |
613e8135 | 1400 | |
a3fcb948 JG |
1401 | for (i = 1; i < pattern.len; i++) |
1402 | { | |
1403 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1404 | insn_matched = 0; | |
37bdc87e | 1405 | } |
a3fcb948 JG |
1406 | return insn_matched; |
1407 | } | |
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1412 | the first instruction description that matches. Otherwise, return | |
1413 | NULL. */ | |
1414 | ||
1415 | static struct i386_insn * | |
1416 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1417 | { | |
1418 | struct i386_insn *pattern; | |
1419 | ||
1420 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1421 | { | |
1422 | if (i386_match_pattern (pc, *pattern)) | |
1423 | return pattern; | |
37bdc87e MK |
1424 | } |
1425 | ||
1426 | return NULL; | |
1427 | } | |
1428 | ||
a3fcb948 JG |
1429 | /* Return whether PC points inside a sequence of instructions that |
1430 | matches INSN_PATTERNS. */ | |
1431 | ||
1432 | static int | |
1433 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1434 | { | |
1435 | CORE_ADDR current_pc; | |
1436 | int ix, i; | |
a3fcb948 JG |
1437 | struct i386_insn *insn; |
1438 | ||
1439 | insn = i386_match_insn (pc, insn_patterns); | |
1440 | if (insn == NULL) | |
1441 | return 0; | |
1442 | ||
8bbdd3f4 | 1443 | current_pc = pc; |
a3fcb948 JG |
1444 | ix = insn - insn_patterns; |
1445 | for (i = ix - 1; i >= 0; i--) | |
1446 | { | |
8bbdd3f4 MK |
1447 | current_pc -= insn_patterns[i].len; |
1448 | ||
a3fcb948 JG |
1449 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1450 | return 0; | |
a3fcb948 JG |
1451 | } |
1452 | ||
1453 | current_pc = pc + insn->len; | |
1454 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1455 | { | |
1456 | if (!i386_match_pattern (current_pc, *insn)) | |
1457 | return 0; | |
1458 | ||
1459 | current_pc += insn->len; | |
1460 | } | |
1461 | ||
1462 | return 1; | |
1463 | } | |
1464 | ||
37bdc87e MK |
1465 | /* Some special instructions that might be migrated by GCC into the |
1466 | part of the prologue that sets up the new stack frame. Because the | |
1467 | stack frame hasn't been setup yet, no registers have been saved | |
1468 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1469 | touched. */ | |
1470 | ||
1471 | struct i386_insn i386_frame_setup_skip_insns[] = | |
1472 | { | |
1777feb0 | 1473 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1474 | |
1475 | ??? Should we handle 16-bit operand-sizes here? */ | |
1476 | ||
1477 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1478 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1479 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1480 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1481 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1482 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1483 | { 5, { 0xb8 }, { 0xfe } }, | |
1484 | /* `movl imm32, %edx' */ | |
1485 | { 5, { 0xba }, { 0xff } }, | |
1486 | ||
1487 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1488 | encoding for `mov m32, %eax'. | |
1489 | ||
1490 | ??? Should we handle SIB adressing here? | |
1491 | ??? Should we handle 16-bit operand-sizes here? */ | |
1492 | ||
1493 | /* `movl m32, %eax' */ | |
1494 | { 5, { 0xa1 }, { 0xff } }, | |
1495 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1496 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1497 | /* `movl m32, %edx' */ | |
1498 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1499 | ||
1500 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1501 | Because of the symmetry, there are actually two ways to encode | |
1502 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1503 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1504 | ||
1505 | /* `subl %eax, %eax' */ | |
1506 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1507 | /* `subl %ecx, %ecx' */ | |
1508 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1509 | /* `subl %edx, %edx' */ | |
1510 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1511 | /* `xorl %eax, %eax' */ | |
1512 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1513 | /* `xorl %ecx, %ecx' */ | |
1514 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1515 | /* `xorl %edx, %edx' */ | |
1516 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1517 | { 0 } | |
1518 | }; | |
1519 | ||
e11481da PM |
1520 | |
1521 | /* Check whether PC points to a no-op instruction. */ | |
1522 | static CORE_ADDR | |
1523 | i386_skip_noop (CORE_ADDR pc) | |
1524 | { | |
1525 | gdb_byte op; | |
1526 | int check = 1; | |
1527 | ||
0865b04a | 1528 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1529 | return pc; |
e11481da PM |
1530 | |
1531 | while (check) | |
1532 | { | |
1533 | check = 0; | |
1534 | /* Ignore `nop' instruction. */ | |
1535 | if (op == 0x90) | |
1536 | { | |
1537 | pc += 1; | |
0865b04a | 1538 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1539 | return pc; |
e11481da PM |
1540 | check = 1; |
1541 | } | |
1542 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1543 | Microsoft system dlls often start with | |
1544 | a `mov %edi,%edi' instruction. | |
1545 | The 5 bytes before the function start are | |
1546 | filled with `nop' instructions. | |
1547 | This pattern can be used for hot-patching: | |
1548 | The `mov %edi, %edi' instruction can be replaced by a | |
1549 | near jump to the location of the 5 `nop' instructions | |
1550 | which can be replaced by a 32-bit jump to anywhere | |
1551 | in the 32-bit address space. */ | |
1552 | ||
1553 | else if (op == 0x8b) | |
1554 | { | |
0865b04a | 1555 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1556 | return pc; |
1557 | ||
e11481da PM |
1558 | if (op == 0xff) |
1559 | { | |
1560 | pc += 2; | |
0865b04a | 1561 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1562 | return pc; |
1563 | ||
e11481da PM |
1564 | check = 1; |
1565 | } | |
1566 | } | |
1567 | } | |
1568 | return pc; | |
1569 | } | |
1570 | ||
acd5c798 MK |
1571 | /* Check whether PC points at a code that sets up a new stack frame. |
1572 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1573 | instruction after the sequence that sets up the frame or LIMIT, |
1574 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1575 | |
1576 | static CORE_ADDR | |
e17a4113 UW |
1577 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1578 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1579 | struct i386_frame_cache *cache) |
1580 | { | |
e17a4113 | 1581 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1582 | struct i386_insn *insn; |
63c0089f | 1583 | gdb_byte op; |
26604a34 | 1584 | int skip = 0; |
acd5c798 | 1585 | |
37bdc87e MK |
1586 | if (limit <= pc) |
1587 | return limit; | |
acd5c798 | 1588 | |
0865b04a | 1589 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1590 | return pc; |
acd5c798 | 1591 | |
c906108c | 1592 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1593 | { |
acd5c798 MK |
1594 | /* Take into account that we've executed the `pushl %ebp' that |
1595 | starts this instruction sequence. */ | |
fd13a04a | 1596 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1597 | cache->sp_offset += 4; |
37bdc87e | 1598 | pc++; |
acd5c798 MK |
1599 | |
1600 | /* If that's all, return now. */ | |
37bdc87e MK |
1601 | if (limit <= pc) |
1602 | return limit; | |
26604a34 | 1603 | |
b4632131 | 1604 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1605 | GCC into the prologue and skip them. At this point in the |
1606 | prologue, code should only touch the scratch registers %eax, | |
1607 | %ecx and %edx, so while the number of posibilities is sheer, | |
1608 | it is limited. | |
5daa5b4e | 1609 | |
26604a34 MK |
1610 | Make sure we only skip these instructions if we later see the |
1611 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1612 | while (pc + skip < limit) |
26604a34 | 1613 | { |
37bdc87e MK |
1614 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1615 | if (insn == NULL) | |
1616 | break; | |
b4632131 | 1617 | |
37bdc87e | 1618 | skip += insn->len; |
26604a34 MK |
1619 | } |
1620 | ||
37bdc87e MK |
1621 | /* If that's all, return now. */ |
1622 | if (limit <= pc + skip) | |
1623 | return limit; | |
1624 | ||
0865b04a | 1625 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1626 | return pc + skip; |
37bdc87e | 1627 | |
30f8135b YQ |
1628 | /* The i386 prologue looks like |
1629 | ||
1630 | push %ebp | |
1631 | mov %esp,%ebp | |
1632 | sub $0x10,%esp | |
1633 | ||
1634 | and a different prologue can be generated for atom. | |
1635 | ||
1636 | push %ebp | |
1637 | lea (%esp),%ebp | |
1638 | lea -0x10(%esp),%esp | |
1639 | ||
1640 | We handle both of them here. */ | |
1641 | ||
acd5c798 | 1642 | switch (op) |
c906108c | 1643 | { |
30f8135b | 1644 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1645 | case 0x8b: |
0865b04a | 1646 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1647 | != 0xec) |
37bdc87e | 1648 | return pc; |
30f8135b | 1649 | pc += (skip + 2); |
c906108c SS |
1650 | break; |
1651 | case 0x89: | |
0865b04a | 1652 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1653 | != 0xe5) |
37bdc87e | 1654 | return pc; |
30f8135b YQ |
1655 | pc += (skip + 2); |
1656 | break; | |
1657 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1658 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1659 | != 0x242c) |
1660 | return pc; | |
1661 | pc += (skip + 3); | |
c906108c SS |
1662 | break; |
1663 | default: | |
37bdc87e | 1664 | return pc; |
c906108c | 1665 | } |
acd5c798 | 1666 | |
26604a34 MK |
1667 | /* OK, we actually have a frame. We just don't know how large |
1668 | it is yet. Set its size to zero. We'll adjust it if | |
1669 | necessary. We also now commit to skipping the special | |
1670 | instructions mentioned before. */ | |
acd5c798 MK |
1671 | cache->locals = 0; |
1672 | ||
1673 | /* If that's all, return now. */ | |
37bdc87e MK |
1674 | if (limit <= pc) |
1675 | return limit; | |
acd5c798 | 1676 | |
fc338970 MK |
1677 | /* Check for stack adjustment |
1678 | ||
acd5c798 | 1679 | subl $XXX, %esp |
30f8135b YQ |
1680 | or |
1681 | lea -XXX(%esp),%esp | |
fc338970 | 1682 | |
fd35795f | 1683 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1684 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1685 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1686 | return pc; |
c906108c SS |
1687 | if (op == 0x83) |
1688 | { | |
fd35795f | 1689 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1690 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1691 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1692 | return pc; |
acd5c798 | 1693 | |
37bdc87e MK |
1694 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1695 | make sense to be negative). */ | |
0865b04a | 1696 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1697 | return pc + 3; |
c906108c SS |
1698 | } |
1699 | else if (op == 0x81) | |
1700 | { | |
fd35795f | 1701 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1702 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1703 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1704 | return pc; |
acd5c798 | 1705 | |
fd35795f | 1706 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1707 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1708 | return pc + 6; |
c906108c | 1709 | } |
30f8135b YQ |
1710 | else if (op == 0x8d) |
1711 | { | |
1712 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1713 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1714 | return pc; |
1715 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1716 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1717 | return pc + 4; |
1718 | } | |
c906108c SS |
1719 | else |
1720 | { | |
30f8135b | 1721 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1722 | return pc; |
c906108c SS |
1723 | } |
1724 | } | |
37bdc87e | 1725 | else if (op == 0xc8) /* enter */ |
c906108c | 1726 | { |
0865b04a | 1727 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1728 | return pc + 4; |
c906108c | 1729 | } |
21d0e8a4 | 1730 | |
acd5c798 | 1731 | return pc; |
21d0e8a4 MK |
1732 | } |
1733 | ||
acd5c798 MK |
1734 | /* Check whether PC points at code that saves registers on the stack. |
1735 | If so, it updates CACHE and returns the address of the first | |
1736 | instruction after the register saves or CURRENT_PC, whichever is | |
1737 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1738 | |
1739 | static CORE_ADDR | |
acd5c798 MK |
1740 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1741 | struct i386_frame_cache *cache) | |
6bff26de | 1742 | { |
99ab4326 | 1743 | CORE_ADDR offset = 0; |
63c0089f | 1744 | gdb_byte op; |
99ab4326 | 1745 | int i; |
c0d1d883 | 1746 | |
99ab4326 MK |
1747 | if (cache->locals > 0) |
1748 | offset -= cache->locals; | |
1749 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1750 | { | |
0865b04a | 1751 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1752 | return pc; |
99ab4326 MK |
1753 | if (op < 0x50 || op > 0x57) |
1754 | break; | |
0d17c81d | 1755 | |
99ab4326 MK |
1756 | offset -= 4; |
1757 | cache->saved_regs[op - 0x50] = offset; | |
1758 | cache->sp_offset += 4; | |
1759 | pc++; | |
6bff26de MK |
1760 | } |
1761 | ||
acd5c798 | 1762 | return pc; |
22797942 AC |
1763 | } |
1764 | ||
acd5c798 MK |
1765 | /* Do a full analysis of the prologue at PC and update CACHE |
1766 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1767 | address where the analysis stopped. | |
ed84f6c1 | 1768 | |
fc338970 MK |
1769 | We handle these cases: |
1770 | ||
1771 | The startup sequence can be at the start of the function, or the | |
1772 | function can start with a branch to startup code at the end. | |
1773 | ||
1774 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1775 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1776 | once used in the System V compiler). | |
1777 | ||
1778 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1779 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1780 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1781 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1782 | |
1783 | Next, the registers used by this function are pushed. With the | |
1784 | System V compiler they will always be in the order: %edi, %esi, | |
1785 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1786 | restore %eax); however, the code below is willing to see the pushes | |
1787 | in any order, and will handle up to 8 of them. | |
1788 | ||
1789 | If the setup sequence is at the end of the function, then the next | |
1790 | instruction will be a branch back to the start. */ | |
c906108c | 1791 | |
acd5c798 | 1792 | static CORE_ADDR |
e17a4113 UW |
1793 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1794 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1795 | struct i386_frame_cache *cache) |
c906108c | 1796 | { |
e11481da | 1797 | pc = i386_skip_noop (pc); |
e17a4113 | 1798 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1799 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1800 | pc = i386_skip_probe (pc); | |
92dd43fa | 1801 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1802 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1803 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1804 | } |
1805 | ||
fc338970 | 1806 | /* Return PC of first real instruction. */ |
c906108c | 1807 | |
3a1e71e3 | 1808 | static CORE_ADDR |
6093d2eb | 1809 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1810 | { |
e17a4113 UW |
1811 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1812 | ||
63c0089f | 1813 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1814 | { |
1815 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1816 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1817 | }; |
acd5c798 MK |
1818 | struct i386_frame_cache cache; |
1819 | CORE_ADDR pc; | |
63c0089f | 1820 | gdb_byte op; |
acd5c798 | 1821 | int i; |
56bf0743 | 1822 | CORE_ADDR func_addr; |
4e879fc2 | 1823 | |
56bf0743 KB |
1824 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1825 | { | |
1826 | CORE_ADDR post_prologue_pc | |
1827 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1828 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 KB |
1829 | |
1830 | /* Clang always emits a line note before the prologue and another | |
1831 | one after. We trust clang to emit usable line notes. */ | |
1832 | if (post_prologue_pc | |
43f3e411 DE |
1833 | && (cust != NULL |
1834 | && COMPUNIT_PRODUCER (cust) != NULL | |
61012eef | 1835 | && startswith (COMPUNIT_PRODUCER (cust), "clang "))) |
325fac50 | 1836 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1837 | } |
1838 | ||
e0f33b1f | 1839 | cache.locals = -1; |
e17a4113 | 1840 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1841 | if (cache.locals < 0) |
1842 | return start_pc; | |
c5aa993b | 1843 | |
acd5c798 | 1844 | /* Found valid frame setup. */ |
c906108c | 1845 | |
fc338970 MK |
1846 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1847 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1848 | %ebx: |
1849 | ||
fc338970 MK |
1850 | call 0x0 |
1851 | popl %ebx | |
1852 | movl %ebx,x(%ebp) (optional) | |
1853 | addl y,%ebx | |
1854 | ||
c906108c SS |
1855 | This code is with the rest of the prologue (at the end of the |
1856 | function), so we have to skip it to get to the first real | |
1857 | instruction at the start of the function. */ | |
c5aa993b | 1858 | |
c906108c SS |
1859 | for (i = 0; i < 6; i++) |
1860 | { | |
0865b04a | 1861 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1862 | return pc; |
1863 | ||
c5aa993b | 1864 | if (pic_pat[i] != op) |
c906108c SS |
1865 | break; |
1866 | } | |
1867 | if (i == 6) | |
1868 | { | |
acd5c798 MK |
1869 | int delta = 6; |
1870 | ||
0865b04a | 1871 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1872 | return pc; |
c906108c | 1873 | |
c5aa993b | 1874 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1875 | { |
0865b04a | 1876 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1877 | |
fc338970 | 1878 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1879 | delta += 3; |
fc338970 | 1880 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1881 | delta += 6; |
fc338970 | 1882 | else /* Unexpected instruction. */ |
acd5c798 MK |
1883 | delta = 0; |
1884 | ||
0865b04a | 1885 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1886 | return pc; |
c906108c | 1887 | } |
acd5c798 | 1888 | |
c5aa993b | 1889 | /* addl y,%ebx */ |
acd5c798 | 1890 | if (delta > 0 && op == 0x81 |
0865b04a | 1891 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1892 | == 0xc3) |
c906108c | 1893 | { |
acd5c798 | 1894 | pc += delta + 6; |
c906108c SS |
1895 | } |
1896 | } | |
c5aa993b | 1897 | |
e63bbc88 MK |
1898 | /* If the function starts with a branch (to startup code at the end) |
1899 | the last instruction should bring us back to the first | |
1900 | instruction of the real code. */ | |
e17a4113 UW |
1901 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1902 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1903 | |
1904 | return pc; | |
c906108c SS |
1905 | } |
1906 | ||
4309257c PM |
1907 | /* Check that the code pointed to by PC corresponds to a call to |
1908 | __main, skip it if so. Return PC otherwise. */ | |
1909 | ||
1910 | CORE_ADDR | |
1911 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1912 | { | |
e17a4113 | 1913 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1914 | gdb_byte op; |
1915 | ||
0865b04a | 1916 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1917 | return pc; |
4309257c PM |
1918 | if (op == 0xe8) |
1919 | { | |
1920 | gdb_byte buf[4]; | |
1921 | ||
0865b04a | 1922 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
4309257c PM |
1923 | { |
1924 | /* Make sure address is computed correctly as a 32bit | |
1925 | integer even if CORE_ADDR is 64 bit wide. */ | |
7cbd4a93 | 1926 | struct bound_minimal_symbol s; |
e17a4113 | 1927 | CORE_ADDR call_dest; |
4309257c | 1928 | |
e17a4113 | 1929 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c PM |
1930 | call_dest = call_dest & 0xffffffffU; |
1931 | s = lookup_minimal_symbol_by_pc (call_dest); | |
7cbd4a93 | 1932 | if (s.minsym != NULL |
efd66ac6 TT |
1933 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
1934 | && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) | |
4309257c PM |
1935 | pc += 5; |
1936 | } | |
1937 | } | |
1938 | ||
1939 | return pc; | |
1940 | } | |
1941 | ||
acd5c798 | 1942 | /* This function is 64-bit safe. */ |
93924b6b | 1943 | |
acd5c798 MK |
1944 | static CORE_ADDR |
1945 | i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
93924b6b | 1946 | { |
63c0089f | 1947 | gdb_byte buf[8]; |
acd5c798 | 1948 | |
875f8d0e | 1949 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1950 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1951 | } |
acd5c798 | 1952 | \f |
93924b6b | 1953 | |
acd5c798 | 1954 | /* Normal frames. */ |
c5aa993b | 1955 | |
8fbca658 PA |
1956 | static void |
1957 | i386_frame_cache_1 (struct frame_info *this_frame, | |
1958 | struct i386_frame_cache *cache) | |
a7769679 | 1959 | { |
e17a4113 UW |
1960 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1961 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1962 | gdb_byte buf[4]; |
acd5c798 MK |
1963 | int i; |
1964 | ||
8fbca658 | 1965 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1966 | |
1967 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1968 | which holds the base address for the current stack frame. | |
1969 | However, for functions that don't need it, the frame pointer is | |
1970 | optional. For these "frameless" functions the frame pointer is | |
1971 | actually the frame pointer of the calling frame. Signal | |
1972 | trampolines are just a special case of a "frameless" function. | |
1973 | They (usually) share their frame pointer with the frame that was | |
1974 | in progress when the signal occurred. */ | |
1975 | ||
10458914 | 1976 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 1977 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 1978 | if (cache->base == 0) |
620fa63a PA |
1979 | { |
1980 | cache->base_p = 1; | |
1981 | return; | |
1982 | } | |
acd5c798 MK |
1983 | |
1984 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 1985 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 1986 | |
acd5c798 | 1987 | if (cache->pc != 0) |
e17a4113 UW |
1988 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
1989 | cache); | |
acd5c798 MK |
1990 | |
1991 | if (cache->locals < 0) | |
1992 | { | |
1993 | /* We didn't find a valid frame, which means that CACHE->base | |
1994 | currently holds the frame pointer for our calling frame. If | |
1995 | we're at the start of a function, or somewhere half-way its | |
1996 | prologue, the function's frame probably hasn't been fully | |
1997 | setup yet. Try to reconstruct the base address for the stack | |
1998 | frame by looking at the stack pointer. For truly "frameless" | |
1999 | functions this might work too. */ | |
2000 | ||
e0c62198 | 2001 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2002 | { |
8fbca658 PA |
2003 | /* Saved stack pointer has been saved. */ |
2004 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2005 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2006 | ||
92dd43fa MK |
2007 | /* We're halfway aligning the stack. */ |
2008 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2009 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2010 | ||
2011 | /* This will be added back below. */ | |
2012 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2013 | } | |
7618e12b | 2014 | else if (cache->pc != 0 |
0865b04a | 2015 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2016 | { |
7618e12b DJ |
2017 | /* We're in a known function, but did not find a frame |
2018 | setup. Assume that the function does not use %ebp. | |
2019 | Alternatively, we may have jumped to an invalid | |
2020 | address; in that case there is definitely no new | |
2021 | frame in %ebp. */ | |
10458914 | 2022 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2023 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2024 | + cache->sp_offset; | |
92dd43fa | 2025 | } |
7618e12b DJ |
2026 | else |
2027 | /* We're in an unknown function. We could not find the start | |
2028 | of the function to analyze the prologue; our best option is | |
2029 | to assume a typical frame layout with the caller's %ebp | |
2030 | saved. */ | |
2031 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2032 | } |
2033 | ||
8fbca658 PA |
2034 | if (cache->saved_sp_reg != -1) |
2035 | { | |
2036 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2037 | register may be unavailable). */ | |
2038 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2039 | && deprecated_frame_register_read (this_frame, |
2040 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2041 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2042 | } | |
acd5c798 MK |
2043 | /* Now that we have the base address for the stack frame we can |
2044 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2045 | else if (cache->saved_sp == 0) |
92dd43fa | 2046 | cache->saved_sp = cache->base + 8; |
a7769679 | 2047 | |
acd5c798 MK |
2048 | /* Adjust all the saved registers such that they contain addresses |
2049 | instead of offsets. */ | |
2050 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2051 | if (cache->saved_regs[i] != -1) |
2052 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2053 | |
8fbca658 PA |
2054 | cache->base_p = 1; |
2055 | } | |
2056 | ||
2057 | static struct i386_frame_cache * | |
2058 | i386_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2059 | { | |
8fbca658 PA |
2060 | struct i386_frame_cache *cache; |
2061 | ||
2062 | if (*this_cache) | |
9a3c8263 | 2063 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2064 | |
2065 | cache = i386_alloc_frame_cache (); | |
2066 | *this_cache = cache; | |
2067 | ||
492d29ea | 2068 | TRY |
8fbca658 PA |
2069 | { |
2070 | i386_frame_cache_1 (this_frame, cache); | |
2071 | } | |
492d29ea | 2072 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2073 | { |
2074 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2075 | throw_exception (ex); | |
2076 | } | |
492d29ea | 2077 | END_CATCH |
8fbca658 | 2078 | |
acd5c798 | 2079 | return cache; |
a7769679 MK |
2080 | } |
2081 | ||
3a1e71e3 | 2082 | static void |
10458914 | 2083 | i386_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 | 2084 | struct frame_id *this_id) |
c906108c | 2085 | { |
10458914 | 2086 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2087 | |
5ce0145d PA |
2088 | if (!cache->base_p) |
2089 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2090 | else if (cache->base == 0) | |
2091 | { | |
2092 | /* This marks the outermost frame. */ | |
2093 | } | |
2094 | else | |
2095 | { | |
2096 | /* See the end of i386_push_dummy_call. */ | |
2097 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2098 | } | |
acd5c798 MK |
2099 | } |
2100 | ||
8fbca658 PA |
2101 | static enum unwind_stop_reason |
2102 | i386_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2103 | void **this_cache) | |
2104 | { | |
2105 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2106 | ||
2107 | if (!cache->base_p) | |
2108 | return UNWIND_UNAVAILABLE; | |
2109 | ||
2110 | /* This marks the outermost frame. */ | |
2111 | if (cache->base == 0) | |
2112 | return UNWIND_OUTERMOST; | |
2113 | ||
2114 | return UNWIND_NO_REASON; | |
2115 | } | |
2116 | ||
10458914 DJ |
2117 | static struct value * |
2118 | i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, | |
2119 | int regnum) | |
acd5c798 | 2120 | { |
10458914 | 2121 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2122 | |
2123 | gdb_assert (regnum >= 0); | |
2124 | ||
2125 | /* The System V ABI says that: | |
2126 | ||
2127 | "The flags register contains the system flags, such as the | |
2128 | direction flag and the carry flag. The direction flag must be | |
2129 | set to the forward (that is, zero) direction before entry and | |
2130 | upon exit from a function. Other user flags have no specified | |
2131 | role in the standard calling sequence and are not preserved." | |
2132 | ||
2133 | To guarantee the "upon exit" part of that statement we fake a | |
2134 | saved flags register that has its direction flag cleared. | |
2135 | ||
2136 | Note that GCC doesn't seem to rely on the fact that the direction | |
2137 | flag is cleared after a function return; it always explicitly | |
2138 | clears the flag before operations where it matters. | |
2139 | ||
2140 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2141 | right thing to do. The way we fake the flags register here makes | |
2142 | it impossible to change it. */ | |
2143 | ||
2144 | if (regnum == I386_EFLAGS_REGNUM) | |
2145 | { | |
10458914 | 2146 | ULONGEST val; |
c5aa993b | 2147 | |
10458914 DJ |
2148 | val = get_frame_register_unsigned (this_frame, regnum); |
2149 | val &= ~(1 << 10); | |
2150 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2151 | } |
1211c4e4 | 2152 | |
acd5c798 | 2153 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2154 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2155 | |
fcf250e2 UW |
2156 | if (regnum == I386_ESP_REGNUM |
2157 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2158 | { |
2159 | /* If the SP has been saved, but we don't know where, then this | |
2160 | means that SAVED_SP_REG register was found unavailable back | |
2161 | when we built the cache. */ | |
fcf250e2 | 2162 | if (cache->saved_sp == 0) |
8fbca658 PA |
2163 | return frame_unwind_got_register (this_frame, regnum, |
2164 | cache->saved_sp_reg); | |
2165 | else | |
2166 | return frame_unwind_got_constant (this_frame, regnum, | |
2167 | cache->saved_sp); | |
2168 | } | |
acd5c798 | 2169 | |
fd13a04a | 2170 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2171 | return frame_unwind_got_memory (this_frame, regnum, |
2172 | cache->saved_regs[regnum]); | |
fd13a04a | 2173 | |
10458914 | 2174 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2175 | } |
2176 | ||
2177 | static const struct frame_unwind i386_frame_unwind = | |
2178 | { | |
2179 | NORMAL_FRAME, | |
8fbca658 | 2180 | i386_frame_unwind_stop_reason, |
acd5c798 | 2181 | i386_frame_this_id, |
10458914 DJ |
2182 | i386_frame_prev_register, |
2183 | NULL, | |
2184 | default_frame_sniffer | |
acd5c798 | 2185 | }; |
06da04c6 MS |
2186 | |
2187 | /* Normal frames, but in a function epilogue. */ | |
2188 | ||
c9cf6e20 MG |
2189 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2190 | ||
2191 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2192 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2193 | the function's stack frame. */ | |
2194 | ||
2195 | static int | |
c9cf6e20 | 2196 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2197 | { |
2198 | gdb_byte insn; | |
43f3e411 | 2199 | struct compunit_symtab *cust; |
e0d00bc7 | 2200 | |
43f3e411 DE |
2201 | cust = find_pc_compunit_symtab (pc); |
2202 | if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) | |
e0d00bc7 | 2203 | return 0; |
06da04c6 MS |
2204 | |
2205 | if (target_read_memory (pc, &insn, 1)) | |
2206 | return 0; /* Can't read memory at pc. */ | |
2207 | ||
2208 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2209 | return 0; | |
2210 | ||
2211 | return 1; | |
2212 | } | |
2213 | ||
2214 | static int | |
2215 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
2216 | struct frame_info *this_frame, | |
2217 | void **this_prologue_cache) | |
2218 | { | |
2219 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2220 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2221 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2222 | else |
2223 | return 0; | |
2224 | } | |
2225 | ||
2226 | static struct i386_frame_cache * | |
2227 | i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
2228 | { | |
06da04c6 | 2229 | struct i386_frame_cache *cache; |
0d6c2135 | 2230 | CORE_ADDR sp; |
06da04c6 MS |
2231 | |
2232 | if (*this_cache) | |
9a3c8263 | 2233 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2234 | |
2235 | cache = i386_alloc_frame_cache (); | |
2236 | *this_cache = cache; | |
2237 | ||
492d29ea | 2238 | TRY |
8fbca658 | 2239 | { |
0d6c2135 | 2240 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2241 | |
0d6c2135 MK |
2242 | /* At this point the stack looks as if we just entered the |
2243 | function, with the return address at the top of the | |
2244 | stack. */ | |
2245 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2246 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2247 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2248 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2249 | |
8fbca658 PA |
2250 | cache->base_p = 1; |
2251 | } | |
492d29ea | 2252 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2253 | { |
2254 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2255 | throw_exception (ex); | |
2256 | } | |
492d29ea | 2257 | END_CATCH |
06da04c6 MS |
2258 | |
2259 | return cache; | |
2260 | } | |
2261 | ||
8fbca658 PA |
2262 | static enum unwind_stop_reason |
2263 | i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2264 | void **this_cache) | |
2265 | { | |
0d6c2135 MK |
2266 | struct i386_frame_cache *cache = |
2267 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2268 | |
2269 | if (!cache->base_p) | |
2270 | return UNWIND_UNAVAILABLE; | |
2271 | ||
2272 | return UNWIND_NO_REASON; | |
2273 | } | |
2274 | ||
06da04c6 MS |
2275 | static void |
2276 | i386_epilogue_frame_this_id (struct frame_info *this_frame, | |
2277 | void **this_cache, | |
2278 | struct frame_id *this_id) | |
2279 | { | |
0d6c2135 MK |
2280 | struct i386_frame_cache *cache = |
2281 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2282 | |
8fbca658 | 2283 | if (!cache->base_p) |
5ce0145d PA |
2284 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2285 | else | |
2286 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2287 | } |
2288 | ||
0d6c2135 MK |
2289 | static struct value * |
2290 | i386_epilogue_frame_prev_register (struct frame_info *this_frame, | |
2291 | void **this_cache, int regnum) | |
2292 | { | |
2293 | /* Make sure we've initialized the cache. */ | |
2294 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2295 | ||
2296 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2297 | } | |
2298 | ||
06da04c6 MS |
2299 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2300 | { | |
2301 | NORMAL_FRAME, | |
8fbca658 | 2302 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2303 | i386_epilogue_frame_this_id, |
0d6c2135 | 2304 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2305 | NULL, |
2306 | i386_epilogue_frame_sniffer | |
2307 | }; | |
acd5c798 MK |
2308 | \f |
2309 | ||
a3fcb948 JG |
2310 | /* Stack-based trampolines. */ |
2311 | ||
2312 | /* These trampolines are used on cross x86 targets, when taking the | |
2313 | address of a nested function. When executing these trampolines, | |
2314 | no stack frame is set up, so we are in a similar situation as in | |
2315 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2316 | ||
2317 | /* Static chain passed in register. */ | |
2318 | ||
2319 | struct i386_insn i386_tramp_chain_in_reg_insns[] = | |
2320 | { | |
2321 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2322 | { 5, { 0xb8 }, { 0xfe } }, | |
2323 | ||
2324 | /* `jmp imm32' */ | |
2325 | { 5, { 0xe9 }, { 0xff } }, | |
2326 | ||
2327 | {0} | |
2328 | }; | |
2329 | ||
2330 | /* Static chain passed on stack (when regparm=3). */ | |
2331 | ||
2332 | struct i386_insn i386_tramp_chain_on_stack_insns[] = | |
2333 | { | |
2334 | /* `push imm32' */ | |
2335 | { 5, { 0x68 }, { 0xff } }, | |
2336 | ||
2337 | /* `jmp imm32' */ | |
2338 | { 5, { 0xe9 }, { 0xff } }, | |
2339 | ||
2340 | {0} | |
2341 | }; | |
2342 | ||
2343 | /* Return whether PC points inside a stack trampoline. */ | |
2344 | ||
2345 | static int | |
6df81a63 | 2346 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2347 | { |
2348 | gdb_byte insn; | |
2c02bd72 | 2349 | const char *name; |
a3fcb948 JG |
2350 | |
2351 | /* A stack trampoline is detected if no name is associated | |
2352 | to the current pc and if it points inside a trampoline | |
2353 | sequence. */ | |
2354 | ||
2355 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2356 | if (name) | |
2357 | return 0; | |
2358 | ||
2359 | if (target_read_memory (pc, &insn, 1)) | |
2360 | return 0; | |
2361 | ||
2362 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2363 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2364 | return 0; | |
2365 | ||
2366 | return 1; | |
2367 | } | |
2368 | ||
2369 | static int | |
2370 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
0d6c2135 MK |
2371 | struct frame_info *this_frame, |
2372 | void **this_cache) | |
a3fcb948 JG |
2373 | { |
2374 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2375 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2376 | else |
2377 | return 0; | |
2378 | } | |
2379 | ||
2380 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2381 | { | |
2382 | NORMAL_FRAME, | |
2383 | i386_epilogue_frame_unwind_stop_reason, | |
2384 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2385 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2386 | NULL, |
2387 | i386_stack_tramp_frame_sniffer | |
2388 | }; | |
2389 | \f | |
6710bf39 SS |
2390 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2391 | ||
2392 | static void | |
2393 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2394 | struct agent_expr *ax, struct axs_value *value, | |
2395 | CORE_ADDR scope) | |
2396 | { | |
2397 | /* The following sequence assumes the traditional use of the base | |
2398 | register. */ | |
2399 | ax_reg (ax, I386_EBP_REGNUM); | |
2400 | ax_const_l (ax, 4); | |
2401 | ax_simple (ax, aop_add); | |
2402 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2403 | value->kind = axs_lvalue_memory; | |
2404 | } | |
2405 | \f | |
a3fcb948 | 2406 | |
acd5c798 MK |
2407 | /* Signal trampolines. */ |
2408 | ||
2409 | static struct i386_frame_cache * | |
10458914 | 2410 | i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2411 | { |
e17a4113 UW |
2412 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2413 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2414 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
acd5c798 | 2415 | struct i386_frame_cache *cache; |
acd5c798 | 2416 | CORE_ADDR addr; |
63c0089f | 2417 | gdb_byte buf[4]; |
acd5c798 MK |
2418 | |
2419 | if (*this_cache) | |
9a3c8263 | 2420 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2421 | |
fd13a04a | 2422 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2423 | |
492d29ea | 2424 | TRY |
a3386186 | 2425 | { |
8fbca658 PA |
2426 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2427 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2428 | |
8fbca658 PA |
2429 | addr = tdep->sigcontext_addr (this_frame); |
2430 | if (tdep->sc_reg_offset) | |
2431 | { | |
2432 | int i; | |
a3386186 | 2433 | |
8fbca658 PA |
2434 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2435 | ||
2436 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2437 | if (tdep->sc_reg_offset[i] != -1) | |
2438 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2439 | } | |
2440 | else | |
2441 | { | |
2442 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2443 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2444 | } | |
2445 | ||
2446 | cache->base_p = 1; | |
a3386186 | 2447 | } |
492d29ea | 2448 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
2449 | { |
2450 | if (ex.error != NOT_AVAILABLE_ERROR) | |
2451 | throw_exception (ex); | |
2452 | } | |
492d29ea | 2453 | END_CATCH |
acd5c798 MK |
2454 | |
2455 | *this_cache = cache; | |
2456 | return cache; | |
2457 | } | |
2458 | ||
8fbca658 PA |
2459 | static enum unwind_stop_reason |
2460 | i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, | |
2461 | void **this_cache) | |
2462 | { | |
2463 | struct i386_frame_cache *cache = | |
2464 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2465 | ||
2466 | if (!cache->base_p) | |
2467 | return UNWIND_UNAVAILABLE; | |
2468 | ||
2469 | return UNWIND_NO_REASON; | |
2470 | } | |
2471 | ||
acd5c798 | 2472 | static void |
10458914 | 2473 | i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, |
acd5c798 MK |
2474 | struct frame_id *this_id) |
2475 | { | |
2476 | struct i386_frame_cache *cache = | |
10458914 | 2477 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2478 | |
8fbca658 | 2479 | if (!cache->base_p) |
5ce0145d PA |
2480 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2481 | else | |
2482 | { | |
2483 | /* See the end of i386_push_dummy_call. */ | |
2484 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2485 | } | |
acd5c798 MK |
2486 | } |
2487 | ||
10458914 DJ |
2488 | static struct value * |
2489 | i386_sigtramp_frame_prev_register (struct frame_info *this_frame, | |
2490 | void **this_cache, int regnum) | |
acd5c798 MK |
2491 | { |
2492 | /* Make sure we've initialized the cache. */ | |
10458914 | 2493 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2494 | |
10458914 | 2495 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2496 | } |
c0d1d883 | 2497 | |
10458914 DJ |
2498 | static int |
2499 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
2500 | struct frame_info *this_frame, | |
2501 | void **this_prologue_cache) | |
acd5c798 | 2502 | { |
10458914 | 2503 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); |
acd5c798 | 2504 | |
911bc6ee MK |
2505 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2506 | handler. */ | |
2507 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2508 | return 0; |
1c3545ae | 2509 | |
911bc6ee MK |
2510 | if (tdep->sigtramp_p != NULL) |
2511 | { | |
10458914 DJ |
2512 | if (tdep->sigtramp_p (this_frame)) |
2513 | return 1; | |
911bc6ee MK |
2514 | } |
2515 | ||
2516 | if (tdep->sigtramp_start != 0) | |
2517 | { | |
10458914 | 2518 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2519 | |
2520 | gdb_assert (tdep->sigtramp_end != 0); | |
2521 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2522 | return 1; |
911bc6ee | 2523 | } |
acd5c798 | 2524 | |
10458914 | 2525 | return 0; |
acd5c798 | 2526 | } |
10458914 DJ |
2527 | |
2528 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2529 | { | |
2530 | SIGTRAMP_FRAME, | |
8fbca658 | 2531 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2532 | i386_sigtramp_frame_this_id, |
2533 | i386_sigtramp_frame_prev_register, | |
2534 | NULL, | |
2535 | i386_sigtramp_frame_sniffer | |
2536 | }; | |
acd5c798 MK |
2537 | \f |
2538 | ||
2539 | static CORE_ADDR | |
10458914 | 2540 | i386_frame_base_address (struct frame_info *this_frame, void **this_cache) |
acd5c798 | 2541 | { |
10458914 | 2542 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2543 | |
2544 | return cache->base; | |
2545 | } | |
2546 | ||
2547 | static const struct frame_base i386_frame_base = | |
2548 | { | |
2549 | &i386_frame_unwind, | |
2550 | i386_frame_base_address, | |
2551 | i386_frame_base_address, | |
2552 | i386_frame_base_address | |
2553 | }; | |
2554 | ||
acd5c798 | 2555 | static struct frame_id |
10458914 | 2556 | i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
acd5c798 | 2557 | { |
acd5c798 MK |
2558 | CORE_ADDR fp; |
2559 | ||
10458914 | 2560 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2561 | |
3e210248 | 2562 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2563 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2564 | } |
e04e5beb JM |
2565 | |
2566 | /* _Decimal128 function return values need 16-byte alignment on the | |
2567 | stack. */ | |
2568 | ||
2569 | static CORE_ADDR | |
2570 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2571 | { | |
2572 | return sp & -(CORE_ADDR)16; | |
2573 | } | |
fc338970 | 2574 | \f |
c906108c | 2575 | |
fc338970 MK |
2576 | /* Figure out where the longjmp will land. Slurp the args out of the |
2577 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2578 | structure from which we extract the address that we will land at. |
28bcfd30 | 2579 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2580 | success. */ |
c906108c | 2581 | |
8201327c | 2582 | static int |
60ade65d | 2583 | i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) |
c906108c | 2584 | { |
436675d3 | 2585 | gdb_byte buf[4]; |
c906108c | 2586 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2587 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2588 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
20a6ec49 | 2589 | int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; |
c906108c | 2590 | |
8201327c MK |
2591 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2592 | longjmp will land. */ | |
2593 | if (jb_pc_offset == -1) | |
c906108c SS |
2594 | return 0; |
2595 | ||
436675d3 | 2596 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2597 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2598 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2599 | return 0; |
2600 | ||
e17a4113 | 2601 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2602 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2603 | return 0; |
c906108c | 2604 | |
e17a4113 | 2605 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2606 | return 1; |
2607 | } | |
fc338970 | 2608 | \f |
c906108c | 2609 | |
7ccc1c74 JM |
2610 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2611 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2612 | unions containing such types must be 16-byte-aligned; other | |
2613 | arguments are 4-byte-aligned. */ | |
2614 | ||
2615 | static int | |
2616 | i386_16_byte_align_p (struct type *type) | |
2617 | { | |
2618 | type = check_typedef (type); | |
2619 | if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT | |
2620 | || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) | |
2621 | && TYPE_LENGTH (type) == 16) | |
2622 | return 1; | |
2623 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
2624 | return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); | |
2625 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2626 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2627 | { | |
2628 | int i; | |
2629 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
2630 | { | |
2631 | if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) | |
2632 | return 1; | |
2633 | } | |
2634 | } | |
2635 | return 0; | |
2636 | } | |
2637 | ||
a9b8d892 JK |
2638 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2639 | ||
2640 | static CORE_ADDR | |
2641 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2642 | struct value **args, int nargs, struct type *value_type, | |
2643 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2644 | struct regcache *regcache) | |
2645 | { | |
2646 | /* Use 0xcc breakpoint - 1 byte. */ | |
2647 | *bp_addr = sp - 1; | |
2648 | *real_pc = funaddr; | |
2649 | ||
2650 | /* Keep the stack aligned. */ | |
2651 | return sp - 16; | |
2652 | } | |
2653 | ||
3a1e71e3 | 2654 | static CORE_ADDR |
7d9b040b | 2655 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6a65450a AC |
2656 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
2657 | struct value **args, CORE_ADDR sp, int struct_return, | |
2658 | CORE_ADDR struct_addr) | |
22f8ba57 | 2659 | { |
e17a4113 | 2660 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2661 | gdb_byte buf[4]; |
acd5c798 | 2662 | int i; |
7ccc1c74 JM |
2663 | int write_pass; |
2664 | int args_space = 0; | |
acd5c798 | 2665 | |
7ccc1c74 JM |
2666 | /* Determine the total space required for arguments and struct |
2667 | return address in a first pass (allowing for 16-byte-aligned | |
2668 | arguments), then push arguments in a second pass. */ | |
2669 | ||
2670 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2671 | { |
7ccc1c74 | 2672 | int args_space_used = 0; |
7ccc1c74 JM |
2673 | |
2674 | if (struct_return) | |
2675 | { | |
2676 | if (write_pass) | |
2677 | { | |
2678 | /* Push value address. */ | |
e17a4113 | 2679 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2680 | write_memory (sp, buf, 4); |
2681 | args_space_used += 4; | |
2682 | } | |
2683 | else | |
2684 | args_space += 4; | |
2685 | } | |
2686 | ||
2687 | for (i = 0; i < nargs; i++) | |
2688 | { | |
2689 | int len = TYPE_LENGTH (value_enclosing_type (args[i])); | |
acd5c798 | 2690 | |
7ccc1c74 JM |
2691 | if (write_pass) |
2692 | { | |
2693 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
2694 | args_space_used = align_up (args_space_used, 16); | |
acd5c798 | 2695 | |
7ccc1c74 JM |
2696 | write_memory (sp + args_space_used, |
2697 | value_contents_all (args[i]), len); | |
2698 | /* The System V ABI says that: | |
acd5c798 | 2699 | |
7ccc1c74 JM |
2700 | "An argument's size is increased, if necessary, to make it a |
2701 | multiple of [32-bit] words. This may require tail padding, | |
2702 | depending on the size of the argument." | |
22f8ba57 | 2703 | |
7ccc1c74 JM |
2704 | This makes sure the stack stays word-aligned. */ |
2705 | args_space_used += align_up (len, 4); | |
2706 | } | |
2707 | else | |
2708 | { | |
2709 | if (i386_16_byte_align_p (value_enclosing_type (args[i]))) | |
284c5a60 | 2710 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2711 | args_space += align_up (len, 4); |
2712 | } | |
2713 | } | |
2714 | ||
2715 | if (!write_pass) | |
2716 | { | |
7ccc1c74 | 2717 | sp -= args_space; |
284c5a60 MK |
2718 | |
2719 | /* The original System V ABI only requires word alignment, | |
2720 | but modern incarnations need 16-byte alignment in order | |
2721 | to support SSE. Since wasting a few bytes here isn't | |
2722 | harmful we unconditionally enforce 16-byte alignment. */ | |
2723 | sp &= ~0xf; | |
7ccc1c74 | 2724 | } |
22f8ba57 MK |
2725 | } |
2726 | ||
acd5c798 MK |
2727 | /* Store return address. */ |
2728 | sp -= 4; | |
e17a4113 | 2729 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2730 | write_memory (sp, buf, 4); |
2731 | ||
2732 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2733 | store_unsigned_integer (buf, 4, byte_order, sp); |
acd5c798 MK |
2734 | regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); |
2735 | ||
2736 | /* ...and fake a frame pointer. */ | |
2737 | regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); | |
2738 | ||
3e210248 AC |
2739 | /* MarkK wrote: This "+ 8" is all over the place: |
2740 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2741 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2742 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2743 | definition of the stack address of a frame. Otherwise frame id |
2744 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2745 | stack address *before* the function call as a frame's CFA. On |
2746 | the i386, when %ebp is used as a frame pointer, the offset | |
2747 | between the contents %ebp and the CFA as defined by GCC. */ | |
2748 | return sp + 8; | |
22f8ba57 MK |
2749 | } |
2750 | ||
1a309862 MK |
2751 | /* These registers are used for returning integers (and on some |
2752 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2753 | size and alignment match an integer type). */ |
acd5c798 MK |
2754 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2755 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2756 | |
c5e656c1 MK |
2757 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2758 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2759 | |
3a1e71e3 | 2760 | static void |
c5e656c1 | 2761 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2762 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2763 | { |
c5e656c1 | 2764 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1a309862 | 2765 | int len = TYPE_LENGTH (type); |
63c0089f | 2766 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2767 | |
1e8d0a7b | 2768 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
c906108c | 2769 | { |
5716833c | 2770 | if (tdep->st0_regnum < 0) |
1a309862 | 2771 | { |
8a3fe4f8 | 2772 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2773 | memset (valbuf, 0, len); |
ef9dff19 | 2774 | return; |
1a309862 MK |
2775 | } |
2776 | ||
c6ba6f0d MK |
2777 | /* Floating-point return values can be found in %st(0). Convert |
2778 | its contents to the desired type. This is probably not | |
2779 | exactly how it would happen on the target itself, but it is | |
2780 | the best we can do. */ | |
acd5c798 | 2781 | regcache_raw_read (regcache, I386_ST0_REGNUM, buf); |
27067745 | 2782 | convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2783 | } |
2784 | else | |
c5aa993b | 2785 | { |
875f8d0e UW |
2786 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2787 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2788 | |
2789 | if (len <= low_size) | |
00f8375e | 2790 | { |
0818c12a | 2791 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2792 | memcpy (valbuf, buf, len); |
2793 | } | |
d4f3574e SS |
2794 | else if (len <= (low_size + high_size)) |
2795 | { | |
0818c12a | 2796 | regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); |
00f8375e | 2797 | memcpy (valbuf, buf, low_size); |
0818c12a | 2798 | regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); |
63c0089f | 2799 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2800 | } |
2801 | else | |
8e65ff28 | 2802 | internal_error (__FILE__, __LINE__, |
1777feb0 MS |
2803 | _("Cannot extract return value of %d bytes long."), |
2804 | len); | |
c906108c SS |
2805 | } |
2806 | } | |
2807 | ||
c5e656c1 MK |
2808 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2809 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2810 | |
3a1e71e3 | 2811 | static void |
c5e656c1 | 2812 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2813 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2814 | { |
c5e656c1 | 2815 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
ef9dff19 MK |
2816 | int len = TYPE_LENGTH (type); |
2817 | ||
1e8d0a7b | 2818 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
ef9dff19 | 2819 | { |
3d7f4f49 | 2820 | ULONGEST fstat; |
63c0089f | 2821 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2822 | |
5716833c | 2823 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2824 | { |
8a3fe4f8 | 2825 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2826 | return; |
2827 | } | |
2828 | ||
635b0cc1 MK |
2829 | /* Returning floating-point values is a bit tricky. Apart from |
2830 | storing the return value in %st(0), we have to simulate the | |
2831 | state of the FPU at function return point. */ | |
2832 | ||
c6ba6f0d MK |
2833 | /* Convert the value found in VALBUF to the extended |
2834 | floating-point format used by the FPU. This is probably | |
2835 | not exactly how it would happen on the target itself, but | |
2836 | it is the best we can do. */ | |
27067745 | 2837 | convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); |
acd5c798 | 2838 | regcache_raw_write (regcache, I386_ST0_REGNUM, buf); |
ccb945b8 | 2839 | |
635b0cc1 MK |
2840 | /* Set the top of the floating-point register stack to 7. The |
2841 | actual value doesn't really matter, but 7 is what a normal | |
2842 | function return would end up with if the program started out | |
2843 | with a freshly initialized FPU. */ | |
20a6ec49 | 2844 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2845 | fstat |= (7 << 11); |
20a6ec49 | 2846 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2847 | |
635b0cc1 MK |
2848 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
2849 | the floating-point register stack to 7, the appropriate value | |
2850 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2851 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2852 | } |
2853 | else | |
2854 | { | |
875f8d0e UW |
2855 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2856 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2857 | |
2858 | if (len <= low_size) | |
3d7f4f49 | 2859 | regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2860 | else if (len <= (low_size + high_size)) |
2861 | { | |
3d7f4f49 MK |
2862 | regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); |
2863 | regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, | |
63c0089f | 2864 | len - low_size, valbuf + low_size); |
ef9dff19 MK |
2865 | } |
2866 | else | |
8e65ff28 | 2867 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2868 | _("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2869 | } |
2870 | } | |
fc338970 | 2871 | \f |
ef9dff19 | 2872 | |
8201327c MK |
2873 | /* This is the variable that is set with "set struct-convention", and |
2874 | its legitimate values. */ | |
2875 | static const char default_struct_convention[] = "default"; | |
2876 | static const char pcc_struct_convention[] = "pcc"; | |
2877 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2878 | static const char *const valid_conventions[] = |
8201327c MK |
2879 | { |
2880 | default_struct_convention, | |
2881 | pcc_struct_convention, | |
2882 | reg_struct_convention, | |
2883 | NULL | |
2884 | }; | |
2885 | static const char *struct_convention = default_struct_convention; | |
2886 | ||
0e4377e1 JB |
2887 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2888 | a union type, or an array type, should be returned in registers | |
2889 | for architecture GDBARCH. */ | |
c5e656c1 | 2890 | |
8201327c | 2891 | static int |
c5e656c1 | 2892 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2893 | { |
c5e656c1 MK |
2894 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2895 | enum type_code code = TYPE_CODE (type); | |
2896 | int len = TYPE_LENGTH (type); | |
8201327c | 2897 | |
0e4377e1 JB |
2898 | gdb_assert (code == TYPE_CODE_STRUCT |
2899 | || code == TYPE_CODE_UNION | |
2900 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
2901 | |
2902 | if (struct_convention == pcc_struct_convention | |
2903 | || (struct_convention == default_struct_convention | |
2904 | && tdep->struct_return == pcc_struct_return)) | |
2905 | return 0; | |
2906 | ||
9edde48e MK |
2907 | /* Structures consisting of a single `float', `double' or 'long |
2908 | double' member are returned in %st(0). */ | |
2909 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) | |
2910 | { | |
2911 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
2912 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2913 | return (len == 4 || len == 8 || len == 12); | |
2914 | } | |
2915 | ||
c5e656c1 MK |
2916 | return (len == 1 || len == 2 || len == 4 || len == 8); |
2917 | } | |
2918 | ||
2919 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
2920 | should be returned. If it is supposed to be returned in registers, | |
2921 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
2922 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
2923 | from WRITEBUF into REGCACHE. */ | |
2924 | ||
2925 | static enum return_value_convention | |
6a3a010b | 2926 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2927 | struct type *type, struct regcache *regcache, |
2928 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
c5e656c1 MK |
2929 | { |
2930 | enum type_code code = TYPE_CODE (type); | |
2931 | ||
5daa78cc TJB |
2932 | if (((code == TYPE_CODE_STRUCT |
2933 | || code == TYPE_CODE_UNION | |
2934 | || code == TYPE_CODE_ARRAY) | |
2935 | && !i386_reg_struct_return_p (gdbarch, type)) | |
2445fd7b MK |
2936 | /* Complex double and long double uses the struct return covention. */ |
2937 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) | |
2938 | || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) | |
5daa78cc TJB |
2939 | /* 128-bit decimal float uses the struct return convention. */ |
2940 | || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) | |
31db7b6c MK |
2941 | { |
2942 | /* The System V ABI says that: | |
2943 | ||
2944 | "A function that returns a structure or union also sets %eax | |
2945 | to the value of the original address of the caller's area | |
2946 | before it returns. Thus when the caller receives control | |
2947 | again, the address of the returned object resides in register | |
2948 | %eax and can be used to access the object." | |
2949 | ||
2950 | So the ABI guarantees that we can always find the return | |
2951 | value just after the function has returned. */ | |
2952 | ||
0e4377e1 JB |
2953 | /* Note that the ABI doesn't mention functions returning arrays, |
2954 | which is something possible in certain languages such as Ada. | |
2955 | In this case, the value is returned as if it was wrapped in | |
2956 | a record, so the convention applied to records also applies | |
2957 | to arrays. */ | |
2958 | ||
31db7b6c MK |
2959 | if (readbuf) |
2960 | { | |
2961 | ULONGEST addr; | |
2962 | ||
2963 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
2964 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
2965 | } | |
2966 | ||
2967 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2968 | } | |
c5e656c1 MK |
2969 | |
2970 | /* This special case is for structures consisting of a single | |
9edde48e MK |
2971 | `float', `double' or 'long double' member. These structures are |
2972 | returned in %st(0). For these structures, we call ourselves | |
2973 | recursively, changing TYPE into the type of the first member of | |
2974 | the structure. Since that should work for all structures that | |
2975 | have only one member, we don't bother to check the member's type | |
2976 | here. */ | |
c5e656c1 MK |
2977 | if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) |
2978 | { | |
2979 | type = check_typedef (TYPE_FIELD_TYPE (type, 0)); | |
6a3a010b | 2980 | return i386_return_value (gdbarch, function, type, regcache, |
c055b101 | 2981 | readbuf, writebuf); |
c5e656c1 MK |
2982 | } |
2983 | ||
2984 | if (readbuf) | |
2985 | i386_extract_return_value (gdbarch, type, regcache, readbuf); | |
2986 | if (writebuf) | |
2987 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 2988 | |
c5e656c1 | 2989 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
2990 | } |
2991 | \f | |
2992 | ||
27067745 UW |
2993 | struct type * |
2994 | i387_ext_type (struct gdbarch *gdbarch) | |
2995 | { | |
2996 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2997 | ||
2998 | if (!tdep->i387_ext_type) | |
90884b2b L |
2999 | { |
3000 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3001 | gdb_assert (tdep->i387_ext_type != NULL); | |
3002 | } | |
27067745 UW |
3003 | |
3004 | return tdep->i387_ext_type; | |
3005 | } | |
3006 | ||
1dbcd68c WT |
3007 | /* Construct type for pseudo BND registers. We can't use |
3008 | tdesc_find_type since a complement of one value has to be used | |
3009 | to describe the upper bound. */ | |
3010 | ||
3011 | static struct type * | |
3012 | i386_bnd_type (struct gdbarch *gdbarch) | |
3013 | { | |
3014 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3015 | ||
3016 | ||
3017 | if (!tdep->i386_bnd_type) | |
3018 | { | |
870f88f7 | 3019 | struct type *t; |
1dbcd68c WT |
3020 | const struct builtin_type *bt = builtin_type (gdbarch); |
3021 | ||
3022 | /* The type we're building is described bellow: */ | |
3023 | #if 0 | |
3024 | struct __bound128 | |
3025 | { | |
3026 | void *lbound; | |
3027 | void *ubound; /* One complement of raw ubound field. */ | |
3028 | }; | |
3029 | #endif | |
3030 | ||
3031 | t = arch_composite_type (gdbarch, | |
3032 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3033 | ||
3034 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3035 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3036 | ||
3037 | TYPE_NAME (t) = "builtin_type_bound128"; | |
3038 | tdep->i386_bnd_type = t; | |
3039 | } | |
3040 | ||
3041 | return tdep->i386_bnd_type; | |
3042 | } | |
3043 | ||
01f9f808 MS |
3044 | /* Construct vector type for pseudo ZMM registers. We can't use |
3045 | tdesc_find_type since ZMM isn't described in target description. */ | |
3046 | ||
3047 | static struct type * | |
3048 | i386_zmm_type (struct gdbarch *gdbarch) | |
3049 | { | |
3050 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3051 | ||
3052 | if (!tdep->i386_zmm_type) | |
3053 | { | |
3054 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3055 | ||
3056 | /* The type we're building is this: */ | |
3057 | #if 0 | |
3058 | union __gdb_builtin_type_vec512i | |
3059 | { | |
3060 | int128_t uint128[4]; | |
3061 | int64_t v4_int64[8]; | |
3062 | int32_t v8_int32[16]; | |
3063 | int16_t v16_int16[32]; | |
3064 | int8_t v32_int8[64]; | |
3065 | double v4_double[8]; | |
3066 | float v8_float[16]; | |
3067 | }; | |
3068 | #endif | |
3069 | ||
3070 | struct type *t; | |
3071 | ||
3072 | t = arch_composite_type (gdbarch, | |
3073 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
3074 | append_composite_type_field (t, "v16_float", | |
3075 | init_vector_type (bt->builtin_float, 16)); | |
3076 | append_composite_type_field (t, "v8_double", | |
3077 | init_vector_type (bt->builtin_double, 8)); | |
3078 | append_composite_type_field (t, "v64_int8", | |
3079 | init_vector_type (bt->builtin_int8, 64)); | |
3080 | append_composite_type_field (t, "v32_int16", | |
3081 | init_vector_type (bt->builtin_int16, 32)); | |
3082 | append_composite_type_field (t, "v16_int32", | |
3083 | init_vector_type (bt->builtin_int32, 16)); | |
3084 | append_composite_type_field (t, "v8_int64", | |
3085 | init_vector_type (bt->builtin_int64, 8)); | |
3086 | append_composite_type_field (t, "v4_int128", | |
3087 | init_vector_type (bt->builtin_int128, 4)); | |
3088 | ||
3089 | TYPE_VECTOR (t) = 1; | |
3090 | TYPE_NAME (t) = "builtin_type_vec512i"; | |
3091 | tdep->i386_zmm_type = t; | |
3092 | } | |
3093 | ||
3094 | return tdep->i386_zmm_type; | |
3095 | } | |
3096 | ||
c131fcee L |
3097 | /* Construct vector type for pseudo YMM registers. We can't use |
3098 | tdesc_find_type since YMM isn't described in target description. */ | |
3099 | ||
3100 | static struct type * | |
3101 | i386_ymm_type (struct gdbarch *gdbarch) | |
3102 | { | |
3103 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3104 | ||
3105 | if (!tdep->i386_ymm_type) | |
3106 | { | |
3107 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3108 | ||
3109 | /* The type we're building is this: */ | |
3110 | #if 0 | |
3111 | union __gdb_builtin_type_vec256i | |
3112 | { | |
3113 | int128_t uint128[2]; | |
3114 | int64_t v2_int64[4]; | |
3115 | int32_t v4_int32[8]; | |
3116 | int16_t v8_int16[16]; | |
3117 | int8_t v16_int8[32]; | |
3118 | double v2_double[4]; | |
3119 | float v4_float[8]; | |
3120 | }; | |
3121 | #endif | |
3122 | ||
3123 | struct type *t; | |
3124 | ||
3125 | t = arch_composite_type (gdbarch, | |
3126 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
3127 | append_composite_type_field (t, "v8_float", | |
3128 | init_vector_type (bt->builtin_float, 8)); | |
3129 | append_composite_type_field (t, "v4_double", | |
3130 | init_vector_type (bt->builtin_double, 4)); | |
3131 | append_composite_type_field (t, "v32_int8", | |
3132 | init_vector_type (bt->builtin_int8, 32)); | |
3133 | append_composite_type_field (t, "v16_int16", | |
3134 | init_vector_type (bt->builtin_int16, 16)); | |
3135 | append_composite_type_field (t, "v8_int32", | |
3136 | init_vector_type (bt->builtin_int32, 8)); | |
3137 | append_composite_type_field (t, "v4_int64", | |
3138 | init_vector_type (bt->builtin_int64, 4)); | |
3139 | append_composite_type_field (t, "v2_int128", | |
3140 | init_vector_type (bt->builtin_int128, 2)); | |
3141 | ||
3142 | TYPE_VECTOR (t) = 1; | |
0c5acf93 | 3143 | TYPE_NAME (t) = "builtin_type_vec256i"; |
c131fcee L |
3144 | tdep->i386_ymm_type = t; |
3145 | } | |
3146 | ||
3147 | return tdep->i386_ymm_type; | |
3148 | } | |
3149 | ||
794ac428 | 3150 | /* Construct vector type for MMX registers. */ |
90884b2b | 3151 | static struct type * |
794ac428 UW |
3152 | i386_mmx_type (struct gdbarch *gdbarch) |
3153 | { | |
3154 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3155 | ||
3156 | if (!tdep->i386_mmx_type) | |
3157 | { | |
df4df182 UW |
3158 | const struct builtin_type *bt = builtin_type (gdbarch); |
3159 | ||
794ac428 UW |
3160 | /* The type we're building is this: */ |
3161 | #if 0 | |
3162 | union __gdb_builtin_type_vec64i | |
3163 | { | |
3164 | int64_t uint64; | |
3165 | int32_t v2_int32[2]; | |
3166 | int16_t v4_int16[4]; | |
3167 | int8_t v8_int8[8]; | |
3168 | }; | |
3169 | #endif | |
3170 | ||
3171 | struct type *t; | |
3172 | ||
e9bb382b UW |
3173 | t = arch_composite_type (gdbarch, |
3174 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3175 | |
3176 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3177 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3178 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3179 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3180 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3181 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3182 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3183 | |
876cecd0 | 3184 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
3185 | TYPE_NAME (t) = "builtin_type_vec64i"; |
3186 | tdep->i386_mmx_type = t; | |
3187 | } | |
3188 | ||
3189 | return tdep->i386_mmx_type; | |
3190 | } | |
3191 | ||
d7a0d72c | 3192 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3193 | register REGNUM. */ |
d7a0d72c | 3194 | |
fff4548b | 3195 | struct type * |
90884b2b | 3196 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3197 | { |
1dbcd68c WT |
3198 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3199 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3200 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3201 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3202 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3203 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3204 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3205 | return i386_ymm_type (gdbarch); | |
3206 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3207 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3208 | else |
3209 | { | |
3210 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3211 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3212 | return bt->builtin_int8; | |
3213 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3214 | return bt->builtin_int16; | |
3215 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3216 | return bt->builtin_int32; | |
01f9f808 MS |
3217 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3218 | return bt->builtin_int64; | |
1ba53b71 L |
3219 | } |
3220 | ||
3221 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
d7a0d72c MK |
3222 | } |
3223 | ||
28fc6740 | 3224 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3225 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3226 | |
3227 | static int | |
c86c27af | 3228 | i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) |
28fc6740 | 3229 | { |
5716833c MK |
3230 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
3231 | int mmxreg, fpreg; | |
28fc6740 AC |
3232 | ULONGEST fstat; |
3233 | int tos; | |
c86c27af | 3234 | |
5716833c | 3235 | mmxreg = regnum - tdep->mm0_regnum; |
20a6ec49 | 3236 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3237 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3238 | fpreg = (mmxreg + tos) % 8; |
3239 | ||
20a6ec49 | 3240 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3241 | } |
3242 | ||
3543a589 TT |
3243 | /* A helper function for us by i386_pseudo_register_read_value and |
3244 | amd64_pseudo_register_read_value. It does all the work but reads | |
3245 | the data into an already-allocated value. */ | |
3246 | ||
3247 | void | |
3248 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
3249 | struct regcache *regcache, | |
3250 | int regnum, | |
3251 | struct value *result_value) | |
28fc6740 | 3252 | { |
1ba53b71 | 3253 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
05d1431c | 3254 | enum register_status status; |
3543a589 | 3255 | gdb_byte *buf = value_contents_raw (result_value); |
1ba53b71 | 3256 | |
5716833c | 3257 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3258 | { |
c86c27af MK |
3259 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3260 | ||
28fc6740 | 3261 | /* Extract (always little endian). */ |
05d1431c PA |
3262 | status = regcache_raw_read (regcache, fpnum, raw_buf); |
3263 | if (status != REG_VALID) | |
3543a589 TT |
3264 | mark_value_bytes_unavailable (result_value, 0, |
3265 | TYPE_LENGTH (value_type (result_value))); | |
3266 | else | |
3267 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3268 | } |
3269 | else | |
1ba53b71 L |
3270 | { |
3271 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1dbcd68c WT |
3272 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3273 | { | |
3274 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3275 | |
1dbcd68c WT |
3276 | /* Extract (always little endian). Read lower 128bits. */ |
3277 | status = regcache_raw_read (regcache, | |
3278 | I387_BND0R_REGNUM (tdep) + regnum, | |
3279 | raw_buf); | |
3280 | if (status != REG_VALID) | |
3281 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3282 | else | |
3283 | { | |
3284 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3285 | LONGEST upper, lower; | |
3286 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3287 | ||
3288 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3289 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3290 | upper = ~upper; | |
3291 | ||
3292 | memcpy (buf, &lower, size); | |
3293 | memcpy (buf + size, &upper, size); | |
3294 | } | |
3295 | } | |
01f9f808 MS |
3296 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3297 | { | |
3298 | regnum -= tdep->k0_regnum; | |
3299 | ||
3300 | /* Extract (always little endian). */ | |
3301 | status = regcache_raw_read (regcache, | |
3302 | tdep->k0_regnum + regnum, | |
3303 | raw_buf); | |
3304 | if (status != REG_VALID) | |
3305 | mark_value_bytes_unavailable (result_value, 0, 8); | |
3306 | else | |
3307 | memcpy (buf, raw_buf, 8); | |
3308 | } | |
3309 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3310 | { | |
3311 | regnum -= tdep->zmm0_regnum; | |
3312 | ||
3313 | if (regnum < num_lower_zmm_regs) | |
3314 | { | |
3315 | /* Extract (always little endian). Read lower 128bits. */ | |
3316 | status = regcache_raw_read (regcache, | |
3317 | I387_XMM0_REGNUM (tdep) + regnum, | |
3318 | raw_buf); | |
3319 | if (status != REG_VALID) | |
3320 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3321 | else | |
3322 | memcpy (buf, raw_buf, 16); | |
3323 | ||
3324 | /* Extract (always little endian). Read upper 128bits. */ | |
3325 | status = regcache_raw_read (regcache, | |
3326 | tdep->ymm0h_regnum + regnum, | |
3327 | raw_buf); | |
3328 | if (status != REG_VALID) | |
3329 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3330 | else | |
3331 | memcpy (buf + 16, raw_buf, 16); | |
3332 | } | |
3333 | else | |
3334 | { | |
3335 | /* Extract (always little endian). Read lower 128bits. */ | |
3336 | status = regcache_raw_read (regcache, | |
3337 | I387_XMM16_REGNUM (tdep) + regnum | |
3338 | - num_lower_zmm_regs, | |
3339 | raw_buf); | |
3340 | if (status != REG_VALID) | |
3341 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3342 | else | |
3343 | memcpy (buf, raw_buf, 16); | |
3344 | ||
3345 | /* Extract (always little endian). Read upper 128bits. */ | |
3346 | status = regcache_raw_read (regcache, | |
3347 | I387_YMM16H_REGNUM (tdep) + regnum | |
3348 | - num_lower_zmm_regs, | |
3349 | raw_buf); | |
3350 | if (status != REG_VALID) | |
3351 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3352 | else | |
3353 | memcpy (buf + 16, raw_buf, 16); | |
3354 | } | |
3355 | ||
3356 | /* Read upper 256bits. */ | |
3357 | status = regcache_raw_read (regcache, | |
3358 | tdep->zmm0h_regnum + regnum, | |
3359 | raw_buf); | |
3360 | if (status != REG_VALID) | |
3361 | mark_value_bytes_unavailable (result_value, 32, 32); | |
3362 | else | |
3363 | memcpy (buf + 32, raw_buf, 32); | |
3364 | } | |
1dbcd68c | 3365 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3366 | { |
3367 | regnum -= tdep->ymm0_regnum; | |
3368 | ||
1777feb0 | 3369 | /* Extract (always little endian). Read lower 128bits. */ |
05d1431c PA |
3370 | status = regcache_raw_read (regcache, |
3371 | I387_XMM0_REGNUM (tdep) + regnum, | |
3372 | raw_buf); | |
3373 | if (status != REG_VALID) | |
3543a589 TT |
3374 | mark_value_bytes_unavailable (result_value, 0, 16); |
3375 | else | |
3376 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3377 | /* Read upper 128bits. */ |
05d1431c PA |
3378 | status = regcache_raw_read (regcache, |
3379 | tdep->ymm0h_regnum + regnum, | |
3380 | raw_buf); | |
3381 | if (status != REG_VALID) | |
3543a589 TT |
3382 | mark_value_bytes_unavailable (result_value, 16, 32); |
3383 | else | |
3384 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3385 | } |
01f9f808 MS |
3386 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3387 | { | |
3388 | regnum -= tdep->ymm16_regnum; | |
3389 | /* Extract (always little endian). Read lower 128bits. */ | |
3390 | status = regcache_raw_read (regcache, | |
3391 | I387_XMM16_REGNUM (tdep) + regnum, | |
3392 | raw_buf); | |
3393 | if (status != REG_VALID) | |
3394 | mark_value_bytes_unavailable (result_value, 0, 16); | |
3395 | else | |
3396 | memcpy (buf, raw_buf, 16); | |
3397 | /* Read upper 128bits. */ | |
3398 | status = regcache_raw_read (regcache, | |
3399 | tdep->ymm16h_regnum + regnum, | |
3400 | raw_buf); | |
3401 | if (status != REG_VALID) | |
3402 | mark_value_bytes_unavailable (result_value, 16, 16); | |
3403 | else | |
3404 | memcpy (buf + 16, raw_buf, 16); | |
3405 | } | |
c131fcee | 3406 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3407 | { |
3408 | int gpnum = regnum - tdep->ax_regnum; | |
3409 | ||
3410 | /* Extract (always little endian). */ | |
05d1431c PA |
3411 | status = regcache_raw_read (regcache, gpnum, raw_buf); |
3412 | if (status != REG_VALID) | |
3543a589 TT |
3413 | mark_value_bytes_unavailable (result_value, 0, |
3414 | TYPE_LENGTH (value_type (result_value))); | |
3415 | else | |
3416 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3417 | } |
3418 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3419 | { | |
1ba53b71 L |
3420 | int gpnum = regnum - tdep->al_regnum; |
3421 | ||
3422 | /* Extract (always little endian). We read both lower and | |
3423 | upper registers. */ | |
05d1431c PA |
3424 | status = regcache_raw_read (regcache, gpnum % 4, raw_buf); |
3425 | if (status != REG_VALID) | |
3543a589 TT |
3426 | mark_value_bytes_unavailable (result_value, 0, |
3427 | TYPE_LENGTH (value_type (result_value))); | |
3428 | else if (gpnum >= 4) | |
1ba53b71 L |
3429 | memcpy (buf, raw_buf + 1, 1); |
3430 | else | |
3431 | memcpy (buf, raw_buf, 1); | |
3432 | } | |
3433 | else | |
3434 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3435 | } | |
3543a589 TT |
3436 | } |
3437 | ||
3438 | static struct value * | |
3439 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
3440 | struct regcache *regcache, | |
3441 | int regnum) | |
3442 | { | |
3443 | struct value *result; | |
3444 | ||
3445 | result = allocate_value (register_type (gdbarch, regnum)); | |
3446 | VALUE_LVAL (result) = lval_register; | |
3447 | VALUE_REGNUM (result) = regnum; | |
3448 | ||
3449 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3450 | |
3543a589 | 3451 | return result; |
28fc6740 AC |
3452 | } |
3453 | ||
1ba53b71 | 3454 | void |
28fc6740 | 3455 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3456 | int regnum, const gdb_byte *buf) |
28fc6740 | 3457 | { |
1ba53b71 L |
3458 | gdb_byte raw_buf[MAX_REGISTER_SIZE]; |
3459 | ||
5716833c | 3460 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3461 | { |
c86c27af MK |
3462 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3463 | ||
28fc6740 | 3464 | /* Read ... */ |
1ba53b71 | 3465 | regcache_raw_read (regcache, fpnum, raw_buf); |
28fc6740 | 3466 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3467 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3468 | /* ... Write. */ |
1ba53b71 | 3469 | regcache_raw_write (regcache, fpnum, raw_buf); |
28fc6740 AC |
3470 | } |
3471 | else | |
1ba53b71 L |
3472 | { |
3473 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3474 | ||
1dbcd68c WT |
3475 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3476 | { | |
3477 | ULONGEST upper, lower; | |
3478 | int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); | |
3479 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3480 | ||
3481 | /* New values from input value. */ | |
3482 | regnum -= tdep->bnd0_regnum; | |
3483 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3484 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3485 | ||
3486 | /* Fetching register buffer. */ | |
3487 | regcache_raw_read (regcache, | |
3488 | I387_BND0R_REGNUM (tdep) + regnum, | |
3489 | raw_buf); | |
3490 | ||
3491 | upper = ~upper; | |
3492 | ||
3493 | /* Set register bits. */ | |
3494 | memcpy (raw_buf, &lower, 8); | |
3495 | memcpy (raw_buf + 8, &upper, 8); | |
3496 | ||
3497 | ||
3498 | regcache_raw_write (regcache, | |
3499 | I387_BND0R_REGNUM (tdep) + regnum, | |
3500 | raw_buf); | |
3501 | } | |
01f9f808 MS |
3502 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3503 | { | |
3504 | regnum -= tdep->k0_regnum; | |
3505 | ||
3506 | regcache_raw_write (regcache, | |
3507 | tdep->k0_regnum + regnum, | |
3508 | buf); | |
3509 | } | |
3510 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3511 | { | |
3512 | regnum -= tdep->zmm0_regnum; | |
3513 | ||
3514 | if (regnum < num_lower_zmm_regs) | |
3515 | { | |
3516 | /* Write lower 128bits. */ | |
3517 | regcache_raw_write (regcache, | |
3518 | I387_XMM0_REGNUM (tdep) + regnum, | |
3519 | buf); | |
3520 | /* Write upper 128bits. */ | |
3521 | regcache_raw_write (regcache, | |
3522 | I387_YMM0_REGNUM (tdep) + regnum, | |
3523 | buf + 16); | |
3524 | } | |
3525 | else | |
3526 | { | |
3527 | /* Write lower 128bits. */ | |
3528 | regcache_raw_write (regcache, | |
3529 | I387_XMM16_REGNUM (tdep) + regnum | |
3530 | - num_lower_zmm_regs, | |
3531 | buf); | |
3532 | /* Write upper 128bits. */ | |
3533 | regcache_raw_write (regcache, | |
3534 | I387_YMM16H_REGNUM (tdep) + regnum | |
3535 | - num_lower_zmm_regs, | |
3536 | buf + 16); | |
3537 | } | |
3538 | /* Write upper 256bits. */ | |
3539 | regcache_raw_write (regcache, | |
3540 | tdep->zmm0h_regnum + regnum, | |
3541 | buf + 32); | |
3542 | } | |
1dbcd68c | 3543 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3544 | { |
3545 | regnum -= tdep->ymm0_regnum; | |
3546 | ||
3547 | /* ... Write lower 128bits. */ | |
3548 | regcache_raw_write (regcache, | |
3549 | I387_XMM0_REGNUM (tdep) + regnum, | |
3550 | buf); | |
3551 | /* ... Write upper 128bits. */ | |
3552 | regcache_raw_write (regcache, | |
3553 | tdep->ymm0h_regnum + regnum, | |
3554 | buf + 16); | |
3555 | } | |
01f9f808 MS |
3556 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3557 | { | |
3558 | regnum -= tdep->ymm16_regnum; | |
3559 | ||
3560 | /* ... Write lower 128bits. */ | |
3561 | regcache_raw_write (regcache, | |
3562 | I387_XMM16_REGNUM (tdep) + regnum, | |
3563 | buf); | |
3564 | /* ... Write upper 128bits. */ | |
3565 | regcache_raw_write (regcache, | |
3566 | tdep->ymm16h_regnum + regnum, | |
3567 | buf + 16); | |
3568 | } | |
c131fcee | 3569 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3570 | { |
3571 | int gpnum = regnum - tdep->ax_regnum; | |
3572 | ||
3573 | /* Read ... */ | |
3574 | regcache_raw_read (regcache, gpnum, raw_buf); | |
3575 | /* ... Modify ... (always little endian). */ | |
3576 | memcpy (raw_buf, buf, 2); | |
3577 | /* ... Write. */ | |
3578 | regcache_raw_write (regcache, gpnum, raw_buf); | |
3579 | } | |
3580 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3581 | { | |
1ba53b71 L |
3582 | int gpnum = regnum - tdep->al_regnum; |
3583 | ||
3584 | /* Read ... We read both lower and upper registers. */ | |
3585 | regcache_raw_read (regcache, gpnum % 4, raw_buf); | |
3586 | /* ... Modify ... (always little endian). */ | |
3587 | if (gpnum >= 4) | |
3588 | memcpy (raw_buf + 1, buf, 1); | |
3589 | else | |
3590 | memcpy (raw_buf, buf, 1); | |
3591 | /* ... Write. */ | |
3592 | regcache_raw_write (regcache, gpnum % 4, raw_buf); | |
3593 | } | |
3594 | else | |
3595 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3596 | } | |
28fc6740 | 3597 | } |
62e5fd57 MK |
3598 | |
3599 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3600 | ||
3601 | int | |
3602 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3603 | struct agent_expr *ax, int regnum) | |
3604 | { | |
3605 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3606 | ||
3607 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3608 | { | |
3609 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3610 | not care and collect everything... */ | |
3611 | int i; | |
3612 | ||
3613 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3614 | for (i = 0; i < 8; i++) | |
3615 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3616 | return 0; | |
3617 | } | |
3618 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3619 | { | |
3620 | regnum -= tdep->bnd0_regnum; | |
3621 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3622 | return 0; | |
3623 | } | |
3624 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3625 | { | |
3626 | regnum -= tdep->k0_regnum; | |
3627 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3628 | return 0; | |
3629 | } | |
3630 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3631 | { | |
3632 | regnum -= tdep->zmm0_regnum; | |
3633 | if (regnum < num_lower_zmm_regs) | |
3634 | { | |
3635 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3636 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3637 | } | |
3638 | else | |
3639 | { | |
3640 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3641 | - num_lower_zmm_regs); | |
3642 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3643 | - num_lower_zmm_regs); | |
3644 | } | |
3645 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3646 | return 0; | |
3647 | } | |
3648 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3649 | { | |
3650 | regnum -= tdep->ymm0_regnum; | |
3651 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3652 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3653 | return 0; | |
3654 | } | |
3655 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3656 | { | |
3657 | regnum -= tdep->ymm16_regnum; | |
3658 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3659 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3660 | return 0; | |
3661 | } | |
3662 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3663 | { | |
3664 | int gpnum = regnum - tdep->ax_regnum; | |
3665 | ||
3666 | ax_reg_mask (ax, gpnum); | |
3667 | return 0; | |
3668 | } | |
3669 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3670 | { | |
3671 | int gpnum = regnum - tdep->al_regnum; | |
3672 | ||
3673 | ax_reg_mask (ax, gpnum % 4); | |
3674 | return 0; | |
3675 | } | |
3676 | else | |
3677 | internal_error (__FILE__, __LINE__, _("invalid regnum")); | |
3678 | return 1; | |
3679 | } | |
ff2e87ac AC |
3680 | \f |
3681 | ||
ff2e87ac AC |
3682 | /* Return the register number of the register allocated by GCC after |
3683 | REGNUM, or -1 if there is no such register. */ | |
3684 | ||
3685 | static int | |
3686 | i386_next_regnum (int regnum) | |
3687 | { | |
3688 | /* GCC allocates the registers in the order: | |
3689 | ||
3690 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3691 | ||
3692 | Since storing a variable in %esp doesn't make any sense we return | |
3693 | -1 for %ebp and for %esp itself. */ | |
3694 | static int next_regnum[] = | |
3695 | { | |
3696 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3697 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3698 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3699 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3700 | -1, -1, /* Slots for %esp and %ebp. */ | |
3701 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3702 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3703 | }; | |
3704 | ||
de5b9bb9 | 3705 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3706 | return next_regnum[regnum]; |
28fc6740 | 3707 | |
ff2e87ac AC |
3708 | return -1; |
3709 | } | |
3710 | ||
3711 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3712 | needs any special handling. */ | |
d7a0d72c | 3713 | |
3a1e71e3 | 3714 | static int |
1777feb0 MS |
3715 | i386_convert_register_p (struct gdbarch *gdbarch, |
3716 | int regnum, struct type *type) | |
d7a0d72c | 3717 | { |
de5b9bb9 MK |
3718 | int len = TYPE_LENGTH (type); |
3719 | ||
ff2e87ac AC |
3720 | /* Values may be spread across multiple registers. Most debugging |
3721 | formats aren't expressive enough to specify the locations, so | |
3722 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3723 | have a length that is a multiple of the word size, since GCC |
3724 | doesn't seem to put any other types into registers. */ | |
3725 | if (len > 4 && len % 4 == 0) | |
3726 | { | |
3727 | int last_regnum = regnum; | |
3728 | ||
3729 | while (len > 4) | |
3730 | { | |
3731 | last_regnum = i386_next_regnum (last_regnum); | |
3732 | len -= 4; | |
3733 | } | |
3734 | ||
3735 | if (last_regnum != -1) | |
3736 | return 1; | |
3737 | } | |
ff2e87ac | 3738 | |
0abe36f5 | 3739 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3740 | } |
3741 | ||
ff2e87ac AC |
3742 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3743 | return its contents in TO. */ | |
ac27f131 | 3744 | |
8dccd430 | 3745 | static int |
ff2e87ac | 3746 | i386_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
3747 | struct type *type, gdb_byte *to, |
3748 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3749 | { |
20a6ec49 | 3750 | struct gdbarch *gdbarch = get_frame_arch (frame); |
de5b9bb9 | 3751 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3752 | |
20a6ec49 | 3753 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3754 | return i387_register_to_value (frame, regnum, type, to, |
3755 | optimizedp, unavailablep); | |
ff2e87ac | 3756 | |
fd35795f | 3757 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3758 | |
3759 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3760 | |
de5b9bb9 MK |
3761 | while (len > 0) |
3762 | { | |
3763 | gdb_assert (regnum != -1); | |
20a6ec49 | 3764 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3765 | |
8dccd430 PA |
3766 | if (!get_frame_register_bytes (frame, regnum, 0, |
3767 | register_size (gdbarch, regnum), | |
3768 | to, optimizedp, unavailablep)) | |
3769 | return 0; | |
3770 | ||
de5b9bb9 MK |
3771 | regnum = i386_next_regnum (regnum); |
3772 | len -= 4; | |
42835c2b | 3773 | to += 4; |
de5b9bb9 | 3774 | } |
8dccd430 PA |
3775 | |
3776 | *optimizedp = *unavailablep = 0; | |
3777 | return 1; | |
ac27f131 MK |
3778 | } |
3779 | ||
ff2e87ac AC |
3780 | /* Write the contents FROM of a value of type TYPE into register |
3781 | REGNUM in frame FRAME. */ | |
ac27f131 | 3782 | |
3a1e71e3 | 3783 | static void |
ff2e87ac | 3784 | i386_value_to_register (struct frame_info *frame, int regnum, |
42835c2b | 3785 | struct type *type, const gdb_byte *from) |
ac27f131 | 3786 | { |
de5b9bb9 | 3787 | int len = TYPE_LENGTH (type); |
de5b9bb9 | 3788 | |
20a6ec49 | 3789 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3790 | { |
d532c08f MK |
3791 | i387_value_to_register (frame, regnum, type, from); |
3792 | return; | |
3793 | } | |
3d261580 | 3794 | |
fd35795f | 3795 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3796 | |
3797 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3798 | |
de5b9bb9 MK |
3799 | while (len > 0) |
3800 | { | |
3801 | gdb_assert (regnum != -1); | |
875f8d0e | 3802 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3803 | |
42835c2b | 3804 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3805 | regnum = i386_next_regnum (regnum); |
3806 | len -= 4; | |
42835c2b | 3807 | from += 4; |
de5b9bb9 | 3808 | } |
ac27f131 | 3809 | } |
ff2e87ac | 3810 | \f |
7fdafb5a MK |
3811 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3812 | in the general-purpose register set REGSET to register cache | |
3813 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3814 | |
20187ed5 | 3815 | void |
473f17b0 MK |
3816 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3817 | int regnum, const void *gregs, size_t len) | |
3818 | { | |
09424cff AA |
3819 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3820 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3821 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3822 | int i; |
3823 | ||
1528345d | 3824 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3825 | |
3826 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3827 | { | |
3828 | if ((regnum == i || regnum == -1) | |
3829 | && tdep->gregset_reg_offset[i] != -1) | |
3830 | regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3831 | } | |
3832 | } | |
3833 | ||
7fdafb5a MK |
3834 | /* Collect register REGNUM from the register cache REGCACHE and store |
3835 | it in the buffer specified by GREGS and LEN as described by the | |
3836 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3837 | all registers in REGSET. */ | |
3838 | ||
ecc37a5a | 3839 | static void |
7fdafb5a MK |
3840 | i386_collect_gregset (const struct regset *regset, |
3841 | const struct regcache *regcache, | |
3842 | int regnum, void *gregs, size_t len) | |
3843 | { | |
09424cff AA |
3844 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3845 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
9a3c8263 | 3846 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3847 | int i; |
3848 | ||
1528345d | 3849 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3850 | |
3851 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3852 | { | |
3853 | if ((regnum == i || regnum == -1) | |
3854 | && tdep->gregset_reg_offset[i] != -1) | |
3855 | regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); | |
3856 | } | |
3857 | } | |
3858 | ||
3859 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3860 | in the floating-point register set REGSET to register cache | |
3861 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3862 | |
3863 | static void | |
3864 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3865 | int regnum, const void *fpregs, size_t len) | |
3866 | { | |
09424cff AA |
3867 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3868 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
473f17b0 | 3869 | |
66a72d25 MK |
3870 | if (len == I387_SIZEOF_FXSAVE) |
3871 | { | |
3872 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3873 | return; | |
3874 | } | |
3875 | ||
1528345d | 3876 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3877 | i387_supply_fsave (regcache, regnum, fpregs); |
3878 | } | |
8446b36a | 3879 | |
2f305df1 MK |
3880 | /* Collect register REGNUM from the register cache REGCACHE and store |
3881 | it in the buffer specified by FPREGS and LEN as described by the | |
3882 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3883 | all registers in REGSET. */ | |
7fdafb5a MK |
3884 | |
3885 | static void | |
3886 | i386_collect_fpregset (const struct regset *regset, | |
3887 | const struct regcache *regcache, | |
3888 | int regnum, void *fpregs, size_t len) | |
3889 | { | |
09424cff AA |
3890 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
3891 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7fdafb5a MK |
3892 | |
3893 | if (len == I387_SIZEOF_FXSAVE) | |
3894 | { | |
3895 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3896 | return; | |
3897 | } | |
3898 | ||
1528345d | 3899 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3900 | i387_collect_fsave (regcache, regnum, fpregs); |
3901 | } | |
3902 | ||
ecc37a5a AA |
3903 | /* Register set definitions. */ |
3904 | ||
3905 | const struct regset i386_gregset = | |
3906 | { | |
3907 | NULL, i386_supply_gregset, i386_collect_gregset | |
3908 | }; | |
3909 | ||
8f0435f7 | 3910 | const struct regset i386_fpregset = |
ecc37a5a AA |
3911 | { |
3912 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
3913 | }; | |
3914 | ||
490496c3 | 3915 | /* Default iterator over core file register note sections. */ |
8446b36a | 3916 | |
490496c3 AA |
3917 | void |
3918 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
3919 | iterate_over_regset_sections_cb *cb, | |
3920 | void *cb_data, | |
3921 | const struct regcache *regcache) | |
8446b36a MK |
3922 | { |
3923 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3924 | ||
490496c3 AA |
3925 | cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data); |
3926 | if (tdep->sizeof_fpregset) | |
3927 | cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); | |
8446b36a | 3928 | } |
473f17b0 | 3929 | \f |
fc338970 | 3930 | |
fc338970 | 3931 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
3932 | |
3933 | CORE_ADDR | |
e17a4113 UW |
3934 | i386_pe_skip_trampoline_code (struct frame_info *frame, |
3935 | CORE_ADDR pc, char *name) | |
c906108c | 3936 | { |
e17a4113 UW |
3937 | struct gdbarch *gdbarch = get_frame_arch (frame); |
3938 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
3939 | ||
3940 | /* jmp *(dest) */ | |
3941 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 3942 | { |
e17a4113 UW |
3943 | unsigned long indirect = |
3944 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 3945 | struct minimal_symbol *indsym = |
7cbd4a93 | 3946 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
efd66ac6 | 3947 | const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; |
c906108c | 3948 | |
c5aa993b | 3949 | if (symname) |
c906108c | 3950 | { |
61012eef GB |
3951 | if (startswith (symname, "__imp_") |
3952 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
3953 | return name ? 1 : |
3954 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
3955 | } |
3956 | } | |
fc338970 | 3957 | return 0; /* Not a trampoline. */ |
c906108c | 3958 | } |
fc338970 MK |
3959 | \f |
3960 | ||
10458914 DJ |
3961 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
3962 | routine. */ | |
8201327c | 3963 | |
4bd207ef | 3964 | int |
10458914 | 3965 | i386_sigtramp_p (struct frame_info *this_frame) |
8201327c | 3966 | { |
10458914 | 3967 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 3968 | const char *name; |
911bc6ee MK |
3969 | |
3970 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
3971 | return (name && strcmp ("_sigtramp", name) == 0); |
3972 | } | |
3973 | \f | |
3974 | ||
fc338970 MK |
3975 | /* We have two flavours of disassembly. The machinery on this page |
3976 | deals with switching between those. */ | |
c906108c SS |
3977 | |
3978 | static int | |
a89aa300 | 3979 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 3980 | { |
5e3397bb MK |
3981 | gdb_assert (disassembly_flavor == att_flavor |
3982 | || disassembly_flavor == intel_flavor); | |
3983 | ||
3984 | /* FIXME: kettenis/20020915: Until disassembler_options is properly | |
3985 | constified, cast to prevent a compiler warning. */ | |
3986 | info->disassembler_options = (char *) disassembly_flavor; | |
5e3397bb MK |
3987 | |
3988 | return print_insn_i386 (pc, info); | |
7a292a7a | 3989 | } |
fc338970 | 3990 | \f |
3ce1502b | 3991 | |
8201327c MK |
3992 | /* There are a few i386 architecture variants that differ only |
3993 | slightly from the generic i386 target. For now, we don't give them | |
3994 | their own source file, but include them here. As a consequence, | |
3995 | they'll always be included. */ | |
3ce1502b | 3996 | |
8201327c | 3997 | /* System V Release 4 (SVR4). */ |
3ce1502b | 3998 | |
10458914 DJ |
3999 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4000 | routine. */ | |
911bc6ee | 4001 | |
8201327c | 4002 | static int |
10458914 | 4003 | i386_svr4_sigtramp_p (struct frame_info *this_frame) |
d2a7c97a | 4004 | { |
10458914 | 4005 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4006 | const char *name; |
911bc6ee | 4007 | |
05b4bd79 | 4008 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4009 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4010 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4011 | || strcmp ("sigvechandler", name) == 0)); |
4012 | } | |
d2a7c97a | 4013 | |
10458914 DJ |
4014 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4015 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4016 | |
3a1e71e3 | 4017 | static CORE_ADDR |
10458914 | 4018 | i386_svr4_sigcontext_addr (struct frame_info *this_frame) |
8201327c | 4019 | { |
e17a4113 UW |
4020 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4021 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4022 | gdb_byte buf[4]; |
acd5c798 | 4023 | CORE_ADDR sp; |
3ce1502b | 4024 | |
10458914 | 4025 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4026 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4027 | |
e17a4113 | 4028 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4029 | } |
55aa24fb SDJ |
4030 | |
4031 | \f | |
4032 | ||
4033 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4034 | gdbarch.h. */ | |
4035 | ||
4036 | int | |
4037 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4038 | { | |
4039 | return (*s == '$' /* Literal number. */ | |
4040 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4041 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4042 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4043 | } | |
4044 | ||
5acfdbae SDJ |
4045 | /* Helper function for i386_stap_parse_special_token. |
4046 | ||
4047 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4048 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4049 | ||
4050 | Return 1 if the operand was parsed successfully, zero | |
4051 | otherwise. */ | |
4052 | ||
4053 | static int | |
4054 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, | |
4055 | struct stap_parse_info *p) | |
4056 | { | |
4057 | const char *s = p->arg; | |
4058 | ||
4059 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4060 | { | |
4061 | int got_minus[3]; | |
4062 | int i; | |
4063 | long displacements[3]; | |
4064 | const char *start; | |
4065 | char *regname; | |
4066 | int len; | |
4067 | struct stoken str; | |
4068 | char *endp; | |
4069 | ||
4070 | got_minus[0] = 0; | |
4071 | if (*s == '+') | |
4072 | ++s; | |
4073 | else if (*s == '-') | |
4074 | { | |
4075 | ++s; | |
4076 | got_minus[0] = 1; | |
4077 | } | |
4078 | ||
d7b30f67 SDJ |
4079 | if (!isdigit ((unsigned char) *s)) |
4080 | return 0; | |
4081 | ||
5acfdbae SDJ |
4082 | displacements[0] = strtol (s, &endp, 10); |
4083 | s = endp; | |
4084 | ||
4085 | if (*s != '+' && *s != '-') | |
4086 | { | |
4087 | /* We are not dealing with a triplet. */ | |
4088 | return 0; | |
4089 | } | |
4090 | ||
4091 | got_minus[1] = 0; | |
4092 | if (*s == '+') | |
4093 | ++s; | |
4094 | else | |
4095 | { | |
4096 | ++s; | |
4097 | got_minus[1] = 1; | |
4098 | } | |
4099 | ||
d7b30f67 SDJ |
4100 | if (!isdigit ((unsigned char) *s)) |
4101 | return 0; | |
4102 | ||
5acfdbae SDJ |
4103 | displacements[1] = strtol (s, &endp, 10); |
4104 | s = endp; | |
4105 | ||
4106 | if (*s != '+' && *s != '-') | |
4107 | { | |
4108 | /* We are not dealing with a triplet. */ | |
4109 | return 0; | |
4110 | } | |
4111 | ||
4112 | got_minus[2] = 0; | |
4113 | if (*s == '+') | |
4114 | ++s; | |
4115 | else | |
4116 | { | |
4117 | ++s; | |
4118 | got_minus[2] = 1; | |
4119 | } | |
4120 | ||
d7b30f67 SDJ |
4121 | if (!isdigit ((unsigned char) *s)) |
4122 | return 0; | |
4123 | ||
5acfdbae SDJ |
4124 | displacements[2] = strtol (s, &endp, 10); |
4125 | s = endp; | |
4126 | ||
4127 | if (*s != '(' || s[1] != '%') | |
4128 | return 0; | |
4129 | ||
4130 | s += 2; | |
4131 | start = s; | |
4132 | ||
4133 | while (isalnum (*s)) | |
4134 | ++s; | |
4135 | ||
4136 | if (*s++ != ')') | |
4137 | return 0; | |
4138 | ||
d7b30f67 | 4139 | len = s - start - 1; |
224c3ddb | 4140 | regname = (char *) alloca (len + 1); |
5acfdbae SDJ |
4141 | |
4142 | strncpy (regname, start, len); | |
4143 | regname[len] = '\0'; | |
4144 | ||
4145 | if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) | |
4146 | error (_("Invalid register name `%s' on expression `%s'."), | |
4147 | regname, p->saved_arg); | |
4148 | ||
4149 | for (i = 0; i < 3; i++) | |
4150 | { | |
410a0ff2 SDJ |
4151 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4152 | write_exp_elt_type | |
4153 | (&p->pstate, builtin_type (gdbarch)->builtin_long); | |
4154 | write_exp_elt_longcst (&p->pstate, displacements[i]); | |
4155 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4156 | if (got_minus[i]) |
410a0ff2 | 4157 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4158 | } |
4159 | ||
410a0ff2 | 4160 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4161 | str.ptr = regname; |
4162 | str.length = len; | |
410a0ff2 SDJ |
4163 | write_exp_string (&p->pstate, str); |
4164 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae | 4165 | |
410a0ff2 SDJ |
4166 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4167 | write_exp_elt_type (&p->pstate, | |
4168 | builtin_type (gdbarch)->builtin_data_ptr); | |
4169 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4170 | |
410a0ff2 SDJ |
4171 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
4172 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
4173 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); | |
5acfdbae | 4174 | |
410a0ff2 SDJ |
4175 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4176 | write_exp_elt_type (&p->pstate, | |
4177 | lookup_pointer_type (p->arg_type)); | |
4178 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4179 | |
410a0ff2 | 4180 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4181 | |
4182 | p->arg = s; | |
4183 | ||
4184 | return 1; | |
4185 | } | |
4186 | ||
4187 | return 0; | |
4188 | } | |
4189 | ||
4190 | /* Helper function for i386_stap_parse_special_token. | |
4191 | ||
4192 | This function parses operands of the form `register base + | |
4193 | (register index * size) + offset', as represented in | |
4194 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4195 | ||
4196 | Return 1 if the operand was parsed successfully, zero | |
4197 | otherwise. */ | |
4198 | ||
4199 | static int | |
4200 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, | |
4201 | struct stap_parse_info *p) | |
4202 | { | |
4203 | const char *s = p->arg; | |
4204 | ||
4205 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4206 | { | |
4207 | int offset_minus = 0; | |
4208 | long offset = 0; | |
4209 | int size_minus = 0; | |
4210 | long size = 0; | |
4211 | const char *start; | |
4212 | char *base; | |
4213 | int len_base; | |
4214 | char *index; | |
4215 | int len_index; | |
4216 | struct stoken base_token, index_token; | |
4217 | ||
4218 | if (*s == '+') | |
4219 | ++s; | |
4220 | else if (*s == '-') | |
4221 | { | |
4222 | ++s; | |
4223 | offset_minus = 1; | |
4224 | } | |
4225 | ||
4226 | if (offset_minus && !isdigit (*s)) | |
4227 | return 0; | |
4228 | ||
4229 | if (isdigit (*s)) | |
4230 | { | |
4231 | char *endp; | |
4232 | ||
4233 | offset = strtol (s, &endp, 10); | |
4234 | s = endp; | |
4235 | } | |
4236 | ||
4237 | if (*s != '(' || s[1] != '%') | |
4238 | return 0; | |
4239 | ||
4240 | s += 2; | |
4241 | start = s; | |
4242 | ||
4243 | while (isalnum (*s)) | |
4244 | ++s; | |
4245 | ||
4246 | if (*s != ',' || s[1] != '%') | |
4247 | return 0; | |
4248 | ||
4249 | len_base = s - start; | |
224c3ddb | 4250 | base = (char *) alloca (len_base + 1); |
5acfdbae SDJ |
4251 | strncpy (base, start, len_base); |
4252 | base[len_base] = '\0'; | |
4253 | ||
4254 | if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) | |
4255 | error (_("Invalid register name `%s' on expression `%s'."), | |
4256 | base, p->saved_arg); | |
4257 | ||
4258 | s += 2; | |
4259 | start = s; | |
4260 | ||
4261 | while (isalnum (*s)) | |
4262 | ++s; | |
4263 | ||
4264 | len_index = s - start; | |
224c3ddb | 4265 | index = (char *) alloca (len_index + 1); |
5acfdbae SDJ |
4266 | strncpy (index, start, len_index); |
4267 | index[len_index] = '\0'; | |
4268 | ||
4269 | if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) | |
4270 | error (_("Invalid register name `%s' on expression `%s'."), | |
4271 | index, p->saved_arg); | |
4272 | ||
4273 | if (*s != ',' && *s != ')') | |
4274 | return 0; | |
4275 | ||
4276 | if (*s == ',') | |
4277 | { | |
4278 | char *endp; | |
4279 | ||
4280 | ++s; | |
4281 | if (*s == '+') | |
4282 | ++s; | |
4283 | else if (*s == '-') | |
4284 | { | |
4285 | ++s; | |
4286 | size_minus = 1; | |
4287 | } | |
4288 | ||
4289 | size = strtol (s, &endp, 10); | |
4290 | s = endp; | |
4291 | ||
4292 | if (*s != ')') | |
4293 | return 0; | |
4294 | } | |
4295 | ||
4296 | ++s; | |
4297 | ||
4298 | if (offset) | |
4299 | { | |
410a0ff2 SDJ |
4300 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4301 | write_exp_elt_type (&p->pstate, | |
4302 | builtin_type (gdbarch)->builtin_long); | |
4303 | write_exp_elt_longcst (&p->pstate, offset); | |
4304 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4305 | if (offset_minus) |
410a0ff2 | 4306 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
5acfdbae SDJ |
4307 | } |
4308 | ||
410a0ff2 | 4309 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4310 | base_token.ptr = base; |
4311 | base_token.length = len_base; | |
410a0ff2 SDJ |
4312 | write_exp_string (&p->pstate, base_token); |
4313 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4314 | |
4315 | if (offset) | |
410a0ff2 | 4316 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4317 | |
410a0ff2 | 4318 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); |
5acfdbae SDJ |
4319 | index_token.ptr = index; |
4320 | index_token.length = len_index; | |
410a0ff2 SDJ |
4321 | write_exp_string (&p->pstate, index_token); |
4322 | write_exp_elt_opcode (&p->pstate, OP_REGISTER); | |
5acfdbae SDJ |
4323 | |
4324 | if (size) | |
4325 | { | |
410a0ff2 SDJ |
4326 | write_exp_elt_opcode (&p->pstate, OP_LONG); |
4327 | write_exp_elt_type (&p->pstate, | |
4328 | builtin_type (gdbarch)->builtin_long); | |
4329 | write_exp_elt_longcst (&p->pstate, size); | |
4330 | write_exp_elt_opcode (&p->pstate, OP_LONG); | |
5acfdbae | 4331 | if (size_minus) |
410a0ff2 SDJ |
4332 | write_exp_elt_opcode (&p->pstate, UNOP_NEG); |
4333 | write_exp_elt_opcode (&p->pstate, BINOP_MUL); | |
5acfdbae SDJ |
4334 | } |
4335 | ||
410a0ff2 | 4336 | write_exp_elt_opcode (&p->pstate, BINOP_ADD); |
5acfdbae | 4337 | |
410a0ff2 SDJ |
4338 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); |
4339 | write_exp_elt_type (&p->pstate, | |
4340 | lookup_pointer_type (p->arg_type)); | |
4341 | write_exp_elt_opcode (&p->pstate, UNOP_CAST); | |
5acfdbae | 4342 | |
410a0ff2 | 4343 | write_exp_elt_opcode (&p->pstate, UNOP_IND); |
5acfdbae SDJ |
4344 | |
4345 | p->arg = s; | |
4346 | ||
4347 | return 1; | |
4348 | } | |
4349 | ||
4350 | return 0; | |
4351 | } | |
4352 | ||
55aa24fb SDJ |
4353 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4354 | gdbarch.h. */ | |
4355 | ||
4356 | int | |
4357 | i386_stap_parse_special_token (struct gdbarch *gdbarch, | |
4358 | struct stap_parse_info *p) | |
4359 | { | |
55aa24fb SDJ |
4360 | /* In order to parse special tokens, we use a state-machine that go |
4361 | through every known token and try to get a match. */ | |
4362 | enum | |
4363 | { | |
4364 | TRIPLET, | |
4365 | THREE_ARG_DISPLACEMENT, | |
4366 | DONE | |
570dc176 TT |
4367 | }; |
4368 | int current_state; | |
55aa24fb SDJ |
4369 | |
4370 | current_state = TRIPLET; | |
4371 | ||
4372 | /* The special tokens to be parsed here are: | |
4373 | ||
4374 | - `register base + (register index * size) + offset', as represented | |
4375 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4376 | ||
4377 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4378 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4379 | ||
4380 | while (current_state != DONE) | |
4381 | { | |
55aa24fb SDJ |
4382 | switch (current_state) |
4383 | { | |
4384 | case TRIPLET: | |
5acfdbae SDJ |
4385 | if (i386_stap_parse_special_token_triplet (gdbarch, p)) |
4386 | return 1; | |
4387 | break; | |
4388 | ||
55aa24fb | 4389 | case THREE_ARG_DISPLACEMENT: |
5acfdbae SDJ |
4390 | if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) |
4391 | return 1; | |
4392 | break; | |
55aa24fb SDJ |
4393 | } |
4394 | ||
4395 | /* Advancing to the next state. */ | |
4396 | ++current_state; | |
4397 | } | |
4398 | ||
4399 | return 0; | |
4400 | } | |
4401 | ||
8201327c | 4402 | \f |
3ce1502b | 4403 | |
ac04f72b TT |
4404 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4405 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4406 | ||
4407 | static const char * | |
4408 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4409 | { | |
4410 | return "(x86_64|i.86)"; | |
4411 | } | |
4412 | ||
4413 | \f | |
4414 | ||
8201327c | 4415 | /* Generic ELF. */ |
d2a7c97a | 4416 | |
8201327c MK |
4417 | void |
4418 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4419 | { | |
05c0465e SDJ |
4420 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4421 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4422 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4423 | NULL }; | |
4424 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4425 | NULL }; | |
4426 | ||
c4fc7f1b MK |
4427 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4428 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4429 | |
4430 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4431 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4432 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4433 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4434 | stap_register_indirection_prefixes); | |
4435 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4436 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4437 | set_gdbarch_stap_is_single_operand (gdbarch, |
4438 | i386_stap_is_single_operand); | |
4439 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4440 | i386_stap_parse_special_token); | |
ac04f72b TT |
4441 | |
4442 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
8201327c | 4443 | } |
3ce1502b | 4444 | |
8201327c | 4445 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4446 | |
8201327c MK |
4447 | void |
4448 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4449 | { | |
4450 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3ce1502b | 4451 | |
8201327c MK |
4452 | /* System V Release 4 uses ELF. */ |
4453 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4454 | |
dfe01d39 | 4455 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4456 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4457 | ||
911bc6ee | 4458 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4459 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4460 | tdep->sc_pc_offset = 36 + 14 * 4; |
4461 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4462 | |
8201327c | 4463 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4464 | } |
4465 | ||
8201327c | 4466 | /* DJGPP. */ |
3ce1502b | 4467 | |
3a1e71e3 | 4468 | static void |
8201327c | 4469 | i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) |
3ce1502b | 4470 | { |
8201327c | 4471 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3ce1502b | 4472 | |
911bc6ee MK |
4473 | /* DJGPP doesn't have any special frames for signal handlers. */ |
4474 | tdep->sigtramp_p = NULL; | |
3ce1502b | 4475 | |
8201327c | 4476 | tdep->jb_pc_offset = 36; |
15430fc0 EZ |
4477 | |
4478 | /* DJGPP does not support the SSE registers. */ | |
3a13a53b L |
4479 | if (! tdesc_has_registers (info.target_desc)) |
4480 | tdep->tdesc = tdesc_i386_mmx; | |
3d22076f EZ |
4481 | |
4482 | /* Native compiler is GCC, which uses the SVR4 register numbering | |
4483 | even in COFF and STABS. See the comment in i386_gdbarch_init, | |
4484 | before the calls to set_gdbarch_stab_reg_to_regnum and | |
4485 | set_gdbarch_sdb_reg_to_regnum. */ | |
4486 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
4487 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
ab38a727 PA |
4488 | |
4489 | set_gdbarch_has_dos_based_file_system (gdbarch, 1); | |
ac04f72b TT |
4490 | |
4491 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); | |
3ce1502b | 4492 | } |
8201327c | 4493 | \f |
2acceee2 | 4494 | |
38c968cf AC |
4495 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4496 | and "sse". */ | |
4497 | ||
4498 | static struct reggroup *i386_sse_reggroup; | |
4499 | static struct reggroup *i386_mmx_reggroup; | |
4500 | ||
4501 | static void | |
4502 | i386_init_reggroups (void) | |
4503 | { | |
4504 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4505 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4506 | } | |
4507 | ||
4508 | static void | |
4509 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4510 | { | |
4511 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4512 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
4513 | reggroup_add (gdbarch, general_reggroup); | |
4514 | reggroup_add (gdbarch, float_reggroup); | |
4515 | reggroup_add (gdbarch, all_reggroup); | |
4516 | reggroup_add (gdbarch, save_reggroup); | |
4517 | reggroup_add (gdbarch, restore_reggroup); | |
4518 | reggroup_add (gdbarch, vector_reggroup); | |
4519 | reggroup_add (gdbarch, system_reggroup); | |
4520 | } | |
4521 | ||
4522 | int | |
4523 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
4524 | struct reggroup *group) | |
4525 | { | |
c131fcee L |
4526 | const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4527 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, | |
01f9f808 MS |
4528 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
4529 | bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, | |
4530 | zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
4531 | avx512_p, avx_p, sse_p; | |
acd5c798 | 4532 | |
1ba53b71 L |
4533 | /* Don't include pseudo registers, except for MMX, in any register |
4534 | groups. */ | |
c131fcee | 4535 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4536 | return 0; |
4537 | ||
c131fcee | 4538 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4539 | return 0; |
4540 | ||
c131fcee | 4541 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4542 | return 0; |
4543 | ||
4544 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4545 | if (group == i386_mmx_reggroup) |
4546 | return mmx_regnum_p; | |
1ba53b71 | 4547 | |
c131fcee | 4548 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4549 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4550 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4551 | if (group == i386_sse_reggroup) |
01f9f808 | 4552 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4553 | |
4554 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4555 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4556 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4557 | ||
df7e5265 GB |
4558 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) |
4559 | == X86_XSTATE_AVX512_MASK); | |
4560 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4561 | == X86_XSTATE_AVX_MASK) && !avx512_p; | |
4562 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) | |
4563 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; | |
01f9f808 | 4564 | |
38c968cf | 4565 | if (group == vector_reggroup) |
c131fcee | 4566 | return (mmx_regnum_p |
01f9f808 MS |
4567 | || (zmm_regnum_p && avx512_p) |
4568 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4569 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4570 | || mxcsr_regnum_p); | |
1ba53b71 L |
4571 | |
4572 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4573 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4574 | if (group == float_reggroup) |
4575 | return fp_regnum_p; | |
1ba53b71 | 4576 | |
c131fcee L |
4577 | /* For "info reg all", don't include upper YMM registers nor XMM |
4578 | registers when AVX is supported. */ | |
4579 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4580 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4581 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4582 | if (group == all_reggroup |
01f9f808 MS |
4583 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4584 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4585 | || ymmh_regnum_p | |
4586 | || ymmh_avx512_regnum_p | |
4587 | || zmmh_regnum_p)) | |
c131fcee L |
4588 | return 0; |
4589 | ||
1dbcd68c WT |
4590 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4591 | if (group == all_reggroup | |
df7e5265 | 4592 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4593 | return bnd_regnum_p; |
4594 | ||
4595 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4596 | if (group == all_reggroup | |
df7e5265 | 4597 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4598 | return 0; |
4599 | ||
4600 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4601 | if (group == all_reggroup | |
df7e5265 | 4602 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4603 | return mpx_ctrl_regnum_p; |
4604 | ||
38c968cf | 4605 | if (group == general_reggroup) |
1ba53b71 L |
4606 | return (!fp_regnum_p |
4607 | && !mmx_regnum_p | |
c131fcee L |
4608 | && !mxcsr_regnum_p |
4609 | && !xmm_regnum_p | |
01f9f808 | 4610 | && !xmm_avx512_regnum_p |
c131fcee | 4611 | && !ymm_regnum_p |
1dbcd68c | 4612 | && !ymmh_regnum_p |
01f9f808 MS |
4613 | && !ymm_avx512_regnum_p |
4614 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4615 | && !bndr_regnum_p |
4616 | && !bnd_regnum_p | |
01f9f808 MS |
4617 | && !mpx_ctrl_regnum_p |
4618 | && !zmm_regnum_p | |
4619 | && !zmmh_regnum_p); | |
acd5c798 | 4620 | |
38c968cf AC |
4621 | return default_register_reggroup_p (gdbarch, regnum, group); |
4622 | } | |
38c968cf | 4623 | \f |
acd5c798 | 4624 | |
f837910f MK |
4625 | /* Get the ARGIth function argument for the current function. */ |
4626 | ||
42c466d7 | 4627 | static CORE_ADDR |
143985b7 AF |
4628 | i386_fetch_pointer_argument (struct frame_info *frame, int argi, |
4629 | struct type *type) | |
4630 | { | |
e17a4113 UW |
4631 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4632 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4633 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4634 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4635 | } |
4636 | ||
7ad10968 HZ |
4637 | #define PREFIX_REPZ 0x01 |
4638 | #define PREFIX_REPNZ 0x02 | |
4639 | #define PREFIX_LOCK 0x04 | |
4640 | #define PREFIX_DATA 0x08 | |
4641 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4642 | |
7ad10968 HZ |
4643 | /* operand size */ |
4644 | enum | |
4645 | { | |
4646 | OT_BYTE = 0, | |
4647 | OT_WORD, | |
4648 | OT_LONG, | |
cf648174 | 4649 | OT_QUAD, |
a3c4230a | 4650 | OT_DQUAD, |
7ad10968 | 4651 | }; |
473f17b0 | 4652 | |
7ad10968 HZ |
4653 | /* i386 arith/logic operations */ |
4654 | enum | |
4655 | { | |
4656 | OP_ADDL, | |
4657 | OP_ORL, | |
4658 | OP_ADCL, | |
4659 | OP_SBBL, | |
4660 | OP_ANDL, | |
4661 | OP_SUBL, | |
4662 | OP_XORL, | |
4663 | OP_CMPL, | |
4664 | }; | |
5716833c | 4665 | |
7ad10968 HZ |
4666 | struct i386_record_s |
4667 | { | |
cf648174 | 4668 | struct gdbarch *gdbarch; |
7ad10968 | 4669 | struct regcache *regcache; |
df61f520 | 4670 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4671 | CORE_ADDR addr; |
4672 | int aflag; | |
4673 | int dflag; | |
4674 | int override; | |
4675 | uint8_t modrm; | |
4676 | uint8_t mod, reg, rm; | |
4677 | int ot; | |
cf648174 HZ |
4678 | uint8_t rex_x; |
4679 | uint8_t rex_b; | |
4680 | int rip_offset; | |
4681 | int popl_esp_hack; | |
4682 | const int *regmap; | |
7ad10968 | 4683 | }; |
5716833c | 4684 | |
99c1624c PA |
4685 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4686 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4687 | |
7ad10968 HZ |
4688 | static int |
4689 | i386_record_modrm (struct i386_record_s *irp) | |
4690 | { | |
cf648174 | 4691 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4692 | |
4ffa4fc7 PA |
4693 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4694 | return -1; | |
4695 | ||
7ad10968 HZ |
4696 | irp->addr++; |
4697 | irp->mod = (irp->modrm >> 6) & 3; | |
4698 | irp->reg = (irp->modrm >> 3) & 7; | |
4699 | irp->rm = irp->modrm & 7; | |
5716833c | 4700 | |
7ad10968 HZ |
4701 | return 0; |
4702 | } | |
d2a7c97a | 4703 | |
99c1624c PA |
4704 | /* Extract the memory address that the current instruction writes to, |
4705 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4706 | |
7ad10968 | 4707 | static int |
cf648174 | 4708 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4709 | { |
cf648174 | 4710 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4711 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4712 | gdb_byte buf[4]; | |
4713 | ULONGEST offset64; | |
21d0e8a4 | 4714 | |
7ad10968 | 4715 | *addr = 0; |
1e87984a | 4716 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4717 | { |
1e87984a | 4718 | /* 32/64 bits */ |
7ad10968 HZ |
4719 | int havesib = 0; |
4720 | uint8_t scale = 0; | |
648d0c8b | 4721 | uint8_t byte; |
7ad10968 HZ |
4722 | uint8_t index = 0; |
4723 | uint8_t base = irp->rm; | |
896fb97d | 4724 | |
7ad10968 HZ |
4725 | if (base == 4) |
4726 | { | |
4727 | havesib = 1; | |
4ffa4fc7 PA |
4728 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4729 | return -1; | |
7ad10968 | 4730 | irp->addr++; |
648d0c8b MS |
4731 | scale = (byte >> 6) & 3; |
4732 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4733 | base = (byte & 7); | |
7ad10968 | 4734 | } |
cf648174 | 4735 | base |= irp->rex_b; |
21d0e8a4 | 4736 | |
7ad10968 HZ |
4737 | switch (irp->mod) |
4738 | { | |
4739 | case 0: | |
4740 | if ((base & 7) == 5) | |
4741 | { | |
4742 | base = 0xff; | |
4ffa4fc7 PA |
4743 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4744 | return -1; | |
7ad10968 | 4745 | irp->addr += 4; |
60a1502a | 4746 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4747 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4748 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4749 | } |
7ad10968 HZ |
4750 | break; |
4751 | case 1: | |
4ffa4fc7 PA |
4752 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4753 | return -1; | |
7ad10968 | 4754 | irp->addr++; |
60a1502a | 4755 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4756 | break; |
4757 | case 2: | |
4ffa4fc7 PA |
4758 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4759 | return -1; | |
60a1502a | 4760 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4761 | irp->addr += 4; |
4762 | break; | |
4763 | } | |
356a6b3e | 4764 | |
60a1502a | 4765 | offset64 = 0; |
7ad10968 | 4766 | if (base != 0xff) |
cf648174 HZ |
4767 | { |
4768 | if (base == 4 && irp->popl_esp_hack) | |
4769 | *addr += irp->popl_esp_hack; | |
4770 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
60a1502a | 4771 | &offset64); |
7ad10968 | 4772 | } |
cf648174 HZ |
4773 | if (irp->aflag == 2) |
4774 | { | |
60a1502a | 4775 | *addr += offset64; |
cf648174 HZ |
4776 | } |
4777 | else | |
60a1502a | 4778 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4779 | |
7ad10968 HZ |
4780 | if (havesib && (index != 4 || scale != 0)) |
4781 | { | |
cf648174 | 4782 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
60a1502a | 4783 | &offset64); |
cf648174 | 4784 | if (irp->aflag == 2) |
60a1502a | 4785 | *addr += offset64 << scale; |
cf648174 | 4786 | else |
60a1502a | 4787 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4788 | } |
e85596e0 L |
4789 | |
4790 | if (!irp->aflag) | |
4791 | { | |
4792 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4793 | address from 32-bit to 64-bit. */ | |
4794 | *addr = (uint32_t) *addr; | |
4795 | } | |
7ad10968 HZ |
4796 | } |
4797 | else | |
4798 | { | |
4799 | /* 16 bits */ | |
4800 | switch (irp->mod) | |
4801 | { | |
4802 | case 0: | |
4803 | if (irp->rm == 6) | |
4804 | { | |
4ffa4fc7 PA |
4805 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4806 | return -1; | |
7ad10968 | 4807 | irp->addr += 2; |
60a1502a | 4808 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4809 | irp->rm = 0; |
4810 | goto no_rm; | |
4811 | } | |
7ad10968 HZ |
4812 | break; |
4813 | case 1: | |
4ffa4fc7 PA |
4814 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4815 | return -1; | |
7ad10968 | 4816 | irp->addr++; |
60a1502a | 4817 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4818 | break; |
4819 | case 2: | |
4ffa4fc7 PA |
4820 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4821 | return -1; | |
7ad10968 | 4822 | irp->addr += 2; |
60a1502a | 4823 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4824 | break; |
4825 | } | |
c4fc7f1b | 4826 | |
7ad10968 HZ |
4827 | switch (irp->rm) |
4828 | { | |
4829 | case 0: | |
cf648174 HZ |
4830 | regcache_raw_read_unsigned (irp->regcache, |
4831 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4832 | &offset64); |
4833 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4834 | regcache_raw_read_unsigned (irp->regcache, |
4835 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4836 | &offset64); |
4837 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4838 | break; |
4839 | case 1: | |
cf648174 HZ |
4840 | regcache_raw_read_unsigned (irp->regcache, |
4841 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4842 | &offset64); |
4843 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4844 | regcache_raw_read_unsigned (irp->regcache, |
4845 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4846 | &offset64); |
4847 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4848 | break; |
4849 | case 2: | |
cf648174 HZ |
4850 | regcache_raw_read_unsigned (irp->regcache, |
4851 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4852 | &offset64); |
4853 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4854 | regcache_raw_read_unsigned (irp->regcache, |
4855 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4856 | &offset64); |
4857 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4858 | break; |
4859 | case 3: | |
cf648174 HZ |
4860 | regcache_raw_read_unsigned (irp->regcache, |
4861 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4862 | &offset64); |
4863 | *addr = (uint32_t) (*addr + offset64); | |
cf648174 HZ |
4864 | regcache_raw_read_unsigned (irp->regcache, |
4865 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4866 | &offset64); |
4867 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4868 | break; |
4869 | case 4: | |
cf648174 HZ |
4870 | regcache_raw_read_unsigned (irp->regcache, |
4871 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
60a1502a MS |
4872 | &offset64); |
4873 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4874 | break; |
4875 | case 5: | |
cf648174 HZ |
4876 | regcache_raw_read_unsigned (irp->regcache, |
4877 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
60a1502a MS |
4878 | &offset64); |
4879 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4880 | break; |
4881 | case 6: | |
cf648174 HZ |
4882 | regcache_raw_read_unsigned (irp->regcache, |
4883 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
60a1502a MS |
4884 | &offset64); |
4885 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4886 | break; |
4887 | case 7: | |
cf648174 HZ |
4888 | regcache_raw_read_unsigned (irp->regcache, |
4889 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
60a1502a MS |
4890 | &offset64); |
4891 | *addr = (uint32_t) (*addr + offset64); | |
7ad10968 HZ |
4892 | break; |
4893 | } | |
4894 | *addr &= 0xffff; | |
4895 | } | |
c4fc7f1b | 4896 | |
01fe1b41 | 4897 | no_rm: |
7ad10968 HZ |
4898 | return 0; |
4899 | } | |
c4fc7f1b | 4900 | |
99c1624c PA |
4901 | /* Record the address and contents of the memory that will be changed |
4902 | by the current instruction. Return -1 if something goes wrong, 0 | |
4903 | otherwise. */ | |
356a6b3e | 4904 | |
7ad10968 HZ |
4905 | static int |
4906 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4907 | { | |
cf648174 HZ |
4908 | struct gdbarch *gdbarch = irp->gdbarch; |
4909 | uint64_t addr; | |
356a6b3e | 4910 | |
d7877f7e | 4911 | if (irp->override >= 0) |
7ad10968 | 4912 | { |
25ea693b | 4913 | if (record_full_memory_query) |
bb08c432 | 4914 | { |
651ce16a | 4915 | if (yquery (_("\ |
bb08c432 HZ |
4916 | Process record ignores the memory change of instruction at address %s\n\ |
4917 | because it can't get the value of the segment register.\n\ | |
4918 | Do you want to stop the program?"), | |
651ce16a PA |
4919 | paddress (gdbarch, irp->orig_addr))) |
4920 | return -1; | |
bb08c432 HZ |
4921 | } |
4922 | ||
7ad10968 HZ |
4923 | return 0; |
4924 | } | |
61113f8b | 4925 | |
7ad10968 HZ |
4926 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4927 | return -1; | |
96297dab | 4928 | |
25ea693b | 4929 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4930 | return -1; |
a62cc96e | 4931 | |
7ad10968 HZ |
4932 | return 0; |
4933 | } | |
b6197528 | 4934 | |
99c1624c PA |
4935 | /* Record the effects of a push operation. Return -1 if something |
4936 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4937 | |
4938 | static int | |
4939 | i386_record_push (struct i386_record_s *irp, int size) | |
4940 | { | |
648d0c8b | 4941 | ULONGEST addr; |
cf648174 | 4942 | |
25ea693b MM |
4943 | if (record_full_arch_list_add_reg (irp->regcache, |
4944 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4945 | return -1; |
4946 | regcache_raw_read_unsigned (irp->regcache, | |
4947 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4948 | &addr); |
25ea693b | 4949 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4950 | return -1; |
4951 | ||
4952 | return 0; | |
4953 | } | |
4954 | ||
0289bdd7 MS |
4955 | |
4956 | /* Defines contents to record. */ | |
4957 | #define I386_SAVE_FPU_REGS 0xfffd | |
4958 | #define I386_SAVE_FPU_ENV 0xfffe | |
4959 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4960 | ||
99c1624c PA |
4961 | /* Record the values of the floating point registers which will be |
4962 | changed by the current instruction. Returns -1 if something is | |
4963 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
4964 | |
4965 | static int i386_record_floats (struct gdbarch *gdbarch, | |
4966 | struct i386_record_s *ir, | |
4967 | uint32_t iregnum) | |
4968 | { | |
4969 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4970 | int i; | |
4971 | ||
4972 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
4973 | happen. Currently we store st0-st7 registers, but we need not store all | |
4974 | registers all the time, in future we use ftag register and record only | |
4975 | those who are not marked as an empty. */ | |
4976 | ||
4977 | if (I386_SAVE_FPU_REGS == iregnum) | |
4978 | { | |
4979 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
4980 | { | |
25ea693b | 4981 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4982 | return -1; |
4983 | } | |
4984 | } | |
4985 | else if (I386_SAVE_FPU_ENV == iregnum) | |
4986 | { | |
4987 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4988 | { | |
25ea693b | 4989 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4990 | return -1; |
4991 | } | |
4992 | } | |
4993 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
4994 | { | |
4995 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
4996 | { | |
25ea693b | 4997 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
4998 | return -1; |
4999 | } | |
5000 | } | |
5001 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
5002 | (iregnum <= I387_FOP_REGNUM (tdep))) | |
5003 | { | |
25ea693b | 5004 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
0289bdd7 MS |
5005 | return -1; |
5006 | } | |
5007 | else | |
5008 | { | |
5009 | /* Parameter error. */ | |
5010 | return -1; | |
5011 | } | |
5012 | if(I386_SAVE_FPU_ENV != iregnum) | |
5013 | { | |
5014 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5015 | { | |
25ea693b | 5016 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
0289bdd7 MS |
5017 | return -1; |
5018 | } | |
5019 | } | |
5020 | return 0; | |
5021 | } | |
5022 | ||
99c1624c PA |
5023 | /* Parse the current instruction, and record the values of the |
5024 | registers and memory that will be changed by the current | |
5025 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5026 | |
25ea693b MM |
5027 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5028 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5029 | |
a6b808b4 | 5030 | int |
7ad10968 | 5031 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5032 | CORE_ADDR input_addr) |
7ad10968 | 5033 | { |
60a1502a | 5034 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5035 | int prefixes = 0; |
580879fc | 5036 | int regnum = 0; |
425b824a | 5037 | uint32_t opcode; |
f4644a3f | 5038 | uint8_t opcode8; |
648d0c8b | 5039 | ULONGEST addr; |
60a1502a | 5040 | gdb_byte buf[MAX_REGISTER_SIZE]; |
7ad10968 | 5041 | struct i386_record_s ir; |
0289bdd7 | 5042 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
cf648174 HZ |
5043 | uint8_t rex_w = -1; |
5044 | uint8_t rex_r = 0; | |
7ad10968 | 5045 | |
8408d274 | 5046 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5047 | ir.regcache = regcache; |
648d0c8b MS |
5048 | ir.addr = input_addr; |
5049 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5050 | ir.aflag = 1; |
5051 | ir.dflag = 1; | |
cf648174 HZ |
5052 | ir.override = -1; |
5053 | ir.popl_esp_hack = 0; | |
a3c4230a | 5054 | ir.regmap = tdep->record_regmap; |
cf648174 | 5055 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5056 | |
5057 | if (record_debug > 1) | |
5058 | fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " | |
5af949e3 UW |
5059 | "addr = %s\n", |
5060 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5061 | |
5062 | /* prefixes */ | |
5063 | while (1) | |
5064 | { | |
4ffa4fc7 PA |
5065 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5066 | return -1; | |
7ad10968 | 5067 | ir.addr++; |
425b824a | 5068 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5069 | { |
01fe1b41 | 5070 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5071 | prefixes |= PREFIX_REPZ; |
5072 | break; | |
01fe1b41 | 5073 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5074 | prefixes |= PREFIX_REPNZ; |
5075 | break; | |
01fe1b41 | 5076 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5077 | prefixes |= PREFIX_LOCK; |
5078 | break; | |
01fe1b41 | 5079 | case CS_PREFIX_OPCODE: |
cf648174 | 5080 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5081 | break; |
01fe1b41 | 5082 | case SS_PREFIX_OPCODE: |
cf648174 | 5083 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5084 | break; |
01fe1b41 | 5085 | case DS_PREFIX_OPCODE: |
cf648174 | 5086 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5087 | break; |
01fe1b41 | 5088 | case ES_PREFIX_OPCODE: |
cf648174 | 5089 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5090 | break; |
01fe1b41 | 5091 | case FS_PREFIX_OPCODE: |
cf648174 | 5092 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5093 | break; |
01fe1b41 | 5094 | case GS_PREFIX_OPCODE: |
cf648174 | 5095 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5096 | break; |
01fe1b41 | 5097 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5098 | prefixes |= PREFIX_DATA; |
5099 | break; | |
01fe1b41 | 5100 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5101 | prefixes |= PREFIX_ADDR; |
5102 | break; | |
d691bec7 MS |
5103 | case 0x40: /* i386 inc %eax */ |
5104 | case 0x41: /* i386 inc %ecx */ | |
5105 | case 0x42: /* i386 inc %edx */ | |
5106 | case 0x43: /* i386 inc %ebx */ | |
5107 | case 0x44: /* i386 inc %esp */ | |
5108 | case 0x45: /* i386 inc %ebp */ | |
5109 | case 0x46: /* i386 inc %esi */ | |
5110 | case 0x47: /* i386 inc %edi */ | |
5111 | case 0x48: /* i386 dec %eax */ | |
5112 | case 0x49: /* i386 dec %ecx */ | |
5113 | case 0x4a: /* i386 dec %edx */ | |
5114 | case 0x4b: /* i386 dec %ebx */ | |
5115 | case 0x4c: /* i386 dec %esp */ | |
5116 | case 0x4d: /* i386 dec %ebp */ | |
5117 | case 0x4e: /* i386 dec %esi */ | |
5118 | case 0x4f: /* i386 dec %edi */ | |
5119 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
cf648174 HZ |
5120 | { |
5121 | /* REX */ | |
425b824a MS |
5122 | rex_w = (opcode8 >> 3) & 1; |
5123 | rex_r = (opcode8 & 0x4) << 1; | |
5124 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5125 | ir.rex_b = (opcode8 & 0x1) << 3; | |
cf648174 | 5126 | } |
d691bec7 MS |
5127 | else /* 32 bit target */ |
5128 | goto out_prefixes; | |
cf648174 | 5129 | break; |
7ad10968 HZ |
5130 | default: |
5131 | goto out_prefixes; | |
5132 | break; | |
5133 | } | |
5134 | } | |
01fe1b41 | 5135 | out_prefixes: |
cf648174 HZ |
5136 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5137 | { | |
5138 | ir.dflag = 2; | |
5139 | } | |
5140 | else | |
5141 | { | |
5142 | if (prefixes & PREFIX_DATA) | |
5143 | ir.dflag ^= 1; | |
5144 | } | |
7ad10968 HZ |
5145 | if (prefixes & PREFIX_ADDR) |
5146 | ir.aflag ^= 1; | |
cf648174 HZ |
5147 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5148 | ir.aflag = 2; | |
7ad10968 | 5149 | |
1777feb0 | 5150 | /* Now check op code. */ |
425b824a | 5151 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5152 | reswitch: |
7ad10968 HZ |
5153 | switch (opcode) |
5154 | { | |
5155 | case 0x0f: | |
4ffa4fc7 PA |
5156 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5157 | return -1; | |
7ad10968 | 5158 | ir.addr++; |
a3c4230a | 5159 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5160 | goto reswitch; |
5161 | break; | |
93924b6b | 5162 | |
a38bba38 | 5163 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5164 | case 0x01: |
5165 | case 0x02: | |
5166 | case 0x03: | |
5167 | case 0x04: | |
5168 | case 0x05: | |
5169 | case 0x08: | |
5170 | case 0x09: | |
5171 | case 0x0a: | |
5172 | case 0x0b: | |
5173 | case 0x0c: | |
5174 | case 0x0d: | |
5175 | case 0x10: | |
5176 | case 0x11: | |
5177 | case 0x12: | |
5178 | case 0x13: | |
5179 | case 0x14: | |
5180 | case 0x15: | |
5181 | case 0x18: | |
5182 | case 0x19: | |
5183 | case 0x1a: | |
5184 | case 0x1b: | |
5185 | case 0x1c: | |
5186 | case 0x1d: | |
5187 | case 0x20: | |
5188 | case 0x21: | |
5189 | case 0x22: | |
5190 | case 0x23: | |
5191 | case 0x24: | |
5192 | case 0x25: | |
5193 | case 0x28: | |
5194 | case 0x29: | |
5195 | case 0x2a: | |
5196 | case 0x2b: | |
5197 | case 0x2c: | |
5198 | case 0x2d: | |
5199 | case 0x30: | |
5200 | case 0x31: | |
5201 | case 0x32: | |
5202 | case 0x33: | |
5203 | case 0x34: | |
5204 | case 0x35: | |
5205 | case 0x38: | |
5206 | case 0x39: | |
5207 | case 0x3a: | |
5208 | case 0x3b: | |
5209 | case 0x3c: | |
5210 | case 0x3d: | |
5211 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5212 | { | |
5213 | if ((opcode & 1) == 0) | |
5214 | ir.ot = OT_BYTE; | |
5215 | else | |
5216 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5217 | |
7ad10968 HZ |
5218 | switch ((opcode >> 1) & 3) |
5219 | { | |
a38bba38 | 5220 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5221 | if (i386_record_modrm (&ir)) |
5222 | return -1; | |
5223 | if (ir.mod != 3) | |
5224 | { | |
5225 | if (i386_record_lea_modrm (&ir)) | |
5226 | return -1; | |
5227 | } | |
5228 | else | |
5229 | { | |
cf648174 HZ |
5230 | ir.rm |= ir.rex_b; |
5231 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5232 | ir.rm &= 0x3; |
25ea693b | 5233 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5234 | } |
5235 | break; | |
a38bba38 | 5236 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5237 | if (i386_record_modrm (&ir)) |
5238 | return -1; | |
cf648174 HZ |
5239 | ir.reg |= rex_r; |
5240 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5241 | ir.reg &= 0x3; |
25ea693b | 5242 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5243 | break; |
a38bba38 | 5244 | case 2: /* OP A, Iv */ |
25ea693b | 5245 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5246 | break; |
5247 | } | |
5248 | } | |
25ea693b | 5249 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5250 | break; |
42fdc8df | 5251 | |
a38bba38 | 5252 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5253 | case 0x81: |
5254 | case 0x82: | |
5255 | case 0x83: | |
5256 | if (i386_record_modrm (&ir)) | |
5257 | return -1; | |
8201327c | 5258 | |
7ad10968 HZ |
5259 | if (ir.reg != OP_CMPL) |
5260 | { | |
5261 | if ((opcode & 1) == 0) | |
5262 | ir.ot = OT_BYTE; | |
5263 | else | |
5264 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5265 | |
7ad10968 HZ |
5266 | if (ir.mod != 3) |
5267 | { | |
cf648174 HZ |
5268 | if (opcode == 0x83) |
5269 | ir.rip_offset = 1; | |
5270 | else | |
5271 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5272 | if (i386_record_lea_modrm (&ir)) |
5273 | return -1; | |
5274 | } | |
5275 | else | |
25ea693b | 5276 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5277 | } |
25ea693b | 5278 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5279 | break; |
5e3397bb | 5280 | |
a38bba38 | 5281 | case 0x40: /* inc */ |
7ad10968 HZ |
5282 | case 0x41: |
5283 | case 0x42: | |
5284 | case 0x43: | |
5285 | case 0x44: | |
5286 | case 0x45: | |
5287 | case 0x46: | |
5288 | case 0x47: | |
a38bba38 MS |
5289 | |
5290 | case 0x48: /* dec */ | |
7ad10968 HZ |
5291 | case 0x49: |
5292 | case 0x4a: | |
5293 | case 0x4b: | |
5294 | case 0x4c: | |
5295 | case 0x4d: | |
5296 | case 0x4e: | |
5297 | case 0x4f: | |
a38bba38 | 5298 | |
25ea693b MM |
5299 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5300 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5301 | break; |
acd5c798 | 5302 | |
a38bba38 | 5303 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5304 | case 0xf7: |
5305 | if ((opcode & 1) == 0) | |
5306 | ir.ot = OT_BYTE; | |
5307 | else | |
5308 | ir.ot = ir.dflag + OT_WORD; | |
5309 | if (i386_record_modrm (&ir)) | |
5310 | return -1; | |
acd5c798 | 5311 | |
cf648174 HZ |
5312 | if (ir.mod != 3 && ir.reg == 0) |
5313 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5314 | ||
7ad10968 HZ |
5315 | switch (ir.reg) |
5316 | { | |
a38bba38 | 5317 | case 0: /* test */ |
25ea693b | 5318 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5319 | break; |
a38bba38 MS |
5320 | case 2: /* not */ |
5321 | case 3: /* neg */ | |
7ad10968 HZ |
5322 | if (ir.mod != 3) |
5323 | { | |
5324 | if (i386_record_lea_modrm (&ir)) | |
5325 | return -1; | |
5326 | } | |
5327 | else | |
5328 | { | |
cf648174 HZ |
5329 | ir.rm |= ir.rex_b; |
5330 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5331 | ir.rm &= 0x3; |
25ea693b | 5332 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5333 | } |
a38bba38 | 5334 | if (ir.reg == 3) /* neg */ |
25ea693b | 5335 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5336 | break; |
a38bba38 MS |
5337 | case 4: /* mul */ |
5338 | case 5: /* imul */ | |
5339 | case 6: /* div */ | |
5340 | case 7: /* idiv */ | |
25ea693b | 5341 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5342 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5343 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5344 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5345 | break; |
5346 | default: | |
5347 | ir.addr -= 2; | |
5348 | opcode = opcode << 8 | ir.modrm; | |
5349 | goto no_support; | |
5350 | break; | |
5351 | } | |
5352 | break; | |
5353 | ||
a38bba38 MS |
5354 | case 0xfe: /* GRP4 */ |
5355 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5356 | if (i386_record_modrm (&ir)) |
5357 | return -1; | |
5358 | if (ir.reg >= 2 && opcode == 0xfe) | |
5359 | { | |
5360 | ir.addr -= 2; | |
5361 | opcode = opcode << 8 | ir.modrm; | |
5362 | goto no_support; | |
5363 | } | |
7ad10968 HZ |
5364 | switch (ir.reg) |
5365 | { | |
a38bba38 MS |
5366 | case 0: /* inc */ |
5367 | case 1: /* dec */ | |
cf648174 HZ |
5368 | if ((opcode & 1) == 0) |
5369 | ir.ot = OT_BYTE; | |
5370 | else | |
5371 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5372 | if (ir.mod != 3) |
5373 | { | |
5374 | if (i386_record_lea_modrm (&ir)) | |
5375 | return -1; | |
5376 | } | |
5377 | else | |
5378 | { | |
cf648174 HZ |
5379 | ir.rm |= ir.rex_b; |
5380 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5381 | ir.rm &= 0x3; |
25ea693b | 5382 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5383 | } |
25ea693b | 5384 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5385 | break; |
a38bba38 | 5386 | case 2: /* call */ |
cf648174 HZ |
5387 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5388 | ir.dflag = 2; | |
5389 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5390 | return -1; |
25ea693b | 5391 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5392 | break; |
a38bba38 | 5393 | case 3: /* lcall */ |
25ea693b | 5394 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5395 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5396 | return -1; |
25ea693b | 5397 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5398 | break; |
a38bba38 MS |
5399 | case 4: /* jmp */ |
5400 | case 5: /* ljmp */ | |
25ea693b | 5401 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5402 | break; |
a38bba38 | 5403 | case 6: /* push */ |
cf648174 HZ |
5404 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5405 | ir.dflag = 2; | |
5406 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5407 | return -1; | |
7ad10968 HZ |
5408 | break; |
5409 | default: | |
5410 | ir.addr -= 2; | |
5411 | opcode = opcode << 8 | ir.modrm; | |
5412 | goto no_support; | |
5413 | break; | |
5414 | } | |
5415 | break; | |
5416 | ||
a38bba38 | 5417 | case 0x84: /* test */ |
7ad10968 HZ |
5418 | case 0x85: |
5419 | case 0xa8: | |
5420 | case 0xa9: | |
25ea693b | 5421 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5422 | break; |
5423 | ||
a38bba38 | 5424 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5425 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5426 | break; |
5427 | ||
a38bba38 | 5428 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5429 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5430 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5431 | break; |
5432 | ||
a38bba38 | 5433 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5434 | case 0x69: |
5435 | case 0x6b: | |
5436 | ir.ot = ir.dflag + OT_WORD; | |
5437 | if (i386_record_modrm (&ir)) | |
5438 | return -1; | |
cf648174 HZ |
5439 | if (opcode == 0x69) |
5440 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
5441 | else if (opcode == 0x6b) | |
5442 | ir.rip_offset = 1; | |
5443 | ir.reg |= rex_r; | |
5444 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5445 | ir.reg &= 0x3; |
25ea693b MM |
5446 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5447 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5448 | break; |
5449 | ||
a38bba38 | 5450 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5451 | case 0x0fc1: |
5452 | if ((opcode & 1) == 0) | |
5453 | ir.ot = OT_BYTE; | |
5454 | else | |
5455 | ir.ot = ir.dflag + OT_WORD; | |
5456 | if (i386_record_modrm (&ir)) | |
5457 | return -1; | |
cf648174 | 5458 | ir.reg |= rex_r; |
7ad10968 HZ |
5459 | if (ir.mod == 3) |
5460 | { | |
cf648174 | 5461 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5462 | ir.reg &= 0x3; |
25ea693b | 5463 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5464 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5465 | ir.rm &= 0x3; |
25ea693b | 5466 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5467 | } |
5468 | else | |
5469 | { | |
5470 | if (i386_record_lea_modrm (&ir)) | |
5471 | return -1; | |
cf648174 | 5472 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5473 | ir.reg &= 0x3; |
25ea693b | 5474 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5475 | } |
25ea693b | 5476 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5477 | break; |
5478 | ||
a38bba38 | 5479 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5480 | case 0x0fb1: |
5481 | if ((opcode & 1) == 0) | |
5482 | ir.ot = OT_BYTE; | |
5483 | else | |
5484 | ir.ot = ir.dflag + OT_WORD; | |
5485 | if (i386_record_modrm (&ir)) | |
5486 | return -1; | |
5487 | if (ir.mod == 3) | |
5488 | { | |
cf648174 | 5489 | ir.reg |= rex_r; |
25ea693b | 5490 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5491 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5492 | ir.reg &= 0x3; |
25ea693b | 5493 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5494 | } |
5495 | else | |
5496 | { | |
25ea693b | 5497 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5498 | if (i386_record_lea_modrm (&ir)) |
5499 | return -1; | |
5500 | } | |
25ea693b | 5501 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5502 | break; |
5503 | ||
a38bba38 | 5504 | case 0x0fc7: /* cmpxchg8b */ |
7ad10968 HZ |
5505 | if (i386_record_modrm (&ir)) |
5506 | return -1; | |
5507 | if (ir.mod == 3) | |
5508 | { | |
5509 | ir.addr -= 2; | |
5510 | opcode = opcode << 8 | ir.modrm; | |
5511 | goto no_support; | |
5512 | } | |
25ea693b MM |
5513 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5514 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5515 | if (i386_record_lea_modrm (&ir)) |
5516 | return -1; | |
25ea693b | 5517 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5518 | break; |
5519 | ||
a38bba38 | 5520 | case 0x50: /* push */ |
7ad10968 HZ |
5521 | case 0x51: |
5522 | case 0x52: | |
5523 | case 0x53: | |
5524 | case 0x54: | |
5525 | case 0x55: | |
5526 | case 0x56: | |
5527 | case 0x57: | |
5528 | case 0x68: | |
5529 | case 0x6a: | |
cf648174 HZ |
5530 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5531 | ir.dflag = 2; | |
5532 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5533 | return -1; | |
5534 | break; | |
5535 | ||
a38bba38 MS |
5536 | case 0x06: /* push es */ |
5537 | case 0x0e: /* push cs */ | |
5538 | case 0x16: /* push ss */ | |
5539 | case 0x1e: /* push ds */ | |
cf648174 HZ |
5540 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5541 | { | |
5542 | ir.addr -= 1; | |
5543 | goto no_support; | |
5544 | } | |
5545 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5546 | return -1; | |
5547 | break; | |
5548 | ||
a38bba38 MS |
5549 | case 0x0fa0: /* push fs */ |
5550 | case 0x0fa8: /* push gs */ | |
cf648174 HZ |
5551 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5552 | { | |
5553 | ir.addr -= 2; | |
5554 | goto no_support; | |
5555 | } | |
5556 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5557 | return -1; |
cf648174 HZ |
5558 | break; |
5559 | ||
a38bba38 | 5560 | case 0x60: /* pusha */ |
cf648174 HZ |
5561 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5562 | { | |
5563 | ir.addr -= 1; | |
5564 | goto no_support; | |
5565 | } | |
5566 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5567 | return -1; |
5568 | break; | |
5569 | ||
a38bba38 | 5570 | case 0x58: /* pop */ |
7ad10968 HZ |
5571 | case 0x59: |
5572 | case 0x5a: | |
5573 | case 0x5b: | |
5574 | case 0x5c: | |
5575 | case 0x5d: | |
5576 | case 0x5e: | |
5577 | case 0x5f: | |
25ea693b MM |
5578 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5579 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5580 | break; |
5581 | ||
a38bba38 | 5582 | case 0x61: /* popa */ |
cf648174 HZ |
5583 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5584 | { | |
5585 | ir.addr -= 1; | |
5586 | goto no_support; | |
7ad10968 | 5587 | } |
425b824a MS |
5588 | for (regnum = X86_RECORD_REAX_REGNUM; |
5589 | regnum <= X86_RECORD_REDI_REGNUM; | |
5590 | regnum++) | |
25ea693b | 5591 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5592 | break; |
5593 | ||
a38bba38 | 5594 | case 0x8f: /* pop */ |
cf648174 HZ |
5595 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5596 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5597 | else | |
5598 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5599 | if (i386_record_modrm (&ir)) |
5600 | return -1; | |
5601 | if (ir.mod == 3) | |
25ea693b | 5602 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5603 | else |
5604 | { | |
cf648174 | 5605 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5606 | if (i386_record_lea_modrm (&ir)) |
5607 | return -1; | |
5608 | } | |
25ea693b | 5609 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5610 | break; |
5611 | ||
a38bba38 | 5612 | case 0xc8: /* enter */ |
25ea693b | 5613 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 HZ |
5614 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5615 | ir.dflag = 2; | |
5616 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 HZ |
5617 | return -1; |
5618 | break; | |
5619 | ||
a38bba38 | 5620 | case 0xc9: /* leave */ |
25ea693b MM |
5621 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5622 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5623 | break; |
5624 | ||
a38bba38 | 5625 | case 0x07: /* pop es */ |
cf648174 HZ |
5626 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5627 | { | |
5628 | ir.addr -= 1; | |
5629 | goto no_support; | |
5630 | } | |
25ea693b MM |
5631 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5632 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5633 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5634 | break; |
5635 | ||
a38bba38 | 5636 | case 0x17: /* pop ss */ |
cf648174 HZ |
5637 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5638 | { | |
5639 | ir.addr -= 1; | |
5640 | goto no_support; | |
5641 | } | |
25ea693b MM |
5642 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5643 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5644 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5645 | break; |
5646 | ||
a38bba38 | 5647 | case 0x1f: /* pop ds */ |
cf648174 HZ |
5648 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5649 | { | |
5650 | ir.addr -= 1; | |
5651 | goto no_support; | |
5652 | } | |
25ea693b MM |
5653 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5654 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5655 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5656 | break; |
5657 | ||
a38bba38 | 5658 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5659 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5660 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5661 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5662 | break; |
5663 | ||
a38bba38 | 5664 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5665 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5666 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5667 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5668 | break; |
5669 | ||
a38bba38 | 5670 | case 0x88: /* mov */ |
7ad10968 HZ |
5671 | case 0x89: |
5672 | case 0xc6: | |
5673 | case 0xc7: | |
5674 | if ((opcode & 1) == 0) | |
5675 | ir.ot = OT_BYTE; | |
5676 | else | |
5677 | ir.ot = ir.dflag + OT_WORD; | |
5678 | ||
5679 | if (i386_record_modrm (&ir)) | |
5680 | return -1; | |
5681 | ||
5682 | if (ir.mod != 3) | |
5683 | { | |
cf648174 HZ |
5684 | if (opcode == 0xc6 || opcode == 0xc7) |
5685 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5686 | if (i386_record_lea_modrm (&ir)) |
5687 | return -1; | |
5688 | } | |
5689 | else | |
5690 | { | |
cf648174 HZ |
5691 | if (opcode == 0xc6 || opcode == 0xc7) |
5692 | ir.rm |= ir.rex_b; | |
5693 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5694 | ir.rm &= 0x3; |
25ea693b | 5695 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5696 | } |
7ad10968 | 5697 | break; |
cf648174 | 5698 | |
a38bba38 | 5699 | case 0x8a: /* mov */ |
7ad10968 HZ |
5700 | case 0x8b: |
5701 | if ((opcode & 1) == 0) | |
5702 | ir.ot = OT_BYTE; | |
5703 | else | |
5704 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5705 | if (i386_record_modrm (&ir)) |
5706 | return -1; | |
cf648174 HZ |
5707 | ir.reg |= rex_r; |
5708 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5709 | ir.reg &= 0x3; |
25ea693b | 5710 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5711 | break; |
7ad10968 | 5712 | |
a38bba38 | 5713 | case 0x8c: /* mov seg */ |
cf648174 | 5714 | if (i386_record_modrm (&ir)) |
7ad10968 | 5715 | return -1; |
cf648174 HZ |
5716 | if (ir.reg > 5) |
5717 | { | |
5718 | ir.addr -= 2; | |
5719 | opcode = opcode << 8 | ir.modrm; | |
5720 | goto no_support; | |
5721 | } | |
5722 | ||
5723 | if (ir.mod == 3) | |
25ea693b | 5724 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5725 | else |
5726 | { | |
5727 | ir.ot = OT_WORD; | |
5728 | if (i386_record_lea_modrm (&ir)) | |
5729 | return -1; | |
5730 | } | |
7ad10968 HZ |
5731 | break; |
5732 | ||
a38bba38 | 5733 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5734 | if (i386_record_modrm (&ir)) |
5735 | return -1; | |
7ad10968 HZ |
5736 | switch (ir.reg) |
5737 | { | |
5738 | case 0: | |
425b824a | 5739 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5740 | break; |
5741 | case 2: | |
425b824a | 5742 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5743 | break; |
5744 | case 3: | |
425b824a | 5745 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5746 | break; |
5747 | case 4: | |
425b824a | 5748 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5749 | break; |
5750 | case 5: | |
425b824a | 5751 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5752 | break; |
5753 | default: | |
5754 | ir.addr -= 2; | |
5755 | opcode = opcode << 8 | ir.modrm; | |
5756 | goto no_support; | |
5757 | break; | |
5758 | } | |
25ea693b MM |
5759 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5760 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5761 | break; |
5762 | ||
a38bba38 MS |
5763 | case 0x0fb6: /* movzbS */ |
5764 | case 0x0fb7: /* movzwS */ | |
5765 | case 0x0fbe: /* movsbS */ | |
5766 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5767 | if (i386_record_modrm (&ir)) |
5768 | return -1; | |
25ea693b | 5769 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5770 | break; |
5771 | ||
a38bba38 | 5772 | case 0x8d: /* lea */ |
7ad10968 HZ |
5773 | if (i386_record_modrm (&ir)) |
5774 | return -1; | |
5775 | if (ir.mod == 3) | |
5776 | { | |
5777 | ir.addr -= 2; | |
5778 | opcode = opcode << 8 | ir.modrm; | |
5779 | goto no_support; | |
5780 | } | |
7ad10968 | 5781 | ir.ot = ir.dflag; |
cf648174 HZ |
5782 | ir.reg |= rex_r; |
5783 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5784 | ir.reg &= 0x3; |
25ea693b | 5785 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5786 | break; |
5787 | ||
a38bba38 | 5788 | case 0xa0: /* mov EAX */ |
7ad10968 | 5789 | case 0xa1: |
a38bba38 MS |
5790 | |
5791 | case 0xd7: /* xlat */ | |
25ea693b | 5792 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5793 | break; |
5794 | ||
a38bba38 | 5795 | case 0xa2: /* mov EAX */ |
7ad10968 | 5796 | case 0xa3: |
d7877f7e | 5797 | if (ir.override >= 0) |
cf648174 | 5798 | { |
25ea693b | 5799 | if (record_full_memory_query) |
bb08c432 | 5800 | { |
651ce16a | 5801 | if (yquery (_("\ |
bb08c432 HZ |
5802 | Process record ignores the memory change of instruction at address %s\n\ |
5803 | because it can't get the value of the segment register.\n\ | |
5804 | Do you want to stop the program?"), | |
651ce16a | 5805 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
5806 | return -1; |
5807 | } | |
cf648174 HZ |
5808 | } |
5809 | else | |
5810 | { | |
5811 | if ((opcode & 1) == 0) | |
5812 | ir.ot = OT_BYTE; | |
5813 | else | |
5814 | ir.ot = ir.dflag + OT_WORD; | |
5815 | if (ir.aflag == 2) | |
5816 | { | |
4ffa4fc7 PA |
5817 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
5818 | return -1; | |
cf648174 | 5819 | ir.addr += 8; |
60a1502a | 5820 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 HZ |
5821 | } |
5822 | else if (ir.aflag) | |
5823 | { | |
4ffa4fc7 PA |
5824 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
5825 | return -1; | |
cf648174 | 5826 | ir.addr += 4; |
60a1502a | 5827 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 HZ |
5828 | } |
5829 | else | |
5830 | { | |
4ffa4fc7 PA |
5831 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
5832 | return -1; | |
cf648174 | 5833 | ir.addr += 2; |
60a1502a | 5834 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5835 | } |
25ea693b | 5836 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 HZ |
5837 | return -1; |
5838 | } | |
7ad10968 HZ |
5839 | break; |
5840 | ||
a38bba38 | 5841 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5842 | case 0xb1: |
5843 | case 0xb2: | |
5844 | case 0xb3: | |
5845 | case 0xb4: | |
5846 | case 0xb5: | |
5847 | case 0xb6: | |
5848 | case 0xb7: | |
25ea693b MM |
5849 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5850 | ? ((opcode & 0x7) | ir.rex_b) | |
5851 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5852 | break; |
5853 | ||
a38bba38 | 5854 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5855 | case 0xb9: |
5856 | case 0xba: | |
5857 | case 0xbb: | |
5858 | case 0xbc: | |
5859 | case 0xbd: | |
5860 | case 0xbe: | |
5861 | case 0xbf: | |
25ea693b | 5862 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5863 | break; |
5864 | ||
a38bba38 | 5865 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5866 | case 0x92: |
5867 | case 0x93: | |
5868 | case 0x94: | |
5869 | case 0x95: | |
5870 | case 0x96: | |
5871 | case 0x97: | |
25ea693b MM |
5872 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5873 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5874 | break; |
5875 | ||
a38bba38 | 5876 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5877 | case 0x87: |
5878 | if ((opcode & 1) == 0) | |
5879 | ir.ot = OT_BYTE; | |
5880 | else | |
5881 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5882 | if (i386_record_modrm (&ir)) |
5883 | return -1; | |
7ad10968 HZ |
5884 | if (ir.mod == 3) |
5885 | { | |
86839d38 | 5886 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5887 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5888 | ir.rm &= 0x3; | |
25ea693b | 5889 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5890 | } |
5891 | else | |
5892 | { | |
5893 | if (i386_record_lea_modrm (&ir)) | |
5894 | return -1; | |
5895 | } | |
cf648174 HZ |
5896 | ir.reg |= rex_r; |
5897 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5898 | ir.reg &= 0x3; |
25ea693b | 5899 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5900 | break; |
5901 | ||
a38bba38 MS |
5902 | case 0xc4: /* les Gv */ |
5903 | case 0xc5: /* lds Gv */ | |
cf648174 HZ |
5904 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5905 | { | |
5906 | ir.addr -= 1; | |
5907 | goto no_support; | |
5908 | } | |
d3f323f3 | 5909 | /* FALLTHROUGH */ |
a38bba38 MS |
5910 | case 0x0fb2: /* lss Gv */ |
5911 | case 0x0fb4: /* lfs Gv */ | |
5912 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5913 | if (i386_record_modrm (&ir)) |
5914 | return -1; | |
5915 | if (ir.mod == 3) | |
5916 | { | |
5917 | if (opcode > 0xff) | |
5918 | ir.addr -= 3; | |
5919 | else | |
5920 | ir.addr -= 2; | |
5921 | opcode = opcode << 8 | ir.modrm; | |
5922 | goto no_support; | |
5923 | } | |
7ad10968 HZ |
5924 | switch (opcode) |
5925 | { | |
a38bba38 | 5926 | case 0xc4: /* les Gv */ |
425b824a | 5927 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5928 | break; |
a38bba38 | 5929 | case 0xc5: /* lds Gv */ |
425b824a | 5930 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5931 | break; |
a38bba38 | 5932 | case 0x0fb2: /* lss Gv */ |
425b824a | 5933 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5934 | break; |
a38bba38 | 5935 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5936 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5937 | break; |
a38bba38 | 5938 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5939 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5940 | break; |
5941 | } | |
25ea693b MM |
5942 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5943 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
5944 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5945 | break; |
5946 | ||
a38bba38 | 5947 | case 0xc0: /* shifts */ |
7ad10968 HZ |
5948 | case 0xc1: |
5949 | case 0xd0: | |
5950 | case 0xd1: | |
5951 | case 0xd2: | |
5952 | case 0xd3: | |
5953 | if ((opcode & 1) == 0) | |
5954 | ir.ot = OT_BYTE; | |
5955 | else | |
5956 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5957 | if (i386_record_modrm (&ir)) |
5958 | return -1; | |
7ad10968 HZ |
5959 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
5960 | { | |
5961 | if (i386_record_lea_modrm (&ir)) | |
5962 | return -1; | |
5963 | } | |
5964 | else | |
5965 | { | |
cf648174 HZ |
5966 | ir.rm |= ir.rex_b; |
5967 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5968 | ir.rm &= 0x3; |
25ea693b | 5969 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5970 | } |
25ea693b | 5971 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5972 | break; |
5973 | ||
5974 | case 0x0fa4: | |
5975 | case 0x0fa5: | |
5976 | case 0x0fac: | |
5977 | case 0x0fad: | |
5978 | if (i386_record_modrm (&ir)) | |
5979 | return -1; | |
5980 | if (ir.mod == 3) | |
5981 | { | |
25ea693b | 5982 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
5983 | return -1; |
5984 | } | |
5985 | else | |
5986 | { | |
5987 | if (i386_record_lea_modrm (&ir)) | |
5988 | return -1; | |
5989 | } | |
5990 | break; | |
5991 | ||
a38bba38 | 5992 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
5993 | case 0xd9: |
5994 | case 0xda: | |
5995 | case 0xdb: | |
5996 | case 0xdc: | |
5997 | case 0xdd: | |
5998 | case 0xde: | |
5999 | case 0xdf: | |
6000 | if (i386_record_modrm (&ir)) | |
6001 | return -1; | |
6002 | ir.reg |= ((opcode & 7) << 3); | |
6003 | if (ir.mod != 3) | |
6004 | { | |
1777feb0 | 6005 | /* Memory. */ |
955db0c0 | 6006 | uint64_t addr64; |
7ad10968 | 6007 | |
955db0c0 | 6008 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6009 | return -1; |
6010 | switch (ir.reg) | |
6011 | { | |
7ad10968 | 6012 | case 0x02: |
0289bdd7 MS |
6013 | case 0x12: |
6014 | case 0x22: | |
6015 | case 0x32: | |
6016 | /* For fcom, ficom nothing to do. */ | |
6017 | break; | |
7ad10968 | 6018 | case 0x03: |
0289bdd7 MS |
6019 | case 0x13: |
6020 | case 0x23: | |
6021 | case 0x33: | |
6022 | /* For fcomp, ficomp pop FPU stack, store all. */ | |
6023 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6024 | return -1; | |
6025 | break; | |
6026 | case 0x00: | |
6027 | case 0x01: | |
7ad10968 HZ |
6028 | case 0x04: |
6029 | case 0x05: | |
6030 | case 0x06: | |
6031 | case 0x07: | |
6032 | case 0x10: | |
6033 | case 0x11: | |
7ad10968 HZ |
6034 | case 0x14: |
6035 | case 0x15: | |
6036 | case 0x16: | |
6037 | case 0x17: | |
6038 | case 0x20: | |
6039 | case 0x21: | |
7ad10968 HZ |
6040 | case 0x24: |
6041 | case 0x25: | |
6042 | case 0x26: | |
6043 | case 0x27: | |
6044 | case 0x30: | |
6045 | case 0x31: | |
7ad10968 HZ |
6046 | case 0x34: |
6047 | case 0x35: | |
6048 | case 0x36: | |
6049 | case 0x37: | |
0289bdd7 MS |
6050 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6051 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6052 | of code, always affects st(0) register. */ | |
6053 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6054 | return -1; | |
7ad10968 HZ |
6055 | break; |
6056 | case 0x08: | |
6057 | case 0x0a: | |
6058 | case 0x0b: | |
6059 | case 0x18: | |
6060 | case 0x19: | |
6061 | case 0x1a: | |
6062 | case 0x1b: | |
0289bdd7 | 6063 | case 0x1d: |
7ad10968 HZ |
6064 | case 0x28: |
6065 | case 0x29: | |
6066 | case 0x2a: | |
6067 | case 0x2b: | |
6068 | case 0x38: | |
6069 | case 0x39: | |
6070 | case 0x3a: | |
6071 | case 0x3b: | |
0289bdd7 MS |
6072 | case 0x3c: |
6073 | case 0x3d: | |
7ad10968 HZ |
6074 | switch (ir.reg & 7) |
6075 | { | |
6076 | case 0: | |
0289bdd7 MS |
6077 | /* Handling fld, fild. */ |
6078 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6079 | return -1; | |
7ad10968 HZ |
6080 | break; |
6081 | case 1: | |
6082 | switch (ir.reg >> 4) | |
6083 | { | |
6084 | case 0: | |
25ea693b | 6085 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6086 | return -1; |
6087 | break; | |
6088 | case 2: | |
25ea693b | 6089 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6090 | return -1; |
6091 | break; | |
6092 | case 3: | |
0289bdd7 | 6093 | break; |
7ad10968 | 6094 | default: |
25ea693b | 6095 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6096 | return -1; |
6097 | break; | |
6098 | } | |
6099 | break; | |
6100 | default: | |
6101 | switch (ir.reg >> 4) | |
6102 | { | |
6103 | case 0: | |
25ea693b | 6104 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6105 | return -1; |
6106 | if (3 == (ir.reg & 7)) | |
6107 | { | |
6108 | /* For fstp m32fp. */ | |
6109 | if (i386_record_floats (gdbarch, &ir, | |
6110 | I386_SAVE_FPU_REGS)) | |
6111 | return -1; | |
6112 | } | |
6113 | break; | |
7ad10968 | 6114 | case 1: |
25ea693b | 6115 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6116 | return -1; |
0289bdd7 MS |
6117 | if ((3 == (ir.reg & 7)) |
6118 | || (5 == (ir.reg & 7)) | |
6119 | || (7 == (ir.reg & 7))) | |
6120 | { | |
6121 | /* For fstp insn. */ | |
6122 | if (i386_record_floats (gdbarch, &ir, | |
6123 | I386_SAVE_FPU_REGS)) | |
6124 | return -1; | |
6125 | } | |
7ad10968 HZ |
6126 | break; |
6127 | case 2: | |
25ea693b | 6128 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6129 | return -1; |
0289bdd7 MS |
6130 | if (3 == (ir.reg & 7)) |
6131 | { | |
6132 | /* For fstp m64fp. */ | |
6133 | if (i386_record_floats (gdbarch, &ir, | |
6134 | I386_SAVE_FPU_REGS)) | |
6135 | return -1; | |
6136 | } | |
7ad10968 HZ |
6137 | break; |
6138 | case 3: | |
0289bdd7 MS |
6139 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6140 | { | |
6141 | /* For fistp, fbld, fild, fbstp. */ | |
6142 | if (i386_record_floats (gdbarch, &ir, | |
6143 | I386_SAVE_FPU_REGS)) | |
6144 | return -1; | |
6145 | } | |
6146 | /* Fall through */ | |
7ad10968 | 6147 | default: |
25ea693b | 6148 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6149 | return -1; |
6150 | break; | |
6151 | } | |
6152 | break; | |
6153 | } | |
6154 | break; | |
6155 | case 0x0c: | |
0289bdd7 MS |
6156 | /* Insn fldenv. */ |
6157 | if (i386_record_floats (gdbarch, &ir, | |
6158 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6159 | return -1; | |
6160 | break; | |
7ad10968 | 6161 | case 0x0d: |
0289bdd7 MS |
6162 | /* Insn fldcw. */ |
6163 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6164 | return -1; | |
6165 | break; | |
7ad10968 | 6166 | case 0x2c: |
0289bdd7 MS |
6167 | /* Insn frstor. */ |
6168 | if (i386_record_floats (gdbarch, &ir, | |
6169 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6170 | return -1; | |
7ad10968 HZ |
6171 | break; |
6172 | case 0x0e: | |
6173 | if (ir.dflag) | |
6174 | { | |
25ea693b | 6175 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6176 | return -1; |
6177 | } | |
6178 | else | |
6179 | { | |
25ea693b | 6180 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6181 | return -1; |
6182 | } | |
6183 | break; | |
6184 | case 0x0f: | |
6185 | case 0x2f: | |
25ea693b | 6186 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6187 | return -1; |
0289bdd7 MS |
6188 | /* Insn fstp, fbstp. */ |
6189 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6190 | return -1; | |
7ad10968 HZ |
6191 | break; |
6192 | case 0x1f: | |
6193 | case 0x3e: | |
25ea693b | 6194 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6195 | return -1; |
6196 | break; | |
6197 | case 0x2e: | |
6198 | if (ir.dflag) | |
6199 | { | |
25ea693b | 6200 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6201 | return -1; |
955db0c0 | 6202 | addr64 += 28; |
7ad10968 HZ |
6203 | } |
6204 | else | |
6205 | { | |
25ea693b | 6206 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6207 | return -1; |
955db0c0 | 6208 | addr64 += 14; |
7ad10968 | 6209 | } |
25ea693b | 6210 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6211 | return -1; |
0289bdd7 MS |
6212 | /* Insn fsave. */ |
6213 | if (i386_record_floats (gdbarch, &ir, | |
6214 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6215 | return -1; | |
7ad10968 HZ |
6216 | break; |
6217 | case 0x3f: | |
25ea693b | 6218 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6219 | return -1; |
0289bdd7 MS |
6220 | /* Insn fistp. */ |
6221 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6222 | return -1; | |
7ad10968 HZ |
6223 | break; |
6224 | default: | |
6225 | ir.addr -= 2; | |
6226 | opcode = opcode << 8 | ir.modrm; | |
6227 | goto no_support; | |
6228 | break; | |
6229 | } | |
6230 | } | |
0289bdd7 MS |
6231 | /* Opcode is an extension of modR/M byte. */ |
6232 | else | |
6233 | { | |
6234 | switch (opcode) | |
6235 | { | |
6236 | case 0xd8: | |
6237 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6238 | return -1; | |
6239 | break; | |
6240 | case 0xd9: | |
6241 | if (0x0c == (ir.modrm >> 4)) | |
6242 | { | |
6243 | if ((ir.modrm & 0x0f) <= 7) | |
6244 | { | |
6245 | if (i386_record_floats (gdbarch, &ir, | |
6246 | I386_SAVE_FPU_REGS)) | |
6247 | return -1; | |
6248 | } | |
6249 | else | |
6250 | { | |
6251 | if (i386_record_floats (gdbarch, &ir, | |
6252 | I387_ST0_REGNUM (tdep))) | |
6253 | return -1; | |
6254 | /* If only st(0) is changing, then we have already | |
6255 | recorded. */ | |
6256 | if ((ir.modrm & 0x0f) - 0x08) | |
6257 | { | |
6258 | if (i386_record_floats (gdbarch, &ir, | |
6259 | I387_ST0_REGNUM (tdep) + | |
6260 | ((ir.modrm & 0x0f) - 0x08))) | |
6261 | return -1; | |
6262 | } | |
6263 | } | |
6264 | } | |
6265 | else | |
6266 | { | |
6267 | switch (ir.modrm) | |
6268 | { | |
6269 | case 0xe0: | |
6270 | case 0xe1: | |
6271 | case 0xf0: | |
6272 | case 0xf5: | |
6273 | case 0xf8: | |
6274 | case 0xfa: | |
6275 | case 0xfc: | |
6276 | case 0xfe: | |
6277 | case 0xff: | |
6278 | if (i386_record_floats (gdbarch, &ir, | |
6279 | I387_ST0_REGNUM (tdep))) | |
6280 | return -1; | |
6281 | break; | |
6282 | case 0xf1: | |
6283 | case 0xf2: | |
6284 | case 0xf3: | |
6285 | case 0xf4: | |
6286 | case 0xf6: | |
6287 | case 0xf7: | |
6288 | case 0xe8: | |
6289 | case 0xe9: | |
6290 | case 0xea: | |
6291 | case 0xeb: | |
6292 | case 0xec: | |
6293 | case 0xed: | |
6294 | case 0xee: | |
6295 | case 0xf9: | |
6296 | case 0xfb: | |
6297 | if (i386_record_floats (gdbarch, &ir, | |
6298 | I386_SAVE_FPU_REGS)) | |
6299 | return -1; | |
6300 | break; | |
6301 | case 0xfd: | |
6302 | if (i386_record_floats (gdbarch, &ir, | |
6303 | I387_ST0_REGNUM (tdep))) | |
6304 | return -1; | |
6305 | if (i386_record_floats (gdbarch, &ir, | |
6306 | I387_ST0_REGNUM (tdep) + 1)) | |
6307 | return -1; | |
6308 | break; | |
6309 | } | |
6310 | } | |
6311 | break; | |
6312 | case 0xda: | |
6313 | if (0xe9 == ir.modrm) | |
6314 | { | |
6315 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6316 | return -1; | |
6317 | } | |
6318 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6319 | { | |
6320 | if (i386_record_floats (gdbarch, &ir, | |
6321 | I387_ST0_REGNUM (tdep))) | |
6322 | return -1; | |
6323 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6324 | { | |
6325 | if (i386_record_floats (gdbarch, &ir, | |
6326 | I387_ST0_REGNUM (tdep) + | |
6327 | (ir.modrm & 0x0f))) | |
6328 | return -1; | |
6329 | } | |
6330 | else if ((ir.modrm & 0x0f) - 0x08) | |
6331 | { | |
6332 | if (i386_record_floats (gdbarch, &ir, | |
6333 | I387_ST0_REGNUM (tdep) + | |
6334 | ((ir.modrm & 0x0f) - 0x08))) | |
6335 | return -1; | |
6336 | } | |
6337 | } | |
6338 | break; | |
6339 | case 0xdb: | |
6340 | if (0xe3 == ir.modrm) | |
6341 | { | |
6342 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) | |
6343 | return -1; | |
6344 | } | |
6345 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6346 | { | |
6347 | if (i386_record_floats (gdbarch, &ir, | |
6348 | I387_ST0_REGNUM (tdep))) | |
6349 | return -1; | |
6350 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6351 | { | |
6352 | if (i386_record_floats (gdbarch, &ir, | |
6353 | I387_ST0_REGNUM (tdep) + | |
6354 | (ir.modrm & 0x0f))) | |
6355 | return -1; | |
6356 | } | |
6357 | else if ((ir.modrm & 0x0f) - 0x08) | |
6358 | { | |
6359 | if (i386_record_floats (gdbarch, &ir, | |
6360 | I387_ST0_REGNUM (tdep) + | |
6361 | ((ir.modrm & 0x0f) - 0x08))) | |
6362 | return -1; | |
6363 | } | |
6364 | } | |
6365 | break; | |
6366 | case 0xdc: | |
6367 | if ((0x0c == ir.modrm >> 4) | |
6368 | || (0x0d == ir.modrm >> 4) | |
6369 | || (0x0f == ir.modrm >> 4)) | |
6370 | { | |
6371 | if ((ir.modrm & 0x0f) <= 7) | |
6372 | { | |
6373 | if (i386_record_floats (gdbarch, &ir, | |
6374 | I387_ST0_REGNUM (tdep) + | |
6375 | (ir.modrm & 0x0f))) | |
6376 | return -1; | |
6377 | } | |
6378 | else | |
6379 | { | |
6380 | if (i386_record_floats (gdbarch, &ir, | |
6381 | I387_ST0_REGNUM (tdep) + | |
6382 | ((ir.modrm & 0x0f) - 0x08))) | |
6383 | return -1; | |
6384 | } | |
6385 | } | |
6386 | break; | |
6387 | case 0xdd: | |
6388 | if (0x0c == ir.modrm >> 4) | |
6389 | { | |
6390 | if (i386_record_floats (gdbarch, &ir, | |
6391 | I387_FTAG_REGNUM (tdep))) | |
6392 | return -1; | |
6393 | } | |
6394 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6395 | { | |
6396 | if ((ir.modrm & 0x0f) <= 7) | |
6397 | { | |
6398 | if (i386_record_floats (gdbarch, &ir, | |
6399 | I387_ST0_REGNUM (tdep) + | |
6400 | (ir.modrm & 0x0f))) | |
6401 | return -1; | |
6402 | } | |
6403 | else | |
6404 | { | |
6405 | if (i386_record_floats (gdbarch, &ir, | |
6406 | I386_SAVE_FPU_REGS)) | |
6407 | return -1; | |
6408 | } | |
6409 | } | |
6410 | break; | |
6411 | case 0xde: | |
6412 | if ((0x0c == ir.modrm >> 4) | |
6413 | || (0x0e == ir.modrm >> 4) | |
6414 | || (0x0f == ir.modrm >> 4) | |
6415 | || (0xd9 == ir.modrm)) | |
6416 | { | |
6417 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6418 | return -1; | |
6419 | } | |
6420 | break; | |
6421 | case 0xdf: | |
6422 | if (0xe0 == ir.modrm) | |
6423 | { | |
25ea693b MM |
6424 | if (record_full_arch_list_add_reg (ir.regcache, |
6425 | I386_EAX_REGNUM)) | |
0289bdd7 MS |
6426 | return -1; |
6427 | } | |
6428 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6429 | { | |
6430 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6431 | return -1; | |
6432 | } | |
6433 | break; | |
6434 | } | |
6435 | } | |
7ad10968 | 6436 | break; |
7ad10968 | 6437 | /* string ops */ |
a38bba38 | 6438 | case 0xa4: /* movsS */ |
7ad10968 | 6439 | case 0xa5: |
a38bba38 | 6440 | case 0xaa: /* stosS */ |
7ad10968 | 6441 | case 0xab: |
a38bba38 | 6442 | case 0x6c: /* insS */ |
7ad10968 | 6443 | case 0x6d: |
cf648174 | 6444 | regcache_raw_read_unsigned (ir.regcache, |
77d7dc92 | 6445 | ir.regmap[X86_RECORD_RECX_REGNUM], |
648d0c8b MS |
6446 | &addr); |
6447 | if (addr) | |
cf648174 | 6448 | { |
77d7dc92 HZ |
6449 | ULONGEST es, ds; |
6450 | ||
6451 | if ((opcode & 1) == 0) | |
6452 | ir.ot = OT_BYTE; | |
6453 | else | |
6454 | ir.ot = ir.dflag + OT_WORD; | |
cf648174 HZ |
6455 | regcache_raw_read_unsigned (ir.regcache, |
6456 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
648d0c8b | 6457 | &addr); |
77d7dc92 | 6458 | |
d7877f7e HZ |
6459 | regcache_raw_read_unsigned (ir.regcache, |
6460 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6461 | &es); | |
6462 | regcache_raw_read_unsigned (ir.regcache, | |
6463 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6464 | &ds); | |
6465 | if (ir.aflag && (es != ds)) | |
77d7dc92 HZ |
6466 | { |
6467 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
25ea693b | 6468 | if (record_full_memory_query) |
bb08c432 | 6469 | { |
651ce16a | 6470 | if (yquery (_("\ |
bb08c432 HZ |
6471 | Process record ignores the memory change of instruction at address %s\n\ |
6472 | because it can't get the value of the segment register.\n\ | |
6473 | Do you want to stop the program?"), | |
651ce16a | 6474 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
6475 | return -1; |
6476 | } | |
df61f520 HZ |
6477 | } |
6478 | else | |
6479 | { | |
25ea693b | 6480 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
df61f520 | 6481 | return -1; |
77d7dc92 HZ |
6482 | } |
6483 | ||
6484 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
25ea693b | 6485 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
77d7dc92 | 6486 | if (opcode == 0xa4 || opcode == 0xa5) |
25ea693b MM |
6487 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
6488 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6489 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6490 | } |
cf648174 | 6491 | break; |
7ad10968 | 6492 | |
a38bba38 | 6493 | case 0xa6: /* cmpsS */ |
cf648174 | 6494 | case 0xa7: |
25ea693b MM |
6495 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6496 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6497 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6498 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6499 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6500 | break; |
6501 | ||
a38bba38 | 6502 | case 0xac: /* lodsS */ |
7ad10968 | 6503 | case 0xad: |
25ea693b MM |
6504 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6505 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6506 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6507 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6508 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6509 | break; |
6510 | ||
a38bba38 | 6511 | case 0xae: /* scasS */ |
7ad10968 | 6512 | case 0xaf: |
25ea693b | 6513 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6514 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6515 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6516 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6517 | break; |
6518 | ||
a38bba38 | 6519 | case 0x6e: /* outsS */ |
cf648174 | 6520 | case 0x6f: |
25ea693b | 6521 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6522 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
25ea693b MM |
6523 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6524 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6525 | break; |
6526 | ||
a38bba38 | 6527 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6528 | case 0xe5: |
6529 | case 0xec: | |
6530 | case 0xed: | |
25ea693b MM |
6531 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6532 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6533 | break; |
6534 | ||
6535 | case 0xe6: | |
6536 | case 0xe7: | |
6537 | case 0xee: | |
6538 | case 0xef: | |
6539 | break; | |
6540 | ||
6541 | /* control */ | |
a38bba38 MS |
6542 | case 0xc2: /* ret im */ |
6543 | case 0xc3: /* ret */ | |
25ea693b MM |
6544 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6546 | break; |
6547 | ||
a38bba38 MS |
6548 | case 0xca: /* lret im */ |
6549 | case 0xcb: /* lret */ | |
6550 | case 0xcf: /* iret */ | |
25ea693b MM |
6551 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6552 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6554 | break; |
6555 | ||
a38bba38 | 6556 | case 0xe8: /* call im */ |
cf648174 HZ |
6557 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6558 | ir.dflag = 2; | |
6559 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6560 | return -1; | |
7ad10968 HZ |
6561 | break; |
6562 | ||
a38bba38 | 6563 | case 0x9a: /* lcall im */ |
cf648174 HZ |
6564 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6565 | { | |
6566 | ir.addr -= 1; | |
6567 | goto no_support; | |
6568 | } | |
25ea693b | 6569 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 HZ |
6570 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
6571 | return -1; | |
7ad10968 HZ |
6572 | break; |
6573 | ||
a38bba38 MS |
6574 | case 0xe9: /* jmp im */ |
6575 | case 0xea: /* ljmp im */ | |
6576 | case 0xeb: /* jmp Jb */ | |
6577 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6578 | case 0x71: |
6579 | case 0x72: | |
6580 | case 0x73: | |
6581 | case 0x74: | |
6582 | case 0x75: | |
6583 | case 0x76: | |
6584 | case 0x77: | |
6585 | case 0x78: | |
6586 | case 0x79: | |
6587 | case 0x7a: | |
6588 | case 0x7b: | |
6589 | case 0x7c: | |
6590 | case 0x7d: | |
6591 | case 0x7e: | |
6592 | case 0x7f: | |
a38bba38 | 6593 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6594 | case 0x0f81: |
6595 | case 0x0f82: | |
6596 | case 0x0f83: | |
6597 | case 0x0f84: | |
6598 | case 0x0f85: | |
6599 | case 0x0f86: | |
6600 | case 0x0f87: | |
6601 | case 0x0f88: | |
6602 | case 0x0f89: | |
6603 | case 0x0f8a: | |
6604 | case 0x0f8b: | |
6605 | case 0x0f8c: | |
6606 | case 0x0f8d: | |
6607 | case 0x0f8e: | |
6608 | case 0x0f8f: | |
6609 | break; | |
6610 | ||
a38bba38 | 6611 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6612 | case 0x0f91: |
6613 | case 0x0f92: | |
6614 | case 0x0f93: | |
6615 | case 0x0f94: | |
6616 | case 0x0f95: | |
6617 | case 0x0f96: | |
6618 | case 0x0f97: | |
6619 | case 0x0f98: | |
6620 | case 0x0f99: | |
6621 | case 0x0f9a: | |
6622 | case 0x0f9b: | |
6623 | case 0x0f9c: | |
6624 | case 0x0f9d: | |
6625 | case 0x0f9e: | |
6626 | case 0x0f9f: | |
25ea693b | 6627 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6628 | ir.ot = OT_BYTE; |
6629 | if (i386_record_modrm (&ir)) | |
6630 | return -1; | |
6631 | if (ir.mod == 3) | |
25ea693b MM |
6632 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
6633 | : (ir.rm & 0x3)); | |
7ad10968 HZ |
6634 | else |
6635 | { | |
6636 | if (i386_record_lea_modrm (&ir)) | |
6637 | return -1; | |
6638 | } | |
6639 | break; | |
6640 | ||
a38bba38 | 6641 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6642 | case 0x0f41: |
6643 | case 0x0f42: | |
6644 | case 0x0f43: | |
6645 | case 0x0f44: | |
6646 | case 0x0f45: | |
6647 | case 0x0f46: | |
6648 | case 0x0f47: | |
6649 | case 0x0f48: | |
6650 | case 0x0f49: | |
6651 | case 0x0f4a: | |
6652 | case 0x0f4b: | |
6653 | case 0x0f4c: | |
6654 | case 0x0f4d: | |
6655 | case 0x0f4e: | |
6656 | case 0x0f4f: | |
6657 | if (i386_record_modrm (&ir)) | |
6658 | return -1; | |
cf648174 | 6659 | ir.reg |= rex_r; |
7ad10968 HZ |
6660 | if (ir.dflag == OT_BYTE) |
6661 | ir.reg &= 0x3; | |
25ea693b | 6662 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6663 | break; |
6664 | ||
6665 | /* flags */ | |
a38bba38 | 6666 | case 0x9c: /* pushf */ |
25ea693b | 6667 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6668 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
6669 | ir.dflag = 2; | |
6670 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
6671 | return -1; | |
7ad10968 HZ |
6672 | break; |
6673 | ||
a38bba38 | 6674 | case 0x9d: /* popf */ |
25ea693b MM |
6675 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6676 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6677 | break; |
6678 | ||
a38bba38 | 6679 | case 0x9e: /* sahf */ |
cf648174 HZ |
6680 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6681 | { | |
6682 | ir.addr -= 1; | |
6683 | goto no_support; | |
6684 | } | |
d3f323f3 | 6685 | /* FALLTHROUGH */ |
a38bba38 MS |
6686 | case 0xf5: /* cmc */ |
6687 | case 0xf8: /* clc */ | |
6688 | case 0xf9: /* stc */ | |
6689 | case 0xfc: /* cld */ | |
6690 | case 0xfd: /* std */ | |
25ea693b | 6691 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6692 | break; |
6693 | ||
a38bba38 | 6694 | case 0x9f: /* lahf */ |
cf648174 HZ |
6695 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6696 | { | |
6697 | ir.addr -= 1; | |
6698 | goto no_support; | |
6699 | } | |
25ea693b MM |
6700 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6701 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6702 | break; |
6703 | ||
6704 | /* bit operations */ | |
a38bba38 | 6705 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6706 | ir.ot = ir.dflag + OT_WORD; |
6707 | if (i386_record_modrm (&ir)) | |
6708 | return -1; | |
6709 | if (ir.reg < 4) | |
6710 | { | |
cf648174 | 6711 | ir.addr -= 2; |
7ad10968 HZ |
6712 | opcode = opcode << 8 | ir.modrm; |
6713 | goto no_support; | |
6714 | } | |
cf648174 | 6715 | if (ir.reg != 4) |
7ad10968 | 6716 | { |
cf648174 | 6717 | if (ir.mod == 3) |
25ea693b | 6718 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6719 | else |
6720 | { | |
cf648174 | 6721 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6722 | return -1; |
6723 | } | |
6724 | } | |
25ea693b | 6725 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6726 | break; |
6727 | ||
a38bba38 | 6728 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6729 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6730 | break; |
6731 | ||
a38bba38 MS |
6732 | case 0x0fab: /* bts */ |
6733 | case 0x0fb3: /* btr */ | |
6734 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6735 | ir.ot = ir.dflag + OT_WORD; |
6736 | if (i386_record_modrm (&ir)) | |
6737 | return -1; | |
6738 | if (ir.mod == 3) | |
25ea693b | 6739 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 HZ |
6740 | else |
6741 | { | |
955db0c0 MS |
6742 | uint64_t addr64; |
6743 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
cf648174 HZ |
6744 | return -1; |
6745 | regcache_raw_read_unsigned (ir.regcache, | |
6746 | ir.regmap[ir.reg | rex_r], | |
648d0c8b | 6747 | &addr); |
cf648174 HZ |
6748 | switch (ir.dflag) |
6749 | { | |
6750 | case 0: | |
648d0c8b | 6751 | addr64 += ((int16_t) addr >> 4) << 4; |
cf648174 HZ |
6752 | break; |
6753 | case 1: | |
648d0c8b | 6754 | addr64 += ((int32_t) addr >> 5) << 5; |
cf648174 HZ |
6755 | break; |
6756 | case 2: | |
648d0c8b | 6757 | addr64 += ((int64_t) addr >> 6) << 6; |
cf648174 HZ |
6758 | break; |
6759 | } | |
25ea693b | 6760 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) |
cf648174 HZ |
6761 | return -1; |
6762 | if (i386_record_lea_modrm (&ir)) | |
6763 | return -1; | |
6764 | } | |
25ea693b | 6765 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6766 | break; |
6767 | ||
a38bba38 MS |
6768 | case 0x0fbc: /* bsf */ |
6769 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6770 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6771 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6772 | break; |
6773 | ||
6774 | /* bcd */ | |
a38bba38 MS |
6775 | case 0x27: /* daa */ |
6776 | case 0x2f: /* das */ | |
6777 | case 0x37: /* aaa */ | |
6778 | case 0x3f: /* aas */ | |
6779 | case 0xd4: /* aam */ | |
6780 | case 0xd5: /* aad */ | |
cf648174 HZ |
6781 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6782 | { | |
6783 | ir.addr -= 1; | |
6784 | goto no_support; | |
6785 | } | |
25ea693b MM |
6786 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6787 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6788 | break; |
6789 | ||
6790 | /* misc */ | |
a38bba38 | 6791 | case 0x90: /* nop */ |
7ad10968 HZ |
6792 | if (prefixes & PREFIX_LOCK) |
6793 | { | |
6794 | ir.addr -= 1; | |
6795 | goto no_support; | |
6796 | } | |
6797 | break; | |
6798 | ||
a38bba38 | 6799 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6800 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6801 | return -1; | |
425b824a | 6802 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6803 | ir.addr++; |
6804 | goto reswitch; | |
7ad10968 HZ |
6805 | break; |
6806 | ||
7ad10968 | 6807 | /* XXX */ |
a38bba38 | 6808 | case 0xcc: /* int3 */ |
a3c4230a | 6809 | printf_unfiltered (_("Process record does not support instruction " |
7ad10968 HZ |
6810 | "int3.\n")); |
6811 | ir.addr -= 1; | |
6812 | goto no_support; | |
6813 | break; | |
6814 | ||
7ad10968 | 6815 | /* XXX */ |
a38bba38 | 6816 | case 0xcd: /* int */ |
7ad10968 HZ |
6817 | { |
6818 | int ret; | |
425b824a | 6819 | uint8_t interrupt; |
4ffa4fc7 PA |
6820 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6821 | return -1; | |
7ad10968 | 6822 | ir.addr++; |
425b824a | 6823 | if (interrupt != 0x80 |
a3c4230a | 6824 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6825 | { |
a3c4230a | 6826 | printf_unfiltered (_("Process record does not support " |
7ad10968 | 6827 | "instruction int 0x%02x.\n"), |
425b824a | 6828 | interrupt); |
7ad10968 HZ |
6829 | ir.addr -= 2; |
6830 | goto no_support; | |
6831 | } | |
a3c4230a | 6832 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6833 | if (ret) |
6834 | return ret; | |
6835 | } | |
6836 | break; | |
6837 | ||
7ad10968 | 6838 | /* XXX */ |
a38bba38 | 6839 | case 0xce: /* into */ |
a3c4230a | 6840 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6841 | "instruction into.\n")); |
6842 | ir.addr -= 1; | |
6843 | goto no_support; | |
6844 | break; | |
6845 | ||
a38bba38 MS |
6846 | case 0xfa: /* cli */ |
6847 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6848 | break; |
6849 | ||
a38bba38 | 6850 | case 0x62: /* bound */ |
a3c4230a | 6851 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6852 | "instruction bound.\n")); |
6853 | ir.addr -= 1; | |
6854 | goto no_support; | |
6855 | break; | |
6856 | ||
a38bba38 | 6857 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6858 | case 0x0fc9: |
6859 | case 0x0fca: | |
6860 | case 0x0fcb: | |
6861 | case 0x0fcc: | |
6862 | case 0x0fcd: | |
6863 | case 0x0fce: | |
6864 | case 0x0fcf: | |
25ea693b | 6865 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6866 | break; |
6867 | ||
a38bba38 | 6868 | case 0xd6: /* salc */ |
cf648174 HZ |
6869 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6870 | { | |
6871 | ir.addr -= 1; | |
6872 | goto no_support; | |
6873 | } | |
25ea693b MM |
6874 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6875 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6876 | break; |
6877 | ||
a38bba38 MS |
6878 | case 0xe0: /* loopnz */ |
6879 | case 0xe1: /* loopz */ | |
6880 | case 0xe2: /* loop */ | |
6881 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6882 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6883 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6884 | break; |
6885 | ||
a38bba38 | 6886 | case 0x0f30: /* wrmsr */ |
a3c4230a | 6887 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6888 | "instruction wrmsr.\n")); |
6889 | ir.addr -= 2; | |
6890 | goto no_support; | |
6891 | break; | |
6892 | ||
a38bba38 | 6893 | case 0x0f32: /* rdmsr */ |
a3c4230a | 6894 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6895 | "instruction rdmsr.\n")); |
6896 | ir.addr -= 2; | |
6897 | goto no_support; | |
6898 | break; | |
6899 | ||
a38bba38 | 6900 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6901 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6902 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6903 | break; |
6904 | ||
a38bba38 | 6905 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6906 | { |
6907 | int ret; | |
cf648174 HZ |
6908 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6909 | { | |
6910 | ir.addr -= 2; | |
6911 | goto no_support; | |
6912 | } | |
a3c4230a | 6913 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6914 | { |
a3c4230a | 6915 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6916 | "instruction sysenter.\n")); |
6917 | ir.addr -= 2; | |
6918 | goto no_support; | |
6919 | } | |
a3c4230a | 6920 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6921 | if (ret) |
6922 | return ret; | |
6923 | } | |
6924 | break; | |
6925 | ||
a38bba38 | 6926 | case 0x0f35: /* sysexit */ |
a3c4230a | 6927 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6928 | "instruction sysexit.\n")); |
6929 | ir.addr -= 2; | |
6930 | goto no_support; | |
6931 | break; | |
6932 | ||
a38bba38 | 6933 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6934 | { |
6935 | int ret; | |
a3c4230a | 6936 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 6937 | { |
a3c4230a | 6938 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6939 | "instruction syscall.\n")); |
6940 | ir.addr -= 2; | |
6941 | goto no_support; | |
6942 | } | |
a3c4230a | 6943 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
6944 | if (ret) |
6945 | return ret; | |
6946 | } | |
6947 | break; | |
6948 | ||
a38bba38 | 6949 | case 0x0f07: /* sysret */ |
a3c4230a | 6950 | printf_unfiltered (_("Process record does not support " |
cf648174 HZ |
6951 | "instruction sysret.\n")); |
6952 | ir.addr -= 2; | |
6953 | goto no_support; | |
6954 | break; | |
6955 | ||
a38bba38 | 6956 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
6957 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6958 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6959 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
6960 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
6961 | break; |
6962 | ||
a38bba38 | 6963 | case 0xf4: /* hlt */ |
a3c4230a | 6964 | printf_unfiltered (_("Process record does not support " |
7ad10968 HZ |
6965 | "instruction hlt.\n")); |
6966 | ir.addr -= 1; | |
6967 | goto no_support; | |
6968 | break; | |
6969 | ||
6970 | case 0x0f00: | |
6971 | if (i386_record_modrm (&ir)) | |
6972 | return -1; | |
6973 | switch (ir.reg) | |
6974 | { | |
a38bba38 MS |
6975 | case 0: /* sldt */ |
6976 | case 1: /* str */ | |
7ad10968 | 6977 | if (ir.mod == 3) |
25ea693b | 6978 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
6979 | else |
6980 | { | |
6981 | ir.ot = OT_WORD; | |
6982 | if (i386_record_lea_modrm (&ir)) | |
6983 | return -1; | |
6984 | } | |
6985 | break; | |
a38bba38 MS |
6986 | case 2: /* lldt */ |
6987 | case 3: /* ltr */ | |
7ad10968 | 6988 | break; |
a38bba38 MS |
6989 | case 4: /* verr */ |
6990 | case 5: /* verw */ | |
25ea693b | 6991 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6992 | break; |
6993 | default: | |
6994 | ir.addr -= 3; | |
6995 | opcode = opcode << 8 | ir.modrm; | |
6996 | goto no_support; | |
6997 | break; | |
6998 | } | |
6999 | break; | |
7000 | ||
7001 | case 0x0f01: | |
7002 | if (i386_record_modrm (&ir)) | |
7003 | return -1; | |
7004 | switch (ir.reg) | |
7005 | { | |
a38bba38 | 7006 | case 0: /* sgdt */ |
7ad10968 | 7007 | { |
955db0c0 | 7008 | uint64_t addr64; |
7ad10968 HZ |
7009 | |
7010 | if (ir.mod == 3) | |
7011 | { | |
7012 | ir.addr -= 3; | |
7013 | opcode = opcode << 8 | ir.modrm; | |
7014 | goto no_support; | |
7015 | } | |
d7877f7e | 7016 | if (ir.override >= 0) |
7ad10968 | 7017 | { |
25ea693b | 7018 | if (record_full_memory_query) |
bb08c432 | 7019 | { |
651ce16a | 7020 | if (yquery (_("\ |
bb08c432 HZ |
7021 | Process record ignores the memory change of instruction at address %s\n\ |
7022 | because it can't get the value of the segment register.\n\ | |
7023 | Do you want to stop the program?"), | |
651ce16a PA |
7024 | paddress (gdbarch, ir.orig_addr))) |
7025 | return -1; | |
bb08c432 | 7026 | } |
7ad10968 HZ |
7027 | } |
7028 | else | |
7029 | { | |
955db0c0 | 7030 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7031 | return -1; |
25ea693b | 7032 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7033 | return -1; |
955db0c0 | 7034 | addr64 += 2; |
cf648174 HZ |
7035 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7036 | { | |
25ea693b | 7037 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7038 | return -1; |
7039 | } | |
7040 | else | |
7041 | { | |
25ea693b | 7042 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7043 | return -1; |
7044 | } | |
7ad10968 HZ |
7045 | } |
7046 | } | |
7047 | break; | |
7048 | case 1: | |
7049 | if (ir.mod == 3) | |
7050 | { | |
7051 | switch (ir.rm) | |
7052 | { | |
a38bba38 | 7053 | case 0: /* monitor */ |
7ad10968 | 7054 | break; |
a38bba38 | 7055 | case 1: /* mwait */ |
25ea693b | 7056 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7057 | break; |
7058 | default: | |
7059 | ir.addr -= 3; | |
7060 | opcode = opcode << 8 | ir.modrm; | |
7061 | goto no_support; | |
7062 | break; | |
7063 | } | |
7064 | } | |
7065 | else | |
7066 | { | |
7067 | /* sidt */ | |
d7877f7e | 7068 | if (ir.override >= 0) |
7ad10968 | 7069 | { |
25ea693b | 7070 | if (record_full_memory_query) |
bb08c432 | 7071 | { |
651ce16a | 7072 | if (yquery (_("\ |
bb08c432 HZ |
7073 | Process record ignores the memory change of instruction at address %s\n\ |
7074 | because it can't get the value of the segment register.\n\ | |
7075 | Do you want to stop the program?"), | |
651ce16a | 7076 | paddress (gdbarch, ir.orig_addr))) |
bb08c432 HZ |
7077 | return -1; |
7078 | } | |
7ad10968 HZ |
7079 | } |
7080 | else | |
7081 | { | |
955db0c0 | 7082 | uint64_t addr64; |
7ad10968 | 7083 | |
955db0c0 | 7084 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7085 | return -1; |
25ea693b | 7086 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7087 | return -1; |
955db0c0 | 7088 | addr64 += 2; |
cf648174 HZ |
7089 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7090 | { | |
25ea693b | 7091 | if (record_full_arch_list_add_mem (addr64, 8)) |
cf648174 HZ |
7092 | return -1; |
7093 | } | |
7094 | else | |
7095 | { | |
25ea693b | 7096 | if (record_full_arch_list_add_mem (addr64, 4)) |
cf648174 HZ |
7097 | return -1; |
7098 | } | |
7ad10968 HZ |
7099 | } |
7100 | } | |
7101 | break; | |
a38bba38 | 7102 | case 2: /* lgdt */ |
3800e645 MS |
7103 | if (ir.mod == 3) |
7104 | { | |
7105 | /* xgetbv */ | |
7106 | if (ir.rm == 0) | |
7107 | { | |
25ea693b MM |
7108 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7109 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7110 | break; |
7111 | } | |
7112 | /* xsetbv */ | |
7113 | else if (ir.rm == 1) | |
7114 | break; | |
7115 | } | |
a38bba38 | 7116 | case 3: /* lidt */ |
7ad10968 HZ |
7117 | if (ir.mod == 3) |
7118 | { | |
7119 | ir.addr -= 3; | |
7120 | opcode = opcode << 8 | ir.modrm; | |
7121 | goto no_support; | |
7122 | } | |
7123 | break; | |
a38bba38 | 7124 | case 4: /* smsw */ |
7ad10968 HZ |
7125 | if (ir.mod == 3) |
7126 | { | |
25ea693b | 7127 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7128 | return -1; |
7129 | } | |
7130 | else | |
7131 | { | |
7132 | ir.ot = OT_WORD; | |
7133 | if (i386_record_lea_modrm (&ir)) | |
7134 | return -1; | |
7135 | } | |
25ea693b | 7136 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7137 | break; |
a38bba38 | 7138 | case 6: /* lmsw */ |
25ea693b | 7139 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7140 | break; |
a38bba38 | 7141 | case 7: /* invlpg */ |
cf648174 HZ |
7142 | if (ir.mod == 3) |
7143 | { | |
7144 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7145 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 HZ |
7146 | else |
7147 | { | |
7148 | ir.addr -= 3; | |
7149 | opcode = opcode << 8 | ir.modrm; | |
7150 | goto no_support; | |
7151 | } | |
7152 | } | |
7153 | else | |
25ea693b | 7154 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7155 | break; |
7156 | default: | |
7157 | ir.addr -= 3; | |
7158 | opcode = opcode << 8 | ir.modrm; | |
7159 | goto no_support; | |
7ad10968 HZ |
7160 | break; |
7161 | } | |
7162 | break; | |
7163 | ||
a38bba38 MS |
7164 | case 0x0f08: /* invd */ |
7165 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7166 | break; |
7167 | ||
a38bba38 | 7168 | case 0x63: /* arpl */ |
7ad10968 HZ |
7169 | if (i386_record_modrm (&ir)) |
7170 | return -1; | |
cf648174 HZ |
7171 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
7172 | { | |
25ea693b MM |
7173 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] |
7174 | ? (ir.reg | rex_r) : ir.rm); | |
cf648174 | 7175 | } |
7ad10968 | 7176 | else |
cf648174 HZ |
7177 | { |
7178 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7179 | if (i386_record_lea_modrm (&ir)) | |
7180 | return -1; | |
7181 | } | |
7182 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) | |
25ea693b | 7183 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7184 | break; |
7185 | ||
a38bba38 MS |
7186 | case 0x0f02: /* lar */ |
7187 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7188 | if (i386_record_modrm (&ir)) |
7189 | return -1; | |
25ea693b MM |
7190 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7191 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7192 | break; |
7193 | ||
7194 | case 0x0f18: | |
cf648174 HZ |
7195 | if (i386_record_modrm (&ir)) |
7196 | return -1; | |
7197 | if (ir.mod == 3 && ir.reg == 3) | |
7198 | { | |
7199 | ir.addr -= 3; | |
7200 | opcode = opcode << 8 | ir.modrm; | |
7201 | goto no_support; | |
7202 | } | |
7ad10968 HZ |
7203 | break; |
7204 | ||
7ad10968 HZ |
7205 | case 0x0f19: |
7206 | case 0x0f1a: | |
7207 | case 0x0f1b: | |
7208 | case 0x0f1c: | |
7209 | case 0x0f1d: | |
7210 | case 0x0f1e: | |
7211 | case 0x0f1f: | |
a38bba38 | 7212 | /* nop (multi byte) */ |
7ad10968 HZ |
7213 | break; |
7214 | ||
a38bba38 MS |
7215 | case 0x0f20: /* mov reg, crN */ |
7216 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7217 | if (i386_record_modrm (&ir)) |
7218 | return -1; | |
7219 | if ((ir.modrm & 0xc0) != 0xc0) | |
7220 | { | |
cf648174 | 7221 | ir.addr -= 3; |
7ad10968 HZ |
7222 | opcode = opcode << 8 | ir.modrm; |
7223 | goto no_support; | |
7224 | } | |
7225 | switch (ir.reg) | |
7226 | { | |
7227 | case 0: | |
7228 | case 2: | |
7229 | case 3: | |
7230 | case 4: | |
7231 | case 8: | |
7232 | if (opcode & 2) | |
25ea693b | 7233 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7234 | else |
25ea693b | 7235 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7236 | break; |
7237 | default: | |
cf648174 | 7238 | ir.addr -= 3; |
7ad10968 HZ |
7239 | opcode = opcode << 8 | ir.modrm; |
7240 | goto no_support; | |
7241 | break; | |
7242 | } | |
7243 | break; | |
7244 | ||
a38bba38 MS |
7245 | case 0x0f21: /* mov reg, drN */ |
7246 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7247 | if (i386_record_modrm (&ir)) |
7248 | return -1; | |
7249 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7250 | || ir.reg == 5 || ir.reg >= 8) | |
7251 | { | |
cf648174 | 7252 | ir.addr -= 3; |
7ad10968 HZ |
7253 | opcode = opcode << 8 | ir.modrm; |
7254 | goto no_support; | |
7255 | } | |
7256 | if (opcode & 2) | |
25ea693b | 7257 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7258 | else |
25ea693b | 7259 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7260 | break; |
7261 | ||
a38bba38 | 7262 | case 0x0f06: /* clts */ |
25ea693b | 7263 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7264 | break; |
7265 | ||
a3c4230a HZ |
7266 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7267 | ||
7268 | case 0x0f0d: /* 3DNow! prefetch */ | |
7269 | break; | |
7270 | ||
7271 | case 0x0f0e: /* 3DNow! femms */ | |
7272 | case 0x0f77: /* emms */ | |
7273 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
7274 | goto no_support; | |
25ea693b | 7275 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7276 | break; |
7277 | ||
7278 | case 0x0f0f: /* 3DNow! data */ | |
7279 | if (i386_record_modrm (&ir)) | |
7280 | return -1; | |
4ffa4fc7 PA |
7281 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7282 | return -1; | |
a3c4230a HZ |
7283 | ir.addr++; |
7284 | switch (opcode8) | |
7285 | { | |
7286 | case 0x0c: /* 3DNow! pi2fw */ | |
7287 | case 0x0d: /* 3DNow! pi2fd */ | |
7288 | case 0x1c: /* 3DNow! pf2iw */ | |
7289 | case 0x1d: /* 3DNow! pf2id */ | |
7290 | case 0x8a: /* 3DNow! pfnacc */ | |
7291 | case 0x8e: /* 3DNow! pfpnacc */ | |
7292 | case 0x90: /* 3DNow! pfcmpge */ | |
7293 | case 0x94: /* 3DNow! pfmin */ | |
7294 | case 0x96: /* 3DNow! pfrcp */ | |
7295 | case 0x97: /* 3DNow! pfrsqrt */ | |
7296 | case 0x9a: /* 3DNow! pfsub */ | |
7297 | case 0x9e: /* 3DNow! pfadd */ | |
7298 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7299 | case 0xa4: /* 3DNow! pfmax */ | |
7300 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7301 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7302 | case 0xaa: /* 3DNow! pfsubr */ | |
7303 | case 0xae: /* 3DNow! pfacc */ | |
7304 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7305 | case 0xb4: /* 3DNow! pfmul */ | |
7306 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7307 | case 0xb7: /* 3DNow! pmulhrw */ | |
7308 | case 0xbb: /* 3DNow! pswapd */ | |
7309 | case 0xbf: /* 3DNow! pavgusb */ | |
7310 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7311 | goto no_support_3dnow_data; | |
25ea693b | 7312 | record_full_arch_list_add_reg (ir.regcache, ir.reg); |
a3c4230a HZ |
7313 | break; |
7314 | ||
7315 | default: | |
7316 | no_support_3dnow_data: | |
7317 | opcode = (opcode << 8) | opcode8; | |
7318 | goto no_support; | |
7319 | break; | |
7320 | } | |
7321 | break; | |
7322 | ||
7323 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7324 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7325 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7326 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7327 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7328 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7329 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7330 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7331 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7332 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7333 | break; |
7334 | ||
7335 | case 0x0fae: | |
7336 | if (i386_record_modrm (&ir)) | |
7337 | return -1; | |
7338 | switch(ir.reg) | |
7339 | { | |
7340 | case 0: /* fxsave */ | |
7341 | { | |
7342 | uint64_t tmpu64; | |
7343 | ||
25ea693b | 7344 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7345 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7346 | return -1; | |
25ea693b | 7347 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
a3c4230a HZ |
7348 | return -1; |
7349 | } | |
7350 | break; | |
7351 | ||
7352 | case 1: /* fxrstor */ | |
7353 | { | |
7354 | int i; | |
7355 | ||
25ea693b | 7356 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7357 | |
7358 | for (i = I387_MM0_REGNUM (tdep); | |
7359 | i386_mmx_regnum_p (gdbarch, i); i++) | |
25ea693b | 7360 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7361 | |
7362 | for (i = I387_XMM0_REGNUM (tdep); | |
c131fcee | 7363 | i386_xmm_regnum_p (gdbarch, i); i++) |
25ea693b | 7364 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7365 | |
7366 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
25ea693b MM |
7367 | record_full_arch_list_add_reg (ir.regcache, |
7368 | I387_MXCSR_REGNUM(tdep)); | |
a3c4230a HZ |
7369 | |
7370 | for (i = I387_ST0_REGNUM (tdep); | |
7371 | i386_fp_regnum_p (gdbarch, i); i++) | |
25ea693b | 7372 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7373 | |
7374 | for (i = I387_FCTRL_REGNUM (tdep); | |
7375 | i386_fpc_regnum_p (gdbarch, i); i++) | |
25ea693b | 7376 | record_full_arch_list_add_reg (ir.regcache, i); |
a3c4230a HZ |
7377 | } |
7378 | break; | |
7379 | ||
7380 | case 2: /* ldmxcsr */ | |
7381 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7382 | goto no_support; | |
25ea693b | 7383 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); |
a3c4230a HZ |
7384 | break; |
7385 | ||
7386 | case 3: /* stmxcsr */ | |
7387 | ir.ot = OT_LONG; | |
7388 | if (i386_record_lea_modrm (&ir)) | |
7389 | return -1; | |
7390 | break; | |
7391 | ||
7392 | case 5: /* lfence */ | |
7393 | case 6: /* mfence */ | |
7394 | case 7: /* sfence clflush */ | |
7395 | break; | |
7396 | ||
7397 | default: | |
7398 | opcode = (opcode << 8) | ir.modrm; | |
7399 | goto no_support; | |
7400 | break; | |
7401 | } | |
7402 | break; | |
7403 | ||
7404 | case 0x0fc3: /* movnti */ | |
7405 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7406 | if (i386_record_modrm (&ir)) | |
7407 | return -1; | |
7408 | if (ir.mod == 3) | |
7409 | goto no_support; | |
7410 | ir.reg |= rex_r; | |
7411 | if (i386_record_lea_modrm (&ir)) | |
7412 | return -1; | |
7413 | break; | |
7414 | ||
7415 | /* Add prefix to opcode. */ | |
7416 | case 0x0f10: | |
7417 | case 0x0f11: | |
7418 | case 0x0f12: | |
7419 | case 0x0f13: | |
7420 | case 0x0f14: | |
7421 | case 0x0f15: | |
7422 | case 0x0f16: | |
7423 | case 0x0f17: | |
7424 | case 0x0f28: | |
7425 | case 0x0f29: | |
7426 | case 0x0f2a: | |
7427 | case 0x0f2b: | |
7428 | case 0x0f2c: | |
7429 | case 0x0f2d: | |
7430 | case 0x0f2e: | |
7431 | case 0x0f2f: | |
7432 | case 0x0f38: | |
7433 | case 0x0f39: | |
7434 | case 0x0f3a: | |
7435 | case 0x0f50: | |
7436 | case 0x0f51: | |
7437 | case 0x0f52: | |
7438 | case 0x0f53: | |
7439 | case 0x0f54: | |
7440 | case 0x0f55: | |
7441 | case 0x0f56: | |
7442 | case 0x0f57: | |
7443 | case 0x0f58: | |
7444 | case 0x0f59: | |
7445 | case 0x0f5a: | |
7446 | case 0x0f5b: | |
7447 | case 0x0f5c: | |
7448 | case 0x0f5d: | |
7449 | case 0x0f5e: | |
7450 | case 0x0f5f: | |
7451 | case 0x0f60: | |
7452 | case 0x0f61: | |
7453 | case 0x0f62: | |
7454 | case 0x0f63: | |
7455 | case 0x0f64: | |
7456 | case 0x0f65: | |
7457 | case 0x0f66: | |
7458 | case 0x0f67: | |
7459 | case 0x0f68: | |
7460 | case 0x0f69: | |
7461 | case 0x0f6a: | |
7462 | case 0x0f6b: | |
7463 | case 0x0f6c: | |
7464 | case 0x0f6d: | |
7465 | case 0x0f6e: | |
7466 | case 0x0f6f: | |
7467 | case 0x0f70: | |
7468 | case 0x0f71: | |
7469 | case 0x0f72: | |
7470 | case 0x0f73: | |
7471 | case 0x0f74: | |
7472 | case 0x0f75: | |
7473 | case 0x0f76: | |
7474 | case 0x0f7c: | |
7475 | case 0x0f7d: | |
7476 | case 0x0f7e: | |
7477 | case 0x0f7f: | |
7478 | case 0x0fb8: | |
7479 | case 0x0fc2: | |
7480 | case 0x0fc4: | |
7481 | case 0x0fc5: | |
7482 | case 0x0fc6: | |
7483 | case 0x0fd0: | |
7484 | case 0x0fd1: | |
7485 | case 0x0fd2: | |
7486 | case 0x0fd3: | |
7487 | case 0x0fd4: | |
7488 | case 0x0fd5: | |
7489 | case 0x0fd6: | |
7490 | case 0x0fd7: | |
7491 | case 0x0fd8: | |
7492 | case 0x0fd9: | |
7493 | case 0x0fda: | |
7494 | case 0x0fdb: | |
7495 | case 0x0fdc: | |
7496 | case 0x0fdd: | |
7497 | case 0x0fde: | |
7498 | case 0x0fdf: | |
7499 | case 0x0fe0: | |
7500 | case 0x0fe1: | |
7501 | case 0x0fe2: | |
7502 | case 0x0fe3: | |
7503 | case 0x0fe4: | |
7504 | case 0x0fe5: | |
7505 | case 0x0fe6: | |
7506 | case 0x0fe7: | |
7507 | case 0x0fe8: | |
7508 | case 0x0fe9: | |
7509 | case 0x0fea: | |
7510 | case 0x0feb: | |
7511 | case 0x0fec: | |
7512 | case 0x0fed: | |
7513 | case 0x0fee: | |
7514 | case 0x0fef: | |
7515 | case 0x0ff0: | |
7516 | case 0x0ff1: | |
7517 | case 0x0ff2: | |
7518 | case 0x0ff3: | |
7519 | case 0x0ff4: | |
7520 | case 0x0ff5: | |
7521 | case 0x0ff6: | |
7522 | case 0x0ff7: | |
7523 | case 0x0ff8: | |
7524 | case 0x0ff9: | |
7525 | case 0x0ffa: | |
7526 | case 0x0ffb: | |
7527 | case 0x0ffc: | |
7528 | case 0x0ffd: | |
7529 | case 0x0ffe: | |
f9fda3f5 L |
7530 | /* Mask out PREFIX_ADDR. */ |
7531 | switch ((prefixes & ~PREFIX_ADDR)) | |
a3c4230a HZ |
7532 | { |
7533 | case PREFIX_REPNZ: | |
7534 | opcode |= 0xf20000; | |
7535 | break; | |
7536 | case PREFIX_DATA: | |
7537 | opcode |= 0x660000; | |
7538 | break; | |
7539 | case PREFIX_REPZ: | |
7540 | opcode |= 0xf30000; | |
7541 | break; | |
7542 | } | |
7543 | reswitch_prefix_add: | |
7544 | switch (opcode) | |
7545 | { | |
7546 | case 0x0f38: | |
7547 | case 0x660f38: | |
7548 | case 0xf20f38: | |
7549 | case 0x0f3a: | |
7550 | case 0x660f3a: | |
4ffa4fc7 PA |
7551 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7552 | return -1; | |
a3c4230a HZ |
7553 | ir.addr++; |
7554 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7555 | goto reswitch_prefix_add; | |
7556 | break; | |
7557 | ||
7558 | case 0x0f10: /* movups */ | |
7559 | case 0x660f10: /* movupd */ | |
7560 | case 0xf30f10: /* movss */ | |
7561 | case 0xf20f10: /* movsd */ | |
7562 | case 0x0f12: /* movlps */ | |
7563 | case 0x660f12: /* movlpd */ | |
7564 | case 0xf30f12: /* movsldup */ | |
7565 | case 0xf20f12: /* movddup */ | |
7566 | case 0x0f14: /* unpcklps */ | |
7567 | case 0x660f14: /* unpcklpd */ | |
7568 | case 0x0f15: /* unpckhps */ | |
7569 | case 0x660f15: /* unpckhpd */ | |
7570 | case 0x0f16: /* movhps */ | |
7571 | case 0x660f16: /* movhpd */ | |
7572 | case 0xf30f16: /* movshdup */ | |
7573 | case 0x0f28: /* movaps */ | |
7574 | case 0x660f28: /* movapd */ | |
7575 | case 0x0f2a: /* cvtpi2ps */ | |
7576 | case 0x660f2a: /* cvtpi2pd */ | |
7577 | case 0xf30f2a: /* cvtsi2ss */ | |
7578 | case 0xf20f2a: /* cvtsi2sd */ | |
7579 | case 0x0f2c: /* cvttps2pi */ | |
7580 | case 0x660f2c: /* cvttpd2pi */ | |
7581 | case 0x0f2d: /* cvtps2pi */ | |
7582 | case 0x660f2d: /* cvtpd2pi */ | |
7583 | case 0x660f3800: /* pshufb */ | |
7584 | case 0x660f3801: /* phaddw */ | |
7585 | case 0x660f3802: /* phaddd */ | |
7586 | case 0x660f3803: /* phaddsw */ | |
7587 | case 0x660f3804: /* pmaddubsw */ | |
7588 | case 0x660f3805: /* phsubw */ | |
7589 | case 0x660f3806: /* phsubd */ | |
4f7d61a8 | 7590 | case 0x660f3807: /* phsubsw */ |
a3c4230a HZ |
7591 | case 0x660f3808: /* psignb */ |
7592 | case 0x660f3809: /* psignw */ | |
7593 | case 0x660f380a: /* psignd */ | |
7594 | case 0x660f380b: /* pmulhrsw */ | |
7595 | case 0x660f3810: /* pblendvb */ | |
7596 | case 0x660f3814: /* blendvps */ | |
7597 | case 0x660f3815: /* blendvpd */ | |
7598 | case 0x660f381c: /* pabsb */ | |
7599 | case 0x660f381d: /* pabsw */ | |
7600 | case 0x660f381e: /* pabsd */ | |
7601 | case 0x660f3820: /* pmovsxbw */ | |
7602 | case 0x660f3821: /* pmovsxbd */ | |
7603 | case 0x660f3822: /* pmovsxbq */ | |
7604 | case 0x660f3823: /* pmovsxwd */ | |
7605 | case 0x660f3824: /* pmovsxwq */ | |
7606 | case 0x660f3825: /* pmovsxdq */ | |
7607 | case 0x660f3828: /* pmuldq */ | |
7608 | case 0x660f3829: /* pcmpeqq */ | |
7609 | case 0x660f382a: /* movntdqa */ | |
7610 | case 0x660f3a08: /* roundps */ | |
7611 | case 0x660f3a09: /* roundpd */ | |
7612 | case 0x660f3a0a: /* roundss */ | |
7613 | case 0x660f3a0b: /* roundsd */ | |
7614 | case 0x660f3a0c: /* blendps */ | |
7615 | case 0x660f3a0d: /* blendpd */ | |
7616 | case 0x660f3a0e: /* pblendw */ | |
7617 | case 0x660f3a0f: /* palignr */ | |
7618 | case 0x660f3a20: /* pinsrb */ | |
7619 | case 0x660f3a21: /* insertps */ | |
7620 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7621 | case 0x660f3a40: /* dpps */ | |
7622 | case 0x660f3a41: /* dppd */ | |
7623 | case 0x660f3a42: /* mpsadbw */ | |
7624 | case 0x660f3a60: /* pcmpestrm */ | |
7625 | case 0x660f3a61: /* pcmpestri */ | |
7626 | case 0x660f3a62: /* pcmpistrm */ | |
7627 | case 0x660f3a63: /* pcmpistri */ | |
7628 | case 0x0f51: /* sqrtps */ | |
7629 | case 0x660f51: /* sqrtpd */ | |
7630 | case 0xf20f51: /* sqrtsd */ | |
7631 | case 0xf30f51: /* sqrtss */ | |
7632 | case 0x0f52: /* rsqrtps */ | |
7633 | case 0xf30f52: /* rsqrtss */ | |
7634 | case 0x0f53: /* rcpps */ | |
7635 | case 0xf30f53: /* rcpss */ | |
7636 | case 0x0f54: /* andps */ | |
7637 | case 0x660f54: /* andpd */ | |
7638 | case 0x0f55: /* andnps */ | |
7639 | case 0x660f55: /* andnpd */ | |
7640 | case 0x0f56: /* orps */ | |
7641 | case 0x660f56: /* orpd */ | |
7642 | case 0x0f57: /* xorps */ | |
7643 | case 0x660f57: /* xorpd */ | |
7644 | case 0x0f58: /* addps */ | |
7645 | case 0x660f58: /* addpd */ | |
7646 | case 0xf20f58: /* addsd */ | |
7647 | case 0xf30f58: /* addss */ | |
7648 | case 0x0f59: /* mulps */ | |
7649 | case 0x660f59: /* mulpd */ | |
7650 | case 0xf20f59: /* mulsd */ | |
7651 | case 0xf30f59: /* mulss */ | |
7652 | case 0x0f5a: /* cvtps2pd */ | |
7653 | case 0x660f5a: /* cvtpd2ps */ | |
7654 | case 0xf20f5a: /* cvtsd2ss */ | |
7655 | case 0xf30f5a: /* cvtss2sd */ | |
7656 | case 0x0f5b: /* cvtdq2ps */ | |
7657 | case 0x660f5b: /* cvtps2dq */ | |
7658 | case 0xf30f5b: /* cvttps2dq */ | |
7659 | case 0x0f5c: /* subps */ | |
7660 | case 0x660f5c: /* subpd */ | |
7661 | case 0xf20f5c: /* subsd */ | |
7662 | case 0xf30f5c: /* subss */ | |
7663 | case 0x0f5d: /* minps */ | |
7664 | case 0x660f5d: /* minpd */ | |
7665 | case 0xf20f5d: /* minsd */ | |
7666 | case 0xf30f5d: /* minss */ | |
7667 | case 0x0f5e: /* divps */ | |
7668 | case 0x660f5e: /* divpd */ | |
7669 | case 0xf20f5e: /* divsd */ | |
7670 | case 0xf30f5e: /* divss */ | |
7671 | case 0x0f5f: /* maxps */ | |
7672 | case 0x660f5f: /* maxpd */ | |
7673 | case 0xf20f5f: /* maxsd */ | |
7674 | case 0xf30f5f: /* maxss */ | |
7675 | case 0x660f60: /* punpcklbw */ | |
7676 | case 0x660f61: /* punpcklwd */ | |
7677 | case 0x660f62: /* punpckldq */ | |
7678 | case 0x660f63: /* packsswb */ | |
7679 | case 0x660f64: /* pcmpgtb */ | |
7680 | case 0x660f65: /* pcmpgtw */ | |
56d2815c | 7681 | case 0x660f66: /* pcmpgtd */ |
a3c4230a HZ |
7682 | case 0x660f67: /* packuswb */ |
7683 | case 0x660f68: /* punpckhbw */ | |
7684 | case 0x660f69: /* punpckhwd */ | |
7685 | case 0x660f6a: /* punpckhdq */ | |
7686 | case 0x660f6b: /* packssdw */ | |
7687 | case 0x660f6c: /* punpcklqdq */ | |
7688 | case 0x660f6d: /* punpckhqdq */ | |
7689 | case 0x660f6e: /* movd */ | |
7690 | case 0x660f6f: /* movdqa */ | |
7691 | case 0xf30f6f: /* movdqu */ | |
7692 | case 0x660f70: /* pshufd */ | |
7693 | case 0xf20f70: /* pshuflw */ | |
7694 | case 0xf30f70: /* pshufhw */ | |
7695 | case 0x660f74: /* pcmpeqb */ | |
7696 | case 0x660f75: /* pcmpeqw */ | |
56d2815c | 7697 | case 0x660f76: /* pcmpeqd */ |
a3c4230a HZ |
7698 | case 0x660f7c: /* haddpd */ |
7699 | case 0xf20f7c: /* haddps */ | |
7700 | case 0x660f7d: /* hsubpd */ | |
7701 | case 0xf20f7d: /* hsubps */ | |
7702 | case 0xf30f7e: /* movq */ | |
7703 | case 0x0fc2: /* cmpps */ | |
7704 | case 0x660fc2: /* cmppd */ | |
7705 | case 0xf20fc2: /* cmpsd */ | |
7706 | case 0xf30fc2: /* cmpss */ | |
7707 | case 0x660fc4: /* pinsrw */ | |
7708 | case 0x0fc6: /* shufps */ | |
7709 | case 0x660fc6: /* shufpd */ | |
7710 | case 0x660fd0: /* addsubpd */ | |
7711 | case 0xf20fd0: /* addsubps */ | |
7712 | case 0x660fd1: /* psrlw */ | |
7713 | case 0x660fd2: /* psrld */ | |
7714 | case 0x660fd3: /* psrlq */ | |
7715 | case 0x660fd4: /* paddq */ | |
7716 | case 0x660fd5: /* pmullw */ | |
7717 | case 0xf30fd6: /* movq2dq */ | |
7718 | case 0x660fd8: /* psubusb */ | |
7719 | case 0x660fd9: /* psubusw */ | |
7720 | case 0x660fda: /* pminub */ | |
7721 | case 0x660fdb: /* pand */ | |
7722 | case 0x660fdc: /* paddusb */ | |
7723 | case 0x660fdd: /* paddusw */ | |
7724 | case 0x660fde: /* pmaxub */ | |
7725 | case 0x660fdf: /* pandn */ | |
7726 | case 0x660fe0: /* pavgb */ | |
7727 | case 0x660fe1: /* psraw */ | |
7728 | case 0x660fe2: /* psrad */ | |
7729 | case 0x660fe3: /* pavgw */ | |
7730 | case 0x660fe4: /* pmulhuw */ | |
7731 | case 0x660fe5: /* pmulhw */ | |
7732 | case 0x660fe6: /* cvttpd2dq */ | |
7733 | case 0xf20fe6: /* cvtpd2dq */ | |
7734 | case 0xf30fe6: /* cvtdq2pd */ | |
7735 | case 0x660fe8: /* psubsb */ | |
7736 | case 0x660fe9: /* psubsw */ | |
7737 | case 0x660fea: /* pminsw */ | |
7738 | case 0x660feb: /* por */ | |
7739 | case 0x660fec: /* paddsb */ | |
7740 | case 0x660fed: /* paddsw */ | |
7741 | case 0x660fee: /* pmaxsw */ | |
7742 | case 0x660fef: /* pxor */ | |
4f7d61a8 | 7743 | case 0xf20ff0: /* lddqu */ |
a3c4230a HZ |
7744 | case 0x660ff1: /* psllw */ |
7745 | case 0x660ff2: /* pslld */ | |
7746 | case 0x660ff3: /* psllq */ | |
7747 | case 0x660ff4: /* pmuludq */ | |
7748 | case 0x660ff5: /* pmaddwd */ | |
7749 | case 0x660ff6: /* psadbw */ | |
7750 | case 0x660ff8: /* psubb */ | |
7751 | case 0x660ff9: /* psubw */ | |
56d2815c | 7752 | case 0x660ffa: /* psubd */ |
a3c4230a HZ |
7753 | case 0x660ffb: /* psubq */ |
7754 | case 0x660ffc: /* paddb */ | |
7755 | case 0x660ffd: /* paddw */ | |
56d2815c | 7756 | case 0x660ffe: /* paddd */ |
a3c4230a HZ |
7757 | if (i386_record_modrm (&ir)) |
7758 | return -1; | |
7759 | ir.reg |= rex_r; | |
c131fcee | 7760 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) |
a3c4230a | 7761 | goto no_support; |
25ea693b MM |
7762 | record_full_arch_list_add_reg (ir.regcache, |
7763 | I387_XMM0_REGNUM (tdep) + ir.reg); | |
a3c4230a | 7764 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
25ea693b | 7765 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7766 | break; |
7767 | ||
7768 | case 0x0f11: /* movups */ | |
7769 | case 0x660f11: /* movupd */ | |
7770 | case 0xf30f11: /* movss */ | |
7771 | case 0xf20f11: /* movsd */ | |
7772 | case 0x0f13: /* movlps */ | |
7773 | case 0x660f13: /* movlpd */ | |
7774 | case 0x0f17: /* movhps */ | |
7775 | case 0x660f17: /* movhpd */ | |
7776 | case 0x0f29: /* movaps */ | |
7777 | case 0x660f29: /* movapd */ | |
7778 | case 0x660f3a14: /* pextrb */ | |
7779 | case 0x660f3a15: /* pextrw */ | |
7780 | case 0x660f3a16: /* pextrd pextrq */ | |
7781 | case 0x660f3a17: /* extractps */ | |
7782 | case 0x660f7f: /* movdqa */ | |
7783 | case 0xf30f7f: /* movdqu */ | |
7784 | if (i386_record_modrm (&ir)) | |
7785 | return -1; | |
7786 | if (ir.mod == 3) | |
7787 | { | |
7788 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7789 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7790 | goto no_support; | |
7791 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
7792 | if (!i386_xmm_regnum_p (gdbarch, |
7793 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 7794 | goto no_support; |
25ea693b MM |
7795 | record_full_arch_list_add_reg (ir.regcache, |
7796 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7797 | } |
7798 | else | |
7799 | { | |
7800 | switch (opcode) | |
7801 | { | |
7802 | case 0x660f3a14: | |
7803 | ir.ot = OT_BYTE; | |
7804 | break; | |
7805 | case 0x660f3a15: | |
7806 | ir.ot = OT_WORD; | |
7807 | break; | |
7808 | case 0x660f3a16: | |
7809 | ir.ot = OT_LONG; | |
7810 | break; | |
7811 | case 0x660f3a17: | |
7812 | ir.ot = OT_QUAD; | |
7813 | break; | |
7814 | default: | |
7815 | ir.ot = OT_DQUAD; | |
7816 | break; | |
7817 | } | |
7818 | if (i386_record_lea_modrm (&ir)) | |
7819 | return -1; | |
7820 | } | |
7821 | break; | |
7822 | ||
7823 | case 0x0f2b: /* movntps */ | |
7824 | case 0x660f2b: /* movntpd */ | |
7825 | case 0x0fe7: /* movntq */ | |
7826 | case 0x660fe7: /* movntdq */ | |
7827 | if (ir.mod == 3) | |
7828 | goto no_support; | |
7829 | if (opcode == 0x0fe7) | |
7830 | ir.ot = OT_QUAD; | |
7831 | else | |
7832 | ir.ot = OT_DQUAD; | |
7833 | if (i386_record_lea_modrm (&ir)) | |
7834 | return -1; | |
7835 | break; | |
7836 | ||
7837 | case 0xf30f2c: /* cvttss2si */ | |
7838 | case 0xf20f2c: /* cvttsd2si */ | |
7839 | case 0xf30f2d: /* cvtss2si */ | |
7840 | case 0xf20f2d: /* cvtsd2si */ | |
7841 | case 0xf20f38f0: /* crc32 */ | |
7842 | case 0xf20f38f1: /* crc32 */ | |
7843 | case 0x0f50: /* movmskps */ | |
7844 | case 0x660f50: /* movmskpd */ | |
7845 | case 0x0fc5: /* pextrw */ | |
7846 | case 0x660fc5: /* pextrw */ | |
7847 | case 0x0fd7: /* pmovmskb */ | |
7848 | case 0x660fd7: /* pmovmskb */ | |
25ea693b | 7849 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
a3c4230a HZ |
7850 | break; |
7851 | ||
7852 | case 0x0f3800: /* pshufb */ | |
7853 | case 0x0f3801: /* phaddw */ | |
7854 | case 0x0f3802: /* phaddd */ | |
7855 | case 0x0f3803: /* phaddsw */ | |
7856 | case 0x0f3804: /* pmaddubsw */ | |
7857 | case 0x0f3805: /* phsubw */ | |
7858 | case 0x0f3806: /* phsubd */ | |
4f7d61a8 | 7859 | case 0x0f3807: /* phsubsw */ |
a3c4230a HZ |
7860 | case 0x0f3808: /* psignb */ |
7861 | case 0x0f3809: /* psignw */ | |
7862 | case 0x0f380a: /* psignd */ | |
7863 | case 0x0f380b: /* pmulhrsw */ | |
7864 | case 0x0f381c: /* pabsb */ | |
7865 | case 0x0f381d: /* pabsw */ | |
7866 | case 0x0f381e: /* pabsd */ | |
7867 | case 0x0f382b: /* packusdw */ | |
7868 | case 0x0f3830: /* pmovzxbw */ | |
7869 | case 0x0f3831: /* pmovzxbd */ | |
7870 | case 0x0f3832: /* pmovzxbq */ | |
7871 | case 0x0f3833: /* pmovzxwd */ | |
7872 | case 0x0f3834: /* pmovzxwq */ | |
7873 | case 0x0f3835: /* pmovzxdq */ | |
7874 | case 0x0f3837: /* pcmpgtq */ | |
7875 | case 0x0f3838: /* pminsb */ | |
7876 | case 0x0f3839: /* pminsd */ | |
7877 | case 0x0f383a: /* pminuw */ | |
7878 | case 0x0f383b: /* pminud */ | |
7879 | case 0x0f383c: /* pmaxsb */ | |
7880 | case 0x0f383d: /* pmaxsd */ | |
7881 | case 0x0f383e: /* pmaxuw */ | |
7882 | case 0x0f383f: /* pmaxud */ | |
7883 | case 0x0f3840: /* pmulld */ | |
7884 | case 0x0f3841: /* phminposuw */ | |
7885 | case 0x0f3a0f: /* palignr */ | |
7886 | case 0x0f60: /* punpcklbw */ | |
7887 | case 0x0f61: /* punpcklwd */ | |
7888 | case 0x0f62: /* punpckldq */ | |
7889 | case 0x0f63: /* packsswb */ | |
7890 | case 0x0f64: /* pcmpgtb */ | |
7891 | case 0x0f65: /* pcmpgtw */ | |
56d2815c | 7892 | case 0x0f66: /* pcmpgtd */ |
a3c4230a HZ |
7893 | case 0x0f67: /* packuswb */ |
7894 | case 0x0f68: /* punpckhbw */ | |
7895 | case 0x0f69: /* punpckhwd */ | |
7896 | case 0x0f6a: /* punpckhdq */ | |
7897 | case 0x0f6b: /* packssdw */ | |
7898 | case 0x0f6e: /* movd */ | |
7899 | case 0x0f6f: /* movq */ | |
7900 | case 0x0f70: /* pshufw */ | |
7901 | case 0x0f74: /* pcmpeqb */ | |
7902 | case 0x0f75: /* pcmpeqw */ | |
56d2815c | 7903 | case 0x0f76: /* pcmpeqd */ |
a3c4230a HZ |
7904 | case 0x0fc4: /* pinsrw */ |
7905 | case 0x0fd1: /* psrlw */ | |
7906 | case 0x0fd2: /* psrld */ | |
7907 | case 0x0fd3: /* psrlq */ | |
7908 | case 0x0fd4: /* paddq */ | |
7909 | case 0x0fd5: /* pmullw */ | |
7910 | case 0xf20fd6: /* movdq2q */ | |
7911 | case 0x0fd8: /* psubusb */ | |
7912 | case 0x0fd9: /* psubusw */ | |
7913 | case 0x0fda: /* pminub */ | |
7914 | case 0x0fdb: /* pand */ | |
7915 | case 0x0fdc: /* paddusb */ | |
7916 | case 0x0fdd: /* paddusw */ | |
7917 | case 0x0fde: /* pmaxub */ | |
7918 | case 0x0fdf: /* pandn */ | |
7919 | case 0x0fe0: /* pavgb */ | |
7920 | case 0x0fe1: /* psraw */ | |
7921 | case 0x0fe2: /* psrad */ | |
7922 | case 0x0fe3: /* pavgw */ | |
7923 | case 0x0fe4: /* pmulhuw */ | |
7924 | case 0x0fe5: /* pmulhw */ | |
7925 | case 0x0fe8: /* psubsb */ | |
7926 | case 0x0fe9: /* psubsw */ | |
7927 | case 0x0fea: /* pminsw */ | |
7928 | case 0x0feb: /* por */ | |
7929 | case 0x0fec: /* paddsb */ | |
7930 | case 0x0fed: /* paddsw */ | |
7931 | case 0x0fee: /* pmaxsw */ | |
7932 | case 0x0fef: /* pxor */ | |
7933 | case 0x0ff1: /* psllw */ | |
7934 | case 0x0ff2: /* pslld */ | |
7935 | case 0x0ff3: /* psllq */ | |
7936 | case 0x0ff4: /* pmuludq */ | |
7937 | case 0x0ff5: /* pmaddwd */ | |
7938 | case 0x0ff6: /* psadbw */ | |
7939 | case 0x0ff8: /* psubb */ | |
7940 | case 0x0ff9: /* psubw */ | |
56d2815c | 7941 | case 0x0ffa: /* psubd */ |
a3c4230a HZ |
7942 | case 0x0ffb: /* psubq */ |
7943 | case 0x0ffc: /* paddb */ | |
7944 | case 0x0ffd: /* paddw */ | |
56d2815c | 7945 | case 0x0ffe: /* paddd */ |
a3c4230a HZ |
7946 | if (i386_record_modrm (&ir)) |
7947 | return -1; | |
7948 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7949 | goto no_support; | |
25ea693b MM |
7950 | record_full_arch_list_add_reg (ir.regcache, |
7951 | I387_MM0_REGNUM (tdep) + ir.reg); | |
a3c4230a HZ |
7952 | break; |
7953 | ||
7954 | case 0x0f71: /* psllw */ | |
7955 | case 0x0f72: /* pslld */ | |
7956 | case 0x0f73: /* psllq */ | |
7957 | if (i386_record_modrm (&ir)) | |
7958 | return -1; | |
7959 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
7960 | goto no_support; | |
25ea693b MM |
7961 | record_full_arch_list_add_reg (ir.regcache, |
7962 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7963 | break; |
7964 | ||
7965 | case 0x660f71: /* psllw */ | |
7966 | case 0x660f72: /* pslld */ | |
7967 | case 0x660f73: /* psllq */ | |
7968 | if (i386_record_modrm (&ir)) | |
7969 | return -1; | |
7970 | ir.rm |= ir.rex_b; | |
c131fcee | 7971 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) |
a3c4230a | 7972 | goto no_support; |
25ea693b MM |
7973 | record_full_arch_list_add_reg (ir.regcache, |
7974 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
7975 | break; |
7976 | ||
7977 | case 0x0f7e: /* movd */ | |
7978 | case 0x660f7e: /* movd */ | |
7979 | if (i386_record_modrm (&ir)) | |
7980 | return -1; | |
7981 | if (ir.mod == 3) | |
25ea693b | 7982 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
a3c4230a HZ |
7983 | else |
7984 | { | |
7985 | if (ir.dflag == 2) | |
7986 | ir.ot = OT_QUAD; | |
7987 | else | |
7988 | ir.ot = OT_LONG; | |
7989 | if (i386_record_lea_modrm (&ir)) | |
7990 | return -1; | |
7991 | } | |
7992 | break; | |
7993 | ||
7994 | case 0x0f7f: /* movq */ | |
7995 | if (i386_record_modrm (&ir)) | |
7996 | return -1; | |
7997 | if (ir.mod == 3) | |
7998 | { | |
7999 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8000 | goto no_support; | |
25ea693b MM |
8001 | record_full_arch_list_add_reg (ir.regcache, |
8002 | I387_MM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8003 | } |
8004 | else | |
8005 | { | |
8006 | ir.ot = OT_QUAD; | |
8007 | if (i386_record_lea_modrm (&ir)) | |
8008 | return -1; | |
8009 | } | |
8010 | break; | |
8011 | ||
8012 | case 0xf30fb8: /* popcnt */ | |
8013 | if (i386_record_modrm (&ir)) | |
8014 | return -1; | |
25ea693b MM |
8015 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8016 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
a3c4230a HZ |
8017 | break; |
8018 | ||
8019 | case 0x660fd6: /* movq */ | |
8020 | if (i386_record_modrm (&ir)) | |
8021 | return -1; | |
8022 | if (ir.mod == 3) | |
8023 | { | |
8024 | ir.rm |= ir.rex_b; | |
1777feb0 MS |
8025 | if (!i386_xmm_regnum_p (gdbarch, |
8026 | I387_XMM0_REGNUM (tdep) + ir.rm)) | |
a3c4230a | 8027 | goto no_support; |
25ea693b MM |
8028 | record_full_arch_list_add_reg (ir.regcache, |
8029 | I387_XMM0_REGNUM (tdep) + ir.rm); | |
a3c4230a HZ |
8030 | } |
8031 | else | |
8032 | { | |
8033 | ir.ot = OT_QUAD; | |
8034 | if (i386_record_lea_modrm (&ir)) | |
8035 | return -1; | |
8036 | } | |
8037 | break; | |
8038 | ||
8039 | case 0x660f3817: /* ptest */ | |
8040 | case 0x0f2e: /* ucomiss */ | |
8041 | case 0x660f2e: /* ucomisd */ | |
8042 | case 0x0f2f: /* comiss */ | |
8043 | case 0x660f2f: /* comisd */ | |
25ea693b | 8044 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
8045 | break; |
8046 | ||
8047 | case 0x0ff7: /* maskmovq */ | |
8048 | regcache_raw_read_unsigned (ir.regcache, | |
8049 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8050 | &addr); | |
25ea693b | 8051 | if (record_full_arch_list_add_mem (addr, 64)) |
a3c4230a HZ |
8052 | return -1; |
8053 | break; | |
8054 | ||
8055 | case 0x660ff7: /* maskmovdqu */ | |
8056 | regcache_raw_read_unsigned (ir.regcache, | |
8057 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8058 | &addr); | |
25ea693b | 8059 | if (record_full_arch_list_add_mem (addr, 128)) |
a3c4230a HZ |
8060 | return -1; |
8061 | break; | |
8062 | ||
8063 | default: | |
8064 | goto no_support; | |
8065 | break; | |
8066 | } | |
8067 | break; | |
7ad10968 HZ |
8068 | |
8069 | default: | |
7ad10968 HZ |
8070 | goto no_support; |
8071 | break; | |
8072 | } | |
8073 | ||
cf648174 | 8074 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8075 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8076 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8077 | return -1; |
8078 | ||
8079 | return 0; | |
8080 | ||
01fe1b41 | 8081 | no_support: |
a3c4230a HZ |
8082 | printf_unfiltered (_("Process record does not support instruction 0x%02x " |
8083 | "at address %s.\n"), | |
8084 | (unsigned int) (opcode), | |
8085 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8086 | return -1; |
8087 | } | |
8088 | ||
cf648174 HZ |
8089 | static const int i386_record_regmap[] = |
8090 | { | |
8091 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8092 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8093 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8094 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8095 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8096 | }; | |
8097 | ||
7a697b8d | 8098 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8099 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8100 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8101 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8102 | middle of the tracepoint jump. On x86, it may be possible to use |
8103 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8104 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8105 | of instruction to replace, and 0 if not, plus an explanatory |
8106 | string. */ | |
8107 | ||
8108 | static int | |
6b940e6a PL |
8109 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
8110 | char **msg) | |
7a697b8d SS |
8111 | { |
8112 | int len, jumplen; | |
8113 | static struct ui_file *gdb_null = NULL; | |
8114 | ||
405f8e94 SS |
8115 | /* Ask the target for the minimum instruction length supported. */ |
8116 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8117 | ||
8118 | if (jumplen < 0) | |
8119 | { | |
8120 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8121 | operation, assume that fast tracepoints will always be implemented | |
8122 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8123 | jumplen = 5; | |
8124 | } | |
8125 | else if (jumplen == 0) | |
8126 | { | |
8127 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8128 | returns zero, then the IPA has not loaded yet. In this case, | |
8129 | we optimistically assume that truncated 2-byte relative jumps | |
8130 | will be available on x86, and compensate later if this assumption | |
8131 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8132 | jumps will always be used. */ | |
8133 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8134 | } | |
7a697b8d SS |
8135 | |
8136 | /* Dummy file descriptor for the disassembler. */ | |
8137 | if (!gdb_null) | |
8138 | gdb_null = ui_file_new (); | |
8139 | ||
8140 | /* Check for fit. */ | |
8141 | len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); | |
405f8e94 | 8142 | |
7a697b8d SS |
8143 | if (len < jumplen) |
8144 | { | |
8145 | /* Return a bit of target-specific detail to add to the caller's | |
8146 | generic failure message. */ | |
8147 | if (msg) | |
1777feb0 MS |
8148 | *msg = xstrprintf (_("; instruction is only %d bytes long, " |
8149 | "need at least %d bytes for the jump"), | |
7a697b8d SS |
8150 | len, jumplen); |
8151 | return 0; | |
8152 | } | |
405f8e94 SS |
8153 | else |
8154 | { | |
8155 | if (msg) | |
8156 | *msg = NULL; | |
8157 | return 1; | |
8158 | } | |
7a697b8d SS |
8159 | } |
8160 | ||
00d5215e UW |
8161 | /* Return a floating-point format for a floating-point variable of |
8162 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8163 | If no suitable type is found, return NULL. */ | |
8164 | ||
8165 | const struct floatformat ** | |
8166 | i386_floatformat_for_type (struct gdbarch *gdbarch, | |
8167 | const char *name, int len) | |
8168 | { | |
8169 | if (len == 128 && name) | |
8170 | if (strcmp (name, "__float128") == 0 | |
8171 | || strcmp (name, "_Float128") == 0 | |
8172 | || strcmp (name, "complex _Float128") == 0) | |
8173 | return floatformats_ia64_quad; | |
8174 | ||
8175 | return default_floatformat_for_type (gdbarch, name, len); | |
8176 | } | |
8177 | ||
90884b2b L |
8178 | static int |
8179 | i386_validate_tdesc_p (struct gdbarch_tdep *tdep, | |
8180 | struct tdesc_arch_data *tdesc_data) | |
8181 | { | |
8182 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8183 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8184 | |
8185 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
8186 | *feature_avx512; | |
90884b2b L |
8187 | int i, num_regs, valid_p; |
8188 | ||
8189 | if (! tdesc_has_registers (tdesc)) | |
8190 | return 0; | |
8191 | ||
8192 | /* Get core registers. */ | |
8193 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8194 | if (feature_core == NULL) |
8195 | return 0; | |
90884b2b L |
8196 | |
8197 | /* Get SSE registers. */ | |
c131fcee | 8198 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8199 | |
c131fcee L |
8200 | /* Try AVX registers. */ |
8201 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8202 | ||
1dbcd68c WT |
8203 | /* Try MPX registers. */ |
8204 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8205 | ||
01f9f808 MS |
8206 | /* Try AVX512 registers. */ |
8207 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8208 | ||
90884b2b L |
8209 | valid_p = 1; |
8210 | ||
c131fcee | 8211 | /* The XCR0 bits. */ |
01f9f808 MS |
8212 | if (feature_avx512) |
8213 | { | |
8214 | /* AVX512 register description requires AVX register description. */ | |
8215 | if (!feature_avx) | |
8216 | return 0; | |
8217 | ||
df7e5265 | 8218 | tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK; |
01f9f808 MS |
8219 | |
8220 | /* It may have been set by OSABI initialization function. */ | |
8221 | if (tdep->k0_regnum < 0) | |
8222 | { | |
8223 | tdep->k_register_names = i386_k_names; | |
8224 | tdep->k0_regnum = I386_K0_REGNUM; | |
8225 | } | |
8226 | ||
8227 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8228 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8229 | tdep->k0_regnum + i, | |
8230 | i386_k_names[i]); | |
8231 | ||
8232 | if (tdep->num_zmm_regs == 0) | |
8233 | { | |
8234 | tdep->zmmh_register_names = i386_zmmh_names; | |
8235 | tdep->num_zmm_regs = 8; | |
8236 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8237 | } | |
8238 | ||
8239 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8240 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8241 | tdep->zmm0h_regnum + i, | |
8242 | tdep->zmmh_register_names[i]); | |
8243 | ||
8244 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8245 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8246 | tdep->xmm16_regnum + i, | |
8247 | tdep->xmm_avx512_register_names[i]); | |
8248 | ||
8249 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8250 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8251 | tdep->ymm16h_regnum + i, | |
8252 | tdep->ymm16h_register_names[i]); | |
8253 | } | |
c131fcee L |
8254 | if (feature_avx) |
8255 | { | |
3a13a53b L |
8256 | /* AVX register description requires SSE register description. */ |
8257 | if (!feature_sse) | |
8258 | return 0; | |
8259 | ||
01f9f808 | 8260 | if (!feature_avx512) |
df7e5265 | 8261 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8262 | |
8263 | /* It may have been set by OSABI initialization function. */ | |
8264 | if (tdep->num_ymm_regs == 0) | |
8265 | { | |
8266 | tdep->ymmh_register_names = i386_ymmh_names; | |
8267 | tdep->num_ymm_regs = 8; | |
8268 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8269 | } | |
8270 | ||
8271 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8272 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8273 | tdep->ymm0h_regnum + i, | |
8274 | tdep->ymmh_register_names[i]); | |
8275 | } | |
3a13a53b | 8276 | else if (feature_sse) |
df7e5265 | 8277 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8278 | else |
8279 | { | |
df7e5265 | 8280 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8281 | tdep->num_xmm_regs = 0; |
8282 | } | |
c131fcee | 8283 | |
90884b2b L |
8284 | num_regs = tdep->num_core_regs; |
8285 | for (i = 0; i < num_regs; i++) | |
8286 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8287 | tdep->register_names[i]); | |
8288 | ||
3a13a53b L |
8289 | if (feature_sse) |
8290 | { | |
8291 | /* Need to include %mxcsr, so add one. */ | |
8292 | num_regs += tdep->num_xmm_regs + 1; | |
8293 | for (; i < num_regs; i++) | |
8294 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8295 | tdep->register_names[i]); | |
8296 | } | |
90884b2b | 8297 | |
1dbcd68c WT |
8298 | if (feature_mpx) |
8299 | { | |
df7e5265 | 8300 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8301 | |
8302 | if (tdep->bnd0r_regnum < 0) | |
8303 | { | |
8304 | tdep->mpx_register_names = i386_mpx_names; | |
8305 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8306 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8307 | } | |
8308 | ||
8309 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8310 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8311 | I387_BND0R_REGNUM (tdep) + i, | |
8312 | tdep->mpx_register_names[i]); | |
8313 | } | |
8314 | ||
90884b2b L |
8315 | return valid_p; |
8316 | } | |
8317 | ||
7ad10968 | 8318 | \f |
ad9eb1fd DE |
8319 | /* Note: This is called for both i386 and amd64. */ |
8320 | ||
7ad10968 HZ |
8321 | static struct gdbarch * |
8322 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8323 | { | |
8324 | struct gdbarch_tdep *tdep; | |
8325 | struct gdbarch *gdbarch; | |
90884b2b L |
8326 | struct tdesc_arch_data *tdesc_data; |
8327 | const struct target_desc *tdesc; | |
1ba53b71 | 8328 | int mm0_regnum; |
c131fcee | 8329 | int ymm0_regnum; |
1dbcd68c WT |
8330 | int bnd0_regnum; |
8331 | int num_bnd_cooked; | |
7ad10968 HZ |
8332 | |
8333 | /* If there is already a candidate, use it. */ | |
8334 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8335 | if (arches != NULL) | |
8336 | return arches->gdbarch; | |
8337 | ||
ad9eb1fd | 8338 | /* Allocate space for the new architecture. Assume i386 for now. */ |
fc270c35 | 8339 | tdep = XCNEW (struct gdbarch_tdep); |
7ad10968 HZ |
8340 | gdbarch = gdbarch_alloc (&info, tdep); |
8341 | ||
8342 | /* General-purpose registers. */ | |
7ad10968 HZ |
8343 | tdep->gregset_reg_offset = NULL; |
8344 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8345 | tdep->sizeof_gregset = 0; | |
8346 | ||
8347 | /* Floating-point registers. */ | |
7ad10968 | 8348 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8349 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8350 | |
8351 | /* The default settings include the FPU registers, the MMX registers | |
8352 | and the SSE registers. This can be overridden for a specific ABI | |
8353 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8354 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8355 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8356 | |
8357 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8358 | ||
7ad10968 HZ |
8359 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8360 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8361 | ||
8362 | tdep->jb_pc_offset = -1; | |
8363 | tdep->struct_return = pcc_struct_return; | |
8364 | tdep->sigtramp_start = 0; | |
8365 | tdep->sigtramp_end = 0; | |
8366 | tdep->sigtramp_p = i386_sigtramp_p; | |
8367 | tdep->sigcontext_addr = NULL; | |
8368 | tdep->sc_reg_offset = NULL; | |
8369 | tdep->sc_pc_offset = -1; | |
8370 | tdep->sc_sp_offset = -1; | |
8371 | ||
c131fcee L |
8372 | tdep->xsave_xcr0_offset = -1; |
8373 | ||
cf648174 HZ |
8374 | tdep->record_regmap = i386_record_regmap; |
8375 | ||
205c306f DM |
8376 | set_gdbarch_long_long_align_bit (gdbarch, 32); |
8377 | ||
7ad10968 HZ |
8378 | /* The format used for `long double' on almost all i386 targets is |
8379 | the i387 extended floating-point format. In fact, of all targets | |
8380 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8381 | on having a `long double' that's not `long' at all. */ | |
8382 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8383 | ||
8384 | /* Although the i387 extended floating-point has only 80 significant | |
8385 | bits, a `long double' actually takes up 96, probably to enforce | |
8386 | alignment. */ | |
8387 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8388 | ||
00d5215e UW |
8389 | /* Support for floating-point data type variants. */ |
8390 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8391 | ||
7ad10968 HZ |
8392 | /* Register numbers of various important registers. */ |
8393 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8394 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8395 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8396 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8397 | ||
8398 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8399 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8400 | differ in how they number %ebp, %esp, %eflags, and the | |
8401 | floating-point registers, and are implemented by the arrays | |
8402 | dbx_register_map[] and svr4_dbx_register_map in | |
8403 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8404 | gcc/config/i386.c, which it designates as the "default" register | |
8405 | map used in 64bit mode. This last register numbering scheme is | |
8406 | implemented in dbx64_register_map, and is used for AMD64; see | |
8407 | amd64-tdep.c. | |
8408 | ||
8409 | Currently, each GCC i386 target always uses the same register | |
8410 | numbering scheme across all its supported debugging formats | |
8411 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8412 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8413 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8414 | respective config header in a manner independent of the requested | |
8415 | output debugging format. | |
8416 | ||
8417 | This does not match the arrangement below, which presumes that | |
8418 | the SDB and stabs numbering schemes differ from the DWARF and | |
8419 | DWARF 2 ones. The reason for this arrangement is that it is | |
8420 | likely to get the numbering scheme for the target's | |
8421 | default/native debug format right. For targets where GCC is the | |
8422 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8423 | targets where the native toolchain uses a different numbering | |
8424 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8425 | the defaults below will have to be overridden, like | |
8426 | i386_elf_init_abi() does. */ | |
8427 | ||
8428 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8429 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8430 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8431 | ||
8432 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8433 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8434 | |
8435 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8436 | be in use on any of the supported i386 targets. */ | |
8437 | ||
8438 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8439 | ||
8440 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8441 | ||
8442 | /* Call dummy code. */ | |
a9b8d892 JK |
8443 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8444 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8445 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8446 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8447 | |
8448 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8449 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8450 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8451 | ||
8452 | set_gdbarch_return_value (gdbarch, i386_return_value); | |
8453 | ||
8454 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8455 | ||
8456 | /* Stack grows downward. */ | |
8457 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8458 | ||
04180708 YQ |
8459 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8460 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8461 | ||
7ad10968 HZ |
8462 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8463 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8464 | ||
8465 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8466 | ||
7ad10968 HZ |
8467 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8468 | ||
8469 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8470 | ||
8471 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8472 | ||
8473 | /* Add the i386 register groups. */ | |
8474 | i386_add_reggroups (gdbarch); | |
90884b2b | 8475 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8476 | |
143985b7 AF |
8477 | /* Helper for function argument information. */ |
8478 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8479 | ||
06da04c6 | 8480 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8481 | appended to the list first, so that it supercedes the DWARF |
8482 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 MS |
8483 | currently fails). */ |
8484 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
8485 | ||
8486 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8487 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8488 | CFI info will be used if it is available. */ |
10458914 | 8489 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8490 | |
acd5c798 | 8491 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8492 | |
1ba53b71 | 8493 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8494 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8495 | i386_pseudo_register_read_value); | |
90884b2b | 8496 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8497 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8498 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8499 | |
8500 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8501 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8502 | ||
c131fcee L |
8503 | /* Override the normal target description method to make the AVX |
8504 | upper halves anonymous. */ | |
8505 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8506 | ||
8507 | /* Even though the default ABI only includes general-purpose registers, | |
8508 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 MS |
8509 | gap for the upper AVX, MPX and AVX512 registers. */ |
8510 | set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS); | |
90884b2b | 8511 | |
ac04f72b TT |
8512 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8513 | ||
90884b2b L |
8514 | /* Get the x86 target description from INFO. */ |
8515 | tdesc = info.target_desc; | |
8516 | if (! tdesc_has_registers (tdesc)) | |
8517 | tdesc = tdesc_i386; | |
8518 | tdep->tdesc = tdesc; | |
8519 | ||
8520 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8521 | tdep->register_names = i386_register_names; | |
8522 | ||
c131fcee L |
8523 | /* No upper YMM registers. */ |
8524 | tdep->ymmh_register_names = NULL; | |
8525 | tdep->ymm0h_regnum = -1; | |
8526 | ||
01f9f808 MS |
8527 | /* No upper ZMM registers. */ |
8528 | tdep->zmmh_register_names = NULL; | |
8529 | tdep->zmm0h_regnum = -1; | |
8530 | ||
8531 | /* No high XMM registers. */ | |
8532 | tdep->xmm_avx512_register_names = NULL; | |
8533 | tdep->xmm16_regnum = -1; | |
8534 | ||
8535 | /* No upper YMM16-31 registers. */ | |
8536 | tdep->ymm16h_register_names = NULL; | |
8537 | tdep->ymm16h_regnum = -1; | |
8538 | ||
1ba53b71 L |
8539 | tdep->num_byte_regs = 8; |
8540 | tdep->num_word_regs = 8; | |
8541 | tdep->num_dword_regs = 0; | |
8542 | tdep->num_mmx_regs = 8; | |
c131fcee | 8543 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8544 | |
1dbcd68c WT |
8545 | /* No MPX registers. */ |
8546 | tdep->bnd0r_regnum = -1; | |
8547 | tdep->bndcfgu_regnum = -1; | |
8548 | ||
01f9f808 MS |
8549 | /* No AVX512 registers. */ |
8550 | tdep->k0_regnum = -1; | |
8551 | tdep->num_zmm_regs = 0; | |
8552 | tdep->num_ymm_avx512_regs = 0; | |
8553 | tdep->num_xmm_avx512_regs = 0; | |
8554 | ||
90884b2b L |
8555 | tdesc_data = tdesc_data_alloc (); |
8556 | ||
dde08ee1 PA |
8557 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8558 | ||
6710bf39 SS |
8559 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8560 | ||
c2170eef MM |
8561 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8562 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8563 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8564 | ||
ad9eb1fd DE |
8565 | /* Hook in ABI-specific overrides, if they have been registered. |
8566 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8567 | a 32-bit i386 into a 64-bit amd64. */ | |
ede5f151 | 8568 | info.tdep_info = tdesc_data; |
4be87837 | 8569 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8570 | |
c131fcee L |
8571 | if (!i386_validate_tdesc_p (tdep, tdesc_data)) |
8572 | { | |
8573 | tdesc_data_cleanup (tdesc_data); | |
8574 | xfree (tdep); | |
8575 | gdbarch_free (gdbarch); | |
8576 | return NULL; | |
8577 | } | |
8578 | ||
1dbcd68c WT |
8579 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8580 | ||
1ba53b71 L |
8581 | /* Wire in pseudo registers. Number of pseudo registers may be |
8582 | changed. */ | |
8583 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8584 | + tdep->num_word_regs | |
8585 | + tdep->num_dword_regs | |
c131fcee | 8586 | + tdep->num_mmx_regs |
1dbcd68c | 8587 | + tdep->num_ymm_regs |
01f9f808 MS |
8588 | + num_bnd_cooked |
8589 | + tdep->num_ymm_avx512_regs | |
8590 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8591 | |
90884b2b L |
8592 | /* Target description may be changed. */ |
8593 | tdesc = tdep->tdesc; | |
8594 | ||
90884b2b L |
8595 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); |
8596 | ||
8597 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8598 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8599 | ||
1ba53b71 L |
8600 | /* Make %al the first pseudo-register. */ |
8601 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8602 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8603 | ||
c131fcee | 8604 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8605 | if (tdep->num_dword_regs) |
8606 | { | |
1c6272a6 | 8607 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8608 | tdep->eax_regnum = ymm0_regnum; |
8609 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8610 | } |
8611 | else | |
8612 | tdep->eax_regnum = -1; | |
8613 | ||
c131fcee L |
8614 | mm0_regnum = ymm0_regnum; |
8615 | if (tdep->num_ymm_regs) | |
8616 | { | |
1c6272a6 | 8617 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8618 | tdep->ymm0_regnum = ymm0_regnum; |
8619 | mm0_regnum += tdep->num_ymm_regs; | |
8620 | } | |
8621 | else | |
8622 | tdep->ymm0_regnum = -1; | |
8623 | ||
01f9f808 MS |
8624 | if (tdep->num_ymm_avx512_regs) |
8625 | { | |
8626 | /* Support YMM16-31 pseudo registers if available. */ | |
8627 | tdep->ymm16_regnum = mm0_regnum; | |
8628 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8629 | } | |
8630 | else | |
8631 | tdep->ymm16_regnum = -1; | |
8632 | ||
8633 | if (tdep->num_zmm_regs) | |
8634 | { | |
8635 | /* Support ZMM pseudo-register if it is available. */ | |
8636 | tdep->zmm0_regnum = mm0_regnum; | |
8637 | mm0_regnum += tdep->num_zmm_regs; | |
8638 | } | |
8639 | else | |
8640 | tdep->zmm0_regnum = -1; | |
8641 | ||
1dbcd68c | 8642 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8643 | if (tdep->num_mmx_regs != 0) |
8644 | { | |
1c6272a6 | 8645 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8646 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8647 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8648 | } |
8649 | else | |
8650 | tdep->mm0_regnum = -1; | |
8651 | ||
1dbcd68c WT |
8652 | if (tdep->bnd0r_regnum > 0) |
8653 | tdep->bnd0_regnum = bnd0_regnum; | |
8654 | else | |
8655 | tdep-> bnd0_regnum = -1; | |
8656 | ||
06da04c6 | 8657 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
a3fcb948 | 8658 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); |
10458914 DJ |
8659 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); |
8660 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
acd5c798 | 8661 | |
8446b36a MK |
8662 | /* If we have a register mapping, enable the generic core file |
8663 | support, unless it has already been enabled. */ | |
8664 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8665 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8666 | set_gdbarch_iterate_over_regset_sections |
8667 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8668 | |
7a697b8d SS |
8669 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8670 | i386_fast_tracepoint_valid_at); | |
8671 | ||
a62cc96e AC |
8672 | return gdbarch; |
8673 | } | |
8674 | ||
8201327c MK |
8675 | static enum gdb_osabi |
8676 | i386_coff_osabi_sniffer (bfd *abfd) | |
8677 | { | |
762c5349 MK |
8678 | if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 |
8679 | || strcmp (bfd_get_target (abfd), "coff-go32") == 0) | |
8201327c MK |
8680 | return GDB_OSABI_GO32; |
8681 | ||
8682 | return GDB_OSABI_UNKNOWN; | |
8683 | } | |
8201327c MK |
8684 | \f |
8685 | ||
97de3545 JB |
8686 | /* Return the target description for a specified XSAVE feature mask. */ |
8687 | ||
8688 | const struct target_desc * | |
8689 | i386_target_description (uint64_t xcr0) | |
8690 | { | |
8691 | switch (xcr0 & X86_XSTATE_ALL_MASK) | |
8692 | { | |
8693 | case X86_XSTATE_MPX_AVX512_MASK: | |
8694 | case X86_XSTATE_AVX512_MASK: | |
8695 | return tdesc_i386_avx512; | |
2b863f51 WT |
8696 | case X86_XSTATE_AVX_MPX_MASK: |
8697 | return tdesc_i386_avx_mpx; | |
97de3545 JB |
8698 | case X86_XSTATE_MPX_MASK: |
8699 | return tdesc_i386_mpx; | |
8700 | case X86_XSTATE_AVX_MASK: | |
8701 | return tdesc_i386_avx; | |
8702 | default: | |
8703 | return tdesc_i386; | |
8704 | } | |
8705 | } | |
8706 | ||
29c1c244 WT |
8707 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8708 | ||
8709 | /* Find the bound directory base address. */ | |
8710 | ||
8711 | static unsigned long | |
8712 | i386_mpx_bd_base (void) | |
8713 | { | |
8714 | struct regcache *rcache; | |
8715 | struct gdbarch_tdep *tdep; | |
8716 | ULONGEST ret; | |
8717 | enum register_status regstatus; | |
29c1c244 WT |
8718 | |
8719 | rcache = get_current_regcache (); | |
8720 | tdep = gdbarch_tdep (get_regcache_arch (rcache)); | |
8721 | ||
8722 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8723 | ||
8724 | if (regstatus != REG_VALID) | |
8725 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8726 | ||
8727 | return ret & MPX_BASE_MASK; | |
8728 | } | |
8729 | ||
012b3a21 | 8730 | int |
29c1c244 WT |
8731 | i386_mpx_enabled (void) |
8732 | { | |
8733 | const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); | |
8734 | const struct target_desc *tdesc = tdep->tdesc; | |
8735 | ||
8736 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8737 | } | |
8738 | ||
8739 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8740 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8741 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8742 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8743 | ||
8744 | /* Find the bound table entry given the pointer location and the base | |
8745 | address of the table. */ | |
8746 | ||
8747 | static CORE_ADDR | |
8748 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8749 | { | |
8750 | CORE_ADDR offset1; | |
8751 | CORE_ADDR offset2; | |
8752 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8753 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8754 | CORE_ADDR bd_entry_addr; | |
8755 | CORE_ADDR bt_addr; | |
8756 | CORE_ADDR bd_entry; | |
8757 | struct gdbarch *gdbarch = get_current_arch (); | |
8758 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8759 | ||
8760 | ||
8761 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8762 | { | |
966f0aef | 8763 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8764 | bd_ptr_r_shift = 20; |
8765 | bd_ptr_l_shift = 3; | |
8766 | bt_select_r_shift = 3; | |
8767 | bt_select_l_shift = 5; | |
966f0aef WT |
8768 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8769 | ||
8770 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8771 | error (_("bound table examination not supported\ |
8772 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8773 | } |
8774 | else | |
8775 | { | |
8776 | mpx_bd_mask = MPX_BD_MASK_32; | |
8777 | bd_ptr_r_shift = 12; | |
8778 | bd_ptr_l_shift = 2; | |
8779 | bt_select_r_shift = 2; | |
8780 | bt_select_l_shift = 4; | |
8781 | bt_mask = MPX_BT_MASK_32; | |
8782 | } | |
8783 | ||
8784 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8785 | bd_entry_addr = bd_base + offset1; | |
8786 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8787 | ||
8788 | if ((bd_entry & 0x1) == 0) | |
8789 | error (_("Invalid bounds directory entry at %s."), | |
8790 | paddress (get_current_arch (), bd_entry_addr)); | |
8791 | ||
8792 | /* Clearing status bit. */ | |
8793 | bd_entry--; | |
8794 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8795 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8796 | ||
8797 | return bt_addr + offset2; | |
8798 | } | |
8799 | ||
8800 | /* Print routine for the mpx bounds. */ | |
8801 | ||
8802 | static void | |
8803 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8804 | { | |
8805 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8806 | LONGEST size; |
29c1c244 WT |
8807 | struct gdbarch *gdbarch = get_current_arch (); |
8808 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8809 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8810 | ||
8811 | if (bounds_in_map == 1) | |
8812 | { | |
112e8700 SM |
8813 | uiout->text ("Null bounds on map:"); |
8814 | uiout->text (" pointer value = "); | |
8815 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8816 | uiout->text ("."); | |
8817 | uiout->text ("\n"); | |
29c1c244 WT |
8818 | } |
8819 | else | |
8820 | { | |
112e8700 SM |
8821 | uiout->text ("{lbound = "); |
8822 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8823 | uiout->text (", ubound = "); | |
29c1c244 WT |
8824 | |
8825 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8826 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8827 | uiout->text ("}: pointer value = "); | |
8828 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8829 | |
8830 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8831 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8832 | else | |
8833 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8834 | ||
8835 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8836 | -1 represents in this sense full memory access, and there is no need | |
8837 | one to the size. */ | |
8838 | ||
8839 | size = (size > -1 ? size + 1 : size); | |
112e8700 SM |
8840 | uiout->text (", size = "); |
8841 | uiout->field_fmt ("size", "%s", plongest (size)); | |
29c1c244 | 8842 | |
112e8700 SM |
8843 | uiout->text (", metadata = "); |
8844 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8845 | uiout->text ("\n"); | |
29c1c244 WT |
8846 | } |
8847 | } | |
8848 | ||
8849 | /* Implement the command "show mpx bound". */ | |
8850 | ||
8851 | static void | |
8852 | i386_mpx_info_bounds (char *args, int from_tty) | |
8853 | { | |
8854 | CORE_ADDR bd_base = 0; | |
8855 | CORE_ADDR addr; | |
8856 | CORE_ADDR bt_entry_addr = 0; | |
8857 | CORE_ADDR bt_entry[4]; | |
8858 | int i; | |
8859 | struct gdbarch *gdbarch = get_current_arch (); | |
8860 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8861 | ||
ae71e7b5 MR |
8862 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8863 | || !i386_mpx_enabled ()) | |
118ca224 | 8864 | { |
bc504a31 | 8865 | printf_unfiltered (_("Intel Memory Protection Extensions not " |
118ca224 PP |
8866 | "supported on this target.\n")); |
8867 | return; | |
8868 | } | |
29c1c244 WT |
8869 | |
8870 | if (args == NULL) | |
118ca224 PP |
8871 | { |
8872 | printf_unfiltered (_("Address of pointer variable expected.\n")); | |
8873 | return; | |
8874 | } | |
29c1c244 WT |
8875 | |
8876 | addr = parse_and_eval_address (args); | |
8877 | ||
8878 | bd_base = i386_mpx_bd_base (); | |
8879 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8880 | ||
8881 | memset (bt_entry, 0, sizeof (bt_entry)); | |
8882 | ||
8883 | for (i = 0; i < 4; i++) | |
8884 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8885 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8886 | data_ptr_type); |
8887 | ||
8888 | i386_mpx_print_bounds (bt_entry); | |
8889 | } | |
8890 | ||
8891 | /* Implement the command "set mpx bound". */ | |
8892 | ||
8893 | static void | |
8894 | i386_mpx_set_bounds (char *args, int from_tty) | |
8895 | { | |
8896 | CORE_ADDR bd_base = 0; | |
8897 | CORE_ADDR addr, lower, upper; | |
8898 | CORE_ADDR bt_entry_addr = 0; | |
8899 | CORE_ADDR bt_entry[2]; | |
8900 | const char *input = args; | |
8901 | int i; | |
8902 | struct gdbarch *gdbarch = get_current_arch (); | |
8903 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
8904 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8905 | ||
ae71e7b5 MR |
8906 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8907 | || !i386_mpx_enabled ()) | |
bc504a31 | 8908 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
8909 | on this target.")); |
8910 | ||
8911 | if (args == NULL) | |
8912 | error (_("Pointer value expected.")); | |
8913 | ||
8914 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
8915 | ||
8916 | if (input[0] == ',') | |
8917 | ++input; | |
8918 | if (input[0] == '\0') | |
8919 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
8920 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
8921 | ||
8922 | if (input[0] == ',') | |
8923 | ++input; | |
8924 | if (input[0] == '\0') | |
8925 | error (_("Wrong number of arguments; Missing upper bound.")); | |
8926 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
8927 | ||
8928 | bd_base = i386_mpx_bd_base (); | |
8929 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
8930 | for (i = 0; i < 2; i++) | |
8931 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
132874d7 | 8932 | + i * TYPE_LENGTH (data_ptr_type), |
29c1c244 WT |
8933 | data_ptr_type); |
8934 | bt_entry[0] = (uint64_t) lower; | |
8935 | bt_entry[1] = ~(uint64_t) upper; | |
8936 | ||
8937 | for (i = 0; i < 2; i++) | |
132874d7 AB |
8938 | write_memory_unsigned_integer (bt_entry_addr |
8939 | + i * TYPE_LENGTH (data_ptr_type), | |
8940 | TYPE_LENGTH (data_ptr_type), byte_order, | |
29c1c244 WT |
8941 | bt_entry[i]); |
8942 | } | |
8943 | ||
8944 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
8945 | ||
8946 | /* Helper function for the CLI commands. */ | |
8947 | ||
8948 | static void | |
8949 | set_mpx_cmd (char *args, int from_tty) | |
8950 | { | |
118ca224 | 8951 | help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout); |
29c1c244 WT |
8952 | } |
8953 | ||
8954 | /* Helper function for the CLI commands. */ | |
8955 | ||
8956 | static void | |
8957 | show_mpx_cmd (char *args, int from_tty) | |
8958 | { | |
8959 | cmd_show_list (mpx_show_cmdlist, from_tty, ""); | |
8960 | } | |
8961 | ||
28e9e0f0 MK |
8962 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
8963 | void _initialize_i386_tdep (void); | |
8964 | ||
c906108c | 8965 | void |
fba45db2 | 8966 | _initialize_i386_tdep (void) |
c906108c | 8967 | { |
a62cc96e AC |
8968 | register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); |
8969 | ||
fc338970 | 8970 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
8971 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
8972 | &disassembly_flavor, _("\ | |
8973 | Set the disassembly flavor."), _("\ | |
8974 | Show the disassembly flavor."), _("\ | |
8975 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
8976 | NULL, | |
8977 | NULL, /* FIXME: i18n: */ | |
8978 | &setlist, &showlist); | |
8201327c MK |
8979 | |
8980 | /* Add the variable that controls the convention for returning | |
8981 | structs. */ | |
7ab04401 AC |
8982 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
8983 | &struct_convention, _("\ | |
8984 | Set the convention for returning small structs."), _("\ | |
8985 | Show the convention for returning small structs."), _("\ | |
8986 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
8987 | is \"default\"."), | |
8988 | NULL, | |
8989 | NULL, /* FIXME: i18n: */ | |
8990 | &setlist, &showlist); | |
8201327c | 8991 | |
29c1c244 WT |
8992 | /* Add "mpx" prefix for the set commands. */ |
8993 | ||
8994 | add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\ | |
bc504a31 | 8995 | Set Intel Memory Protection Extensions specific variables."), |
118ca224 | 8996 | &mpx_set_cmdlist, "set mpx ", |
29c1c244 WT |
8997 | 0 /* allow-unknown */, &setlist); |
8998 | ||
8999 | /* Add "mpx" prefix for the show commands. */ | |
9000 | ||
9001 | add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\ | |
bc504a31 | 9002 | Show Intel Memory Protection Extensions specific variables."), |
29c1c244 WT |
9003 | &mpx_show_cmdlist, "show mpx ", |
9004 | 0 /* allow-unknown */, &showlist); | |
9005 | ||
9006 | /* Add "bound" command for the show mpx commands list. */ | |
9007 | ||
9008 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9009 | "Show the memory bounds for a given array/pointer storage\ | |
9010 | in the bound table.", | |
9011 | &mpx_show_cmdlist); | |
9012 | ||
9013 | /* Add "bound" command for the set mpx commands list. */ | |
9014 | ||
9015 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9016 | "Set the memory bounds for a given array/pointer storage\ | |
9017 | in the bound table.", | |
9018 | &mpx_set_cmdlist); | |
9019 | ||
8201327c MK |
9020 | gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, |
9021 | i386_coff_osabi_sniffer); | |
8201327c | 9022 | |
05816f70 | 9023 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9024 | i386_svr4_init_abi); |
05816f70 | 9025 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, |
8201327c | 9026 | i386_go32_init_abi); |
38c968cf | 9027 | |
209bd28e | 9028 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9029 | i386_init_reggroups (); |
90884b2b L |
9030 | |
9031 | /* Initialize the standard target descriptions. */ | |
9032 | initialize_tdesc_i386 (); | |
3a13a53b | 9033 | initialize_tdesc_i386_mmx (); |
c131fcee | 9034 | initialize_tdesc_i386_avx (); |
1dbcd68c | 9035 | initialize_tdesc_i386_mpx (); |
2b863f51 | 9036 | initialize_tdesc_i386_avx_mpx (); |
01f9f808 | 9037 | initialize_tdesc_i386_avx512 (); |
c8d5aac9 L |
9038 | |
9039 | /* Tell remote stub that we support XML target description. */ | |
9040 | register_remote_support_xml ("i386"); | |
c906108c | 9041 | } |