2003-07-18 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / i386-tdep.c
CommitLineData
c906108c 1/* Intel 386 target-dependent stuff.
349c5d5f
AC
2
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4be87837 4 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
c906108c 12
c5aa993b
JM
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b
JM
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
c906108c
SS
22
23#include "defs.h"
acd5c798
MK
24#include "arch-utils.h"
25#include "command.h"
26#include "dummy-frame.h"
6405b0a6 27#include "dwarf2-frame.h"
acd5c798
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28#include "doublest.h"
29#include "floatformat.h"
c906108c 30#include "frame.h"
acd5c798
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31#include "frame-base.h"
32#include "frame-unwind.h"
c906108c 33#include "inferior.h"
acd5c798 34#include "gdbcmd.h"
c906108c 35#include "gdbcore.h"
dfe01d39 36#include "objfiles.h"
acd5c798
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37#include "osabi.h"
38#include "regcache.h"
39#include "reggroups.h"
c0d1d883 40#include "symfile.h"
c906108c 41#include "symtab.h"
acd5c798 42#include "target.h"
fd0407d6 43#include "value.h"
acd5c798 44
3d261580 45#include "gdb_assert.h"
acd5c798 46#include "gdb_string.h"
3d261580 47
d2a7c97a 48#include "i386-tdep.h"
61113f8b 49#include "i387-tdep.h"
d2a7c97a 50
fc633446
MK
51/* Names of the registers. The first 10 registers match the register
52 numbering scheme used by GCC for stabs and DWARF. */
c40e1eab 53
fc633446
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54static char *i386_register_names[] =
55{
56 "eax", "ecx", "edx", "ebx",
57 "esp", "ebp", "esi", "edi",
58 "eip", "eflags", "cs", "ss",
59 "ds", "es", "fs", "gs",
60 "st0", "st1", "st2", "st3",
61 "st4", "st5", "st6", "st7",
62 "fctrl", "fstat", "ftag", "fiseg",
63 "fioff", "foseg", "fooff", "fop",
64 "xmm0", "xmm1", "xmm2", "xmm3",
65 "xmm4", "xmm5", "xmm6", "xmm7",
66 "mxcsr"
67};
68
c40e1eab
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69static const int i386_num_register_names =
70 (sizeof (i386_register_names) / sizeof (*i386_register_names));
71
28fc6740
AC
72/* MMX registers. */
73
74static char *i386_mmx_names[] =
75{
76 "mm0", "mm1", "mm2", "mm3",
77 "mm4", "mm5", "mm6", "mm7"
78};
c40e1eab
MK
79
80static const int i386_num_mmx_regs =
81 (sizeof (i386_mmx_names) / sizeof (i386_mmx_names[0]));
82
83#define MM0_REGNUM NUM_REGS
28fc6740
AC
84
85static int
c40e1eab 86i386_mmx_regnum_p (int regnum)
28fc6740 87{
c40e1eab
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88 return (regnum >= MM0_REGNUM
89 && regnum < MM0_REGNUM + i386_num_mmx_regs);
28fc6740
AC
90}
91
23a34459
AC
92/* FP register? */
93
94int
95i386_fp_regnum_p (int regnum)
96{
97 return (regnum < NUM_REGS
c40e1eab 98 && (FP0_REGNUM && FP0_REGNUM <= regnum && regnum < FPC_REGNUM));
23a34459
AC
99}
100
101int
102i386_fpc_regnum_p (int regnum)
103{
104 return (regnum < NUM_REGS
c40e1eab 105 && (FPC_REGNUM <= regnum && regnum < XMM0_REGNUM));
23a34459
AC
106}
107
108/* SSE register? */
109
110int
111i386_sse_regnum_p (int regnum)
112{
113 return (regnum < NUM_REGS
c40e1eab 114 && (XMM0_REGNUM <= regnum && regnum < MXCSR_REGNUM));
23a34459
AC
115}
116
117int
118i386_mxcsr_regnum_p (int regnum)
119{
120 return (regnum < NUM_REGS
c40e1eab 121 && regnum == MXCSR_REGNUM);
23a34459
AC
122}
123
fc633446
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124/* Return the name of register REG. */
125
fa88f677 126const char *
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127i386_register_name (int reg)
128{
23a34459 129 if (i386_mmx_regnum_p (reg))
28fc6740 130 return i386_mmx_names[reg - MM0_REGNUM];
fc633446 131
70913449
MK
132 if (reg >= 0 && reg < i386_num_register_names)
133 return i386_register_names[reg];
134
c40e1eab 135 return NULL;
fc633446
MK
136}
137
85540d8c
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138/* Convert stabs register number REG to the appropriate register
139 number used by GDB. */
140
8201327c 141static int
85540d8c
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142i386_stab_reg_to_regnum (int reg)
143{
144 /* This implements what GCC calls the "default" register map. */
145 if (reg >= 0 && reg <= 7)
146 {
acd5c798 147 /* General-purpose registers. */
85540d8c
MK
148 return reg;
149 }
150 else if (reg >= 12 && reg <= 19)
151 {
152 /* Floating-point registers. */
153 return reg - 12 + FP0_REGNUM;
154 }
155 else if (reg >= 21 && reg <= 28)
156 {
157 /* SSE registers. */
158 return reg - 21 + XMM0_REGNUM;
159 }
160 else if (reg >= 29 && reg <= 36)
161 {
162 /* MMX registers. */
7d12f766 163 return reg - 29 + MM0_REGNUM;
85540d8c
MK
164 }
165
166 /* This will hopefully provoke a warning. */
167 return NUM_REGS + NUM_PSEUDO_REGS;
168}
169
8201327c 170/* Convert DWARF register number REG to the appropriate register
85540d8c
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171 number used by GDB. */
172
8201327c 173static int
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174i386_dwarf_reg_to_regnum (int reg)
175{
176 /* The DWARF register numbering includes %eip and %eflags, and
177 numbers the floating point registers differently. */
178 if (reg >= 0 && reg <= 9)
179 {
acd5c798 180 /* General-purpose registers. */
85540d8c
MK
181 return reg;
182 }
183 else if (reg >= 11 && reg <= 18)
184 {
185 /* Floating-point registers. */
186 return reg - 11 + FP0_REGNUM;
187 }
188 else if (reg >= 21)
189 {
190 /* The SSE and MMX registers have identical numbers as in stabs. */
191 return i386_stab_reg_to_regnum (reg);
192 }
193
194 /* This will hopefully provoke a warning. */
195 return NUM_REGS + NUM_PSEUDO_REGS;
196}
fc338970 197\f
917317f4 198
fc338970
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199/* This is the variable that is set with "set disassembly-flavor", and
200 its legitimate values. */
53904c9e
AC
201static const char att_flavor[] = "att";
202static const char intel_flavor[] = "intel";
203static const char *valid_flavors[] =
c5aa993b 204{
c906108c
SS
205 att_flavor,
206 intel_flavor,
207 NULL
208};
53904c9e 209static const char *disassembly_flavor = att_flavor;
acd5c798 210\f
c906108c 211
acd5c798
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212/* Use the program counter to determine the contents and size of a
213 breakpoint instruction. Return a pointer to a string of bytes that
214 encode a breakpoint instruction, store the length of the string in
215 *LEN and optionally adjust *PC to point to the correct memory
216 location for inserting the breakpoint.
c906108c 217
acd5c798
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218 On the i386 we have a single breakpoint that fits in a single byte
219 and can be inserted anywhere.
c906108c 220
acd5c798
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221 This function is 64-bit safe. */
222
223static const unsigned char *
224i386_breakpoint_from_pc (CORE_ADDR *pc, int *len)
c906108c 225{
acd5c798
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226 static unsigned char break_insn[] = { 0xcc }; /* int 3 */
227
228 *len = sizeof (break_insn);
229 return break_insn;
c906108c 230}
fc338970 231\f
acd5c798
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232#ifdef I386_REGNO_TO_SYMMETRY
233#error "The Sequent Symmetry is no longer supported."
234#endif
c906108c 235
acd5c798
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236/* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
237 and %esp "belong" to the calling function. Therefore these
238 registers should be saved if they're going to be modified. */
c906108c 239
acd5c798
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240/* The maximum number of saved registers. This should include all
241 registers mentioned above, and %eip. */
a3386186 242#define I386_NUM_SAVED_REGS I386_NUM_GREGS
acd5c798
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243
244struct i386_frame_cache
c906108c 245{
acd5c798
MK
246 /* Base address. */
247 CORE_ADDR base;
248 CORE_ADDR sp_offset;
249 CORE_ADDR pc;
250
fd13a04a
AC
251 /* Saved registers. */
252 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
acd5c798
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253 CORE_ADDR saved_sp;
254 int pc_in_eax;
255
256 /* Stack space reserved for local variables. */
257 long locals;
258};
259
260/* Allocate and initialize a frame cache. */
261
262static struct i386_frame_cache *
fd13a04a 263i386_alloc_frame_cache (void)
acd5c798
MK
264{
265 struct i386_frame_cache *cache;
266 int i;
267
268 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
269
270 /* Base address. */
271 cache->base = 0;
272 cache->sp_offset = -4;
273 cache->pc = 0;
274
fd13a04a
AC
275 /* Saved registers. We initialize these to -1 since zero is a valid
276 offset (that's where %ebp is supposed to be stored). */
277 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
278 cache->saved_regs[i] = -1;
acd5c798
MK
279 cache->saved_sp = 0;
280 cache->pc_in_eax = 0;
281
282 /* Frameless until proven otherwise. */
283 cache->locals = -1;
284
285 return cache;
286}
c906108c 287
acd5c798
MK
288/* If the instruction at PC is a jump, return the address of its
289 target. Otherwise, return PC. */
c906108c 290
acd5c798
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291static CORE_ADDR
292i386_follow_jump (CORE_ADDR pc)
293{
294 unsigned char op;
295 long delta = 0;
296 int data16 = 0;
c906108c 297
acd5c798
MK
298 op = read_memory_unsigned_integer (pc, 1);
299 if (op == 0x66)
c906108c 300 {
c906108c 301 data16 = 1;
acd5c798 302 op = read_memory_unsigned_integer (pc + 1, 1);
c906108c
SS
303 }
304
acd5c798 305 switch (op)
c906108c
SS
306 {
307 case 0xe9:
fc338970 308 /* Relative jump: if data16 == 0, disp32, else disp16. */
c906108c
SS
309 if (data16)
310 {
acd5c798 311 delta = read_memory_integer (pc + 2, 2);
c906108c 312
fc338970
MK
313 /* Include the size of the jmp instruction (including the
314 0x66 prefix). */
acd5c798 315 delta += 4;
c906108c
SS
316 }
317 else
318 {
acd5c798 319 delta = read_memory_integer (pc + 1, 4);
c906108c 320
acd5c798
MK
321 /* Include the size of the jmp instruction. */
322 delta += 5;
c906108c
SS
323 }
324 break;
325 case 0xeb:
fc338970 326 /* Relative jump, disp8 (ignore data16). */
acd5c798 327 delta = read_memory_integer (pc + data16 + 1, 1);
c906108c 328
acd5c798 329 delta += data16 + 2;
c906108c
SS
330 break;
331 }
c906108c 332
acd5c798
MK
333 return pc + delta;
334}
fc338970 335
acd5c798
MK
336/* Check whether PC points at a prologue for a function returning a
337 structure or union. If so, it updates CACHE and returns the
338 address of the first instruction after the code sequence that
339 removes the "hidden" argument from the stack or CURRENT_PC,
340 whichever is smaller. Otherwise, return PC. */
c906108c 341
acd5c798
MK
342static CORE_ADDR
343i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
344 struct i386_frame_cache *cache)
c906108c 345{
acd5c798
MK
346 /* Functions that return a structure or union start with:
347
348 popl %eax 0x58
349 xchgl %eax, (%esp) 0x87 0x04 0x24
350 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
351
352 (the System V compiler puts out the second `xchg' instruction,
353 and the assembler doesn't try to optimize it, so the 'sib' form
354 gets generated). This sequence is used to get the address of the
355 return buffer for a function that returns a structure. */
356 static unsigned char proto1[3] = { 0x87, 0x04, 0x24 };
357 static unsigned char proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
358 unsigned char buf[4];
c906108c
SS
359 unsigned char op;
360
acd5c798
MK
361 if (current_pc <= pc)
362 return pc;
363
364 op = read_memory_unsigned_integer (pc, 1);
c906108c 365
acd5c798
MK
366 if (op != 0x58) /* popl %eax */
367 return pc;
c906108c 368
acd5c798
MK
369 read_memory (pc + 1, buf, 4);
370 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
371 return pc;
c906108c 372
acd5c798 373 if (current_pc == pc)
c906108c 374 {
acd5c798
MK
375 cache->sp_offset += 4;
376 return current_pc;
c906108c
SS
377 }
378
acd5c798 379 if (current_pc == pc + 1)
c906108c 380 {
acd5c798
MK
381 cache->pc_in_eax = 1;
382 return current_pc;
383 }
384
385 if (buf[1] == proto1[1])
386 return pc + 4;
387 else
388 return pc + 5;
389}
390
391static CORE_ADDR
392i386_skip_probe (CORE_ADDR pc)
393{
394 /* A function may start with
fc338970 395
acd5c798
MK
396 pushl constant
397 call _probe
398 addl $4, %esp
fc338970 399
acd5c798
MK
400 followed by
401
402 pushl %ebp
fc338970 403
acd5c798
MK
404 etc. */
405 unsigned char buf[8];
406 unsigned char op;
fc338970 407
acd5c798
MK
408 op = read_memory_unsigned_integer (pc, 1);
409
410 if (op == 0x68 || op == 0x6a)
411 {
412 int delta;
c906108c 413
acd5c798
MK
414 /* Skip past the `pushl' instruction; it has either a one-byte or a
415 four-byte operand, depending on the opcode. */
c906108c 416 if (op == 0x68)
acd5c798 417 delta = 5;
c906108c 418 else
acd5c798 419 delta = 2;
c906108c 420
acd5c798
MK
421 /* Read the following 8 bytes, which should be `call _probe' (6
422 bytes) followed by `addl $4,%esp' (2 bytes). */
423 read_memory (pc + delta, buf, sizeof (buf));
c906108c 424 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
acd5c798 425 pc += delta + sizeof (buf);
c906108c
SS
426 }
427
acd5c798
MK
428 return pc;
429}
430
431/* Check whether PC points at a code that sets up a new stack frame.
432 If so, it updates CACHE and returns the address of the first
433 instruction after the sequence that sets removes the "hidden"
434 argument from the stack or CURRENT_PC, whichever is smaller.
435 Otherwise, return PC. */
436
437static CORE_ADDR
438i386_analyze_frame_setup (CORE_ADDR pc, CORE_ADDR current_pc,
439 struct i386_frame_cache *cache)
440{
441 unsigned char op;
442
443 if (current_pc <= pc)
444 return current_pc;
445
446 op = read_memory_unsigned_integer (pc, 1);
447
c906108c 448 if (op == 0x55) /* pushl %ebp */
c5aa993b 449 {
acd5c798
MK
450 /* Take into account that we've executed the `pushl %ebp' that
451 starts this instruction sequence. */
fd13a04a 452 cache->saved_regs[I386_EBP_REGNUM] = 0;
acd5c798
MK
453 cache->sp_offset += 4;
454
455 /* If that's all, return now. */
456 if (current_pc <= pc + 1)
457 return current_pc;
458
459 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
460 op = read_memory_unsigned_integer (pc + 1, 1);
461 switch (op)
c906108c
SS
462 {
463 case 0x8b:
acd5c798
MK
464 if (read_memory_unsigned_integer (pc + 2, 1) != 0xec)
465 return pc + 1;
c906108c
SS
466 break;
467 case 0x89:
acd5c798
MK
468 if (read_memory_unsigned_integer (pc + 2, 1) != 0xe5)
469 return pc + 1;
c906108c
SS
470 break;
471 default:
acd5c798 472 return pc + 1;
c906108c 473 }
acd5c798
MK
474
475 /* OK, we actually have a frame. We just don't know how large it is
476 yet. Set its size to zero. We'll adjust it if necessary. */
477 cache->locals = 0;
478
479 /* If that's all, return now. */
480 if (current_pc <= pc + 3)
481 return current_pc;
482
fc338970
MK
483 /* Check for stack adjustment
484
acd5c798 485 subl $XXX, %esp
fc338970
MK
486
487 NOTE: You can't subtract a 16 bit immediate from a 32 bit
488 reg, so we don't have to worry about a data16 prefix. */
acd5c798 489 op = read_memory_unsigned_integer (pc + 3, 1);
c906108c
SS
490 if (op == 0x83)
491 {
fc338970 492 /* `subl' with 8 bit immediate. */
acd5c798 493 if (read_memory_unsigned_integer (pc + 4, 1) != 0xec)
fc338970 494 /* Some instruction starting with 0x83 other than `subl'. */
acd5c798
MK
495 return pc + 3;
496
497 /* `subl' with signed byte immediate (though it wouldn't make
498 sense to be negative). */
499 cache->locals = read_memory_integer (pc + 5, 1);
500 return pc + 6;
c906108c
SS
501 }
502 else if (op == 0x81)
503 {
fc338970 504 /* Maybe it is `subl' with a 32 bit immedediate. */
acd5c798 505 if (read_memory_unsigned_integer (pc + 4, 1) != 0xec)
fc338970 506 /* Some instruction starting with 0x81 other than `subl'. */
acd5c798
MK
507 return pc + 3;
508
fc338970 509 /* It is `subl' with a 32 bit immediate. */
acd5c798
MK
510 cache->locals = read_memory_integer (pc + 5, 4);
511 return pc + 9;
c906108c
SS
512 }
513 else
514 {
acd5c798
MK
515 /* Some instruction other than `subl'. */
516 return pc + 3;
c906108c
SS
517 }
518 }
acd5c798 519 else if (op == 0xc8) /* enter $XXX */
c906108c 520 {
acd5c798
MK
521 cache->locals = read_memory_unsigned_integer (pc + 1, 2);
522 return pc + 4;
c906108c 523 }
21d0e8a4 524
acd5c798 525 return pc;
21d0e8a4
MK
526}
527
acd5c798
MK
528/* Check whether PC points at code that saves registers on the stack.
529 If so, it updates CACHE and returns the address of the first
530 instruction after the register saves or CURRENT_PC, whichever is
531 smaller. Otherwise, return PC. */
6bff26de
MK
532
533static CORE_ADDR
acd5c798
MK
534i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
535 struct i386_frame_cache *cache)
6bff26de 536{
acd5c798 537 if (cache->locals >= 0)
267bf4bb 538 {
acd5c798
MK
539 CORE_ADDR offset;
540 unsigned char op;
541 int i;
c0d1d883 542
acd5c798
MK
543 offset = - 4 - cache->locals;
544 for (i = 0; i < 8 && pc < current_pc; i++)
545 {
546 op = read_memory_unsigned_integer (pc, 1);
547 if (op < 0x50 || op > 0x57)
548 break;
0d17c81d 549
fd13a04a 550 cache->saved_regs[op - 0x50] = offset;
acd5c798
MK
551 offset -= 4;
552 pc++;
553 }
6bff26de
MK
554 }
555
acd5c798 556 return pc;
22797942
AC
557}
558
acd5c798
MK
559/* Do a full analysis of the prologue at PC and update CACHE
560 accordingly. Bail out early if CURRENT_PC is reached. Return the
561 address where the analysis stopped.
ed84f6c1 562
fc338970
MK
563 We handle these cases:
564
565 The startup sequence can be at the start of the function, or the
566 function can start with a branch to startup code at the end.
567
568 %ebp can be set up with either the 'enter' instruction, or "pushl
569 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
570 once used in the System V compiler).
571
572 Local space is allocated just below the saved %ebp by either the
573 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a 16
574 bit unsigned argument for space to allocate, and the 'addl'
575 instruction could have either a signed byte, or 32 bit immediate.
576
577 Next, the registers used by this function are pushed. With the
578 System V compiler they will always be in the order: %edi, %esi,
579 %ebx (and sometimes a harmless bug causes it to also save but not
580 restore %eax); however, the code below is willing to see the pushes
581 in any order, and will handle up to 8 of them.
582
583 If the setup sequence is at the end of the function, then the next
584 instruction will be a branch back to the start. */
c906108c 585
acd5c798
MK
586static CORE_ADDR
587i386_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
588 struct i386_frame_cache *cache)
c906108c 589{
acd5c798
MK
590 pc = i386_follow_jump (pc);
591 pc = i386_analyze_struct_return (pc, current_pc, cache);
592 pc = i386_skip_probe (pc);
593 pc = i386_analyze_frame_setup (pc, current_pc, cache);
594 return i386_analyze_register_saves (pc, current_pc, cache);
c906108c
SS
595}
596
fc338970 597/* Return PC of first real instruction. */
c906108c 598
3a1e71e3 599static CORE_ADDR
acd5c798 600i386_skip_prologue (CORE_ADDR start_pc)
c906108c 601{
c5aa993b 602 static unsigned char pic_pat[6] =
acd5c798
MK
603 {
604 0xe8, 0, 0, 0, 0, /* call 0x0 */
605 0x5b, /* popl %ebx */
c5aa993b 606 };
acd5c798
MK
607 struct i386_frame_cache cache;
608 CORE_ADDR pc;
609 unsigned char op;
610 int i;
c5aa993b 611
acd5c798
MK
612 cache.locals = -1;
613 pc = i386_analyze_prologue (start_pc, 0xffffffff, &cache);
614 if (cache.locals < 0)
615 return start_pc;
c5aa993b 616
acd5c798 617 /* Found valid frame setup. */
c906108c 618
fc338970
MK
619 /* The native cc on SVR4 in -K PIC mode inserts the following code
620 to get the address of the global offset table (GOT) into register
acd5c798
MK
621 %ebx:
622
fc338970
MK
623 call 0x0
624 popl %ebx
625 movl %ebx,x(%ebp) (optional)
626 addl y,%ebx
627
c906108c
SS
628 This code is with the rest of the prologue (at the end of the
629 function), so we have to skip it to get to the first real
630 instruction at the start of the function. */
c5aa993b 631
c906108c
SS
632 for (i = 0; i < 6; i++)
633 {
acd5c798 634 op = read_memory_unsigned_integer (pc + i, 1);
c5aa993b 635 if (pic_pat[i] != op)
c906108c
SS
636 break;
637 }
638 if (i == 6)
639 {
acd5c798
MK
640 int delta = 6;
641
642 op = read_memory_unsigned_integer (pc + delta, 1);
c906108c 643
c5aa993b 644 if (op == 0x89) /* movl %ebx, x(%ebp) */
c906108c 645 {
acd5c798
MK
646 op = read_memory_unsigned_integer (pc + delta + 1, 1);
647
fc338970 648 if (op == 0x5d) /* One byte offset from %ebp. */
acd5c798 649 delta += 3;
fc338970 650 else if (op == 0x9d) /* Four byte offset from %ebp. */
acd5c798 651 delta += 6;
fc338970 652 else /* Unexpected instruction. */
acd5c798
MK
653 delta = 0;
654
655 op = read_memory_unsigned_integer (pc + delta, 1);
c906108c 656 }
acd5c798 657
c5aa993b 658 /* addl y,%ebx */
acd5c798
MK
659 if (delta > 0 && op == 0x81
660 && read_memory_unsigned_integer (pc + delta + 1, 1) == 0xc3);
c906108c 661 {
acd5c798 662 pc += delta + 6;
c906108c
SS
663 }
664 }
c5aa993b 665
acd5c798 666 return i386_follow_jump (pc);
c906108c
SS
667}
668
acd5c798 669/* This function is 64-bit safe. */
93924b6b 670
acd5c798
MK
671static CORE_ADDR
672i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
93924b6b 673{
acd5c798
MK
674 char buf[8];
675
676 frame_unwind_register (next_frame, PC_REGNUM, buf);
677 return extract_typed_address (buf, builtin_type_void_func_ptr);
93924b6b 678}
acd5c798 679\f
93924b6b 680
acd5c798 681/* Normal frames. */
c5aa993b 682
acd5c798
MK
683static struct i386_frame_cache *
684i386_frame_cache (struct frame_info *next_frame, void **this_cache)
a7769679 685{
acd5c798 686 struct i386_frame_cache *cache;
c0d1d883 687 char buf[4];
acd5c798
MK
688 int i;
689
690 if (*this_cache)
691 return *this_cache;
692
fd13a04a 693 cache = i386_alloc_frame_cache ();
acd5c798
MK
694 *this_cache = cache;
695
696 /* In principle, for normal frames, %ebp holds the frame pointer,
697 which holds the base address for the current stack frame.
698 However, for functions that don't need it, the frame pointer is
699 optional. For these "frameless" functions the frame pointer is
700 actually the frame pointer of the calling frame. Signal
701 trampolines are just a special case of a "frameless" function.
702 They (usually) share their frame pointer with the frame that was
703 in progress when the signal occurred. */
704
705 frame_unwind_register (next_frame, I386_EBP_REGNUM, buf);
706 cache->base = extract_unsigned_integer (buf, 4);
707 if (cache->base == 0)
708 return cache;
709
710 /* For normal frames, %eip is stored at 4(%ebp). */
fd13a04a 711 cache->saved_regs[I386_EIP_REGNUM] = 4;
acd5c798
MK
712
713 cache->pc = frame_func_unwind (next_frame);
714 if (cache->pc != 0)
715 i386_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
716
717 if (cache->locals < 0)
718 {
719 /* We didn't find a valid frame, which means that CACHE->base
720 currently holds the frame pointer for our calling frame. If
721 we're at the start of a function, or somewhere half-way its
722 prologue, the function's frame probably hasn't been fully
723 setup yet. Try to reconstruct the base address for the stack
724 frame by looking at the stack pointer. For truly "frameless"
725 functions this might work too. */
726
727 frame_unwind_register (next_frame, I386_ESP_REGNUM, buf);
728 cache->base = extract_unsigned_integer (buf, 4) + cache->sp_offset;
729 }
730
731 /* Now that we have the base address for the stack frame we can
732 calculate the value of %esp in the calling frame. */
733 cache->saved_sp = cache->base + 8;
a7769679 734
acd5c798
MK
735 /* Adjust all the saved registers such that they contain addresses
736 instead of offsets. */
737 for (i = 0; i < I386_NUM_SAVED_REGS; i++)
fd13a04a
AC
738 if (cache->saved_regs[i] != -1)
739 cache->saved_regs[i] += cache->base;
acd5c798
MK
740
741 return cache;
a7769679
MK
742}
743
3a1e71e3 744static void
acd5c798
MK
745i386_frame_this_id (struct frame_info *next_frame, void **this_cache,
746 struct frame_id *this_id)
c906108c 747{
acd5c798
MK
748 struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache);
749
750 /* This marks the outermost frame. */
751 if (cache->base == 0)
752 return;
753
3e210248 754 /* See the end of i386_push_dummy_call. */
acd5c798
MK
755 (*this_id) = frame_id_build (cache->base + 8, cache->pc);
756}
757
758static void
759i386_frame_prev_register (struct frame_info *next_frame, void **this_cache,
760 int regnum, int *optimizedp,
761 enum lval_type *lvalp, CORE_ADDR *addrp,
762 int *realnump, void *valuep)
763{
764 struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache);
765
766 gdb_assert (regnum >= 0);
767
768 /* The System V ABI says that:
769
770 "The flags register contains the system flags, such as the
771 direction flag and the carry flag. The direction flag must be
772 set to the forward (that is, zero) direction before entry and
773 upon exit from a function. Other user flags have no specified
774 role in the standard calling sequence and are not preserved."
775
776 To guarantee the "upon exit" part of that statement we fake a
777 saved flags register that has its direction flag cleared.
778
779 Note that GCC doesn't seem to rely on the fact that the direction
780 flag is cleared after a function return; it always explicitly
781 clears the flag before operations where it matters.
782
783 FIXME: kettenis/20030316: I'm not quite sure whether this is the
784 right thing to do. The way we fake the flags register here makes
785 it impossible to change it. */
786
787 if (regnum == I386_EFLAGS_REGNUM)
788 {
789 *optimizedp = 0;
790 *lvalp = not_lval;
791 *addrp = 0;
792 *realnump = -1;
793 if (valuep)
794 {
795 ULONGEST val;
c5aa993b 796
acd5c798
MK
797 /* Clear the direction flag. */
798 frame_unwind_unsigned_register (next_frame, PS_REGNUM, &val);
799 val &= ~(1 << 10);
800 store_unsigned_integer (valuep, 4, val);
801 }
802
803 return;
804 }
1211c4e4 805
acd5c798 806 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
c906108c 807 {
acd5c798
MK
808 frame_register_unwind (next_frame, I386_EAX_REGNUM,
809 optimizedp, lvalp, addrp, realnump, valuep);
810 return;
811 }
812
813 if (regnum == I386_ESP_REGNUM && cache->saved_sp)
814 {
815 *optimizedp = 0;
816 *lvalp = not_lval;
817 *addrp = 0;
818 *realnump = -1;
819 if (valuep)
c906108c 820 {
acd5c798
MK
821 /* Store the value. */
822 store_unsigned_integer (valuep, 4, cache->saved_sp);
c906108c 823 }
acd5c798 824 return;
c906108c 825 }
acd5c798 826
fd13a04a
AC
827 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
828 {
829 *optimizedp = 0;
830 *lvalp = lval_memory;
831 *addrp = cache->saved_regs[regnum];
832 *realnump = -1;
833 if (valuep)
834 {
835 /* Read the value in from memory. */
836 read_memory (*addrp, valuep,
837 register_size (current_gdbarch, regnum));
838 }
839 return;
840 }
841
842 frame_register_unwind (next_frame, regnum,
843 optimizedp, lvalp, addrp, realnump, valuep);
acd5c798
MK
844}
845
846static const struct frame_unwind i386_frame_unwind =
847{
848 NORMAL_FRAME,
849 i386_frame_this_id,
850 i386_frame_prev_register
851};
852
853static const struct frame_unwind *
336d1bba 854i386_frame_sniffer (struct frame_info *next_frame)
acd5c798
MK
855{
856 return &i386_frame_unwind;
857}
858\f
859
860/* Signal trampolines. */
861
862static struct i386_frame_cache *
863i386_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
864{
865 struct i386_frame_cache *cache;
866 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
867 CORE_ADDR addr;
868 char buf[4];
869
870 if (*this_cache)
871 return *this_cache;
872
fd13a04a 873 cache = i386_alloc_frame_cache ();
acd5c798
MK
874
875 frame_unwind_register (next_frame, I386_ESP_REGNUM, buf);
876 cache->base = extract_unsigned_integer (buf, 4) - 4;
877
878 addr = tdep->sigcontext_addr (next_frame);
a3386186
MK
879 if (tdep->sc_reg_offset)
880 {
881 int i;
882
883 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
884
885 for (i = 0; i < tdep->sc_num_regs; i++)
886 if (tdep->sc_reg_offset[i] != -1)
fd13a04a 887 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
a3386186
MK
888 }
889 else
890 {
fd13a04a
AC
891 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
892 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
a3386186 893 }
acd5c798
MK
894
895 *this_cache = cache;
896 return cache;
897}
898
899static void
900i386_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
901 struct frame_id *this_id)
902{
903 struct i386_frame_cache *cache =
904 i386_sigtramp_frame_cache (next_frame, this_cache);
905
3e210248 906 /* See the end of i386_push_dummy_call. */
acd5c798
MK
907 (*this_id) = frame_id_build (cache->base + 8, frame_pc_unwind (next_frame));
908}
909
910static void
911i386_sigtramp_frame_prev_register (struct frame_info *next_frame,
912 void **this_cache,
913 int regnum, int *optimizedp,
914 enum lval_type *lvalp, CORE_ADDR *addrp,
915 int *realnump, void *valuep)
916{
917 /* Make sure we've initialized the cache. */
918 i386_sigtramp_frame_cache (next_frame, this_cache);
919
920 i386_frame_prev_register (next_frame, this_cache, regnum,
921 optimizedp, lvalp, addrp, realnump, valuep);
c906108c 922}
c0d1d883 923
acd5c798
MK
924static const struct frame_unwind i386_sigtramp_frame_unwind =
925{
926 SIGTRAMP_FRAME,
927 i386_sigtramp_frame_this_id,
928 i386_sigtramp_frame_prev_register
929};
930
931static const struct frame_unwind *
336d1bba 932i386_sigtramp_frame_sniffer (struct frame_info *next_frame)
acd5c798 933{
336d1bba 934 CORE_ADDR pc = frame_pc_unwind (next_frame);
acd5c798
MK
935 char *name;
936
1c3545ae
MK
937 /* We shouldn't even bother to try if the OSABI didn't register
938 a sigcontext_addr handler. */
939 if (!gdbarch_tdep (current_gdbarch)->sigcontext_addr)
940 return NULL;
941
acd5c798
MK
942 find_pc_partial_function (pc, &name, NULL, NULL);
943 if (PC_IN_SIGTRAMP (pc, name))
944 return &i386_sigtramp_frame_unwind;
945
946 return NULL;
947}
948\f
949
950static CORE_ADDR
951i386_frame_base_address (struct frame_info *next_frame, void **this_cache)
952{
953 struct i386_frame_cache *cache = i386_frame_cache (next_frame, this_cache);
954
955 return cache->base;
956}
957
958static const struct frame_base i386_frame_base =
959{
960 &i386_frame_unwind,
961 i386_frame_base_address,
962 i386_frame_base_address,
963 i386_frame_base_address
964};
965
acd5c798
MK
966static struct frame_id
967i386_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
968{
969 char buf[4];
970 CORE_ADDR fp;
971
972 frame_unwind_register (next_frame, I386_EBP_REGNUM, buf);
973 fp = extract_unsigned_integer (buf, 4);
974
3e210248 975 /* See the end of i386_push_dummy_call. */
acd5c798 976 return frame_id_build (fp + 8, frame_pc_unwind (next_frame));
c0d1d883 977}
fc338970 978\f
c906108c 979
fc338970
MK
980/* Figure out where the longjmp will land. Slurp the args out of the
981 stack. We expect the first arg to be a pointer to the jmp_buf
8201327c 982 structure from which we extract the address that we will land at.
28bcfd30 983 This address is copied into PC. This routine returns non-zero on
acd5c798
MK
984 success.
985
986 This function is 64-bit safe. */
c906108c 987
8201327c
MK
988static int
989i386_get_longjmp_target (CORE_ADDR *pc)
c906108c 990{
28bcfd30 991 char buf[8];
c906108c 992 CORE_ADDR sp, jb_addr;
8201327c 993 int jb_pc_offset = gdbarch_tdep (current_gdbarch)->jb_pc_offset;
f9d3c2a8 994 int len = TYPE_LENGTH (builtin_type_void_func_ptr);
c906108c 995
8201327c
MK
996 /* If JB_PC_OFFSET is -1, we have no way to find out where the
997 longjmp will land. */
998 if (jb_pc_offset == -1)
c906108c
SS
999 return 0;
1000
8201327c 1001 sp = read_register (SP_REGNUM);
28bcfd30 1002 if (target_read_memory (sp + len, buf, len))
c906108c
SS
1003 return 0;
1004
f9d3c2a8 1005 jb_addr = extract_typed_address (buf, builtin_type_void_func_ptr);
28bcfd30 1006 if (target_read_memory (jb_addr + jb_pc_offset, buf, len))
8201327c 1007 return 0;
c906108c 1008
f9d3c2a8 1009 *pc = extract_typed_address (buf, builtin_type_void_func_ptr);
c906108c
SS
1010 return 1;
1011}
fc338970 1012\f
c906108c 1013
3a1e71e3 1014static CORE_ADDR
6a65450a
AC
1015i386_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1016 struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
1017 struct value **args, CORE_ADDR sp, int struct_return,
1018 CORE_ADDR struct_addr)
22f8ba57 1019{
acd5c798
MK
1020 char buf[4];
1021 int i;
1022
1023 /* Push arguments in reverse order. */
1024 for (i = nargs - 1; i >= 0; i--)
22f8ba57 1025 {
acd5c798
MK
1026 int len = TYPE_LENGTH (VALUE_ENCLOSING_TYPE (args[i]));
1027
1028 /* The System V ABI says that:
1029
1030 "An argument's size is increased, if necessary, to make it a
1031 multiple of [32-bit] words. This may require tail padding,
1032 depending on the size of the argument."
1033
1034 This makes sure the stack says word-aligned. */
1035 sp -= (len + 3) & ~3;
1036 write_memory (sp, VALUE_CONTENTS_ALL (args[i]), len);
1037 }
22f8ba57 1038
acd5c798
MK
1039 /* Push value address. */
1040 if (struct_return)
1041 {
22f8ba57 1042 sp -= 4;
fbd9dcd3 1043 store_unsigned_integer (buf, 4, struct_addr);
22f8ba57
MK
1044 write_memory (sp, buf, 4);
1045 }
1046
acd5c798
MK
1047 /* Store return address. */
1048 sp -= 4;
6a65450a 1049 store_unsigned_integer (buf, 4, bp_addr);
acd5c798
MK
1050 write_memory (sp, buf, 4);
1051
1052 /* Finally, update the stack pointer... */
1053 store_unsigned_integer (buf, 4, sp);
1054 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf);
1055
1056 /* ...and fake a frame pointer. */
1057 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf);
1058
3e210248
AC
1059 /* MarkK wrote: This "+ 8" is all over the place:
1060 (i386_frame_this_id, i386_sigtramp_frame_this_id,
1061 i386_unwind_dummy_id). It's there, since all frame unwinders for
1062 a given target have to agree (within a certain margin) on the
1063 defenition of the stack address of a frame. Otherwise
1064 frame_id_inner() won't work correctly. Since DWARF2/GCC uses the
1065 stack address *before* the function call as a frame's CFA. On
1066 the i386, when %ebp is used as a frame pointer, the offset
1067 between the contents %ebp and the CFA as defined by GCC. */
1068 return sp + 8;
22f8ba57
MK
1069}
1070
1a309862
MK
1071/* These registers are used for returning integers (and on some
1072 targets also for returning `struct' and `union' values when their
ef9dff19 1073 size and alignment match an integer type). */
acd5c798
MK
1074#define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
1075#define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
1a309862
MK
1076
1077/* Extract from an array REGBUF containing the (raw) register state, a
1078 function return value of TYPE, and copy that, in virtual format,
1079 into VALBUF. */
1080
3a1e71e3 1081static void
00f8375e 1082i386_extract_return_value (struct type *type, struct regcache *regcache,
ebba8386 1083 void *dst)
c906108c 1084{
ebba8386 1085 bfd_byte *valbuf = dst;
1a309862 1086 int len = TYPE_LENGTH (type);
00f8375e 1087 char buf[I386_MAX_REGISTER_SIZE];
1a309862 1088
1e8d0a7b
MK
1089 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1090 && TYPE_NFIELDS (type) == 1)
3df1b9b4 1091 {
00f8375e 1092 i386_extract_return_value (TYPE_FIELD_TYPE (type, 0), regcache, valbuf);
3df1b9b4
MK
1093 return;
1094 }
1e8d0a7b
MK
1095
1096 if (TYPE_CODE (type) == TYPE_CODE_FLT)
c906108c 1097 {
94ea66b3 1098 if (FP0_REGNUM < 0)
1a309862
MK
1099 {
1100 warning ("Cannot find floating-point return value.");
1101 memset (valbuf, 0, len);
ef9dff19 1102 return;
1a309862
MK
1103 }
1104
c6ba6f0d
MK
1105 /* Floating-point return values can be found in %st(0). Convert
1106 its contents to the desired type. This is probably not
1107 exactly how it would happen on the target itself, but it is
1108 the best we can do. */
acd5c798 1109 regcache_raw_read (regcache, I386_ST0_REGNUM, buf);
00f8375e 1110 convert_typed_floating (buf, builtin_type_i387_ext, valbuf, type);
c906108c
SS
1111 }
1112 else
c5aa993b 1113 {
d4f3574e
SS
1114 int low_size = REGISTER_RAW_SIZE (LOW_RETURN_REGNUM);
1115 int high_size = REGISTER_RAW_SIZE (HIGH_RETURN_REGNUM);
1116
1117 if (len <= low_size)
00f8375e 1118 {
0818c12a 1119 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
00f8375e
MK
1120 memcpy (valbuf, buf, len);
1121 }
d4f3574e
SS
1122 else if (len <= (low_size + high_size))
1123 {
0818c12a 1124 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf);
00f8375e 1125 memcpy (valbuf, buf, low_size);
0818c12a 1126 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf);
00f8375e 1127 memcpy (valbuf + low_size, buf, len - low_size);
d4f3574e
SS
1128 }
1129 else
8e65ff28
AC
1130 internal_error (__FILE__, __LINE__,
1131 "Cannot extract return value of %d bytes long.", len);
c906108c
SS
1132 }
1133}
1134
ef9dff19
MK
1135/* Write into the appropriate registers a function return value stored
1136 in VALBUF of type TYPE, given in virtual format. */
1137
3a1e71e3 1138static void
3d7f4f49
MK
1139i386_store_return_value (struct type *type, struct regcache *regcache,
1140 const void *valbuf)
ef9dff19
MK
1141{
1142 int len = TYPE_LENGTH (type);
1143
1e8d0a7b
MK
1144 if (TYPE_CODE (type) == TYPE_CODE_STRUCT
1145 && TYPE_NFIELDS (type) == 1)
3df1b9b4 1146 {
3d7f4f49 1147 i386_store_return_value (TYPE_FIELD_TYPE (type, 0), regcache, valbuf);
3df1b9b4
MK
1148 return;
1149 }
1e8d0a7b
MK
1150
1151 if (TYPE_CODE (type) == TYPE_CODE_FLT)
ef9dff19 1152 {
3d7f4f49 1153 ULONGEST fstat;
c6ba6f0d 1154 char buf[FPU_REG_RAW_SIZE];
ccb945b8 1155
94ea66b3 1156 if (FP0_REGNUM < 0)
ef9dff19
MK
1157 {
1158 warning ("Cannot set floating-point return value.");
1159 return;
1160 }
1161
635b0cc1
MK
1162 /* Returning floating-point values is a bit tricky. Apart from
1163 storing the return value in %st(0), we have to simulate the
1164 state of the FPU at function return point. */
1165
c6ba6f0d
MK
1166 /* Convert the value found in VALBUF to the extended
1167 floating-point format used by the FPU. This is probably
1168 not exactly how it would happen on the target itself, but
1169 it is the best we can do. */
1170 convert_typed_floating (valbuf, type, buf, builtin_type_i387_ext);
acd5c798 1171 regcache_raw_write (regcache, I386_ST0_REGNUM, buf);
ccb945b8 1172
635b0cc1
MK
1173 /* Set the top of the floating-point register stack to 7. The
1174 actual value doesn't really matter, but 7 is what a normal
1175 function return would end up with if the program started out
1176 with a freshly initialized FPU. */
3d7f4f49 1177 regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
ccb945b8 1178 fstat |= (7 << 11);
3d7f4f49 1179 regcache_raw_write_unsigned (regcache, FSTAT_REGNUM, fstat);
ccb945b8 1180
635b0cc1
MK
1181 /* Mark %st(1) through %st(7) as empty. Since we set the top of
1182 the floating-point register stack to 7, the appropriate value
1183 for the tag word is 0x3fff. */
3d7f4f49 1184 regcache_raw_write_unsigned (regcache, FTAG_REGNUM, 0x3fff);
ef9dff19
MK
1185 }
1186 else
1187 {
1188 int low_size = REGISTER_RAW_SIZE (LOW_RETURN_REGNUM);
1189 int high_size = REGISTER_RAW_SIZE (HIGH_RETURN_REGNUM);
1190
1191 if (len <= low_size)
3d7f4f49 1192 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf);
ef9dff19
MK
1193 else if (len <= (low_size + high_size))
1194 {
3d7f4f49
MK
1195 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf);
1196 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0,
1197 len - low_size, (char *) valbuf + low_size);
ef9dff19
MK
1198 }
1199 else
8e65ff28
AC
1200 internal_error (__FILE__, __LINE__,
1201 "Cannot store return value of %d bytes long.", len);
ef9dff19
MK
1202 }
1203}
f7af9647 1204
751f1375
MK
1205/* Extract from REGCACHE, which contains the (raw) register state, the
1206 address in which a function should return its structure value, as a
1207 CORE_ADDR. */
f7af9647 1208
3a1e71e3 1209static CORE_ADDR
00f8375e 1210i386_extract_struct_value_address (struct regcache *regcache)
f7af9647 1211{
acd5c798 1212 char buf[4];
751f1375 1213
acd5c798
MK
1214 regcache_cooked_read (regcache, I386_EAX_REGNUM, buf);
1215 return extract_unsigned_integer (buf, 4);
f7af9647 1216}
fc338970 1217\f
ef9dff19 1218
8201327c
MK
1219/* This is the variable that is set with "set struct-convention", and
1220 its legitimate values. */
1221static const char default_struct_convention[] = "default";
1222static const char pcc_struct_convention[] = "pcc";
1223static const char reg_struct_convention[] = "reg";
1224static const char *valid_conventions[] =
1225{
1226 default_struct_convention,
1227 pcc_struct_convention,
1228 reg_struct_convention,
1229 NULL
1230};
1231static const char *struct_convention = default_struct_convention;
1232
1233static int
1234i386_use_struct_convention (int gcc_p, struct type *type)
1235{
1236 enum struct_return struct_return;
1237
1238 if (struct_convention == default_struct_convention)
1239 struct_return = gdbarch_tdep (current_gdbarch)->struct_return;
1240 else if (struct_convention == pcc_struct_convention)
1241 struct_return = pcc_struct_return;
1242 else
1243 struct_return = reg_struct_return;
1244
1245 return generic_use_struct_convention (struct_return == reg_struct_return,
1246 type);
1247}
1248\f
1249
d7a0d72c
MK
1250/* Return the GDB type object for the "standard" data type of data in
1251 register REGNUM. Perhaps %esi and %edi should go here, but
1252 potentially they could be used for things other than address. */
1253
3a1e71e3 1254static struct type *
4e259f09 1255i386_register_type (struct gdbarch *gdbarch, int regnum)
d7a0d72c 1256{
acd5c798
MK
1257 if (regnum == I386_EIP_REGNUM
1258 || regnum == I386_EBP_REGNUM || regnum == I386_ESP_REGNUM)
d7a0d72c
MK
1259 return lookup_pointer_type (builtin_type_void);
1260
23a34459 1261 if (i386_fp_regnum_p (regnum))
c6ba6f0d 1262 return builtin_type_i387_ext;
d7a0d72c 1263
23a34459 1264 if (i386_sse_regnum_p (regnum))
3139facc 1265 return builtin_type_vec128i;
d7a0d72c 1266
23a34459 1267 if (i386_mmx_regnum_p (regnum))
28fc6740
AC
1268 return builtin_type_vec64i;
1269
d7a0d72c
MK
1270 return builtin_type_int;
1271}
1272
28fc6740 1273/* Map a cooked register onto a raw register or memory. For the i386,
acd5c798 1274 the MMX registers need to be mapped onto floating point registers. */
28fc6740
AC
1275
1276static int
c86c27af 1277i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum)
28fc6740
AC
1278{
1279 int mmxi;
1280 ULONGEST fstat;
1281 int tos;
1282 int fpi;
c86c27af 1283
28fc6740
AC
1284 mmxi = regnum - MM0_REGNUM;
1285 regcache_raw_read_unsigned (regcache, FSTAT_REGNUM, &fstat);
1286 tos = (fstat >> 11) & 0x7;
1287 fpi = (mmxi + tos) % 8;
c86c27af 1288
28fc6740
AC
1289 return (FP0_REGNUM + fpi);
1290}
1291
1292static void
1293i386_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1294 int regnum, void *buf)
1295{
23a34459 1296 if (i386_mmx_regnum_p (regnum))
28fc6740 1297 {
d9d9c31f 1298 char mmx_buf[MAX_REGISTER_SIZE];
c86c27af
MK
1299 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
1300
28fc6740 1301 /* Extract (always little endian). */
c86c27af 1302 regcache_raw_read (regcache, fpnum, mmx_buf);
28fc6740
AC
1303 memcpy (buf, mmx_buf, REGISTER_RAW_SIZE (regnum));
1304 }
1305 else
1306 regcache_raw_read (regcache, regnum, buf);
1307}
1308
1309static void
1310i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1311 int regnum, const void *buf)
1312{
23a34459 1313 if (i386_mmx_regnum_p (regnum))
28fc6740 1314 {
d9d9c31f 1315 char mmx_buf[MAX_REGISTER_SIZE];
c86c27af
MK
1316 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum);
1317
28fc6740
AC
1318 /* Read ... */
1319 regcache_raw_read (regcache, fpnum, mmx_buf);
1320 /* ... Modify ... (always little endian). */
1321 memcpy (mmx_buf, buf, REGISTER_RAW_SIZE (regnum));
1322 /* ... Write. */
1323 regcache_raw_write (regcache, fpnum, mmx_buf);
1324 }
1325 else
1326 regcache_raw_write (regcache, regnum, buf);
1327}
ff2e87ac
AC
1328\f
1329
1330/* These registers don't have pervasive standard uses. Move them to
1331 i386-tdep.h if necessary. */
1332
1333#define I386_EBX_REGNUM 3 /* %ebx */
1334#define I386_ECX_REGNUM 1 /* %ecx */
1335#define I386_ESI_REGNUM 6 /* %esi */
1336#define I386_EDI_REGNUM 7 /* %edi */
1337
1338/* Return the register number of the register allocated by GCC after
1339 REGNUM, or -1 if there is no such register. */
1340
1341static int
1342i386_next_regnum (int regnum)
1343{
1344 /* GCC allocates the registers in the order:
1345
1346 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
1347
1348 Since storing a variable in %esp doesn't make any sense we return
1349 -1 for %ebp and for %esp itself. */
1350 static int next_regnum[] =
1351 {
1352 I386_EDX_REGNUM, /* Slot for %eax. */
1353 I386_EBX_REGNUM, /* Slot for %ecx. */
1354 I386_ECX_REGNUM, /* Slot for %edx. */
1355 I386_ESI_REGNUM, /* Slot for %ebx. */
1356 -1, -1, /* Slots for %esp and %ebp. */
1357 I386_EDI_REGNUM, /* Slot for %esi. */
1358 I386_EBP_REGNUM /* Slot for %edi. */
1359 };
1360
de5b9bb9 1361 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0]))
ff2e87ac 1362 return next_regnum[regnum];
28fc6740 1363
ff2e87ac
AC
1364 return -1;
1365}
1366
1367/* Return nonzero if a value of type TYPE stored in register REGNUM
1368 needs any special handling. */
d7a0d72c 1369
3a1e71e3 1370static int
ff2e87ac 1371i386_convert_register_p (int regnum, struct type *type)
d7a0d72c 1372{
de5b9bb9
MK
1373 int len = TYPE_LENGTH (type);
1374
ff2e87ac
AC
1375 /* Values may be spread across multiple registers. Most debugging
1376 formats aren't expressive enough to specify the locations, so
1377 some heuristics is involved. Right now we only handle types that
de5b9bb9
MK
1378 have a length that is a multiple of the word size, since GCC
1379 doesn't seem to put any other types into registers. */
1380 if (len > 4 && len % 4 == 0)
1381 {
1382 int last_regnum = regnum;
1383
1384 while (len > 4)
1385 {
1386 last_regnum = i386_next_regnum (last_regnum);
1387 len -= 4;
1388 }
1389
1390 if (last_regnum != -1)
1391 return 1;
1392 }
ff2e87ac 1393
23a34459 1394 return i386_fp_regnum_p (regnum);
d7a0d72c
MK
1395}
1396
ff2e87ac
AC
1397/* Read a value of type TYPE from register REGNUM in frame FRAME, and
1398 return its contents in TO. */
ac27f131 1399
3a1e71e3 1400static void
ff2e87ac
AC
1401i386_register_to_value (struct frame_info *frame, int regnum,
1402 struct type *type, void *to)
ac27f131 1403{
de5b9bb9
MK
1404 int len = TYPE_LENGTH (type);
1405 char *buf = to;
1406
ff2e87ac
AC
1407 /* FIXME: kettenis/20030609: What should we do if REGNUM isn't
1408 available in FRAME (i.e. if it wasn't saved)? */
3d261580 1409
ff2e87ac 1410 if (i386_fp_regnum_p (regnum))
8d7f6b4a 1411 {
d532c08f
MK
1412 i387_register_to_value (frame, regnum, type, to);
1413 return;
8d7f6b4a 1414 }
ff2e87ac 1415
de5b9bb9
MK
1416 /* Read a value spread accross multiple registers. */
1417
1418 gdb_assert (len > 4 && len % 4 == 0);
3d261580 1419
de5b9bb9
MK
1420 while (len > 0)
1421 {
1422 gdb_assert (regnum != -1);
1423 gdb_assert (register_size (current_gdbarch, regnum) == 4);
d532c08f 1424
de5b9bb9
MK
1425 frame_read_register (frame, regnum, buf);
1426 regnum = i386_next_regnum (regnum);
1427 len -= 4;
1428 buf += 4;
1429 }
ac27f131
MK
1430}
1431
ff2e87ac
AC
1432/* Write the contents FROM of a value of type TYPE into register
1433 REGNUM in frame FRAME. */
ac27f131 1434
3a1e71e3 1435static void
ff2e87ac
AC
1436i386_value_to_register (struct frame_info *frame, int regnum,
1437 struct type *type, const void *from)
ac27f131 1438{
de5b9bb9
MK
1439 int len = TYPE_LENGTH (type);
1440 const char *buf = from;
1441
ff2e87ac 1442 if (i386_fp_regnum_p (regnum))
c6ba6f0d 1443 {
d532c08f
MK
1444 i387_value_to_register (frame, regnum, type, from);
1445 return;
1446 }
3d261580 1447
de5b9bb9
MK
1448 /* Write a value spread accross multiple registers. */
1449
1450 gdb_assert (len > 4 && len % 4 == 0);
ff2e87ac 1451
de5b9bb9
MK
1452 while (len > 0)
1453 {
1454 gdb_assert (regnum != -1);
1455 gdb_assert (register_size (current_gdbarch, regnum) == 4);
d532c08f 1456
de5b9bb9
MK
1457 put_frame_register (frame, regnum, buf);
1458 regnum = i386_next_regnum (regnum);
1459 len -= 4;
1460 buf += 4;
1461 }
ac27f131 1462}
ff2e87ac
AC
1463\f
1464
fc338970 1465
c906108c 1466#ifdef STATIC_TRANSFORM_NAME
fc338970
MK
1467/* SunPRO encodes the static variables. This is not related to C++
1468 mangling, it is done for C too. */
c906108c
SS
1469
1470char *
fba45db2 1471sunpro_static_transform_name (char *name)
c906108c
SS
1472{
1473 char *p;
1474 if (IS_STATIC_TRANSFORM_NAME (name))
1475 {
fc338970
MK
1476 /* For file-local statics there will be a period, a bunch of
1477 junk (the contents of which match a string given in the
c5aa993b
JM
1478 N_OPT), a period and the name. For function-local statics
1479 there will be a bunch of junk (which seems to change the
1480 second character from 'A' to 'B'), a period, the name of the
1481 function, and the name. So just skip everything before the
1482 last period. */
c906108c
SS
1483 p = strrchr (name, '.');
1484 if (p != NULL)
1485 name = p + 1;
1486 }
1487 return name;
1488}
1489#endif /* STATIC_TRANSFORM_NAME */
fc338970 1490\f
c906108c 1491
fc338970 1492/* Stuff for WIN32 PE style DLL's but is pretty generic really. */
c906108c
SS
1493
1494CORE_ADDR
1cce71eb 1495i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name)
c906108c 1496{
fc338970 1497 if (pc && read_memory_unsigned_integer (pc, 2) == 0x25ff) /* jmp *(dest) */
c906108c 1498 {
c5aa993b 1499 unsigned long indirect = read_memory_unsigned_integer (pc + 2, 4);
c906108c 1500 struct minimal_symbol *indsym =
fc338970 1501 indirect ? lookup_minimal_symbol_by_pc (indirect) : 0;
645dd519 1502 char *symname = indsym ? SYMBOL_LINKAGE_NAME (indsym) : 0;
c906108c 1503
c5aa993b 1504 if (symname)
c906108c 1505 {
c5aa993b
JM
1506 if (strncmp (symname, "__imp_", 6) == 0
1507 || strncmp (symname, "_imp_", 5) == 0)
c906108c
SS
1508 return name ? 1 : read_memory_unsigned_integer (indirect, 4);
1509 }
1510 }
fc338970 1511 return 0; /* Not a trampoline. */
c906108c 1512}
fc338970
MK
1513\f
1514
8201327c
MK
1515/* Return non-zero if PC and NAME show that we are in a signal
1516 trampoline. */
1517
1518static int
1519i386_pc_in_sigtramp (CORE_ADDR pc, char *name)
1520{
1521 return (name && strcmp ("_sigtramp", name) == 0);
1522}
1523\f
1524
fc338970
MK
1525/* We have two flavours of disassembly. The machinery on this page
1526 deals with switching between those. */
c906108c
SS
1527
1528static int
5e3397bb 1529i386_print_insn (bfd_vma pc, disassemble_info *info)
c906108c 1530{
5e3397bb
MK
1531 gdb_assert (disassembly_flavor == att_flavor
1532 || disassembly_flavor == intel_flavor);
1533
1534 /* FIXME: kettenis/20020915: Until disassembler_options is properly
1535 constified, cast to prevent a compiler warning. */
1536 info->disassembler_options = (char *) disassembly_flavor;
1537 info->mach = gdbarch_bfd_arch_info (current_gdbarch)->mach;
1538
1539 return print_insn_i386 (pc, info);
7a292a7a 1540}
fc338970 1541\f
3ce1502b 1542
8201327c
MK
1543/* There are a few i386 architecture variants that differ only
1544 slightly from the generic i386 target. For now, we don't give them
1545 their own source file, but include them here. As a consequence,
1546 they'll always be included. */
3ce1502b 1547
8201327c 1548/* System V Release 4 (SVR4). */
3ce1502b 1549
8201327c
MK
1550static int
1551i386_svr4_pc_in_sigtramp (CORE_ADDR pc, char *name)
d2a7c97a 1552{
acd5c798
MK
1553 /* UnixWare uses _sigacthandler. The origin of the other symbols is
1554 currently unknown. */
8201327c
MK
1555 return (name && (strcmp ("_sigreturn", name) == 0
1556 || strcmp ("_sigacthandler", name) == 0
1557 || strcmp ("sigvechandler", name) == 0));
1558}
d2a7c97a 1559
acd5c798
MK
1560/* Assuming NEXT_FRAME is for a frame following a SVR4 sigtramp
1561 routine, return the address of the associated sigcontext (ucontext)
1562 structure. */
3ce1502b 1563
3a1e71e3 1564static CORE_ADDR
acd5c798 1565i386_svr4_sigcontext_addr (struct frame_info *next_frame)
8201327c 1566{
acd5c798
MK
1567 char buf[4];
1568 CORE_ADDR sp;
3ce1502b 1569
acd5c798
MK
1570 frame_unwind_register (next_frame, I386_ESP_REGNUM, buf);
1571 sp = extract_unsigned_integer (buf, 4);
21d0e8a4 1572
acd5c798 1573 return read_memory_unsigned_integer (sp + 8, 4);
8201327c
MK
1574}
1575\f
3ce1502b 1576
8201327c 1577/* DJGPP. */
d2a7c97a 1578
8201327c
MK
1579static int
1580i386_go32_pc_in_sigtramp (CORE_ADDR pc, char *name)
1581{
1582 /* DJGPP doesn't have any special frames for signal handlers. */
1583 return 0;
1584}
1585\f
d2a7c97a 1586
8201327c 1587/* Generic ELF. */
d2a7c97a 1588
8201327c
MK
1589void
1590i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1591{
1592 /* We typically use stabs-in-ELF with the DWARF register numbering. */
1593 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum);
1594}
3ce1502b 1595
8201327c 1596/* System V Release 4 (SVR4). */
3ce1502b 1597
8201327c
MK
1598void
1599i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1600{
1601 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3ce1502b 1602
8201327c
MK
1603 /* System V Release 4 uses ELF. */
1604 i386_elf_init_abi (info, gdbarch);
3ce1502b 1605
dfe01d39
MK
1606 /* System V Release 4 has shared libraries. */
1607 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
1608 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
1609
8201327c 1610 set_gdbarch_pc_in_sigtramp (gdbarch, i386_svr4_pc_in_sigtramp);
21d0e8a4 1611 tdep->sigcontext_addr = i386_svr4_sigcontext_addr;
acd5c798
MK
1612 tdep->sc_pc_offset = 36 + 14 * 4;
1613 tdep->sc_sp_offset = 36 + 17 * 4;
3ce1502b 1614
8201327c 1615 tdep->jb_pc_offset = 20;
3ce1502b
MK
1616}
1617
8201327c 1618/* DJGPP. */
3ce1502b 1619
3a1e71e3 1620static void
8201327c 1621i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3ce1502b 1622{
8201327c 1623 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3ce1502b 1624
8201327c 1625 set_gdbarch_pc_in_sigtramp (gdbarch, i386_go32_pc_in_sigtramp);
3ce1502b 1626
8201327c 1627 tdep->jb_pc_offset = 36;
3ce1502b
MK
1628}
1629
8201327c 1630/* NetWare. */
3ce1502b 1631
3a1e71e3 1632static void
8201327c 1633i386_nw_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
3ce1502b 1634{
8201327c 1635 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3ce1502b 1636
8201327c 1637 tdep->jb_pc_offset = 24;
d2a7c97a 1638}
8201327c 1639\f
2acceee2 1640
38c968cf
AC
1641/* i386 register groups. In addition to the normal groups, add "mmx"
1642 and "sse". */
1643
1644static struct reggroup *i386_sse_reggroup;
1645static struct reggroup *i386_mmx_reggroup;
1646
1647static void
1648i386_init_reggroups (void)
1649{
1650 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP);
1651 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP);
1652}
1653
1654static void
1655i386_add_reggroups (struct gdbarch *gdbarch)
1656{
1657 reggroup_add (gdbarch, i386_sse_reggroup);
1658 reggroup_add (gdbarch, i386_mmx_reggroup);
1659 reggroup_add (gdbarch, general_reggroup);
1660 reggroup_add (gdbarch, float_reggroup);
1661 reggroup_add (gdbarch, all_reggroup);
1662 reggroup_add (gdbarch, save_reggroup);
1663 reggroup_add (gdbarch, restore_reggroup);
1664 reggroup_add (gdbarch, vector_reggroup);
1665 reggroup_add (gdbarch, system_reggroup);
1666}
1667
1668int
1669i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1670 struct reggroup *group)
1671{
1672 int sse_regnum_p = (i386_sse_regnum_p (regnum)
1673 || i386_mxcsr_regnum_p (regnum));
1674 int fp_regnum_p = (i386_fp_regnum_p (regnum)
1675 || i386_fpc_regnum_p (regnum));
1676 int mmx_regnum_p = (i386_mmx_regnum_p (regnum));
acd5c798 1677
38c968cf
AC
1678 if (group == i386_mmx_reggroup)
1679 return mmx_regnum_p;
1680 if (group == i386_sse_reggroup)
1681 return sse_regnum_p;
1682 if (group == vector_reggroup)
1683 return (mmx_regnum_p || sse_regnum_p);
1684 if (group == float_reggroup)
1685 return fp_regnum_p;
1686 if (group == general_reggroup)
1687 return (!fp_regnum_p && !mmx_regnum_p && !sse_regnum_p);
acd5c798 1688
38c968cf
AC
1689 return default_register_reggroup_p (gdbarch, regnum, group);
1690}
38c968cf 1691\f
acd5c798 1692
143985b7 1693/* Get the ith function argument for the current function. */
42c466d7 1694static CORE_ADDR
143985b7
AF
1695i386_fetch_pointer_argument (struct frame_info *frame, int argi,
1696 struct type *type)
1697{
1698 CORE_ADDR stack;
1699 frame_read_register (frame, SP_REGNUM, &stack);
1700 return read_memory_unsigned_integer (stack + (4 * (argi + 1)), 4);
1701}
1702
1703\f
3a1e71e3 1704static struct gdbarch *
a62cc96e
AC
1705i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1706{
cd3c07fc 1707 struct gdbarch_tdep *tdep;
a62cc96e
AC
1708 struct gdbarch *gdbarch;
1709
4be87837
DJ
1710 /* If there is already a candidate, use it. */
1711 arches = gdbarch_list_lookup_by_info (arches, &info);
1712 if (arches != NULL)
1713 return arches->gdbarch;
a62cc96e
AC
1714
1715 /* Allocate space for the new architecture. */
1716 tdep = XMALLOC (struct gdbarch_tdep);
1717 gdbarch = gdbarch_alloc (&info, tdep);
1718
8201327c 1719 /* The i386 default settings don't include the SSE registers.
356a6b3e
MK
1720 FIXME: kettenis/20020614: They do include the FPU registers for
1721 now, which probably is not quite right. */
8201327c 1722 tdep->num_xmm_regs = 0;
d2a7c97a 1723
8201327c
MK
1724 tdep->jb_pc_offset = -1;
1725 tdep->struct_return = pcc_struct_return;
8201327c
MK
1726 tdep->sigtramp_start = 0;
1727 tdep->sigtramp_end = 0;
21d0e8a4 1728 tdep->sigcontext_addr = NULL;
a3386186 1729 tdep->sc_reg_offset = NULL;
8201327c 1730 tdep->sc_pc_offset = -1;
21d0e8a4 1731 tdep->sc_sp_offset = -1;
8201327c 1732
896fb97d
MK
1733 /* The format used for `long double' on almost all i386 targets is
1734 the i387 extended floating-point format. In fact, of all targets
1735 in the GCC 2.95 tree, only OSF/1 does it different, and insists
1736 on having a `long double' that's not `long' at all. */
1737 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
21d0e8a4 1738
66da5fd8 1739 /* Although the i387 extended floating-point has only 80 significant
896fb97d
MK
1740 bits, a `long double' actually takes up 96, probably to enforce
1741 alignment. */
1742 set_gdbarch_long_double_bit (gdbarch, 96);
1743
acd5c798
MK
1744 /* The default ABI includes general-purpose registers and
1745 floating-point registers. */
356a6b3e 1746 set_gdbarch_num_regs (gdbarch, I386_NUM_GREGS + I386_NUM_FREGS);
acd5c798
MK
1747 set_gdbarch_register_name (gdbarch, i386_register_name);
1748 set_gdbarch_register_type (gdbarch, i386_register_type);
21d0e8a4 1749
acd5c798
MK
1750 /* Register numbers of various important registers. */
1751 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */
1752 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */
1753 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */
1754 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */
356a6b3e
MK
1755
1756 /* Use the "default" register numbering scheme for stabs and COFF. */
1757 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum);
1758 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_stab_reg_to_regnum);
1759
1760 /* Use the DWARF register numbering scheme for DWARF and DWARF 2. */
1761 set_gdbarch_dwarf_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum);
1762 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_dwarf_reg_to_regnum);
1763
1764 /* We don't define ECOFF_REG_TO_REGNUM, since ECOFF doesn't seem to
1765 be in use on any of the supported i386 targets. */
1766
61113f8b
MK
1767 set_gdbarch_print_float_info (gdbarch, i387_print_float_info);
1768
8201327c 1769 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target);
96297dab 1770
a62cc96e 1771 /* Call dummy code. */
acd5c798 1772 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call);
a62cc96e 1773
ff2e87ac
AC
1774 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p);
1775 set_gdbarch_register_to_value (gdbarch, i386_register_to_value);
1776 set_gdbarch_value_to_register (gdbarch, i386_value_to_register);
b6197528 1777
00f8375e 1778 set_gdbarch_extract_return_value (gdbarch, i386_extract_return_value);
3d7f4f49 1779 set_gdbarch_store_return_value (gdbarch, i386_store_return_value);
00f8375e 1780 set_gdbarch_extract_struct_value_address (gdbarch,
fc08ec52 1781 i386_extract_struct_value_address);
8201327c
MK
1782 set_gdbarch_use_struct_convention (gdbarch, i386_use_struct_convention);
1783
93924b6b
MK
1784 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue);
1785
1786 /* Stack grows downward. */
1787 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1788
1789 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc);
1790 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1791 set_gdbarch_function_start_offset (gdbarch, 0);
42fdc8df 1792
42fdc8df 1793 set_gdbarch_frame_args_skip (gdbarch, 8);
8201327c
MK
1794 set_gdbarch_pc_in_sigtramp (gdbarch, i386_pc_in_sigtramp);
1795
28fc6740 1796 /* Wire in the MMX registers. */
0f751ff2 1797 set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs);
28fc6740
AC
1798 set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read);
1799 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write);
1800
5e3397bb
MK
1801 set_gdbarch_print_insn (gdbarch, i386_print_insn);
1802
acd5c798 1803 set_gdbarch_unwind_dummy_id (gdbarch, i386_unwind_dummy_id);
acd5c798
MK
1804
1805 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc);
1806
38c968cf
AC
1807 /* Add the i386 register groups. */
1808 i386_add_reggroups (gdbarch);
1809 set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p);
1810
143985b7
AF
1811 /* Helper for function argument information. */
1812 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument);
1813
6405b0a6 1814 /* Hook in the DWARF CFI frame unwinder. */
336d1bba 1815 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
6405b0a6 1816
acd5c798 1817 frame_base_set_default (gdbarch, &i386_frame_base);
6c0e89ed 1818
3ce1502b 1819 /* Hook in ABI-specific overrides, if they have been registered. */
4be87837 1820 gdbarch_init_osabi (info, gdbarch);
3ce1502b 1821
336d1bba
AC
1822 frame_unwind_append_sniffer (gdbarch, i386_sigtramp_frame_sniffer);
1823 frame_unwind_append_sniffer (gdbarch, i386_frame_sniffer);
acd5c798 1824
a62cc96e
AC
1825 return gdbarch;
1826}
1827
8201327c
MK
1828static enum gdb_osabi
1829i386_coff_osabi_sniffer (bfd *abfd)
1830{
762c5349
MK
1831 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0
1832 || strcmp (bfd_get_target (abfd), "coff-go32") == 0)
8201327c
MK
1833 return GDB_OSABI_GO32;
1834
1835 return GDB_OSABI_UNKNOWN;
1836}
1837
1838static enum gdb_osabi
1839i386_nlm_osabi_sniffer (bfd *abfd)
1840{
1841 return GDB_OSABI_NETWARE;
1842}
1843\f
1844
28e9e0f0
MK
1845/* Provide a prototype to silence -Wmissing-prototypes. */
1846void _initialize_i386_tdep (void);
1847
c906108c 1848void
fba45db2 1849_initialize_i386_tdep (void)
c906108c 1850{
a62cc96e
AC
1851 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init);
1852
fc338970 1853 /* Add the variable that controls the disassembly flavor. */
917317f4
JM
1854 {
1855 struct cmd_list_element *new_cmd;
7a292a7a 1856
917317f4
JM
1857 new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class,
1858 valid_flavors,
1ed2a135 1859 &disassembly_flavor,
fc338970
MK
1860 "\
1861Set the disassembly flavor, the valid values are \"att\" and \"intel\", \
c906108c 1862and the default value is \"att\".",
917317f4 1863 &setlist);
917317f4
JM
1864 add_show_from_set (new_cmd, &showlist);
1865 }
8201327c
MK
1866
1867 /* Add the variable that controls the convention for returning
1868 structs. */
1869 {
1870 struct cmd_list_element *new_cmd;
1871
1872 new_cmd = add_set_enum_cmd ("struct-convention", no_class,
5e3397bb 1873 valid_conventions,
8201327c
MK
1874 &struct_convention, "\
1875Set the convention for returning small structs, valid values \
1876are \"default\", \"pcc\" and \"reg\", and the default value is \"default\".",
1877 &setlist);
1878 add_show_from_set (new_cmd, &showlist);
1879 }
1880
1881 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour,
1882 i386_coff_osabi_sniffer);
1883 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_nlm_flavour,
1884 i386_nlm_osabi_sniffer);
1885
05816f70 1886 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4,
8201327c 1887 i386_svr4_init_abi);
05816f70 1888 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32,
8201327c 1889 i386_go32_init_abi);
05816f70 1890 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_NETWARE,
8201327c 1891 i386_nw_init_abi);
38c968cf
AC
1892
1893 /* Initialize the i386 specific register groups. */
1894 i386_init_reggroups ();
c906108c 1895}
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