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9a82579f JS |
1 | /* Target-dependent code for GDB, the GNU debugger. |
2 | Copyright 2001 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef I386_TDEP_H | |
23 | #define I386_TDEP_H | |
24 | ||
96297dab MK |
25 | /* GDB's i386 target supports both the 32-bit Intel Architecture |
26 | (IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses | |
27 | a similar register layout for both. | |
28 | ||
29 | - General purpose registers | |
30 | - FPU data registers | |
31 | - FPU control registers | |
32 | - SSE data registers | |
33 | - SSE control register | |
34 | ||
35 | The general purpose registers for the x86-64 architecture are quite | |
36 | different from IA-32. Therefore, the FP0_REGNUM target macro | |
37 | determines the register number at which the FPU data registers | |
38 | start. The number of FPU data and control registers is the same | |
39 | for both architectures. The number of SSE registers however, | |
40 | differs and is determined by the num_xmm_regs member of `struct | |
41 | gdbarch_tdep'. */ | |
42 | ||
3ce1502b MK |
43 | /* ABI variants that we know about. */ |
44 | enum i386_abi | |
45 | { | |
46 | I386_ABI_UNKNOWN = 0, | |
47 | ||
48 | /* ELF */ | |
49 | I386_ABI_SVR4, /* This is the default. */ | |
50 | I386_ABI_NETBSD, | |
51 | I386_ABI_LINUX, | |
52 | I386_ABI_HURD, | |
53 | I386_ABI_SOLARIS, | |
54 | I386_ABI_FREEBSD, | |
55 | ||
56 | I386_ABI_INVALID = -1 | |
57 | }; | |
58 | ||
96297dab MK |
59 | /* i386 architecture specific information. */ |
60 | struct gdbarch_tdep | |
61 | { | |
3ce1502b MK |
62 | /* ABI. */ |
63 | enum i386_abi abi; | |
d2a7c97a | 64 | |
96297dab MK |
65 | /* Number of SSE registers. */ |
66 | int num_xmm_regs; | |
67 | }; | |
68 | ||
69 | /* Floating-point registers. */ | |
70 | ||
9a82579f JS |
71 | #define FPU_REG_RAW_SIZE 10 |
72 | ||
96297dab MK |
73 | /* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit |
74 | (at most) in the FPU, but are zero-extended to 32 bits in GDB's | |
75 | register cache. */ | |
76 | ||
77 | /* "Generic" floating point control register. */ | |
78 | #define FPC_REGNUM (FP0_REGNUM + 8) | |
79 | ||
9a82579f | 80 | /* FPU control word. */ |
96297dab MK |
81 | #define FCTRL_REGNUM FPC_REGNUM |
82 | ||
9a82579f | 83 | /* FPU status word. */ |
96297dab MK |
84 | #define FSTAT_REGNUM (FPC_REGNUM + 1) |
85 | ||
9a82579f | 86 | /* FPU register tag word. */ |
96297dab MK |
87 | #define FTAG_REGNUM (FPC_REGNUM + 2) |
88 | ||
89 | /* FPU instruction's code segment selector, called "FPU Instruction | |
90 | Pointer Selector" in the IA-32 manuals. */ | |
91 | #define FISEG_REGNUM (FPC_REGNUM + 3) | |
92 | ||
93 | /* FPU instruction's offset within segment. */ | |
94 | #define FIOFF_REGNUM (FPC_REGNUM + 4) | |
95 | ||
9a82579f | 96 | /* FPU operand's data segment. */ |
96297dab MK |
97 | #define FOSEG_REGNUM (FPC_REGNUM + 5) |
98 | ||
99 | /* FPU operand's offset within segment */ | |
100 | #define FOOFF_REGNUM (FPC_REGNUM + 6) | |
101 | ||
9a82579f | 102 | /* FPU opcode, bottom eleven bits. */ |
96297dab | 103 | #define FOP_REGNUM (FPC_REGNUM + 7) |
9a82579f | 104 | |
96297dab MK |
105 | /* Return non-zero if N corresponds to a FPU data registers. */ |
106 | #define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM) | |
107 | ||
108 | /* Return non-zero if N corresponds to a FPU control register. */ | |
109 | #define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM) | |
110 | ||
111 | /* SSE registers. */ | |
112 | ||
113 | /* First SSE data register. */ | |
114 | #define XMM0_REGNUM (FPC_REGNUM + 8) | |
115 | ||
116 | /* SSE control/status register. */ | |
117 | #define MXCSR_REGNUM \ | |
118 | (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
119 | ||
120 | /* Return non-zero if N corresponds to a SSE data register. */ | |
121 | #define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM) | |
122 | ||
123 | /* FIXME: kettenis/2001-11-24: Obsolete macro's. */ | |
124 | #define FCS_REGNUM FISEG_REGNUM | |
125 | #define FCOFF_REGNUM FIOFF_REGNUM | |
126 | #define FDS_REGNUM FOSEG_REGNUM | |
127 | #define FDOFF_REGNUM FOOFF_REGNUM | |
128 | #define IS_FP_REGNUM(n) FP_REGNUM_P (n) | |
129 | #define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n) | |
130 | #define IS_SSE_REGNUM(n) SSE_REGNUM_P (n) | |
9a82579f | 131 | |
3ce1502b MK |
132 | void i386_gdbarch_register_os_abi (enum i386_abi, |
133 | void (*init_abi)(struct gdbarch_info, | |
134 | struct gdbarch *)); | |
135 | ||
96297dab | 136 | #endif /* i386-tdep.h */ |