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9a82579f JS |
1 | /* Target-dependent code for GDB, the GNU debugger. |
2 | Copyright 2001 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef I386_TDEP_H | |
23 | #define I386_TDEP_H | |
24 | ||
96297dab MK |
25 | /* GDB's i386 target supports both the 32-bit Intel Architecture |
26 | (IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses | |
27 | a similar register layout for both. | |
28 | ||
29 | - General purpose registers | |
30 | - FPU data registers | |
31 | - FPU control registers | |
32 | - SSE data registers | |
33 | - SSE control register | |
34 | ||
35 | The general purpose registers for the x86-64 architecture are quite | |
36 | different from IA-32. Therefore, the FP0_REGNUM target macro | |
37 | determines the register number at which the FPU data registers | |
38 | start. The number of FPU data and control registers is the same | |
39 | for both architectures. The number of SSE registers however, | |
40 | differs and is determined by the num_xmm_regs member of `struct | |
41 | gdbarch_tdep'. */ | |
42 | ||
43 | /* i386 architecture specific information. */ | |
44 | struct gdbarch_tdep | |
45 | { | |
d2a7c97a MK |
46 | /* OS/ABI. */ |
47 | int os_ident; | |
48 | ||
96297dab MK |
49 | /* Number of SSE registers. */ |
50 | int num_xmm_regs; | |
51 | }; | |
52 | ||
53 | /* Floating-point registers. */ | |
54 | ||
9a82579f JS |
55 | #define FPU_REG_RAW_SIZE 10 |
56 | ||
96297dab MK |
57 | /* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit |
58 | (at most) in the FPU, but are zero-extended to 32 bits in GDB's | |
59 | register cache. */ | |
60 | ||
61 | /* "Generic" floating point control register. */ | |
62 | #define FPC_REGNUM (FP0_REGNUM + 8) | |
63 | ||
9a82579f | 64 | /* FPU control word. */ |
96297dab MK |
65 | #define FCTRL_REGNUM FPC_REGNUM |
66 | ||
9a82579f | 67 | /* FPU status word. */ |
96297dab MK |
68 | #define FSTAT_REGNUM (FPC_REGNUM + 1) |
69 | ||
9a82579f | 70 | /* FPU register tag word. */ |
96297dab MK |
71 | #define FTAG_REGNUM (FPC_REGNUM + 2) |
72 | ||
73 | /* FPU instruction's code segment selector, called "FPU Instruction | |
74 | Pointer Selector" in the IA-32 manuals. */ | |
75 | #define FISEG_REGNUM (FPC_REGNUM + 3) | |
76 | ||
77 | /* FPU instruction's offset within segment. */ | |
78 | #define FIOFF_REGNUM (FPC_REGNUM + 4) | |
79 | ||
9a82579f | 80 | /* FPU operand's data segment. */ |
96297dab MK |
81 | #define FOSEG_REGNUM (FPC_REGNUM + 5) |
82 | ||
83 | /* FPU operand's offset within segment */ | |
84 | #define FOOFF_REGNUM (FPC_REGNUM + 6) | |
85 | ||
9a82579f | 86 | /* FPU opcode, bottom eleven bits. */ |
96297dab | 87 | #define FOP_REGNUM (FPC_REGNUM + 7) |
9a82579f | 88 | |
96297dab MK |
89 | /* Return non-zero if N corresponds to a FPU data registers. */ |
90 | #define FP_REGNUM_P(n) (FP0_REGNUM <= (n) && (n) < FPC_REGNUM) | |
91 | ||
92 | /* Return non-zero if N corresponds to a FPU control register. */ | |
93 | #define FPC_REGNUM_P(n) (FPC_REGNUM <= (n) && (n) < XMM0_REGNUM) | |
94 | ||
95 | /* SSE registers. */ | |
96 | ||
97 | /* First SSE data register. */ | |
98 | #define XMM0_REGNUM (FPC_REGNUM + 8) | |
99 | ||
100 | /* SSE control/status register. */ | |
101 | #define MXCSR_REGNUM \ | |
102 | (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
103 | ||
104 | /* Return non-zero if N corresponds to a SSE data register. */ | |
105 | #define SSE_REGNUM_P(n) (XMM0_REGNUM <= (n) && (n) < MXCSR_REGNUM) | |
106 | ||
107 | /* FIXME: kettenis/2001-11-24: Obsolete macro's. */ | |
108 | #define FCS_REGNUM FISEG_REGNUM | |
109 | #define FCOFF_REGNUM FIOFF_REGNUM | |
110 | #define FDS_REGNUM FOSEG_REGNUM | |
111 | #define FDOFF_REGNUM FOOFF_REGNUM | |
112 | #define IS_FP_REGNUM(n) FP_REGNUM_P (n) | |
113 | #define IS_FPU_CTRL_REGNUM(n) FPC_REGNUM_P (n) | |
114 | #define IS_SSE_REGNUM(n) SSE_REGNUM_P (n) | |
9a82579f | 115 | |
96297dab | 116 | #endif /* i386-tdep.h */ |