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5716833c MK |
1 | /* Target-dependent code for the i386. |
2 | ||
4be87837 | 3 | Copyright 2001, 2002, 2003 |
9a82579f JS |
4 | Free Software Foundation, Inc. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #ifndef I386_TDEP_H | |
24 | #define I386_TDEP_H | |
25 | ||
da3331ec | 26 | struct frame_info; |
5716833c MK |
27 | struct gdbarch; |
28 | struct reggroup; | |
da3331ec | 29 | |
96297dab MK |
30 | /* GDB's i386 target supports both the 32-bit Intel Architecture |
31 | (IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses | |
32 | a similar register layout for both. | |
33 | ||
34 | - General purpose registers | |
35 | - FPU data registers | |
36 | - FPU control registers | |
37 | - SSE data registers | |
38 | - SSE control register | |
39 | ||
40 | The general purpose registers for the x86-64 architecture are quite | |
41 | different from IA-32. Therefore, the FP0_REGNUM target macro | |
42 | determines the register number at which the FPU data registers | |
43 | start. The number of FPU data and control registers is the same | |
44 | for both architectures. The number of SSE registers however, | |
45 | differs and is determined by the num_xmm_regs member of `struct | |
46 | gdbarch_tdep'. */ | |
47 | ||
8201327c | 48 | /* Convention for returning structures. */ |
3ce1502b | 49 | |
8201327c MK |
50 | enum struct_return |
51 | { | |
52 | pcc_struct_return, /* Return "short" structures in memory. */ | |
53 | reg_struct_return /* Return "short" structures in registers. */ | |
3ce1502b MK |
54 | }; |
55 | ||
96297dab MK |
56 | /* i386 architecture specific information. */ |
57 | struct gdbarch_tdep | |
58 | { | |
473f17b0 MK |
59 | /* General-purpose registers. */ |
60 | struct regset *gregset; | |
61 | int *gregset_reg_offset; | |
62 | int gregset_num_regs; | |
63 | size_t sizeof_gregset; | |
64 | ||
65 | /* Floating-point registers. */ | |
66 | struct regset *fpregset; | |
67 | size_t sizeof_fpregset; | |
68 | ||
5716833c MK |
69 | /* Register number for %st(0). The register numbers for the other |
70 | registers follow from this one. Set this to -1 to indicate the | |
71 | absence of an FPU. */ | |
72 | int st0_regnum; | |
73 | ||
74 | /* Register number for %mm0. Set this to -1 to indicate the absence | |
75 | of MMX support. */ | |
76 | int mm0_regnum; | |
77 | ||
96297dab MK |
78 | /* Number of SSE registers. */ |
79 | int num_xmm_regs; | |
8201327c MK |
80 | |
81 | /* Offset of saved PC in jmp_buf. */ | |
82 | int jb_pc_offset; | |
83 | ||
84 | /* Convention for returning structures. */ | |
85 | enum struct_return struct_return; | |
86 | ||
8201327c MK |
87 | /* Address range where sigtramp lives. */ |
88 | CORE_ADDR sigtramp_start; | |
89 | CORE_ADDR sigtramp_end; | |
90 | ||
21d0e8a4 MK |
91 | /* Get address of sigcontext for sigtramp. */ |
92 | CORE_ADDR (*sigcontext_addr) (struct frame_info *); | |
93 | ||
a3386186 MK |
94 | /* Offset of registers in `struct sigcontext'. */ |
95 | int *sc_reg_offset; | |
96 | int sc_num_regs; | |
97 | ||
98 | /* Offset of saved PC and SP in `struct sigcontext'. Usage of these | |
99 | is deprecated, please use `sc_reg_offset' instead. */ | |
8201327c | 100 | int sc_pc_offset; |
21d0e8a4 | 101 | int sc_sp_offset; |
96297dab MK |
102 | }; |
103 | ||
104 | /* Floating-point registers. */ | |
105 | ||
9a82579f JS |
106 | #define FPU_REG_RAW_SIZE 10 |
107 | ||
96297dab MK |
108 | /* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit |
109 | (at most) in the FPU, but are zero-extended to 32 bits in GDB's | |
110 | register cache. */ | |
111 | ||
112 | /* "Generic" floating point control register. */ | |
113 | #define FPC_REGNUM (FP0_REGNUM + 8) | |
114 | ||
9a82579f | 115 | /* FPU control word. */ |
96297dab MK |
116 | #define FCTRL_REGNUM FPC_REGNUM |
117 | ||
9a82579f | 118 | /* FPU status word. */ |
96297dab MK |
119 | #define FSTAT_REGNUM (FPC_REGNUM + 1) |
120 | ||
9a82579f | 121 | /* FPU register tag word. */ |
96297dab MK |
122 | #define FTAG_REGNUM (FPC_REGNUM + 2) |
123 | ||
124 | /* FPU instruction's code segment selector, called "FPU Instruction | |
125 | Pointer Selector" in the IA-32 manuals. */ | |
126 | #define FISEG_REGNUM (FPC_REGNUM + 3) | |
127 | ||
128 | /* FPU instruction's offset within segment. */ | |
129 | #define FIOFF_REGNUM (FPC_REGNUM + 4) | |
130 | ||
9a82579f | 131 | /* FPU operand's data segment. */ |
96297dab MK |
132 | #define FOSEG_REGNUM (FPC_REGNUM + 5) |
133 | ||
134 | /* FPU operand's offset within segment */ | |
135 | #define FOOFF_REGNUM (FPC_REGNUM + 6) | |
136 | ||
9a82579f | 137 | /* FPU opcode, bottom eleven bits. */ |
96297dab | 138 | #define FOP_REGNUM (FPC_REGNUM + 7) |
9a82579f | 139 | |
23a34459 AC |
140 | /* Return non-zero if REGNUM matches the FP register and the FP |
141 | register set is active. */ | |
142 | extern int i386_fp_regnum_p (int regnum); | |
143 | extern int i386_fpc_regnum_p (int regnum); | |
96297dab MK |
144 | |
145 | /* SSE registers. */ | |
146 | ||
147 | /* First SSE data register. */ | |
148 | #define XMM0_REGNUM (FPC_REGNUM + 8) | |
149 | ||
150 | /* SSE control/status register. */ | |
151 | #define MXCSR_REGNUM \ | |
152 | (XMM0_REGNUM + gdbarch_tdep (current_gdbarch)->num_xmm_regs) | |
153 | ||
96297dab MK |
154 | /* FIXME: kettenis/2001-11-24: Obsolete macro's. */ |
155 | #define FCS_REGNUM FISEG_REGNUM | |
156 | #define FCOFF_REGNUM FIOFF_REGNUM | |
157 | #define FDS_REGNUM FOSEG_REGNUM | |
158 | #define FDOFF_REGNUM FOOFF_REGNUM | |
9a82579f | 159 | |
a3386186 MK |
160 | /* Register numbers of various important registers. */ |
161 | ||
162 | #define I386_EAX_REGNUM 0 /* %eax */ | |
163 | #define I386_EDX_REGNUM 2 /* %edx */ | |
164 | #define I386_ESP_REGNUM 4 /* %esp */ | |
165 | #define I386_EBP_REGNUM 5 /* %ebp */ | |
166 | #define I386_EIP_REGNUM 8 /* %eip */ | |
167 | #define I386_EFLAGS_REGNUM 9 /* %eflags */ | |
168 | #define I386_ST0_REGNUM 16 /* %st(0) */ | |
169 | ||
8201327c MK |
170 | #define I386_NUM_GREGS 16 |
171 | #define I386_NUM_FREGS 16 | |
172 | #define I386_NUM_XREGS 9 | |
173 | ||
174 | #define I386_SSE_NUM_REGS (I386_NUM_GREGS + I386_NUM_FREGS \ | |
175 | + I386_NUM_XREGS) | |
176 | ||
00f8375e MK |
177 | /* Size of the largest register. */ |
178 | #define I386_MAX_REGISTER_SIZE 16 | |
179 | ||
1cce71eb JB |
180 | /* Functions exported from i386-tdep.c. */ |
181 | extern CORE_ADDR i386_pe_skip_trampoline_code (CORE_ADDR pc, char *name); | |
5512c44a | 182 | extern int i386_frameless_signal_p (struct frame_info *frame); |
1cce71eb | 183 | |
8201327c | 184 | /* Return the name of register REG. */ |
fa88f677 | 185 | extern char const *i386_register_name (int reg); |
8201327c | 186 | |
38c968cf AC |
187 | /* Return non-zero if REGNUM is a member of the specified group. */ |
188 | extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
189 | struct reggroup *group); | |
190 | ||
8201327c MK |
191 | /* Initialize a basic ELF architecture variant. */ |
192 | extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *); | |
193 | ||
194 | /* Initialize a SVR4 architecture variant. */ | |
195 | extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *); | |
de0b6abb | 196 | \f |
8201327c | 197 | |
de0b6abb | 198 | /* Functions and variables exported from i386bsd-tdep.c. */ |
8201327c | 199 | |
3cac699e | 200 | extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *); |
de0b6abb MK |
201 | extern CORE_ADDR i386fbsd_sigtramp_start; |
202 | extern CORE_ADDR i386fbsd_sigtramp_end; | |
203 | extern CORE_ADDR i386obsd_sigtramp_start; | |
204 | extern CORE_ADDR i386obsd_sigtramp_end; | |
205 | extern int i386fbsd4_sc_reg_offset[]; | |
206 | extern int i386fbsd_sc_reg_offset[]; | |
207 | extern int i386nbsd_sc_reg_offset[]; | |
208 | extern int i386obsd_sc_reg_offset[]; | |
209 | extern int i386bsd_sc_reg_offset[]; | |
3ce1502b | 210 | |
96297dab | 211 | #endif /* i386-tdep.h */ |