Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Intel 387 floating point stuff. |
38edeab8 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1988-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
786a90bb MK |
21 | #include "doublest.h" |
22 | #include "floatformat.h" | |
c906108c | 23 | #include "frame.h" |
786a90bb | 24 | #include "gdbcore.h" |
c906108c SS |
25 | #include "inferior.h" |
26 | #include "language.h" | |
4e052eda | 27 | #include "regcache.h" |
786a90bb MK |
28 | #include "value.h" |
29 | ||
d0df8472 | 30 | #include "gdb_assert.h" |
0e9f083f | 31 | #include <string.h> |
c906108c | 32 | |
9a82579f | 33 | #include "i386-tdep.h" |
42c466d7 | 34 | #include "i387-tdep.h" |
31aeac78 | 35 | #include "i386-xstate.h" |
c906108c | 36 | |
de57eccd | 37 | /* Print the floating point number specified by RAW. */ |
786a90bb | 38 | |
de57eccd | 39 | static void |
27067745 UW |
40 | print_i387_value (struct gdbarch *gdbarch, |
41 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd JM |
42 | { |
43 | DOUBLEST value; | |
4583280c MK |
44 | |
45 | /* Using extract_typed_floating here might affect the representation | |
46 | of certain numbers such as NaNs, even if GDB is running natively. | |
47 | This is fine since our caller already detects such special | |
48 | numbers and we print the hexadecimal representation anyway. */ | |
27067745 | 49 | value = extract_typed_floating (raw, i387_ext_type (gdbarch)); |
de57eccd JM |
50 | |
51 | /* We try to print 19 digits. The last digit may or may not contain | |
52 | garbage, but we'd better print one too many. We need enough room | |
53 | to print the value, 1 position for the sign, 1 for the decimal | |
54 | point, 19 for the digits and 6 for the exponent adds up to 27. */ | |
55 | #ifdef PRINTF_HAS_LONG_DOUBLE | |
61113f8b | 56 | fprintf_filtered (file, " %-+27.19Lg", (long double) value); |
de57eccd | 57 | #else |
61113f8b | 58 | fprintf_filtered (file, " %-+27.19g", (double) value); |
de57eccd JM |
59 | #endif |
60 | } | |
61 | ||
62 | /* Print the classification for the register contents RAW. */ | |
786a90bb | 63 | |
de57eccd | 64 | static void |
27067745 UW |
65 | print_i387_ext (struct gdbarch *gdbarch, |
66 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd JM |
67 | { |
68 | int sign; | |
69 | int integer; | |
70 | unsigned int exponent; | |
71 | unsigned long fraction[2]; | |
72 | ||
73 | sign = raw[9] & 0x80; | |
74 | integer = raw[7] & 0x80; | |
75 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
76 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
77 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
78 | | (raw[5] << 8) | raw[4]); | |
79 | ||
80 | if (exponent == 0x7fff && integer) | |
81 | { | |
82 | if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000) | |
83 | /* Infinity. */ | |
61113f8b | 84 | fprintf_filtered (file, " %cInf", (sign ? '-' : '+')); |
de57eccd JM |
85 | else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000) |
86 | /* Real Indefinite (QNaN). */ | |
61113f8b | 87 | fputs_unfiltered (" Real Indefinite (QNaN)", file); |
de57eccd JM |
88 | else if (fraction[1] & 0x40000000) |
89 | /* QNaN. */ | |
61113f8b | 90 | fputs_filtered (" QNaN", file); |
de57eccd JM |
91 | else |
92 | /* SNaN. */ | |
61113f8b | 93 | fputs_filtered (" SNaN", file); |
de57eccd JM |
94 | } |
95 | else if (exponent < 0x7fff && exponent > 0x0000 && integer) | |
96 | /* Normal. */ | |
27067745 | 97 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
98 | else if (exponent == 0x0000) |
99 | { | |
100 | /* Denormal or zero. */ | |
27067745 | 101 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
102 | |
103 | if (integer) | |
104 | /* Pseudo-denormal. */ | |
61113f8b | 105 | fputs_filtered (" Pseudo-denormal", file); |
de57eccd JM |
106 | else if (fraction[0] || fraction[1]) |
107 | /* Denormal. */ | |
61113f8b | 108 | fputs_filtered (" Denormal", file); |
de57eccd JM |
109 | } |
110 | else | |
111 | /* Unsupported. */ | |
61113f8b | 112 | fputs_filtered (" Unsupported", file); |
de57eccd JM |
113 | } |
114 | ||
ad5f7d6e PA |
115 | /* Print the status word STATUS. If STATUS_P is false, then STATUS |
116 | was unavailable. */ | |
786a90bb | 117 | |
de57eccd | 118 | static void |
ad5f7d6e PA |
119 | print_i387_status_word (int status_p, |
120 | unsigned int status, struct ui_file *file) | |
de57eccd | 121 | { |
ad5f7d6e PA |
122 | fprintf_filtered (file, "Status Word: "); |
123 | if (!status_p) | |
124 | { | |
125 | fprintf_filtered (file, "%s\n", _("<unavailable>")); | |
126 | return; | |
127 | } | |
128 | ||
129 | fprintf_filtered (file, "%s", hex_string_custom (status, 4)); | |
61113f8b MK |
130 | fputs_filtered (" ", file); |
131 | fprintf_filtered (file, " %s", (status & 0x0001) ? "IE" : " "); | |
132 | fprintf_filtered (file, " %s", (status & 0x0002) ? "DE" : " "); | |
133 | fprintf_filtered (file, " %s", (status & 0x0004) ? "ZE" : " "); | |
134 | fprintf_filtered (file, " %s", (status & 0x0008) ? "OE" : " "); | |
135 | fprintf_filtered (file, " %s", (status & 0x0010) ? "UE" : " "); | |
136 | fprintf_filtered (file, " %s", (status & 0x0020) ? "PE" : " "); | |
137 | fputs_filtered (" ", file); | |
138 | fprintf_filtered (file, " %s", (status & 0x0080) ? "ES" : " "); | |
139 | fputs_filtered (" ", file); | |
140 | fprintf_filtered (file, " %s", (status & 0x0040) ? "SF" : " "); | |
141 | fputs_filtered (" ", file); | |
142 | fprintf_filtered (file, " %s", (status & 0x0100) ? "C0" : " "); | |
143 | fprintf_filtered (file, " %s", (status & 0x0200) ? "C1" : " "); | |
144 | fprintf_filtered (file, " %s", (status & 0x0400) ? "C2" : " "); | |
145 | fprintf_filtered (file, " %s", (status & 0x4000) ? "C3" : " "); | |
146 | ||
147 | fputs_filtered ("\n", file); | |
148 | ||
149 | fprintf_filtered (file, | |
150 | " TOP: %d\n", ((status >> 11) & 7)); | |
de57eccd JM |
151 | } |
152 | ||
ad5f7d6e PA |
153 | /* Print the control word CONTROL. If CONTROL_P is false, then |
154 | CONTROL was unavailable. */ | |
786a90bb | 155 | |
de57eccd | 156 | static void |
ad5f7d6e PA |
157 | print_i387_control_word (int control_p, |
158 | unsigned int control, struct ui_file *file) | |
de57eccd | 159 | { |
ad5f7d6e PA |
160 | fprintf_filtered (file, "Control Word: "); |
161 | if (!control_p) | |
162 | { | |
163 | fprintf_filtered (file, "%s\n", _("<unavailable>")); | |
164 | return; | |
165 | } | |
166 | ||
167 | fprintf_filtered (file, "%s", hex_string_custom (control, 4)); | |
61113f8b MK |
168 | fputs_filtered (" ", file); |
169 | fprintf_filtered (file, " %s", (control & 0x0001) ? "IM" : " "); | |
170 | fprintf_filtered (file, " %s", (control & 0x0002) ? "DM" : " "); | |
171 | fprintf_filtered (file, " %s", (control & 0x0004) ? "ZM" : " "); | |
172 | fprintf_filtered (file, " %s", (control & 0x0008) ? "OM" : " "); | |
173 | fprintf_filtered (file, " %s", (control & 0x0010) ? "UM" : " "); | |
174 | fprintf_filtered (file, " %s", (control & 0x0020) ? "PM" : " "); | |
de57eccd | 175 | |
61113f8b | 176 | fputs_filtered ("\n", file); |
de57eccd | 177 | |
61113f8b | 178 | fputs_filtered (" PC: ", file); |
de57eccd JM |
179 | switch ((control >> 8) & 3) |
180 | { | |
181 | case 0: | |
61113f8b | 182 | fputs_filtered ("Single Precision (24-bits)\n", file); |
de57eccd JM |
183 | break; |
184 | case 1: | |
61113f8b | 185 | fputs_filtered ("Reserved\n", file); |
de57eccd JM |
186 | break; |
187 | case 2: | |
61113f8b | 188 | fputs_filtered ("Double Precision (53-bits)\n", file); |
de57eccd JM |
189 | break; |
190 | case 3: | |
61113f8b | 191 | fputs_filtered ("Extended Precision (64-bits)\n", file); |
de57eccd JM |
192 | break; |
193 | } | |
194 | ||
61113f8b | 195 | fputs_filtered (" RC: ", file); |
de57eccd JM |
196 | switch ((control >> 10) & 3) |
197 | { | |
198 | case 0: | |
61113f8b | 199 | fputs_filtered ("Round to nearest\n", file); |
de57eccd JM |
200 | break; |
201 | case 1: | |
61113f8b | 202 | fputs_filtered ("Round down\n", file); |
de57eccd JM |
203 | break; |
204 | case 2: | |
61113f8b | 205 | fputs_filtered ("Round up\n", file); |
de57eccd JM |
206 | break; |
207 | case 3: | |
61113f8b | 208 | fputs_filtered ("Round toward zero\n", file); |
de57eccd JM |
209 | break; |
210 | } | |
211 | } | |
212 | ||
9b949a49 | 213 | /* Print out the i387 floating point state. Note that we ignore FRAME |
7d8d2918 MK |
214 | in the code below. That's OK since floating-point registers are |
215 | never saved on the stack. */ | |
216 | ||
de57eccd | 217 | void |
61113f8b | 218 | i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
8e186fd6 | 219 | struct frame_info *frame, const char *args) |
de57eccd | 220 | { |
5716833c | 221 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
1d70089a | 222 | ULONGEST fctrl; |
ad5f7d6e | 223 | int fctrl_p; |
1d70089a | 224 | ULONGEST fstat; |
ad5f7d6e | 225 | int fstat_p; |
1d70089a | 226 | ULONGEST ftag; |
ad5f7d6e | 227 | int ftag_p; |
1d70089a | 228 | ULONGEST fiseg; |
ad5f7d6e | 229 | int fiseg_p; |
1d70089a | 230 | ULONGEST fioff; |
ad5f7d6e | 231 | int fioff_p; |
1d70089a | 232 | ULONGEST foseg; |
ad5f7d6e | 233 | int foseg_p; |
1d70089a | 234 | ULONGEST fooff; |
ad5f7d6e | 235 | int fooff_p; |
1d70089a | 236 | ULONGEST fop; |
ad5f7d6e | 237 | int fop_p; |
de57eccd JM |
238 | int fpreg; |
239 | int top; | |
240 | ||
5716833c MK |
241 | gdb_assert (gdbarch == get_frame_arch (frame)); |
242 | ||
ad5f7d6e PA |
243 | fctrl_p = read_frame_register_unsigned (frame, |
244 | I387_FCTRL_REGNUM (tdep), &fctrl); | |
245 | fstat_p = read_frame_register_unsigned (frame, | |
246 | I387_FSTAT_REGNUM (tdep), &fstat); | |
247 | ftag_p = read_frame_register_unsigned (frame, | |
248 | I387_FTAG_REGNUM (tdep), &ftag); | |
249 | fiseg_p = read_frame_register_unsigned (frame, | |
250 | I387_FISEG_REGNUM (tdep), &fiseg); | |
251 | fioff_p = read_frame_register_unsigned (frame, | |
252 | I387_FIOFF_REGNUM (tdep), &fioff); | |
253 | foseg_p = read_frame_register_unsigned (frame, | |
254 | I387_FOSEG_REGNUM (tdep), &foseg); | |
255 | fooff_p = read_frame_register_unsigned (frame, | |
256 | I387_FOOFF_REGNUM (tdep), &fooff); | |
257 | fop_p = read_frame_register_unsigned (frame, | |
258 | I387_FOP_REGNUM (tdep), &fop); | |
259 | ||
260 | if (fstat_p) | |
de57eccd | 261 | { |
ad5f7d6e | 262 | top = ((fstat >> 11) & 7); |
de57eccd | 263 | |
ad5f7d6e | 264 | for (fpreg = 7; fpreg >= 0; fpreg--) |
de57eccd | 265 | { |
ad5f7d6e PA |
266 | struct value *regval; |
267 | int regnum; | |
268 | int i; | |
269 | int tag = -1; | |
270 | ||
271 | fprintf_filtered (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); | |
272 | ||
273 | if (ftag_p) | |
274 | { | |
275 | tag = (ftag >> (fpreg * 2)) & 3; | |
276 | ||
277 | switch (tag) | |
278 | { | |
279 | case 0: | |
280 | fputs_filtered ("Valid ", file); | |
281 | break; | |
282 | case 1: | |
283 | fputs_filtered ("Zero ", file); | |
284 | break; | |
285 | case 2: | |
286 | fputs_filtered ("Special ", file); | |
287 | break; | |
288 | case 3: | |
289 | fputs_filtered ("Empty ", file); | |
290 | break; | |
291 | } | |
292 | } | |
293 | else | |
294 | fputs_filtered ("Unknown ", file); | |
295 | ||
296 | regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); | |
297 | regval = get_frame_register_value (frame, regnum); | |
298 | ||
299 | if (value_entirely_available (regval)) | |
300 | { | |
433730c9 | 301 | const gdb_byte *raw = value_contents (regval); |
ad5f7d6e PA |
302 | |
303 | fputs_filtered ("0x", file); | |
304 | for (i = 9; i >= 0; i--) | |
305 | fprintf_filtered (file, "%02x", raw[i]); | |
306 | ||
307 | if (tag != -1 && tag != 3) | |
308 | print_i387_ext (gdbarch, raw, file); | |
309 | } | |
310 | else | |
311 | fprintf_filtered (file, "%s", _("<unavailable>")); | |
312 | ||
313 | fputs_filtered ("\n", file); | |
de57eccd | 314 | } |
de57eccd JM |
315 | } |
316 | ||
f16a25ae | 317 | fputs_filtered ("\n", file); |
ad5f7d6e PA |
318 | print_i387_status_word (fstat_p, fstat, file); |
319 | print_i387_control_word (fctrl_p, fctrl, file); | |
61113f8b | 320 | fprintf_filtered (file, "Tag Word: %s\n", |
ad5f7d6e | 321 | ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>")); |
61113f8b | 322 | fprintf_filtered (file, "Instruction Pointer: %s:", |
ad5f7d6e PA |
323 | fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>")); |
324 | fprintf_filtered (file, "%s\n", | |
325 | fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>")); | |
61113f8b | 326 | fprintf_filtered (file, "Operand Pointer: %s:", |
ad5f7d6e PA |
327 | foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>")); |
328 | fprintf_filtered (file, "%s\n", | |
329 | fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>")); | |
61113f8b | 330 | fprintf_filtered (file, "Opcode: %s\n", |
ad5f7d6e PA |
331 | fop_p |
332 | ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) | |
333 | : _("<unavailable>")); | |
de57eccd | 334 | } |
d532c08f MK |
335 | \f |
336 | ||
83acabca DJ |
337 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
338 | needs any special handling. */ | |
339 | ||
340 | int | |
1777feb0 MS |
341 | i387_convert_register_p (struct gdbarch *gdbarch, int regnum, |
342 | struct type *type) | |
83acabca | 343 | { |
20a6ec49 | 344 | if (i386_fp_regnum_p (gdbarch, regnum)) |
83acabca DJ |
345 | { |
346 | /* Floating point registers must be converted unless we are | |
347 | accessing them in their hardware type. */ | |
27067745 | 348 | if (type == i387_ext_type (gdbarch)) |
83acabca DJ |
349 | return 0; |
350 | else | |
351 | return 1; | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
d532c08f MK |
357 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
358 | return its contents in TO. */ | |
359 | ||
8dccd430 | 360 | int |
d532c08f | 361 | i387_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
362 | struct type *type, gdb_byte *to, |
363 | int *optimizedp, int *unavailablep) | |
d532c08f | 364 | { |
27067745 | 365 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 366 | gdb_byte from[I386_MAX_REGISTER_SIZE]; |
d532c08f | 367 | |
27067745 | 368 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
369 | |
370 | /* We only support floating-point values. */ | |
371 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
372 | { | |
8a3fe4f8 AC |
373 | warning (_("Cannot convert floating-point register value " |
374 | "to non-floating-point type.")); | |
8dccd430 PA |
375 | *optimizedp = *unavailablep = 0; |
376 | return 0; | |
d532c08f MK |
377 | } |
378 | ||
83acabca | 379 | /* Convert to TYPE. */ |
8dccd430 PA |
380 | if (!get_frame_register_bytes (frame, regnum, 0, TYPE_LENGTH (type), |
381 | from, optimizedp, unavailablep)) | |
382 | return 0; | |
383 | ||
27067745 | 384 | convert_typed_floating (from, i387_ext_type (gdbarch), to, type); |
8dccd430 PA |
385 | *optimizedp = *unavailablep = 0; |
386 | return 1; | |
d532c08f MK |
387 | } |
388 | ||
389 | /* Write the contents FROM of a value of type TYPE into register | |
390 | REGNUM in frame FRAME. */ | |
391 | ||
392 | void | |
393 | i387_value_to_register (struct frame_info *frame, int regnum, | |
42835c2b | 394 | struct type *type, const gdb_byte *from) |
d532c08f | 395 | { |
27067745 | 396 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 397 | gdb_byte to[I386_MAX_REGISTER_SIZE]; |
d532c08f | 398 | |
27067745 | 399 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
400 | |
401 | /* We only support floating-point values. */ | |
402 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
403 | { | |
8a3fe4f8 AC |
404 | warning (_("Cannot convert non-floating-point type " |
405 | "to floating-point register value.")); | |
d532c08f MK |
406 | return; |
407 | } | |
408 | ||
83acabca | 409 | /* Convert from TYPE. */ |
27067745 | 410 | convert_typed_floating (from, type, to, i387_ext_type (gdbarch)); |
d532c08f MK |
411 | put_frame_register (frame, regnum, to); |
412 | } | |
413 | \f | |
e750d25e | 414 | |
786a90bb | 415 | /* Handle FSAVE and FXSAVE formats. */ |
e750d25e JT |
416 | |
417 | /* At fsave_offset[REGNUM] you'll find the offset to the location in | |
418 | the data structure used by the "fsave" instruction where GDB | |
419 | register REGNUM is stored. */ | |
420 | ||
421 | static int fsave_offset[] = | |
422 | { | |
5716833c MK |
423 | 28 + 0 * 10, /* %st(0) ... */ |
424 | 28 + 1 * 10, | |
425 | 28 + 2 * 10, | |
426 | 28 + 3 * 10, | |
427 | 28 + 4 * 10, | |
428 | 28 + 5 * 10, | |
429 | 28 + 6 * 10, | |
430 | 28 + 7 * 10, /* ... %st(7). */ | |
431 | 0, /* `fctrl' (16 bits). */ | |
432 | 4, /* `fstat' (16 bits). */ | |
433 | 8, /* `ftag' (16 bits). */ | |
434 | 16, /* `fiseg' (16 bits). */ | |
435 | 12, /* `fioff'. */ | |
436 | 24, /* `foseg' (16 bits). */ | |
437 | 20, /* `fooff'. */ | |
438 | 18 /* `fop' (bottom 11 bits). */ | |
e750d25e JT |
439 | }; |
440 | ||
20a6ec49 MD |
441 | #define FSAVE_ADDR(tdep, fsave, regnum) \ |
442 | (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
e750d25e JT |
443 | \f |
444 | ||
41d041d6 MK |
445 | /* Fill register REGNUM in REGCACHE with the appropriate value from |
446 | *FSAVE. This function masks off any of the reserved bits in | |
447 | *FSAVE. */ | |
e750d25e JT |
448 | |
449 | void | |
41d041d6 | 450 | i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) |
e750d25e | 451 | { |
e17a4113 UW |
452 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
453 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
454 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
b4ad899f | 455 | const gdb_byte *regs = fsave; |
e750d25e JT |
456 | int i; |
457 | ||
5716833c MK |
458 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
459 | ||
20a6ec49 | 460 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
ed504bdf MK |
461 | if (regnum == -1 || regnum == i) |
462 | { | |
463 | if (fsave == NULL) | |
464 | { | |
5716833c MK |
465 | regcache_raw_supply (regcache, i, NULL); |
466 | continue; | |
ed504bdf MK |
467 | } |
468 | ||
469 | /* Most of the FPU control registers occupy only 16 bits in the | |
470 | fsave area. Give those a special treatment. */ | |
20a6ec49 MD |
471 | if (i >= I387_FCTRL_REGNUM (tdep) |
472 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 473 | { |
b4ad899f | 474 | gdb_byte val[4]; |
ed504bdf | 475 | |
20a6ec49 | 476 | memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 477 | val[2] = val[3] = 0; |
20a6ec49 | 478 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 479 | val[1] &= ((1 << 3) - 1); |
5716833c | 480 | regcache_raw_supply (regcache, i, val); |
ed504bdf MK |
481 | } |
482 | else | |
20a6ec49 | 483 | regcache_raw_supply (regcache, i, FSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 484 | } |
b87bc0d8 MK |
485 | |
486 | /* Provide dummy values for the SSE registers. */ | |
20a6ec49 | 487 | for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
b87bc0d8 MK |
488 | if (regnum == -1 || regnum == i) |
489 | regcache_raw_supply (regcache, i, NULL); | |
20a6ec49 | 490 | if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) |
b87bc0d8 | 491 | { |
b4ad899f | 492 | gdb_byte buf[4]; |
b87bc0d8 | 493 | |
e17a4113 | 494 | store_unsigned_integer (buf, 4, byte_order, 0x1f80); |
20a6ec49 | 495 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), buf); |
b87bc0d8 | 496 | } |
e750d25e JT |
497 | } |
498 | ||
499 | /* Fill register REGNUM (if it is a floating-point register) in *FSAVE | |
63b6c53f MK |
500 | with the value from REGCACHE. If REGNUM is -1, do this for all |
501 | registers. This function doesn't touch any of the reserved bits in | |
502 | *FSAVE. */ | |
e750d25e JT |
503 | |
504 | void | |
63b6c53f | 505 | i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) |
e750d25e | 506 | { |
e071d1f6 | 507 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
b4ad899f | 508 | gdb_byte *regs = fsave; |
e750d25e JT |
509 | int i; |
510 | ||
5716833c MK |
511 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
512 | ||
20a6ec49 | 513 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
e750d25e JT |
514 | if (regnum == -1 || regnum == i) |
515 | { | |
516 | /* Most of the FPU control registers occupy only 16 bits in | |
517 | the fsave area. Give those a special treatment. */ | |
20a6ec49 MD |
518 | if (i >= I387_FCTRL_REGNUM (tdep) |
519 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 520 | { |
b4ad899f | 521 | gdb_byte buf[4]; |
e750d25e | 522 | |
5716833c | 523 | regcache_raw_collect (regcache, i, buf); |
e750d25e | 524 | |
20a6ec49 | 525 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
526 | { |
527 | /* The opcode occupies only 11 bits. Make sure we | |
528 | don't touch the other bits. */ | |
529 | buf[1] &= ((1 << 3) - 1); | |
20a6ec49 | 530 | buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 531 | } |
20a6ec49 | 532 | memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); |
e750d25e JT |
533 | } |
534 | else | |
20a6ec49 | 535 | regcache_raw_collect (regcache, i, FSAVE_ADDR (tdep, regs, i)); |
e750d25e JT |
536 | } |
537 | } | |
538 | \f | |
539 | ||
540 | /* At fxsave_offset[REGNUM] you'll find the offset to the location in | |
541 | the data structure used by the "fxsave" instruction where GDB | |
542 | register REGNUM is stored. */ | |
543 | ||
544 | static int fxsave_offset[] = | |
545 | { | |
5716833c | 546 | 32, /* %st(0) through ... */ |
e750d25e JT |
547 | 48, |
548 | 64, | |
549 | 80, | |
550 | 96, | |
551 | 112, | |
552 | 128, | |
5716833c MK |
553 | 144, /* ... %st(7) (80 bits each). */ |
554 | 0, /* `fctrl' (16 bits). */ | |
555 | 2, /* `fstat' (16 bits). */ | |
556 | 4, /* `ftag' (16 bits). */ | |
557 | 12, /* `fiseg' (16 bits). */ | |
558 | 8, /* `fioff'. */ | |
559 | 20, /* `foseg' (16 bits). */ | |
560 | 16, /* `fooff'. */ | |
561 | 6, /* `fop' (bottom 11 bits). */ | |
562 | 160 + 0 * 16, /* %xmm0 through ... */ | |
04c8243f MK |
563 | 160 + 1 * 16, |
564 | 160 + 2 * 16, | |
565 | 160 + 3 * 16, | |
566 | 160 + 4 * 16, | |
567 | 160 + 5 * 16, | |
568 | 160 + 6 * 16, | |
569 | 160 + 7 * 16, | |
570 | 160 + 8 * 16, | |
571 | 160 + 9 * 16, | |
572 | 160 + 10 * 16, | |
573 | 160 + 11 * 16, | |
574 | 160 + 12 * 16, | |
575 | 160 + 13 * 16, | |
576 | 160 + 14 * 16, | |
5716833c | 577 | 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ |
e750d25e JT |
578 | }; |
579 | ||
20a6ec49 MD |
580 | #define FXSAVE_ADDR(tdep, fxsave, regnum) \ |
581 | (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
5716833c MK |
582 | |
583 | /* We made an unfortunate choice in putting %mxcsr after the SSE | |
584 | registers %xmm0-%xmm7 instead of before, since it makes supporting | |
585 | the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we | |
586 | don't include the offset for %mxcsr here above. */ | |
587 | ||
588 | #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24) | |
e750d25e | 589 | |
b4ad899f | 590 | static int i387_tag (const gdb_byte *raw); |
e750d25e JT |
591 | \f |
592 | ||
41d041d6 | 593 | /* Fill register REGNUM in REGCACHE with the appropriate |
ed504bdf MK |
594 | floating-point or SSE register value from *FXSAVE. This function |
595 | masks off any of the reserved bits in *FXSAVE. */ | |
e750d25e JT |
596 | |
597 | void | |
41d041d6 | 598 | i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) |
e750d25e | 599 | { |
41d041d6 | 600 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
b4ad899f | 601 | const gdb_byte *regs = fxsave; |
5716833c MK |
602 | int i; |
603 | ||
604 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
605 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 606 | |
20a6ec49 | 607 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
ed504bdf MK |
608 | if (regnum == -1 || regnum == i) |
609 | { | |
5716833c | 610 | if (regs == NULL) |
ed504bdf | 611 | { |
5716833c | 612 | regcache_raw_supply (regcache, i, NULL); |
ed504bdf MK |
613 | continue; |
614 | } | |
932bb524 | 615 | |
ed504bdf MK |
616 | /* Most of the FPU control registers occupy only 16 bits in |
617 | the fxsave area. Give those a special treatment. */ | |
20a6ec49 MD |
618 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
619 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 620 | { |
b4ad899f | 621 | gdb_byte val[4]; |
ed504bdf | 622 | |
20a6ec49 | 623 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 624 | val[2] = val[3] = 0; |
20a6ec49 | 625 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 626 | val[1] &= ((1 << 3) - 1); |
20a6ec49 | 627 | else if (i== I387_FTAG_REGNUM (tdep)) |
ed504bdf MK |
628 | { |
629 | /* The fxsave area contains a simplified version of | |
630 | the tag word. We have to look at the actual 80-bit | |
631 | FP data to recreate the traditional i387 tag word. */ | |
632 | ||
633 | unsigned long ftag = 0; | |
634 | int fpreg; | |
635 | int top; | |
636 | ||
20a6ec49 MD |
637 | top = ((FXSAVE_ADDR (tdep, regs, |
638 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
5716833c | 639 | top &= 0x7; |
ed504bdf MK |
640 | |
641 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
642 | { | |
643 | int tag; | |
644 | ||
645 | if (val[0] & (1 << fpreg)) | |
646 | { | |
6d5e094a MS |
647 | int thisreg = (fpreg + 8 - top) % 8 |
648 | + I387_ST0_REGNUM (tdep); | |
649 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); | |
ed504bdf MK |
650 | } |
651 | else | |
652 | tag = 3; /* Empty */ | |
653 | ||
654 | ftag |= tag << (2 * fpreg); | |
655 | } | |
656 | val[0] = ftag & 0xff; | |
657 | val[1] = (ftag >> 8) & 0xff; | |
658 | } | |
5716833c | 659 | regcache_raw_supply (regcache, i, val); |
ed504bdf MK |
660 | } |
661 | else | |
20a6ec49 | 662 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 663 | } |
5716833c | 664 | |
20a6ec49 | 665 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
5716833c MK |
666 | { |
667 | if (regs == NULL) | |
20a6ec49 | 668 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), NULL); |
5716833c | 669 | else |
20a6ec49 | 670 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), |
5716833c MK |
671 | FXSAVE_MXCSR_ADDR (regs)); |
672 | } | |
e750d25e JT |
673 | } |
674 | ||
675 | /* Fill register REGNUM (if it is a floating-point or SSE register) in | |
80571bff MK |
676 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for |
677 | all registers. This function doesn't touch any of the reserved | |
678 | bits in *FXSAVE. */ | |
e750d25e JT |
679 | |
680 | void | |
80571bff | 681 | i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) |
e750d25e | 682 | { |
e071d1f6 | 683 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
b4ad899f | 684 | gdb_byte *regs = fxsave; |
5716833c MK |
685 | int i; |
686 | ||
687 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
688 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 689 | |
20a6ec49 | 690 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
e750d25e JT |
691 | if (regnum == -1 || regnum == i) |
692 | { | |
693 | /* Most of the FPU control registers occupy only 16 bits in | |
694 | the fxsave area. Give those a special treatment. */ | |
20a6ec49 MD |
695 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
696 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 697 | { |
b4ad899f | 698 | gdb_byte buf[4]; |
e750d25e | 699 | |
5716833c | 700 | regcache_raw_collect (regcache, i, buf); |
e750d25e | 701 | |
31aeac78 L |
702 | if (i == I387_FOP_REGNUM (tdep)) |
703 | { | |
704 | /* The opcode occupies only 11 bits. Make sure we | |
705 | don't touch the other bits. */ | |
706 | buf[1] &= ((1 << 3) - 1); | |
707 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); | |
708 | } | |
709 | else if (i == I387_FTAG_REGNUM (tdep)) | |
710 | { | |
711 | /* Converting back is much easier. */ | |
712 | ||
713 | unsigned short ftag; | |
714 | int fpreg; | |
715 | ||
716 | ftag = (buf[1] << 8) | buf[0]; | |
717 | buf[0] = 0; | |
718 | buf[1] = 0; | |
719 | ||
720 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
721 | { | |
722 | int tag = (ftag >> (fpreg * 2)) & 3; | |
723 | ||
724 | if (tag != 3) | |
725 | buf[0] |= (1 << fpreg); | |
726 | } | |
727 | } | |
728 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); | |
729 | } | |
730 | else | |
731 | regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
732 | } | |
733 | ||
734 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
735 | regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), | |
736 | FXSAVE_MXCSR_ADDR (regs)); | |
737 | } | |
738 | ||
739 | /* `xstate_bv' is at byte offset 512. */ | |
740 | #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) | |
741 | ||
742 | /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in | |
743 | the upper 128bit of AVX register data structure used by the "xsave" | |
744 | instruction where GDB register REGNUM is stored. */ | |
745 | ||
746 | static int xsave_avxh_offset[] = | |
747 | { | |
748 | 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ | |
749 | 576 + 1 * 16, | |
750 | 576 + 2 * 16, | |
751 | 576 + 3 * 16, | |
752 | 576 + 4 * 16, | |
753 | 576 + 5 * 16, | |
754 | 576 + 6 * 16, | |
755 | 576 + 7 * 16, | |
756 | 576 + 8 * 16, | |
757 | 576 + 9 * 16, | |
758 | 576 + 10 * 16, | |
759 | 576 + 11 * 16, | |
760 | 576 + 12 * 16, | |
761 | 576 + 13 * 16, | |
762 | 576 + 14 * 16, | |
763 | 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ | |
764 | }; | |
765 | ||
1dbcd68c WT |
766 | static int xsave_mpx_offset[] = |
767 | { | |
768 | 960 + 0 * 16, /* bnd0r...bnd3r registers. */ | |
769 | 960 + 1 * 16, | |
770 | 960 + 2 * 16, | |
771 | 960 + 3 * 16, | |
772 | 1024 + 0 * 8, /* bndcfg ... bndstatus. */ | |
773 | 1024 + 1 * 8, | |
774 | }; | |
775 | ||
31aeac78 L |
776 | #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ |
777 | (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) | |
778 | ||
1dbcd68c WT |
779 | #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ |
780 | (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) | |
781 | ||
31aeac78 L |
782 | /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ |
783 | ||
784 | void | |
785 | i387_supply_xsave (struct regcache *regcache, int regnum, | |
786 | const void *xsave) | |
787 | { | |
788 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); | |
789 | const gdb_byte *regs = xsave; | |
790 | int i; | |
791 | unsigned int clear_bv; | |
b4d36fb8 | 792 | static const gdb_byte zero[MAX_REGISTER_SIZE] = { 0 }; |
31aeac78 L |
793 | enum |
794 | { | |
795 | none = 0x0, | |
796 | x87 = 0x1, | |
797 | sse = 0x2, | |
798 | avxh = 0x4, | |
1dbcd68c WT |
799 | mpx = 0x8, |
800 | all = x87 | sse | avxh | mpx | |
31aeac78 L |
801 | } regclass; |
802 | ||
275418ae | 803 | gdb_assert (regs != NULL); |
31aeac78 L |
804 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
805 | gdb_assert (tdep->num_xmm_regs > 0); | |
806 | ||
807 | if (regnum == -1) | |
808 | regclass = all; | |
809 | else if (regnum >= I387_YMM0H_REGNUM (tdep) | |
810 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
811 | regclass = avxh; | |
1dbcd68c WT |
812 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
813 | && regnum < I387_MPXEND_REGNUM (tdep)) | |
814 | regclass = mpx; | |
31aeac78 L |
815 | else if (regnum >= I387_XMM0_REGNUM(tdep) |
816 | && regnum < I387_MXCSR_REGNUM (tdep)) | |
817 | regclass = sse; | |
818 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
819 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
820 | regclass = x87; | |
821 | else | |
822 | regclass = none; | |
823 | ||
275418ae | 824 | if (regclass != none) |
31aeac78 L |
825 | { |
826 | /* Get `xstat_bv'. */ | |
827 | const gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs); | |
828 | ||
829 | /* The supported bits in `xstat_bv' are 1 byte. Clear part in | |
830 | vector registers if its bit in xstat_bv is zero. */ | |
831 | clear_bv = (~(*xstate_bv_p)) & tdep->xcr0; | |
832 | } | |
833 | else | |
1dbcd68c | 834 | clear_bv = I386_XSTATE_ALL_MASK; |
31aeac78 | 835 | |
b4d36fb8 PA |
836 | /* With the delayed xsave mechanism, in between the program |
837 | starting, and the program accessing the vector registers for the | |
838 | first time, the register's values are invalid. The kernel | |
839 | initializes register states to zero when they are set the first | |
840 | time in a program. This means that from the user-space programs' | |
841 | perspective, it's the same as if the registers have always been | |
842 | zero from the start of the program. Therefore, the debugger | |
275418ae | 843 | should provide the same illusion to the user. */ |
b4d36fb8 | 844 | |
31aeac78 L |
845 | switch (regclass) |
846 | { | |
847 | case none: | |
848 | break; | |
849 | ||
850 | case avxh: | |
851 | if ((clear_bv & I386_XSTATE_AVX)) | |
275418ae | 852 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 853 | else |
b4d36fb8 PA |
854 | regcache_raw_supply (regcache, regnum, |
855 | XSAVE_AVXH_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
856 | return; |
857 | ||
1dbcd68c WT |
858 | case mpx: |
859 | if ((clear_bv & I386_XSTATE_BNDREGS)) | |
860 | regcache_raw_supply (regcache, regnum, zero); | |
861 | else | |
862 | regcache_raw_supply (regcache, regnum, | |
863 | XSAVE_MPX_ADDR (tdep, regs, regnum)); | |
864 | return; | |
865 | ||
31aeac78 L |
866 | case sse: |
867 | if ((clear_bv & I386_XSTATE_SSE)) | |
275418ae | 868 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 869 | else |
b4d36fb8 PA |
870 | regcache_raw_supply (regcache, regnum, |
871 | FXSAVE_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
872 | return; |
873 | ||
874 | case x87: | |
875 | if ((clear_bv & I386_XSTATE_X87)) | |
275418ae | 876 | regcache_raw_supply (regcache, regnum, zero); |
31aeac78 | 877 | else |
b4d36fb8 PA |
878 | regcache_raw_supply (regcache, regnum, |
879 | FXSAVE_ADDR (tdep, regs, regnum)); | |
31aeac78 L |
880 | return; |
881 | ||
882 | case all: | |
86d31898 | 883 | /* Handle the upper YMM registers. */ |
31aeac78 L |
884 | if ((tdep->xcr0 & I386_XSTATE_AVX)) |
885 | { | |
886 | if ((clear_bv & I386_XSTATE_AVX)) | |
b4d36fb8 PA |
887 | { |
888 | for (i = I387_YMM0H_REGNUM (tdep); | |
889 | i < I387_YMMENDH_REGNUM (tdep); | |
890 | i++) | |
275418ae | 891 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 892 | } |
31aeac78 | 893 | else |
31aeac78 | 894 | { |
b4d36fb8 PA |
895 | for (i = I387_YMM0H_REGNUM (tdep); |
896 | i < I387_YMMENDH_REGNUM (tdep); | |
897 | i++) | |
898 | regcache_raw_supply (regcache, i, | |
899 | XSAVE_AVXH_ADDR (tdep, regs, i)); | |
31aeac78 L |
900 | } |
901 | } | |
902 | ||
1dbcd68c WT |
903 | /* Handle the MPX registers. */ |
904 | if ((tdep->xcr0 & I386_XSTATE_BNDREGS)) | |
905 | { | |
906 | if (clear_bv & I386_XSTATE_BNDREGS) | |
907 | { | |
908 | for (i = I387_BND0R_REGNUM (tdep); | |
909 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
910 | regcache_raw_supply (regcache, i, zero); | |
911 | } | |
912 | else | |
913 | { | |
914 | for (i = I387_BND0R_REGNUM (tdep); | |
915 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
916 | regcache_raw_supply (regcache, i, | |
917 | XSAVE_MPX_ADDR (tdep, regs, i)); | |
918 | } | |
919 | } | |
920 | ||
921 | /* Handle the MPX registers. */ | |
922 | if ((tdep->xcr0 & I386_XSTATE_BNDCFG)) | |
923 | { | |
924 | if (clear_bv & I386_XSTATE_BNDCFG) | |
925 | { | |
926 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
927 | i < I387_MPXEND_REGNUM (tdep); i++) | |
928 | regcache_raw_supply (regcache, i, zero); | |
929 | } | |
930 | else | |
931 | { | |
932 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
933 | i < I387_MPXEND_REGNUM (tdep); i++) | |
934 | regcache_raw_supply (regcache, i, | |
935 | XSAVE_MPX_ADDR (tdep, regs, i)); | |
936 | } | |
937 | } | |
938 | ||
31aeac78 L |
939 | /* Handle the XMM registers. */ |
940 | if ((tdep->xcr0 & I386_XSTATE_SSE)) | |
941 | { | |
942 | if ((clear_bv & I386_XSTATE_SSE)) | |
b4d36fb8 PA |
943 | { |
944 | for (i = I387_XMM0_REGNUM (tdep); | |
945 | i < I387_MXCSR_REGNUM (tdep); | |
946 | i++) | |
275418ae | 947 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 948 | } |
31aeac78 | 949 | else |
31aeac78 | 950 | { |
b4d36fb8 PA |
951 | for (i = I387_XMM0_REGNUM (tdep); |
952 | i < I387_MXCSR_REGNUM (tdep); i++) | |
953 | regcache_raw_supply (regcache, i, | |
954 | FXSAVE_ADDR (tdep, regs, i)); | |
31aeac78 L |
955 | } |
956 | } | |
957 | ||
958 | /* Handle the x87 registers. */ | |
959 | if ((tdep->xcr0 & I386_XSTATE_X87)) | |
960 | { | |
961 | if ((clear_bv & I386_XSTATE_X87)) | |
b4d36fb8 PA |
962 | { |
963 | for (i = I387_ST0_REGNUM (tdep); | |
964 | i < I387_FCTRL_REGNUM (tdep); | |
965 | i++) | |
275418ae | 966 | regcache_raw_supply (regcache, i, zero); |
b4d36fb8 | 967 | } |
31aeac78 | 968 | else |
31aeac78 | 969 | { |
b4d36fb8 PA |
970 | for (i = I387_ST0_REGNUM (tdep); |
971 | i < I387_FCTRL_REGNUM (tdep); | |
972 | i++) | |
973 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
31aeac78 L |
974 | } |
975 | } | |
976 | break; | |
977 | } | |
978 | ||
979 | /* Only handle x87 control registers. */ | |
980 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
981 | if (regnum == -1 || regnum == i) | |
982 | { | |
31aeac78 L |
983 | /* Most of the FPU control registers occupy only 16 bits in |
984 | the xsave extended state. Give those a special treatment. */ | |
985 | if (i != I387_FIOFF_REGNUM (tdep) | |
986 | && i != I387_FOOFF_REGNUM (tdep)) | |
987 | { | |
988 | gdb_byte val[4]; | |
989 | ||
990 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); | |
991 | val[2] = val[3] = 0; | |
992 | if (i == I387_FOP_REGNUM (tdep)) | |
993 | val[1] &= ((1 << 3) - 1); | |
994 | else if (i== I387_FTAG_REGNUM (tdep)) | |
995 | { | |
996 | /* The fxsave area contains a simplified version of | |
997 | the tag word. We have to look at the actual 80-bit | |
998 | FP data to recreate the traditional i387 tag word. */ | |
999 | ||
1000 | unsigned long ftag = 0; | |
1001 | int fpreg; | |
1002 | int top; | |
1003 | ||
1004 | top = ((FXSAVE_ADDR (tdep, regs, | |
1005 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
1006 | top &= 0x7; | |
1007 | ||
1008 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1009 | { | |
1010 | int tag; | |
1011 | ||
1012 | if (val[0] & (1 << fpreg)) | |
1013 | { | |
e5b3d7d6 | 1014 | int thisreg = (fpreg + 8 - top) % 8 |
31aeac78 | 1015 | + I387_ST0_REGNUM (tdep); |
e5b3d7d6 | 1016 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
31aeac78 L |
1017 | } |
1018 | else | |
1019 | tag = 3; /* Empty */ | |
1020 | ||
1021 | ftag |= tag << (2 * fpreg); | |
1022 | } | |
1023 | val[0] = ftag & 0xff; | |
1024 | val[1] = (ftag >> 8) & 0xff; | |
1025 | } | |
1026 | regcache_raw_supply (regcache, i, val); | |
1027 | } | |
1028 | else | |
1029 | regcache_raw_supply (regcache, i, FXSAVE_ADDR (tdep, regs, i)); | |
1030 | } | |
1031 | ||
1032 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
275418ae PA |
1033 | regcache_raw_supply (regcache, I387_MXCSR_REGNUM (tdep), |
1034 | FXSAVE_MXCSR_ADDR (regs)); | |
31aeac78 L |
1035 | } |
1036 | ||
1037 | /* Similar to i387_collect_fxsave, but use XSAVE extended state. */ | |
1038 | ||
1039 | void | |
1040 | i387_collect_xsave (const struct regcache *regcache, int regnum, | |
1041 | void *xsave, int gcore) | |
1042 | { | |
1043 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); | |
1044 | gdb_byte *regs = xsave; | |
1045 | int i; | |
1046 | enum | |
1047 | { | |
1048 | none = 0x0, | |
1049 | check = 0x1, | |
1050 | x87 = 0x2 | check, | |
1051 | sse = 0x4 | check, | |
1052 | avxh = 0x8 | check, | |
1dbcd68c WT |
1053 | mpx = 0x10 | check, |
1054 | all = x87 | sse | avxh | mpx | |
31aeac78 L |
1055 | } regclass; |
1056 | ||
1057 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
1058 | gdb_assert (tdep->num_xmm_regs > 0); | |
1059 | ||
1060 | if (regnum == -1) | |
1061 | regclass = all; | |
1062 | else if (regnum >= I387_YMM0H_REGNUM (tdep) | |
1063 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
1064 | regclass = avxh; | |
1dbcd68c WT |
1065 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
1066 | && regnum < I387_MPXEND_REGNUM (tdep)) | |
1067 | regclass = mpx; | |
1068 | else if (regnum >= I387_XMM0_REGNUM (tdep) | |
31aeac78 L |
1069 | && regnum < I387_MXCSR_REGNUM (tdep)) |
1070 | regclass = sse; | |
1071 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
1072 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
1073 | regclass = x87; | |
1074 | else | |
1075 | regclass = none; | |
1076 | ||
1077 | if (gcore) | |
1078 | { | |
1079 | /* Clear XSAVE extended state. */ | |
1080 | memset (regs, 0, I386_XSTATE_SIZE (tdep->xcr0)); | |
1081 | ||
1082 | /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ | |
1083 | if (tdep->xsave_xcr0_offset != -1) | |
1084 | memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); | |
1085 | memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); | |
1086 | } | |
1087 | ||
1088 | if ((regclass & check)) | |
1089 | { | |
1090 | gdb_byte raw[I386_MAX_REGISTER_SIZE]; | |
1091 | gdb_byte *xstate_bv_p = XSAVE_XSTATE_BV_ADDR (regs); | |
1092 | unsigned int xstate_bv = 0; | |
1777feb0 | 1093 | /* The supported bits in `xstat_bv' are 1 byte. */ |
31aeac78 L |
1094 | unsigned int clear_bv = (~(*xstate_bv_p)) & tdep->xcr0; |
1095 | gdb_byte *p; | |
1096 | ||
1097 | /* Clear register set if its bit in xstat_bv is zero. */ | |
1098 | if (clear_bv) | |
1099 | { | |
1dbcd68c WT |
1100 | if ((clear_bv & I386_XSTATE_BNDREGS)) |
1101 | for (i = I387_BND0R_REGNUM (tdep); | |
1102 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1103 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); | |
1104 | ||
1105 | if ((clear_bv & I386_XSTATE_BNDCFG)) | |
1106 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1107 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1108 | memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); | |
1109 | ||
31aeac78 L |
1110 | if ((clear_bv & I386_XSTATE_AVX)) |
1111 | for (i = I387_YMM0H_REGNUM (tdep); | |
1112 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1113 | memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); | |
1114 | ||
1115 | if ((clear_bv & I386_XSTATE_SSE)) | |
1116 | for (i = I387_XMM0_REGNUM (tdep); | |
1117 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1118 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); | |
1119 | ||
1120 | if ((clear_bv & I386_XSTATE_X87)) | |
1121 | for (i = I387_ST0_REGNUM (tdep); | |
1122 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1123 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); | |
1124 | } | |
1125 | ||
1126 | if (regclass == all) | |
1127 | { | |
1128 | /* Check if any upper YMM registers are changed. */ | |
1129 | if ((tdep->xcr0 & I386_XSTATE_AVX)) | |
1130 | for (i = I387_YMM0H_REGNUM (tdep); | |
1131 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1132 | { | |
1133 | regcache_raw_collect (regcache, i, raw); | |
1134 | p = XSAVE_AVXH_ADDR (tdep, regs, i); | |
1135 | if (memcmp (raw, p, 16)) | |
1136 | { | |
1137 | xstate_bv |= I386_XSTATE_AVX; | |
1138 | memcpy (p, raw, 16); | |
1139 | } | |
1140 | } | |
1dbcd68c WT |
1141 | /* Check if any upper MPX registers are changed. */ |
1142 | if ((tdep->xcr0 & I386_XSTATE_BNDREGS)) | |
1143 | for (i = I387_BND0R_REGNUM (tdep); | |
1144 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1145 | { | |
1146 | regcache_raw_collect (regcache, i, raw); | |
1147 | p = XSAVE_MPX_ADDR (tdep, regs, i); | |
1148 | if (memcmp (raw, p, 16)) | |
1149 | { | |
1150 | xstate_bv |= I386_XSTATE_BNDREGS; | |
1151 | memcpy (p, raw, 16); | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | /* Check if any upper MPX registers are changed. */ | |
1156 | if ((tdep->xcr0 & I386_XSTATE_BNDCFG)) | |
1157 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1158 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1159 | { | |
1160 | regcache_raw_collect (regcache, i, raw); | |
1161 | p = XSAVE_MPX_ADDR (tdep, regs, i); | |
1162 | if (memcmp (raw, p, 8)) | |
1163 | { | |
1164 | xstate_bv |= I386_XSTATE_BNDCFG; | |
1165 | memcpy (p, raw, 8); | |
1166 | } | |
1167 | } | |
31aeac78 L |
1168 | |
1169 | /* Check if any SSE registers are changed. */ | |
1170 | if ((tdep->xcr0 & I386_XSTATE_SSE)) | |
1171 | for (i = I387_XMM0_REGNUM (tdep); | |
1172 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1173 | { | |
1174 | regcache_raw_collect (regcache, i, raw); | |
1175 | p = FXSAVE_ADDR (tdep, regs, i); | |
1176 | if (memcmp (raw, p, 16)) | |
1177 | { | |
1178 | xstate_bv |= I386_XSTATE_SSE; | |
1179 | memcpy (p, raw, 16); | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | /* Check if any X87 registers are changed. */ | |
1184 | if ((tdep->xcr0 & I386_XSTATE_X87)) | |
1185 | for (i = I387_ST0_REGNUM (tdep); | |
1186 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1187 | { | |
1188 | regcache_raw_collect (regcache, i, raw); | |
1189 | p = FXSAVE_ADDR (tdep, regs, i); | |
1190 | if (memcmp (raw, p, 10)) | |
1191 | { | |
1192 | xstate_bv |= I386_XSTATE_X87; | |
1193 | memcpy (p, raw, 10); | |
1194 | } | |
1195 | } | |
1196 | } | |
1197 | else | |
1198 | { | |
1199 | /* Check if REGNUM is changed. */ | |
1200 | regcache_raw_collect (regcache, regnum, raw); | |
1201 | ||
1202 | switch (regclass) | |
1203 | { | |
1204 | default: | |
4e4d8374 L |
1205 | internal_error (__FILE__, __LINE__, |
1206 | _("invalid i387 regclass")); | |
31aeac78 | 1207 | |
40936b0d L |
1208 | case avxh: |
1209 | /* This is an upper YMM register. */ | |
1210 | p = XSAVE_AVXH_ADDR (tdep, regs, regnum); | |
1211 | if (memcmp (raw, p, 16)) | |
31aeac78 | 1212 | { |
40936b0d L |
1213 | xstate_bv |= I386_XSTATE_AVX; |
1214 | memcpy (p, raw, 16); | |
1215 | } | |
1216 | break; | |
31aeac78 | 1217 | |
1dbcd68c WT |
1218 | case mpx: |
1219 | if (regnum < I387_BNDCFGU_REGNUM (tdep)) | |
1220 | { | |
1221 | regcache_raw_collect (regcache, regnum, raw); | |
1222 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); | |
1223 | if (memcmp (raw, p, 16)) | |
1224 | { | |
1225 | xstate_bv |= I386_XSTATE_BNDREGS; | |
1226 | memcpy (p, raw, 16); | |
1227 | } | |
1228 | } | |
1229 | else | |
1230 | { | |
1231 | p = XSAVE_MPX_ADDR (tdep, regs, regnum); | |
1232 | xstate_bv |= I386_XSTATE_BNDCFG; | |
1233 | memcpy (p, raw, 8); | |
1234 | } | |
1235 | break; | |
1236 | ||
40936b0d L |
1237 | case sse: |
1238 | /* This is an SSE register. */ | |
1239 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1240 | if (memcmp (raw, p, 16)) | |
1241 | { | |
1242 | xstate_bv |= I386_XSTATE_SSE; | |
1243 | memcpy (p, raw, 16); | |
1244 | } | |
1245 | break; | |
31aeac78 | 1246 | |
40936b0d L |
1247 | case x87: |
1248 | /* This is an x87 register. */ | |
1249 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1250 | if (memcmp (raw, p, 10)) | |
1251 | { | |
1252 | xstate_bv |= I386_XSTATE_X87; | |
1253 | memcpy (p, raw, 10); | |
31aeac78 | 1254 | } |
40936b0d | 1255 | break; |
31aeac78 | 1256 | } |
40936b0d L |
1257 | } |
1258 | ||
1259 | /* Update the corresponding bits in `xstate_bv' if any SSE/AVX | |
1260 | registers are changed. */ | |
1261 | if (xstate_bv) | |
1262 | { | |
1263 | /* The supported bits in `xstat_bv' are 1 byte. */ | |
1264 | *xstate_bv_p |= (gdb_byte) xstate_bv; | |
1265 | ||
1266 | switch (regclass) | |
31aeac78 | 1267 | { |
40936b0d | 1268 | default: |
4e4d8374 L |
1269 | internal_error (__FILE__, __LINE__, |
1270 | _("invalid i387 regclass")); | |
40936b0d L |
1271 | |
1272 | case all: | |
1273 | break; | |
1274 | ||
1275 | case x87: | |
1276 | case sse: | |
1277 | case avxh: | |
1dbcd68c | 1278 | case mpx: |
40936b0d L |
1279 | /* Register REGNUM has been updated. Return. */ |
1280 | return; | |
31aeac78 | 1281 | } |
40936b0d L |
1282 | } |
1283 | else | |
1284 | { | |
1285 | /* Return if REGNUM isn't changed. */ | |
1286 | if (regclass != all) | |
1287 | return; | |
1288 | } | |
31aeac78 L |
1289 | } |
1290 | ||
1291 | /* Only handle x87 control registers. */ | |
1292 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
1293 | if (regnum == -1 || regnum == i) | |
1294 | { | |
1295 | /* Most of the FPU control registers occupy only 16 bits in | |
1296 | the xsave extended state. Give those a special treatment. */ | |
1297 | if (i != I387_FIOFF_REGNUM (tdep) | |
1298 | && i != I387_FOOFF_REGNUM (tdep)) | |
1299 | { | |
1300 | gdb_byte buf[4]; | |
1301 | ||
1302 | regcache_raw_collect (regcache, i, buf); | |
1303 | ||
20a6ec49 | 1304 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
1305 | { |
1306 | /* The opcode occupies only 11 bits. Make sure we | |
40936b0d | 1307 | don't touch the other bits. */ |
e750d25e | 1308 | buf[1] &= ((1 << 3) - 1); |
20a6ec49 | 1309 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 1310 | } |
20a6ec49 | 1311 | else if (i == I387_FTAG_REGNUM (tdep)) |
e750d25e JT |
1312 | { |
1313 | /* Converting back is much easier. */ | |
1314 | ||
1315 | unsigned short ftag; | |
1316 | int fpreg; | |
1317 | ||
1318 | ftag = (buf[1] << 8) | buf[0]; | |
1319 | buf[0] = 0; | |
1320 | buf[1] = 0; | |
1321 | ||
1322 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1323 | { | |
1324 | int tag = (ftag >> (fpreg * 2)) & 3; | |
1325 | ||
1326 | if (tag != 3) | |
1327 | buf[0] |= (1 << fpreg); | |
1328 | } | |
1329 | } | |
20a6ec49 | 1330 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); |
e750d25e JT |
1331 | } |
1332 | else | |
20a6ec49 | 1333 | regcache_raw_collect (regcache, i, FXSAVE_ADDR (tdep, regs, i)); |
e750d25e | 1334 | } |
5716833c | 1335 | |
20a6ec49 MD |
1336 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
1337 | regcache_raw_collect (regcache, I387_MXCSR_REGNUM (tdep), | |
5716833c | 1338 | FXSAVE_MXCSR_ADDR (regs)); |
e750d25e JT |
1339 | } |
1340 | ||
1341 | /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in | |
1342 | *RAW. */ | |
1343 | ||
1344 | static int | |
b4ad899f | 1345 | i387_tag (const gdb_byte *raw) |
e750d25e JT |
1346 | { |
1347 | int integer; | |
1348 | unsigned int exponent; | |
1349 | unsigned long fraction[2]; | |
1350 | ||
1351 | integer = raw[7] & 0x80; | |
1352 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
1353 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
1354 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
1355 | | (raw[5] << 8) | raw[4]); | |
1356 | ||
1357 | if (exponent == 0x7fff) | |
1358 | { | |
1359 | /* Special. */ | |
1360 | return (2); | |
1361 | } | |
1362 | else if (exponent == 0x0000) | |
1363 | { | |
1364 | if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer) | |
1365 | { | |
1366 | /* Zero. */ | |
1367 | return (1); | |
1368 | } | |
1369 | else | |
1370 | { | |
1371 | /* Special. */ | |
1372 | return (2); | |
1373 | } | |
1374 | } | |
1375 | else | |
1376 | { | |
1377 | if (integer) | |
1378 | { | |
1379 | /* Valid. */ | |
1380 | return (0); | |
1381 | } | |
1382 | else | |
1383 | { | |
1384 | /* Special. */ | |
1385 | return (2); | |
1386 | } | |
1387 | } | |
1388 | } | |
efb1c01c MK |
1389 | |
1390 | /* Prepare the FPU stack in REGCACHE for a function return. */ | |
1391 | ||
1392 | void | |
1393 | i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) | |
1394 | { | |
1395 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1396 | ULONGEST fstat; | |
1397 | ||
efb1c01c MK |
1398 | /* Set the top of the floating-point register stack to 7. The |
1399 | actual value doesn't really matter, but 7 is what a normal | |
1400 | function return would end up with if the program started out with | |
1401 | a freshly initialized FPU. */ | |
20a6ec49 | 1402 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
efb1c01c | 1403 | fstat |= (7 << 11); |
20a6ec49 | 1404 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
efb1c01c MK |
1405 | |
1406 | /* Mark %st(1) through %st(7) as empty. Since we set the top of the | |
1407 | floating-point register stack to 7, the appropriate value for the | |
1408 | tag word is 0x3fff. */ | |
20a6ec49 | 1409 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
efb1c01c | 1410 | |
efb1c01c | 1411 | } |