Commit | Line | Data |
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67278683 FF |
1 | /* Machine-dependent code which would otherwise be in inflow.c and core.c, |
2 | for GDB, the GNU debugger. | |
3 | Copyright (C) 1986, 1987 Free Software Foundation, Inc. | |
4 | This code is for the i860 cpu. | |
be9a2362 FF |
5 | |
6 | GDB is distributed in the hope that it will be useful, but WITHOUT ANY | |
7 | WARRANTY. No author or distributor accepts responsibility to anyone | |
8 | for the consequences of using it or for whether it serves any | |
9 | particular purpose or works at all, unless he says so in writing. | |
10 | Refer to the GDB General Public License for full details. | |
11 | ||
12 | Everyone is granted permission to copy, modify and redistribute GDB, | |
13 | but only under the conditions described in the GDB General Public | |
14 | License. A copy of this license is supposed to have been given to you | |
15 | along with GDB so you can know your rights and responsibilities. It | |
16 | should be in a file named COPYING. Among other things, the copyright | |
17 | notice and this notice must be preserved on all copies. | |
18 | ||
19 | In other words, go ahead and share GDB, but don't try to stop | |
20 | anyone else from sharing it farther. Help stamp out software hoarding! | |
21 | */ | |
67278683 | 22 | #include <stdio.h> |
2213b721 FF |
23 | #include <stdlib.h> |
24 | #include <stdarg.h> | |
25 | ||
be9a2362 | 26 | |
67278683 | 27 | #include "defs.h" |
be9a2362 FF |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "obstack.h" | |
31 | #include "symtab.h" | |
32 | #include "value.h" | |
118a1e4d | 33 | #include "gdbcore.h" |
be9a2362 | 34 | |
be9a2362 FF |
35 | #include "i860-opcode.h" |
36 | ||
67278683 FF |
37 | #include "breakpoint.h" |
38 | #include "i860-break.h" | |
2213b721 | 39 | #include "command.h" |
67278683 | 40 | #include "target.h" |
be9a2362 FF |
41 | |
42 | #ifdef notdef | |
be9a2362 FF |
43 | #include <sys/types.h> |
44 | #include <sys/param.h> | |
45 | #include <sys/dir.h> | |
be9a2362 FF |
46 | #endif |
47 | ||
48 | #include <signal.h> | |
49 | #include <sys/ioctl.h> | |
50 | #include <fcntl.h> | |
51 | ||
52 | /* #include <sys/reg.h> */ | |
53 | #include "i860_reg.h" | |
54 | ||
55 | #include <a.out.h> | |
56 | #include <sys/file.h> | |
be9a2362 FF |
57 | #include <core.h> |
58 | ||
59 | #include <sys/user.h> | |
be9a2362 FF |
60 | #include <elf.h> |
61 | #include <sys/elftypes.h> | |
62 | #include <sys/elf_860.h> | |
63 | #include <libelf.h> | |
64 | ||
65 | ||
2213b721 | 66 | extern int print_insn(); |
2213b721 | 67 | |
be9a2362 | 68 | int btdebug = 0; /* change value to 1 to enable debugging code */ |
67278683 | 69 | int ansi_conformant; |
be9a2362 FF |
70 | |
71 | #define BTDEBUG if (btdebug) btdebug_message | |
72 | ||
2213b721 | 73 | extern int errno; |
67278683 | 74 | extern char registers[]; |
ca8820f9 | 75 | CORE_ADDR get_saved_basereg(); |
be9a2362 | 76 | |
2213b721 FF |
77 | #define INSTRUCTION_LENGTH 4 |
78 | #define REGISTER_LENGTH 4 | |
67278683 FF |
79 | #define ALIGN_ARG(size,len) ((size + (len-1))&(-len)) |
80 | #define NUM_FLOAT_ARG_REGS 8 | |
81 | #define NUM_INT_ARG_REGS 12 | |
be9a2362 | 82 | |
2213b721 FF |
83 | /* routine to print debugging messages */ |
84 | void btdebug_message(char *format, ...) | |
be9a2362 FF |
85 | { |
86 | va_list arglist; | |
87 | va_start( arglist, format ); | |
88 | ||
89 | if( btdebug ) | |
90 | vfprintf (stderr, format, arglist ); | |
91 | va_end ( arglist ); | |
92 | } | |
93 | ||
67278683 FF |
94 | \f |
95 | /* Peggy Fieland. Routine that attempts to find the start of the entry sequence | |
96 | for a routine. */ | |
97 | /* maximum number of instrutions to search back */ | |
98 | #define MAX_ROUTINE_SIZE 4096 | |
99 | CORE_ADDR find_entry_start(pc) | |
100 | CORE_ADDR pc; | |
101 | { | |
102 | CORE_ADDR instr, top_pc; | |
103 | int i; | |
104 | ||
105 | top_pc = pc; | |
106 | for (i = 0; i < MAX_ROUTINE_SIZE; ++i) | |
107 | ||
108 | { | |
109 | instr = (unsigned)( adj_read_memory_integer (top_pc)); | |
110 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
111 | ||
112 | if ((instr & 0xEFFF0000) == 0x84420000) | |
113 | { | |
114 | return (top_pc); | |
115 | } | |
116 | top_pc -= INSTRUCTION_LENGTH; | |
117 | } | |
118 | return (0); | |
119 | } | |
120 | ||
121 | ||
122 | \f | |
123 | /* Written by Peggy Fieland (Margaret_Fieland@vos.stratus.com) */ | |
124 | /* get the contents of a base register. Used for dwarf OP_BASEREG */ | |
125 | /* At present, only OP_BASEREG generated is for R28. NOTE that for stuff based on R28, | |
126 | the value we want is the VALUE AT PROCEDURE INVOKATION, and thus is the frame we | |
127 | use to get the value is the caller's frame. */ | |
128 | CORE_ADDR get_saved_basereg (frame, basereg) | |
129 | FRAME frame; | |
130 | int basereg; | |
131 | { | |
132 | CORE_ADDR addr; | |
133 | if (basereg == R28) /* Unconditionally ??? */ | |
134 | { | |
135 | frame = get_prev_frame (frame); | |
136 | get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame, | |
137 | basereg, (enum lval_type *)NULL); | |
138 | ||
139 | } | |
140 | else | |
141 | get_saved_register((char *) &addr, (int *) NULL, (CORE_ADDR *) NULL, frame, | |
142 | basereg, (enum lval_type *)NULL); | |
143 | ||
144 | return (addr); | |
145 | } | |
146 | ||
be9a2362 FF |
147 | \f |
148 | ||
149 | /* return nonzero if the routine containing pc has been | |
150 | * compiled with -g. We assume -g if the first instruction is | |
151 | * an addu|adds -X,sp and the second is st.l fp,XX(sp) | |
152 | * | |
153 | * based on skip_prologue(); | |
154 | */ | |
155 | ||
2213b721 | 156 | static int g_routine(pc) |
67278683 | 157 | |
be9a2362 FF |
158 | CORE_ADDR pc; |
159 | { | |
2213b721 | 160 | CORE_ADDR instr; |
be9a2362 FF |
161 | CORE_ADDR top_pc; |
162 | ||
163 | top_pc = get_pc_function_start(pc); | |
67278683 FF |
164 | if (top_pc == NULL) |
165 | top_pc = find_entry_start (pc); | |
166 | ||
2213b721 | 167 | if (top_pc != NULL) |
be9a2362 | 168 | { |
2213b721 | 169 | instr = (unsigned)( adj_read_memory_integer (top_pc)); |
be9a2362 FF |
170 | /* Recognize "addu|adds -X,sp,sp" insn. */ |
171 | ||
172 | if ((instr & 0xEFFF0000) == 0x84420000) | |
173 | { | |
2213b721 FF |
174 | top_pc += INSTRUCTION_LENGTH; |
175 | instr = (unsigned)(adj_read_memory_integer (top_pc)); | |
be9a2362 FF |
176 | |
177 | if( (instr & 0xFFE0F801) == 0x1C401801 ) /* st.l fp,X(sp) */ | |
178 | return(1); | |
179 | } | |
180 | } | |
181 | return(0); | |
182 | } | |
183 | ||
184 | ||
2213b721 FF |
185 | /* return the stack offset where the fp register is stored */ |
186 | static int find_fp_offset(pc) | |
be9a2362 FF |
187 | CORE_ADDR pc; |
188 | { | |
2213b721 FF |
189 | int fp_off,i; |
190 | CORE_ADDR instr; | |
be9a2362 | 191 | |
2213b721 | 192 | /* look for the instruction and examine the offset */ |
be9a2362 | 193 | |
2213b721 FF |
194 | for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH){ |
195 | instr = (unsigned)(adj_read_memory_integer(pc+i)); | |
196 | if( (instr & 0xFFE0F801) == 0x1C401801) { /* st.l fp,X(sp) */ | |
197 | ||
198 | fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | | |
199 | (instr&0x000007FE)); | |
200 | return(fp_off); | |
be9a2362 | 201 | } |
2213b721 FF |
202 | } |
203 | return(0); | |
204 | } | |
205 | ||
67278683 | 206 | |
2213b721 | 207 | /* return the stack offset where r1 (return linkage ) register is stored */ |
67278683 FF |
208 | static CORE_ADDR find_r1(pc,sp,fp) |
209 | CORE_ADDR pc,sp, fp; | |
2213b721 FF |
210 | { |
211 | int r1_off,i; | |
67278683 | 212 | CORE_ADDR instr, ret_pc; |
be9a2362 | 213 | |
2213b721 | 214 | /* look for the instruction and examine the offset */ |
be9a2362 | 215 | |
67278683 FF |
216 | for (i=INSTRUCTION_LENGTH*1; i< INSTRUCTION_LENGTH*4; i+=INSTRUCTION_LENGTH) |
217 | { | |
218 | instr = (unsigned)( adj_read_memory_integer(pc+i)); | |
219 | if ((instr & 0xFFE0F801) == 0x1C400801) | |
220 | { | |
221 | /* st.l r1,X(sp) */ | |
2213b721 | 222 | |
67278683 FF |
223 | r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | |
224 | (instr&0x000007FE)); | |
225 | ret_pc = read_memory_integer(sp+r1_off,sizeof(long)); | |
226 | return(ret_pc); | |
227 | } | |
228 | else if ((instr & 0xFFE0F801) == 0x1C600801) | |
229 | { | |
230 | /* st.l r1,X(fp) */ | |
231 | r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | | |
232 | (instr&0x000007FE)); | |
233 | ret_pc = read_memory_integer(fp+r1_off,sizeof(long)); | |
234 | return(ret_pc); | |
235 | } | |
be9a2362 | 236 | } |
67278683 | 237 | return(0); |
be9a2362 FF |
238 | } |
239 | ||
2213b721 | 240 | CORE_ADDR skip_prologue(CORE_ADDR); |
be9a2362 | 241 | |
2213b721 FF |
242 | /* does routine starting at pc build a stack frame of any kind?? */ |
243 | static int has_a_frame(pc) | |
244 | CORE_ADDR pc; | |
245 | { | |
246 | if( skip_prologue(pc) != pc )return(1); | |
247 | else return(0); | |
248 | } | |
be9a2362 FF |
249 | |
250 | ||
2213b721 FF |
251 | /* written by Peggy Fieland Margaret_Fieland@vos.stratus.com |
252 | Routine to validate the return register and the frame pointer | |
253 | This routine is called when the routine we are in doesn't have a frame | |
254 | In that case, we assume that the return address and frame pointer have | |
255 | not been touched. In the following routine, we try to range check them | |
256 | to see if they are valid. */ | |
257 | ||
258 | static int valid_regs (rp, fp) | |
259 | CORE_ADDR rp, fp; | |
be9a2362 | 260 | { |
2213b721 FF |
261 | if ( ( (rp % 4) != 0) | ( (fp % 16) != 0) ) |
262 | return (0); | |
263 | else | |
264 | return (1); | |
be9a2362 | 265 | } |
2213b721 FF |
266 | /* get the pc and frame pointer (or sp ) |
267 | * for the routine that called us | |
268 | * when we (this_pc) is not within a -g routine | |
269 | * if caller is non g we return sp for fp | |
270 | */ | |
be9a2362 | 271 | |
2213b721 FF |
272 | /* note this is written for Metaware version R2.1d compiler */ |
273 | /* Modified by Peggy Fieland Margaret_Fieland@vos.stratus.com */ | |
67278683 FF |
274 | static int caller_pc(this_pc,this_sp,this_fp,to_pc,to_fp, called_from_frame_chain) |
275 | CORE_ADDR this_pc,this_sp, this_fp; | |
2213b721 | 276 | CORE_ADDR *to_pc, *to_fp; |
67278683 | 277 | int called_from_frame_chain; |
be9a2362 | 278 | { |
2213b721 FF |
279 | CORE_ADDR func_start; |
280 | int sp_offset,offset; | |
281 | CORE_ADDR sp,pc,fp,instr; | |
be9a2362 | 282 | |
2213b721 | 283 | BTDEBUG("caller_pc %x sp = %x\n",this_pc,this_sp); |
be9a2362 | 284 | |
2213b721 FF |
285 | func_start = get_pc_function_start(this_pc); |
286 | ||
67278683 FF |
287 | if (func_start == NULL) |
288 | func_start = find_entry_start (this_pc); | |
289 | ||
2213b721 FF |
290 | BTDEBUG("caller_pc func_start %x\n", func_start); |
291 | ||
67278683 FF |
292 | if ((func_start == NULL)) |
293 | { | |
294 | /* error in traceback */ | |
295 | fprintf(stderr, "error, unable to find start of function\n"); | |
296 | return(0); | |
297 | ||
298 | } | |
299 | ||
2213b721 | 300 | if (func_start!= NULL) |
be9a2362 FF |
301 | { |
302 | if( has_a_frame(func_start) ){ | |
303 | ||
304 | BTDEBUG("has_a_frame\n"); | |
305 | ||
306 | /* if our caller has a preamble and | |
307 | * declares space for a stack frame | |
308 | * then we must work to find our return address | |
309 | */ | |
2213b721 | 310 | instr = (unsigned)( adj_read_memory_integer (func_start)); |
be9a2362 FF |
311 | /* Recognize "addu|adds -X,sp,sp" insn. */ |
312 | ||
313 | if ((instr & 0xEFFF0000) == 0x84420000) | |
314 | sp_offset=SIGN_EXT16(instr&0x0000FFFF); | |
315 | } | |
2213b721 FF |
316 | else |
317 | { | |
67278683 | 318 | /* if we get here, procedure doesn't have a frame. If we |
2213b721 FF |
319 | do anything weird, the frame pointer and return register have |
320 | the values we want. Check them to see if they are valid. */ | |
321 | ||
322 | CORE_ADDR temp_rp, temp_fp; | |
323 | ||
67278683 FF |
324 | /* temporary warning, since at the moment we don't have support for |
325 | the shared library */ | |
326 | ||
2213b721 FF |
327 | temp_rp = read_register(RP_REGNUM); |
328 | temp_fp = read_register(FP_REGNUM); | |
329 | ||
330 | if (!valid_regs(temp_rp, temp_fp)) | |
331 | { | |
67278683 FF |
332 | fprintf(stderr, |
333 | "error - unable to find return address, traceback terminating\n"); | |
2213b721 FF |
334 | return(0); |
335 | } | |
336 | BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n", | |
337 | temp_rp, temp_fp); | |
338 | *to_pc = temp_rp; | |
339 | *to_fp = temp_fp; | |
340 | return (1); | |
341 | } | |
be9a2362 FF |
342 | |
343 | BTDEBUG("sp_offset = %d %x\n",sp_offset,sp_offset); | |
344 | ||
67278683 | 345 | pc = find_r1(func_start, this_sp, this_fp); |
be9a2362 | 346 | |
67278683 FF |
347 | if(pc == NULL) |
348 | { | |
349 | ||
350 | /* r1 wasn't stored between pc and function start */ | |
351 | pc = read_register (RP_REGNUM); | |
352 | } | |
353 | ||
be9a2362 FF |
354 | sp= this_sp - sp_offset; |
355 | ||
356 | BTDEBUG("callers pc = %x sp = %x\n",pc,sp); | |
357 | ||
358 | /* our caller a -g routine ? | |
359 | * if he is we have to find his real fp | |
360 | * else provide the sp as his fp | |
361 | */ | |
362 | ||
363 | if( g_routine(pc) ){ | |
364 | ||
365 | BTDEBUG("caller_a_g\n"); | |
366 | ||
367 | if( ! (offset = find_fp_offset(func_start)) ) { | |
67278683 FF |
368 | fprintf(stderr, "error - unable to find caller frame for routine at 0x%x, " |
369 | "traceback terminating\n", func_start); | |
be9a2362 FF |
370 | return(0); |
371 | } | |
372 | BTDEBUG("offset = %x %d\n",offset,offset); | |
373 | ||
2213b721 | 374 | fp = read_memory_integer(this_sp+offset,sizeof(long)); |
be9a2362 FF |
375 | *to_pc = CLEAN_PC(pc); |
376 | *to_fp = fp; | |
377 | return(1); | |
378 | }else | |
379 | *to_pc = CLEAN_PC(pc); | |
380 | *to_fp = sp; | |
381 | return(1); | |
382 | } else { | |
383 | /* pc = read_register(RP_REGNUM); */ | |
2213b721 FF |
384 | /* pc = 0; */ |
385 | /* if we get here, procedure doesn't have a frame. If we didn't | |
386 | do anything weird, the frame pointer and return register have | |
387 | the values we want. Check them to see if they are valid. */ | |
388 | ||
389 | CORE_ADDR temp_rp, temp_fp; | |
390 | ||
391 | temp_rp = read_register(RP_REGNUM); | |
392 | temp_fp = read_register(FP_REGNUM); | |
393 | ||
394 | if (!valid_regs(temp_rp, temp_fp)) | |
395 | { | |
67278683 FF |
396 | fprintf(stderr, |
397 | "error - unable to find return address, traceback terminating\n"); | |
398 | ||
2213b721 FF |
399 | return(0); |
400 | } | |
401 | BTDEBUG("caller_pc no frame, using r1 %x and fp %x\n", | |
402 | temp_rp, temp_fp); | |
403 | *to_pc = temp_rp; | |
404 | *to_fp = temp_fp; | |
405 | return (1); | |
be9a2362 FF |
406 | } |
407 | } | |
408 | ||
2213b721 FF |
409 | /* |
410 | ** Figure out address to place next breakpoint. Avoid tricky spots, | |
411 | ** ie. delayed instruction slots etc. | |
412 | ** Need to upgrade this later to allow delayed instruction breakpoints | |
413 | ** with fix-up work done AFTER breakpoint. | |
414 | ** Note that this routine DOES deal with dual instruction mode | |
415 | */ | |
416 | #define BIM 0x8008 | |
be9a2362 | 417 | |
2213b721 FF |
418 | static branch_type |
419 | place_brk (addr, mode, brk) | |
420 | CORE_ADDR addr; | |
421 | int mode; | |
422 | struct breakpoint *brk; | |
be9a2362 | 423 | { |
2213b721 FF |
424 | CORE_ADDR instr; |
425 | CORE_ADDR nextadr, prevadr; | |
be9a2362 FF |
426 | int val = not_branch; |
427 | long offset; /* Must be signed for sign-extend */ | |
be9a2362 FF |
428 | prevadr = nextadr = 0; |
429 | ||
430 | brk->address1 = 0; | |
431 | ||
432 | if (mode == SINGLE_STEP_MODE) | |
433 | { | |
434 | if (INDIM || ENDIM) | |
435 | { | |
2213b721 FF |
436 | nextadr = brk->address = (addr + INSTRUCTION_LENGTH*2); |
437 | instr = (unsigned)(adj_read_memory_integer ((addr + INSTRUCTION_LENGTH))); | |
be9a2362 FF |
438 | brk->mode = DIM; |
439 | } | |
440 | else | |
441 | { | |
2213b721 FF |
442 | nextadr = brk->address = (addr + INSTRUCTION_LENGTH); |
443 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
be9a2362 FF |
444 | if (STDIM) |
445 | brk->mode = DIM; | |
446 | else | |
447 | brk->mode = SIM; | |
448 | } | |
449 | ||
450 | ||
451 | /* | |
452 | ** For br/call one more sequential instruction gets executed and then we | |
453 | ** continue at the current addr + offset. We are definitely going to | |
454 | ** the dest. We are NOT allowed to place a breakpoint in the "delay" | |
455 | ** slot - (the next sequential instruction) so we only place 1 breakpoint | |
456 | ** at the destination. | |
457 | ** For the bc/bnc the next instruction executed is EITHER the next sequential | |
458 | ** or the destination of the branch, we therefore place 2 breakpoints one | |
459 | ** at each location. | |
460 | ** For the bc.t/bnc.t either 1 more sequential instruction is performed | |
461 | ** followed by a branch (like br/call) OR we skip the sequential | |
462 | ** instruction and keep going. We therefore place a breakpoint at the | |
463 | ** destination of the branch AND the second sequential instruction after | |
464 | ** the branch. Again a breakpoint is NOT allowed in the "delay slot" | |
465 | */ | |
466 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
467 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
468 | { | |
469 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
470 | val = uncond_d; | |
471 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t/bnc.t */ | |
472 | val = cond_d; | |
473 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
474 | val = cond; | |
475 | offset = (instr & 0x03ffffff); | |
476 | if (offset & 0x02000000) /*?sign extend*/ | |
477 | offset |= 0xFC000000; | |
478 | if (val == uncond_d) /* br/call*/ | |
479 | prevadr = 0; | |
480 | else if (val == cond_d) /* bc.t/bnc.t */ | |
481 | { | |
482 | if ((INDIM) && !(ENDIM)) | |
2213b721 | 483 | prevadr = nextadr + (2*INSTRUCTION_LENGTH); |
be9a2362 | 484 | else |
2213b721 | 485 | prevadr = nextadr + INSTRUCTION_LENGTH; |
be9a2362 FF |
486 | } else { /* bc /bnc */ |
487 | if ((INDIM) && !(ENDIM)) | |
488 | prevadr = nextadr; | |
489 | else | |
490 | prevadr = nextadr; | |
491 | } | |
492 | nextadr += (offset << 2); | |
493 | } | |
494 | /* | |
495 | ** We treat the bri/calli the same way as the br/call case. | |
496 | */ | |
497 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
498 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
499 | { | |
500 | val = uncond_d; | |
501 | offset = ((instr & 0x0000F800) >> 11); | |
502 | nextadr = (read_register(offset + R0) & 0xFFFFFFFC); | |
503 | prevadr = 0; | |
504 | } | |
505 | /* | |
506 | ** We treat the bte/btne the same way as the bc/bnc case. | |
507 | */ | |
508 | else if ((instr & 0xF0000000) == 0x50000000) /* bte/btne */ | |
509 | { | |
510 | val = cond; | |
511 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | | |
512 | (instr & 0x000007FF)); | |
513 | if ((INDIM) && !(ENDIM)) | |
514 | prevadr = nextadr; | |
515 | else | |
516 | prevadr = nextadr; | |
517 | ||
518 | nextadr += (offset << 2); | |
519 | } | |
520 | /* | |
521 | ** We treat the bte/btne the same way as the bc/bnc case. | |
522 | ** With the caveat that the 2 breakpoints may turn out to be at the same | |
523 | ** address in which case we ignore one of them. | |
524 | */ | |
525 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
526 | { | |
527 | val = cond_d; | |
528 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | | |
529 | (instr & 0x000007FF)); | |
530 | if ((INDIM) && !(ENDIM)) | |
531 | { | |
2213b721 | 532 | prevadr = nextadr + 2*INSTRUCTION_LENGTH; |
be9a2362 | 533 | } else { |
2213b721 | 534 | prevadr = nextadr + INSTRUCTION_LENGTH; |
be9a2362 FF |
535 | } |
536 | nextadr += (offset << 2); | |
537 | if (prevadr == nextadr) prevadr = 0; | |
538 | } | |
539 | } else { | |
540 | int adjust = 0; | |
541 | ||
542 | nextadr = addr; | |
543 | ||
544 | if (ISDIM(FOPADR(addr))) | |
545 | { | |
2213b721 | 546 | if (ISDIM(FOPADR(nextadr- INSTRUCTION_LENGTH*2))) |
be9a2362 | 547 | { |
2213b721 FF |
548 | instr = (unsigned)(adj_read_memory_integer(CORADR(addr |
549 | -(INSTRUCTION_LENGTH*2)))); | |
be9a2362 FF |
550 | brk->mode = DIM; |
551 | } else { | |
2213b721 | 552 | instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
553 | brk->mode = RIM; |
554 | } | |
555 | } else { | |
2213b721 | 556 | if (ISDIM(addr-INSTRUCTION_LENGTH)) |
be9a2362 | 557 | { |
2213b721 | 558 | instr = (unsigned)(adj_read_memory_integer(addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
559 | brk->mode = BIM; |
560 | } else { | |
2213b721 | 561 | instr = (unsigned)(adj_read_memory_integer (addr-INSTRUCTION_LENGTH)); |
be9a2362 FF |
562 | brk->mode = SIM; |
563 | } | |
564 | } | |
565 | ||
566 | /* examine the PREVIOUS instruction to determine if we are in a branch delay | |
567 | slot. If we are, dont set a break here -- set it on the previous instruction. | |
568 | This code also accounts for dual instruction mode */ | |
569 | if ((instr & 0xE0000000) == 0x60000000 && | |
570 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
571 | { | |
2213b721 FF |
572 | adjust++; |
573 | /* br /call */ | |
574 | /* bc /bnc */ | |
575 | /* bc.t /bnc.t*/ | |
576 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
67278683 | 577 | BTDEBUG(" Breakpoint adjusted to avoid br/call delay slot and multiple breakpoints\n"); |
2213b721 FF |
578 | |
579 | if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
67278683 FF |
580 | BTDEBUG(" Breakpoint adjusted to avoid bc.t/bnc.t delay slot and" |
581 | "multiple breakpoints\n"); | |
582 | ||
2213b721 FF |
583 | /* it IS really OK to set a break on the instruction AFTER the conditional branch |
584 | -- it DOESN't have a delay slot */ | |
585 | if ((instr & 0xF4000000) == 0x70000000) /* bc / bnc */ | |
2213b721 FF |
586 | adjust = 0; |
587 | } else if | |
588 | ((instr & 0xFC00003F) == 0x4C000002 || /* bri/ calli */ | |
589 | (instr & 0xFC000000) == 0x40000000) | |
590 | { | |
591 | adjust++; | |
67278683 FF |
592 | BTDEBUG(" Breakpoint adjusted to avoid calli/bri delay slot and" |
593 | " multiple breakpoints\n"); | |
2213b721 FF |
594 | } else if |
595 | ((instr & 0xF0000000) == 0x50000000) /* bte - btne */ | |
596 | { | |
597 | /* it's OK to set a break here -- we are NOT in aa branch delay slot */ | |
598 | /* | |
599 | adjust++; | |
600 | printf(" Breakpoint adjusted to avoid bte/btne multiple breakpoints\n"); | |
601 | */ | |
602 | adjust = 0; | |
603 | } else if | |
604 | ((instr & 0xFC000000) == 0xB4000000) | |
605 | { | |
606 | adjust++; | |
67278683 FF |
607 | BTDEBUG(" Breakpoint adjusted to avoid bla delay slot and" |
608 | " multiple breakpoints\n"); | |
2213b721 FF |
609 | } |
610 | if (adjust != 0) | |
611 | { | |
612 | if (brk->mode == DIM) | |
613 | { | |
614 | nextadr -= INSTRUCTION_LENGTH*2; | |
615 | nextadr = CORADR(nextadr); | |
616 | } | |
617 | else | |
618 | nextadr -= INSTRUCTION_LENGTH; | |
619 | } | |
620 | ||
621 | } | |
622 | ||
623 | if (brk->mode == RIM) | |
624 | brk->mode = DIM; | |
625 | if (brk->mode == BIM) | |
626 | brk->mode = SIM; | |
627 | ||
628 | if (nextadr != NULL) | |
629 | { | |
630 | if (brk->mode == DIM) | |
631 | { | |
632 | brk->act_addr[0] = CORADR(nextadr); | |
633 | brk->act_addr[1] = FOPADR(nextadr); | |
634 | } else { | |
635 | brk->act_addr[0] = nextadr; | |
636 | brk->act_addr[1] = 0; | |
637 | } | |
638 | } | |
639 | ||
640 | if (prevadr != NULL) | |
641 | { | |
642 | brk->address1 = prevadr; | |
643 | if (brk->mode == DIM) | |
644 | { | |
645 | brk->act_addr[2] = CORADR(prevadr); | |
646 | brk->act_addr[3] = FOPADR(prevadr); | |
647 | } else { | |
648 | brk->act_addr[2] = prevadr; | |
649 | brk->act_addr[3] = 0; | |
650 | } | |
651 | } else { | |
652 | brk->act_addr[2] = brk->act_addr[3] = 0; | |
653 | } | |
654 | return val; | |
655 | } | |
656 | ||
657 | /* This routine checks to see if r1 has been stored into the frame between | |
658 | the addresses prologue_start and prologue_end. Recognize stores of r1 | |
659 | relative to both the sp and fp registers. */ | |
660 | static int has_stored_r1(CORE_ADDR prologue_start, CORE_ADDR prologue_end) | |
661 | { | |
662 | CORE_ADDR instr; | |
663 | CORE_ADDR addr; | |
664 | ||
665 | BTDEBUG("has_stored_r1, prologue_start %x, prologue_end %x\n", | |
666 | prologue_start, prologue_end); | |
667 | ||
668 | for (addr = prologue_start; addr <= prologue_end; addr += INSTRUCTION_LENGTH) | |
669 | { | |
670 | ||
671 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
672 | if ((instr & 0xFFE0F801) == 0x1C400801 /* st.l r1,X(sp) */ | |
673 | || (instr & 0xFFE0F801) == 0x1C600801) /* st.l r1,X(fp) */ | |
674 | return (1); | |
675 | } | |
676 | return 0; | |
677 | } | |
678 | /* This is used when GDB is exiting. It gives less chance of error.*/ | |
679 | ||
680 | ||
681 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
682 | Beihl (beihl@mcc.com). */ | |
683 | /* Modified for i860 by Jim Hanko (hanko@orc.olivetti.com) */ | |
684 | ||
685 | ||
686 | static struct breakpoint brk; | |
687 | typedef char binsn_quantum[sizeof break_insn]; | |
688 | ||
689 | /* Non-zero if we just simulated a single-step ptrace call. This is | |
690 | needed because we cannot remove the breakpoints in the inferior | |
691 | process until after the `wait' in `wait_for_inferior'. Used for | |
692 | i860. */ | |
693 | ||
694 | int one_stepped; | |
695 | ||
696 | /* single_step() is called just before we want to resume the inferior, | |
697 | if we want to single-step it but there is no hardware or kernel single-step | |
698 | support. We find all the possible targets of the coming instruction and | |
699 | breakpoint them. | |
700 | ||
701 | single_step is also called just after the inferior stops. If we had | |
702 | set up a simulated single-step, we undo our damage. */ | |
703 | /* Note that we don't need the parameter, but it's dictated as part of the interface. */ | |
704 | void | |
705 | single_step (signal) | |
706 | int signal; | |
707 | { | |
708 | CORE_ADDR pc; | |
709 | branch_type place_brk(); | |
67278683 FF |
710 | int *shadow0, *shadow1, *shadow2, *shadow3; |
711 | ||
712 | shadow0 = (int *) &brk.shadow_contents[0]; | |
713 | shadow1 = (int *) &brk.shadow_contents[4]; | |
714 | shadow2 = (int *) &brk.shadow_contents[8]; | |
715 | shadow3 = (int *) &brk.shadow_contents[12]; | |
2213b721 FF |
716 | pc = read_register (PC_REGNUM); |
717 | ||
718 | if (!one_stepped) | |
719 | { | |
720 | brk.address = pc; | |
721 | place_brk (pc, SINGLE_STEP_MODE, &brk); | |
67278683 | 722 | *shadow0 = *shadow1 = *shadow2 = *shadow3 = 0; |
2213b721 FF |
723 | |
724 | if (brk.mode == DIM) | |
725 | { | |
726 | if (btdebug != 0) | |
727 | { | |
728 | btdebug_message(" DIM1 -> %x : ", brk.act_addr[3]); | |
729 | print_insn( brk.act_addr[3], stderr); | |
730 | btdebug_message("\t -|- %x : ", brk.act_addr[2]); | |
731 | print_insn( brk.act_addr[2], stderr); | |
732 | btdebug_message("\n"); | |
733 | } | |
734 | if (( brk.address1 != NULL)) | |
735 | { | |
67278683 | 736 | adj_read_memory (brk.act_addr[2], shadow2, |
2213b721 FF |
737 | INSTRUCTION_LENGTH); |
738 | adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
67278683 | 739 | adj_read_memory (brk.act_addr[3], shadow3, |
2213b721 FF |
740 | INSTRUCTION_LENGTH); |
741 | /* adj_write_memory (brk.act_addr[3], float_insn, | |
742 | INSTRUCTION_LENGTH); */ | |
743 | ||
744 | } | |
745 | if (btdebug != 0) | |
746 | { | |
747 | if ( brk.address1 != 0) | |
748 | btdebug_message(" DIM2 ->"); | |
749 | else | |
750 | btdebug_message(" DIM1 ->"); | |
751 | ||
752 | btdebug_message(" %x : ", brk.act_addr[1]); | |
753 | print_insn( brk.act_addr[1], stderr); | |
754 | btdebug_message("\t -|- %x : ", brk.act_addr[0]); | |
755 | print_insn( brk.act_addr[0], stderr); | |
756 | btdebug_message("\n"); | |
757 | } | |
758 | ||
67278683 | 759 | adj_read_memory (brk.act_addr[0], shadow0, |
2213b721 FF |
760 | INSTRUCTION_LENGTH); |
761 | adj_write_memory (brk.act_addr[0], break_insn, | |
762 | INSTRUCTION_LENGTH); | |
67278683 | 763 | adj_read_memory (brk.act_addr[1], shadow1, |
2213b721 FF |
764 | INSTRUCTION_LENGTH); |
765 | /* adj_write_memory (brk.act_addr[1], float_insn, | |
766 | INSTRUCTION_LENGTH); */ | |
767 | ||
768 | } | |
769 | else { | |
770 | if (brk.address1 != NULL) | |
771 | { | |
772 | if (btdebug) | |
773 | { | |
774 | btdebug_message(" SIM1 ->"); | |
775 | btdebug_message(" %x : ", brk.act_addr[2]); | |
776 | print_insn( brk.act_addr[2], stderr); | |
777 | btdebug_message("\n"); | |
778 | } | |
67278683 | 779 | adj_read_memory (brk.act_addr[2], shadow2, |
2213b721 FF |
780 | INSTRUCTION_LENGTH); |
781 | adj_write_memory (brk.act_addr[2], break_insn, INSTRUCTION_LENGTH); | |
782 | } | |
783 | if (btdebug) | |
784 | { | |
785 | if ( brk.address1 != NULL) | |
786 | btdebug_message(" SIM2 ->"); | |
787 | else | |
788 | btdebug_message(" SIM1 ->"); | |
789 | ||
790 | btdebug_message(" %x : ", brk.act_addr[0]); | |
791 | print_insn( brk.act_addr[0], stderr); | |
792 | btdebug_message("\n"); | |
793 | } | |
67278683 | 794 | adj_read_memory (brk.act_addr[0], shadow0, |
2213b721 FF |
795 | INSTRUCTION_LENGTH); |
796 | adj_write_memory (brk.act_addr[0], break_insn,INSTRUCTION_LENGTH); | |
797 | } | |
798 | ||
799 | /* Let it go */ | |
800 | one_stepped = 1; | |
801 | return; | |
802 | } | |
803 | else | |
804 | { | |
805 | /* Remove breakpoints */ | |
806 | if (brk.mode == DIM) | |
807 | { | |
67278683 | 808 | adj_write_memory (brk.act_addr[0], shadow0, |
2213b721 | 809 | INSTRUCTION_LENGTH); |
67278683 | 810 | adj_write_memory (brk.act_addr[1], shadow1, |
2213b721 FF |
811 | INSTRUCTION_LENGTH); |
812 | } else { | |
67278683 | 813 | adj_write_memory (brk.act_addr[0], shadow0, |
2213b721 FF |
814 | INSTRUCTION_LENGTH); |
815 | } | |
816 | ||
817 | if (brk.address1 != NULL) | |
818 | { | |
819 | if (brk.mode == DIM) | |
820 | { | |
67278683 | 821 | adj_write_memory (brk.act_addr[2], shadow2, |
2213b721 | 822 | INSTRUCTION_LENGTH); |
67278683 | 823 | adj_write_memory (brk.act_addr[3], shadow3, |
2213b721 FF |
824 | INSTRUCTION_LENGTH); |
825 | } else { | |
67278683 | 826 | adj_write_memory (brk.act_addr[2], shadow2, |
2213b721 FF |
827 | INSTRUCTION_LENGTH); |
828 | } | |
829 | } | |
830 | one_stepped = 0; | |
831 | } | |
832 | } | |
833 | ||
834 | ||
835 | ||
836 | /* Written for i860 by Jim Hanko (hanko@orc.olivetti.com) */ | |
837 | /* This code was based on SPARC code written by Gary Beihl (beihl@mcc.com), | |
838 | by Michael Tiemann (tiemann@corto.inria.fr). */ | |
839 | /* This routine returns the first memory address following the prologue code, | |
840 | if there is a prologue. */ | |
841 | ||
842 | struct command_line *get_breakpoint_commands (); | |
843 | ||
844 | CORE_ADDR | |
845 | skip_prologue (pc) | |
846 | CORE_ADDR pc; | |
847 | { | |
848 | CORE_ADDR instr; | |
849 | int regno; | |
850 | ||
851 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
852 | ||
853 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
854 | if ((instr & 0xEFFF0000) == 0x84420000) | |
855 | { | |
856 | pc += INSTRUCTION_LENGTH; | |
857 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
858 | } | |
859 | else | |
860 | return(pc); /* No frame! */ | |
861 | ||
862 | /* Recognize store of return addr and frame pointer into frame */ | |
863 | for (; ;) | |
864 | { | |
865 | if ((instr & 0xFFE0F801) == 0x1C400801 || /* st.l r1,X(sp) */ | |
866 | (instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */ | |
867 | { | |
868 | pc += INSTRUCTION_LENGTH; | |
869 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
870 | } | |
871 | else | |
872 | break; | |
873 | } | |
874 | ||
875 | /* Recognize "addu|adds X,sp,fp" insn. */ | |
876 | if ((instr & 0xEFFF0000) == 0x84430000) | |
877 | { | |
878 | pc += INSTRUCTION_LENGTH; | |
879 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
880 | } | |
881 | ||
882 | /* Now recognize stores into the frame from the registers. */ | |
883 | ||
884 | for (; ;) | |
885 | { | |
886 | if ((instr & 0xFFA00003) == 0x1C200001 || /* st.l rn,X(fp|sp) */ | |
887 | (instr & 0xFFA00001) == 0x4C200000) /* fst.y fn,X(fp|sp) */ | |
888 | { | |
889 | regno = (instr >> 11) & 0x1f; | |
890 | if (regno == 0) /* source reg == 0? quit */ | |
891 | break; | |
892 | pc += INSTRUCTION_LENGTH; | |
893 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
894 | } | |
895 | else | |
896 | break; | |
897 | } | |
898 | ||
899 | return(pc); | |
900 | } | |
901 | ||
902 | #if 0 | |
903 | /* This routine is uncalled. Remove it sometime. */ | |
904 | /* Set *nextpc to branch target if we find a branch. If it is not a branch, | |
905 | set it to the next instruction (addr + 4) */ | |
906 | ||
907 | ||
908 | branch_type | |
909 | isabranch (addr, nextpc) | |
910 | CORE_ADDR addr, *nextpc; | |
911 | { | |
912 | CORE_ADDR instr; | |
913 | branch_type val = not_branch; | |
914 | long offset; /* Must be signed for sign-extend */ | |
915 | ||
916 | BTDEBUG(" isabranch\n"); | |
917 | *nextpc = addr; | |
918 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
919 | ||
920 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
921 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
922 | { | |
923 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
924 | val = uncond_d; | |
925 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
926 | val = cond_d; | |
927 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
928 | val = cond; | |
929 | ||
930 | offset = (instr & 0x03ffffff); | |
931 | if (offset & 0x02000000) /* sign extend? */ | |
932 | offset |= 0xFC000000; | |
933 | *nextpc = addr + 4 + (offset << 2); | |
934 | } | |
935 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
936 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
937 | { | |
938 | val = uncond_d; | |
939 | offset = ((instr & 0x0000F800) >> 11); | |
940 | *nextpc = (read_register(offset) & 0xFFFFFFFC); | |
941 | } | |
942 | else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */ | |
943 | { | |
944 | val = cond; | |
945 | ||
946 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
947 | *nextpc = addr + 4 + (offset << 2); | |
948 | } | |
949 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
950 | { | |
951 | val = cond_d; | |
952 | ||
953 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
954 | *nextpc = addr + 4 + (offset << 2); | |
955 | } | |
956 | ||
957 | BTDEBUG(" Final addr - %x\n", *nextpc); | |
958 | /*BTDEBUG("isabranch ret: %d\n",val); */ | |
959 | return val; | |
960 | } | |
961 | #endif | |
962 | ||
963 | /* set in call_function() [valops.c] to the address of the "call dummy" code | |
964 | so dummy frames can be easily recognized; also used in wait_for_inferior() | |
965 | [infrun.c]. When not used, it points into the ABI's 'reserved area' */ | |
966 | ||
967 | CORE_ADDR call_dummy_set = 0; /* true if dummy call being done */ | |
968 | CORE_ADDR call_dummy_start; /* address of call dummy code */ | |
969 | ||
970 | /* this routine routine gets the values of the registers stored in the frame | |
971 | and stores their values into the frame_saved_regs structure. */ | |
972 | ||
973 | void | |
974 | frame_find_saved_regs(frame_info, frame_saved_regs) | |
975 | struct frame_info *frame_info; | |
976 | struct frame_saved_regs *frame_saved_regs; | |
977 | { | |
978 | register CORE_ADDR pc; | |
979 | CORE_ADDR instr; | |
980 | long offset, spdelta = 0; | |
981 | int i, size, reg; | |
982 | int r1_off = -1, fp_off = -1; | |
983 | int framesize; | |
984 | ||
985 | bzero (frame_saved_regs, sizeof(*frame_saved_regs)); | |
986 | ||
987 | if (call_dummy_set && frame_info->pc >= call_dummy_start && | |
988 | frame_info->pc <= call_dummy_start + CALL_DUMMY_LENGTH) | |
989 | { | |
990 | /* DUMMY frame - all registers stored in order at fp; old sp is | |
991 | at fp + NUM_REGS*4 */ | |
992 | ||
993 | for (i = 1; i < NUM_REGS; i++) /* skip reg 0 */ | |
67278683 FF |
994 | /* the register numbers used in the instruction and the ones used to index |
995 | the regs array are not the same -- compensate */ | |
996 | frame_saved_regs->regs[i+R0] = frame_info->frame + i*REGISTER_LENGTH; | |
2213b721 FF |
997 | |
998 | call_dummy_set = 0; | |
999 | return; | |
1000 | } | |
1001 | ||
1002 | pc = get_pc_function_start (frame_info->pc); | |
67278683 FF |
1003 | if (pc == NULL) |
1004 | pc = find_entry_start (frame_info->pc); | |
1005 | ||
2213b721 FF |
1006 | if (pc != NULL) |
1007 | { | |
1008 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1009 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
1010 | if ((instr & 0xEFFF0000) == 0x84420000) | |
1011 | { | |
1012 | framesize = -SIGN_EXT16(instr & 0x0000FFFF); | |
1013 | pc += INSTRUCTION_LENGTH; | |
1014 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1015 | } | |
1016 | } | |
1017 | else | |
1018 | goto punt; /* No frame! */ | |
1019 | ||
1020 | /* Recognize store of return addr and frame pointer into frame */ | |
1021 | for (; ;) | |
1022 | { | |
1023 | if ((instr & 0xFFE0F801) == 0x1C400801) /* st.l r1,X(sp) */ | |
1024 | { | |
1025 | r1_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
1026 | pc += INSTRUCTION_LENGTH; | |
1027 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1028 | } | |
1029 | else if ((instr & 0xFFE0F801) == 0x1C401801) /* st.l fp,X(sp) */ | |
1030 | { | |
1031 | fp_off = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
1032 | pc += INSTRUCTION_LENGTH; | |
1033 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1034 | } | |
1035 | else | |
1036 | break; | |
1037 | } | |
1038 | ||
1039 | /* Recognize "addu|adds X,sp,fp" insn. */ | |
1040 | if ((instr & 0xEFFF0000) == 0x84430000) | |
1041 | { | |
1042 | spdelta = SIGN_EXT16(instr & 0x0000FFFF); | |
1043 | pc += INSTRUCTION_LENGTH; | |
1044 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1045 | } | |
1046 | ||
1047 | /* Now recognize stores into the frame from the registers. */ | |
1048 | ||
1049 | for (; ;) | |
1050 | { | |
1051 | if ((instr & 0xFFC00003) == 0x1C400001) /* st.l rn,X(fp|sp) */ | |
1052 | { | |
1053 | offset = SIGN_EXT16(((instr&0x001F0000) >> 5) | (instr&0x000007FE)); | |
1054 | reg = (instr >> 11) & 0x1F; | |
1055 | if (reg == 0) | |
1056 | break; | |
1057 | if ((instr & 0x00200000) == 0) /* was this using sp? */ | |
1058 | if (spdelta != 0) /* and we know sp-fp delta */ | |
1059 | offset -= spdelta; /* if so, adjust the offset */ | |
1060 | else | |
1061 | break; /* if not, give up */ | |
1062 | ||
1063 | ||
1064 | /* Handle the case where the return address is stored after the fp | |
1065 | is adjusted */ | |
1066 | ||
1067 | if (reg == 1) | |
1068 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + offset; | |
1069 | else | |
1070 | frame_saved_regs->regs[reg+R0] = frame_info->frame + offset; | |
1071 | ||
1072 | pc += INSTRUCTION_LENGTH; | |
1073 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1074 | } | |
1075 | else if ((instr & 0xFFC00001) == 0x2C400000) /* fst.y fn,X(fp|sp) */ | |
1076 | { | |
1077 | /* | |
1078 | * The number of words in a floating store based on 3 LSB of instr | |
1079 | */ | |
1080 | static int fst_sizes[] = {2, 0, 1, 0, 4, 0, 1, 0}; | |
1081 | ||
1082 | size = fst_sizes[instr & 7]; | |
1083 | reg = ((instr >> 16) & 0x1F) + FP0_REGNUM; | |
1084 | if (reg == 0) | |
1085 | break; | |
1086 | ||
1087 | if (size > 1) /* align the offset */ | |
1088 | offset = SIGN_EXT16(instr & 0x0000FFF8); /* drop 3 bits */ | |
1089 | else | |
1090 | offset = SIGN_EXT16(instr & 0x0000FFFC); /* drop 2 bits */ | |
1091 | ||
1092 | if ((instr & 0x00200000) == 0) /* was this using sp? */ | |
1093 | if (spdelta != 0) /* and we know sp-fp delta */ | |
1094 | offset -= spdelta; /* if so, adjust the offset */ | |
1095 | else | |
1096 | break; /* if not, give up */ | |
1097 | ||
1098 | for (i = 0; i < size; i++) | |
1099 | { | |
1100 | frame_saved_regs->regs[reg] = frame_info->frame + offset; | |
1101 | ||
1102 | offset += REGISTER_LENGTH; | |
1103 | reg++; | |
1104 | } | |
1105 | ||
1106 | pc += INSTRUCTION_LENGTH; | |
1107 | instr = (unsigned)(adj_read_memory_integer (pc)); | |
1108 | } | |
1109 | else | |
1110 | break; | |
1111 | } | |
1112 | ||
1113 | punt: ; | |
1114 | if (framesize != 0 && spdelta != 0) | |
1115 | frame_saved_regs->regs[SP_REGNUM] = frame_info->frame+(framesize-spdelta); | |
1116 | else | |
1117 | frame_saved_regs->regs[SP_REGNUM] = frame_info->frame + 8; | |
1118 | ||
1119 | if ((spdelta != 0) && fp_off != -1) | |
1120 | frame_saved_regs->regs[FP_REGNUM] = frame_info->frame - spdelta + fp_off; | |
1121 | else | |
1122 | frame_saved_regs->regs[FP_REGNUM] = frame_info->frame; | |
1123 | ||
1124 | if ((spdelta != 0) && r1_off != -1) | |
1125 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame - spdelta + r1_off; | |
1126 | else | |
1127 | frame_saved_regs->regs[PC_REGNUM] = frame_info->frame + 4; | |
1128 | } | |
1129 | ||
1130 | ||
1131 | /* get the frame pointer of the caller. | |
1132 | * note that only routines that have been compiled with | |
1133 | * -g have full (XX)fp style stack frames | |
1134 | * if we are not returning to a non -g caller then we | |
1135 | * return the sp at entry to us as it is the caller's | |
1136 | * frame reference. | |
1137 | */ | |
1138 | ||
1139 | frame_chain(thisframe) | |
1140 | FRAME thisframe; | |
1141 | { | |
1142 | CORE_ADDR fp, pc; | |
1143 | CORE_ADDR func_start; | |
1144 | CORE_ADDR instr; | |
1145 | int offset; | |
1146 | CORE_ADDR thisfp = thisframe->frame; | |
67278683 FF |
1147 | struct frame_saved_regs fsr; |
1148 | CORE_ADDR thissp; | |
1149 | ||
1150 | /* get the frame pointer actually sp for a non -g | |
2213b721 FF |
1151 | * for the routine that called us routine |
1152 | */ | |
1153 | ||
1154 | BTDEBUG("FRAME_CHAIN(%x)\n",thisframe); | |
1155 | ||
1156 | if ( !read_memory_integer (thisframe->frame,sizeof(long)) ) | |
1157 | { | |
1158 | return (0); | |
1159 | } | |
1160 | ||
1161 | if( ! g_routine(thisframe->pc) ){ | |
67278683 FF |
1162 | thissp = get_saved_basereg (thisframe, SP_REGNUM); |
1163 | ||
2213b721 | 1164 | BTDEBUG( "non g at %x\n",thisframe->pc); |
67278683 | 1165 | caller_pc(thisframe->pc, thissp, thisfp,&pc,&fp, 1); |
2213b721 FF |
1166 | BTDEBUG("caller_pc returned %x %x \n",pc,fp); |
1167 | return(fp); | |
1168 | ||
1169 | }/* else a -g routine */ | |
1170 | ||
1171 | ||
1172 | fp = read_memory_integer (thisfp, sizeof(long)); | |
1173 | ||
1174 | if (fp < thisfp || fp > (unsigned) STACK_END_ADDR) | |
1175 | { | |
1176 | /* handle the Metaware-type pseudo-frame */ | |
1177 | ||
1178 | func_start = get_pc_function_start(thisframe->pc); | |
67278683 FF |
1179 | if (func_start == NULL) |
1180 | func_start = find_entry_start (thisframe->pc); | |
1181 | ||
2213b721 FF |
1182 | if (func_start != NULL) |
1183 | { | |
1184 | ||
1185 | instr = (unsigned)(adj_read_memory_integer (func_start)); | |
1186 | /* Recognize "addu|adds -X,sp,sp" insn. */ | |
1187 | if ((instr & 0xEFFF0000) == 0x84420000) | |
1188 | offset = SIGN_EXT16(instr & 0x0000FFFF); | |
be9a2362 | 1189 | |
be9a2362 FF |
1190 | } |
1191 | ||
2213b721 FF |
1192 | fp = 0; |
1193 | if (offset < 0) | |
1194 | fp = thisfp - offset; | |
be9a2362 | 1195 | } |
2213b721 FF |
1196 | BTDEBUG("frame_chain returned %d\n",fp); |
1197 | return(fp); | |
1198 | } | |
1199 | ||
1200 | /* This function returns 1 if there is no stored r1, 0 otherwise. | |
1201 | The function returns 1 if the pc is in a function prologue, | |
1202 | or the function prologue didn't save the return pointer in | |
1203 | the stack frame, 0 otherwise */ | |
1204 | ||
1205 | int no_stored_rp(CORE_ADDR pc) | |
1206 | { | |
1207 | CORE_ADDR func_start, prologue_end; | |
be9a2362 | 1208 | |
2213b721 | 1209 | func_start = get_pc_function_start(pc); |
67278683 FF |
1210 | if (func_start == NULL) |
1211 | func_start = find_entry_start (pc); | |
1212 | ||
2213b721 | 1213 | if (func_start != NULL) |
be9a2362 | 1214 | { |
2213b721 FF |
1215 | prologue_end = func_start; |
1216 | SKIP_PROLOGUE(prologue_end); | |
1217 | if ( (pc >= func_start) && (pc <= prologue_end)) | |
be9a2362 | 1218 | { |
2213b721 FF |
1219 | BTDEBUG("no_stored_rp: pc %x is in prologue \n",pc); |
1220 | return 1; | |
1221 | } | |
1222 | /* otherwise, see if the entry sequence stored the return pointer. | |
1223 | If it didn't, return 1 */ | |
1224 | /* Some procedures , at least, store the return pointer AFTER | |
1225 | the prologue sequence, so check for stores from function start to | |
1226 | present pc value. */ | |
1227 | if (!has_stored_r1(func_start, pc)) | |
1228 | { | |
1229 | BTDEBUG("no_stored_rp, for pc %x, prologue didn't store r1\n",pc); | |
1230 | return 1; | |
be9a2362 FF |
1231 | } |
1232 | } | |
2213b721 FF |
1233 | BTDEBUG("no_stored_rp for pc %x return pointer was stored \n", pc); |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
1238 | /* get the PC of the caller */ | |
1239 | CORE_ADDR frame_saved_pc(frame_struct) | |
1240 | FRAME frame_struct; | |
1241 | { | |
1242 | CORE_ADDR frame; | |
1243 | CORE_ADDR pc; | |
1244 | CORE_ADDR pc1; | |
1245 | CORE_ADDR sp ; | |
1246 | CORE_ADDR fp; | |
67278683 | 1247 | struct frame_saved_regs fsr; |
2213b721 FF |
1248 | |
1249 | frame = frame_struct->frame; | |
1250 | pc = frame_struct->pc; | |
67278683 FF |
1251 | |
1252 | ||
2213b721 FF |
1253 | BTDEBUG("frame_saved_pc input: frame %x, pc %x", |
1254 | frame, pc); | |
1255 | ||
1256 | /* First see if this is the current frame. If it is, return the value in r1, | |
1257 | as it may not have been stored */ | |
1258 | ||
1259 | fp = read_register(FP_REGNUM); | |
1260 | ||
1261 | /* check to see if we are in an entry sequence, where the return pointer has not yet been stored */ | |
1262 | if (fp == frame && no_stored_rp(pc)) | |
1263 | { | |
1264 | pc = read_register(RP_REGNUM); | |
1265 | frame_struct->rp = pc; | |
1266 | } | |
1267 | else if( ! g_routine(pc) ) | |
1268 | { | |
67278683 FF |
1269 | sp = get_saved_basereg (frame_struct, SP_REGNUM); |
1270 | ||
1271 | caller_pc(pc,sp,frame_struct->frame, &pc,&frame, 0); | |
2213b721 FF |
1272 | } |
1273 | else | |
1274 | { | |
1275 | ||
1276 | pc = read_memory_integer (frame + 4, sizeof(long)); | |
1277 | ||
67278683 | 1278 | if (inside_entry_file(pc)) |
2213b721 FF |
1279 | { |
1280 | ||
67278683 | 1281 | BTDEBUG("pc %x outside entry file \n",pc); |
2213b721 FF |
1282 | |
1283 | pc1 = read_memory_integer (frame, sizeof(long)); | |
1284 | ||
67278683 | 1285 | if (!inside_entry_file(pc1)) |
2213b721 FF |
1286 | pc = pc1; |
1287 | else | |
1288 | pc = 0; | |
1289 | } | |
1290 | } | |
1291 | BTDEBUG(" returning pc %x\n", CLEAN_PC(pc)); | |
1292 | return(CLEAN_PC(pc)); | |
1293 | ||
1294 | } | |
1295 | ||
1296 | /* Pass arguments to a function in the inferior process - ABI compliant | |
67278683 FF |
1297 | Modified by Peggy Fieland (Margaret_Fieland@vos.stratus.com) to account |
1298 | for newer ABI conventions. Note that now, unfortunately, we MUST KNOW | |
1299 | if we expect a float or a double. For now, we will assume that the | |
1300 | caller of this routine has the types of these arguments correct.... | |
1301 | NOTE THAT THIS ROUTINE DOES NO ARGUMENT COERCION -- it's all in the | |
1302 | caller. | |
1303 | Modified by Peggy Fieland to handle memory argument lists. | |
1304 | */ | |
2213b721 | 1305 | |
67278683 FF |
1306 | #define IS_EVEN_REG(fl) (((fl - FP0_REGNUM)%2) == 0) |
1307 | CORE_ADDR | |
1308 | pass_function_arguments(args, nargs, struct_return, struct_addr, sp) | |
2213b721 FF |
1309 | value *args; |
1310 | int nargs; | |
1311 | int struct_return; | |
67278683 FF |
1312 | CORE_ADDR struct_addr; |
1313 | CORE_ADDR sp; | |
2213b721 | 1314 | { |
67278683 FF |
1315 | int ireg = (struct_return) ? R17 : R16; |
1316 | int freg = F8; | |
2213b721 FF |
1317 | int i; |
1318 | struct type *type; | |
1319 | value arg; | |
67278683 FF |
1320 | signed long tmp; |
1321 | unsigned long ul_tmp; | |
1322 | signed short s_tmp; | |
1323 | unsigned short us_tmp; | |
1324 | signed char c_tmp; | |
1325 | unsigned char uc_tmp; | |
1326 | CORE_ADDR arg_ptr; | |
1327 | int len; | |
1328 | ||
1329 | if (struct_return) | |
1330 | { | |
1331 | write_register(R16, struct_addr); | |
1332 | } | |
1333 | ||
1334 | arg_ptr = sp; /* Space was allocated for memory argument list in i860_arg_coerce */ | |
1335 | ||
1336 | /* Loop through the arguments, putting the values in a register or memory as appropriate. */ | |
2213b721 FF |
1337 | |
1338 | for (i = 0; i < nargs; i++) | |
be9a2362 | 1339 | { |
67278683 | 1340 | arg = args[i]; |
2213b721 | 1341 | type = VALUE_TYPE(arg); |
67278683 | 1342 | len = TYPE_LENGTH(type); |
2213b721 | 1343 | if (type == builtin_type_double) |
be9a2362 | 1344 | { |
67278683 FF |
1345 | /* see ABI . Note freg MUST BE INCREMENTED even if arg goes into the |
1346 | memory argument list for this code to work correctly for subsequent | |
1347 | arguments. */ | |
1348 | if (!IS_EVEN_REG(freg)) | |
1349 | freg += 1; | |
1350 | /* see if argument can be put in a register, or whether it must go | |
1351 | into the memory argument list */ | |
1352 | if (freg < F8 + NUM_FLOAT_ARG_REGS) | |
1353 | { | |
1354 | /* It can go in a register */ | |
1355 | bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(double)); | |
1356 | write_register_bytes(REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type)); | |
1357 | freg += 2; | |
1358 | } | |
1359 | else | |
1360 | { | |
1361 | /* It goes into memory argument list */ | |
1362 | arg_ptr = ALIGN_ARG( arg_ptr, sizeof(double)); | |
1363 | write_memory (arg_ptr, VALUE_CONTENTS (arg), len); | |
1364 | arg_ptr += len; | |
1365 | } | |
1366 | ||
1367 | } | |
1368 | else if (type == builtin_type_float) | |
1369 | { | |
1370 | if (freg < F8 + NUM_FLOAT_ARG_REGS) | |
1371 | { | |
1372 | /* It can go in a register */ | |
1373 | bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long)); | |
1374 | write_register_bytes (REGISTER_BYTE(freg), (char *) &tmp, TYPE_LENGTH(type)); | |
1375 | freg++; | |
1376 | } | |
1377 | else | |
1378 | { | |
1379 | /* It goes into the memory argument list */ | |
1380 | arg_ptr = ALIGN_ARG(arg_ptr, sizeof(float)); | |
1381 | write_memory (arg_ptr, VALUE_CONTENTS (arg), len); | |
1382 | arg_ptr += len; | |
1383 | } | |
2213b721 FF |
1384 | } |
1385 | else | |
1386 | { | |
67278683 FF |
1387 | /* All structs are passed by value, and hence they all go into the memory |
1388 | argument list (see ABI); otherwise, as above, see if we have run | |
1389 | out of registers */ | |
1390 | ||
1391 | /* Cast value correctly so we can load it into a register or into the | |
1392 | memory argument list -- see ABI */ | |
1393 | if (TYPE_LENGTH(type) < sizeof(long)) | |
1394 | { | |
1395 | if (TYPE_FLAGS(type) & TYPE_FLAG_UNSIGNED) | |
1396 | arg = value_cast(builtin_type_unsigned_int, arg); | |
1397 | else | |
1398 | arg = value_cast (builtin_type_int, arg); | |
1399 | type = VALUE_TYPE(arg); | |
1400 | len = TYPE_LENGTH(type); | |
1401 | } | |
1402 | ||
1403 | if ((TYPE_CODE(type) == TYPE_CODE_STRUCT) || (ireg >= R16 + NUM_INT_ARG_REGS)) | |
1404 | { | |
1405 | /* It goes into the memory argument list. Minimum alignment requirements | |
1406 | are on a 4-byte boundary */ | |
1407 | ||
1408 | if ((TYPE_CODE(type) == TYPE_CODE_INT) || | |
1409 | (TYPE_CODE(type) == TYPE_CODE_ENUM) || | |
1410 | (TYPE_CODE(type) == TYPE_CODE_CHAR) || | |
1411 | (TYPE_CODE(type) == TYPE_CODE_BOOL)) | |
1412 | arg_ptr = ALIGN_ARG(arg_ptr, len); | |
1413 | else | |
1414 | arg_ptr = ALIGN_ARG (arg_ptr, sizeof(long)); /* align on 4-byte boundary */ | |
1415 | write_memory (arg_ptr, VALUE_CONTENTS (arg), len); | |
1416 | arg_ptr += len; | |
1417 | } | |
1418 | else | |
1419 | { | |
1420 | ||
1421 | bcopy(VALUE_CONTENTS(arg), &tmp, sizeof(long)); | |
1422 | write_register(ireg, tmp); | |
1423 | ireg++; | |
1424 | } | |
1425 | ||
be9a2362 | 1426 | } |
be9a2362 | 1427 | } |
67278683 FF |
1428 | |
1429 | ||
1430 | return (sp); | |
1431 | ||
2213b721 FF |
1432 | } |
1433 | ||
1434 | ||
1435 | #define SPACES " " | |
1436 | #define P_SPACES " " | |
1437 | #define BYTE 0xff | |
1438 | ||
1439 | int screen_lines=24; | |
1440 | ||
1441 | char *spec_reg[] = { | |
1442 | "fsr", "db", "dirbase", "fir", "psr", "epsr", | |
1443 | }; | |
1444 | ||
1445 | char *doro_reg[] = { | |
1446 | "scp", "cbsp", "pt_cs", "intmsk", "intack", | |
1447 | }; | |
1448 | #define NREGS 32 | |
1449 | ||
67278683 | 1450 | |
2213b721 FF |
1451 | get_reg(regno) |
1452 | { | |
1453 | char raw_buffer[32]; | |
1454 | int addr; | |
1455 | int virtual_buffer; | |
67278683 FF |
1456 | |
1457 | /* NOTE that only integer and floating point registers can be relative to a frame */ | |
1458 | ||
1459 | if ((regno >= R0) && (regno <= F31)) /* user register */ | |
1460 | read_relative_register_raw_bytes (regno, raw_buffer); | |
1461 | else | |
1462 | bcopy (®isters[regno << 2], raw_buffer, sizeof (long)); | |
1463 | ||
2213b721 FF |
1464 | REGISTER_CONVERT_TO_VIRTUAL (addr, raw_buffer, &virtual_buffer); |
1465 | return(virtual_buffer); | |
be9a2362 | 1466 | } |
2213b721 FF |
1467 | |
1468 | ||
1469 | #if 0 | |
1470 | /* This routine is uncalled. Remove it sometime. */ | |
be9a2362 FF |
1471 | |
1472 | /* | |
1473 | ** Figure out whether we are in a delayed slot and if so then take necessary | |
1474 | ** action to resume properly - remember trap pre-empts instruction | |
1475 | */ | |
1476 | int | |
1477 | wasabranch (addr, nextpc, ss) | |
1478 | CORE_ADDR addr, *nextpc; | |
1479 | int ss; | |
1480 | { | |
2213b721 | 1481 | CORE_ADDR nextadr, instr; |
be9a2362 FF |
1482 | int val = not_branch; |
1483 | long offset; /* Must be signed for sign-extend */ | |
1484 | ||
1485 | if (ss) | |
1486 | { | |
1487 | if (INDIM) | |
1488 | { | |
2213b721 FF |
1489 | nextadr = CORADR((int)(addr + INSTRUCTION_LENGTH*2)); |
1490 | instr = (unsigned)(adj_read_memory_integer (CORADR(addr))); | |
be9a2362 FF |
1491 | } |
1492 | else | |
1493 | { | |
2213b721 FF |
1494 | nextadr = addr + INSTRUCTION_LENGTH; |
1495 | instr = (unsigned)(adj_read_memory_integer (addr)); | |
be9a2362 FF |
1496 | } |
1497 | } else { | |
1498 | if (ISDIM(addr)) | |
1499 | { | |
1500 | nextadr = CORADR(addr); | |
2213b721 | 1501 | instr = (unsigned)(adj_read_memory_integer (nextadr)); |
be9a2362 FF |
1502 | } |
1503 | else | |
1504 | { | |
1505 | nextadr = addr; | |
2213b721 | 1506 | instr = (unsigned)(adj_read_memory_integer (addr)); |
be9a2362 FF |
1507 | } |
1508 | } | |
1509 | ||
1510 | ||
1511 | if ((instr & 0xE0000000) == 0x60000000 && /* CTRL format */ | |
1512 | (instr & 0xF8000000) != 0x60000000) /* not pfld.y */ | |
1513 | { | |
1514 | if ((instr & 0xF8000000) == 0x68000000) /* br or call */ | |
1515 | val = uncond_d; | |
1516 | else if ((instr & 0xF4000000) == 0x74000000) /* bc.t or bnc.t */ | |
1517 | val = cond_d; | |
1518 | else if ((instr & 0xF4000000) == 0x70000000) /* bc or bnc */ | |
1519 | val = cond; | |
1520 | ||
1521 | offset = (instr & 0x03ffffff); | |
1522 | if (offset & 0x02000000) /* sign extend? */ | |
1523 | offset |= 0xFC000000; | |
1524 | nextadr += (offset << 2); | |
1525 | } | |
1526 | else if ((instr & 0xFC00003F) == 0x4C000002 || /* calli */ | |
1527 | (instr & 0xFC000000) == 0x40000000) /* bri */ | |
1528 | { | |
1529 | if (ss) | |
1530 | { | |
1531 | val = uncond_d; | |
1532 | offset = ((instr & 0x0000F800) >> 11); | |
1533 | nextadr = (read_register(offset) & 0xFFFFFFFC); | |
1534 | } else { | |
1535 | val = uncond_d; | |
1536 | } | |
1537 | } | |
1538 | else if ((instr & 0xF0000000) == 0x50000000) /* bte or btne */ | |
1539 | { | |
1540 | val = cond; | |
1541 | ||
1542 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
1543 | nextadr += (offset << 2); | |
1544 | } | |
1545 | else if ((instr & 0xFC000000) == 0xB4000000) /* bla */ | |
1546 | { | |
1547 | val = cond_d; | |
1548 | ||
1549 | offset = SIGN_EXT16(((instr & 0x001F0000) >> 5) | (instr & 0x000007FF)); | |
1550 | nextadr += (offset << 2); | |
1551 | } | |
1552 | ||
1553 | *nextpc = nextadr; | |
1554 | return val; | |
1555 | } | |
2213b721 | 1556 | #endif |
be9a2362 | 1557 | |
be9a2362 | 1558 | |
2213b721 | 1559 | /* i860-specific routine to print the register set. Note that we ALWAYS print information |
67278683 FF |
1560 | on the floating point registers, so we ignore the parameter fpregs. |
1561 | NOTE also that only integer and floating point registers can be relative to a frame -- | |
1562 | see subroutine get_reg (above ) */ | |
1563 | ||
2213b721 | 1564 | void i860_do_registers_info(regnum,fpregs) |
be9a2362 FF |
1565 | int regnum; |
1566 | int fpregs; | |
1567 | { | |
1568 | register int i; | |
1569 | unsigned int val; | |
1570 | unsigned int j,k; | |
1571 | ||
2213b721 | 1572 | |
be9a2362 FF |
1573 | if (regnum == -1) |
1574 | printf_filtered ( | |
1575 | "Register Contents (relative to selected stack frame)\n\n"); | |
1576 | ||
1577 | if (regnum != -1) /* print one register */ | |
1578 | { | |
67278683 | 1579 | val = get_reg(regnum); |
be9a2362 FF |
1580 | printf("%-4s 0x%08x\t", reg_names[regnum], val); |
1581 | printf("\n\t"); fflush(stdout); | |
1582 | } | |
1583 | else /* print all registers */ | |
1584 | { | |
1585 | ||
1586 | printf("\n Control/Status Registers :- \n\t"); | |
1587 | for (j=0; j<=DB; j++) | |
1588 | { | |
67278683 | 1589 | val = get_reg(j); |
be9a2362 FF |
1590 | printf("%-4s 0x%08x\t", reg_names[j], val); |
1591 | } | |
1592 | printf("\n\t"); fflush(stdout); | |
1593 | ||
1594 | /* EPSR */ | |
67278683 | 1595 | val = get_reg(EPSR); |
be9a2362 FF |
1596 | printf("%-4s 0x%08x\t", reg_names[EPSR], val); |
1597 | ||
1598 | /* FSR */ | |
67278683 | 1599 | val = get_reg(FSR); |
be9a2362 FF |
1600 | printf("%-4s 0x%08x\t", reg_names[FSR], val); |
1601 | ||
1602 | /* CCR */ | |
67278683 | 1603 | val = get_reg(CCR); |
be9a2362 FF |
1604 | printf("%-4s 0x%08x\t", reg_names[CCR], val); |
1605 | /* BEAR*/ | |
67278683 | 1606 | val = get_reg(BEAR); |
be9a2362 FF |
1607 | printf("%-4s 0x%08x\t", reg_names[BEAR], val); |
1608 | ||
1609 | ||
1610 | #ifdef JIM_ADD_PRIV | |
1611 | for (j=P0; j<=P3; j++) | |
1612 | { | |
67278683 | 1613 | val = get_reg(j); |
be9a2362 FF |
1614 | printf("%-4s 0x%08x\t", reg_names[j], val); |
1615 | } | |
1616 | #endif | |
1617 | ||
1618 | printf("\n Integer Registers :- \n\t"); | |
1619 | for (j=R0; j<=R31; j++) | |
1620 | { | |
2213b721 | 1621 | if (j != IREGS && (j % REGISTER_LENGTH == 0)) |
be9a2362 FF |
1622 | { |
1623 | printf("\n\t"); fflush(stdout); | |
1624 | } | |
67278683 | 1625 | val = get_reg(j); |
be9a2362 FF |
1626 | printf("%-4s 0x%08x\t", reg_names[j], val); |
1627 | } | |
1628 | ||
1629 | printf("\n Floating Registers :- \n\t"); | |
1630 | for (j=F0; j<=F31; j++) | |
1631 | { | |
2213b721 | 1632 | if (j != FREGS && (j % REGISTER_LENGTH == 0)) |
be9a2362 FF |
1633 | { |
1634 | printf("\n\t"); fflush(stdout); | |
1635 | } | |
67278683 | 1636 | val = get_reg(j); |
be9a2362 FF |
1637 | printf("%-4s 0x%08x\t", reg_names[j], val); |
1638 | } | |
1639 | ||
1640 | printf("\n Special Registers :- \n\t"); | |
1641 | for (j=SPC_KI; j<=SPC_MERGE; j+=2) | |
1642 | { | |
1643 | unsigned int valh; | |
1644 | if (j == SPC_T) | |
1645 | { | |
1646 | printf("\n\t"); fflush(stdout); | |
1647 | } | |
67278683 FF |
1648 | val = get_reg(j); |
1649 | valh = get_reg(j+1); | |
be9a2362 FF |
1650 | printf("%-6s 0x%08x %08x\t", reg_names[j], val,valh); |
1651 | } | |
1652 | ||
1653 | printf("\n Graphics Pipeline :- \n"); | |
1654 | { | |
2213b721 | 1655 | unsigned int valh; |
be9a2362 | 1656 | j = PSV_I1; |
67278683 FF |
1657 | val = get_reg(j); |
1658 | valh = get_reg(j+1); | |
be9a2362 FF |
1659 | printf("\t\t\t%-8s 0x%08x %08x \n", reg_names[j], val,valh); |
1660 | } | |
1661 | ||
1662 | printf(" Memory Load Pipeline :- \n"); | |
2213b721 | 1663 | for (j=PSV_L1; j<=PSV_L3; j+=REGISTER_LENGTH) |
be9a2362 FF |
1664 | { |
1665 | unsigned int valh, val2,val3; | |
67278683 FF |
1666 | |
1667 | val = get_reg(j); | |
1668 | valh = get_reg(j+1); | |
1669 | val2 = get_reg(j+2); | |
1670 | val3 = get_reg(j+3); | |
1671 | ||
be9a2362 FF |
1672 | printf("\t\t%-8s 0x%08x %08x %08x %08x\n", reg_names[j], |
1673 | val,valh,val2,val3); | |
1674 | } | |
1675 | ||
1676 | printf("\n Adder Pipeline :-\t\tMultiplier Pipeline :-\t\tFSR results :-\n"); | |
1677 | for (i=PSV_FSR1,j=PSV_A1,k=PSV_M1; j<=PSV_A3; i++,j+=2,k+=2) | |
1678 | { | |
1679 | unsigned int valh,val2,val3,val4; | |
67278683 FF |
1680 | |
1681 | val4 = get_reg(i); | |
1682 | val = get_reg(j); | |
1683 | valh = get_reg(j+1); | |
1684 | val2 = get_reg(k); | |
1685 | val3 = get_reg(k+1); | |
1686 | ||
be9a2362 FF |
1687 | printf(" %-4s 0x%08x %08x\t", reg_names[j], val,valh); |
1688 | printf("%-4s 0x%08x %08x\t", reg_names[k], val2,val3); | |
1689 | printf("%-4s 0x%08x\n", reg_names[i], val4); | |
1690 | } | |
1691 | ||
1692 | } | |
1693 | ||
1694 | ||
1695 | } | |
1696 | ||
be9a2362 | 1697 | |
be9a2362 FF |
1698 | |
1699 | /* The following set of routines was adapted from existing code previously | |
1700 | in an i860-specific version of breakpoint.c by Peggy Fieland | |
1701 | (Margaret_Fieland@vos.stratus.com) */ | |
2213b721 FF |
1702 | /* routines to set a data breakpoint by setting the value in the DB register. |
1703 | Note that "hitting" the breakpoint will generate a data access trap. We | |
1704 | do not have a special trap handler. */ | |
be9a2362 FF |
1705 | unsigned int dbrkval, dbrkmod; |
1706 | void i860_dbrk_breakpoint() | |
1707 | { | |
1708 | BTDEBUG("i860_dbrk_breakpoint was called , dbrkval %x\n", dbrkval); | |
1709 | ||
2213b721 | 1710 | if (dbrkval != 0) |
be9a2362 FF |
1711 | { |
1712 | *(int *)®isters[DB<<2] = dbrkval; | |
1713 | } | |
1714 | else | |
1715 | { | |
1716 | *(int *)®isters[DB<<2] = 0; | |
1717 | } | |
1718 | ||
1719 | *(int *)®isters[PSR<<2] &= ~3; | |
1720 | *(int *)®isters[PSR<<2] |= dbrkmod; | |
1721 | ||
1722 | store_inferior_registers(DB); | |
1723 | store_inferior_registers(PSR); | |
1724 | ||
1725 | } | |
1726 | ||
2213b721 | 1727 | /* set a "read" data breakpoint. */ |
be9a2362 | 1728 | void |
67278683 | 1729 | d_ro_break_command(char *arg, int num) |
be9a2362 FF |
1730 | { |
1731 | dbrkval = strtoul(arg, NULL, 0); | |
1732 | dbrkmod = 0x01; | |
2213b721 | 1733 | BTDEBUG(" ro_dbreak - %x %x\n", dbrkval, dbrkmod); |
be9a2362 FF |
1734 | } |
1735 | ||
2213b721 | 1736 | /* set a "write" data breakpoint. */ |
be9a2362 | 1737 | void |
67278683 | 1738 | d_wo_break_command(char *arg, int num) |
be9a2362 FF |
1739 | { |
1740 | dbrkval = strtoul(arg, NULL, 0); | |
1741 | dbrkmod = 0x02; | |
2213b721 | 1742 | BTDEBUG(" wo_dbreak - %x %x\n", dbrkval, dbrkmod); |
be9a2362 FF |
1743 | } |
1744 | ||
2213b721 | 1745 | /* set a "read/write" data breakpoint. */ |
be9a2362 | 1746 | void |
67278683 FF |
1747 | d_rw_break_command(char *arg, int num) |
1748 | { | |
1749 | dbrkval = strtoul(arg, NULL, 0); | |
1750 | dbrkmod = 0x03; | |
1751 | BTDEBUG(" rw_dbreak - %x %x\n", dbrkval, dbrkmod); | |
1752 | } | |
be9a2362 | 1753 | |
2213b721 | 1754 | /* clear data breakpoint. */ |
67278683 FF |
1755 | void clear_dbreak(char *arg, int num) |
1756 | { | |
1757 | dbrkval = 0; | |
1758 | dbrkmod = 0; | |
1759 | } | |
1760 | ||
1761 | /* i860-specific breakpoint initialization. Includes adding the | |
1762 | i860-specific data breakpoint commands. */ | |
1763 | void i860_init_breakpoints() | |
1764 | { | |
be9a2362 FF |
1765 | dbrkval = dbrkmod = 0; |
1766 | add_com ("dbro", class_breakpoint, d_ro_break_command, | |
1767 | "Set a data breakpoint READ ONLY, 32-bit data element."); | |
1768 | add_com ("dbwo", class_breakpoint, d_wo_break_command, | |
1769 | "Set a data breakpoint WRITE ONLY, 32-bit data element."); | |
1770 | add_com ("dbrw", class_breakpoint, d_rw_break_command, | |
1771 | "Set a data breakpoint READ/WRITE, 32-bit data element."); | |
1772 | add_com ("dclear", class_breakpoint, clear_dbreak, | |
1773 | "clear the current data breakpoint."); | |
1774 | add_com_alias ("dc", "dclear", class_breakpoint, 1); | |
1775 | ||
1776 | } | |
1777 | ||
2213b721 | 1778 | /* i860-specific code to insert a breakpoint. */ |
be9a2362 FF |
1779 | int i860_insert_breakpoint(b) |
1780 | struct breakpoint *b; | |
1781 | { | |
1782 | int val; | |
67278683 FF |
1783 | int *shadow0, *shadow1, *shadow2, *shadow3; |
1784 | ||
1785 | shadow0 = (int *)&b->shadow_contents[0]; | |
1786 | shadow1 = (int *)&b->shadow_contents[4]; | |
1787 | shadow2 = (int *)&b->shadow_contents[8]; | |
1788 | shadow3 = (int *)&b->shadow_contents[12]; | |
be9a2362 FF |
1789 | |
1790 | place_brk( b->address, BREAK_MODE, b ); | |
67278683 | 1791 | |
be9a2362 FF |
1792 | if (b->mode == DIM) |
1793 | { | |
1794 | ||
67278683 | 1795 | adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH); |
2213b721 FF |
1796 | val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH); |
1797 | if (val != 0 ) return val; | |
67278683 | 1798 | adj_read_memory (b->act_addr[1], shadow1, INSTRUCTION_LENGTH); |
2213b721 FF |
1799 | /* val = adj_write_memory (b->act_addr[1], float_insn, INSTRUCTION_LENGTH); */ |
1800 | if (val != 0) return val; | |
be9a2362 FF |
1801 | } |
1802 | else | |
1803 | { | |
67278683 | 1804 | adj_read_memory (b->act_addr[0], shadow0, INSTRUCTION_LENGTH); |
2213b721 | 1805 | val = adj_write_memory (b->act_addr[0], break_insn, INSTRUCTION_LENGTH); |
be9a2362 | 1806 | } |
2213b721 | 1807 | if (b->address1 != 0) |
be9a2362 FF |
1808 | { |
1809 | if (b->mode == DIM) | |
1810 | { | |
1811 | ||
67278683 | 1812 | adj_read_memory (b->act_addr[2], shadow2, INSTRUCTION_LENGTH); |
2213b721 | 1813 | val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH); |
be9a2362 | 1814 | if (val) return val; |
67278683 | 1815 | adj_read_memory (b->act_addr[3], shadow3, INSTRUCTION_LENGTH); |
2213b721 FF |
1816 | /* val = adj_write_memory (b->act_addr[3], float_insn, INSTRUCTION_LENGTH); */ |
1817 | if (val != 0) return val; | |
be9a2362 FF |
1818 | } |
1819 | else | |
1820 | { | |
67278683 | 1821 | adj_read_memory (b->act_addr[2], shadow0, INSTRUCTION_LENGTH); |
2213b721 | 1822 | val = adj_write_memory (b->act_addr[2], break_insn, INSTRUCTION_LENGTH); |
be9a2362 FF |
1823 | } |
1824 | } | |
2213b721 | 1825 | if (val != 0) |
be9a2362 | 1826 | return val; |
67278683 | 1827 | |
be9a2362 FF |
1828 | b->inserted = 1; |
1829 | return 0; | |
1830 | } | |
1831 | ||
1832 | int i860_remove_breakpoint(b) | |
1833 | struct breakpoint *b; | |
1834 | { | |
1835 | int val; | |
67278683 FF |
1836 | int *shadow0, *shadow1, *shadow2, *shadow3; |
1837 | ||
1838 | shadow0 = (int *)&b->shadow_contents[0]; | |
1839 | shadow1 = (int *)&b->shadow_contents[4]; | |
1840 | shadow2 = (int *)&b->shadow_contents[8]; | |
1841 | shadow3 = (int *)&b->shadow_contents[12]; | |
1842 | ||
be9a2362 FF |
1843 | |
1844 | if (b->inserted) | |
1845 | { | |
1846 | if (b->mode == DIM) | |
1847 | { | |
67278683 | 1848 | val =adj_write_memory (b->act_addr[0], shadow0, |
2213b721 | 1849 | INSTRUCTION_LENGTH); |
67278683 | 1850 | val =adj_write_memory (b->act_addr[1],shadow1, |
2213b721 FF |
1851 | INSTRUCTION_LENGTH); |
1852 | if (b->address1 != NULL) | |
be9a2362 | 1853 | { |
67278683 | 1854 | val =adj_write_memory (b->act_addr[2],shadow2, |
2213b721 | 1855 | INSTRUCTION_LENGTH); |
67278683 | 1856 | val =adj_write_memory (b->act_addr[3], shadow3, |
2213b721 | 1857 | INSTRUCTION_LENGTH); |
be9a2362 FF |
1858 | } |
1859 | } | |
1860 | else | |
1861 | { | |
67278683 | 1862 | val =adj_write_memory (b->act_addr[0], shadow0, |
2213b721 FF |
1863 | INSTRUCTION_LENGTH); |
1864 | if (b->address1 != NULL) | |
be9a2362 | 1865 | { |
67278683 | 1866 | val =adj_write_memory (b->act_addr[2],shadow0, |
2213b721 | 1867 | INSTRUCTION_LENGTH); |
be9a2362 FF |
1868 | } |
1869 | } | |
2213b721 | 1870 | if (val != 0) |
be9a2362 FF |
1871 | return val; |
1872 | b->inserted = 0; | |
be9a2362 FF |
1873 | } |
1874 | ||
1875 | return 0; | |
1876 | ||
1877 | ||
1878 | } | |
1879 | ||
1880 | ||
1881 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ | |
1882 | ||
1883 | #include <sys/procfs.h> | |
1884 | ||
1885 | /* The following routines were added by Peggy Fieland (Margaret_Fieland@vos.stratus.com) | |
1886 | They were adapted from the m-68k versions of the routines .*/ | |
1887 | ||
1888 | /* Given a pointer to a floating point register set in /proc format | |
1889 | (fpregset_t *), unpack the register contents and supply them as gdb's | |
1890 | idea of the current floating point register values. */ | |
1891 | ||
1892 | void | |
1893 | supply_fpregset (fpregsetp) | |
1894 | fpregset_t *fpregsetp; | |
1895 | { | |
1896 | register int regno; | |
1897 | ||
1898 | BTDEBUG("supply_fregset called \n"); | |
1899 | ||
1900 | for (regno = F0 ; regno <= F31 ; regno++) | |
1901 | { | |
1902 | supply_register (regno, (char *) &(fpregsetp -> fpu.r_freg[regno-F0])); | |
1903 | } | |
1904 | } | |
1905 | ||
1906 | /* Given a pointer to a floating point register set in /proc format | |
1907 | (fpregset_t *), update the register specified by REGNO from gdb's idea | |
1908 | of the current floating point register set. If REGNO is -1, update | |
1909 | them all. */ | |
1910 | ||
1911 | void | |
1912 | fill_fpregset (fpregsetp, regno) | |
1913 | fpregset_t *fpregsetp; | |
1914 | int regno; | |
1915 | { | |
1916 | int regi; | |
1917 | char *to; | |
1918 | char *from; | |
1919 | extern char registers[]; | |
1920 | BTDEBUG("fill_fregset regno %d\n",regno); | |
1921 | ||
1922 | for (regi = F0 ; regi <= F31 ; regi++) | |
1923 | { | |
1924 | if ((regno == -1) || (regno == regi)) | |
1925 | { | |
1926 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
1927 | to = (char *) &(fpregsetp -> fpu.r_freg[regi-F0]); | |
1928 | bcopy (from, to, REGISTER_RAW_SIZE (regno)); | |
1929 | } | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | ||
1934 | /* Given a pointer to a general register set in /proc format (gregset_t *), | |
1935 | unpack the register contents and supply them as gdb's idea of the current | |
1936 | register values. */ | |
1937 | ||
1938 | void | |
1939 | supply_gregset (gregsetp) | |
1940 | gregset_t *gregsetp; | |
1941 | { | |
1942 | register int regno; | |
1943 | register greg_t *regp = (greg_t *) gregsetp; | |
1944 | ||
1945 | BTDEBUG("supply_gregset called \n"); | |
1946 | ||
1947 | for (regno = 0 ; regno <= R31 ; regno++) | |
1948 | { | |
1949 | supply_register (regno, (char *) (regp + regno)); | |
1950 | } | |
1951 | } | |
1952 | ||
2213b721 FF |
1953 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
1954 | update the register specified by REGNO from gdb's idea | |
1955 | of the current general register set. If REGNO is -1, update | |
1956 | them all. */ | |
1957 | ||
be9a2362 FF |
1958 | void |
1959 | fill_gregset (gregsetp, regno) | |
1960 | gregset_t *gregsetp; | |
1961 | int regno; | |
1962 | { | |
1963 | int regi; | |
1964 | extern char registers[]; | |
1965 | register greg_t *regp = (greg_t *) gregsetp; | |
1966 | BTDEBUG("fill_gregset regno %d \n",regno); | |
1967 | ||
1968 | for (regi = 0 ; regi <= R31 ; regi++) | |
1969 | { | |
1970 | if ((regno == -1) || (regno == regi)) | |
1971 | { | |
1972 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; | |
1973 | } | |
1974 | ||
1975 | } | |
1976 | } | |
1977 | #endif | |
67278683 FF |
1978 | |
1979 | ||
1980 | /* Push an empty stack frame, to record the current PC, etc. */ | |
1981 | /* We have this frame with fp pointing to a block where all GDB-visible | |
1982 | registers are stored in the order GDB knows them, and sp at the next | |
1983 | alignment point below fp. Note: fp + NUM_REGS*4 was the old sp | |
1984 | */ | |
1985 | extern CORE_ADDR text_end; | |
1986 | CORE_ADDR dummy_start_addr; | |
1987 | void i860_push_frame() | |
1988 | { | |
1989 | register CORE_ADDR old_fp = read_register(FP_REGNUM); | |
1990 | register CORE_ADDR old_sp = read_register(SP_REGNUM); | |
1991 | register CORE_ADDR fp ; | |
1992 | extern char registers[]; | |
1993 | ||
1994 | fp = old_sp - REGISTER_BYTES; | |
1995 | write_memory(fp, registers, REGISTER_BYTES); /* write out old register values */ | |
1996 | /* reset FP and SP */ | |
1997 | write_register(FP_REGNUM, fp); | |
1998 | write_register(SP_REGNUM, (fp &~ 15)); /* re-align */ | |
1999 | call_dummy_set = 1; | |
2000 | } | |
2001 | /* Discard from the stack the innermost frame, | |
2002 | restoring all saved registers. */ | |
2003 | ||
2004 | void i860_pop_frame() | |
2005 | { register FRAME frame = get_current_frame (); | |
2006 | register CORE_ADDR fp; | |
2007 | struct frame_info *fi; | |
2008 | int i; | |
2009 | ||
2010 | fi = get_frame_info (frame); | |
2011 | fp = fi->frame; | |
2012 | ||
2013 | if (call_dummy_set && fi -> pc >= call_dummy_start && | |
2014 | fi -> pc <= call_dummy_start + CALL_DUMMY_LENGTH) | |
2015 | { | |
2016 | ||
2017 | read_memory(fp, registers, REGISTER_BYTES); | |
2018 | ||
2019 | target_store_registers(-1); | |
2020 | ||
2021 | { | |
2022 | /* since we stomped on code that will be executed when we exit the program, | |
2023 | restore it. */ | |
2024 | extern REGISTER_TYPE call_save_code[4]; | |
2025 | ||
2026 | write_memory (call_dummy_start, (char *) call_save_code, 16); | |
2027 | ||
2028 | } | |
2029 | call_dummy_set = 0; | |
2030 | } | |
2031 | else | |
2032 | { | |
2033 | register int regnum; | |
2034 | struct frame_saved_regs fsr; | |
2035 | char raw_buffer[12]; | |
2036 | ||
2037 | get_frame_saved_regs (fi, &fsr); | |
2038 | for (regnum = FP0_REGNUM + 31; regnum >= FP0_REGNUM; regnum--) | |
2039 | if (fsr.regs[regnum]) | |
2040 | write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); | |
2041 | for (regnum = R31; regnum >= 1; regnum--) | |
2042 | if (fsr.regs[regnum]) | |
2043 | if (regnum != SP_REGNUM) | |
2044 | write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); | |
2045 | else | |
2046 | write_register (SP_REGNUM, fsr.regs[SP_REGNUM]); | |
2047 | if (fsr.regs[PS_REGNUM]) | |
2048 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
2049 | if (fsr.regs[FPS_REGNUM]) | |
2050 | write_register (FPS_REGNUM, read_memory_integer (fsr.regs[FPS_REGNUM],4)); | |
2051 | if (fsr.regs[PC_REGNUM]) | |
2052 | write_register (PC_REGNUM,CLEAN_PC( read_memory_integer (fsr.regs[PC_REGNUM], 4))); | |
2053 | } | |
2054 | ||
2055 | flush_cached_frames (); | |
2056 | ||
2057 | set_current_frame (create_new_frame (read_register (FP_REGNUM), | |
2058 | read_pc ())); | |
2059 | ||
2060 | } | |
2061 | ||
2062 | CORE_ADDR i860_arg_coerce(nargs, args, struct_return, sp) | |
2063 | int nargs; | |
2064 | value *args; | |
2065 | int struct_return; | |
2066 | CORE_ADDR sp; | |
2067 | { | |
2068 | ||
2069 | register int scalar; | |
2070 | register enum type_code code2; | |
2071 | register struct type *type; | |
2072 | int i; | |
2073 | value arg; | |
2074 | int num_int_args = 0; | |
2075 | int num_float_args = 0; | |
2076 | int size = 0; | |
2077 | CORE_ADDR arg_ptr; | |
2078 | ||
2079 | /* if we return a structure, it's address is in R16, and thus it uses up one of the integer | |
2080 | argument registers. See the ABI. */ | |
2081 | if (struct_return) | |
2082 | num_int_args += 1; | |
2083 | ||
2084 | /* loop to do the right thing with all the arguments and calculate the size of the memory | |
2085 | argument list. We keep count of the number of integer and the number of float parameters, | |
2086 | as well as the size of the memory argument list. */ | |
2087 | ||
2088 | for (i = 0; i < nargs; i++) | |
2089 | { | |
2090 | ||
2091 | /* NOTE that this is all hunky dory in spite of the fact that we don't actually | |
2092 | have the signature of the called procedure EXCEPT if we are passing in floats! | |
2093 | This is true, since registers are 4 bytes, and the minimum alignment in the | |
2094 | memory argument list is 4 bytes. See the ABI for more gory details. The switch | |
2095 | "ansi-conformant" is an attempt to get around this problem. */ | |
2096 | ||
2097 | code2 = TYPE_CODE (VALUE_TYPE(args[i])); | |
2098 | ||
2099 | /* Only coerce if we've got switch "ansi-conformant" off. | |
2100 | Actually, it's OK ( and probably helpful) to coerce ALL integer arguments | |
2101 | (see comment above), but never mind, we make them the right size in | |
2102 | pass_function_arguments. */ | |
2103 | ||
2104 | if ((!ansi_conformant) && (code2 != TYPE_CODE_STRUCT)) | |
2105 | value_arg_coerce(args[i]); | |
2106 | ||
2107 | arg = args[i]; | |
2108 | type = VALUE_TYPE(args[i]); | |
2109 | ||
2110 | /* All structures are passed by value in the memory argument list. */ | |
2111 | if (code2 == TYPE_CODE_STRUCT) | |
2112 | { | |
2113 | size = ALIGN_ARG(size, sizeof(long)); | |
2114 | size += TYPE_LENGTH(type); | |
2115 | } | |
2116 | else if (type == builtin_type_float) | |
2117 | { | |
2118 | num_float_args += 1; | |
2119 | if (num_float_args > NUM_FLOAT_ARG_REGS) | |
2120 | { | |
2121 | size = ALIGN_ARG(size, TYPE_LENGTH(type)) ; | |
2122 | size += TYPE_LENGTH(type); | |
2123 | } | |
2124 | } | |
2125 | else if (type == builtin_type_double) | |
2126 | { | |
2127 | /* floating register alignment -- see ABI */ | |
2128 | if ((num_float_args%2) != 0) | |
2129 | num_float_args += 1; | |
2130 | ||
2131 | num_float_args += 2; /* use up two registers */ | |
2132 | ||
2133 | if (num_float_args > NUM_FLOAT_ARG_REGS) | |
2134 | { | |
2135 | size = ALIGN_ARG(size, TYPE_LENGTH(type)) ; | |
2136 | size += TYPE_LENGTH(type); | |
2137 | } | |
2138 | } | |
2139 | else | |
2140 | { | |
2141 | int len = max (sizeof(long), TYPE_LENGTH(type)); | |
2142 | ||
2143 | num_int_args += 1; | |
2144 | ||
2145 | if (num_int_args > NUM_INT_ARG_REGS) | |
2146 | { | |
2147 | /* see ABI -- in-memory arguments have AT LEAST word alignment */ | |
2148 | if ((TYPE_CODE(type) == TYPE_CODE_INT) || | |
2149 | (TYPE_CODE(type) == TYPE_CODE_ENUM) || | |
2150 | (TYPE_CODE(type) == TYPE_CODE_CHAR) || | |
2151 | (TYPE_CODE(type) == TYPE_CODE_BOOL)) | |
2152 | size = ALIGN_ARG(size, len); | |
2153 | else | |
2154 | size = ALIGN_ARG(size, sizeof(long)); | |
2155 | size += len; | |
2156 | } | |
2157 | } | |
2158 | ||
2159 | } | |
2160 | ||
2161 | ||
2162 | /* recalculate the stack pointer, leaving enough space for the memory argument list and | |
2163 | realigning the stack pointer. */ | |
2164 | if (size != 0) | |
2165 | { | |
2166 | arg_ptr = sp - size; | |
2167 | ||
2168 | arg_ptr = arg_ptr & (-16); /* realign stack */ | |
2169 | write_register (R28,arg_ptr); | |
2170 | sp = arg_ptr; | |
2171 | } | |
2172 | ||
2173 | return (sp); | |
2174 | ||
2175 | } | |
2176 | void i860_extract_return_value(type,regbuf,valbuf) | |
2177 | struct type *type; | |
2178 | char regbuf[REGISTER_BYTES]; | |
2179 | char *valbuf; | |
2180 | { | |
2181 | register int len = TYPE_LENGTH (type); | |
2182 | double tmp_db; | |
2183 | float tmp_flt; | |
2184 | ||
2185 | if ((TYPE_CODE(type) == TYPE_CODE_FLT)) | |
2186 | { | |
2187 | if (len == sizeof (float)) | |
2188 | { | |
2189 | /* FIXME | |
2190 | NOTE that this assumes that the function declaration was ANSI_CONFORMANT -- | |
2191 | at the present time I can't think of ANY WAY to disambiguate the two following | |
2192 | cases: | |
2193 | float really_does_return_a_float(float ff) | |
2194 | { ...} | |
2195 | and | |
2196 | float actually_returns_a_double(ff) | |
2197 | float ff; | |
2198 | {...} | |
2199 | */ | |
2200 | bcopy ((char *) (regbuf) + REGISTER_BYTE(ADJ_FREG(F8)), (valbuf), TYPE_LENGTH (type)) ; | |
2201 | } | |
2202 | else | |
2203 | bcopy ((char *) (regbuf) + REGISTER_BYTE(F8), (valbuf), TYPE_LENGTH (type)) ; | |
2204 | } | |
2205 | else | |
2206 | bcopy ((char *) (regbuf) + REGISTER_BYTE(R16), (valbuf), TYPE_LENGTH (type)); | |
2207 | ||
2208 | } | |
2209 | void i860_store_return_value(type,valbuf) | |
2210 | struct type *type; | |
2211 | char *valbuf; | |
2212 | { | |
2213 | register int len = TYPE_LENGTH (type); | |
2214 | double tmp_db; | |
2215 | ||
2216 | if ((TYPE_CODE(type) == TYPE_CODE_FLT) ) | |
2217 | { | |
2218 | write_register_bytes (REGISTER_BYTE (F8), valbuf, len); | |
2219 | } | |
2220 | else | |
2221 | write_register_bytes (REGISTER_BYTE (R16), valbuf, TYPE_LENGTH (type)); | |
2222 | ||
2223 | } | |
ca8820f9 | 2224 |