Commit | Line | Data |
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c906108c | 1 | /* Target-machine dependent code for the Intel 960 |
b6ba6518 KB |
2 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 |
3 | Free Software Foundation, Inc. | |
c906108c SS |
4 | Contributed by Intel Corporation. |
5 | examine_prologue and other parts contributed by Wind River Systems. | |
6 | ||
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "symtab.h" | |
26 | #include "value.h" | |
27 | #include "frame.h" | |
28 | #include "floatformat.h" | |
29 | #include "target.h" | |
30 | #include "gdbcore.h" | |
2acceee2 | 31 | #include "inferior.h" |
4e052eda | 32 | #include "regcache.h" |
c906108c | 33 | |
a14ed312 KB |
34 | static CORE_ADDR next_insn (CORE_ADDR memaddr, |
35 | unsigned int *pword1, unsigned int *pword2); | |
c906108c SS |
36 | |
37 | /* Does the specified function use the "struct returning" convention | |
38 | or the "value returning" convention? The "value returning" convention | |
39 | almost invariably returns the entire value in registers. The | |
40 | "struct returning" convention often returns the entire value in | |
41 | memory, and passes a pointer (out of or into the function) saying | |
42 | where the value (is or should go). | |
43 | ||
44 | Since this sometimes depends on whether it was compiled with GCC, | |
45 | this is also an argument. This is used in call_function to build a | |
46 | stack, and in value_being_returned to print return values. | |
47 | ||
48 | On i960, a structure is returned in registers g0-g3, if it will fit. | |
49 | If it's more than 16 bytes long, g13 pointed to it on entry. */ | |
50 | ||
51 | int | |
fba45db2 | 52 | i960_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
53 | { |
54 | return (TYPE_LENGTH (type) > 16); | |
55 | } | |
56 | ||
57 | /* gdb960 is always running on a non-960 host. Check its characteristics. | |
58 | This routine must be called as part of gdb initialization. */ | |
59 | ||
60 | static void | |
fba45db2 | 61 | check_host (void) |
c906108c | 62 | { |
c5aa993b | 63 | int i; |
c906108c | 64 | |
c5aa993b JM |
65 | static struct typestruct |
66 | { | |
67 | int hostsize; /* Size of type on host */ | |
68 | int i960size; /* Size of type on i960 */ | |
69 | char *typename; /* Name of type, for error msg */ | |
70 | } | |
71 | types[] = | |
72 | { | |
73 | { | |
74 | sizeof (short), 2, "short" | |
75 | } | |
76 | , | |
77 | { | |
78 | sizeof (int), 4, "int" | |
79 | } | |
80 | , | |
81 | { | |
82 | sizeof (long), 4, "long" | |
83 | } | |
84 | , | |
85 | { | |
86 | sizeof (float), 4, "float" | |
87 | } | |
88 | , | |
89 | { | |
90 | sizeof (double), 8, "double" | |
91 | } | |
92 | , | |
93 | { | |
94 | sizeof (char *), 4, "pointer" | |
95 | } | |
96 | , | |
97 | }; | |
98 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) | |
c906108c | 99 | |
c5aa993b JM |
100 | /* Make sure that host type sizes are same as i960 |
101 | */ | |
102 | for (i = 0; i < TYPELEN; i++) | |
103 | { | |
104 | if (types[i].hostsize != types[i].i960size) | |
105 | { | |
106 | printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", | |
107 | types[i].typename, types[i].i960size); | |
c906108c | 108 | } |
c5aa993b JM |
109 | |
110 | } | |
c906108c SS |
111 | } |
112 | \f | |
113 | /* Examine an i960 function prologue, recording the addresses at which | |
114 | registers are saved explicitly by the prologue code, and returning | |
115 | the address of the first instruction after the prologue (but not | |
116 | after the instruction at address LIMIT, as explained below). | |
117 | ||
118 | LIMIT places an upper bound on addresses of the instructions to be | |
119 | examined. If the prologue code scan reaches LIMIT, the scan is | |
120 | aborted and LIMIT is returned. This is used, when examining the | |
121 | prologue for the current frame, to keep examine_prologue () from | |
122 | claiming that a given register has been saved when in fact the | |
123 | instruction that saves it has not yet been executed. LIMIT is used | |
124 | at other times to stop the scan when we hit code after the true | |
125 | function prologue (e.g. for the first source line) which might | |
126 | otherwise be mistaken for function prologue. | |
127 | ||
128 | The format of the function prologue matched by this routine is | |
129 | derived from examination of the source to gcc960 1.21, particularly | |
130 | the routine i960_function_prologue (). A "regular expression" for | |
131 | the function prologue is given below: | |
132 | ||
133 | (lda LRn, g14 | |
c5aa993b JM |
134 | mov g14, g[0-7] |
135 | (mov 0, g14) | (lda 0, g14))? | |
c906108c SS |
136 | |
137 | (mov[qtl]? g[0-15], r[4-15])* | |
138 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? | |
139 | (st[qtl]? g[0-15], n(fp))* | |
140 | ||
141 | (cmpobne 0, g14, LFn | |
c5aa993b JM |
142 | mov sp, g14 |
143 | lda 0x30(sp), sp | |
144 | LFn: stq g0, (g14) | |
145 | stq g4, 0x10(g14) | |
146 | stq g8, 0x20(g14))? | |
c906108c SS |
147 | |
148 | (st g14, n(fp))? | |
149 | (mov g13,r[4-15])? | |
c5aa993b | 150 | */ |
c906108c SS |
151 | |
152 | /* Macros for extracting fields from i960 instructions. */ | |
153 | ||
154 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
155 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
156 | ||
157 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) | |
158 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) | |
159 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
160 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
161 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) | |
162 | ||
163 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
164 | is not the address of a valid instruction, the address of the next | |
165 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
166 | of the instruction, and (for two-word instructions), *PWORD2 receives | |
167 | the second. */ | |
168 | ||
169 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ | |
170 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) | |
171 | ||
172 | static CORE_ADDR | |
fba45db2 KB |
173 | examine_prologue (register CORE_ADDR ip, register CORE_ADDR limit, |
174 | CORE_ADDR frame_addr, struct frame_saved_regs *fsr) | |
c906108c SS |
175 | { |
176 | register CORE_ADDR next_ip; | |
177 | register int src, dst; | |
178 | register unsigned int *pcode; | |
179 | unsigned int insn1, insn2; | |
180 | int size; | |
181 | int within_leaf_prologue; | |
182 | CORE_ADDR save_addr; | |
c5aa993b JM |
183 | static unsigned int varargs_prologue_code[] = |
184 | { | |
185 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ | |
186 | 0x5cf01601, /* mov sp, g14 */ | |
187 | 0x8c086030, /* lda 0x30(sp), sp */ | |
188 | 0xb2879000, /* LFn: stq g0, (g14) */ | |
189 | 0xb2a7a010, /* stq g4, 0x10(g14) */ | |
190 | 0xb2c7a020 /* stq g8, 0x20(g14) */ | |
191 | }; | |
c906108c SS |
192 | |
193 | /* Accept a leaf procedure prologue code fragment if present. | |
194 | Note that ip might point to either the leaf or non-leaf | |
195 | entry point; we look for the non-leaf entry point first: */ | |
196 | ||
197 | within_leaf_prologue = 0; | |
198 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
199 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
200 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ | |
c906108c SS |
201 | { |
202 | within_leaf_prologue = 1; | |
203 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); | |
204 | } | |
205 | ||
206 | /* Now look for the prologue code at a leaf entry point: */ | |
207 | ||
208 | if (next_ip | |
c5aa993b | 209 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
210 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
211 | { | |
212 | within_leaf_prologue = 1; | |
213 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
214 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
215 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ | |
c906108c SS |
216 | { |
217 | ip = next_ip; | |
218 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
219 | within_leaf_prologue = 0; | |
220 | } | |
221 | } | |
222 | ||
223 | /* If something that looks like the beginning of a leaf prologue | |
224 | has been seen, but the remainder of the prologue is missing, bail. | |
225 | We don't know what we've got. */ | |
226 | ||
227 | if (within_leaf_prologue) | |
228 | return (ip); | |
c5aa993b | 229 | |
c906108c SS |
230 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
231 | This may cause us to mistake the moving of a register | |
232 | parameter to a local register for the saving of a callee-saved | |
233 | register, but that can't be helped, since with the | |
234 | "-fcall-saved" flag, any register can be made callee-saved. */ | |
235 | ||
236 | while (next_ip | |
237 | && (insn1 & 0xfc802fb0) == 0x5c000610 | |
238 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
239 | { | |
240 | src = REG_SRC1 (insn1); | |
241 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; | |
242 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
243 | while (size--) | |
244 | { | |
245 | fsr->regs[src++] = save_addr; | |
246 | save_addr += 4; | |
247 | } | |
248 | ip = next_ip; | |
249 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
250 | } | |
251 | ||
252 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ | |
253 | ||
254 | if (next_ip && | |
255 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ | |
256 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ | |
257 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ | |
258 | { | |
259 | ip = next_ip; | |
260 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
261 | } | |
262 | ||
263 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". | |
264 | This may cause us to mistake the copying of a register | |
265 | parameter to the frame for the saving of a callee-saved | |
266 | register, but that can't be helped, since with the | |
267 | "-fcall-saved" flag, any register can be made callee-saved. | |
268 | We can, however, refuse to accept a save of register g14, | |
269 | since that is matched explicitly below. */ | |
270 | ||
271 | while (next_ip && | |
c5aa993b JM |
272 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
273 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ | |
274 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ | |
275 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ | |
c906108c SS |
276 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
277 | { | |
278 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) | |
279 | ? insn2 : MEMA_OFFSET (insn1)); | |
280 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) | |
c5aa993b | 281 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
c906108c SS |
282 | while (size--) |
283 | { | |
284 | fsr->regs[src++] = save_addr; | |
285 | save_addr += 4; | |
286 | } | |
287 | ip = next_ip; | |
288 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
289 | } | |
290 | ||
291 | /* Accept the varargs prologue code if present. */ | |
292 | ||
293 | size = sizeof (varargs_prologue_code) / sizeof (int); | |
294 | pcode = varargs_prologue_code; | |
295 | while (size-- && next_ip && *pcode++ == insn1) | |
296 | { | |
297 | ip = next_ip; | |
298 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
299 | } | |
300 | ||
301 | /* Accept an optional "st g14, n(fp)". */ | |
302 | ||
303 | if (next_ip && | |
c5aa993b JM |
304 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
305 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ | |
c906108c SS |
306 | { |
307 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) | |
c5aa993b | 308 | ? insn2 : MEMA_OFFSET (insn1)); |
c906108c SS |
309 | ip = next_ip; |
310 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
311 | } | |
312 | ||
313 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. | |
314 | This is saving the address where a struct should be returned. */ | |
315 | ||
316 | if (next_ip | |
317 | && (insn1 & 0xff802fbf) == 0x5c00061d | |
318 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
319 | { | |
320 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
c5aa993b | 321 | fsr->regs[G0_REGNUM + 13] = save_addr; |
c906108c | 322 | ip = next_ip; |
c5aa993b | 323 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
c906108c SS |
324 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
325 | #endif | |
326 | } | |
327 | ||
328 | return (ip); | |
329 | } | |
330 | ||
331 | /* Given an ip value corresponding to the start of a function, | |
332 | return the ip of the first instruction after the function | |
333 | prologue. */ | |
334 | ||
335 | CORE_ADDR | |
5c678a12 | 336 | i960_skip_prologue (CORE_ADDR ip) |
c906108c SS |
337 | { |
338 | struct frame_saved_regs saved_regs_dummy; | |
339 | struct symtab_and_line sal; | |
340 | CORE_ADDR limit; | |
341 | ||
342 | sal = find_pc_line (ip, 0); | |
343 | limit = (sal.end) ? sal.end : 0xffffffff; | |
344 | ||
345 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); | |
346 | } | |
347 | ||
348 | /* Put here the code to store, into a struct frame_saved_regs, | |
349 | the addresses of the saved registers of frame described by FRAME_INFO. | |
350 | This includes special registers such as pc and fp saved in special | |
351 | ways in the stack frame. sp is even more special: | |
352 | the address we return for it IS the sp for the next frame. | |
353 | ||
354 | We cache the result of doing this in the frame_obstack, since it is | |
355 | fairly expensive. */ | |
356 | ||
357 | void | |
fba45db2 | 358 | frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr) |
c906108c SS |
359 | { |
360 | register CORE_ADDR next_addr; | |
361 | register CORE_ADDR *saved_regs; | |
362 | register int regnum; | |
363 | register struct frame_saved_regs *cache_fsr; | |
364 | CORE_ADDR ip; | |
365 | struct symtab_and_line sal; | |
366 | CORE_ADDR limit; | |
367 | ||
368 | if (!fi->fsr) | |
369 | { | |
370 | cache_fsr = (struct frame_saved_regs *) | |
371 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); | |
372 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); | |
373 | fi->fsr = cache_fsr; | |
374 | ||
375 | /* Find the start and end of the function prologue. If the PC | |
c5aa993b JM |
376 | is in the function prologue, we only consider the part that |
377 | has executed already. */ | |
378 | ||
c906108c SS |
379 | ip = get_pc_function_start (fi->pc); |
380 | sal = find_pc_line (ip, 0); | |
c5aa993b | 381 | limit = (sal.end && sal.end < fi->pc) ? sal.end : fi->pc; |
c906108c SS |
382 | |
383 | examine_prologue (ip, limit, fi->frame, cache_fsr); | |
384 | ||
385 | /* Record the addresses at which the local registers are saved. | |
c5aa993b JM |
386 | Strictly speaking, we should only do this for non-leaf procedures, |
387 | but no one will ever look at these values if it is a leaf procedure, | |
388 | since local registers are always caller-saved. */ | |
c906108c SS |
389 | |
390 | next_addr = (CORE_ADDR) fi->frame; | |
391 | saved_regs = cache_fsr->regs; | |
392 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) | |
393 | { | |
394 | *saved_regs++ = next_addr; | |
395 | next_addr += 4; | |
396 | } | |
397 | ||
398 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; | |
399 | } | |
400 | ||
401 | *fsr = *fi->fsr; | |
402 | ||
403 | /* Fetch the value of the sp from memory every time, since it | |
404 | is conceivable that it has changed since the cache was flushed. | |
405 | This unfortunately undoes much of the savings from caching the | |
406 | saved register values. I suggest adding an argument to | |
407 | get_frame_saved_regs () specifying the register number we're | |
408 | interested in (or -1 for all registers). This would be passed | |
409 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient | |
410 | computation of saved register addresses (e.g., on the i960, | |
411 | we don't have to examine the prologue to find local registers). | |
c5aa993b | 412 | -- markf@wrs.com |
c906108c SS |
413 | FIXME, we don't need to refetch this, since the cache is cleared |
414 | every time the child process is restarted. If GDB itself | |
415 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ | |
416 | ||
417 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); | |
418 | } | |
419 | ||
420 | /* Return the address of the argument block for the frame | |
421 | described by FI. Returns 0 if the address is unknown. */ | |
422 | ||
423 | CORE_ADDR | |
fba45db2 | 424 | frame_args_address (struct frame_info *fi, int must_be_correct) |
c906108c SS |
425 | { |
426 | struct frame_saved_regs fsr; | |
427 | CORE_ADDR ap; | |
428 | ||
429 | /* If g14 was saved in the frame by the function prologue code, return | |
430 | the saved value. If the frame is current and we are being sloppy, | |
431 | return the value of g14. Otherwise, return zero. */ | |
432 | ||
433 | get_frame_saved_regs (fi, &fsr); | |
434 | if (fsr.regs[G14_REGNUM]) | |
c5aa993b | 435 | ap = read_memory_integer (fsr.regs[G14_REGNUM], 4); |
c906108c SS |
436 | else |
437 | { | |
438 | if (must_be_correct) | |
c5aa993b | 439 | return 0; /* Don't cache this result */ |
c906108c SS |
440 | if (get_next_frame (fi)) |
441 | ap = 0; | |
442 | else | |
443 | ap = read_register (G14_REGNUM); | |
444 | if (ap == 0) | |
445 | ap = fi->frame; | |
446 | } | |
447 | fi->arg_pointer = ap; /* Cache it for next time */ | |
448 | return ap; | |
449 | } | |
450 | ||
451 | /* Return the address of the return struct for the frame | |
452 | described by FI. Returns 0 if the address is unknown. */ | |
453 | ||
454 | CORE_ADDR | |
fba45db2 | 455 | frame_struct_result_address (struct frame_info *fi) |
c906108c SS |
456 | { |
457 | struct frame_saved_regs fsr; | |
458 | CORE_ADDR ap; | |
459 | ||
460 | /* If the frame is non-current, check to see if g14 was saved in the | |
461 | frame by the function prologue code; return the saved value if so, | |
462 | zero otherwise. If the frame is current, return the value of g14. | |
463 | ||
464 | FIXME, shouldn't this use the saved value as long as we are past | |
465 | the function prologue, and only use the current value if we have | |
466 | no saved value and are at TOS? -- gnu@cygnus.com */ | |
467 | ||
468 | if (get_next_frame (fi)) | |
469 | { | |
470 | get_frame_saved_regs (fi, &fsr); | |
471 | if (fsr.regs[G13_REGNUM]) | |
c5aa993b | 472 | ap = read_memory_integer (fsr.regs[G13_REGNUM], 4); |
c906108c SS |
473 | else |
474 | ap = 0; | |
475 | } | |
476 | else | |
477 | ap = read_register (G13_REGNUM); | |
478 | ||
479 | return ap; | |
480 | } | |
481 | ||
482 | /* Return address to which the currently executing leafproc will return, | |
5c678a12 KB |
483 | or 0 if IP, the value of the instruction pointer from the currently |
484 | executing function, is not in a leafproc (or if we can't tell if it | |
485 | is). | |
c5aa993b | 486 | |
5c678a12 | 487 | Do this by finding the starting address of the routine in which IP lies. |
c906108c SS |
488 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this |
489 | is a leafproc and the return address is in register gx. Well, this is | |
490 | true unless the return address points at a RET instruction in the current | |
491 | procedure, which indicates that we have a 'dual entry' routine that | |
492 | has been entered through the CALL entry point. */ | |
493 | ||
494 | CORE_ADDR | |
5c678a12 | 495 | leafproc_return (CORE_ADDR ip) |
c906108c SS |
496 | { |
497 | register struct minimal_symbol *msymbol; | |
498 | char *p; | |
499 | int dst; | |
500 | unsigned int insn1, insn2; | |
501 | CORE_ADDR return_addr; | |
502 | ||
503 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) | |
504 | { | |
c5aa993b | 505 | if ((p = strchr (SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
c906108c SS |
506 | { |
507 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) | |
c5aa993b | 508 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
509 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
510 | { | |
511 | /* Get the return address. If the "mov g14, gx" | |
c5aa993b JM |
512 | instruction hasn't been executed yet, read |
513 | the return address from g14; otherwise, read it | |
514 | from the register into which g14 was moved. */ | |
c906108c SS |
515 | |
516 | return_addr = | |
c5aa993b JM |
517 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
518 | ? G14_REGNUM : dst); | |
c906108c SS |
519 | |
520 | /* We know we are in a leaf procedure, but we don't know | |
c5aa993b JM |
521 | whether the caller actually did a "bal" to the ".lf" |
522 | entry point, or a normal "call" to the non-leaf entry | |
523 | point one instruction before. In the latter case, the | |
524 | return address will be the address of a "ret" | |
525 | instruction within the procedure itself. We test for | |
526 | this below. */ | |
c906108c SS |
527 | |
528 | if (!next_insn (return_addr, &insn1, &insn2) | |
c5aa993b JM |
529 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
530 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) | |
c906108c SS |
531 | return (return_addr); |
532 | } | |
533 | } | |
534 | } | |
c5aa993b | 535 | |
c906108c SS |
536 | return (0); |
537 | } | |
538 | ||
539 | /* Immediately after a function call, return the saved pc. | |
540 | Can't go through the frames for this because on some machines | |
541 | the new frame is not set up until the new function executes | |
542 | some instructions. | |
543 | On the i960, the frame *is* set up immediately after the call, | |
544 | unless the function is a leaf procedure. */ | |
545 | ||
546 | CORE_ADDR | |
fba45db2 | 547 | saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
548 | { |
549 | CORE_ADDR saved_pc; | |
550 | ||
551 | saved_pc = leafproc_return (get_frame_pc (frame)); | |
552 | if (!saved_pc) | |
553 | saved_pc = FRAME_SAVED_PC (frame); | |
554 | ||
555 | return saved_pc; | |
556 | } | |
557 | ||
558 | /* Discard from the stack the innermost frame, | |
559 | restoring all saved registers. */ | |
560 | ||
561 | void | |
d4f3574e | 562 | i960_pop_frame (void) |
c906108c SS |
563 | { |
564 | register struct frame_info *current_fi, *prev_fi; | |
565 | register int i; | |
566 | CORE_ADDR save_addr; | |
567 | CORE_ADDR leaf_return_addr; | |
568 | struct frame_saved_regs fsr; | |
569 | char local_regs_buf[16 * 4]; | |
570 | ||
571 | current_fi = get_current_frame (); | |
572 | ||
573 | /* First, undo what the hardware does when we return. | |
574 | If this is a non-leaf procedure, restore local registers from | |
575 | the save area in the calling frame. Otherwise, load the return | |
576 | address obtained from leafproc_return () into the rip. */ | |
577 | ||
578 | leaf_return_addr = leafproc_return (current_fi->pc); | |
579 | if (!leaf_return_addr) | |
580 | { | |
581 | /* Non-leaf procedure. Restore local registers, incl IP. */ | |
582 | prev_fi = get_prev_frame (current_fi); | |
583 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); | |
c5aa993b JM |
584 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
585 | sizeof (local_regs_buf)); | |
c906108c SS |
586 | |
587 | /* Restore frame pointer. */ | |
588 | write_register (FP_REGNUM, prev_fi->frame); | |
589 | } | |
590 | else | |
591 | { | |
592 | /* Leaf procedure. Just restore the return address into the IP. */ | |
593 | write_register (RIP_REGNUM, leaf_return_addr); | |
594 | } | |
595 | ||
596 | /* Now restore any global regs that the current function had saved. */ | |
597 | get_frame_saved_regs (current_fi, &fsr); | |
598 | for (i = G0_REGNUM; i < G14_REGNUM; i++) | |
599 | { | |
7a292a7a SS |
600 | save_addr = fsr.regs[i]; |
601 | if (save_addr != 0) | |
c906108c SS |
602 | write_register (i, read_memory_integer (save_addr, 4)); |
603 | } | |
604 | ||
605 | /* Flush the frame cache, create a frame for the new innermost frame, | |
606 | and make it the current frame. */ | |
607 | ||
608 | flush_cached_frames (); | |
609 | } | |
610 | ||
611 | /* Given a 960 stop code (fault or trace), return the signal which | |
612 | corresponds. */ | |
613 | ||
614 | enum target_signal | |
fba45db2 | 615 | i960_fault_to_signal (int fault) |
c906108c SS |
616 | { |
617 | switch (fault) | |
618 | { | |
c5aa993b JM |
619 | case 0: |
620 | return TARGET_SIGNAL_BUS; /* parallel fault */ | |
621 | case 1: | |
622 | return TARGET_SIGNAL_UNKNOWN; | |
623 | case 2: | |
624 | return TARGET_SIGNAL_ILL; /* operation fault */ | |
625 | case 3: | |
626 | return TARGET_SIGNAL_FPE; /* arithmetic fault */ | |
627 | case 4: | |
628 | return TARGET_SIGNAL_FPE; /* floating point fault */ | |
c906108c SS |
629 | |
630 | /* constraint fault. This appears not to distinguish between | |
c5aa993b JM |
631 | a range constraint fault (which should be SIGFPE) and a privileged |
632 | fault (which should be SIGILL). */ | |
633 | case 5: | |
634 | return TARGET_SIGNAL_ILL; | |
c906108c | 635 | |
c5aa993b JM |
636 | case 6: |
637 | return TARGET_SIGNAL_SEGV; /* virtual memory fault */ | |
c906108c SS |
638 | |
639 | /* protection fault. This is for an out-of-range argument to | |
c5aa993b JM |
640 | "calls". I guess it also could be SIGILL. */ |
641 | case 7: | |
642 | return TARGET_SIGNAL_SEGV; | |
643 | ||
644 | case 8: | |
645 | return TARGET_SIGNAL_BUS; /* machine fault */ | |
646 | case 9: | |
647 | return TARGET_SIGNAL_BUS; /* structural fault */ | |
648 | case 0xa: | |
649 | return TARGET_SIGNAL_ILL; /* type fault */ | |
650 | case 0xb: | |
651 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
652 | case 0xc: | |
653 | return TARGET_SIGNAL_BUS; /* process fault */ | |
654 | case 0xd: | |
655 | return TARGET_SIGNAL_SEGV; /* descriptor fault */ | |
656 | case 0xe: | |
657 | return TARGET_SIGNAL_BUS; /* event fault */ | |
658 | case 0xf: | |
659 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
660 | case 0x10: | |
661 | return TARGET_SIGNAL_TRAP; /* single-step trace */ | |
662 | case 0x11: | |
663 | return TARGET_SIGNAL_TRAP; /* branch trace */ | |
664 | case 0x12: | |
665 | return TARGET_SIGNAL_TRAP; /* call trace */ | |
666 | case 0x13: | |
667 | return TARGET_SIGNAL_TRAP; /* return trace */ | |
668 | case 0x14: | |
669 | return TARGET_SIGNAL_TRAP; /* pre-return trace */ | |
670 | case 0x15: | |
671 | return TARGET_SIGNAL_TRAP; /* supervisor call trace */ | |
672 | case 0x16: | |
673 | return TARGET_SIGNAL_TRAP; /* breakpoint trace */ | |
674 | default: | |
675 | return TARGET_SIGNAL_UNKNOWN; | |
c906108c SS |
676 | } |
677 | } | |
678 | ||
679 | /****************************************/ | |
c5aa993b | 680 | /* MEM format */ |
c906108c SS |
681 | /****************************************/ |
682 | ||
c5aa993b JM |
683 | struct tabent |
684 | { | |
685 | char *name; | |
686 | char numops; | |
c906108c SS |
687 | }; |
688 | ||
5c678a12 KB |
689 | /* Return instruction length, either 4 or 8. When NOPRINT is non-zero |
690 | (TRUE), don't output any text. (Actually, as implemented, if NOPRINT | |
691 | is 0, abort() is called.) */ | |
692 | ||
693 | static int | |
694 | mem (unsigned long memaddr, unsigned long word1, unsigned long word2, | |
695 | int noprint) | |
c906108c | 696 | { |
c5aa993b JM |
697 | int i, j; |
698 | int len; | |
699 | int mode; | |
700 | int offset; | |
701 | const char *reg1, *reg2, *reg3; | |
702 | ||
703 | /* This lookup table is too sparse to make it worth typing in, but not | |
704 | * so large as to make a sparse array necessary. We allocate the | |
705 | * table at runtime, initialize all entries to empty, and copy the | |
706 | * real ones in from an initialization table. | |
707 | * | |
708 | * NOTE: In this table, the meaning of 'numops' is: | |
709 | * 1: single operand | |
710 | * 2: 2 operands, load instruction | |
711 | * -2: 2 operands, store instruction | |
712 | */ | |
713 | static struct tabent *mem_tab = NULL; | |
c906108c SS |
714 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ |
715 | #define MEM_MIN 0x80 | |
716 | #define MEM_MAX 0xcf | |
717 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) | |
718 | ||
c5aa993b JM |
719 | static struct |
720 | { | |
721 | int opcode; | |
722 | char *name; | |
723 | char numops; | |
724 | } | |
725 | mem_init[] = | |
726 | { | |
727 | 0x80, "ldob", 2, | |
728 | 0x82, "stob", -2, | |
729 | 0x84, "bx", 1, | |
730 | 0x85, "balx", 2, | |
731 | 0x86, "callx", 1, | |
732 | 0x88, "ldos", 2, | |
733 | 0x8a, "stos", -2, | |
734 | 0x8c, "lda", 2, | |
735 | 0x90, "ld", 2, | |
736 | 0x92, "st", -2, | |
737 | 0x98, "ldl", 2, | |
738 | 0x9a, "stl", -2, | |
739 | 0xa0, "ldt", 2, | |
740 | 0xa2, "stt", -2, | |
741 | 0xb0, "ldq", 2, | |
742 | 0xb2, "stq", -2, | |
743 | 0xc0, "ldib", 2, | |
744 | 0xc2, "stib", -2, | |
745 | 0xc8, "ldis", 2, | |
746 | 0xca, "stis", -2, | |
747 | 0, NULL, 0 | |
748 | }; | |
749 | ||
750 | if (mem_tab == NULL) | |
751 | { | |
752 | mem_tab = (struct tabent *) xmalloc (MEM_SIZ); | |
753 | memset (mem_tab, '\0', MEM_SIZ); | |
754 | for (i = 0; mem_init[i].opcode != 0; i++) | |
755 | { | |
756 | j = mem_init[i].opcode - MEM_MIN; | |
757 | mem_tab[j].name = mem_init[i].name; | |
758 | mem_tab[j].numops = mem_init[i].numops; | |
c906108c | 759 | } |
c5aa993b | 760 | } |
c906108c | 761 | |
c5aa993b JM |
762 | i = ((word1 >> 24) & 0xff) - MEM_MIN; |
763 | mode = (word1 >> 10) & 0xf; | |
c906108c | 764 | |
c5aa993b JM |
765 | if ((mem_tab[i].name != NULL) /* Valid instruction */ |
766 | && ((mode == 5) || (mode >= 12))) | |
767 | { /* With 32-bit displacement */ | |
768 | len = 8; | |
769 | } | |
770 | else | |
771 | { | |
772 | len = 4; | |
773 | } | |
c906108c | 774 | |
c5aa993b JM |
775 | if (noprint) |
776 | { | |
777 | return len; | |
778 | } | |
e1e9e218 | 779 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
780 | } |
781 | ||
782 | /* Read the i960 instruction at 'memaddr' and return the address of | |
783 | the next instruction after that, or 0 if 'memaddr' is not the | |
784 | address of a valid instruction. The first word of the instruction | |
785 | is stored at 'pword1', and the second word, if any, is stored at | |
786 | 'pword2'. */ | |
787 | ||
788 | static CORE_ADDR | |
fba45db2 | 789 | next_insn (CORE_ADDR memaddr, unsigned int *pword1, unsigned int *pword2) |
c906108c SS |
790 | { |
791 | int len; | |
792 | char buf[8]; | |
793 | ||
794 | /* Read the two (potential) words of the instruction at once, | |
795 | to eliminate the overhead of two calls to read_memory (). | |
796 | FIXME: Loses if the first one is readable but the second is not | |
797 | (e.g. last word of the segment). */ | |
798 | ||
799 | read_memory (memaddr, buf, 8); | |
800 | *pword1 = extract_unsigned_integer (buf, 4); | |
801 | *pword2 = extract_unsigned_integer (buf + 4, 4); | |
802 | ||
c5aa993b | 803 | /* Divide instruction set into classes based on high 4 bits of opcode */ |
c906108c SS |
804 | |
805 | switch ((*pword1 >> 28) & 0xf) | |
806 | { | |
807 | case 0x0: | |
c5aa993b | 808 | case 0x1: /* ctrl */ |
c906108c SS |
809 | |
810 | case 0x2: | |
c5aa993b | 811 | case 0x3: /* cobr */ |
c906108c SS |
812 | |
813 | case 0x5: | |
814 | case 0x6: | |
c5aa993b | 815 | case 0x7: /* reg */ |
c906108c SS |
816 | len = 4; |
817 | break; | |
818 | ||
819 | case 0x8: | |
820 | case 0x9: | |
821 | case 0xa: | |
822 | case 0xb: | |
823 | case 0xc: | |
824 | len = mem (memaddr, *pword1, *pword2, 1); | |
825 | break; | |
826 | ||
c5aa993b | 827 | default: /* invalid instruction */ |
c906108c SS |
828 | len = 0; |
829 | break; | |
830 | } | |
831 | ||
832 | if (len) | |
833 | return memaddr + len; | |
834 | else | |
835 | return 0; | |
836 | } | |
837 | ||
838 | /* 'start_frame' is a variable in the MON960 runtime startup routine | |
839 | that contains the frame pointer of the 'start' routine (the routine | |
840 | that calls 'main'). By reading its contents out of remote memory, | |
841 | we can tell where the frame chain ends: backtraces should halt before | |
842 | they display this frame. */ | |
843 | ||
844 | int | |
fba45db2 | 845 | mon960_frame_chain_valid (CORE_ADDR chain, struct frame_info *curframe) |
c906108c | 846 | { |
c5aa993b JM |
847 | struct symbol *sym; |
848 | struct minimal_symbol *msymbol; | |
849 | ||
850 | /* crtmon960.o is an assembler module that is assumed to be linked | |
851 | * first in an i80960 executable. It contains the true entry point; | |
852 | * it performs startup up initialization and then calls 'main'. | |
853 | * | |
854 | * 'sf' is the name of a variable in crtmon960.o that is set | |
855 | * during startup to the address of the first frame. | |
856 | * | |
857 | * 'a' is the address of that variable in 80960 memory. | |
858 | */ | |
859 | static char sf[] = "start_frame"; | |
860 | CORE_ADDR a; | |
861 | ||
862 | ||
863 | chain &= ~0x3f; /* Zero low 6 bits because previous frame pointers | |
864 | contain return status info in them. */ | |
865 | if (chain == 0) | |
866 | { | |
867 | return 0; | |
868 | } | |
c906108c | 869 | |
c5aa993b JM |
870 | sym = lookup_symbol (sf, 0, VAR_NAMESPACE, (int *) NULL, |
871 | (struct symtab **) NULL); | |
872 | if (sym != 0) | |
873 | { | |
874 | a = SYMBOL_VALUE (sym); | |
875 | } | |
876 | else | |
877 | { | |
878 | msymbol = lookup_minimal_symbol (sf, NULL, NULL); | |
879 | if (msymbol == NULL) | |
880 | return 0; | |
881 | a = SYMBOL_VALUE_ADDRESS (msymbol); | |
882 | } | |
c906108c | 883 | |
c5aa993b | 884 | return (chain != read_memory_integer (a, 4)); |
c906108c SS |
885 | } |
886 | ||
2acceee2 | 887 | |
c906108c | 888 | void |
fba45db2 | 889 | _initialize_i960_tdep (void) |
c906108c SS |
890 | { |
891 | check_host (); | |
892 | ||
893 | tm_print_insn = print_insn_i960; | |
894 | } |