Commit | Line | Data |
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c906108c | 1 | /* Target-machine dependent code for the Intel 960 |
92e8c9ed AC |
2 | |
3 | Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, | |
4 | 2001, 2002 Free Software Foundation, Inc. | |
5 | ||
c906108c SS |
6 | Contributed by Intel Corporation. |
7 | examine_prologue and other parts contributed by Wind River Systems. | |
8 | ||
c5aa993b | 9 | This file is part of GDB. |
c906108c | 10 | |
c5aa993b JM |
11 | This program is free software; you can redistribute it and/or modify |
12 | it under the terms of the GNU General Public License as published by | |
13 | the Free Software Foundation; either version 2 of the License, or | |
14 | (at your option) any later version. | |
c906108c | 15 | |
c5aa993b JM |
16 | This program is distributed in the hope that it will be useful, |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
c906108c | 20 | |
c5aa993b JM |
21 | You should have received a copy of the GNU General Public License |
22 | along with this program; if not, write to the Free Software | |
23 | Foundation, Inc., 59 Temple Place - Suite 330, | |
24 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
25 | |
26 | #include "defs.h" | |
27 | #include "symtab.h" | |
28 | #include "value.h" | |
29 | #include "frame.h" | |
30 | #include "floatformat.h" | |
31 | #include "target.h" | |
32 | #include "gdbcore.h" | |
2acceee2 | 33 | #include "inferior.h" |
4e052eda | 34 | #include "regcache.h" |
c906108c | 35 | |
a14ed312 KB |
36 | static CORE_ADDR next_insn (CORE_ADDR memaddr, |
37 | unsigned int *pword1, unsigned int *pword2); | |
c906108c | 38 | |
0cb2e7c5 AC |
39 | struct type * |
40 | i960_register_type (int regnum) | |
41 | { | |
42 | if (regnum < FP0_REGNUM) | |
43 | return builtin_type_int32; | |
44 | else | |
45 | return builtin_type_i960_ext; | |
46 | } | |
47 | ||
48 | ||
c906108c SS |
49 | /* Does the specified function use the "struct returning" convention |
50 | or the "value returning" convention? The "value returning" convention | |
51 | almost invariably returns the entire value in registers. The | |
52 | "struct returning" convention often returns the entire value in | |
53 | memory, and passes a pointer (out of or into the function) saying | |
54 | where the value (is or should go). | |
55 | ||
56 | Since this sometimes depends on whether it was compiled with GCC, | |
57 | this is also an argument. This is used in call_function to build a | |
58 | stack, and in value_being_returned to print return values. | |
59 | ||
60 | On i960, a structure is returned in registers g0-g3, if it will fit. | |
61 | If it's more than 16 bytes long, g13 pointed to it on entry. */ | |
62 | ||
63 | int | |
fba45db2 | 64 | i960_use_struct_convention (int gcc_p, struct type *type) |
c906108c SS |
65 | { |
66 | return (TYPE_LENGTH (type) > 16); | |
67 | } | |
68 | ||
69 | /* gdb960 is always running on a non-960 host. Check its characteristics. | |
70 | This routine must be called as part of gdb initialization. */ | |
71 | ||
72 | static void | |
fba45db2 | 73 | check_host (void) |
c906108c | 74 | { |
c5aa993b | 75 | int i; |
c906108c | 76 | |
c5aa993b JM |
77 | static struct typestruct |
78 | { | |
79 | int hostsize; /* Size of type on host */ | |
80 | int i960size; /* Size of type on i960 */ | |
81 | char *typename; /* Name of type, for error msg */ | |
82 | } | |
83 | types[] = | |
84 | { | |
85 | { | |
86 | sizeof (short), 2, "short" | |
87 | } | |
88 | , | |
89 | { | |
90 | sizeof (int), 4, "int" | |
91 | } | |
92 | , | |
93 | { | |
94 | sizeof (long), 4, "long" | |
95 | } | |
96 | , | |
97 | { | |
98 | sizeof (float), 4, "float" | |
99 | } | |
100 | , | |
101 | { | |
102 | sizeof (double), 8, "double" | |
103 | } | |
104 | , | |
105 | { | |
106 | sizeof (char *), 4, "pointer" | |
107 | } | |
108 | , | |
109 | }; | |
110 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) | |
c906108c | 111 | |
c5aa993b JM |
112 | /* Make sure that host type sizes are same as i960 |
113 | */ | |
114 | for (i = 0; i < TYPELEN; i++) | |
115 | { | |
116 | if (types[i].hostsize != types[i].i960size) | |
117 | { | |
118 | printf_unfiltered ("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", | |
119 | types[i].typename, types[i].i960size); | |
c906108c | 120 | } |
c5aa993b JM |
121 | |
122 | } | |
c906108c SS |
123 | } |
124 | \f | |
92e8c9ed AC |
125 | /* i960_find_saved_register () |
126 | ||
127 | Return the address in which frame FRAME's value of register REGNUM | |
128 | has been saved in memory. Or return zero if it has not been saved. | |
129 | If REGNUM specifies the SP, the value we return is actually the SP | |
130 | value, not an address where it was saved. */ | |
131 | ||
132 | static CORE_ADDR | |
133 | i960_find_saved_register (struct frame_info *frame, int regnum) | |
134 | { | |
135 | register struct frame_info *frame1 = NULL; | |
136 | register CORE_ADDR addr = 0; | |
137 | ||
138 | if (frame == NULL) /* No regs saved if want current frame */ | |
139 | return 0; | |
140 | ||
141 | /* We assume that a register in a register window will only be saved | |
142 | in one place (since the name changes and/or disappears as you go | |
143 | towards inner frames), so we only call get_frame_saved_regs on | |
144 | the current frame. This is directly in contradiction to the | |
145 | usage below, which assumes that registers used in a frame must be | |
146 | saved in a lower (more interior) frame. This change is a result | |
147 | of working on a register window machine; get_frame_saved_regs | |
148 | always returns the registers saved within a frame, within the | |
149 | context (register namespace) of that frame. */ | |
150 | ||
151 | /* However, note that we don't want this to return anything if | |
152 | nothing is saved (if there's a frame inside of this one). Also, | |
153 | callers to this routine asking for the stack pointer want the | |
154 | stack pointer saved for *this* frame; this is returned from the | |
155 | next frame. */ | |
156 | ||
157 | if (REGISTER_IN_WINDOW_P (regnum)) | |
158 | { | |
159 | frame1 = get_next_frame (frame); | |
160 | if (!frame1) | |
161 | return 0; /* Registers of this frame are active. */ | |
162 | ||
163 | /* Get the SP from the next frame in; it will be this | |
164 | current frame. */ | |
165 | if (regnum != SP_REGNUM) | |
166 | frame1 = frame; | |
167 | ||
168 | FRAME_INIT_SAVED_REGS (frame1); | |
169 | return frame1->saved_regs[regnum]; /* ... which might be zero */ | |
170 | } | |
171 | ||
172 | /* Note that this next routine assumes that registers used in | |
173 | frame x will be saved only in the frame that x calls and | |
174 | frames interior to it. This is not true on the sparc, but the | |
175 | above macro takes care of it, so we should be all right. */ | |
176 | while (1) | |
177 | { | |
178 | QUIT; | |
179 | frame1 = get_next_frame (frame); | |
180 | if (frame1 == 0) | |
181 | break; | |
182 | frame = frame1; | |
183 | FRAME_INIT_SAVED_REGS (frame1); | |
184 | if (frame1->saved_regs[regnum]) | |
185 | addr = frame1->saved_regs[regnum]; | |
186 | } | |
187 | ||
188 | return addr; | |
189 | } | |
190 | ||
191 | /* i960_get_saved_register () | |
192 | ||
193 | Find register number REGNUM relative to FRAME and put its (raw, | |
194 | target format) contents in *RAW_BUFFER. Set *OPTIMIZED if the | |
195 | variable was optimized out (and thus can't be fetched). Set *LVAL | |
196 | to lval_memory, lval_register, or not_lval, depending on whether | |
197 | the value was fetched from memory, from a register, or in a strange | |
198 | and non-modifiable way (e.g. a frame pointer which was calculated | |
199 | rather than fetched). Set *ADDRP to the address, either in memory | |
200 | on as a REGISTER_BYTE offset into the registers array. | |
201 | ||
202 | Note that this implementation never sets *LVAL to not_lval. But it | |
203 | can be replaced by defining GET_SAVED_REGISTER and supplying your | |
204 | own. | |
205 | ||
206 | The argument RAW_BUFFER must point to aligned memory. */ | |
207 | ||
208 | void | |
209 | i960_get_saved_register (char *raw_buffer, | |
210 | int *optimized, | |
211 | CORE_ADDR *addrp, | |
212 | struct frame_info *frame, | |
213 | int regnum, | |
214 | enum lval_type *lval) | |
215 | { | |
216 | CORE_ADDR addr; | |
217 | ||
218 | if (!target_has_registers) | |
219 | error ("No registers."); | |
220 | ||
221 | /* Normal systems don't optimize out things with register numbers. */ | |
222 | if (optimized != NULL) | |
223 | *optimized = 0; | |
224 | addr = i960_find_saved_register (frame, regnum); | |
225 | if (addr != 0) | |
226 | { | |
227 | if (lval != NULL) | |
228 | *lval = lval_memory; | |
229 | if (regnum == SP_REGNUM) | |
230 | { | |
231 | if (raw_buffer != NULL) | |
232 | { | |
233 | /* Put it back in target format. */ | |
234 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
235 | (LONGEST) addr); | |
236 | } | |
237 | if (addrp != NULL) | |
238 | *addrp = 0; | |
239 | return; | |
240 | } | |
241 | if (raw_buffer != NULL) | |
242 | target_read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
243 | } | |
244 | else | |
245 | { | |
246 | if (lval != NULL) | |
247 | *lval = lval_register; | |
248 | addr = REGISTER_BYTE (regnum); | |
249 | if (raw_buffer != NULL) | |
250 | read_register_gen (regnum, raw_buffer); | |
251 | } | |
252 | if (addrp != NULL) | |
253 | *addrp = addr; | |
254 | } | |
255 | \f | |
c906108c SS |
256 | /* Examine an i960 function prologue, recording the addresses at which |
257 | registers are saved explicitly by the prologue code, and returning | |
258 | the address of the first instruction after the prologue (but not | |
259 | after the instruction at address LIMIT, as explained below). | |
260 | ||
261 | LIMIT places an upper bound on addresses of the instructions to be | |
262 | examined. If the prologue code scan reaches LIMIT, the scan is | |
263 | aborted and LIMIT is returned. This is used, when examining the | |
264 | prologue for the current frame, to keep examine_prologue () from | |
265 | claiming that a given register has been saved when in fact the | |
266 | instruction that saves it has not yet been executed. LIMIT is used | |
267 | at other times to stop the scan when we hit code after the true | |
268 | function prologue (e.g. for the first source line) which might | |
269 | otherwise be mistaken for function prologue. | |
270 | ||
271 | The format of the function prologue matched by this routine is | |
272 | derived from examination of the source to gcc960 1.21, particularly | |
273 | the routine i960_function_prologue (). A "regular expression" for | |
274 | the function prologue is given below: | |
275 | ||
276 | (lda LRn, g14 | |
c5aa993b JM |
277 | mov g14, g[0-7] |
278 | (mov 0, g14) | (lda 0, g14))? | |
c906108c SS |
279 | |
280 | (mov[qtl]? g[0-15], r[4-15])* | |
281 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? | |
282 | (st[qtl]? g[0-15], n(fp))* | |
283 | ||
284 | (cmpobne 0, g14, LFn | |
c5aa993b JM |
285 | mov sp, g14 |
286 | lda 0x30(sp), sp | |
287 | LFn: stq g0, (g14) | |
288 | stq g4, 0x10(g14) | |
289 | stq g8, 0x20(g14))? | |
c906108c SS |
290 | |
291 | (st g14, n(fp))? | |
292 | (mov g13,r[4-15])? | |
c5aa993b | 293 | */ |
c906108c SS |
294 | |
295 | /* Macros for extracting fields from i960 instructions. */ | |
296 | ||
297 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
298 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
299 | ||
300 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) | |
301 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) | |
302 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
303 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
304 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) | |
305 | ||
306 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
307 | is not the address of a valid instruction, the address of the next | |
308 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
309 | of the instruction, and (for two-word instructions), *PWORD2 receives | |
310 | the second. */ | |
311 | ||
312 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ | |
313 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) | |
314 | ||
315 | static CORE_ADDR | |
fba45db2 KB |
316 | examine_prologue (register CORE_ADDR ip, register CORE_ADDR limit, |
317 | CORE_ADDR frame_addr, struct frame_saved_regs *fsr) | |
c906108c SS |
318 | { |
319 | register CORE_ADDR next_ip; | |
320 | register int src, dst; | |
321 | register unsigned int *pcode; | |
322 | unsigned int insn1, insn2; | |
323 | int size; | |
324 | int within_leaf_prologue; | |
325 | CORE_ADDR save_addr; | |
c5aa993b JM |
326 | static unsigned int varargs_prologue_code[] = |
327 | { | |
328 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ | |
329 | 0x5cf01601, /* mov sp, g14 */ | |
330 | 0x8c086030, /* lda 0x30(sp), sp */ | |
331 | 0xb2879000, /* LFn: stq g0, (g14) */ | |
332 | 0xb2a7a010, /* stq g4, 0x10(g14) */ | |
333 | 0xb2c7a020 /* stq g8, 0x20(g14) */ | |
334 | }; | |
c906108c SS |
335 | |
336 | /* Accept a leaf procedure prologue code fragment if present. | |
337 | Note that ip might point to either the leaf or non-leaf | |
338 | entry point; we look for the non-leaf entry point first: */ | |
339 | ||
340 | within_leaf_prologue = 0; | |
341 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
342 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ |
343 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ | |
c906108c SS |
344 | { |
345 | within_leaf_prologue = 1; | |
346 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); | |
347 | } | |
348 | ||
349 | /* Now look for the prologue code at a leaf entry point: */ | |
350 | ||
351 | if (next_ip | |
c5aa993b | 352 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
353 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) |
354 | { | |
355 | within_leaf_prologue = 1; | |
356 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) | |
c5aa993b JM |
357 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ |
358 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ | |
c906108c SS |
359 | { |
360 | ip = next_ip; | |
361 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
362 | within_leaf_prologue = 0; | |
363 | } | |
364 | } | |
365 | ||
366 | /* If something that looks like the beginning of a leaf prologue | |
367 | has been seen, but the remainder of the prologue is missing, bail. | |
368 | We don't know what we've got. */ | |
369 | ||
370 | if (within_leaf_prologue) | |
371 | return (ip); | |
c5aa993b | 372 | |
c906108c SS |
373 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. |
374 | This may cause us to mistake the moving of a register | |
375 | parameter to a local register for the saving of a callee-saved | |
376 | register, but that can't be helped, since with the | |
377 | "-fcall-saved" flag, any register can be made callee-saved. */ | |
378 | ||
379 | while (next_ip | |
380 | && (insn1 & 0xfc802fb0) == 0x5c000610 | |
381 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
382 | { | |
383 | src = REG_SRC1 (insn1); | |
384 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; | |
385 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
386 | while (size--) | |
387 | { | |
388 | fsr->regs[src++] = save_addr; | |
389 | save_addr += 4; | |
390 | } | |
391 | ip = next_ip; | |
392 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
393 | } | |
394 | ||
395 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ | |
396 | ||
397 | if (next_ip && | |
398 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ | |
399 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ | |
400 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ | |
401 | { | |
402 | ip = next_ip; | |
403 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
404 | } | |
405 | ||
406 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". | |
407 | This may cause us to mistake the copying of a register | |
408 | parameter to the frame for the saving of a callee-saved | |
409 | register, but that can't be helped, since with the | |
410 | "-fcall-saved" flag, any register can be made callee-saved. | |
411 | We can, however, refuse to accept a save of register g14, | |
412 | since that is matched explicitly below. */ | |
413 | ||
414 | while (next_ip && | |
c5aa993b JM |
415 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ |
416 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ | |
417 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ | |
418 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ | |
c906108c SS |
419 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) |
420 | { | |
421 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) | |
422 | ? insn2 : MEMA_OFFSET (insn1)); | |
423 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) | |
c5aa993b | 424 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); |
c906108c SS |
425 | while (size--) |
426 | { | |
427 | fsr->regs[src++] = save_addr; | |
428 | save_addr += 4; | |
429 | } | |
430 | ip = next_ip; | |
431 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
432 | } | |
433 | ||
434 | /* Accept the varargs prologue code if present. */ | |
435 | ||
436 | size = sizeof (varargs_prologue_code) / sizeof (int); | |
437 | pcode = varargs_prologue_code; | |
438 | while (size-- && next_ip && *pcode++ == insn1) | |
439 | { | |
440 | ip = next_ip; | |
441 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
442 | } | |
443 | ||
444 | /* Accept an optional "st g14, n(fp)". */ | |
445 | ||
446 | if (next_ip && | |
c5aa993b JM |
447 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ |
448 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ | |
c906108c SS |
449 | { |
450 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) | |
c5aa993b | 451 | ? insn2 : MEMA_OFFSET (insn1)); |
c906108c SS |
452 | ip = next_ip; |
453 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
454 | } | |
455 | ||
456 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. | |
457 | This is saving the address where a struct should be returned. */ | |
458 | ||
459 | if (next_ip | |
460 | && (insn1 & 0xff802fbf) == 0x5c00061d | |
461 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
462 | { | |
463 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
c5aa993b | 464 | fsr->regs[G0_REGNUM + 13] = save_addr; |
c906108c | 465 | ip = next_ip; |
c5aa993b | 466 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ |
c906108c SS |
467 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); |
468 | #endif | |
469 | } | |
470 | ||
471 | return (ip); | |
472 | } | |
473 | ||
474 | /* Given an ip value corresponding to the start of a function, | |
475 | return the ip of the first instruction after the function | |
476 | prologue. */ | |
477 | ||
478 | CORE_ADDR | |
5c678a12 | 479 | i960_skip_prologue (CORE_ADDR ip) |
c906108c SS |
480 | { |
481 | struct frame_saved_regs saved_regs_dummy; | |
482 | struct symtab_and_line sal; | |
483 | CORE_ADDR limit; | |
484 | ||
485 | sal = find_pc_line (ip, 0); | |
486 | limit = (sal.end) ? sal.end : 0xffffffff; | |
487 | ||
488 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); | |
489 | } | |
490 | ||
491 | /* Put here the code to store, into a struct frame_saved_regs, | |
492 | the addresses of the saved registers of frame described by FRAME_INFO. | |
493 | This includes special registers such as pc and fp saved in special | |
494 | ways in the stack frame. sp is even more special: | |
495 | the address we return for it IS the sp for the next frame. | |
496 | ||
497 | We cache the result of doing this in the frame_obstack, since it is | |
498 | fairly expensive. */ | |
499 | ||
500 | void | |
fba45db2 | 501 | frame_find_saved_regs (struct frame_info *fi, struct frame_saved_regs *fsr) |
c906108c SS |
502 | { |
503 | register CORE_ADDR next_addr; | |
504 | register CORE_ADDR *saved_regs; | |
505 | register int regnum; | |
506 | register struct frame_saved_regs *cache_fsr; | |
507 | CORE_ADDR ip; | |
508 | struct symtab_and_line sal; | |
509 | CORE_ADDR limit; | |
510 | ||
511 | if (!fi->fsr) | |
512 | { | |
513 | cache_fsr = (struct frame_saved_regs *) | |
514 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); | |
515 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); | |
516 | fi->fsr = cache_fsr; | |
517 | ||
518 | /* Find the start and end of the function prologue. If the PC | |
c5aa993b JM |
519 | is in the function prologue, we only consider the part that |
520 | has executed already. */ | |
521 | ||
c906108c SS |
522 | ip = get_pc_function_start (fi->pc); |
523 | sal = find_pc_line (ip, 0); | |
c5aa993b | 524 | limit = (sal.end && sal.end < fi->pc) ? sal.end : fi->pc; |
c906108c SS |
525 | |
526 | examine_prologue (ip, limit, fi->frame, cache_fsr); | |
527 | ||
528 | /* Record the addresses at which the local registers are saved. | |
c5aa993b JM |
529 | Strictly speaking, we should only do this for non-leaf procedures, |
530 | but no one will ever look at these values if it is a leaf procedure, | |
531 | since local registers are always caller-saved. */ | |
c906108c SS |
532 | |
533 | next_addr = (CORE_ADDR) fi->frame; | |
534 | saved_regs = cache_fsr->regs; | |
535 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) | |
536 | { | |
537 | *saved_regs++ = next_addr; | |
538 | next_addr += 4; | |
539 | } | |
540 | ||
541 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; | |
542 | } | |
543 | ||
544 | *fsr = *fi->fsr; | |
545 | ||
546 | /* Fetch the value of the sp from memory every time, since it | |
547 | is conceivable that it has changed since the cache was flushed. | |
548 | This unfortunately undoes much of the savings from caching the | |
549 | saved register values. I suggest adding an argument to | |
550 | get_frame_saved_regs () specifying the register number we're | |
551 | interested in (or -1 for all registers). This would be passed | |
552 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient | |
553 | computation of saved register addresses (e.g., on the i960, | |
554 | we don't have to examine the prologue to find local registers). | |
c5aa993b | 555 | -- markf@wrs.com |
c906108c SS |
556 | FIXME, we don't need to refetch this, since the cache is cleared |
557 | every time the child process is restarted. If GDB itself | |
558 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ | |
559 | ||
560 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); | |
561 | } | |
562 | ||
563 | /* Return the address of the argument block for the frame | |
564 | described by FI. Returns 0 if the address is unknown. */ | |
565 | ||
566 | CORE_ADDR | |
fba45db2 | 567 | frame_args_address (struct frame_info *fi, int must_be_correct) |
c906108c SS |
568 | { |
569 | struct frame_saved_regs fsr; | |
570 | CORE_ADDR ap; | |
571 | ||
572 | /* If g14 was saved in the frame by the function prologue code, return | |
573 | the saved value. If the frame is current and we are being sloppy, | |
574 | return the value of g14. Otherwise, return zero. */ | |
575 | ||
576 | get_frame_saved_regs (fi, &fsr); | |
577 | if (fsr.regs[G14_REGNUM]) | |
c5aa993b | 578 | ap = read_memory_integer (fsr.regs[G14_REGNUM], 4); |
c906108c SS |
579 | else |
580 | { | |
581 | if (must_be_correct) | |
c5aa993b | 582 | return 0; /* Don't cache this result */ |
c906108c SS |
583 | if (get_next_frame (fi)) |
584 | ap = 0; | |
585 | else | |
586 | ap = read_register (G14_REGNUM); | |
587 | if (ap == 0) | |
588 | ap = fi->frame; | |
589 | } | |
590 | fi->arg_pointer = ap; /* Cache it for next time */ | |
591 | return ap; | |
592 | } | |
593 | ||
594 | /* Return the address of the return struct for the frame | |
595 | described by FI. Returns 0 if the address is unknown. */ | |
596 | ||
597 | CORE_ADDR | |
fba45db2 | 598 | frame_struct_result_address (struct frame_info *fi) |
c906108c SS |
599 | { |
600 | struct frame_saved_regs fsr; | |
601 | CORE_ADDR ap; | |
602 | ||
603 | /* If the frame is non-current, check to see if g14 was saved in the | |
604 | frame by the function prologue code; return the saved value if so, | |
605 | zero otherwise. If the frame is current, return the value of g14. | |
606 | ||
607 | FIXME, shouldn't this use the saved value as long as we are past | |
608 | the function prologue, and only use the current value if we have | |
609 | no saved value and are at TOS? -- gnu@cygnus.com */ | |
610 | ||
611 | if (get_next_frame (fi)) | |
612 | { | |
613 | get_frame_saved_regs (fi, &fsr); | |
614 | if (fsr.regs[G13_REGNUM]) | |
c5aa993b | 615 | ap = read_memory_integer (fsr.regs[G13_REGNUM], 4); |
c906108c SS |
616 | else |
617 | ap = 0; | |
618 | } | |
619 | else | |
620 | ap = read_register (G13_REGNUM); | |
621 | ||
622 | return ap; | |
623 | } | |
624 | ||
625 | /* Return address to which the currently executing leafproc will return, | |
5c678a12 KB |
626 | or 0 if IP, the value of the instruction pointer from the currently |
627 | executing function, is not in a leafproc (or if we can't tell if it | |
628 | is). | |
c5aa993b | 629 | |
5c678a12 | 630 | Do this by finding the starting address of the routine in which IP lies. |
c906108c SS |
631 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this |
632 | is a leafproc and the return address is in register gx. Well, this is | |
633 | true unless the return address points at a RET instruction in the current | |
634 | procedure, which indicates that we have a 'dual entry' routine that | |
635 | has been entered through the CALL entry point. */ | |
636 | ||
637 | CORE_ADDR | |
5c678a12 | 638 | leafproc_return (CORE_ADDR ip) |
c906108c SS |
639 | { |
640 | register struct minimal_symbol *msymbol; | |
641 | char *p; | |
642 | int dst; | |
643 | unsigned int insn1, insn2; | |
644 | CORE_ADDR return_addr; | |
645 | ||
646 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) | |
647 | { | |
c5aa993b | 648 | if ((p = strchr (SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
c906108c SS |
649 | { |
650 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) | |
c5aa993b | 651 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
c906108c SS |
652 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) |
653 | { | |
654 | /* Get the return address. If the "mov g14, gx" | |
c5aa993b JM |
655 | instruction hasn't been executed yet, read |
656 | the return address from g14; otherwise, read it | |
657 | from the register into which g14 was moved. */ | |
c906108c SS |
658 | |
659 | return_addr = | |
c5aa993b JM |
660 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) |
661 | ? G14_REGNUM : dst); | |
c906108c SS |
662 | |
663 | /* We know we are in a leaf procedure, but we don't know | |
c5aa993b JM |
664 | whether the caller actually did a "bal" to the ".lf" |
665 | entry point, or a normal "call" to the non-leaf entry | |
666 | point one instruction before. In the latter case, the | |
667 | return address will be the address of a "ret" | |
668 | instruction within the procedure itself. We test for | |
669 | this below. */ | |
c906108c SS |
670 | |
671 | if (!next_insn (return_addr, &insn1, &insn2) | |
c5aa993b JM |
672 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ |
673 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) | |
c906108c SS |
674 | return (return_addr); |
675 | } | |
676 | } | |
677 | } | |
c5aa993b | 678 | |
c906108c SS |
679 | return (0); |
680 | } | |
681 | ||
682 | /* Immediately after a function call, return the saved pc. | |
683 | Can't go through the frames for this because on some machines | |
684 | the new frame is not set up until the new function executes | |
685 | some instructions. | |
686 | On the i960, the frame *is* set up immediately after the call, | |
687 | unless the function is a leaf procedure. */ | |
688 | ||
689 | CORE_ADDR | |
fba45db2 | 690 | saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
691 | { |
692 | CORE_ADDR saved_pc; | |
693 | ||
694 | saved_pc = leafproc_return (get_frame_pc (frame)); | |
695 | if (!saved_pc) | |
696 | saved_pc = FRAME_SAVED_PC (frame); | |
697 | ||
698 | return saved_pc; | |
699 | } | |
700 | ||
701 | /* Discard from the stack the innermost frame, | |
702 | restoring all saved registers. */ | |
703 | ||
704 | void | |
d4f3574e | 705 | i960_pop_frame (void) |
c906108c SS |
706 | { |
707 | register struct frame_info *current_fi, *prev_fi; | |
708 | register int i; | |
709 | CORE_ADDR save_addr; | |
710 | CORE_ADDR leaf_return_addr; | |
711 | struct frame_saved_regs fsr; | |
712 | char local_regs_buf[16 * 4]; | |
713 | ||
714 | current_fi = get_current_frame (); | |
715 | ||
716 | /* First, undo what the hardware does when we return. | |
717 | If this is a non-leaf procedure, restore local registers from | |
718 | the save area in the calling frame. Otherwise, load the return | |
719 | address obtained from leafproc_return () into the rip. */ | |
720 | ||
721 | leaf_return_addr = leafproc_return (current_fi->pc); | |
722 | if (!leaf_return_addr) | |
723 | { | |
724 | /* Non-leaf procedure. Restore local registers, incl IP. */ | |
725 | prev_fi = get_prev_frame (current_fi); | |
726 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); | |
c5aa993b JM |
727 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, |
728 | sizeof (local_regs_buf)); | |
c906108c SS |
729 | |
730 | /* Restore frame pointer. */ | |
731 | write_register (FP_REGNUM, prev_fi->frame); | |
732 | } | |
733 | else | |
734 | { | |
735 | /* Leaf procedure. Just restore the return address into the IP. */ | |
736 | write_register (RIP_REGNUM, leaf_return_addr); | |
737 | } | |
738 | ||
739 | /* Now restore any global regs that the current function had saved. */ | |
740 | get_frame_saved_regs (current_fi, &fsr); | |
741 | for (i = G0_REGNUM; i < G14_REGNUM; i++) | |
742 | { | |
7a292a7a SS |
743 | save_addr = fsr.regs[i]; |
744 | if (save_addr != 0) | |
c906108c SS |
745 | write_register (i, read_memory_integer (save_addr, 4)); |
746 | } | |
747 | ||
748 | /* Flush the frame cache, create a frame for the new innermost frame, | |
749 | and make it the current frame. */ | |
750 | ||
751 | flush_cached_frames (); | |
752 | } | |
753 | ||
754 | /* Given a 960 stop code (fault or trace), return the signal which | |
755 | corresponds. */ | |
756 | ||
757 | enum target_signal | |
fba45db2 | 758 | i960_fault_to_signal (int fault) |
c906108c SS |
759 | { |
760 | switch (fault) | |
761 | { | |
c5aa993b JM |
762 | case 0: |
763 | return TARGET_SIGNAL_BUS; /* parallel fault */ | |
764 | case 1: | |
765 | return TARGET_SIGNAL_UNKNOWN; | |
766 | case 2: | |
767 | return TARGET_SIGNAL_ILL; /* operation fault */ | |
768 | case 3: | |
769 | return TARGET_SIGNAL_FPE; /* arithmetic fault */ | |
770 | case 4: | |
771 | return TARGET_SIGNAL_FPE; /* floating point fault */ | |
c906108c SS |
772 | |
773 | /* constraint fault. This appears not to distinguish between | |
c5aa993b JM |
774 | a range constraint fault (which should be SIGFPE) and a privileged |
775 | fault (which should be SIGILL). */ | |
776 | case 5: | |
777 | return TARGET_SIGNAL_ILL; | |
c906108c | 778 | |
c5aa993b JM |
779 | case 6: |
780 | return TARGET_SIGNAL_SEGV; /* virtual memory fault */ | |
c906108c SS |
781 | |
782 | /* protection fault. This is for an out-of-range argument to | |
c5aa993b JM |
783 | "calls". I guess it also could be SIGILL. */ |
784 | case 7: | |
785 | return TARGET_SIGNAL_SEGV; | |
786 | ||
787 | case 8: | |
788 | return TARGET_SIGNAL_BUS; /* machine fault */ | |
789 | case 9: | |
790 | return TARGET_SIGNAL_BUS; /* structural fault */ | |
791 | case 0xa: | |
792 | return TARGET_SIGNAL_ILL; /* type fault */ | |
793 | case 0xb: | |
794 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
795 | case 0xc: | |
796 | return TARGET_SIGNAL_BUS; /* process fault */ | |
797 | case 0xd: | |
798 | return TARGET_SIGNAL_SEGV; /* descriptor fault */ | |
799 | case 0xe: | |
800 | return TARGET_SIGNAL_BUS; /* event fault */ | |
801 | case 0xf: | |
802 | return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
803 | case 0x10: | |
804 | return TARGET_SIGNAL_TRAP; /* single-step trace */ | |
805 | case 0x11: | |
806 | return TARGET_SIGNAL_TRAP; /* branch trace */ | |
807 | case 0x12: | |
808 | return TARGET_SIGNAL_TRAP; /* call trace */ | |
809 | case 0x13: | |
810 | return TARGET_SIGNAL_TRAP; /* return trace */ | |
811 | case 0x14: | |
812 | return TARGET_SIGNAL_TRAP; /* pre-return trace */ | |
813 | case 0x15: | |
814 | return TARGET_SIGNAL_TRAP; /* supervisor call trace */ | |
815 | case 0x16: | |
816 | return TARGET_SIGNAL_TRAP; /* breakpoint trace */ | |
817 | default: | |
818 | return TARGET_SIGNAL_UNKNOWN; | |
c906108c SS |
819 | } |
820 | } | |
821 | ||
822 | /****************************************/ | |
c5aa993b | 823 | /* MEM format */ |
c906108c SS |
824 | /****************************************/ |
825 | ||
c5aa993b JM |
826 | struct tabent |
827 | { | |
828 | char *name; | |
829 | char numops; | |
c906108c SS |
830 | }; |
831 | ||
5c678a12 KB |
832 | /* Return instruction length, either 4 or 8. When NOPRINT is non-zero |
833 | (TRUE), don't output any text. (Actually, as implemented, if NOPRINT | |
834 | is 0, abort() is called.) */ | |
835 | ||
836 | static int | |
837 | mem (unsigned long memaddr, unsigned long word1, unsigned long word2, | |
838 | int noprint) | |
c906108c | 839 | { |
c5aa993b JM |
840 | int i, j; |
841 | int len; | |
842 | int mode; | |
843 | int offset; | |
844 | const char *reg1, *reg2, *reg3; | |
845 | ||
846 | /* This lookup table is too sparse to make it worth typing in, but not | |
847 | * so large as to make a sparse array necessary. We allocate the | |
848 | * table at runtime, initialize all entries to empty, and copy the | |
849 | * real ones in from an initialization table. | |
850 | * | |
851 | * NOTE: In this table, the meaning of 'numops' is: | |
852 | * 1: single operand | |
853 | * 2: 2 operands, load instruction | |
854 | * -2: 2 operands, store instruction | |
855 | */ | |
856 | static struct tabent *mem_tab = NULL; | |
c906108c SS |
857 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ |
858 | #define MEM_MIN 0x80 | |
859 | #define MEM_MAX 0xcf | |
860 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) | |
861 | ||
c5aa993b JM |
862 | static struct |
863 | { | |
864 | int opcode; | |
865 | char *name; | |
866 | char numops; | |
867 | } | |
868 | mem_init[] = | |
869 | { | |
870 | 0x80, "ldob", 2, | |
871 | 0x82, "stob", -2, | |
872 | 0x84, "bx", 1, | |
873 | 0x85, "balx", 2, | |
874 | 0x86, "callx", 1, | |
875 | 0x88, "ldos", 2, | |
876 | 0x8a, "stos", -2, | |
877 | 0x8c, "lda", 2, | |
878 | 0x90, "ld", 2, | |
879 | 0x92, "st", -2, | |
880 | 0x98, "ldl", 2, | |
881 | 0x9a, "stl", -2, | |
882 | 0xa0, "ldt", 2, | |
883 | 0xa2, "stt", -2, | |
884 | 0xb0, "ldq", 2, | |
885 | 0xb2, "stq", -2, | |
886 | 0xc0, "ldib", 2, | |
887 | 0xc2, "stib", -2, | |
888 | 0xc8, "ldis", 2, | |
889 | 0xca, "stis", -2, | |
890 | 0, NULL, 0 | |
891 | }; | |
892 | ||
893 | if (mem_tab == NULL) | |
894 | { | |
895 | mem_tab = (struct tabent *) xmalloc (MEM_SIZ); | |
896 | memset (mem_tab, '\0', MEM_SIZ); | |
897 | for (i = 0; mem_init[i].opcode != 0; i++) | |
898 | { | |
899 | j = mem_init[i].opcode - MEM_MIN; | |
900 | mem_tab[j].name = mem_init[i].name; | |
901 | mem_tab[j].numops = mem_init[i].numops; | |
c906108c | 902 | } |
c5aa993b | 903 | } |
c906108c | 904 | |
c5aa993b JM |
905 | i = ((word1 >> 24) & 0xff) - MEM_MIN; |
906 | mode = (word1 >> 10) & 0xf; | |
c906108c | 907 | |
c5aa993b JM |
908 | if ((mem_tab[i].name != NULL) /* Valid instruction */ |
909 | && ((mode == 5) || (mode >= 12))) | |
910 | { /* With 32-bit displacement */ | |
911 | len = 8; | |
912 | } | |
913 | else | |
914 | { | |
915 | len = 4; | |
916 | } | |
c906108c | 917 | |
c5aa993b JM |
918 | if (noprint) |
919 | { | |
920 | return len; | |
921 | } | |
e1e9e218 | 922 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
923 | } |
924 | ||
925 | /* Read the i960 instruction at 'memaddr' and return the address of | |
926 | the next instruction after that, or 0 if 'memaddr' is not the | |
927 | address of a valid instruction. The first word of the instruction | |
928 | is stored at 'pword1', and the second word, if any, is stored at | |
929 | 'pword2'. */ | |
930 | ||
931 | static CORE_ADDR | |
fba45db2 | 932 | next_insn (CORE_ADDR memaddr, unsigned int *pword1, unsigned int *pword2) |
c906108c SS |
933 | { |
934 | int len; | |
935 | char buf[8]; | |
936 | ||
937 | /* Read the two (potential) words of the instruction at once, | |
938 | to eliminate the overhead of two calls to read_memory (). | |
939 | FIXME: Loses if the first one is readable but the second is not | |
940 | (e.g. last word of the segment). */ | |
941 | ||
942 | read_memory (memaddr, buf, 8); | |
943 | *pword1 = extract_unsigned_integer (buf, 4); | |
944 | *pword2 = extract_unsigned_integer (buf + 4, 4); | |
945 | ||
c5aa993b | 946 | /* Divide instruction set into classes based on high 4 bits of opcode */ |
c906108c SS |
947 | |
948 | switch ((*pword1 >> 28) & 0xf) | |
949 | { | |
950 | case 0x0: | |
c5aa993b | 951 | case 0x1: /* ctrl */ |
c906108c SS |
952 | |
953 | case 0x2: | |
c5aa993b | 954 | case 0x3: /* cobr */ |
c906108c SS |
955 | |
956 | case 0x5: | |
957 | case 0x6: | |
c5aa993b | 958 | case 0x7: /* reg */ |
c906108c SS |
959 | len = 4; |
960 | break; | |
961 | ||
962 | case 0x8: | |
963 | case 0x9: | |
964 | case 0xa: | |
965 | case 0xb: | |
966 | case 0xc: | |
967 | len = mem (memaddr, *pword1, *pword2, 1); | |
968 | break; | |
969 | ||
c5aa993b | 970 | default: /* invalid instruction */ |
c906108c SS |
971 | len = 0; |
972 | break; | |
973 | } | |
974 | ||
975 | if (len) | |
976 | return memaddr + len; | |
977 | else | |
978 | return 0; | |
979 | } | |
980 | ||
981 | /* 'start_frame' is a variable in the MON960 runtime startup routine | |
982 | that contains the frame pointer of the 'start' routine (the routine | |
983 | that calls 'main'). By reading its contents out of remote memory, | |
984 | we can tell where the frame chain ends: backtraces should halt before | |
985 | they display this frame. */ | |
986 | ||
987 | int | |
fba45db2 | 988 | mon960_frame_chain_valid (CORE_ADDR chain, struct frame_info *curframe) |
c906108c | 989 | { |
c5aa993b JM |
990 | struct symbol *sym; |
991 | struct minimal_symbol *msymbol; | |
992 | ||
993 | /* crtmon960.o is an assembler module that is assumed to be linked | |
994 | * first in an i80960 executable. It contains the true entry point; | |
995 | * it performs startup up initialization and then calls 'main'. | |
996 | * | |
997 | * 'sf' is the name of a variable in crtmon960.o that is set | |
998 | * during startup to the address of the first frame. | |
999 | * | |
1000 | * 'a' is the address of that variable in 80960 memory. | |
1001 | */ | |
1002 | static char sf[] = "start_frame"; | |
1003 | CORE_ADDR a; | |
1004 | ||
1005 | ||
1006 | chain &= ~0x3f; /* Zero low 6 bits because previous frame pointers | |
1007 | contain return status info in them. */ | |
1008 | if (chain == 0) | |
1009 | { | |
1010 | return 0; | |
1011 | } | |
c906108c | 1012 | |
c5aa993b JM |
1013 | sym = lookup_symbol (sf, 0, VAR_NAMESPACE, (int *) NULL, |
1014 | (struct symtab **) NULL); | |
1015 | if (sym != 0) | |
1016 | { | |
1017 | a = SYMBOL_VALUE (sym); | |
1018 | } | |
1019 | else | |
1020 | { | |
1021 | msymbol = lookup_minimal_symbol (sf, NULL, NULL); | |
1022 | if (msymbol == NULL) | |
1023 | return 0; | |
1024 | a = SYMBOL_VALUE_ADDRESS (msymbol); | |
1025 | } | |
c906108c | 1026 | |
c5aa993b | 1027 | return (chain != read_memory_integer (a, 4)); |
c906108c SS |
1028 | } |
1029 | ||
2acceee2 | 1030 | |
c906108c | 1031 | void |
fba45db2 | 1032 | _initialize_i960_tdep (void) |
c906108c SS |
1033 | { |
1034 | check_host (); | |
1035 | ||
1036 | tm_print_insn = print_insn_i960; | |
1037 | } |