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dd3b648e | 1 | /* Target-machine dependent code for the Intel 960 |
18b46e7c | 2 | Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc. |
dd3b648e RP |
3 | Contributed by Intel Corporation. |
4 | examine_prologue and other parts contributed by Wind River Systems. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
99a7de40 JG |
10 | the Free Software Foundation; either version 2 of the License, or |
11 | (at your option) any later version. | |
dd3b648e RP |
12 | |
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
99a7de40 | 19 | along with this program; if not, write to the Free Software |
6c9638b4 | 20 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
dd3b648e | 21 | |
dd3b648e | 22 | #include "defs.h" |
dd3b648e RP |
23 | #include "symtab.h" |
24 | #include "value.h" | |
25 | #include "frame.h" | |
48792545 | 26 | #include "floatformat.h" |
98506620 | 27 | #include "target.h" |
b607efe7 | 28 | #include "gdbcore.h" |
dd3b648e | 29 | |
18b46e7c | 30 | static CORE_ADDR next_insn PARAMS ((CORE_ADDR memaddr, |
ff7116e2 SG |
31 | unsigned int *pword1, |
32 | unsigned int *pword2)); | |
18b46e7c | 33 | |
98760eab AC |
34 | /* Does the specified function use the "struct returning" convention |
35 | or the "value returning" convention? The "value returning" convention | |
36 | almost invariably returns the entire value in registers. The | |
37 | "struct returning" convention often returns the entire value in | |
38 | memory, and passes a pointer (out of or into the function) saying | |
39 | where the value (is or should go). | |
40 | ||
41 | Since this sometimes depends on whether it was compiled with GCC, | |
42 | this is also an argument. This is used in call_function to build a | |
43 | stack, and in value_being_returned to print return values. | |
44 | ||
45 | On i960, a structure is returned in registers g0-g3, if it will fit. | |
46 | If it's more than 16 bytes long, g13 pointed to it on entry. */ | |
47 | ||
48 | int | |
49 | i960_use_struct_convention (gcc_p, type) | |
50 | int gcc_p; | |
51 | struct type *type; | |
52 | { | |
53 | return (TYPE_LENGTH (type) > 16); | |
54 | } | |
55 | ||
dd3b648e RP |
56 | /* gdb960 is always running on a non-960 host. Check its characteristics. |
57 | This routine must be called as part of gdb initialization. */ | |
58 | ||
59 | static void | |
60 | check_host() | |
61 | { | |
62 | int i; | |
63 | ||
64 | static struct typestruct { | |
65 | int hostsize; /* Size of type on host */ | |
66 | int i960size; /* Size of type on i960 */ | |
67 | char *typename; /* Name of type, for error msg */ | |
68 | } types[] = { | |
69 | { sizeof(short), 2, "short" }, | |
70 | { sizeof(int), 4, "int" }, | |
71 | { sizeof(long), 4, "long" }, | |
72 | { sizeof(float), 4, "float" }, | |
73 | { sizeof(double), 8, "double" }, | |
74 | { sizeof(char *), 4, "pointer" }, | |
75 | }; | |
76 | #define TYPELEN (sizeof(types) / sizeof(struct typestruct)) | |
77 | ||
78 | /* Make sure that host type sizes are same as i960 | |
79 | */ | |
80 | for ( i = 0; i < TYPELEN; i++ ){ | |
81 | if ( types[i].hostsize != types[i].i960size ){ | |
199b2450 | 82 | printf_unfiltered("sizeof(%s) != %d: PROCEED AT YOUR OWN RISK!\n", |
dd3b648e RP |
83 | types[i].typename, types[i].i960size ); |
84 | } | |
85 | ||
86 | } | |
87 | } | |
88 | \f | |
89 | /* Examine an i960 function prologue, recording the addresses at which | |
90 | registers are saved explicitly by the prologue code, and returning | |
91 | the address of the first instruction after the prologue (but not | |
92 | after the instruction at address LIMIT, as explained below). | |
93 | ||
94 | LIMIT places an upper bound on addresses of the instructions to be | |
95 | examined. If the prologue code scan reaches LIMIT, the scan is | |
96 | aborted and LIMIT is returned. This is used, when examining the | |
97 | prologue for the current frame, to keep examine_prologue () from | |
98 | claiming that a given register has been saved when in fact the | |
99 | instruction that saves it has not yet been executed. LIMIT is used | |
100 | at other times to stop the scan when we hit code after the true | |
101 | function prologue (e.g. for the first source line) which might | |
102 | otherwise be mistaken for function prologue. | |
103 | ||
104 | The format of the function prologue matched by this routine is | |
105 | derived from examination of the source to gcc960 1.21, particularly | |
106 | the routine i960_function_prologue (). A "regular expression" for | |
107 | the function prologue is given below: | |
108 | ||
109 | (lda LRn, g14 | |
110 | mov g14, g[0-7] | |
111 | (mov 0, g14) | (lda 0, g14))? | |
112 | ||
113 | (mov[qtl]? g[0-15], r[4-15])* | |
114 | ((addo [1-31], sp, sp) | (lda n(sp), sp))? | |
115 | (st[qtl]? g[0-15], n(fp))* | |
116 | ||
117 | (cmpobne 0, g14, LFn | |
118 | mov sp, g14 | |
119 | lda 0x30(sp), sp | |
120 | LFn: stq g0, (g14) | |
121 | stq g4, 0x10(g14) | |
122 | stq g8, 0x20(g14))? | |
123 | ||
124 | (st g14, n(fp))? | |
125 | (mov g13,r[4-15])? | |
126 | */ | |
127 | ||
128 | /* Macros for extracting fields from i960 instructions. */ | |
129 | ||
130 | #define BITMASK(pos, width) (((0x1 << (width)) - 1) << (pos)) | |
131 | #define EXTRACT_FIELD(val, pos, width) ((val) >> (pos) & BITMASK (0, width)) | |
132 | ||
133 | #define REG_SRC1(insn) EXTRACT_FIELD (insn, 0, 5) | |
134 | #define REG_SRC2(insn) EXTRACT_FIELD (insn, 14, 5) | |
135 | #define REG_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
136 | #define MEM_SRCDST(insn) EXTRACT_FIELD (insn, 19, 5) | |
137 | #define MEMA_OFFSET(insn) EXTRACT_FIELD (insn, 0, 12) | |
138 | ||
139 | /* Fetch the instruction at ADDR, returning 0 if ADDR is beyond LIM or | |
140 | is not the address of a valid instruction, the address of the next | |
141 | instruction beyond ADDR otherwise. *PWORD1 receives the first word | |
142 | of the instruction, and (for two-word instructions), *PWORD2 receives | |
143 | the second. */ | |
144 | ||
145 | #define NEXT_PROLOGUE_INSN(addr, lim, pword1, pword2) \ | |
146 | (((addr) < (lim)) ? next_insn (addr, pword1, pword2) : 0) | |
147 | ||
148 | static CORE_ADDR | |
149 | examine_prologue (ip, limit, frame_addr, fsr) | |
150 | register CORE_ADDR ip; | |
151 | register CORE_ADDR limit; | |
669caa9c | 152 | CORE_ADDR frame_addr; |
dd3b648e RP |
153 | struct frame_saved_regs *fsr; |
154 | { | |
155 | register CORE_ADDR next_ip; | |
156 | register int src, dst; | |
157 | register unsigned int *pcode; | |
158 | unsigned int insn1, insn2; | |
159 | int size; | |
160 | int within_leaf_prologue; | |
161 | CORE_ADDR save_addr; | |
162 | static unsigned int varargs_prologue_code [] = | |
163 | { | |
164 | 0x3507a00c, /* cmpobne 0x0, g14, LFn */ | |
165 | 0x5cf01601, /* mov sp, g14 */ | |
166 | 0x8c086030, /* lda 0x30(sp), sp */ | |
167 | 0xb2879000, /* LFn: stq g0, (g14) */ | |
168 | 0xb2a7a010, /* stq g4, 0x10(g14) */ | |
169 | 0xb2c7a020 /* stq g8, 0x20(g14) */ | |
170 | }; | |
171 | ||
172 | /* Accept a leaf procedure prologue code fragment if present. | |
173 | Note that ip might point to either the leaf or non-leaf | |
174 | entry point; we look for the non-leaf entry point first: */ | |
175 | ||
176 | within_leaf_prologue = 0; | |
177 | if ((next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2)) | |
178 | && ((insn1 & 0xfffff000) == 0x8cf00000 /* lda LRx, g14 (MEMA) */ | |
179 | || (insn1 & 0xfffffc60) == 0x8cf03000)) /* lda LRx, g14 (MEMB) */ | |
180 | { | |
181 | within_leaf_prologue = 1; | |
182 | next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2); | |
183 | } | |
184 | ||
185 | /* Now look for the prologue code at a leaf entry point: */ | |
186 | ||
187 | if (next_ip | |
188 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ | |
189 | && REG_SRCDST (insn1) <= G0_REGNUM + 7) | |
190 | { | |
191 | within_leaf_prologue = 1; | |
192 | if ((next_ip = NEXT_PROLOGUE_INSN (next_ip, limit, &insn1, &insn2)) | |
193 | && (insn1 == 0x8cf00000 /* lda 0, g14 */ | |
194 | || insn1 == 0x5cf01e00)) /* mov 0, g14 */ | |
195 | { | |
196 | ip = next_ip; | |
197 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
198 | within_leaf_prologue = 0; | |
199 | } | |
200 | } | |
201 | ||
202 | /* If something that looks like the beginning of a leaf prologue | |
203 | has been seen, but the remainder of the prologue is missing, bail. | |
204 | We don't know what we've got. */ | |
205 | ||
206 | if (within_leaf_prologue) | |
207 | return (ip); | |
208 | ||
209 | /* Accept zero or more instances of "mov[qtl]? gx, ry", where y >= 4. | |
210 | This may cause us to mistake the moving of a register | |
211 | parameter to a local register for the saving of a callee-saved | |
212 | register, but that can't be helped, since with the | |
213 | "-fcall-saved" flag, any register can be made callee-saved. */ | |
214 | ||
215 | while (next_ip | |
216 | && (insn1 & 0xfc802fb0) == 0x5c000610 | |
217 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
218 | { | |
219 | src = REG_SRC1 (insn1); | |
220 | size = EXTRACT_FIELD (insn1, 24, 2) + 1; | |
221 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
222 | while (size--) | |
223 | { | |
224 | fsr->regs[src++] = save_addr; | |
225 | save_addr += 4; | |
226 | } | |
227 | ip = next_ip; | |
228 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
229 | } | |
230 | ||
231 | /* Accept an optional "addo n, sp, sp" or "lda n(sp), sp". */ | |
232 | ||
233 | if (next_ip && | |
234 | ((insn1 & 0xffffffe0) == 0x59084800 /* addo n, sp, sp */ | |
235 | || (insn1 & 0xfffff000) == 0x8c086000 /* lda n(sp), sp (MEMA) */ | |
236 | || (insn1 & 0xfffffc60) == 0x8c087400)) /* lda n(sp), sp (MEMB) */ | |
237 | { | |
238 | ip = next_ip; | |
239 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
240 | } | |
241 | ||
242 | /* Accept zero or more instances of "st[qtl]? gx, n(fp)". | |
243 | This may cause us to mistake the copying of a register | |
244 | parameter to the frame for the saving of a callee-saved | |
245 | register, but that can't be helped, since with the | |
246 | "-fcall-saved" flag, any register can be made callee-saved. | |
247 | We can, however, refuse to accept a save of register g14, | |
248 | since that is matched explicitly below. */ | |
249 | ||
250 | while (next_ip && | |
251 | ((insn1 & 0xf787f000) == 0x9287e000 /* stl? gx, n(fp) (MEMA) */ | |
252 | || (insn1 & 0xf787fc60) == 0x9287f400 /* stl? gx, n(fp) (MEMB) */ | |
253 | || (insn1 & 0xef87f000) == 0xa287e000 /* st[tq] gx, n(fp) (MEMA) */ | |
254 | || (insn1 & 0xef87fc60) == 0xa287f400) /* st[tq] gx, n(fp) (MEMB) */ | |
255 | && ((src = MEM_SRCDST (insn1)) != G14_REGNUM)) | |
256 | { | |
257 | save_addr = frame_addr + ((insn1 & BITMASK (12, 1)) | |
258 | ? insn2 : MEMA_OFFSET (insn1)); | |
259 | size = (insn1 & BITMASK (29, 1)) ? ((insn1 & BITMASK (28, 1)) ? 4 : 3) | |
260 | : ((insn1 & BITMASK (27, 1)) ? 2 : 1); | |
261 | while (size--) | |
262 | { | |
263 | fsr->regs[src++] = save_addr; | |
264 | save_addr += 4; | |
265 | } | |
266 | ip = next_ip; | |
267 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
268 | } | |
269 | ||
270 | /* Accept the varargs prologue code if present. */ | |
271 | ||
272 | size = sizeof (varargs_prologue_code) / sizeof (int); | |
273 | pcode = varargs_prologue_code; | |
274 | while (size-- && next_ip && *pcode++ == insn1) | |
275 | { | |
276 | ip = next_ip; | |
277 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
278 | } | |
279 | ||
280 | /* Accept an optional "st g14, n(fp)". */ | |
281 | ||
282 | if (next_ip && | |
283 | ((insn1 & 0xfffff000) == 0x92f7e000 /* st g14, n(fp) (MEMA) */ | |
284 | || (insn1 & 0xfffffc60) == 0x92f7f400)) /* st g14, n(fp) (MEMB) */ | |
285 | { | |
286 | fsr->regs[G14_REGNUM] = frame_addr + ((insn1 & BITMASK (12, 1)) | |
287 | ? insn2 : MEMA_OFFSET (insn1)); | |
288 | ip = next_ip; | |
289 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
290 | } | |
291 | ||
292 | /* Accept zero or one instance of "mov g13, ry", where y >= 4. | |
293 | This is saving the address where a struct should be returned. */ | |
294 | ||
295 | if (next_ip | |
296 | && (insn1 & 0xff802fbf) == 0x5c00061d | |
297 | && (dst = REG_SRCDST (insn1)) >= (R0_REGNUM + 4)) | |
298 | { | |
299 | save_addr = frame_addr + ((dst - R0_REGNUM) * 4); | |
300 | fsr->regs[G0_REGNUM+13] = save_addr; | |
301 | ip = next_ip; | |
302 | #if 0 /* We'll need this once there is a subsequent instruction examined. */ | |
303 | next_ip = NEXT_PROLOGUE_INSN (ip, limit, &insn1, &insn2); | |
304 | #endif | |
305 | } | |
306 | ||
307 | return (ip); | |
308 | } | |
309 | ||
310 | /* Given an ip value corresponding to the start of a function, | |
311 | return the ip of the first instruction after the function | |
312 | prologue. */ | |
313 | ||
314 | CORE_ADDR | |
315 | skip_prologue (ip) | |
316 | CORE_ADDR (ip); | |
317 | { | |
318 | struct frame_saved_regs saved_regs_dummy; | |
319 | struct symtab_and_line sal; | |
320 | CORE_ADDR limit; | |
321 | ||
322 | sal = find_pc_line (ip, 0); | |
323 | limit = (sal.end) ? sal.end : 0xffffffff; | |
324 | ||
669caa9c | 325 | return (examine_prologue (ip, limit, (CORE_ADDR) 0, &saved_regs_dummy)); |
dd3b648e RP |
326 | } |
327 | ||
328 | /* Put here the code to store, into a struct frame_saved_regs, | |
329 | the addresses of the saved registers of frame described by FRAME_INFO. | |
330 | This includes special registers such as pc and fp saved in special | |
331 | ways in the stack frame. sp is even more special: | |
332 | the address we return for it IS the sp for the next frame. | |
333 | ||
86a51f41 AC |
334 | We cache the result of doing this in the frame_obstack, since it is |
335 | fairly expensive. */ | |
dd3b648e RP |
336 | |
337 | void | |
338 | frame_find_saved_regs (fi, fsr) | |
339 | struct frame_info *fi; | |
340 | struct frame_saved_regs *fsr; | |
341 | { | |
342 | register CORE_ADDR next_addr; | |
343 | register CORE_ADDR *saved_regs; | |
344 | register int regnum; | |
345 | register struct frame_saved_regs *cache_fsr; | |
dd3b648e RP |
346 | CORE_ADDR ip; |
347 | struct symtab_and_line sal; | |
348 | CORE_ADDR limit; | |
349 | ||
350 | if (!fi->fsr) | |
351 | { | |
352 | cache_fsr = (struct frame_saved_regs *) | |
86a51f41 | 353 | frame_obstack_alloc (sizeof (struct frame_saved_regs)); |
4ed97c9a | 354 | memset (cache_fsr, '\0', sizeof (struct frame_saved_regs)); |
dd3b648e RP |
355 | fi->fsr = cache_fsr; |
356 | ||
357 | /* Find the start and end of the function prologue. If the PC | |
358 | is in the function prologue, we only consider the part that | |
359 | has executed already. */ | |
360 | ||
361 | ip = get_pc_function_start (fi->pc); | |
362 | sal = find_pc_line (ip, 0); | |
363 | limit = (sal.end && sal.end < fi->pc) ? sal.end: fi->pc; | |
364 | ||
365 | examine_prologue (ip, limit, fi->frame, cache_fsr); | |
366 | ||
367 | /* Record the addresses at which the local registers are saved. | |
368 | Strictly speaking, we should only do this for non-leaf procedures, | |
369 | but no one will ever look at these values if it is a leaf procedure, | |
370 | since local registers are always caller-saved. */ | |
371 | ||
372 | next_addr = (CORE_ADDR) fi->frame; | |
373 | saved_regs = cache_fsr->regs; | |
374 | for (regnum = R0_REGNUM; regnum <= R15_REGNUM; regnum++) | |
375 | { | |
376 | *saved_regs++ = next_addr; | |
377 | next_addr += 4; | |
378 | } | |
379 | ||
380 | cache_fsr->regs[FP_REGNUM] = cache_fsr->regs[PFP_REGNUM]; | |
381 | } | |
382 | ||
383 | *fsr = *fi->fsr; | |
384 | ||
385 | /* Fetch the value of the sp from memory every time, since it | |
386 | is conceivable that it has changed since the cache was flushed. | |
387 | This unfortunately undoes much of the savings from caching the | |
388 | saved register values. I suggest adding an argument to | |
389 | get_frame_saved_regs () specifying the register number we're | |
390 | interested in (or -1 for all registers). This would be passed | |
391 | through to FRAME_FIND_SAVED_REGS (), permitting more efficient | |
392 | computation of saved register addresses (e.g., on the i960, | |
393 | we don't have to examine the prologue to find local registers). | |
394 | -- markf@wrs.com | |
395 | FIXME, we don't need to refetch this, since the cache is cleared | |
396 | every time the child process is restarted. If GDB itself | |
397 | modifies SP, it has to clear the cache by hand (does it?). -gnu */ | |
398 | ||
399 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[SP_REGNUM], 4); | |
400 | } | |
401 | ||
402 | /* Return the address of the argument block for the frame | |
403 | described by FI. Returns 0 if the address is unknown. */ | |
404 | ||
405 | CORE_ADDR | |
406 | frame_args_address (fi, must_be_correct) | |
407 | struct frame_info *fi; | |
408 | { | |
dd3b648e RP |
409 | struct frame_saved_regs fsr; |
410 | CORE_ADDR ap; | |
411 | ||
412 | /* If g14 was saved in the frame by the function prologue code, return | |
413 | the saved value. If the frame is current and we are being sloppy, | |
414 | return the value of g14. Otherwise, return zero. */ | |
415 | ||
dd3b648e RP |
416 | get_frame_saved_regs (fi, &fsr); |
417 | if (fsr.regs[G14_REGNUM]) | |
418 | ap = read_memory_integer (fsr.regs[G14_REGNUM],4); | |
669caa9c SS |
419 | else |
420 | { | |
421 | if (must_be_correct) | |
422 | return 0; /* Don't cache this result */ | |
423 | if (get_next_frame (fi)) | |
424 | ap = 0; | |
425 | else | |
426 | ap = read_register (G14_REGNUM); | |
427 | if (ap == 0) | |
428 | ap = fi->frame; | |
429 | } | |
dd3b648e RP |
430 | fi->arg_pointer = ap; /* Cache it for next time */ |
431 | return ap; | |
432 | } | |
433 | ||
434 | /* Return the address of the return struct for the frame | |
435 | described by FI. Returns 0 if the address is unknown. */ | |
436 | ||
437 | CORE_ADDR | |
438 | frame_struct_result_address (fi) | |
439 | struct frame_info *fi; | |
440 | { | |
dd3b648e RP |
441 | struct frame_saved_regs fsr; |
442 | CORE_ADDR ap; | |
443 | ||
444 | /* If the frame is non-current, check to see if g14 was saved in the | |
445 | frame by the function prologue code; return the saved value if so, | |
446 | zero otherwise. If the frame is current, return the value of g14. | |
447 | ||
448 | FIXME, shouldn't this use the saved value as long as we are past | |
449 | the function prologue, and only use the current value if we have | |
450 | no saved value and are at TOS? -- gnu@cygnus.com */ | |
451 | ||
669caa9c SS |
452 | if (get_next_frame (fi)) |
453 | { | |
454 | get_frame_saved_regs (fi, &fsr); | |
455 | if (fsr.regs[G13_REGNUM]) | |
456 | ap = read_memory_integer (fsr.regs[G13_REGNUM],4); | |
457 | else | |
458 | ap = 0; | |
459 | } | |
460 | else | |
dd3b648e | 461 | ap = read_register (G13_REGNUM); |
669caa9c | 462 | |
dd3b648e RP |
463 | return ap; |
464 | } | |
465 | ||
466 | /* Return address to which the currently executing leafproc will return, | |
467 | or 0 if ip is not in a leafproc (or if we can't tell if it is). | |
468 | ||
469 | Do this by finding the starting address of the routine in which ip lies. | |
470 | If the instruction there is "mov g14, gx" (where x is in [0,7]), this | |
471 | is a leafproc and the return address is in register gx. Well, this is | |
472 | true unless the return address points at a RET instruction in the current | |
473 | procedure, which indicates that we have a 'dual entry' routine that | |
474 | has been entered through the CALL entry point. */ | |
475 | ||
476 | CORE_ADDR | |
477 | leafproc_return (ip) | |
478 | CORE_ADDR ip; /* ip from currently executing function */ | |
479 | { | |
1ab3bf1b | 480 | register struct minimal_symbol *msymbol; |
dd3b648e RP |
481 | char *p; |
482 | int dst; | |
483 | unsigned int insn1, insn2; | |
484 | CORE_ADDR return_addr; | |
dd3b648e | 485 | |
1ab3bf1b | 486 | if ((msymbol = lookup_minimal_symbol_by_pc (ip)) != NULL) |
dd3b648e | 487 | { |
c398de0c | 488 | if ((p = strchr(SYMBOL_NAME (msymbol), '.')) && STREQ (p, ".lf")) |
dd3b648e | 489 | { |
81028ab0 | 490 | if (next_insn (SYMBOL_VALUE_ADDRESS (msymbol), &insn1, &insn2) |
dd3b648e RP |
491 | && (insn1 & 0xff87ffff) == 0x5c80161e /* mov g14, gx */ |
492 | && (dst = REG_SRCDST (insn1)) <= G0_REGNUM + 7) | |
493 | { | |
494 | /* Get the return address. If the "mov g14, gx" | |
495 | instruction hasn't been executed yet, read | |
496 | the return address from g14; otherwise, read it | |
497 | from the register into which g14 was moved. */ | |
498 | ||
81028ab0 FF |
499 | return_addr = |
500 | read_register ((ip == SYMBOL_VALUE_ADDRESS (msymbol)) | |
dd3b648e RP |
501 | ? G14_REGNUM : dst); |
502 | ||
503 | /* We know we are in a leaf procedure, but we don't know | |
504 | whether the caller actually did a "bal" to the ".lf" | |
505 | entry point, or a normal "call" to the non-leaf entry | |
506 | point one instruction before. In the latter case, the | |
507 | return address will be the address of a "ret" | |
508 | instruction within the procedure itself. We test for | |
509 | this below. */ | |
510 | ||
511 | if (!next_insn (return_addr, &insn1, &insn2) | |
512 | || (insn1 & 0xff000000) != 0xa000000 /* ret */ | |
1ab3bf1b | 513 | || lookup_minimal_symbol_by_pc (return_addr) != msymbol) |
dd3b648e RP |
514 | return (return_addr); |
515 | } | |
516 | } | |
517 | } | |
518 | ||
519 | return (0); | |
520 | } | |
521 | ||
522 | /* Immediately after a function call, return the saved pc. | |
523 | Can't go through the frames for this because on some machines | |
524 | the new frame is not set up until the new function executes | |
525 | some instructions. | |
526 | On the i960, the frame *is* set up immediately after the call, | |
527 | unless the function is a leaf procedure. */ | |
528 | ||
529 | CORE_ADDR | |
530 | saved_pc_after_call (frame) | |
669caa9c | 531 | struct frame_info *frame; |
dd3b648e RP |
532 | { |
533 | CORE_ADDR saved_pc; | |
dd3b648e RP |
534 | |
535 | saved_pc = leafproc_return (get_frame_pc (frame)); | |
536 | if (!saved_pc) | |
537 | saved_pc = FRAME_SAVED_PC (frame); | |
538 | ||
669caa9c | 539 | return saved_pc; |
dd3b648e RP |
540 | } |
541 | ||
542 | /* Discard from the stack the innermost frame, | |
543 | restoring all saved registers. */ | |
544 | ||
1c3cd1b0 | 545 | void |
dd3b648e RP |
546 | pop_frame () |
547 | { | |
548 | register struct frame_info *current_fi, *prev_fi; | |
549 | register int i; | |
550 | CORE_ADDR save_addr; | |
551 | CORE_ADDR leaf_return_addr; | |
552 | struct frame_saved_regs fsr; | |
553 | char local_regs_buf[16 * 4]; | |
554 | ||
669caa9c | 555 | current_fi = get_current_frame (); |
dd3b648e RP |
556 | |
557 | /* First, undo what the hardware does when we return. | |
558 | If this is a non-leaf procedure, restore local registers from | |
559 | the save area in the calling frame. Otherwise, load the return | |
560 | address obtained from leafproc_return () into the rip. */ | |
561 | ||
562 | leaf_return_addr = leafproc_return (current_fi->pc); | |
563 | if (!leaf_return_addr) | |
564 | { | |
565 | /* Non-leaf procedure. Restore local registers, incl IP. */ | |
669caa9c | 566 | prev_fi = get_prev_frame (current_fi); |
dd3b648e RP |
567 | read_memory (prev_fi->frame, local_regs_buf, sizeof (local_regs_buf)); |
568 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), local_regs_buf, | |
569 | sizeof (local_regs_buf)); | |
570 | ||
571 | /* Restore frame pointer. */ | |
572 | write_register (FP_REGNUM, prev_fi->frame); | |
573 | } | |
574 | else | |
575 | { | |
576 | /* Leaf procedure. Just restore the return address into the IP. */ | |
577 | write_register (RIP_REGNUM, leaf_return_addr); | |
578 | } | |
579 | ||
580 | /* Now restore any global regs that the current function had saved. */ | |
581 | get_frame_saved_regs (current_fi, &fsr); | |
582 | for (i = G0_REGNUM; i < G14_REGNUM; i++) | |
583 | { | |
584 | if (save_addr = fsr.regs[i]) | |
585 | write_register (i, read_memory_integer (save_addr, 4)); | |
586 | } | |
587 | ||
588 | /* Flush the frame cache, create a frame for the new innermost frame, | |
589 | and make it the current frame. */ | |
590 | ||
591 | flush_cached_frames (); | |
dd3b648e RP |
592 | } |
593 | ||
67ac9759 JK |
594 | /* Given a 960 stop code (fault or trace), return the signal which |
595 | corresponds. */ | |
dd3b648e | 596 | |
67ac9759 JK |
597 | enum target_signal |
598 | i960_fault_to_signal (fault) | |
599 | int fault; | |
dd3b648e | 600 | { |
67ac9759 JK |
601 | switch (fault) |
602 | { | |
603 | case 0: return TARGET_SIGNAL_BUS; /* parallel fault */ | |
604 | case 1: return TARGET_SIGNAL_UNKNOWN; | |
24a11a79 | 605 | case 2: return TARGET_SIGNAL_ILL; /* operation fault */ |
67ac9759 JK |
606 | case 3: return TARGET_SIGNAL_FPE; /* arithmetic fault */ |
607 | case 4: return TARGET_SIGNAL_FPE; /* floating point fault */ | |
24a11a79 | 608 | |
669caa9c SS |
609 | /* constraint fault. This appears not to distinguish between |
610 | a range constraint fault (which should be SIGFPE) and a privileged | |
611 | fault (which should be SIGILL). */ | |
24a11a79 JK |
612 | case 5: return TARGET_SIGNAL_ILL; |
613 | ||
67ac9759 | 614 | case 6: return TARGET_SIGNAL_SEGV; /* virtual memory fault */ |
24a11a79 | 615 | |
669caa9c SS |
616 | /* protection fault. This is for an out-of-range argument to |
617 | "calls". I guess it also could be SIGILL. */ | |
24a11a79 JK |
618 | case 7: return TARGET_SIGNAL_SEGV; |
619 | ||
67ac9759 JK |
620 | case 8: return TARGET_SIGNAL_BUS; /* machine fault */ |
621 | case 9: return TARGET_SIGNAL_BUS; /* structural fault */ | |
24a11a79 | 622 | case 0xa: return TARGET_SIGNAL_ILL; /* type fault */ |
67ac9759 JK |
623 | case 0xb: return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ |
624 | case 0xc: return TARGET_SIGNAL_BUS; /* process fault */ | |
625 | case 0xd: return TARGET_SIGNAL_SEGV; /* descriptor fault */ | |
626 | case 0xe: return TARGET_SIGNAL_BUS; /* event fault */ | |
627 | case 0xf: return TARGET_SIGNAL_UNKNOWN; /* reserved fault */ | |
628 | case 0x10: return TARGET_SIGNAL_TRAP; /* single-step trace */ | |
629 | case 0x11: return TARGET_SIGNAL_TRAP; /* branch trace */ | |
630 | case 0x12: return TARGET_SIGNAL_TRAP; /* call trace */ | |
631 | case 0x13: return TARGET_SIGNAL_TRAP; /* return trace */ | |
632 | case 0x14: return TARGET_SIGNAL_TRAP; /* pre-return trace */ | |
633 | case 0x15: return TARGET_SIGNAL_TRAP; /* supervisor call trace */ | |
634 | case 0x16: return TARGET_SIGNAL_TRAP; /* breakpoint trace */ | |
635 | default: return TARGET_SIGNAL_UNKNOWN; | |
636 | } | |
dd3b648e RP |
637 | } |
638 | ||
18b46e7c SS |
639 | /****************************************/ |
640 | /* MEM format */ | |
641 | /****************************************/ | |
642 | ||
643 | struct tabent { | |
644 | char *name; | |
645 | char numops; | |
646 | }; | |
647 | ||
648 | static int /* returns instruction length: 4 or 8 */ | |
649 | mem( memaddr, word1, word2, noprint ) | |
650 | unsigned long memaddr; | |
651 | unsigned long word1, word2; | |
652 | int noprint; /* If TRUE, return instruction length, but | |
653 | don't output any text. */ | |
654 | { | |
655 | int i, j; | |
656 | int len; | |
657 | int mode; | |
658 | int offset; | |
659 | const char *reg1, *reg2, *reg3; | |
660 | ||
661 | /* This lookup table is too sparse to make it worth typing in, but not | |
662 | * so large as to make a sparse array necessary. We allocate the | |
663 | * table at runtime, initialize all entries to empty, and copy the | |
664 | * real ones in from an initialization table. | |
665 | * | |
666 | * NOTE: In this table, the meaning of 'numops' is: | |
667 | * 1: single operand | |
668 | * 2: 2 operands, load instruction | |
669 | * -2: 2 operands, store instruction | |
670 | */ | |
671 | static struct tabent *mem_tab = NULL; | |
672 | /* Opcodes of 0x8X, 9X, aX, bX, and cX must be in the table. */ | |
673 | #define MEM_MIN 0x80 | |
674 | #define MEM_MAX 0xcf | |
675 | #define MEM_SIZ ((MEM_MAX-MEM_MIN+1) * sizeof(struct tabent)) | |
676 | ||
677 | static struct { int opcode; char *name; char numops; } mem_init[] = { | |
678 | 0x80, "ldob", 2, | |
679 | 0x82, "stob", -2, | |
680 | 0x84, "bx", 1, | |
681 | 0x85, "balx", 2, | |
682 | 0x86, "callx", 1, | |
683 | 0x88, "ldos", 2, | |
684 | 0x8a, "stos", -2, | |
685 | 0x8c, "lda", 2, | |
686 | 0x90, "ld", 2, | |
687 | 0x92, "st", -2, | |
688 | 0x98, "ldl", 2, | |
689 | 0x9a, "stl", -2, | |
690 | 0xa0, "ldt", 2, | |
691 | 0xa2, "stt", -2, | |
692 | 0xb0, "ldq", 2, | |
693 | 0xb2, "stq", -2, | |
694 | 0xc0, "ldib", 2, | |
695 | 0xc2, "stib", -2, | |
696 | 0xc8, "ldis", 2, | |
697 | 0xca, "stis", -2, | |
698 | 0, NULL, 0 | |
699 | }; | |
700 | ||
701 | if ( mem_tab == NULL ){ | |
702 | mem_tab = (struct tabent *) xmalloc( MEM_SIZ ); | |
703 | memset( mem_tab, '\0', MEM_SIZ ); | |
704 | for ( i = 0; mem_init[i].opcode != 0; i++ ){ | |
705 | j = mem_init[i].opcode - MEM_MIN; | |
706 | mem_tab[j].name = mem_init[i].name; | |
707 | mem_tab[j].numops = mem_init[i].numops; | |
708 | } | |
709 | } | |
710 | ||
711 | i = ((word1 >> 24) & 0xff) - MEM_MIN; | |
712 | mode = (word1 >> 10) & 0xf; | |
713 | ||
714 | if ( (mem_tab[i].name != NULL) /* Valid instruction */ | |
715 | && ((mode == 5) || (mode >=12)) ){ /* With 32-bit displacement */ | |
716 | len = 8; | |
717 | } else { | |
718 | len = 4; | |
719 | } | |
720 | ||
721 | if ( noprint ){ | |
722 | return len; | |
723 | } | |
724 | abort (); | |
725 | } | |
726 | ||
727 | /* Read the i960 instruction at 'memaddr' and return the address of | |
728 | the next instruction after that, or 0 if 'memaddr' is not the | |
729 | address of a valid instruction. The first word of the instruction | |
730 | is stored at 'pword1', and the second word, if any, is stored at | |
731 | 'pword2'. */ | |
732 | ||
733 | static CORE_ADDR | |
734 | next_insn (memaddr, pword1, pword2) | |
ff7116e2 | 735 | unsigned int *pword1, *pword2; |
18b46e7c SS |
736 | CORE_ADDR memaddr; |
737 | { | |
738 | int len; | |
739 | char buf[8]; | |
740 | ||
741 | /* Read the two (potential) words of the instruction at once, | |
742 | to eliminate the overhead of two calls to read_memory (). | |
743 | FIXME: Loses if the first one is readable but the second is not | |
744 | (e.g. last word of the segment). */ | |
745 | ||
746 | read_memory (memaddr, buf, 8); | |
747 | *pword1 = extract_unsigned_integer (buf, 4); | |
748 | *pword2 = extract_unsigned_integer (buf + 4, 4); | |
749 | ||
750 | /* Divide instruction set into classes based on high 4 bits of opcode*/ | |
751 | ||
752 | switch ((*pword1 >> 28) & 0xf) | |
753 | { | |
754 | case 0x0: | |
755 | case 0x1: /* ctrl */ | |
756 | ||
757 | case 0x2: | |
758 | case 0x3: /* cobr */ | |
759 | ||
760 | case 0x5: | |
761 | case 0x6: | |
762 | case 0x7: /* reg */ | |
763 | len = 4; | |
764 | break; | |
765 | ||
766 | case 0x8: | |
767 | case 0x9: | |
768 | case 0xa: | |
769 | case 0xb: | |
770 | case 0xc: | |
771 | len = mem (memaddr, *pword1, *pword2, 1); | |
772 | break; | |
773 | ||
774 | default: /* invalid instruction */ | |
775 | len = 0; | |
776 | break; | |
777 | } | |
778 | ||
779 | if (len) | |
780 | return memaddr + len; | |
781 | else | |
782 | return 0; | |
783 | } | |
dd3b648e | 784 | |
2e665cd3 DP |
785 | /* 'start_frame' is a variable in the MON960 runtime startup routine |
786 | that contains the frame pointer of the 'start' routine (the routine | |
787 | that calls 'main'). By reading its contents out of remote memory, | |
788 | we can tell where the frame chain ends: backtraces should halt before | |
789 | they display this frame. */ | |
790 | ||
791 | int | |
792 | mon960_frame_chain_valid (chain, curframe) | |
b6960094 | 793 | CORE_ADDR chain; |
2e665cd3 DP |
794 | struct frame_info *curframe; |
795 | { | |
796 | struct symbol *sym; | |
797 | struct minimal_symbol *msymbol; | |
798 | ||
799 | /* crtmon960.o is an assembler module that is assumed to be linked | |
800 | * first in an i80960 executable. It contains the true entry point; | |
801 | * it performs startup up initialization and then calls 'main'. | |
802 | * | |
803 | * 'sf' is the name of a variable in crtmon960.o that is set | |
804 | * during startup to the address of the first frame. | |
805 | * | |
806 | * 'a' is the address of that variable in 80960 memory. | |
807 | */ | |
808 | static char sf[] = "start_frame"; | |
809 | CORE_ADDR a; | |
810 | ||
811 | ||
812 | chain &= ~0x3f; /* Zero low 6 bits because previous frame pointers | |
813 | contain return status info in them. */ | |
814 | if ( chain == 0 ){ | |
815 | return 0; | |
816 | } | |
817 | ||
818 | sym = lookup_symbol(sf, 0, VAR_NAMESPACE, (int *)NULL, | |
819 | (struct symtab **)NULL); | |
820 | if ( sym != 0 ){ | |
821 | a = SYMBOL_VALUE (sym); | |
822 | } else { | |
823 | msymbol = lookup_minimal_symbol (sf, NULL, NULL); | |
824 | if (msymbol == NULL) | |
825 | return 0; | |
826 | a = SYMBOL_VALUE_ADDRESS (msymbol); | |
827 | } | |
828 | ||
829 | return ( chain != read_memory_integer(a,4) ); | |
830 | } | |
831 | ||
976bb0be | 832 | void |
dd3b648e RP |
833 | _initialize_i960_tdep () |
834 | { | |
835 | check_host (); | |
18b46e7c SS |
836 | |
837 | tm_print_insn = print_insn_i960; | |
dd3b648e | 838 | } |